Remus Munteanu
mbed lib with startup delay fixed for Nucleo401RE
Fork of
mbed-src
by 
mbed official
Revision 155:8435094ec241, committed 2014-04-08
- Comitter:
- mbed_official
- Date:
- Tue Apr 08 09:15:06 2014 +0100
- Parent:
- 154:be4113396fa5
- Child:
- 156:38b9eb24e1d1
- Commit message:
- Synchronized with git revision d616c415fc62f490b915ff0ff39c8d24b2917c0f
Full URL: https://github.com/mbedmicro/mbed/commit/d616c415fc62f490b915ff0ff39c8d24b2917c0f/
[STM32F3XX] Initial port
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/TOOLCHAIN_ARM_MICRO/startup_stm32f302x8.s Tue Apr 08 09:15:06 2014 +0100 @@ -0,0 +1,342 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f302x8.s +; STM32F302x8 Devices vector table for MDK ARM_MICRO toolchain +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2014, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20004000 ; Top of RAM + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD USB_HP_CAN1_TX_IRQHandler ; USB Device High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Device Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD 0 ; Reserved + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD COMP2_IRQHandler ; COMP2 + DCD COMP4_6_IRQHandler ; COMP4 and COMP6 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2C3_EV_IRQHandler ; I2C3 Event + DCD I2C3_ER_IRQHandler ; I2C3 Error + DCD USB_HP_IRQHandler ; USB High Priority remap + DCD USB_LP_IRQHandler ; USB Low Priority remap + DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_TS_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT COMP2_IRQHandler [WEAK] + EXPORT COMP4_6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT USB_HP_IRQHandler [WEAK] + EXPORT USB_LP_IRQHandler [WEAK] + EXPORT USBWakeUp_RMP_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_TS_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +USBWakeUp_IRQHandler +SPI3_IRQHandler +TIM6_DAC_IRQHandler +COMP2_IRQHandler +COMP4_6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +USB_HP_IRQHandler +USB_LP_IRQHandler +USBWakeUp_RMP_IRQHandler +FPU_IRQHandler + + B . + + ENDP + + ALIGN + END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/TOOLCHAIN_ARM_MICRO/stm32f302x8.sct Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F302R8: 64KB FLASH + 16KB SRAM
+LR_IROM1 0x08000000 0x10000 { ; load region size_region
+
+ ER_IROM1 0x08000000 0x10000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; 98 vectors (16 core + 82 peripheral) * 4 bytes = 392 bytes to reserve (0x188)
+ RW_IRAM1 (0x20000000+0x188) (0x4000-0x188) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/TOOLCHAIN_ARM_MICRO/sys.cpp Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/TOOLCHAIN_ARM_STD/startup_stm32f302x8.s Tue Apr 08 09:15:06 2014 +0100 @@ -0,0 +1,315 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f302x8.s +; STM32F302x8 Devices vector table for MDK ARM_STD toolchain +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2014, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +__initial_sp EQU 0x20004000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD USB_HP_CAN1_TX_IRQHandler ; USB Device High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Device Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD 0 ; Reserved + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD COMP2_IRQHandler ; COMP2 + DCD COMP4_6_IRQHandler ; COMP4 and COMP6 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2C3_EV_IRQHandler ; I2C3 Event + DCD I2C3_ER_IRQHandler ; I2C3 Error + DCD USB_HP_IRQHandler ; USB High Priority remap + DCD USB_LP_IRQHandler ; USB Low Priority remap + DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_TS_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT COMP2_IRQHandler [WEAK] + EXPORT COMP4_6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT USB_HP_IRQHandler [WEAK] + EXPORT USB_LP_IRQHandler [WEAK] + EXPORT USBWakeUp_RMP_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_TS_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +USBWakeUp_IRQHandler +SPI3_IRQHandler +TIM6_DAC_IRQHandler +COMP2_IRQHandler +COMP4_6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +USB_HP_IRQHandler +USB_LP_IRQHandler +USBWakeUp_RMP_IRQHandler +FPU_IRQHandler + + B . + + ENDP + + ALIGN + END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/TOOLCHAIN_ARM_STD/stm32f302x8.sct Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F302R8: 64KB FLASH + 16KB SRAM
+LR_IROM1 0x08000000 0x10000 { ; load region size_region
+
+ ER_IROM1 0x08000000 0x10000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; 98 vectors (16 core + 82 peripheral) * 4 bytes = 392 bytes to reserve (0x188)
+ RW_IRAM1 (0x20000000+0x188) (0x4000-0x188) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/TOOLCHAIN_ARM_STD/sys.cpp Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/TOOLCHAIN_GCC_ARM/STM32F3XX.ld Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,157 @@
+/* Linker script for STM32F3xx */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K
+ CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 8K
+ RAM (rwx) : ORIGIN = 0x20000188, LENGTH = 40k - 0x188
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+ /* KEEP(.ioview) */
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/TOOLCHAIN_GCC_ARM/startup_STM32F30x.s Tue Apr 08 09:15:06 2014 +0100 @@ -0,0 +1,465 @@ +/** + ****************************************************************************** + * @file startup_stm32f30x.s + * @author MCD Application Team + * @version V1.0.0 + * @date 04-Spetember-2012 + * @brief STM32F4xx Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system and the external SRAM mounted on + * STM3230C-EVAL board to be used as data memory (optional, + * to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2> + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_TS_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USBWakeUp_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC3_IRQHandler + .word 0 + .word 0 + .word 0 + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word ADC4_IRQHandler + .word 0 + .word 0 + .word COMP1_2_3_IRQHandler + .word COMP4_5_6_IRQHandler + .word COMP7_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word USBWakeUp_RMP_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word FPU_IRQHandler + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_STAMP_IRQHandler + .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_TS_IRQHandler + .thumb_set EXTI2_TS_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak ADC4_IRQHandler + .thumb_set ADC4_IRQHandler,Default_Handler + + .weak COMP1_2_3_IRQHandler + .thumb_set COMP1_2_3_IRQHandler,Default_Handler + + .weak COMP4_5_6_IRQHandler + .thumb_set COMP4_5_6_IRQHandler,Default_Handler + + .weak COMP7_IRQHandler + .thumb_set COMP7_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak USBWakeUp_RMP_IRQHandler + .thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/cmsis.h Tue Apr 08 09:15:06 2014 +0100 @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f30x.h" +#include "cmsis_nvic.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/cmsis_nvic.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/cmsis_nvic.h Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// STM32F302R8
+// CORE: 16 vectors (= 64 bytes from 0x00 to 0x3F)
+// MCU Peripherals: 82 vectors (= 328 bytes from 0x40 to ...)
+// Total: 392 bytes to be reserved in RAM (see scatter file)
+#define NVIC_NUM_VECTORS (16 + 82)
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x.h Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,7705 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral registers definitions, bits
+ * definitions and memory mapping for STM32F30x devices.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The device used in the target application
+ * - To use or not the peripherals drivers in application code(i.e.
+ * code will be based on direct access to peripherals registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_STDPERIPH_DRIVER"
+ * - To change few application-specific parameters such as the HSE
+ * crystal frequency
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral registers declarations and bits definition
+ * - Macros to access peripheral registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f30x
+ * @{
+ */
+
+#ifndef __STM32F30x_H
+#define __STM32F30x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+
+#if !defined (STM32F303xC) && !defined (STM32F334x8) && !defined (STM32F303x8) && !defined (STM32F301x8) && !defined (STM32F302x8)
+#define STM32F303xC /*!< STM32F303CB, STM32F303CC, STM32F303RB, STM32F303RC, STM32F303VB and STM32F303VC Devices */
+ /* #define STM32F334x8 */ /*!< STM32F334C4, STM32F334C6, STM32F334C8, STM32F334R4, STM32F334R6 and STM32F334R8 Devices */
+ /* #define STM32F302x8 */ /*!< STM32F302K4, STM32F302K6, STM32F302K8, STM32F302C4, STM32F302C6, STM32F302C8,
+ STM32F302R4, STM32F302R6 and STM32F302R8 Devices */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+
+/* Old STM32F30X definition, maintained for legacy purpose */
+#if defined(STM32F30X)
+ #define STM32F303xC
+#endif /* STM32F30X */
+
+#if !defined (STM32F303xC) && !defined (STM32F334x8) && !defined (STM32F302x8)
+ #error "Please select first the target STM32F30X device used in your application (in stm32f30x.h file)"
+#endif
+
+#if !defined (USE_STDPERIPH_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+#define USE_STDPERIPH_DRIVER
+#endif /* USE_STDPERIPH_DRIVER */
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+ used in your application
+
+ Tip: To avoid modifying this file each time you need to use different HSE, you
+ can define the HSE value in your toolchain compiler preprocessor.
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External xtal in Hz */
+#endif /* HSE_VALUE */
+
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+ Timeout value
+ */
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSE start up */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
+ Timeout value
+ */
+#if !defined (HSI_STARTUP_TIMEOUT)
+ #define HSI_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSI start up */
+#endif /* HSI_STARTUP_TIMEOUT */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)8000000)
+#endif /* HSI_VALUE */ /*!< Value of the Internal High Speed oscillator in Hz.
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE ((uint32_t)40000)
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+
+/**
+ * @brief STM32F30x Standard Peripherals Library version number V1.1.0
+ */
+#define __STM32F30X_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
+#define __STM32F30X_STDPERIPH_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
+#define __STM32F30X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F30X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F30X_STDPERIPH_VERSION ( (__STM32F30X_STDPERIPH_VERSION_MAIN << 24)\
+ |(__STM32F30X_STDPERIPH_VERSION_SUB1 << 16)\
+ |(__STM32F30X_STDPERIPH_VERSION_SUB2 << 8)\
+ |(__STM32F30X_STDPERIPH_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< STM32F30X provide an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F30X uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< STM32F30X provide an FPU */
+
+
+/**
+ * @brief STM32F30X Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum IRQn
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+#ifdef STM32F303xC
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI lines 17, 19 & 20 */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_TS_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
+ ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
+ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
+ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */
+ TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
+ TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
+ TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
+ ADC4_IRQn = 61, /*!< ADC4 global Interrupt */
+ COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt */
+ COMP4_5_6_IRQn = 65, /*!< COMP5, COMP6 and COMP4 global Interrupt */
+ COMP7_IRQn = 66, /*!< COMP7 global Interrupt */
+ USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt remap */
+ USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt remap */
+ USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */
+ FPU_IRQn = 81 /*!< Floating point Interrupt */
+#endif /* STM32F303xC */
+#ifdef STM32F334x8
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI lines 17, 19 & 20 */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_TS_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
+ ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupts */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupts */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 underrun error interrupts */
+ TIM7_DAC2_IRQn = 55, /*!< TIM7 global and DAC2 underrun error Interrupt */
+ COMP2_IRQn = 64, /*!< COMP2 global Interrupt */
+ COMP4_6_IRQn = 65, /*!< COMP6 and COMP4 global Interrupt */
+ HRTIM1_Master_IRQn = 67, /*!< HRTIM Master Timer global Interrupts */
+ HRTIM1_TIMA_IRQn = 68, /*!< HRTIM Timer A global Interrupt */
+ HRTIM1_TIMB_IRQn = 69, /*!< HRTIM Timer B global Interrupt */
+ HRTIM1_TIMC_IRQn = 70, /*!< HRTIM Timer C global Interrupt */
+ HRTIM1_TIMD_IRQn = 71, /*!< HRTIM Timer D global Interrupt */
+ HRTIM1_TIME_IRQn = 72, /*!< HRTIM Timer E global Interrupt */
+ HRTIM1_FLT_IRQn = 73, /*!< HRTIM Fault global Interrupt */
+ FPU_IRQn = 81 /*!< Floating point Interrupt */
+#endif /* STM32F334x8 */
+#ifdef STM32F302x8
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI lines 20 */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_TS_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
+ ADC1_IRQn = 18, /*!< ADC1 Interrupts */
+ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
+ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ COMP2_IRQn = 64, /*!< COMP2 global Interrupt */
+ COMP4_6_IRQn = 65, /*!< COMP5, COMP6 and COMP4 global Interrupt */
+ COMP7_IRQn = 66, /*!< COMP7 global Interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 Event Interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 Error Interrupt */
+ USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt remap */
+ USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt remap */
+ USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */
+ FPU_IRQn = 81 /*!< Floating point Interrupt */
+#endif /* STM32F302x8 */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f30x.h" /* STM32F30x System Header */
+#include <stdint.h>
+
+/** @addtogroup Exported_types
+ * @{
+ */
+/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
+typedef int32_t s32;
+typedef int16_t s16;
+typedef int8_t s8;
+
+typedef const int32_t sc32; /*!< Read Only */
+typedef const int16_t sc16; /*!< Read Only */
+typedef const int8_t sc8; /*!< Read Only */
+
+typedef __IO int32_t vs32;
+typedef __IO int16_t vs16;
+typedef __IO int8_t vs8;
+
+typedef __I int32_t vsc32; /*!< Read Only */
+typedef __I int16_t vsc16; /*!< Read Only */
+typedef __I int8_t vsc8; /*!< Read Only */
+
+typedef uint32_t u32;
+typedef uint16_t u16;
+typedef uint8_t u8;
+
+typedef const uint32_t uc32; /*!< Read Only */
+typedef const uint16_t uc16; /*!< Read Only */
+typedef const uint8_t uc8; /*!< Read Only */
+
+typedef __IO uint32_t vu32;
+typedef __IO uint16_t vu16;
+typedef __IO uint8_t vu8;
+
+typedef __I uint32_t vuc32; /*!< Read Only */
+typedef __I uint16_t vuc16; /*!< Read Only */
+typedef __I uint8_t vuc8; /*!< Read Only */
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
+ uint32_t RESERVED0; /*!< Reserved, 0x010 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
+ uint32_t RESERVED1; /*!< Reserved, 0x01C */
+ __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */
+ __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */
+ __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */
+ uint32_t RESERVED2; /*!< Reserved, 0x02C */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
+ __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
+ uint32_t RESERVED3; /*!< Reserved, 0x044 */
+ uint32_t RESERVED4; /*!< Reserved, 0x048 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
+ uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
+ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
+ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
+ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
+ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
+ uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
+ uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
+ __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
+ __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
+ uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
+ uint32_t RESERVED9; /*!< Reserved, 0x0AC */
+ __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */
+
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
+ uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ modes, Address offset: ADC1/3 base address + 0x30A */
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+
+/**
+ * @brief Analog Comparators
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
+ __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
+ __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
+ __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
+ __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
+ __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
+}EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t AR; /*!< FLASH address register, Address offset: 0x14 */
+ uint32_t RESERVED; /*!< Reserved, 0x18 */
+ __IO uint32_t OBR; /*!< FLASH Option byte register, Address offset: 0x1C */
+ __IO uint32_t WRPR; /*!< FLASH Write register, Address offset: 0x20 */
+
+} FLASH_TypeDef;
+
+/**
+ * @brief Option Bytes Registers
+ */
+typedef struct
+{
+ __IO uint16_t RDP; /*!<FLASH option byte Read protection, Address offset: 0x00 */
+ __IO uint16_t USER; /*!<FLASH option byte user options, Address offset: 0x02 */
+ uint16_t RESERVED0; /*!< Reserved, 0x04 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint16_t WRP0; /*!<FLASH option byte write protection 0, Address offset: 0x08 */
+ __IO uint16_t WRP1; /*!<FLASH option byte write protection 1, Address offset: 0x0C */
+ __IO uint16_t WRP2; /*!<FLASH option byte write protection 2, Address offset: 0x10 */
+ __IO uint16_t WRP3; /*!<FLASH option byte write protection 3, Address offset: 0x12 */
+} OB_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint16_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ uint16_t RESERVED0; /*!< Reserved, 0x06 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint16_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ uint16_t RESERVED1; /*!< Reserved, 0x12 */
+ __IO uint16_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ uint16_t RESERVED2; /*!< Reserved, 0x16 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
+ __IO uint16_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+ uint16_t RESERVED3; /*!< Reserved, 0x2A */
+}GPIO_TypeDef;
+
+/**
+ * @brief High resolution Timer (HRTIM)
+ */
+/* HRTIM master definition */
+typedef struct
+{
+ __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */
+ __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */
+ __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */
+ __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */
+ __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */
+ __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */
+ __IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */
+ __IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */
+ uint32_t RESERVED0; /*!< Reserved, 0x20 */
+ __IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */
+ __IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */
+ __IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */
+}HRTIM_Master_TypeDef;
+
+/* HRTIM slave definition */
+typedef struct
+{
+ __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */
+ __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */
+ __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */
+ __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */
+ __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */
+ __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */
+ __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */
+ __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */
+ __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */
+ __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */
+ __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */
+ __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */
+ __IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */
+ __IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */
+ __IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */
+ __IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */
+ __IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */
+ __IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */
+ __IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */
+ __IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */
+ __IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */
+ __IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */
+ __IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */
+ __IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */
+ __IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */
+ __IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */
+ uint32_t RESERVED0[5];/*!< Reserved, */
+}HRTIM_Timerx_TypeDef;
+
+/* HRTIM common register definition */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */
+ __IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */
+ __IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */
+ __IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */
+ __IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */
+ __IO uint32_t DISR; /*!< HRTIM Output disable register, Address offset: 0x18 */
+ __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */
+ __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */
+ __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */
+ __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */
+ __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */
+ __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */
+ __IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */
+ __IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */
+ __IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */
+ __IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */
+ __IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */
+ __IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */
+ __IO uint32_t DLLCR; /*!< HRTIM DLL control register, Address offset: 0x4C */
+ __IO uint32_t FLTINxR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */
+ __IO uint32_t FLTINxR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */
+ __IO uint32_t BDMUPDR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */
+ __IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */
+ __IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */
+ __IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */
+ __IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */
+ __IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */
+ __IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */
+}HRTIM_Common_TypeDef;
+
+/* HRTIM register definition */
+typedef struct {
+ HRTIM_Master_TypeDef HRTIM_MASTER;
+ uint32_t RESERVED0[20];
+ HRTIM_Timerx_TypeDef HRTIM_TIMERx[5];
+ uint32_t RESERVED1[32];
+ HRTIM_Common_TypeDef HRTIM_COMMON;
+}HRTIM_TypeDef;
+
+/**
+ * @brief Operational Amplifier (OPAMP)
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */
+} OPAMP_TypeDef;
+
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ __IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
+ __IO uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t RESERVED1; /*!< Reserved, 0x20 */
+ __IO uint32_t RESERVED2; /*!< Reserved, 0x24 */
+ __IO uint32_t RESERVED4; /*!< Reserved, 0x28 */
+ __IO uint32_t RESERVED5; /*!< Reserved, 0x2C */
+ __IO uint32_t RESERVED6; /*!< Reserved, 0x30 */
+ __IO uint32_t RESERVED7; /*!< Reserved, 0x34 */
+ __IO uint32_t RESERVED8; /*!< Reserved, 0x38 */
+ __IO uint32_t RESERVED9; /*!< Reserved, 0x3C */
+ __IO uint32_t RESERVED10; /*!< Reserved, 0x40 */
+ __IO uint32_t RESERVED11; /*!< Reserved, 0x44 */
+ __IO uint32_t RESERVED12; /*!< Reserved, 0x48 */
+ __IO uint32_t RESERVED13; /*!< Reserved, 0x4C */
+ __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x50 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+}I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
+ __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t RESERVED0; /*!< Reserved, 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+} RTC_TypeDef;
+
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint16_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
+ uint16_t RESERVED0; /*!< Reserved, 0x02 */
+ __IO uint16_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint16_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ uint16_t RESERVED2; /*!< Reserved, 0x0A */
+ __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
+ uint16_t RESERVED3; /*!< Reserved, 0x0E */
+ __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ uint16_t RESERVED4; /*!< Reserved, 0x12 */
+ __IO uint16_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
+ uint16_t RESERVED5; /*!< Reserved, 0x16 */
+ __IO uint16_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
+ uint16_t RESERVED6; /*!< Reserved, 0x1A */
+ __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ uint16_t RESERVED7; /*!< Reserved, 0x1E */
+ __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+ uint16_t RESERVED8; /*!< Reserved, 0x22 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ uint16_t RESERVED0; /*!< Reserved, 0x02 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ uint16_t RESERVED9; /*!< Reserved, 0x2A */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ uint16_t RESERVED10; /*!< Reserved, 0x32 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ uint16_t RESERVED12; /*!< Reserved, 0x4A */
+ __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ uint16_t RESERVED13; /*!< Reserved, 0x4E */
+ __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */
+ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
+ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
+ __IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */
+} TIM_TypeDef;
+
+
+/**
+ * @brief Touch Sensing Controller (TSC)
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
+ __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
+ __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
+ __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
+ __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
+ __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
+ __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
+ __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
+} TSC_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ uint16_t RESERVED1; /*!< Reserved, 0x0E */
+ __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ uint16_t RESERVED2; /*!< Reserved, 0x12 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ uint16_t RESERVED3; /*!< Reserved, 0x1A */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ uint16_t RESERVED4; /*!< Reserved, 0x26 */
+ __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+ uint16_t RESERVED5; /*!< Reserved, 0x2A */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
+#define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400)
+#define RTC_BASE (APB1PERIPH_BASE + 0x00002800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x00003400)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x00004000)
+#define USART2_BASE (APB1PERIPH_BASE + 0x00004400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x00004800)
+#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00)
+#define UART5_BASE (APB1PERIPH_BASE + 0x00005000)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400)
+#define PWR_BASE (APB1PERIPH_BASE + 0x00007000)
+#define DAC1_BASE (APB1PERIPH_BASE + 0x00007400)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x00007800)
+#define DAC2_BASE (APB1PERIPH_BASE + 0x00009800)
+#define DAC_BASE DAC1_BASE
+
+/*!< APB2 peripherals */
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000)
+#define COMP_BASE (APB2PERIPH_BASE + 0x0000001C)
+#define COMP1_BASE (APB2PERIPH_BASE + 0x0000001C)
+#define COMP2_BASE (APB2PERIPH_BASE + 0x00000020)
+#define COMP3_BASE (APB2PERIPH_BASE + 0x00000024)
+#define COMP4_BASE (APB2PERIPH_BASE + 0x00000028)
+#define COMP5_BASE (APB2PERIPH_BASE + 0x0000002C)
+#define COMP6_BASE (APB2PERIPH_BASE + 0x00000030)
+#define COMP7_BASE (APB2PERIPH_BASE + 0x00000034)
+#define OPAMP_BASE (APB2PERIPH_BASE + 0x00000038)
+#define OPAMP1_BASE (APB2PERIPH_BASE + 0x00000038)
+#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003C)
+#define OPAMP3_BASE (APB2PERIPH_BASE + 0x00000040)
+#define OPAMP4_BASE (APB2PERIPH_BASE + 0x00000044)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x00003400)
+#define USART1_BASE (APB2PERIPH_BASE + 0x00003800)
+#define TIM15_BASE (APB2PERIPH_BASE + 0x00004000)
+#define TIM16_BASE (APB2PERIPH_BASE + 0x00004400)
+#define TIM17_BASE (APB2PERIPH_BASE + 0x00004800)
+#define HRTIM1_BASE (APB2PERIPH_BASE + 0x00007400)
+#define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080)
+#define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100)
+#define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180)
+#define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200)
+#define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280)
+#define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380)
+
+/*!< AHB1 peripherals */
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000)
+#define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008)
+#define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001C)
+#define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030)
+#define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044)
+#define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058)
+#define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006C)
+#define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400)
+#define DMA2_Channel1_BASE (AHB1PERIPH_BASE + 0x00000408)
+#define DMA2_Channel2_BASE (AHB1PERIPH_BASE + 0x0000041C)
+#define DMA2_Channel3_BASE (AHB1PERIPH_BASE + 0x00000430)
+#define DMA2_Channel4_BASE (AHB1PERIPH_BASE + 0x00000444)
+#define DMA2_Channel5_BASE (AHB1PERIPH_BASE + 0x00000458)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x00001000)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000) /*!< Flash registers base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+#define CRC_BASE (AHB1PERIPH_BASE + 0x00003000)
+#define TSC_BASE (AHB1PERIPH_BASE + 0x00004000)
+
+/*!< AHB2 peripherals */
+#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000)
+#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400)
+#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800)
+#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00)
+#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000)
+#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400)
+
+/*!< AHB3 peripherals */
+#define ADC1_BASE (AHB3PERIPH_BASE + 0x0000)
+#define ADC2_BASE (AHB3PERIPH_BASE + 0x0100)
+#define ADC1_2_BASE (AHB3PERIPH_BASE + 0x0300)
+#define ADC3_BASE (AHB3PERIPH_BASE + 0x0400)
+#define ADC4_BASE (AHB3PERIPH_BASE + 0x0500)
+#define ADC3_4_BASE (AHB3PERIPH_BASE + 0x0700)
+
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
+#define DAC2 ((DAC_TypeDef *) DAC2_BASE)
+#define DAC DAC1
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP ((COMP_TypeDef *) COMP_BASE)
+#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
+#define COMP3 ((COMP_TypeDef *) COMP3_BASE)
+#define COMP4 ((COMP_TypeDef *) COMP4_BASE)
+#define COMP5 ((COMP_TypeDef *) COMP5_BASE)
+#define COMP6 ((COMP_TypeDef *) COMP6_BASE)
+#define COMP7 ((COMP_TypeDef *) COMP7_BASE)
+#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
+#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
+#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
+#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)
+#define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
+#define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)
+#define HRTIM1_TIMA ((HRTIM_TIM_TypeDef *) HRTIM1_TIMA_BASE)
+#define HRTIM1_TIMB ((HRTIM_TIM_TypeDef *) HRTIM1_TIMB_BASE)
+#define HRTIM1_TIMC ((HRTIM_TIM_TypeDef *) HRTIM1_TIMC_BASE)
+#define HRTIM1_TIMD ((HRTIM_TIM_TypeDef *) HRTIM1_TIMD_BASE)
+#define HRTIM1_TIME ((HRTIM_TIM_TypeDef *) HRTIM1_TIME_BASE)
+#define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define TSC ((TSC_TypeDef *) TSC_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define ADC4 ((ADC_TypeDef *) ADC4_BASE)
+#define ADC1_2 ((ADC_Common_TypeDef *) ADC1_2_BASE)
+#define ADC3_4 ((ADC_Common_TypeDef *) ADC3_4_BASE)
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+/******************************************************************************/
+/* */
+/* High Resolution Timer (HRTIM) */
+/* */
+/******************************************************************************/
+/******************** Master Timer control register ***************************/
+#define HRTIM_MCR_CK_PSC ((uint32_t)0x00000007) /*!< Prescaler mask */
+#define HRTIM_MCR_CK_PSC_0 ((uint32_t)0x00000001) /*!< Prescaler bit 0 */
+#define HRTIM_MCR_CK_PSC_1 ((uint32_t)0x00000002) /*!< Prescaler bit 1 */
+#define HRTIM_MCR_CK_PSC_2 ((uint32_t)0x00000004) /*!< Prescaler bit 2 */
+
+#define HRTIM_MCR_CONT ((uint32_t)0x00000008) /*!< Continuous mode */
+#define HRTIM_MCR_RETRIG ((uint32_t)0x00000010) /*!< Rettrigreable mode */
+#define HRTIM_MCR_HALF ((uint32_t)0x00000020) /*!< Half mode */
+
+#define HRTIM_MCR_SYNC_IN ((uint32_t)0x00000300) /*!< Synchronization input master */
+#define HRTIM_MCR_SYNC_IN_0 ((uint32_t)0x00000100) /*!< Synchronization input bit 0 */
+#define HRTIM_MCR_SYNC_IN_1 ((uint32_t)0x00000200) /*!< Synchronization input bit 1 */
+#define HRTIM_MCR_SYNCRSTM ((uint32_t)0x00000400) /*!< Synchronization reset master */
+#define HRTIM_MCR_SYNCSTRTM ((uint32_t)0x00000800) /*!< Synchronization start master */
+#define HRTIM_MCR_SYNC_OUT ((uint32_t)0x00003000) /*!< Synchronization output master */
+#define HRTIM_MCR_SYNC_OUT_0 ((uint32_t)0x00001000) /*!< Synchronization output bit 0 */
+#define HRTIM_MCR_SYNC_OUT_1 ((uint32_t)0x00002000) /*!< Synchronization output bit 1 */
+#define HRTIM_MCR_SYNC_SRC ((uint32_t)0x0000C000) /*!< Synchronization source */
+#define HRTIM_MCR_SYNC_SRC_0 ((uint32_t)0x00004000) /*!< Synchronization source bit 0 */
+#define HRTIM_MCR_SYNC_SRC_1 ((uint32_t)0x00008000) /*!< Synchronization source bit 1 */
+
+#define HRTIM_MCR_MCEN ((uint32_t)0x00010000) /*!< Master counter enable */
+#define HRTIM_MCR_TACEN ((uint32_t)0x00020000) /*!< Timer A counter enable */
+#define HRTIM_MCR_TBCEN ((uint32_t)0x00040000) /*!< Timer B counter enable */
+#define HRTIM_MCR_TCCEN ((uint32_t)0x00080000) /*!< Timer C counter enable */
+#define HRTIM_MCR_TDCEN ((uint32_t)0x00100000) /*!< Timer D counter enable */
+#define HRTIM_MCR_TECEN ((uint32_t)0x00200000) /*!< Timer E counter enable */
+
+#define HRTIM_MCR_DACSYNC ((uint32_t)0x06000000) /*!< DAC synchronization mask */
+#define HRTIM_MCR_DACSYNC_0 ((uint32_t)0x02000000) /*!< DAC synchronization bit 0 */
+#define HRTIM_MCR_DACSYNC_1 ((uint32_t)0x04000000) /*!< DAC synchronization bit 1 */
+
+#define HRTIM_MCR_PREEN ((uint32_t)0x08000000) /*!< Master preload enable */
+#define HRTIM_MCR_MREPU ((uint32_t)0x20000000) /*!< Master repetition update */
+
+#define HRTIM_MCR_BRSTDMA ((uint32_t)0xC0000000) /*!< Burst DMA update */
+#define HRTIM_MCR_BRSTDMA_0 ((uint32_t)0x40000000) /*!< Burst DMA update bit 0*/
+#define HRTIM_MCR_BRSTDMA_1 ((uint32_t)0x80000000) /*!< Burst DMA update bit 1 */
+
+/******************** Master Timer Interrupt status register ******************/
+#define HRTIM_MISR_MCMP1 ((uint32_t)0x00000001) /*!< Master compare 1 interrupt flag */
+#define HRTIM_MISR_MCMP2 ((uint32_t)0x00000002) /*!< Master compare 2 interrupt flag */
+#define HRTIM_MISR_MCMP3 ((uint32_t)0x00000004) /*!< Master compare 3 interrupt flag */
+#define HRTIM_MISR_MCMP4 ((uint32_t)0x00000008) /*!< Master compare 4 interrupt flag */
+#define HRTIM_MISR_MREP ((uint32_t)0x00000010) /*!< Master Repetition interrupt flag */
+#define HRTIM_MISR_SYNC ((uint32_t)0x00000020) /*!< Synchronization input interrupt flag */
+#define HRTIM_MISR_MUPD ((uint32_t)0x00000040) /*!< Master update interrupt flag */
+
+/******************** Master Timer Interrupt clear register *******************/
+#define HRTIM_MICR_MCMP1 ((uint32_t)0x00000001) /*!< Master compare 1 interrupt flag clear */
+#define HRTIM_MICR_MCMP2 ((uint32_t)0x00000002) /*!< Master compare 2 interrupt flag clear */
+#define HRTIM_MICR_MCMP3 ((uint32_t)0x00000004) /*!< Master compare 3 interrupt flag clear */
+#define HRTIM_MICR_MCMP4 ((uint32_t)0x00000008) /*!< Master compare 4 interrupt flag clear */
+#define HRTIM_MICR_MREP ((uint32_t)0x00000010) /*!< Master Repetition interrupt flag clear */
+#define HRTIM_MICR_SYNC ((uint32_t)0x00000020) /*!< Synchronization input interrupt flag clear */
+#define HRTIM_MICR_MUPD ((uint32_t)0x00000040) /*!< Master update interrupt flag clear */
+
+/******************** Master Timer DMA/Interrupt enable register **************/
+#define HRTIM_MDIER_MCMP1IE ((uint32_t)0x00000001) /*!< Master compare 1 interrupt enable */
+#define HRTIM_MDIER_MCMP2IE ((uint32_t)0x00000002) /*!< Master compare 2 interrupt enable */
+#define HRTIM_MDIER_MCMP3IE ((uint32_t)0x00000004) /*!< Master compare 3 interrupt enable */
+#define HRTIM_MDIER_MCMP4IE ((uint32_t)0x00000008) /*!< Master compare 4 interrupt enable */
+#define HRTIM_MDIER_MREPIE ((uint32_t)0x00000010) /*!< Master Repetition interrupt enable */
+#define HRTIM_MDIER_SYNCIE ((uint32_t)0x00000020) /*!< Synchronization input interrupt enable */
+#define HRTIM_MDIER_MUPDIE ((uint32_t)0x00000040) /*!< Master update interrupt enable */
+
+#define HRTIM_MDIER_MCMP1DE ((uint32_t)0x00010000) /*!< Master compare 1 DMA enable */
+#define HRTIM_MDIER_MCMP2DE ((uint32_t)0x00020000) /*!< Master compare 2 DMA enable */
+#define HRTIM_MDIER_MCMP3DE ((uint32_t)0x00040000) /*!< Master compare 3 DMA enable */
+#define HRTIM_MDIER_MCMP4DE ((uint32_t)0x00080000) /*!< Master compare 4 DMA enable */
+#define HRTIM_MDIER_MREPDE ((uint32_t)0x00100000) /*!< Master Repetition DMA enable */
+#define HRTIM_MDIER_SYNCDE ((uint32_t)0x00200000) /*!< Synchronization input DMA enable */
+#define HRTIM_MDIER_MUPDDE ((uint32_t)0x00400000) /*!< Master update DMA enable */
+
+/******************* Bit definition for HRTIM_MCNTR register ****************/
+#define HRTIM_MCNTR_MCNTR ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
+
+/******************* Bit definition for HRTIM_MPER register *****************/
+#define HRTIM_MPER_MPER ((uint32_t)0xFFFFFFFF) /*!< Period Value */
+
+/******************* Bit definition for HRTIM_MREP register *****************/
+#define HRTIM_MREP_MREP ((uint32_t)0xFFFFFFFF) /*!<Repetition Value */
+
+/******************* Bit definition for HRTIM_MCMP1R register *****************/
+#define HRTIM_MCMP1R_MCMP1R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */
+
+/******************* Bit definition for HRTIM_MCMP2R register *****************/
+#define HRTIM_MCMP1R_MCMP2R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */
+
+/******************* Bit definition for HRTIM_MCMP3R register *****************/
+#define HRTIM_MCMP1R_MCMP3R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */
+
+/******************* Bit definition for HRTIM_MCMP4R register *****************/
+#define HRTIM_MCMP1R_MCMP4R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */
+
+/******************** Slave control register **********************************/
+#define HRTIM_TIMCR_CK_PSC ((uint32_t)0x00000007) /*!< Slave prescaler mask*/
+#define HRTIM_TIMCR_CK_PSC_0 ((uint32_t)0x00000001) /*!< prescaler bit 0 */
+#define HRTIM_TIMCR_CK_PSC_1 ((uint32_t)0x00000002) /*!< prescaler bit 1 */
+#define HRTIM_TIMCR_CK_PSC_2 ((uint32_t)0x00000004) /*!< prescaler bit 2 */
+
+#define HRTIM_TIMCR_CONT ((uint32_t)0x00000008) /*!< Slave continuous mode */
+#define HRTIM_TIMCR_RETRIG ((uint32_t)0x00000010) /*!< Slave Retrigreable mode */
+#define HRTIM_TIMCR_HALF ((uint32_t)0x00000020) /*!< Slave Half mode */
+#define HRTIM_TIMCR_PSHPLL ((uint32_t)0x00000040) /*!< Slave push-pull mode */
+
+#define HRTIM_TIMCR_SYNCRST ((uint32_t)0x00000400) /*!< Slave synchronization resets */
+#define HRTIM_TIMCR_SYNCSTRT ((uint32_t)0x00000800) /*!< Slave synchronization starts */
+
+#define HRTIM_TIMCR_DELCMP2 ((uint32_t)0x00003000) /*!< Slave delayed comparator 2 mode mask */
+#define HRTIM_TIMCR_DELCMP2_0 ((uint32_t)0x00001000) /*!< Slave delayed comparator 2 bit 0 */
+#define HRTIM_TIMCR_DELCMP2_1 ((uint32_t)0x00002000) /*!< Slave delayed comparator 2 bit 1 */
+#define HRTIM_TIMCR_DELCMP4 ((uint32_t)0x0000C000) /*!< Slave delayed comparator 4 mode mask */
+#define HRTIM_TIMCR_DELCMP4_0 ((uint32_t)0x00004000) /*!< Slave delayed comparator 4 bit 0 */
+#define HRTIM_TIMCR_DELCMP4_1 ((uint32_t)0x00008000) /*!< Slave delayed comparator 4 bit 1 */
+
+#define HRTIM_TIMCR_TREPU ((uint32_t)0x00020000) /*!< Slave repetition update */
+#define HRTIM_TIMCR_TRSTU ((uint32_t)0x00040000) /*!< Slave reset update */
+#define HRTIM_TIMCR_TAU ((uint32_t)0x00080000) /*!< Slave Timer A update reserved for TIM A */
+#define HRTIM_TIMCR_TBU ((uint32_t)0x00100000) /*!< Slave Timer B update reserved for TIM B */
+#define HRTIM_TIMCR_TCU ((uint32_t)0x00200000) /*!< Slave Timer C update reserved for TIM C */
+#define HRTIM_TIMCR_TDU ((uint32_t)0x00400000) /*!< Slave Timer D update reserved for TIM D */
+#define HRTIM_TIMCR_TEU ((uint32_t)0x00800000) /*!< Slave Timer E update reserved for TIM E */
+#define HRTIM_TIMCR_MSTU ((uint32_t)0x01000000) /*!< Master Update */
+
+#define HRTIM_TIMCR_DACSYNC ((uint32_t)0x06000000) /*!< DAC synchronization mask */
+#define HRTIM_TIMCR_DACSYNC_0 ((uint32_t)0x02000000) /*!< DAC synchronization bit 0 */
+#define HRTIM_TIMCR_DACSYNC_1 ((uint32_t)0x04000000) /*!< DAC synchronization bit 1 */
+#define HRTIM_TIMCR_PREEN ((uint32_t)0x08000000) /*!< Slave preload enable */
+
+#define HRTIM_TIMCR_UPDGAT ((uint32_t)0xF0000000) /*!< Slave update gating mask */
+#define HRTIM_TIMCR_UPDGAT_0 ((uint32_t)0x10000000) /*!< Update gating bit 0 */
+#define HRTIM_TIMCR_UPDGAT_1 ((uint32_t)0x20000000) /*!< Update gating bit 1 */
+#define HRTIM_TIMCR_UPDGAT_2 ((uint32_t)0x40000000) /*!< Update gating bit 2 */
+#define HRTIM_TIMCR_UPDGAT_3 ((uint32_t)0x80000000) /*!< Update gating bit 3 */
+
+/******************** Slave Interrupt status register **************************/
+#define HRTIM_TIMISR_CMP1 ((uint32_t)0x00000001) /*!< Slave compare 1 interrupt flag */
+#define HRTIM_TIMISR_CMP2 ((uint32_t)0x00000002) /*!< Slave compare 2 interrupt flag */
+#define HRTIM_TIMISR_CMP3 ((uint32_t)0x00000004) /*!< Slave compare 3 interrupt flag */
+#define HRTIM_TIMISR_CMP4 ((uint32_t)0x00000008) /*!< Slave compare 4 interrupt flag */
+#define HRTIM_TIMISR_REP ((uint32_t)0x00000010) /*!< Slave repetition interrupt flag */
+#define HRTIM_TIMISR_UPD ((uint32_t)0x00000040) /*!< Slave update interrupt flag */
+#define HRTIM_TIMISR_CPT1 ((uint32_t)0x00000080) /*!< Slave capture 1 interrupt flag */
+#define HRTIM_TIMISR_CPT2 ((uint32_t)0x00000100) /*!< Slave capture 2 interrupt flag */
+#define HRTIM_TIMISR_SET1 ((uint32_t)0x00000200) /*!< Slave output 1 set interrupt flag */
+#define HRTIM_TIMISR_RST1 ((uint32_t)0x00000400) /*!< Slave output 1 reset interrupt flag */
+#define HRTIM_TIMISR_SET2 ((uint32_t)0x00000800) /*!< Slave output 2 set interrupt flag */
+#define HRTIM_TIMISR_RST2 ((uint32_t)0x00001000) /*!< Slave output 2 reset interrupt flag */
+#define HRTIM_TIMISR_RST ((uint32_t)0x00002000) /*!< Slave reset interrupt flag */
+#define HRTIM_TIMISR_DLYPRT ((uint32_t)0x00004000) /*!< Slave output 1 delay protection interrupt flag */
+#define HRTIM_TIMISR_CPPSTAT ((uint32_t)0x00010000) /*!< Slave current push-pull flag */
+#define HRTIM_TIMISR_IPPSTAT ((uint32_t)0x00020000) /*!< Slave idle push-pull flag */
+#define HRTIM_TIMISR_O1STAT ((uint32_t)0x00040000) /*!< Slave output 1 state flag */
+#define HRTIM_TIMISR_O2STAT ((uint32_t)0x00080000) /*!< Slave output 2 state flag */
+#define HRTIM_TIMISR_O1CPY ((uint32_t)0x00100000) /*!< Slave output 1 copy flag */
+#define HRTIM_TIMISR_O2CPY ((uint32_t)0x00200000) /*!< Slave output 2 copy flag */
+
+/******************** Slave Interrupt clear register **************************/
+#define HRTIM_TIMICR_CMP1C ((uint32_t)0x00000001) /*!< Slave compare 1 clear flag */
+#define HRTIM_TIMICR_CMP2C ((uint32_t)0x00000002) /*!< Slave compare 2 clear flag */
+#define HRTIM_TIMICR_CMP3C ((uint32_t)0x00000004) /*!< Slave compare 3 clear flag */
+#define HRTIM_TIMICR_CMP4C ((uint32_t)0x00000008) /*!< Slave compare 4 clear flag */
+#define HRTIM_TIMICR_REPC ((uint32_t)0x00000010) /*!< Slave repetition clear flag */
+#define HRTIM_TIMICR_UPDC ((uint32_t)0x00000040) /*!< Slave update clear flag */
+#define HRTIM_TIMICR_CPT1C ((uint32_t)0x00000080) /*!< Slave capture 1 clear flag */
+#define HRTIM_TIMICR_CPT2C ((uint32_t)0x00000100) /*!< Slave capture 2 clear flag */
+#define HRTIM_TIMICR_SET1C ((uint32_t)0x00000200) /*!< Slave output 1 set clear flag */
+#define HRTIM_TIMICR_RST1C ((uint32_t)0x00000400) /*!< Slave output 1 reset clear flag */
+#define HRTIM_TIMICR_SET2C ((uint32_t)0x00000800) /*!< Slave output 2 set clear flag */
+#define HRTIM_TIMICR_RST2C ((uint32_t)0x00001000) /*!< Slave output 2 reset clear flag */
+#define HRTIM_TIMICR_RSTC ((uint32_t)0x00002000) /*!< Slave reset clear flag */
+#define HRTIM_TIMICR_DLYPRT1C ((uint32_t)0x00004000) /*!< Slave output 1 delay protection clear flag */
+#define HRTIM_TIMICR_DLYPRT2C ((uint32_t)0x00008000) /*!< Slave output 2 delay protection clear flag */
+
+/******************** Slave DMA/Interrupt enable register *********************/
+#define HRTIM_TIMDIER_CMP1IE ((uint32_t)0x00000001) /*!< Slave compare 1 interrupt enable */
+#define HRTIM_TIMDIER_CMP2IE ((uint32_t)0x00000002) /*!< Slave compare 2 interrupt enable */
+#define HRTIM_TIMDIER_CMP3IE ((uint32_t)0x00000004) /*!< Slave compare 3 interrupt enable */
+#define HRTIM_TIMDIER_CMP4IE ((uint32_t)0x00000008) /*!< Slave compare 4 interrupt enable */
+#define HRTIM_TIMDIER_REPIE ((uint32_t)0x00000010) /*!< Slave repetition interrupt enable */
+#define HRTIM_TIMDIER_UPDIE ((uint32_t)0x00000040) /*!< Slave update interrupt enable */
+#define HRTIM_TIMDIER_CPT1IE ((uint32_t)0x00000080) /*!< Slave capture 1 interrupt enable */
+#define HRTIM_TIMDIER_CPT2IE ((uint32_t)0x00000100) /*!< Slave capture 2 interrupt enable */
+#define HRTIM_TIMDIER_SET1IE ((uint32_t)0x00000200) /*!< Slave output 1 set interrupt enable */
+#define HRTIM_TIMDIER_RST1IE ((uint32_t)0x00000400) /*!< Slave output 1 reset interrupt enable */
+#define HRTIM_TIMDIER_SET2IE ((uint32_t)0x00000800) /*!< Slave output 2 set interrupt enable */
+#define HRTIM_TIMDIER_RST2IE ((uint32_t)0x00001000) /*!< Slave output 2 reset interrupt enable */
+#define HRTIM_TIMDIER_RSTIE ((uint32_t)0x00002000) /*!< Slave reset interrupt enable */
+#define HRTIM_TIMDIER_DLYPRTIE ((uint32_t)0x00004000) /*!< Slave delay protection interrupt enable */
+
+#define HRTIM_TIMDIER_CMP1DE ((uint32_t)0x00010000) /*!< Slave compare 1 request enable */
+#define HRTIM_TIMDIER_CMP2DE ((uint32_t)0x00020000) /*!< Slave compare 2 request enable */
+#define HRTIM_TIMDIER_CMP3DE ((uint32_t)0x00040000) /*!< Slave compare 3 request enable */
+#define HRTIM_TIMDIER_CMP4DE ((uint32_t)0x00080000) /*!< Slave compare 4 request enable */
+#define HRTIM_TIMDIER_REPDE ((uint32_t)0x00100000) /*!< Slave repetition request enable */
+#define HRTIM_TIMDIER_UPDDE ((uint32_t)0x00400000) /*!< Slave update request enable */
+#define HRTIM_TIMDIER_CPT1DE ((uint32_t)0x00800000) /*!< Slave capture 1 request enable */
+#define HRTIM_TIMDIER_CPT2DE ((uint32_t)0x01000000) /*!< Slave capture 2 request enable */
+#define HRTIM_TIMDIER_SET1DE ((uint32_t)0x02000000) /*!< Slave output 1 set request enable */
+#define HRTIM_TIMDIER_RST1DE ((uint32_t)0x04000000) /*!< Slave output 1 reset request enable */
+#define HRTIM_TIMDIER_SET2DE ((uint32_t)0x08000000) /*!< Slave output 2 set request enable */
+#define HRTIM_TIMDIER_RST2DE ((uint32_t)0x10000000) /*!< Slave output 2 reset request enable */
+#define HRTIM_TIMDIER_RSTDE ((uint32_t)0x20000000) /*!< Slave reset request enable */
+#define HRTIM_TIMDIER_DLYPRTDE ((uint32_t)0x40000000) /*!< Slave delay protection request enable */
+
+/****************** Bit definition for HRTIM_CNTR register ****************/
+#define HRTIM_CNTR_CNTR ((uint32_t)0xFFFFFFFF) /*!< Counter Value */
+
+/******************* Bit definition for HRTIM_PER register *****************/
+#define HRTIM_PER_PER ((uint32_t)0xFFFFFFFF) /*!< Period Value */
+
+/******************* Bit definition for HRTIM_REP register *****************/
+#define HRTIM_REP_REP ((uint32_t)0xFFFFFFFF) /*!< Repetition Value */
+
+/******************* Bit definition for HRTIM_CMP1R register *****************/
+#define HRTIM_CMP1R_CMP1R ((uint32_t)0xFFFFFFFF) /*!< Compare Value */
+
+/******************* Bit definition for HRTIM_CMP1CR register *****************/
+#define HRTIM_CMP1CR_CMP1CR ((uint32_t)0xFFFFFFFF) /*!< Compare Value */
+
+/******************* Bit definition for HRTIM_CMP2R register *****************/
+#define HRTIM_CMP2R_CMP2R ((uint32_t)0xFFFFFFFF) /*!< Compare Value */
+
+/******************* Bit definition for HRTIM_CMP3R register *****************/
+#define HRTIM_CMP3R_CMP3R ((uint32_t)0xFFFFFFFF) /*!< Compare Value */
+
+/******************* Bit definition for HRTIM_CMP4R register *****************/
+#define HRTIM_CMP4R_CMP4R ((uint32_t)0xFFFFFFFF) /*!< Compare Value */
+
+/******************* Bit definition for HRTIM_CPT1R register ****************/
+#define HRTIM_CPT1R_CPT1R ((uint32_t)0xFFFFFFFF) /*!< Capture Value */
+
+/******************* Bit definition for HRTIM_CPT2R register ****************/
+#define HRTIM_CPT2R_CPT2R ((uint32_t)0xFFFFFFFF) /*!< Capture Value */
+
+/******************** Bit definition for Slave Deadtime register **************/
+#define HRTIM_DTR_DTR ((uint32_t)0x000001FF) /*!< Dead time rising value */
+#define HRTIM_DTR_DTR_0 ((uint32_t)0x00000001) /*!< Dead time rising bit 0 */
+#define HRTIM_DTR_DTR_1 ((uint32_t)0x00000002) /*!< Dead time rising bit 1 */
+#define HRTIM_DTR_DTR_2 ((uint32_t)0x00000004) /*!< Dead time rising bit 2 */
+#define HRTIM_DTR_DTR_3 ((uint32_t)0x00000008) /*!< Dead time rising bit 3 */
+#define HRTIM_DTR_DTR_4 ((uint32_t)0x00000010) /*!< Dead time rising bit 4 */
+#define HRTIM_DTR_DTR_5 ((uint32_t)0x00000020) /*!< Dead time rising bit 5 */
+#define HRTIM_DTR_DTR_6 ((uint32_t)0x00000040) /*!< Dead time rising bit 6 */
+#define HRTIM_DTR_DTR_7 ((uint32_t)0x00000080) /*!< Dead time rising bit 7 */
+#define HRTIM_DTR_DTR_8 ((uint32_t)0x00000100) /*!< Dead time rising bit 8 */
+#define HRTIM_DTR_SDTR ((uint32_t)0x00000200) /*!< Sign dead time rising value */
+#define HRTIM_DTR_DTPRSC ((uint32_t)0x00001C00) /*!< Dead time prescaler */
+#define HRTIM_DTR_DTPRSC_0 ((uint32_t)0x00000400) /*!< Dead time prescaler bit 0 */
+#define HRTIM_DTR_DTPRSC_1 ((uint32_t)0x00000800) /*!< Dead time prescaler bit 1 */
+#define HRTIM_DTR_DTPRSC_2 ((uint32_t)0x00001000) /*!< Dead time prescaler bit 2 */
+#define HRTIM_DTR_DTRSLK ((uint32_t)0x00004000) /*!< Dead time rising sign lock */
+#define HRTIM_DTR_DTRLK ((uint32_t)0x00008000) /*!< Dead time rising lock */
+#define HRTIM_DTR_DTF ((uint32_t)0x01FF0000) /*!< Dead time falling value */
+#define HRTIM_DTR_DTF_0 ((uint32_t)0x00010000) /*!< Dead time falling bit 0 */
+#define HRTIM_DTR_DTF_1 ((uint32_t)0x00020000) /*!< Dead time falling bit 1 */
+#define HRTIM_DTR_DTF_2 ((uint32_t)0x00040000) /*!< Dead time falling bit 2 */
+#define HRTIM_DTR_DTF_3 ((uint32_t)0x00080000) /*!< Dead time falling bit 3 */
+#define HRTIM_DTR_DTF_4 ((uint32_t)0x00100000) /*!< Dead time falling bit 4 */
+#define HRTIM_DTR_DTF_5 ((uint32_t)0x00200000) /*!< Dead time falling bit 5 */
+#define HRTIM_DTR_DTF_6 ((uint32_t)0x00400000) /*!< Dead time falling bit 6 */
+#define HRTIM_DTR_DTF_7 ((uint32_t)0x00800000) /*!< Dead time falling bit 7 */
+#define HRTIM_DTR_DTF_8 ((uint32_t)0x01000000) /*!< Dead time falling bit 8 */
+#define HRTIM_DTR_SDTF ((uint32_t)0x02000000) /*!< Sign dead time falling value */
+#define HRTIM_DTR_DTFSLK ((uint32_t)0x40000000) /*!< Dead time falling sign lock */
+#define HRTIM_DTR_DTFLK ((uint32_t)0x80000000) /*!< Dead time falling lock */
+
+/**** Bit definition for Slave Output 1 set register **************************/
+#define HRTIM_SET1R_SST ((uint32_t)0x00000001) /*!< software set trigger */
+#define HRTIM_SET1R_RESYNC ((uint32_t)0x00000002) /*!< Timer A resynchronization */
+#define HRTIM_SET1R_PER ((uint32_t)0x00000004) /*!< Timer A period */
+#define HRTIM_SET1R_CMP1 ((uint32_t)0x00000008) /*!< Timer A compare 1 */
+#define HRTIM_SET1R_CMP2 ((uint32_t)0x00000010) /*!< Timer A compare 2 */
+#define HRTIM_SET1R_CMP3 ((uint32_t)0x00000020) /*!< Timer A compare 3 */
+#define HRTIM_SET1R_CMP4 ((uint32_t)0x00000040) /*!< Timer A compare 4 */
+
+#define HRTIM_SET1R_MSTPER ((uint32_t)0x00000080) /*!< Master period */
+#define HRTIM_SET1R_MSTCMP1 ((uint32_t)0x00000100) /*!< Master compare 1 */
+#define HRTIM_SET1R_MSTCMP2 ((uint32_t)0x00000200) /*!< Master compare 2 */
+#define HRTIM_SET1R_MSTCMP3 ((uint32_t)0x00000400) /*!< Master compare 3 */
+#define HRTIM_SET1R_MSTCMP4 ((uint32_t)0x00000800) /*!< Master compare 4 */
+
+#define HRTIM_SET1R_TIMEVNT1 ((uint32_t)0x00001000) /*!< Timer event 1 */
+#define HRTIM_SET1R_TIMEVNT2 ((uint32_t)0x00002000) /*!< Timer event 2 */
+#define HRTIM_SET1R_TIMEVNT3 ((uint32_t)0x00004000) /*!< Timer event 3 */
+#define HRTIM_SET1R_TIMEVNT4 ((uint32_t)0x00008000) /*!< Timer event 4 */
+#define HRTIM_SET1R_TIMEVNT5 ((uint32_t)0x00010000) /*!< Timer event 5 */
+#define HRTIM_SET1R_TIMEVNT6 ((uint32_t)0x00020000) /*!< Timer event 6 */
+#define HRTIM_SET1R_TIMEVNT7 ((uint32_t)0x00040000) /*!< Timer event 7 */
+#define HRTIM_SET1R_TIMEVNT8 ((uint32_t)0x00080000) /*!< Timer event 8 */
+#define HRTIM_SET1R_TIMEVNT9 ((uint32_t)0x00100000) /*!< Timer event 9 */
+
+#define HRTIM_SET1R_EXTVNT1 ((uint32_t)0x00200000) /*!< External event 1 */
+#define HRTIM_SET1R_EXTVNT2 ((uint32_t)0x00400000) /*!< External event 2 */
+#define HRTIM_SET1R_EXTVNT3 ((uint32_t)0x00800000) /*!< External event 3 */
+#define HRTIM_SET1R_EXTVNT4 ((uint32_t)0x01000000) /*!< External event 4 */
+#define HRTIM_SET1R_EXTVNT5 ((uint32_t)0x02000000) /*!< External event 5 */
+#define HRTIM_SET1R_EXTVNT6 ((uint32_t)0x04000000) /*!< External event 6 */
+#define HRTIM_SET1R_EXTVNT7 ((uint32_t)0x08000000) /*!< External event 7 */
+#define HRTIM_SET1R_EXTVNT8 ((uint32_t)0x10000000) /*!< External event 8 */
+#define HRTIM_SET1R_EXTVNT9 ((uint32_t)0x20000000) /*!< External event 9 */
+#define HRTIM_SET1R_EXTVNT10 ((uint32_t)0x40000000) /*!< External event 10 */
+
+#define HRTIM_SET1R_UPDATE ((uint32_t)0x80000000) /*!< Register update (transfer preload to active) */
+
+/**** Bit definition for Slave Output 1 reset register ************************/
+#define HRTIM_RST1R_SRT ((uint32_t)0x00000001) /*!< software reset trigger */
+#define HRTIM_RST1R_RESYNC ((uint32_t)0x00000002) /*!< Timer A resynchronization */
+#define HRTIM_RST1R_PER ((uint32_t)0x00000004) /*!< Timer A period */
+#define HRTIM_RST1R_CMP1 ((uint32_t)0x00000008) /*!< Timer A compare 1 */
+#define HRTIM_RST1R_CMP2 ((uint32_t)0x00000010) /*!< Timer A compare 2 */
+#define HRTIM_RST1R_CMP3 ((uint32_t)0x00000020) /*!< Timer A compare 3 */
+#define HRTIM_RST1R_CMP4 ((uint32_t)0x00000040) /*!< Timer A compare 4 */
+
+#define HRTIM_RST1R_MSTPER ((uint32_t)0x00000080) /*!< Master period */
+#define HRTIM_RST1R_MSTCMP1 ((uint32_t)0x00000100) /*!< Master compare 1 */
+#define HRTIM_RST1R_MSTCMP2 ((uint32_t)0x00000200) /*!< Master compare 2 */
+#define HRTIM_RST1R_MSTCMP3 ((uint32_t)0x00000400) /*!< Master compare 3 */
+#define HRTIM_RST1R_MSTCMP4 ((uint32_t)0x00000800) /*!< Master compare 4 */
+
+#define HRTIM_RST1R_TIMEVNT1 ((uint32_t)0x00001000) /*!< Timer event 1 */
+#define HRTIM_RST1R_TIMEVNT2 ((uint32_t)0x00002000) /*!< Timer event 2 */
+#define HRTIM_RST1R_TIMEVNT3 ((uint32_t)0x00004000) /*!< Timer event 3 */
+#define HRTIM_RST1R_TIMEVNT4 ((uint32_t)0x00008000) /*!< Timer event 4 */
+#define HRTIM_RST1R_TIMEVNT5 ((uint32_t)0x00010000) /*!< Timer event 5 */
+#define HRTIM_RST1R_TIMEVNT6 ((uint32_t)0x00020000) /*!< Timer event 6 */
+#define HRTIM_RST1R_TIMEVNT7 ((uint32_t)0x00040000) /*!< Timer event 7 */
+#define HRTIM_RST1R_TIMEVNT8 ((uint32_t)0x00080000) /*!< Timer event 8 */
+#define HRTIM_RST1R_TIMEVNT9 ((uint32_t)0x00100000) /*!< Timer event 9 */
+
+#define HRTIM_RST1R_EXTVNT1 ((uint32_t)0x00200000) /*!< External event 1 */
+#define HRTIM_RST1R_EXTVNT2 ((uint32_t)0x00400000) /*!< External event 2 */
+#define HRTIM_RST1R_EXTVNT3 ((uint32_t)0x00800000) /*!< External event 3 */
+#define HRTIM_RST1R_EXTVNT4 ((uint32_t)0x01000000) /*!< External event 4 */
+#define HRTIM_RST1R_EXTVNT5 ((uint32_t)0x02000000) /*!< External event 5 */
+#define HRTIM_RST1R_EXTVNT6 ((uint32_t)0x04000000) /*!< External event 6 */
+#define HRTIM_RST1R_EXTVNT7 ((uint32_t)0x08000000) /*!< External event 7 */
+#define HRTIM_RST1R_EXTVNT8 ((uint32_t)0x10000000) /*!< External event 8 */
+#define HRTIM_RST1R_EXTVNT9 ((uint32_t)0x20000000) /*!< External event 9 */
+#define HRTIM_RST1R_EXTVNT10 ((uint32_t)0x40000000) /*!< External event 10 */
+
+#define HRTIM_RST1R_UPDATE ((uint32_t)0x80000000) /*!< Register update (transfer preload to active) */
+
+
+/**** Bit definition for Slave Output 2 set register **************************/
+#define HRTIM_SET2R_SST ((uint32_t)0x00000001) /*!< software set trigger */
+#define HRTIM_SET2R_RESYNC ((uint32_t)0x00000002) /*!< Timer A resynchronization */
+#define HRTIM_SET2R_PER ((uint32_t)0x00000004) /*!< Timer A period */
+#define HRTIM_SET2R_CMP1 ((uint32_t)0x00000008) /*!< Timer A compare 1 */
+#define HRTIM_SET2R_CMP2 ((uint32_t)0x00000010) /*!< Timer A compare 2 */
+#define HRTIM_SET2R_CMP3 ((uint32_t)0x00000020) /*!< Timer A compare 3 */
+#define HRTIM_SET2R_CMP4 ((uint32_t)0x00000040) /*!< Timer A compare 4 */
+
+#define HRTIM_SET2R_MSTPER ((uint32_t)0x00000080) /*!< Master period */
+#define HRTIM_SET2R_MSTCMP1 ((uint32_t)0x00000100) /*!< Master compare 1 */
+#define HRTIM_SET2R_MSTCMP2 ((uint32_t)0x00000200) /*!< Master compare 2 */
+#define HRTIM_SET2R_MSTCMP3 ((uint32_t)0x00000400) /*!< Master compare 3 */
+#define HRTIM_SET2R_MSTCMP4 ((uint32_t)0x00000800) /*!< Master compare 4 */
+
+#define HRTIM_SET2R_TIMEVNT1 ((uint32_t)0x00001000) /*!< Timer event 1 */
+#define HRTIM_SET2R_TIMEVNT2 ((uint32_t)0x00002000) /*!< Timer event 2 */
+#define HRTIM_SET2R_TIMEVNT3 ((uint32_t)0x00004000) /*!< Timer event 3 */
+#define HRTIM_SET2R_TIMEVNT4 ((uint32_t)0x00008000) /*!< Timer event 4 */
+#define HRTIM_SET2R_TIMEVNT5 ((uint32_t)0x00010000) /*!< Timer event 5 */
+#define HRTIM_SET2R_TIMEVNT6 ((uint32_t)0x00020000) /*!< Timer event 6 */
+#define HRTIM_SET2R_TIMEVNT7 ((uint32_t)0x00040000) /*!< Timer event 7 */
+#define HRTIM_SET2R_TIMEVNT8 ((uint32_t)0x00080000) /*!< Timer event 8 */
+#define HRTIM_SET2R_TIMEVNT9 ((uint32_t)0x00100000) /*!< Timer event 9 */
+
+#define HRTIM_SET2R_EXTVNT1 ((uint32_t)0x00200000) /*!< External event 1 */
+#define HRTIM_SET2R_EXTVNT2 ((uint32_t)0x00400000) /*!< External event 2 */
+#define HRTIM_SET2R_EXTVNT3 ((uint32_t)0x00800000) /*!< External event 3 */
+#define HRTIM_SET2R_EXTVNT4 ((uint32_t)0x01000000) /*!< External event 4 */
+#define HRTIM_SET2R_EXTVNT5 ((uint32_t)0x02000000) /*!< External event 5 */
+#define HRTIM_SET2R_EXTVNT6 ((uint32_t)0x04000000) /*!< External event 6 */
+#define HRTIM_SET2R_EXTVNT7 ((uint32_t)0x08000000) /*!< External event 7 */
+#define HRTIM_SET2R_EXTVNT8 ((uint32_t)0x10000000) /*!< External event 8 */
+#define HRTIM_SET2R_EXTVNT9 ((uint32_t)0x20000000) /*!< External event 9 */
+#define HRTIM_SET2R_EXTVNT10 ((uint32_t)0x40000000) /*!< External event 10 */
+
+#define HRTIM_SET2R_UPDATE ((uint32_t)0x80000000) /*!< Register update (transfer preload to active) */
+
+/**** Bit definition for Slave Output 2 reset register ************************/
+#define HRTIM_RST2R_SRT ((uint32_t)0x00000001) /*!< software reset trigger */
+#define HRTIM_RST2R_RESYNC ((uint32_t)0x00000002) /*!< Timer A resynchronization */
+#define HRTIM_RST2R_PER ((uint32_t)0x00000004) /*!< Timer A period */
+#define HRTIM_RST2R_CMP1 ((uint32_t)0x00000008) /*!< Timer A compare 1 */
+#define HRTIM_RST2R_CMP2 ((uint32_t)0x00000010) /*!< Timer A compare 2 */
+#define HRTIM_RST2R_CMP3 ((uint32_t)0x00000020) /*!< Timer A compare 3 */
+#define HRTIM_RST2R_CMP4 ((uint32_t)0x00000040) /*!< Timer A compare 4 */
+
+#define HRTIM_RST2R_MSTPER ((uint32_t)0x00000080) /*!< Master period */
+#define HRTIM_RST2R_MSTCMP1 ((uint32_t)0x00000100) /*!< Master compare 1 */
+#define HRTIM_RST2R_MSTCMP2 ((uint32_t)0x00000200) /*!< Master compare 2 */
+#define HRTIM_RST2R_MSTCMP3 ((uint32_t)0x00000400) /*!< Master compare 3 */
+#define HRTIM_RST2R_MSTCMP4 ((uint32_t)0x00000800) /*!< Master compare 4 */
+
+#define HRTIM_RST2R_TIMEVNT1 ((uint32_t)0x00001000) /*!< Timer event 1 */
+#define HRTIM_RST2R_TIMEVNT2 ((uint32_t)0x00002000) /*!< Timer event 2 */
+#define HRTIM_RST2R_TIMEVNT3 ((uint32_t)0x00004000) /*!< Timer event 3 */
+#define HRTIM_RST2R_TIMEVNT4 ((uint32_t)0x00008000) /*!< Timer event 4 */
+#define HRTIM_RST2R_TIMEVNT5 ((uint32_t)0x00010000) /*!< Timer event 5 */
+#define HRTIM_RST2R_TIMEVNT6 ((uint32_t)0x00020000) /*!< Timer event 6 */
+#define HRTIM_RST2R_TIMEVNT7 ((uint32_t)0x00040000) /*!< Timer event 7 */
+#define HRTIM_RST2R_TIMEVNT8 ((uint32_t)0x00080000) /*!< Timer event 8 */
+#define HRTIM_RST2R_TIMEVNT9 ((uint32_t)0x00100000) /*!< Timer event 9 */
+
+#define HRTIM_RST2R_EXTVNT1 ((uint32_t)0x00200000) /*!< External event 1 */
+#define HRTIM_RST2R_EXTVNT2 ((uint32_t)0x00400000) /*!< External event 2 */
+#define HRTIM_RST2R_EXTVNT3 ((uint32_t)0x00800000) /*!< External event 3 */
+#define HRTIM_RST2R_EXTVNT4 ((uint32_t)0x01000000) /*!< External event 4 */
+#define HRTIM_RST2R_EXTVNT5 ((uint32_t)0x02000000) /*!< External event 5 */
+#define HRTIM_RST2R_EXTVNT6 ((uint32_t)0x04000000) /*!< External event 6 */
+#define HRTIM_RST2R_EXTVNT7 ((uint32_t)0x08000000) /*!< External event 7 */
+#define HRTIM_RST2R_EXTVNT8 ((uint32_t)0x10000000) /*!< External event 8 */
+#define HRTIM_RST2R_EXTVNT9 ((uint32_t)0x20000000) /*!< External event 9 */
+#define HRTIM_RST2R_EXTVNT10 ((uint32_t)0x40000000) /*!< External event 10 */
+
+#define HRTIM_RST2R_UPDATE ((uint32_t)0x80000000) /*!< Register update (transfer preload to active) */
+
+/**** Bit definition for Slave external event filtering register 1 ***********/
+#define HRTIM_EEFR1_EE1LTCH ((uint32_t)0x00000001) /*!< External Event 1 latch */
+#define HRTIM_EEFR1_EE1FLTR ((uint32_t)0x0000001E) /*!< External Event 1 filter mask */
+#define HRTIM_EEFR1_EE1FLTR_0 ((uint32_t)0x00000002) /*!< External Event 1 bit 0 */
+#define HRTIM_EEFR1_EE1FLTR_1 ((uint32_t)0x00000004) /*!< External Event 1 bit 1*/
+#define HRTIM_EEFR1_EE1FLTR_2 ((uint32_t)0x00000008) /*!< External Event 1 bit 2 */
+#define HRTIM_EEFR1_EE1FLTR_3 ((uint32_t)0x00000010) /*!< External Event 1 bit 3 */
+
+#define HRTIM_EEFR1_EE2LTCH ((uint32_t)0x00000040) /*!< External Event 2 latch */
+#define HRTIM_EEFR1_EE2FLTR ((uint32_t)0x00000780) /*!< External Event 2 filter mask */
+#define HRTIM_EEFR1_EE2FLTR_0 ((uint32_t)0x00000080) /*!< External Event 2 bit 0 */
+#define HRTIM_EEFR1_EE2FLTR_1 ((uint32_t)0x00000100) /*!< External Event 2 bit 1*/
+#define HRTIM_EEFR1_EE2FLTR_2 ((uint32_t)0x00000200) /*!< External Event 2 bit 2 */
+#define HRTIM_EEFR1_EE2FLTR_3 ((uint32_t)0x00000400) /*!< External Event 2 bit 3 */
+
+#define HRTIM_EEFR1_EE3LTCH ((uint32_t)0x00001000) /*!< External Event 3 latch */
+#define HRTIM_EEFR1_EE3FLTR ((uint32_t)0x0001E000) /*!< External Event 3 filter mask */
+#define HRTIM_EEFR1_EE3FLTR_0 ((uint32_t)0x00002000) /*!< External Event 3 bit 0 */
+#define HRTIM_EEFR1_EE3FLTR_1 ((uint32_t)0x00004000) /*!< External Event 3 bit 1*/
+#define HRTIM_EEFR1_EE3FLTR_2 ((uint32_t)0x00008000) /*!< External Event 3 bit 2 */
+#define HRTIM_EEFR1_EE3FLTR_3 ((uint32_t)0x00010000) /*!< External Event 3 bit 3 */
+
+#define HRTIM_EEFR1_EE4LTCH ((uint32_t)0x00040000) /*!< External Event 4 latch */
+#define HRTIM_EEFR1_EE4FLTR ((uint32_t)0x00780000) /*!< External Event 4 filter mask */
+#define HRTIM_EEFR1_EE4FLTR_0 ((uint32_t)0x00080000) /*!< External Event 4 bit 0 */
+#define HRTIM_EEFR1_EE4FLTR_1 ((uint32_t)0x00100000) /*!< External Event 4 bit 1*/
+#define HRTIM_EEFR1_EE4FLTR_2 ((uint32_t)0x00200000) /*!< External Event 4 bit 2 */
+#define HRTIM_EEFR1_EE4FLTR_3 ((uint32_t)0x00400000) /*!< External Event 4 bit 3 */
+
+#define HRTIM_EEFR1_EE5LTCH ((uint32_t)0x01000000) /*!< External Event 5 latch */
+#define HRTIM_EEFR1_EE5FLTR ((uint32_t)0x1E000000) /*!< External Event 5 filter mask */
+#define HRTIM_EEFR1_EE5FLTR_0 ((uint32_t)0x02000000) /*!< External Event 5 bit 0 */
+#define HRTIM_EEFR1_EE5FLTR_1 ((uint32_t)0x04000000) /*!< External Event 5 bit 1*/
+#define HRTIM_EEFR1_EE5FLTR_2 ((uint32_t)0x08000000) /*!< External Event 5 bit 2 */
+#define HRTIM_EEFR1_EE5FLTR_3 ((uint32_t)0x10000000) /*!< External Event 5 bit 3 */
+
+/**** Bit definition for Slave external event filtering register 2 ***********/
+#define HRTIM_EEFR2_EE6LTCH ((uint32_t)0x00000001) /*!< External Event 6 latch */
+#define HRTIM_EEFR2_EE6FLTR ((uint32_t)0x0000001E) /*!< External Event 6 filter mask */
+#define HRTIM_EEFR2_EE6FLTR_0 ((uint32_t)0x00000002) /*!< External Event 6 bit 0 */
+#define HRTIM_EEFR2_EE6FLTR_1 ((uint32_t)0x00000004) /*!< External Event 6 bit 1*/
+#define HRTIM_EEFR2_EE6FLTR_2 ((uint32_t)0x00000008) /*!< External Event 6 bit 2 */
+#define HRTIM_EEFR2_EE6FLTR_3 ((uint32_t)0x00000010) /*!< External Event 6 bit 3 */
+
+#define HRTIM_EEFR2_EE7LTCH ((uint32_t)0x00000040) /*!< External Event 7 latch */
+#define HRTIM_EEFR2_EE7FLTR ((uint32_t)0x00000780) /*!< External Event 7 filter mask */
+#define HRTIM_EEFR2_EE7FLTR_0 ((uint32_t)0x00000080) /*!< External Event 7 bit 0 */
+#define HRTIM_EEFR2_EE7FLTR_1 ((uint32_t)0x00000100) /*!< External Event 7 bit 1*/
+#define HRTIM_EEFR2_EE7FLTR_2 ((uint32_t)0x00000200) /*!< External Event 7 bit 2 */
+#define HRTIM_EEFR2_EE7FLTR_3 ((uint32_t)0x00000400) /*!< External Event 7 bit 3 */
+
+#define HRTIM_EEFR2_EE8LTCH ((uint32_t)0x00001000) /*!< External Event 8 latch */
+#define HRTIM_EEFR2_EE8FLTR ((uint32_t)0x0001E000) /*!< External Event 8 filter mask */
+#define HRTIM_EEFR2_EE8FLTR_0 ((uint32_t)0x00002000) /*!< External Event 8 bit 0 */
+#define HRTIM_EEFR2_EE8FLTR_1 ((uint32_t)0x00004000) /*!< External Event 8 bit 1*/
+#define HRTIM_EEFR2_EE8FLTR_2 ((uint32_t)0x00008000) /*!< External Event 8 bit 2 */
+#define HRTIM_EEFR2_EE8FLTR_3 ((uint32_t)0x00010000) /*!< External Event 8 bit 3 */
+
+#define HRTIM_EEFR2_EE9LTCH ((uint32_t)0x00040000) /*!< External Event 9 latch */
+#define HRTIM_EEFR2_EE9FLTR ((uint32_t)0x00780000) /*!< External Event 9 filter mask */
+#define HRTIM_EEFR2_EE9FLTR_0 ((uint32_t)0x00080000) /*!< External Event 9 bit 0 */
+#define HRTIM_EEFR2_EE9FLTR_1 ((uint32_t)0x00100000) /*!< External Event 9 bit 1*/
+#define HRTIM_EEFR2_EE9FLTR_2 ((uint32_t)0x00200000) /*!< External Event 9 bit 2 */
+#define HRTIM_EEFR2_EE9FLTR_3 ((uint32_t)0x00400000) /*!< External Event 9 bit 3 */
+
+#define HRTIM_EEFR2_EE10LTCH ((uint32_t)0x01000000) /*!< External Event 10 latch */
+#define HRTIM_EEFR2_EE10FLTR ((uint32_t)0x1E000000) /*!< External Event 10 filter mask */
+#define HRTIM_EEFR2_EE10FLTR_0 ((uint32_t)0x02000000) /*!< External Event 10 bit 0 */
+#define HRTIM_EEFR2_EE10FLTR_1 ((uint32_t)0x04000000) /*!< External Event 10 bit 1*/
+#define HRTIM_EEFR2_EE10FLTR_2 ((uint32_t)0x08000000) /*!< External Event 10 bit 2 */
+#define HRTIM_EEFR2_EE10FLTR_3 ((uint32_t)0x10000000) /*!< External Event 10 bit 3 */
+
+/**** Bit definition for Slave Timer reset register ***************************/
+#define HRTIM_RSTR_UPDATE ((uint32_t)0x00000002) /*!< Timer update */
+#define HRTIM_RSTR_CMP2 ((uint32_t)0x00000004) /*!< Timer compare2 */
+#define HRTIM_RSTR_CMP4 ((uint32_t)0x00000008) /*!< Timer compare4 */
+
+#define HRTIM_RSTR_MSTPER ((uint32_t)0x00000010) /*!< Master period */
+#define HRTIM_RSTR_MSTCMP1 ((uint32_t)0x00000020) /*!< Master compare1 */
+#define HRTIM_RSTR_MSTCMP2 ((uint32_t)0x00000040) /*!< Master compare2 */
+#define HRTIM_RSTR_MSTCMP3 ((uint32_t)0x00000080) /*!< Master compare3 */
+#define HRTIM_RSTR_MSTCMP4 ((uint32_t)0x00000100) /*!< Master compare4 */
+
+#define HRTIM_RSTR_EXTEVNT1 ((uint32_t)0x00000200) /*!< External event 1 */
+#define HRTIM_RSTR_EXTEVNT2 ((uint32_t)0x00000400) /*!< External event 2 */
+#define HRTIM_RSTR_EXTEVNT3 ((uint32_t)0x00000800) /*!< External event 3 */
+#define HRTIM_RSTR_EXTEVNT4 ((uint32_t)0x00001000) /*!< External event 4 */
+#define HRTIM_RSTR_EXTEVNT5 ((uint32_t)0x00002000) /*!< External event 5 */
+#define HRTIM_RSTR_EXTEVNT6 ((uint32_t)0x00004000) /*!< External event 6 */
+#define HRTIM_RSTR_EXTEVNT7 ((uint32_t)0x00008000) /*!< External event 7 */
+#define HRTIM_RSTR_EXTEVNT8 ((uint32_t)0x00010000) /*!< External event 8 */
+#define HRTIM_RSTR_EXTEVNT9 ((uint32_t)0x00020000) /*!< External event 9 */
+#define HRTIM_RSTR_EXTEVNT10 ((uint32_t)0x00040000) /*!< External event 10 */
+
+#define HRTIM_RSTR_TIMBCMP1 ((uint32_t)0x00080000) /*!< Timer B compare 1 */
+#define HRTIM_RSTR_TIMBCMP2 ((uint32_t)0x00100000) /*!< Timer B compare 2 */
+#define HRTIM_RSTR_TIMBCMP4 ((uint32_t)0x00200000) /*!< Timer B compare 4 */
+
+#define HRTIM_RSTR_TIMCCMP1 ((uint32_t)0x00400000) /*!< Timer C compare 1 */
+#define HRTIM_RSTR_TIMCCMP2 ((uint32_t)0x00800000) /*!< Timer C compare 2 */
+#define HRTIM_RSTR_TIMCCMP4 ((uint32_t)0x01000000) /*!< Timer C compare 4 */
+
+#define HRTIM_RSTR_TIMDCMP1 ((uint32_t)0x02000000) /*!< Timer D compare 1 */
+#define HRTIM_RSTR_TIMDCMP2 ((uint32_t)0x04000000) /*!< Timer D compare 2 */
+#define HRTIM_RSTR_TIMDCMP4 ((uint32_t)0x08000000) /*!< Timer D compare 4 */
+
+#define HRTIM_RSTR_TIMECMP1 ((uint32_t)0x10000000) /*!< Timer E compare 1 */
+#define HRTIM_RSTR_TIMECMP2 ((uint32_t)0x20000000) /*!< Timer E compare 2 */
+#define HRTIM_RSTR_TIMECMP4 ((uint32_t)0x40000000) /*!< Timer E compare 4 */
+
+/**** Bit definition for Slave Timer Chopper register *************************/
+#define HRTIM_CHPR_CARFRQ ((uint32_t)0x0000000F) /*!< Timer carrier frequency value */
+#define HRTIM_CHPR_CARFRQ_0 ((uint32_t)0x00000001) /*!< Timer carrier frequency value bit 0 */
+#define HRTIM_CHPR_CARFRQ_1 ((uint32_t)0x00000002) /*!< Timer carrier frequency value bit 1 */
+#define HRTIM_CHPR_CARFRQ_2 ((uint32_t)0x00000004) /*!< Timer carrier frequency value bit 2 */
+#define HRTIM_CHPR_CARFRQ_3 ((uint32_t)0x00000008) /*!< Timer carrier frequency value bit 3 */
+
+#define HRTIM_CHPR_CARDTY ((uint32_t)0x00000070) /*!< Timer chopper duty cycle value */
+#define HRTIM_CHPR_CARDTY_0 ((uint32_t)0x00000010) /*!< Timer chopper duty cycle value bit 0 */
+#define HRTIM_CHPR_CARDTY_1 ((uint32_t)0x00000020) /*!< Timer chopper duty cycle value bit 1 */
+#define HRTIM_CHPR_CARDTY_2 ((uint32_t)0x00000040) /*!< Timer chopper duty cycle value bit 2 */
+
+#define HRTIM_CHPR_STRPW ((uint32_t)0x00000780) /*!< Timer start pulse width value */
+#define HRTIM_CHPR_STRPW_0 ((uint32_t)0x00000080) /*!< Timer start pulse width value bit 0 */
+#define HRTIM_CHPR_STRPW_1 ((uint32_t)0x00000100) /*!< Timer start pulse width value bit 1 */
+#define HRTIM_CHPR_STRPW_2 ((uint32_t)0x00000200) /*!< Timer start pulse width value bit 2 */
+#define HRTIM_CHPR_STRPW_3 ((uint32_t)0x00000400) /*!< Timer start pulse width value bit 3 */
+
+/**** Bit definition for Slave Timer Capture 1 control register ***************/
+#define HRTIM_CPT1CR_SWCPT ((uint32_t)0x00000001) /*!< Software capture */
+#define HRTIM_CPT1CR_UPDCPT ((uint32_t)0x00000002) /*!< Update capture */
+#define HRTIM_CPT1CR_EXEV1CPT ((uint32_t)0x00000004) /*!< External event 1 capture */
+#define HRTIM_CPT1CR_EXEV2CPT ((uint32_t)0x00000008) /*!< External event 2 capture */
+#define HRTIM_CPT1CR_EXEV3CPT ((uint32_t)0x00000010) /*!< External event 3 capture */
+#define HRTIM_CPT1CR_EXEV4CPT ((uint32_t)0x00000020) /*!< External event 4 capture */
+#define HRTIM_CPT1CR_EXEV5CPT ((uint32_t)0x00000040) /*!< External event 5 capture */
+#define HRTIM_CPT1CR_EXEV6CPT ((uint32_t)0x00000080) /*!< External event 6 capture */
+#define HRTIM_CPT1CR_EXEV7CPT ((uint32_t)0x00000100) /*!< External event 7 capture */
+#define HRTIM_CPT1CR_EXEV8CPT ((uint32_t)0x00000200) /*!< External event 8 capture */
+#define HRTIM_CPT1CR_EXEV9CPT ((uint32_t)0x00000400) /*!< External event 9 capture */
+#define HRTIM_CPT1CR_EXEV10CPT ((uint32_t)0x00000800) /*!< External event 10 capture */
+
+#define HRTIM_CPT1CR_TA1SET ((uint32_t)0x00001000) /*!< Timer A output 1 set */
+#define HRTIM_CPT1CR_TA1RST ((uint32_t)0x00002000) /*!< Timer A output 1 reset */
+#define HRTIM_CPT1CR_TA1CMP1 ((uint32_t)0x00004000) /*!< Timer A compare 1 */
+#define HRTIM_CPT1CR_TA1CMP2 ((uint32_t)0x00008000) /*!< Timer A compare 2 */
+
+#define HRTIM_CPT1CR_TB1SET ((uint32_t)0x00010000) /*!< Timer B output 1 set */
+#define HRTIM_CPT1CR_TB1RST ((uint32_t)0x00020000) /*!< Timer B output 1 reset */
+#define HRTIM_CPT1CR_TB1CMP1 ((uint32_t)0x00040000) /*!< Timer B compare 1 */
+#define HRTIM_CPT1CR_TB1CMP2 ((uint32_t)0x00080000) /*!< Timer B compare 2 */
+
+#define HRTIM_CPT1CR_TC1SET ((uint32_t)0x00100000) /*!< Timer C output 1 set */
+#define HRTIM_CPT1CR_TC1RST ((uint32_t)0x00200000) /*!< Timer C output 1 reset */
+#define HRTIM_CPT1CR_TC1CMP1 ((uint32_t)0x00400000) /*!< Timer C compare 1 */
+#define HRTIM_CPT1CR_TC1CMP2 ((uint32_t)0x00800000) /*!< Timer C compare 2 */
+
+#define HRTIM_CPT1CR_TD1SET ((uint32_t)0x01000000) /*!< Timer D output 1 set */
+#define HRTIM_CPT1CR_TD1RST ((uint32_t)0x02000000) /*!< Timer D output 1 reset */
+#define HRTIM_CPT1CR_TD1CMP1 ((uint32_t)0x04000000) /*!< Timer D compare 1 */
+#define HRTIM_CPT1CR_TD1CMP2 ((uint32_t)0x08000000) /*!< Timer D compare 2 */
+
+#define HRTIM_CPT1CR_TE1SET ((uint32_t)0x10000000) /*!< Timer E output 1 set */
+#define HRTIM_CPT1CR_TE1RST ((uint32_t)0x20000000) /*!< Timer E output 1 reset */
+#define HRTIM_CPT1CR_TE1CMP1 ((uint32_t)0x40000000) /*!< Timer E compare 1 */
+#define HRTIM_CPT1CR_TE1CMP2 ((uint32_t)0x80000000) /*!< Timer E compare 2 */
+
+/**** Bit definition for Slave Timer Capture 2 control register ***************/
+#define HRTIM_CPT2CR_SWCPT ((uint32_t)0x00000001) /*!< Software capture */
+#define HRTIM_CPT2CR_UPDCPT ((uint32_t)0x00000002) /*!< Update capture */
+#define HRTIM_CPT2CR_EXEV1CPT ((uint32_t)0x00000004) /*!< External event 1 capture */
+#define HRTIM_CPT2CR_EXEV2CPT ((uint32_t)0x00000008) /*!< External event 2 capture */
+#define HRTIM_CPT2CR_EXEV3CPT ((uint32_t)0x00000010) /*!< External event 3 capture */
+#define HRTIM_CPT2CR_EXEV4CPT ((uint32_t)0x00000020) /*!< External event 4 capture */
+#define HRTIM_CPT2CR_EXEV5CPT ((uint32_t)0x00000040) /*!< External event 5 capture */
+#define HRTIM_CPT2CR_EXEV6CPT ((uint32_t)0x00000080) /*!< External event 6 capture */
+#define HRTIM_CPT2CR_EXEV7CPT ((uint32_t)0x00000100) /*!< External event 7 capture */
+#define HRTIM_CPT2CR_EXEV8CPT ((uint32_t)0x00000200) /*!< External event 8 capture */
+#define HRTIM_CPT2CR_EXEV9CPT ((uint32_t)0x00000400) /*!< External event 9 capture */
+#define HRTIM_CPT2CR_EXEV10CPT ((uint32_t)0x00000800) /*!< External event 10 capture */
+
+#define HRTIM_CPT2CR_TA1SET ((uint32_t)0x00001000) /*!< Timer A output 1 set */
+#define HRTIM_CPT2CR_TA1RST ((uint32_t)0x00002000) /*!< Timer A output 1 reset */
+#define HRTIM_CPT2CR_TA1CMP1 ((uint32_t)0x00004000) /*!< Timer A compare 1 */
+#define HRTIM_CPT2CR_TA1CMP2 ((uint32_t)0x00008000) /*!< Timer A compare 2 */
+
+#define HRTIM_CPT2CR_TB1SET ((uint32_t)0x00010000) /*!< Timer B output 1 set */
+#define HRTIM_CPT2CR_TB1RST ((uint32_t)0x00020000) /*!< Timer B output 1 reset */
+#define HRTIM_CPT2CR_TB1CMP1 ((uint32_t)0x00040000) /*!< Timer B compare 1 */
+#define HRTIM_CPT2CR_TB1CMP2 ((uint32_t)0x00080000) /*!< Timer B compare 2 */
+
+#define HRTIM_CPT2CR_TC1SET ((uint32_t)0x00100000) /*!< Timer C output 1 set */
+#define HRTIM_CPT2CR_TC1RST ((uint32_t)0x00200000) /*!< Timer C output 1 reset */
+#define HRTIM_CPT2CR_TC1CMP1 ((uint32_t)0x00400000) /*!< Timer C compare 1 */
+#define HRTIM_CPT2CR_TC1CMP2 ((uint32_t)0x00800000) /*!< Timer C compare 2 */
+
+#define HRTIM_CPT2CR_TD1SET ((uint32_t)0x01000000) /*!< Timer D output 1 set */
+#define HRTIM_CPT2CR_TD1RST ((uint32_t)0x02000000) /*!< Timer D output 1 reset */
+#define HRTIM_CPT2CR_TD1CMP1 ((uint32_t)0x04000000) /*!< Timer D compare 1 */
+#define HRTIM_CPT2CR_TD1CMP2 ((uint32_t)0x08000000) /*!< Timer D compare 2 */
+
+#define HRTIM_CPT2CR_TE1SET ((uint32_t)0x10000000) /*!< Timer E output 1 set */
+#define HRTIM_CPT2CR_TE1RST ((uint32_t)0x20000000) /*!< Timer E output 1 reset */
+#define HRTIM_CPT2CR_TE1CMP1 ((uint32_t)0x40000000) /*!< Timer E compare 1 */
+#define HRTIM_CPT2CR_TE1CMP2 ((uint32_t)0x80000000) /*!< Timer E compare 2 */
+
+/**** Bit definition for Slave Timer Output register **************************/
+#define HRTIM_OUTR_POL1 ((uint32_t)0x00000002) /*!< Slave output 1 polarity */
+#define HRTIM_OUTR_IDLM1 ((uint32_t)0x00000004) /*!< Slave output 1 idle mode */
+#define HRTIM_OUTR_IDLES1 ((uint32_t)0x00000008) /*!< Slave output 1 idle state */
+#define HRTIM_OUTR_FAULT1 ((uint32_t)0x00000030) /*!< Slave output 1 fault state */
+#define HRTIM_OUTR_FAULT1_0 ((uint32_t)0x00000010) /*!< Slave output 1 fault state bit 0 */
+#define HRTIM_OUTR_FAULT1_1 ((uint32_t)0x00000020) /*!< Slave output 1 fault state bit 1 */
+#define HRTIM_OUTR_CHP1 ((uint32_t)0x00000040) /*!< Slave output 1 chopper enable */
+#define HRTIM_OUTR_DIDL1 ((uint32_t)0x00000080) /*!< Slave output 1 dead time idle */
+
+#define HRTIM_OUTR_DTEN ((uint32_t)0x00000100) /*!< Slave output deadtime enable */
+#define HRTIM_OUTR_DLYPRTEN ((uint32_t)0x00000200) /*!< Slave output delay protection enable */
+#define HRTIM_OUTR_DLYPRT ((uint32_t)0x00001C00) /*!< Slave output delay protection */
+#define HRTIM_OUTR_DLYPRT_0 ((uint32_t)0x00000400) /*!< Slave output delay protection bit 0 */
+#define HRTIM_OUTR_DLYPRT_1 ((uint32_t)0x00000800) /*!< Slave output delay protection bit 1 */
+#define HRTIM_OUTR_DLYPRT_2 ((uint32_t)0x00001000) /*!< Slave output delay protection bit 2 */
+
+#define HRTIM_OUTR_POL2 ((uint32_t)0x00020000) /*!< Slave output 2 polarity */
+#define HRTIM_OUTR_IDLM2 ((uint32_t)0x00040000) /*!< Slave output 2 idle mode */
+#define HRTIM_OUTR_IDLES2 ((uint32_t)0x00080000) /*!< Slave output 2 idle state */
+#define HRTIM_OUTR_FAULT2 ((uint32_t)0x00300000) /*!< Slave output 2 fault state */
+#define HRTIM_OUTR_FAULT2_0 ((uint32_t)0x00100000) /*!< Slave output 2 fault state bit 0 */
+#define HRTIM_OUTR_FAULT2_1 ((uint32_t)0x00200000) /*!< Slave output 2 fault state bit 1 */
+#define HRTIM_OUTR_CHP2 ((uint32_t)0x00400000) /*!< Slave output 2 chopper enable */
+#define HRTIM_OUTR_DIDL2 ((uint32_t)0x00800000) /*!< Slave output 2 dead time idle */
+
+/**** Bit definition for Slave Timer Fault register ***************************/
+#define HRTIM_FLTR_FLT1EN ((uint32_t)0x00000001) /*!< Fault 1 enable */
+#define HRTIM_FLTR_FLT2EN ((uint32_t)0x00000002) /*!< Fault 2 enable */
+#define HRTIM_FLTR_FLT3EN ((uint32_t)0x00000004) /*!< Fault 3 enable */
+#define HRTIM_FLTR_FLT4EN ((uint32_t)0x00000008) /*!< Fault 4 enable */
+#define HRTIM_FLTR_FLT5EN ((uint32_t)0x00000010) /*!< Fault 5 enable */
+#define HRTIM_FLTR_FLTCLK ((uint32_t)0x80000000) /*!< Fault sources lock */
+
+/**** Bit definition for Common HRTIM Timer control register 1 ****************/
+#define HRTIM_CR1_MUDIS ((uint32_t)0x00000001) /*!< Master update disable*/
+#define HRTIM_CR1_TAUDIS ((uint32_t)0x00000002) /*!< Timer A update disable*/
+#define HRTIM_CR1_TBUDIS ((uint32_t)0x00000004) /*!< Timer B update disable*/
+#define HRTIM_CR1_TCUDIS ((uint32_t)0x00000008) /*!< Timer C update disable*/
+#define HRTIM_CR1_TDUDIS ((uint32_t)0x00000010) /*!< Timer D update disable*/
+#define HRTIM_CR1_TEUDIS ((uint32_t)0x00000020) /*!< Timer E update disable*/
+#define HRTIM_CR1_ADC1USRC ((uint32_t)0x00070000) /*!< ADC Trigger 1 update source */
+#define HRTIM_CR1_ADC1USRC_0 ((uint32_t)0x00010000) /*!< ADC Trigger 1 update source bit 0 */
+#define HRTIM_CR1_ADC1USRC_1 ((uint32_t)0x00020000) /*!< ADC Trigger 1 update source bit 1 */
+#define HRTIM_CR1_ADC1USRC_2 ((uint32_t)0x00040000) /*!< ADC Trigger 1 update source bit 2 */
+#define HRTIM_CR1_ADC2USRC ((uint32_t)0x00380000) /*!< ADC Trigger 2 update source */
+#define HRTIM_CR1_ADC2USRC_0 ((uint32_t)0x00080000) /*!< ADC Trigger 2 update source bit 0 */
+#define HRTIM_CR1_ADC2USRC_1 ((uint32_t)0x00100000) /*!< ADC Trigger 2 update source bit 1 */
+#define HRTIM_CR1_ADC2USRC_2 ((uint32_t)0x00200000) /*!< ADC Trigger 2 update source bit 2 */
+#define HRTIM_CR1_ADC3USRC ((uint32_t)0x01C00000) /*!< ADC Trigger 3 update source */
+#define HRTIM_CR1_ADC3USRC_0 ((uint32_t)0x00400000) /*!< ADC Trigger 3 update source bit 0 */
+#define HRTIM_CR1_ADC3USRC_1 ((uint32_t)0x00800000) /*!< ADC Trigger 3 update source bit 1 */
+#define HRTIM_CR1_ADC3USRC_2 ((uint32_t)0x01000000) /*!< ADC Trigger 3 update source bit 2 */
+#define HRTIM_CR1_ADC4USRC ((uint32_t)0x0E000000) /*!< ADC Trigger 4 update source */
+#define HRTIM_CR1_ADC4USRC_0 ((uint32_t)0x02000000) /*!< ADC Trigger 4 update source bit 0 */
+#define HRTIM_CR1_ADC4USRC_1 ((uint32_t)0x04000000) /*!< ADC Trigger 4 update source bit 1 */
+#define HRTIM_CR1_ADC4USRC_2 ((uint32_t)0x0800000) /*!< ADC Trigger 4 update source bit 2 */
+
+/**** Bit definition for Common HRTIM Timer control register 2 ****************/
+#define HRTIM_CR2_MSWU ((uint32_t)0x00000001) /*!< Master software update */
+#define HRTIM_CR2_TASWU ((uint32_t)0x00000002) /*!< Timer A software update */
+#define HRTIM_CR2_TBSWU ((uint32_t)0x00000004) /*!< Timer B software update */
+#define HRTIM_CR2_TCSWU ((uint32_t)0x00000008) /*!< Timer C software update */
+#define HRTIM_CR2_TDSWU ((uint32_t)0x00000010) /*!< Timer D software update */
+#define HRTIM_CR2_TESWU ((uint32_t)0x00000020) /*!< Timer E software update */
+#define HRTIM_CR2_MRST ((uint32_t)0x00000100) /*!< Master count software reset */
+#define HRTIM_CR2_TARST ((uint32_t)0x00000200) /*!< Timer A count software reset */
+#define HRTIM_CR2_TBRST ((uint32_t)0x00000400) /*!< Timer B count software reset */
+#define HRTIM_CR2_TCRST ((uint32_t)0x00000800) /*!< Timer C count software reset */
+#define HRTIM_CR2_TDRST ((uint32_t)0x00001000) /*!< Timer D count software reset */
+#define HRTIM_CR2_TERST ((uint32_t)0x00002000) /*!< Timer E count software reset */
+
+/**** Bit definition for Common HRTIM Timer interrupt status register *********/
+#define HRTIM_ISR_FLT1 ((uint32_t)0x00000001) /*!< Fault 1 interrupt flag */
+#define HRTIM_ISR_FLT2 ((uint32_t)0x00000002) /*!< Fault 2 interrupt flag */
+#define HRTIM_ISR_FLT3 ((uint32_t)0x00000004) /*!< Fault 3 interrupt flag */
+#define HRTIM_ISR_FLT4 ((uint32_t)0x00000008) /*!< Fault 4 interrupt flag */
+#define HRTIM_ISR_FLT5 ((uint32_t)0x00000010) /*!< Fault 5 interrupt flag */
+#define HRTIM_ISR_SYSFLT ((uint32_t)0x00000020) /*!< System Fault interrupt flag */
+#define HRTIM_ISR_DLLRDY ((uint32_t)0x00010000) /*!< DLL ready interrupt flag */
+#define HRTIM_ISR_BMPER ((uint32_t)0x00020000) /*!< Burst mode period interrupt flag */
+
+/**** Bit definition for Common HRTIM Timer interrupt clear register **********/
+#define HRTIM_ICR_FLT1C ((uint32_t)0x00000001) /*!< Fault 1 interrupt flag clear */
+#define HRTIM_ICR_FLT2C ((uint32_t)0x00000002) /*!< Fault 2 interrupt flag clear */
+#define HRTIM_ICR_FLT3C ((uint32_t)0x00000004) /*!< Fault 3 interrupt flag clear */
+#define HRTIM_ICR_FLT4C ((uint32_t)0x00000008) /*!< Fault 4 interrupt flag clear */
+#define HRTIM_ICR_FLT5C ((uint32_t)0x00000010) /*!< Fault 5 interrupt flag clear */
+#define HRTIM_ICR_SYSFLTC ((uint32_t)0x00000020) /*!< System Fault interrupt flag clear */
+#define HRTIM_ICR_DLLRDYC ((uint32_t)0x00010000) /*!< DLL ready interrupt flag clear */
+#define HRTIM_ICR_BMPERC ((uint32_t)0x00020000) /*!< Burst mode period interrupt flag clear */
+
+/**** Bit definition for Common HRTIM Timer interrupt enable register *********/
+#define HRTIM_IER_FLT1 ((uint32_t)0x00000001) /*!< Fault 1 interrupt enable */
+#define HRTIM_IER_FLT2 ((uint32_t)0x00000002) /*!< Fault 2 interrupt enable */
+#define HRTIM_IER_FLT3 ((uint32_t)0x00000004) /*!< Fault 3 interrupt enable */
+#define HRTIM_IER_FLT4 ((uint32_t)0x00000008) /*!< Fault 4 interrupt enable */
+#define HRTIM_IER_FLT5 ((uint32_t)0x00000010) /*!< Fault 5 interrupt enable */
+#define HRTIM_IER_SYSFLT ((uint32_t)0x00000020) /*!< System Fault interrupt enable */
+#define HRTIM_IER_DLLRDY ((uint32_t)0x00010000) /*!< DLL ready interrupt enable */
+#define HRTIM_IER_BMPER ((uint32_t)0x00020000) /*!< Burst mode period interrupt enable */
+
+/**** Bit definition for Common HRTIM Timer output enable register ************/
+#define HRTIM_OENR_TA1OEN ((uint32_t)0x00000001) /*!< Timer A Output 1 enable */
+#define HRTIM_OENR_TA2OEN ((uint32_t)0x00000002) /*!< Timer A Output 2 enable */
+#define HRTIM_OENR_TB1OEN ((uint32_t)0x00000004) /*!< Timer B Output 1 enable */
+#define HRTIM_OENR_TB2OEN ((uint32_t)0x00000008) /*!< Timer B Output 2 enable */
+#define HRTIM_OENR_TC1OEN ((uint32_t)0x00000010) /*!< Timer C Output 1 enable */
+#define HRTIM_OENR_TC2OEN ((uint32_t)0x00000020) /*!< Timer C Output 2 enable */
+#define HRTIM_OENR_TD1OEN ((uint32_t)0x00000040) /*!< Timer D Output 1 enable */
+#define HRTIM_OENR_TD2OEN ((uint32_t)0x00000080) /*!< Timer D Output 2 enable */
+#define HRTIM_OENR_TE1OEN ((uint32_t)0x00000100) /*!< Timer E Output 1 enable */
+#define HRTIM_OENR_TE2OEN ((uint32_t)0x00000200) /*!< Timer E Output 2 enable */
+
+/**** Bit definition for Common HRTIM Timer output disable register ***********/
+#define HRTIM_ODISR_TA1ODIS ((uint32_t)0x00000001) /*!< Timer A Output 1 disable */
+#define HRTIM_ODISR_TA2ODIS ((uint32_t)0x00000002) /*!< Timer A Output 2 disable */
+#define HRTIM_ODISR_TB1ODIS ((uint32_t)0x00000004) /*!< Timer B Output 1 disable */
+#define HRTIM_ODISR_TB2ODIS ((uint32_t)0x00000008) /*!< Timer B Output 2 disable */
+#define HRTIM_ODISR_TC1ODIS ((uint32_t)0x00000010) /*!< Timer C Output 1 disable */
+#define HRTIM_ODISR_TC2ODIS ((uint32_t)0x00000020) /*!< Timer C Output 2 disable */
+#define HRTIM_ODISR_TD1ODIS ((uint32_t)0x00000040) /*!< Timer D Output 1 disable */
+#define HRTIM_ODISR_TD2ODIS ((uint32_t)0x00000080) /*!< Timer D Output 2 disable */
+#define HRTIM_ODISR_TE1ODIS ((uint32_t)0x00000100) /*!< Timer E Output 1 disable */
+#define HRTIM_ODISR_TE2ODIS ((uint32_t)0x00000200) /*!< Timer E Output 2 disable */
+
+/**** Bit definition for Common HRTIM Timer output disable status register *****/
+#define HRTIM_ODSR_TA1ODS ((uint32_t)0x00000001) /*!< Timer A Output 1 disable status */
+#define HRTIM_ODSR_TA2ODS ((uint32_t)0x00000002) /*!< Timer A Output 2 disable status */
+#define HRTIM_ODSR_TB1ODS ((uint32_t)0x00000004) /*!< Timer B Output 1 disable status */
+#define HRTIM_ODSR_TB2ODS ((uint32_t)0x00000008) /*!< Timer B Output 2 disable status */
+#define HRTIM_ODSR_TC1ODS ((uint32_t)0x00000010) /*!< Timer C Output 1 disable status */
+#define HRTIM_ODSR_TC2ODS ((uint32_t)0x00000020) /*!< Timer C Output 2 disable status */
+#define HRTIM_ODSR_TD1ODS ((uint32_t)0x00000040) /*!< Timer D Output 1 disable status */
+#define HRTIM_ODSR_TD2ODS ((uint32_t)0x00000080) /*!< Timer D Output 2 disable status */
+#define HRTIM_ODSR_TE1ODS ((uint32_t)0x00000100) /*!< Timer E Output 1 disable status */
+#define HRTIM_ODSR_TE2ODS ((uint32_t)0x00000200) /*!< Timer E Output 2 disable status */
+
+/**** Bit definition for Common HRTIM Timer Burst mode control register ********/
+#define HRTIM_BMCR_BME ((uint32_t)0x00000001) /*!< Burst mode enable */
+#define HRTIM_BMCR_BMOM ((uint32_t)0x00000002) /*!< Burst mode operating mode */
+#define HRTIM_BMCR_BMCLK ((uint32_t)0x0000003C) /*!< Burst mode clock source */
+#define HRTIM_BMCR_BMCLK_0 ((uint32_t)0x00000004) /*!< Burst mode clock source bit 0 */
+#define HRTIM_BMCR_BMCLK_1 ((uint32_t)0x00000008) /*!< Burst mode clock source bit 1 */
+#define HRTIM_BMCR_BMCLK_2 ((uint32_t)0x00000010) /*!< Burst mode clock source bit 2 */
+#define HRTIM_BMCR_BMCLK_3 ((uint32_t)0x00000020) /*!< Burst mode clock source bit 3 */
+#define HRTIM_BMCR_BMPSC ((uint32_t)0x000003C0) /*!< Burst mode prescaler */
+#define HRTIM_BMCR_BMPSC_0 ((uint32_t)0x00000040) /*!< Burst mode prescaler bit 0 */
+#define HRTIM_BMCR_BMPSC_1 ((uint32_t)0x00000080) /*!< Burst mode prescaler bit 1 */
+#define HRTIM_BMCR_BMPSC_2 ((uint32_t)0x00000100) /*!< Burst mode prescaler bit 2 */
+#define HRTIM_BMCR_BMPSC_3 ((uint32_t)0x00000200) /*!< Burst mode prescaler bit 3 */
+#define HRTIM_BMCR_BMPREN ((uint32_t)0x00000400) /*!< Burst mode Preload bit */
+#define HRTIM_BMCR_MTBM ((uint32_t)0x00010000) /*!< Master Timer Burst mode */
+#define HRTIM_BMCR_TABM ((uint32_t)0x00020000) /*!< Timer A Burst mode */
+#define HRTIM_BMCR_TBBM ((uint32_t)0x00040000) /*!< Timer B Burst mode */
+#define HRTIM_BMCR_TCBM ((uint32_t)0x00080000) /*!< Timer C Burst mode */
+#define HRTIM_BMCR_TDBM ((uint32_t)0x00100000) /*!< Timer D Burst mode */
+#define HRTIM_BMCR_TEBM ((uint32_t)0x00200000) /*!< Timer E Burst mode */
+#define HRTIM_BMCR_BMSTAT ((uint32_t)0x80000000) /*!< Burst mode status */
+
+/**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/
+#define HRTIM_BMTRGR_SW ((uint32_t)0x00000001) /*!< Software start */
+#define HRTIM_BMTRGR_MSTRST ((uint32_t)0x00000002) /*!< Master reset */
+#define HRTIM_BMTRGR_MSTREP ((uint32_t)0x00000004) /*!< Master repetition */
+#define HRTIM_BMTRGR_MSTCMP1 ((uint32_t)0x00000008) /*!< Master compare 1 */
+#define HRTIM_BMTRGR_MSTCMP2 ((uint32_t)0x00000010) /*!< Master compare 2 */
+#define HRTIM_BMTRGR_MSTCMP3 ((uint32_t)0x00000020) /*!< Master compare 3 */
+#define HRTIM_BMTRGR_MSTCMP4 ((uint32_t)0x00000040) /*!< Master compare 4 */
+#define HRTIM_BMTRGR_TARST ((uint32_t)0x00000080) /*!< Timer A reset */
+#define HRTIM_BMTRGR_TAREP ((uint32_t)0x00000100) /*!< Timer A repetition */
+#define HRTIM_BMTRGR_TACMP1 ((uint32_t)0x00000200) /*!< Timer A compare 1 */
+#define HRTIM_BMTRGR_TACMP2 ((uint32_t)0x00000400) /*!< Timer A compare 2 */
+#define HRTIM_BMTRGR_TBRST ((uint32_t)0x00000800) /*!< Timer B reset */
+#define HRTIM_BMTRGR_TBREP ((uint32_t)0x00001000) /*!< Timer B repetition */
+#define HRTIM_BMTRGR_TBCMP1 ((uint32_t)0x00002000) /*!< Timer B compare 1 */
+#define HRTIM_BMTRGR_TBCMP2 ((uint32_t)0x00004000) /*!< Timer B compare 2 */
+#define HRTIM_BMTRGR_TCRST ((uint32_t)0x00008000) /*!< Timer C reset */
+#define HRTIM_BMTRGR_TCREP ((uint32_t)0x00010000) /*!< Timer C repetition */
+#define HRTIM_BMTRGR_TCCMP1 ((uint32_t)0x00020000) /*!< Timer C compare 1 */
+#define HRTIM_BMTRGR_TCCMP2 ((uint32_t)0x00040000) /*!< Timer C compare 2 */
+#define HRTIM_BMTRGR_TDRST ((uint32_t)0x00080000) /*!< Timer D reset */
+#define HRTIM_BMTRGR_TDREP ((uint32_t)0x00100000) /*!< Timer D repetition */
+#define HRTIM_BMTRGR_TDCMP1 ((uint32_t)0x00200000) /*!< Timer D compare 1 */
+#define HRTIM_BMTRGR_TDCMP2 ((uint32_t)0x00400000) /*!< Timer D compare 2 */
+#define HRTIM_BMTRGR_TERST ((uint32_t)0x00800000) /*!< Timer E reset */
+#define HRTIM_BMTRGR_TEREP ((uint32_t)0x01000000) /*!< Timer E repetition */
+#define HRTIM_BMTRGR_TECMP1 ((uint32_t)0x02000000) /*!< Timer E compare 1 */
+#define HRTIM_BMTRGR_TECMP2 ((uint32_t)0x04000000) /*!< Timer E compare 2 */
+#define HRTIM_BMTRGR_TAEEV7 ((uint32_t)0x08000000) /*!< Timer A period following External Event7 */
+#define HRTIM_BMTRGR_TDEEV8 ((uint32_t)0x10000000) /*!< Timer D period following External Event8 */
+#define HRTIM_BMTRGR_EEV7 ((uint32_t)0x20000000) /*!< External Event 7 */
+#define HRTIM_BMTRGR_EEV8 ((uint32_t)0x40000000) /*!< External Event 8 */
+#define HRTIM_BMTRGR_OCHPEV ((uint32_t)0x80000000) /*!< on-chip Event */
+
+/******************* Bit definition for HRTIM_BMCMPR register ***************/
+#define HRTIM_BMCMPR_BMCMPR ((uint32_t)0x0000FFFF) /*!<!<Burst Compare Value */
+
+/******************* Bit definition for HRTIM_BMPER register ****************/
+#define HRTIM_BMPER_BMPER ((uint32_t)0x0000FFFF) /*!<!<Burst period Value */
+
+/******************* Bit definition for HRTIM_EECR1 register ****************/
+#define HRTIM_EECR1_EE1SRC ((uint32_t)0x00000003) /*!< External event 1 source */
+#define HRTIM_EECR1_EE1SRC_0 ((uint32_t)0x00000001) /*!< External event 1 source bit 0 */
+#define HRTIM_EECR1_EE1SRC_1 ((uint32_t)0x00000002) /*!< External event 1 source bit 1 */
+#define HRTIM_EECR1_EE1POL ((uint32_t)0x00000004) /*!< External event 1 Polarity */
+#define HRTIM_EECR1_EE1SNS ((uint32_t)0x00000018) /*!< External event 1 sensitivity */
+#define HRTIM_EECR1_EE1SNS_0 ((uint32_t)0x00000008) /*!< External event 1 sensitivity bit 0 */
+#define HRTIM_EECR1_EE1SNS_1 ((uint32_t)0x00000010) /*!< External event 1 sensitivity bit 1 */
+#define HRTIM_EECR1_EE1FAST ((uint32_t)0x00000020) /*!< External event 1 Fast mode */
+
+#define HRTIM_EECR1_EE2SRC ((uint32_t)0x000000C0) /*!< External event 2 source */
+#define HRTIM_EECR1_EE2SRC_0 ((uint32_t)0x00000040) /*!< External event 2 source bit 0 */
+#define HRTIM_EECR1_EE2SRC_1 ((uint32_t)0x00000080) /*!< External event 2 source bit 1 */
+#define HRTIM_EECR1_EE2POL ((uint32_t)0x00000100) /*!< External event 2 Polarity */
+#define HRTIM_EECR1_EE2SNS ((uint32_t)0x00000600) /*!< External event 2 sensitivity */
+#define HRTIM_EECR1_EE2SNS_0 ((uint32_t)0x00000200) /*!< External event 2 sensitivity bit 0 */
+#define HRTIM_EECR1_EE2SNS_1 ((uint32_t)0x00000400) /*!< External event 2 sensitivity bit 1 */
+#define HRTIM_EECR1_EE2FAST ((uint32_t)0x00000800) /*!< External event 2 Fast mode */
+
+#define HRTIM_EECR1_EE3SRC ((uint32_t)0x00003000) /*!< External event 3 source */
+#define HRTIM_EECR1_EE3SRC_0 ((uint32_t)0x00001000) /*!< External event 3 source bit 0 */
+#define HRTIM_EECR1_EE3SRC_1 ((uint32_t)0x00002000) /*!< External event 3 source bit 1 */
+#define HRTIM_EECR1_EE3POL ((uint32_t)0x00004000) /*!< External event 3 Polarity */
+#define HRTIM_EECR1_EE3SNS ((uint32_t)0x00018000) /*!< External event 3 sensitivity */
+#define HRTIM_EECR1_EE3SNS_0 ((uint32_t)0x00008000) /*!< External event 3 sensitivity bit 0 */
+#define HRTIM_EECR1_EE3SNS_1 ((uint32_t)0x00010000) /*!< External event 3 sensitivity bit 1 */
+#define HRTIM_EECR1_EE3FAST ((uint32_t)0x00020000) /*!< External event 3 Fast mode */
+
+#define HRTIM_EECR1_EE4SRC ((uint32_t)0x000C0000) /*!< External event 4 source */
+#define HRTIM_EECR1_EE4SRC_0 ((uint32_t)0x00040000) /*!< External event 4 source bit 0 */
+#define HRTIM_EECR1_EE4SRC_1 ((uint32_t)0x00080000) /*!< External event 4 source bit 1 */
+#define HRTIM_EECR1_EE4POL ((uint32_t)0x00100000) /*!< External event 4 Polarity */
+#define HRTIM_EECR1_EE4SNS ((uint32_t)0x00600000) /*!< External event 4 sensitivity */
+#define HRTIM_EECR1_EE4SNS_0 ((uint32_t)0x00200000) /*!< External event 4 sensitivity bit 0 */
+#define HRTIM_EECR1_EE4SNS_1 ((uint32_t)0x00400000) /*!< External event 4 sensitivity bit 1 */
+#define HRTIM_EECR1_EE4FAST ((uint32_t)0x00800000) /*!< External event 4 Fast mode */
+
+#define HRTIM_EECR1_EE5SRC ((uint32_t)0x03000000) /*!< External event 5 source */
+#define HRTIM_EECR1_EE5SRC_0 ((uint32_t)0x01000000) /*!< External event 5 source bit 0 */
+#define HRTIM_EECR1_EE5SRC_1 ((uint32_t)0x02000000) /*!< External event 5 source bit 1 */
+#define HRTIM_EECR1_EE5POL ((uint32_t)0x04000000) /*!< External event 5 Polarity */
+#define HRTIM_EECR1_EE5SNS ((uint32_t)0x18000000) /*!< External event 5 sensitivity */
+#define HRTIM_EECR1_EE5SNS_0 ((uint32_t)0x08000000) /*!< External event 5 sensitivity bit 0 */
+#define HRTIM_EECR1_EE5SNS_1 ((uint32_t)0x10000000) /*!< External event 5 sensitivity bit 1 */
+#define HRTIM_EECR1_EE5FAST ((uint32_t)0x20000000) /*!< External event 5 Fast mode */
+
+/******************* Bit definition for HRTIM_EECR2 register ****************/
+#define HRTIM_EECR2_EE6SRC ((uint32_t)0x00000003) /*!< External event 6 source */
+#define HRTIM_EECR2_EE6SRC_0 ((uint32_t)0x00000001) /*!< External event 6 source bit 0 */
+#define HRTIM_EECR2_EE6SRC_1 ((uint32_t)0x00000002) /*!< External event 6 source bit 1 */
+#define HRTIM_EECR2_EE6POL ((uint32_t)0x00000004) /*!< External event 6 Polarity */
+#define HRTIM_EECR2_EE6SNS ((uint32_t)0x00000018) /*!< External event 6 sensitivity */
+#define HRTIM_EECR2_EE6SNS_0 ((uint32_t)0x00000008) /*!< External event 6 sensitivity bit 0 */
+#define HRTIM_EECR2_EE6SNS_1 ((uint32_t)0x00000010) /*!< External event 6 sensitivity bit 1 */
+
+#define HRTIM_EECR2_EE7SRC ((uint32_t)0x000000C0) /*!< External event 7 source */
+#define HRTIM_EECR2_EE7SRC_0 ((uint32_t)0x00000040) /*!< External event 7 source bit 0 */
+#define HRTIM_EECR2_EE7SRC_1 ((uint32_t)0x00000080) /*!< External event 7 source bit 1 */
+#define HRTIM_EECR2_EE7POL ((uint32_t)0x00000100) /*!< External event 7 Polarity */
+#define HRTIM_EECR2_EE7SNS ((uint32_t)0x00000600) /*!< External event 7 sensitivity */
+#define HRTIM_EECR2_EE7SNS_0 ((uint32_t)0x00000200) /*!< External event 7 sensitivity bit 0 */
+#define HRTIM_EECR2_EE7SNS_1 ((uint32_t)0x00000400) /*!< External event 7 sensitivity bit 1 */
+
+#define HRTIM_EECR2_EE8SRC ((uint32_t)0x00003000) /*!< External event 8 source */
+#define HRTIM_EECR2_EE8SRC_0 ((uint32_t)0x00001000) /*!< External event 8 source bit 0 */
+#define HRTIM_EECR2_EE8SRC_1 ((uint32_t)0x00002000) /*!< External event 8 source bit 1 */
+#define HRTIM_EECR2_EE8POL ((uint32_t)0x00004000) /*!< External event 8 Polarity */
+#define HRTIM_EECR2_EE8SNS ((uint32_t)0x00018000) /*!< External event 8 sensitivity */
+#define HRTIM_EECR2_EE8SNS_0 ((uint32_t)0x00008000) /*!< External event 8 sensitivity bit 0 */
+#define HRTIM_EECR2_EE8SNS_1 ((uint32_t)0x00010000) /*!< External event 8 sensitivity bit 1 */
+
+#define HRTIM_EECR2_EE9SRC ((uint32_t)0x000C0000) /*!< External event 9 source */
+#define HRTIM_EECR2_EE9SRC_0 ((uint32_t)0x00040000) /*!< External event 9 source bit 0 */
+#define HRTIM_EECR2_EE9SRC_1 ((uint32_t)0x00080000) /*!< External event 9 source bit 1 */
+#define HRTIM_EECR2_EE9POL ((uint32_t)0x00100000) /*!< External event 9 Polarity */
+#define HRTIM_EECR2_EE9SNS ((uint32_t)0x00600000) /*!< External event 9 sensitivity */
+#define HRTIM_EECR2_EE9SNS_0 ((uint32_t)0x00200000) /*!< External event 9 sensitivity bit 0 */
+#define HRTIM_EECR2_EE9SNS_1 ((uint32_t)0x00400000) /*!< External event 9 sensitivity bit 1 */
+
+#define HRTIM_EECR2_EE10SRC ((uint32_t)0x03000000) /*!< External event 10 source */
+#define HRTIM_EECR2_EE10SRC_0 ((uint32_t)0x01000000) /*!< External event 10 source bit 0 */
+#define HRTIM_EECR2_EE10SRC_1 ((uint32_t)0x02000000) /*!< External event 10 source bit 1 */
+#define HRTIM_EECR2_EE10POL ((uint32_t)0x04000000) /*!< External event 10 Polarity */
+#define HRTIM_EECR2_EE10SNS ((uint32_t)0x18000000) /*!< External event 10 sensitivity */
+#define HRTIM_EECR2_EE10SNS_0 ((uint32_t)0x08000000) /*!< External event 10 sensitivity bit 0 */
+#define HRTIM_EECR2_EE10SNS_1 ((uint32_t)0x10000000) /*!< External event 10 sensitivity bit 1 */
+
+/******************* Bit definition for HRTIM_EECR3 register ****************/
+#define HRTIM_EECR3_EE6F ((uint32_t)0x0000000F) /*!< External event 6 filter */
+#define HRTIM_EECR3_EE6F_0 ((uint32_t)0x00000001) /*!< External event 6 filter bit 0 */
+#define HRTIM_EECR3_EE6F_1 ((uint32_t)0x00000002) /*!< External event 6 filter bit 1 */
+#define HRTIM_EECR3_EE6F_2 ((uint32_t)0x00000004) /*!< External event 6 filter bit 2 */
+#define HRTIM_EECR3_EE6F_3 ((uint32_t)0x00000008) /*!< External event 6 filter bit 3 */
+#define HRTIM_EECR3_EE7F ((uint32_t)0x000003C0) /*!< External event 7 filter */
+#define HRTIM_EECR3_EE7F_0 ((uint32_t)0x00000040) /*!< External event 7 filter bit 0 */
+#define HRTIM_EECR3_EE7F_1 ((uint32_t)0x00000080) /*!< External event 7 filter bit 1 */
+#define HRTIM_EECR3_EE7F_2 ((uint32_t)0x00000100) /*!< External event 7 filter bit 2 */
+#define HRTIM_EECR3_EE7F_3 ((uint32_t)0x00000200) /*!< External event 7 filter bit 3 */
+#define HRTIM_EECR3_EE8F ((uint32_t)0x0000F000) /*!< External event 8 filter */
+#define HRTIM_EECR3_EE8F_0 ((uint32_t)0x00001000) /*!< External event 8 filter bit 0 */
+#define HRTIM_EECR3_EE8F_1 ((uint32_t)0x00002000) /*!< External event 8 filter bit 1 */
+#define HRTIM_EECR3_EE8F_2 ((uint32_t)0x00004000) /*!< External event 8 filter bit 2 */
+#define HRTIM_EECR3_EE8F_3 ((uint32_t)0x00008000) /*!< External event 8 filter bit 3 */
+#define HRTIM_EECR3_EE9F ((uint32_t)0x003C0000) /*!< External event 9 filter */
+#define HRTIM_EECR3_EE9F_0 ((uint32_t)0x00040000) /*!< External event 9 filter bit 0 */
+#define HRTIM_EECR3_EE9F_1 ((uint32_t)0x00080000) /*!< External event 9 filter bit 1 */
+#define HRTIM_EECR3_EE9F_2 ((uint32_t)0x00100000) /*!< External event 9 filter bit 2 */
+#define HRTIM_EECR3_EE9F_3 ((uint32_t)0x00200000) /*!< External event 9 filter bit 3 */
+#define HRTIM_EECR3_EE10F ((uint32_t)0x0F000000) /*!< External event 10 filter */
+#define HRTIM_EECR3_EE10F_0 ((uint32_t)0x01000000) /*!< External event 10 filter bit 0 */
+#define HRTIM_EECR3_EE10F_1 ((uint32_t)0x02000000) /*!< External event 10 filter bit 1 */
+#define HRTIM_EECR3_EE10F_2 ((uint32_t)0x04000000) /*!< External event 10 filter bit 2 */
+#define HRTIM_EECR3_EE10F_3 ((uint32_t)0x08000000) /*!< External event 10 filter bit 3 */
+#define HRTIM_EECR3_EEVSD ((uint32_t)0xC0000000) /*!< External event sampling clock division */
+#define HRTIM_EECR3_EEVSD_0 ((uint32_t)0x40000000) /*!< External event sampling clock division bit 0 */
+#define HRTIM_EECR3_EEVSD_1 ((uint32_t)0x80000000) /*!< External event sampling clock division bit 1 */
+
+/******************* Bit definition for HRTIM_ADC1R register ****************/
+#define HRTIM_ADC1R_AD1MC1 ((uint32_t)0x00000001) /*!< ADC Trigger 1 on master compare 1 */
+#define HRTIM_ADC1R_AD1MC2 ((uint32_t)0x00000002) /*!< ADC Trigger 1 on master compare 2 */
+#define HRTIM_ADC1R_AD1MC3 ((uint32_t)0x00000004) /*!< ADC Trigger 1 on master compare 3 */
+#define HRTIM_ADC1R_AD1MC4 ((uint32_t)0x00000008) /*!< ADC Trigger 1 on master compare 4 */
+#define HRTIM_ADC1R_AD1MPER ((uint32_t)0x00000010) /*!< ADC Trigger 1 on master period */
+#define HRTIM_ADC1R_AD1EEV1 ((uint32_t)0x00000020) /*!< ADC Trigger 1 on external event 1 */
+#define HRTIM_ADC1R_AD1EEV2 ((uint32_t)0x00000040) /*!< ADC Trigger 1 on external event 2 */
+#define HRTIM_ADC1R_AD1EEV3 ((uint32_t)0x00000080) /*!< ADC Trigger 1 on external event 3 */
+#define HRTIM_ADC1R_AD1EEV4 ((uint32_t)0x00000100) /*!< ADC Trigger 1 on external event 4 */
+#define HRTIM_ADC1R_AD1EEV5 ((uint32_t)0x00000200) /*!< ADC Trigger 1 on external event 5 */
+#define HRTIM_ADC1R_AD1TAC2 ((uint32_t)0x00000400) /*!< ADC Trigger 1 on Timer A compare 2 */
+#define HRTIM_ADC1R_AD1TAC3 ((uint32_t)0x00000800) /*!< ADC Trigger 1 on Timer A compare 3 */
+#define HRTIM_ADC1R_AD1TAC4 ((uint32_t)0x00001000) /*!< ADC Trigger 1 on Timer A compare 4 */
+#define HRTIM_ADC1R_AD1TAPER ((uint32_t)0x00002000) /*!< ADC Trigger 1 on Timer A period */
+#define HRTIM_ADC1R_AD1TARST ((uint32_t)0x00004000) /*!< ADC Trigger 1 on Timer A reset */
+#define HRTIM_ADC1R_AD1TBC2 ((uint32_t)0x00008000) /*!< ADC Trigger 1 on Timer B compare 2 */
+#define HRTIM_ADC1R_AD1TBC3 ((uint32_t)0x00010000) /*!< ADC Trigger 1 on Timer B compare 3 */
+#define HRTIM_ADC1R_AD1TBC4 ((uint32_t)0x00020000) /*!< ADC Trigger 1 on Timer B compare 4 */
+#define HRTIM_ADC1R_AD1TBPER ((uint32_t)0x00040000) /*!< ADC Trigger 1 on Timer B period */
+#define HRTIM_ADC1R_AD1TBRST ((uint32_t)0x00080000) /*!< ADC Trigger 1 on Timer B reset */
+#define HRTIM_ADC1R_AD1TCC2 ((uint32_t)0x00100000) /*!< ADC Trigger 1 on Timer C compare 2 */
+#define HRTIM_ADC1R_AD1TCC3 ((uint32_t)0x00200000) /*!< ADC Trigger 1 on Timer C compare 3 */
+#define HRTIM_ADC1R_AD1TCC4 ((uint32_t)0x00400000) /*!< ADC Trigger 1 on Timer C compare 4 */
+#define HRTIM_ADC1R_AD1TCPER ((uint32_t)0x00800000) /*!< ADC Trigger 1 on Timer C period */
+#define HRTIM_ADC1R_AD1TDC2 ((uint32_t)0x01000000) /*!< ADC Trigger 1 on Timer D compare 2 */
+#define HRTIM_ADC1R_AD1TDC3 ((uint32_t)0x02000000) /*!< ADC Trigger 1 on Timer D compare 3 */
+#define HRTIM_ADC1R_AD1TDC4 ((uint32_t)0x04000000) /*!< ADC Trigger 1 on Timer D compare 4 */
+#define HRTIM_ADC1R_AD1TDPER ((uint32_t)0x08000000) /*!< ADC Trigger 1 on Timer D period */
+#define HRTIM_ADC1R_AD1TEC2 ((uint32_t)0x10000000) /*!< ADC Trigger 1 on Timer E compare 2 */
+#define HRTIM_ADC1R_AD1TEC3 ((uint32_t)0x20000000) /*!< ADC Trigger 1 on Timer E compare 3 */
+#define HRTIM_ADC1R_AD1TEC4 ((uint32_t)0x40000000) /*!< ADC Trigger 1 on Timer E compare 4 */
+#define HRTIM_ADC1R_AD1TEPER ((uint32_t)0x80000000) /*!< ADC Trigger 1 on Timer E period */
+
+/******************* Bit definition for HRTIM_ADC2R register ****************/
+#define HRTIM_ADC2R_AD2MC1 ((uint32_t)0x00000001) /*!< ADC Trigger 2 on master compare 1 */
+#define HRTIM_ADC2R_AD2MC2 ((uint32_t)0x00000002) /*!< ADC Trigger 2 on master compare 2 */
+#define HRTIM_ADC2R_AD2MC3 ((uint32_t)0x00000004) /*!< ADC Trigger 2 on master compare 3 */
+#define HRTIM_ADC2R_AD2MC4 ((uint32_t)0x00000008) /*!< ADC Trigger 2 on master compare 4 */
+#define HRTIM_ADC2R_AD2MPER ((uint32_t)0x00000010) /*!< ADC Trigger 2 on master period */
+#define HRTIM_ADC2R_AD2EEV6 ((uint32_t)0x00000020) /*!< ADC Trigger 2 on external event 6 */
+#define HRTIM_ADC2R_AD2EEV7 ((uint32_t)0x00000040) /*!< ADC Trigger 2 on external event 7 */
+#define HRTIM_ADC2R_AD2EEV8 ((uint32_t)0x00000080) /*!< ADC Trigger 2 on external event 8 */
+#define HRTIM_ADC2R_AD2EEV9 ((uint32_t)0x00000100) /*!< ADC Trigger 2 on external event 9 */
+#define HRTIM_ADC2R_AD2EEV10 ((uint32_t)0x00000200) /*!< ADC Trigger 2 on external event 10 */
+#define HRTIM_ADC2R_AD2TAC2 ((uint32_t)0x00000400) /*!< ADC Trigger 2 on Timer A compare 2 */
+#define HRTIM_ADC2R_AD2TAC3 ((uint32_t)0x00000800) /*!< ADC Trigger 2 on Timer A compare 3 */
+#define HRTIM_ADC2R_AD2TAC4 ((uint32_t)0x00001000) /*!< ADC Trigger 2 on Timer A compare 4*/
+#define HRTIM_ADC2R_AD2TAPER ((uint32_t)0x00002000) /*!< ADC Trigger 2 on Timer A period */
+#define HRTIM_ADC2R_AD2TBC2 ((uint32_t)0x00004000) /*!< ADC Trigger 2 on Timer B compare 2 */
+#define HRTIM_ADC2R_AD2TBC3 ((uint32_t)0x00008000) /*!< ADC Trigger 2 on Timer B compare 3 */
+#define HRTIM_ADC2R_AD2TBC4 ((uint32_t)0x00010000) /*!< ADC Trigger 2 on Timer B compare 4 */
+#define HRTIM_ADC2R_AD2TBPER ((uint32_t)0x00020000) /*!< ADC Trigger 2 on Timer B period */
+#define HRTIM_ADC2R_AD2TCC2 ((uint32_t)0x00040000) /*!< ADC Trigger 2 on Timer C compare 2 */
+#define HRTIM_ADC2R_AD2TCC3 ((uint32_t)0x00080000) /*!< ADC Trigger 2 on Timer C compare 3 */
+#define HRTIM_ADC2R_AD2TCC4 ((uint32_t)0x00100000) /*!< ADC Trigger 2 on Timer C compare 4 */
+#define HRTIM_ADC2R_AD2TCPER ((uint32_t)0x00200000) /*!< ADC Trigger 2 on Timer C period */
+#define HRTIM_ADC2R_AD2TCRST ((uint32_t)0x00400000) /*!< ADC Trigger 2 on Timer C reset */
+#define HRTIM_ADC2R_AD2TDC2 ((uint32_t)0x00800000) /*!< ADC Trigger 2 on Timer D compare 2 */
+#define HRTIM_ADC2R_AD2TDC3 ((uint32_t)0x01000000) /*!< ADC Trigger 2 on Timer D compare 3 */
+#define HRTIM_ADC2R_AD2TDC4 ((uint32_t)0x02000000) /*!< ADC Trigger 2 on Timer D compare 4*/
+#define HRTIM_ADC2R_AD2TDPER ((uint32_t)0x04000000) /*!< ADC Trigger 2 on Timer D period */
+#define HRTIM_ADC2R_AD2TDRST ((uint32_t)0x08000000) /*!< ADC Trigger 2 on Timer D reset */
+#define HRTIM_ADC2R_AD2TEC2 ((uint32_t)0x10000000) /*!< ADC Trigger 2 on Timer E compare 2 */
+#define HRTIM_ADC2R_AD2TEC3 ((uint32_t)0x20000000) /*!< ADC Trigger 2 on Timer E compare 3 */
+#define HRTIM_ADC2R_AD2TEC4 ((uint32_t)0x40000000) /*!< ADC Trigger 2 on Timer E compare 4 */
+#define HRTIM_ADC2R_AD2TERST ((uint32_t)0x80000000) /*!< ADC Trigger 2 on Timer E reset */
+
+/******************* Bit definition for HRTIM_ADC3R register ****************/
+#define HRTIM_ADC3R_AD3MC1 ((uint32_t)0x00000001) /*!< ADC Trigger 3 on master compare 1 */
+#define HRTIM_ADC3R_AD3MC2 ((uint32_t)0x00000002) /*!< ADC Trigger 3 on master compare 2 */
+#define HRTIM_ADC3R_AD3MC3 ((uint32_t)0x00000004) /*!< ADC Trigger 3 on master compare 3 */
+#define HRTIM_ADC3R_AD3MC4 ((uint32_t)0x00000008) /*!< ADC Trigger 3 on master compare 4 */
+#define HRTIM_ADC3R_AD3MPER ((uint32_t)0x00000010) /*!< ADC Trigger 3 on master period */
+#define HRTIM_ADC3R_AD3EEV1 ((uint32_t)0x00000020) /*!< ADC Trigger 3 on external event 1 */
+#define HRTIM_ADC3R_AD3EEV2 ((uint32_t)0x00000040) /*!< ADC Trigger 3 on external event 2 */
+#define HRTIM_ADC3R_AD3EEV3 ((uint32_t)0x00000080) /*!< ADC Trigger 3 on external event 3 */
+#define HRTIM_ADC3R_AD3EEV4 ((uint32_t)0x00000100) /*!< ADC Trigger 3 on external event 4 */
+#define HRTIM_ADC3R_AD3EEV5 ((uint32_t)0x00000200) /*!< ADC Trigger 3 on external event 5 */
+#define HRTIM_ADC3R_AD3TAC2 ((uint32_t)0x00000400) /*!< ADC Trigger 3 on Timer A compare 2 */
+#define HRTIM_ADC3R_AD3TAC3 ((uint32_t)0x00000800) /*!< ADC Trigger 3 on Timer A compare 3 */
+#define HRTIM_ADC3R_AD3TAC4 ((uint32_t)0x00001000) /*!< ADC Trigger 3 on Timer A compare 4 */
+#define HRTIM_ADC3R_AD3TAPER ((uint32_t)0x00002000) /*!< ADC Trigger 3 on Timer A period */
+#define HRTIM_ADC3R_AD3TARST ((uint32_t)0x00004000) /*!< ADC Trigger 3 on Timer A reset */
+#define HRTIM_ADC3R_AD3TBC2 ((uint32_t)0x00008000) /*!< ADC Trigger 3 on Timer B compare 2 */
+#define HRTIM_ADC3R_AD3TBC3 ((uint32_t)0x00010000) /*!< ADC Trigger 3 on Timer B compare 3 */
+#define HRTIM_ADC3R_AD3TBC4 ((uint32_t)0x00020000) /*!< ADC Trigger 3 on Timer B compare 4 */
+#define HRTIM_ADC3R_AD3TBPER ((uint32_t)0x00040000) /*!< ADC Trigger 3 on Timer B period */
+#define HRTIM_ADC3R_AD3TBRST ((uint32_t)0x00080000) /*!< ADC Trigger 3 on Timer B reset */
+#define HRTIM_ADC3R_AD3TCC2 ((uint32_t)0x00100000) /*!< ADC Trigger 3 on Timer C compare 2 */
+#define HRTIM_ADC3R_AD3TCC3 ((uint32_t)0x00200000) /*!< ADC Trigger 3 on Timer C compare 3 */
+#define HRTIM_ADC3R_AD3TCC4 ((uint32_t)0x00400000) /*!< ADC Trigger 3 on Timer C compare 4 */
+#define HRTIM_ADC3R_AD3TCPER ((uint32_t)0x00800000) /*!< ADC Trigger 3 on Timer C period */
+#define HRTIM_ADC3R_AD3TDC2 ((uint32_t)0x01000000) /*!< ADC Trigger 3 on Timer D compare 2 */
+#define HRTIM_ADC3R_AD3TDC3 ((uint32_t)0x02000000) /*!< ADC Trigger 3 on Timer D compare 3 */
+#define HRTIM_ADC3R_AD3TDC4 ((uint32_t)0x04000000) /*!< ADC Trigger 3 on Timer D compare 4 */
+#define HRTIM_ADC3R_AD3TDPER ((uint32_t)0x08000000) /*!< ADC Trigger 3 on Timer D period */
+#define HRTIM_ADC3R_AD3TEC2 ((uint32_t)0x10000000) /*!< ADC Trigger 3 on Timer E compare 2 */
+#define HRTIM_ADC3R_AD3TEC3 ((uint32_t)0x20000000) /*!< ADC Trigger 3 on Timer E compare 3 */
+#define HRTIM_ADC3R_AD3TEC4 ((uint32_t)0x40000000) /*!< ADC Trigger 3 on Timer E compare 4 */
+#define HRTIM_ADC3R_AD3TEPER ((uint32_t)0x80000000) /*!< ADC Trigger 3 on Timer E period */
+
+/******************* Bit definition for HRTIM_ADC4R register ****************/
+#define HRTIM_ADC4R_AD4MC1 ((uint32_t)0x00000001) /*!< ADC Trigger 4 on master compare 1 */
+#define HRTIM_ADC4R_AD4MC2 ((uint32_t)0x00000002) /*!< ADC Trigger 4 on master compare 2 */
+#define HRTIM_ADC4R_AD4MC3 ((uint32_t)0x00000004) /*!< ADC Trigger 4 on master compare 3 */
+#define HRTIM_ADC4R_AD4MC4 ((uint32_t)0x00000008) /*!< ADC Trigger 4 on master compare 4 */
+#define HRTIM_ADC4R_AD4MPER ((uint32_t)0x00000010) /*!< ADC Trigger 4 on master period */
+#define HRTIM_ADC4R_AD4EEV6 ((uint32_t)0x00000020) /*!< ADC Trigger 4 on external event 6 */
+#define HRTIM_ADC4R_AD4EEV7 ((uint32_t)0x00000040) /*!< ADC Trigger 4 on external event 7 */
+#define HRTIM_ADC4R_AD4EEV8 ((uint32_t)0x00000080) /*!< ADC Trigger 4 on external event 8 */
+#define HRTIM_ADC4R_AD4EEV9 ((uint32_t)0x00000100) /*!< ADC Trigger 4 on external event 9 */
+#define HRTIM_ADC4R_AD4EEV10 ((uint32_t)0x00000200) /*!< ADC Trigger 4 on external event 10 */
+#define HRTIM_ADC4R_AD4TAC2 ((uint32_t)0x00000400) /*!< ADC Trigger 4 on Timer A compare 2 */
+#define HRTIM_ADC4R_AD4TAC3 ((uint32_t)0x00000800) /*!< ADC Trigger 4 on Timer A compare 3 */
+#define HRTIM_ADC4R_AD4TAC4 ((uint32_t)0x00001000) /*!< ADC Trigger 4 on Timer A compare 4*/
+#define HRTIM_ADC4R_AD4TAPER ((uint32_t)0x00002000) /*!< ADC Trigger 4 on Timer A period */
+#define HRTIM_ADC4R_AD4TBC2 ((uint32_t)0x00004000) /*!< ADC Trigger 4 on Timer B compare 2 */
+#define HRTIM_ADC4R_AD4TBC3 ((uint32_t)0x00008000) /*!< ADC Trigger 4 on Timer B compare 3 */
+#define HRTIM_ADC4R_AD4TBC4 ((uint32_t)0x00010000) /*!< ADC Trigger 4 on Timer B compare 4 */
+#define HRTIM_ADC4R_AD4TBPER ((uint32_t)0x00020000) /*!< ADC Trigger 4 on Timer B period */
+#define HRTIM_ADC4R_AD4TCC2 ((uint32_t)0x00040000) /*!< ADC Trigger 4 on Timer C compare 2 */
+#define HRTIM_ADC4R_AD4TCC3 ((uint32_t)0x00080000) /*!< ADC Trigger 4 on Timer C compare 3 */
+#define HRTIM_ADC4R_AD4TCC4 ((uint32_t)0x00100000) /*!< ADC Trigger 4 on Timer C compare 4 */
+#define HRTIM_ADC4R_AD4TCPER ((uint32_t)0x00200000) /*!< ADC Trigger 4 on Timer C period */
+#define HRTIM_ADC4R_AD4TCRST ((uint32_t)0x00400000) /*!< ADC Trigger 4 on Timer C reset */
+#define HRTIM_ADC4R_AD4TDC2 ((uint32_t)0x00800000) /*!< ADC Trigger 4 on Timer D compare 2 */
+#define HRTIM_ADC4R_AD4TDC3 ((uint32_t)0x01000000) /*!< ADC Trigger 4 on Timer D compare 3 */
+#define HRTIM_ADC4R_AD4TDC4 ((uint32_t)0x02000000) /*!< ADC Trigger 4 on Timer D compare 4*/
+#define HRTIM_ADC4R_AD4TDPER ((uint32_t)0x04000000) /*!< ADC Trigger 4 on Timer D period */
+#define HRTIM_ADC4R_AD4TDRST ((uint32_t)0x08000000) /*!< ADC Trigger 4 on Timer D reset */
+#define HRTIM_ADC4R_AD4TEC2 ((uint32_t)0x10000000) /*!< ADC Trigger 4 on Timer E compare 2 */
+#define HRTIM_ADC4R_AD4TEC3 ((uint32_t)0x20000000) /*!< ADC Trigger 4 on Timer E compare 3 */
+#define HRTIM_ADC4R_AD4TEC4 ((uint32_t)0x40000000) /*!< ADC Trigger 4 on Timer E compare 4 */
+#define HRTIM_ADC4R_AD4TERST ((uint32_t)0x80000000) /*!< ADC Trigger 4 on Timer E reset */
+
+/******************* Bit definition for HRTIM_DLLCR register ****************/
+#define HRTIM_DLLCR_CAL ((uint32_t)0x00000001) /*!< DLL calibration start */
+#define HRTIM_DLLCR_CALEN ((uint32_t)0x00000002) /*!< DLL calibration enable */
+#define HRTIM_DLLCR_CALRTE ((uint32_t)0x0000000C) /*!< DLL calibration rate */
+#define HRTIM_DLLCR_CALRTE_0 ((uint32_t)0x00000004) /*!< DLL calibration rate bit 0 */
+#define HRTIM_DLLCR_CALRTE_1 ((uint32_t)0x00000008) /*!< DLL calibration rate bit 1 */
+
+/******************* Bit definition for HRTIM_FLTINR1 register ***************/
+#define HRTIM_FLTINR1_FLT1E ((uint32_t)0x00000001) /*!< Fault 1 enable */
+#define HRTIM_FLTINR1_FLT1P ((uint32_t)0x00000002) /*!< Fault 1 polarity */
+#define HRTIM_FLTINR1_FLT1SRC ((uint32_t)0x00000004) /*!< Fault 1 source */
+#define HRTIM_FLTINR1_FLT1F ((uint32_t)0x00000078) /*!< Fault 1 filter */
+#define HRTIM_FLTINR1_FLT1F_0 ((uint32_t)0x00000008) /*!< Fault 1 filter bit 0 */
+#define HRTIM_FLTINR1_FLT1F_1 ((uint32_t)0x00000010) /*!< Fault 1 filter bit 1 */
+#define HRTIM_FLTINR1_FLT1F_2 ((uint32_t)0x00000020) /*!< Fault 1 filter bit 2 */
+#define HRTIM_FLTINR1_FLT1F_3 ((uint32_t)0x00000040) /*!< Fault 1 filter bit 3 */
+#define HRTIM_FLTINR1_FLT1LCK ((uint32_t)0x00000080) /*!< Fault 1 lock */
+
+#define HRTIM_FLTINR1_FLT2E ((uint32_t)0x00000100) /*!< Fault 2 enable */
+#define HRTIM_FLTINR1_FLT2P ((uint32_t)0x00000200) /*!< Fault 2 polarity */
+#define HRTIM_FLTINR1_FLT2SRC ((uint32_t)0x00000400) /*!< Fault 2 source */
+#define HRTIM_FLTINR1_FLT2F ((uint32_t)0x00007800) /*!< Fault 2 filter */
+#define HRTIM_FLTINR1_FLT2F_0 ((uint32_t)0x00000800) /*!< Fault 2 filter bit 0 */
+#define HRTIM_FLTINR1_FLT2F_1 ((uint32_t)0x00001000) /*!< Fault 2 filter bit 1 */
+#define HRTIM_FLTINR1_FLT2F_2 ((uint32_t)0x00002000) /*!< Fault 2 filter bit 2 */
+#define HRTIM_FLTINR1_FLT2F_3 ((uint32_t)0x00004000) /*!< Fault 2 filter bit 3 */
+#define HRTIM_FLTINR1_FLT2LCK ((uint32_t)0x00008000) /*!< Fault 2 lock */
+
+#define HRTIM_FLTINR1_FLT3E ((uint32_t)0x00010000) /*!< Fault 3 enable */
+#define HRTIM_FLTINR1_FLT3P ((uint32_t)0x00020000) /*!< Fault 3 polarity */
+#define HRTIM_FLTINR1_FLT3SRC ((uint32_t)0x00040000) /*!< Fault 3 source */
+#define HRTIM_FLTINR1_FLT3F ((uint32_t)0x00780000) /*!< Fault 3 filter */
+#define HRTIM_FLTINR1_FLT3F_0 ((uint32_t)0x00080000) /*!< Fault 3 filter bit 0 */
+#define HRTIM_FLTINR1_FLT3F_1 ((uint32_t)0x00100000) /*!< Fault 3 filter bit 1 */
+#define HRTIM_FLTINR1_FLT3F_2 ((uint32_t)0x00200000) /*!< Fault 3 filter bit 2 */
+#define HRTIM_FLTINR1_FLT3F_3 ((uint32_t)0x00400000) /*!< Fault 3 filter bit 3 */
+#define HRTIM_FLTINR1_FLT3LCK ((uint32_t)0x00800000) /*!< Fault 3 lock */
+
+#define HRTIM_FLTINR1_FLT4E ((uint32_t)0x01000000) /*!< Fault 4 enable */
+#define HRTIM_FLTINR1_FLT4P ((uint32_t)0x02000000) /*!< Fault 4 polarity */
+#define HRTIM_FLTINR1_FLT4SRC ((uint32_t)0x04000000) /*!< Fault 4 source */
+#define HRTIM_FLTINR1_FLT4F ((uint32_t)0x78000000) /*!< Fault 4 filter */
+#define HRTIM_FLTINR1_FLT4F_0 ((uint32_t)0x08000000) /*!< Fault 4 filter bit 0 */
+#define HRTIM_FLTINR1_FLT4F_1 ((uint32_t)0x10000000) /*!< Fault 4 filter bit 1 */
+#define HRTIM_FLTINR1_FLT4F_2 ((uint32_t)0x20000000) /*!< Fault 4 filter bit 2 */
+#define HRTIM_FLTINR1_FLT4F_3 ((uint32_t)0x40000000) /*!< Fault 4 filter bit 3 */
+#define HRTIM_FLTINR1_FLT4LCK ((uint32_t)0x80000000) /*!< Fault 4 lock */
+
+/******************* Bit definition for HRTIM_FLTINR2 register ***************/
+#define HRTIM_FLTINR2_FLT5E ((uint32_t)0x00000001) /*!< Fault 5 enable */
+#define HRTIM_FLTINR2_FLT5P ((uint32_t)0x00000002) /*!< Fault 5 polarity */
+#define HRTIM_FLTINR2_FLT5SRC ((uint32_t)0x00000004) /*!< Fault 5 source */
+#define HRTIM_FLTINR2_FLT5F ((uint32_t)0x00000078) /*!< Fault 5 filter */
+#define HRTIM_FLTINR2_FLT5F_0 ((uint32_t)0x00000008) /*!< Fault 5 filter bit 0 */
+#define HRTIM_FLTINR2_FLT5F_1 ((uint32_t)0x00000010) /*!< Fault 5 filter bit 1 */
+#define HRTIM_FLTINR2_FLT5F_2 ((uint32_t)0x00000020) /*!< Fault 5 filter bit 2 */
+#define HRTIM_FLTINR2_FLT5F_3 ((uint32_t)0x00000040) /*!< Fault 5 filter bit 3 */
+#define HRTIM_FLTINR2_FLT5LCK ((uint32_t)0x00000080) /*!< Fault 5 lock */
+#define HRTIM_FLTINR2_FLTSD ((uint32_t)0x03000000) /*!< Fault sampling clock division */
+#define HRTIM_FLTINR2_FLTSD_0 ((uint32_t)0x01000000) /*!< Fault sampling clock division bit 0 */
+#define HRTIM_FLTINR2_FLTSD_1 ((uint32_t)0x02000000) /*!< Fault sampling clock division bit 1 */
+
+/******************* Bit definition for HRTIM_BDMUPR register ***************/
+#define HRTIM_BDMUPR_MCR ((uint32_t)0x00000001) /*!< MCR register update enable */
+#define HRTIM_BDMUPR_MICR ((uint32_t)0x00000002) /*!< MICR register update enable */
+#define HRTIM_BDMUPR_MDIER ((uint32_t)0x00000004) /*!< MDIER register update enable */
+#define HRTIM_BDMUPR_MCNT ((uint32_t)0x00000008) /*!< MCNT register update enable */
+#define HRTIM_BDMUPR_MPER ((uint32_t)0x00000010) /*!< MPER register update enable */
+#define HRTIM_BDMUPR_MREP ((uint32_t)0x00000020) /*!< MREP register update enable */
+#define HRTIM_BDMUPR_MCMP1 ((uint32_t)0x00000040) /*!< MCMP1 register update enable */
+#define HRTIM_BDMUPR_MCMP2 ((uint32_t)0x00000080) /*!< MCMP2 register update enable */
+#define HRTIM_BDMUPR_MCMP3 ((uint32_t)0x00000100) /*!< MCMP3 register update enable */
+#define HRTIM_BDMUPR_MCMP4 ((uint32_t)0x00000200) /*!< MPCMP4 register update enable */
+
+/******************* Bit definition for HRTIM_BDTUPR register ***************/
+#define HRTIM_BDTUPR_TIMCR ((uint32_t)0x00000001) /*!< TIMCR register update enable */
+#define HRTIM_BDTUPR_TIMICR ((uint32_t)0x00000002) /*!< TIMICR register update enable */
+#define HRTIM_BDTUPR_TIMDIER ((uint32_t)0x00000004) /*!< TIMDIER register update enable */
+#define HRTIM_BDTUPR_TIMCNT ((uint32_t)0x00000008) /*!< TIMCNT register update enable */
+#define HRTIM_BDTUPR_TIMPER ((uint32_t)0x00000010) /*!< TIMPER register update enable */
+#define HRTIM_BDTUPR_TIMREP ((uint32_t)0x00000020) /*!< TIMREP register update enable */
+#define HRTIM_BDTUPR_TIMCMP1 ((uint32_t)0x00000040) /*!< TIMCMP1 register update enable */
+#define HRTIM_BDTUPR_TIMCMP2 ((uint32_t)0x00000080) /*!< TIMCMP2 register update enable */
+#define HRTIM_BDTUPR_TIMCMP3 ((uint32_t)0x00000100) /*!< TIMCMP3 register update enable */
+#define HRTIM_BDTUPR_TIMCMP4 ((uint32_t)0x00000200) /*!< TIMCMP4 register update enable */
+#define HRTIM_BDTUPR_TIMDTR ((uint32_t)0x00000400) /*!< TIMDTR register update enable */
+#define HRTIM_BDTUPR_TIMSET1R ((uint32_t)0x00000800) /*!< TIMSET1R register update enable */
+#define HRTIM_BDTUPR_TIMRST1R ((uint32_t)0x00001000) /*!< TIMRST1R register update enable */
+#define HRTIM_BDTUPR_TIMSET2R ((uint32_t)0x00002000) /*!< TIMSET2R register update enable */
+#define HRTIM_BDTUPR_TIMRST2R ((uint32_t)0x00004000) /*!< TIMRST2R register update enable */
+#define HRTIM_BDTUPR_TIMEEFR1 ((uint32_t)0x00008000) /*!< TIMEEFR1 register update enable */
+#define HRTIM_BDTUPR_TIMEEFR2 ((uint32_t)0x00010000) /*!< TIMEEFR2 register update enable */
+#define HRTIM_BDTUPR_TIMRSTR ((uint32_t)0x00020000) /*!< TIMRSTR register update enable */
+#define HRTIM_BDTUPR_TIMCHPR ((uint32_t)0x00040000) /*!< TIMCHPR register update enable */
+#define HRTIM_BDTUPR_TIMOUTR ((uint32_t)0x00080000) /*!< TIMOUTR register update enable */
+#define HRTIM_BDTUPR_TIMFLTR ((uint32_t)0x00100000) /*!< TIMFLTR register update enable */
+
+/******************* Bit definition for HRTIM_BDMADR register ***************/
+#define HRTIM_BDMADR_BDMADR ((uint32_t)0xFFFFFFFF) /*!< Burst DMA Data register */
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter SAR (ADC) */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_ISR register ********************/
+#define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
+#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
+#define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion flag */
+#define ADC_ISR_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions flag */
+#define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< ADC overrun flag */
+#define ADC_ISR_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion flag */
+#define ADC_ISR_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions flag */
+#define ADC_ISR_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 flag */
+#define ADC_ISR_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 flag */
+#define ADC_ISR_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 flag */
+#define ADC_ISR_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow flag */
+
+/******************** Bit definition for ADC_IER register ********************/
+#define ADC_IER_RDY ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) interrupt source */
+#define ADC_IER_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling interrupt source */
+#define ADC_IER_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion interrupt source */
+#define ADC_IER_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions interrupt source */
+#define ADC_IER_OVR ((uint32_t)0x00000010) /*!< ADC overrun interrupt source */
+#define ADC_IER_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion interrupt source */
+#define ADC_IER_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions interrupt source */
+#define ADC_IER_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 interrupt source */
+#define ADC_IER_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 interrupt source */
+#define ADC_IER_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 interrupt source */
+#define ADC_IER_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow interrupt source */
+
+/******************** Bit definition for ADC_CR register ********************/
+#define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC Enable control */
+#define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC Disable command */
+#define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC Start of Regular conversion */
+#define ADC_CR_JADSTART ((uint32_t)0x00000008) /*!< ADC Start of injected conversion */
+#define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC Stop of Regular conversion */
+#define ADC_CR_JADSTP ((uint32_t)0x00000020) /*!< ADC Stop of injected conversion */
+#define ADC_CR_ADVREGEN ((uint32_t)0x30000000) /*!< ADC Voltage regulator Enable */
+#define ADC_CR_ADVREGEN_0 ((uint32_t)0x10000000) /*!< ADC ADVREGEN bit 0 */
+#define ADC_CR_ADVREGEN_1 ((uint32_t)0x20000000) /*!< ADC ADVREGEN bit 1 */
+#define ADC_CR_ADCALDIF ((uint32_t)0x40000000) /*!< ADC Differential Mode for calibration */
+#define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC Calibration */
+
+/******************** Bit definition for ADC_CFGR register ********************/
+#define ADC_CFGR_DMAEN ((uint32_t)0x00000001) /*!< ADC DMA Enable */
+#define ADC_CFGR_DMACFG ((uint32_t)0x00000002) /*!< ADC DMA configuration */
+
+#define ADC_CFGR_RES ((uint32_t)0x00000018) /*!< ADC Data resolution */
+#define ADC_CFGR_RES_0 ((uint32_t)0x00000008) /*!< ADC RES bit 0 */
+#define ADC_CFGR_RES_1 ((uint32_t)0x00000010) /*!< ADC RES bit 1 */
+
+#define ADC_CFGR_ALIGN ((uint32_t)0x00000020) /*!< ADC Data Alignment */
+
+#define ADC_CFGR_EXTSEL ((uint32_t)0x000003C0) /*!< ADC External trigger selection for regular group */
+#define ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040) /*!< ADC EXTSEL bit 0 */
+#define ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080) /*!< ADC EXTSEL bit 1 */
+#define ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100) /*!< ADC EXTSEL bit 2 */
+#define ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200) /*!< ADC EXTSEL bit 3 */
+
+#define ADC_CFGR_EXTEN ((uint32_t)0x00000C00) /*!< ADC External trigger enable and polarity selection for regular channels */
+#define ADC_CFGR_EXTEN_0 ((uint32_t)0x00000400) /*!< ADC EXTEN bit 0 */
+#define ADC_CFGR_EXTEN_1 ((uint32_t)0x00000800) /*!< ADC EXTEN bit 1 */
+
+#define ADC_CFGR_OVRMOD ((uint32_t)0x00001000) /*!< ADC overrun mode */
+#define ADC_CFGR_CONT ((uint32_t)0x00002000) /*!< ADC Single/continuous conversion mode for regular conversion */
+#define ADC_CFGR_AUTDLY ((uint32_t)0x00004000) /*!< ADC Delayed conversion mode */
+#define ADC_CFGR_DISCEN ((uint32_t)0x00010000) /*!< ADC Discontinuous mode for regular channels */
+
+#define ADC_CFGR_DISCNUM ((uint32_t)0x000E0000) /*!< ADC Discontinuous mode channel count */
+#define ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000) /*!< ADC DISCNUM bit 0 */
+#define ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000) /*!< ADC DISCNUM bit 1 */
+#define ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000) /*!< ADC DISCNUM bit 2 */
+
+#define ADC_CFGR_JDISCEN ((uint32_t)0x00100000) /*!< ADC Discontinuous mode on injected channels */
+#define ADC_CFGR_JQM ((uint32_t)0x00200000) /*!< ADC JSQR Queue mode */
+#define ADC_CFGR_AWD1SGL ((uint32_t)0x00400000) /*!< Enable the watchdog 1 on a single channel or on all channels */
+#define ADC_CFGR_AWD1EN ((uint32_t)0x00800000) /*!< ADC Analog watchdog 1 enable on regular Channels */
+#define ADC_CFGR_JAWD1EN ((uint32_t)0x01000000) /*!< ADC Analog watchdog 1 enable on injected Channels */
+#define ADC_CFGR_JAUTO ((uint32_t)0x02000000) /*!< ADC Automatic injected group conversion */
+
+#define ADC_CFGR_AWD1CH ((uint32_t)0x7C000000) /*!< ADC Analog watchdog 1 Channel selection */
+#define ADC_CFGR_AWD1CH_0 ((uint32_t)0x04000000) /*!< ADC AWD1CH bit 0 */
+#define ADC_CFGR_AWD1CH_1 ((uint32_t)0x08000000) /*!< ADC AWD1CH bit 1 */
+#define ADC_CFGR_AWD1CH_2 ((uint32_t)0x10000000) /*!< ADC AWD1CH bit 2 */
+#define ADC_CFGR_AWD1CH_3 ((uint32_t)0x20000000) /*!< ADC AWD1CH bit 3 */
+#define ADC_CFGR_AWD1CH_4 ((uint32_t)0x40000000) /*!< ADC AWD1CH bit 4 */
+
+/******************** Bit definition for ADC_SMPR1 register ********************/
+#define ADC_SMPR1_SMP0 ((uint32_t)0x00000007) /*!< ADC Channel 0 Sampling time selection */
+#define ADC_SMPR1_SMP0_0 ((uint32_t)0x00000001) /*!< ADC SMP0 bit 0 */
+#define ADC_SMPR1_SMP0_1 ((uint32_t)0x00000002) /*!< ADC SMP0 bit 1 */
+#define ADC_SMPR1_SMP0_2 ((uint32_t)0x00000004) /*!< ADC SMP0 bit 2 */
+
+#define ADC_SMPR1_SMP1 ((uint32_t)0x00000038) /*!< ADC Channel 1 Sampling time selection */
+#define ADC_SMPR1_SMP1_0 ((uint32_t)0x00000008) /*!< ADC SMP1 bit 0 */
+#define ADC_SMPR1_SMP1_1 ((uint32_t)0x00000010) /*!< ADC SMP1 bit 1 */
+#define ADC_SMPR1_SMP1_2 ((uint32_t)0x00000020) /*!< ADC SMP1 bit 2 */
+
+#define ADC_SMPR1_SMP2 ((uint32_t)0x000001C0) /*!< ADC Channel 2 Sampling time selection */
+#define ADC_SMPR1_SMP2_0 ((uint32_t)0x00000040) /*!< ADC SMP2 bit 0 */
+#define ADC_SMPR1_SMP2_1 ((uint32_t)0x00000080) /*!< ADC SMP2 bit 1 */
+#define ADC_SMPR1_SMP2_2 ((uint32_t)0x00000100) /*!< ADC SMP2 bit 2 */
+
+#define ADC_SMPR1_SMP3 ((uint32_t)0x00000E00) /*!< ADC Channel 3 Sampling time selection */
+#define ADC_SMPR1_SMP3_0 ((uint32_t)0x00000200) /*!< ADC SMP3 bit 0 */
+#define ADC_SMPR1_SMP3_1 ((uint32_t)0x00000400) /*!< ADC SMP3 bit 1 */
+#define ADC_SMPR1_SMP3_2 ((uint32_t)0x00000800) /*!< ADC SMP3 bit 2 */
+
+#define ADC_SMPR1_SMP4 ((uint32_t)0x00007000) /*!< ADC Channel 4 Sampling time selection */
+#define ADC_SMPR1_SMP4_0 ((uint32_t)0x00001000) /*!< ADC SMP4 bit 0 */
+#define ADC_SMPR1_SMP4_1 ((uint32_t)0x00002000) /*!< ADC SMP4 bit 1 */
+#define ADC_SMPR1_SMP4_2 ((uint32_t)0x00004000) /*!< ADC SMP4 bit 2 */
+
+#define ADC_SMPR1_SMP5 ((uint32_t)0x00038000) /*!< ADC Channel 5 Sampling time selection */
+#define ADC_SMPR1_SMP5_0 ((uint32_t)0x00008000) /*!< ADC SMP5 bit 0 */
+#define ADC_SMPR1_SMP5_1 ((uint32_t)0x00010000) /*!< ADC SMP5 bit 1 */
+#define ADC_SMPR1_SMP5_2 ((uint32_t)0x00020000) /*!< ADC SMP5 bit 2 */
+
+#define ADC_SMPR1_SMP6 ((uint32_t)0x001C0000) /*!< ADC Channel 6 Sampling time selection */
+#define ADC_SMPR1_SMP6_0 ((uint32_t)0x00040000) /*!< ADC SMP6 bit 0 */
+#define ADC_SMPR1_SMP6_1 ((uint32_t)0x00080000) /*!< ADC SMP6 bit 1 */
+#define ADC_SMPR1_SMP6_2 ((uint32_t)0x00100000) /*!< ADC SMP6 bit 2 */
+
+#define ADC_SMPR1_SMP7 ((uint32_t)0x00E00000) /*!< ADC Channel 7 Sampling time selection */
+#define ADC_SMPR1_SMP7_0 ((uint32_t)0x00200000) /*!< ADC SMP7 bit 0 */
+#define ADC_SMPR1_SMP7_1 ((uint32_t)0x00400000) /*!< ADC SMP7 bit 1 */
+#define ADC_SMPR1_SMP7_2 ((uint32_t)0x00800000) /*!< ADC SMP7 bit 2 */
+
+#define ADC_SMPR1_SMP8 ((uint32_t)0x07000000) /*!< ADC Channel 8 Sampling time selection */
+#define ADC_SMPR1_SMP8_0 ((uint32_t)0x01000000) /*!< ADC SMP8 bit 0 */
+#define ADC_SMPR1_SMP8_1 ((uint32_t)0x02000000) /*!< ADC SMP8 bit 1 */
+#define ADC_SMPR1_SMP8_2 ((uint32_t)0x04000000) /*!< ADC SMP8 bit 2 */
+
+#define ADC_SMPR1_SMP9 ((uint32_t)0x38000000) /*!< ADC Channel 9 Sampling time selection */
+#define ADC_SMPR1_SMP9_0 ((uint32_t)0x08000000) /*!< ADC SMP9 bit 0 */
+#define ADC_SMPR1_SMP9_1 ((uint32_t)0x10000000) /*!< ADC SMP9 bit 1 */
+#define ADC_SMPR1_SMP9_2 ((uint32_t)0x20000000) /*!< ADC SMP9 bit 2 */
+
+/******************** Bit definition for ADC_SMPR2 register ********************/
+#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< ADC Channel 10 Sampling time selection */
+#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< ADC SMP10 bit 0 */
+#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< ADC SMP10 bit 1 */
+#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< ADC SMP10 bit 2 */
+
+#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< ADC Channel 11 Sampling time selection */
+#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< ADC SMP11 bit 0 */
+#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< ADC SMP11 bit 1 */
+#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< ADC SMP11 bit 2 */
+
+#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< ADC Channel 12 Sampling time selection */
+#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< ADC SMP12 bit 0 */
+#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< ADC SMP12 bit 1 */
+#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< ADC SMP12 bit 2 */
+
+#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< ADC Channel 13 Sampling time selection */
+#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< ADC SMP13 bit 0 */
+#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< ADC SMP13 bit 1 */
+#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< ADC SMP13 bit 2 */
+
+#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< ADC Channel 14 Sampling time selection */
+#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< ADC SMP14 bit 0 */
+#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< ADC SMP14 bit 1 */
+#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< ADC SMP14 bit 2 */
+
+#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< ADC Channel 15 Sampling time selection */
+#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< ADC SMP15 bit 0 */
+#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< ADC SMP15 bit 1 */
+#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< ADC SMP15 bit 2 */
+
+#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< ADC Channel 16 Sampling time selection */
+#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< ADC SMP16 bit 0 */
+#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< ADC SMP16 bit 1 */
+#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< ADC SMP16 bit 2 */
+
+#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< ADC Channel 17 Sampling time selection */
+#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< ADC SMP17 bit 0 */
+#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< ADC SMP17 bit 1 */
+#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< ADC SMP17 bit 2 */
+
+#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< ADC Channel 18 Sampling time selection */
+#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< ADC SMP18 bit 0 */
+#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< ADC SMP18 bit 1 */
+#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< ADC SMP18 bit 2 */
+
+/******************** Bit definition for ADC_TR1 register ********************/
+#define ADC_TR1_LT1 ((uint32_t)0x00000FFF) /*!< ADC Analog watchdog 1 lower threshold */
+#define ADC_TR1_LT1_0 ((uint32_t)0x00000001) /*!< ADC LT1 bit 0 */
+#define ADC_TR1_LT1_1 ((uint32_t)0x00000002) /*!< ADC LT1 bit 1 */
+#define ADC_TR1_LT1_2 ((uint32_t)0x00000004) /*!< ADC LT1 bit 2 */
+#define ADC_TR1_LT1_3 ((uint32_t)0x00000008) /*!< ADC LT1 bit 3 */
+#define ADC_TR1_LT1_4 ((uint32_t)0x00000010) /*!< ADC LT1 bit 4 */
+#define ADC_TR1_LT1_5 ((uint32_t)0x00000020) /*!< ADC LT1 bit 5 */
+#define ADC_TR1_LT1_6 ((uint32_t)0x00000040) /*!< ADC LT1 bit 6 */
+#define ADC_TR1_LT1_7 ((uint32_t)0x00000080) /*!< ADC LT1 bit 7 */
+#define ADC_TR1_LT1_8 ((uint32_t)0x00000100) /*!< ADC LT1 bit 8 */
+#define ADC_TR1_LT1_9 ((uint32_t)0x00000200) /*!< ADC LT1 bit 9 */
+#define ADC_TR1_LT1_10 ((uint32_t)0x00000400) /*!< ADC LT1 bit 10 */
+#define ADC_TR1_LT1_11 ((uint32_t)0x00000800) /*!< ADC LT1 bit 11 */
+
+#define ADC_TR1_HT1 ((uint32_t)0x0FFF0000) /*!< ADC Analog watchdog 1 higher threshold */
+#define ADC_TR1_HT1_0 ((uint32_t)0x00010000) /*!< ADC HT1 bit 0 */
+#define ADC_TR1_HT1_1 ((uint32_t)0x00020000) /*!< ADC HT1 bit 1 */
+#define ADC_TR1_HT1_2 ((uint32_t)0x00040000) /*!< ADC HT1 bit 2 */
+#define ADC_TR1_HT1_3 ((uint32_t)0x00080000) /*!< ADC HT1 bit 3 */
+#define ADC_TR1_HT1_4 ((uint32_t)0x00100000) /*!< ADC HT1 bit 4 */
+#define ADC_TR1_HT1_5 ((uint32_t)0x00200000) /*!< ADC HT1 bit 5 */
+#define ADC_TR1_HT1_6 ((uint32_t)0x00400000) /*!< ADC HT1 bit 6 */
+#define ADC_TR1_HT1_7 ((uint32_t)0x00800000) /*!< ADC HT1 bit 7 */
+#define ADC_TR1_HT1_8 ((uint32_t)0x01000000) /*!< ADC HT1 bit 8 */
+#define ADC_TR1_HT1_9 ((uint32_t)0x02000000) /*!< ADC HT1 bit 9 */
+#define ADC_TR1_HT1_10 ((uint32_t)0x04000000) /*!< ADC HT1 bit 10 */
+#define ADC_TR1_HT1_11 ((uint32_t)0x08000000) /*!< ADC HT1 bit 11 */
+
+/******************** Bit definition for ADC_TR2 register ********************/
+#define ADC_TR2_LT2 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 2 lower threshold */
+#define ADC_TR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */
+#define ADC_TR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */
+#define ADC_TR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */
+#define ADC_TR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */
+#define ADC_TR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */
+#define ADC_TR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */
+#define ADC_TR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */
+#define ADC_TR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */
+
+#define ADC_TR2_HT2 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 2 higher threshold */
+#define ADC_TR2_HT2_0 ((uint32_t)0x00010000) /*!< ADC HT2 bit 0 */
+#define ADC_TR2_HT2_1 ((uint32_t)0x00020000) /*!< ADC HT2 bit 1 */
+#define ADC_TR2_HT2_2 ((uint32_t)0x00040000) /*!< ADC HT2 bit 2 */
+#define ADC_TR2_HT2_3 ((uint32_t)0x00080000) /*!< ADC HT2 bit 3 */
+#define ADC_TR2_HT2_4 ((uint32_t)0x00100000) /*!< ADC HT2 bit 4 */
+#define ADC_TR2_HT2_5 ((uint32_t)0x00200000) /*!< ADC HT2 bit 5 */
+#define ADC_TR2_HT2_6 ((uint32_t)0x00400000) /*!< ADC HT2 bit 6 */
+#define ADC_TR2_HT2_7 ((uint32_t)0x00800000) /*!< ADC HT2 bit 7 */
+
+/******************** Bit definition for ADC_TR3 register ********************/
+#define ADC_TR3_LT3 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 3 lower threshold */
+#define ADC_TR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */
+#define ADC_TR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */
+#define ADC_TR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */
+#define ADC_TR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */
+#define ADC_TR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */
+#define ADC_TR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */
+#define ADC_TR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */
+#define ADC_TR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */
+
+#define ADC_TR3_HT3 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 3 higher threshold */
+#define ADC_TR3_HT3_0 ((uint32_t)0x00010000) /*!< ADC HT3 bit 0 */
+#define ADC_TR3_HT3_1 ((uint32_t)0x00020000) /*!< ADC HT3 bit 1 */
+#define ADC_TR3_HT3_2 ((uint32_t)0x00040000) /*!< ADC HT3 bit 2 */
+#define ADC_TR3_HT3_3 ((uint32_t)0x00080000) /*!< ADC HT3 bit 3 */
+#define ADC_TR3_HT3_4 ((uint32_t)0x00100000) /*!< ADC HT3 bit 4 */
+#define ADC_TR3_HT3_5 ((uint32_t)0x00200000) /*!< ADC HT3 bit 5 */
+#define ADC_TR3_HT3_6 ((uint32_t)0x00400000) /*!< ADC HT3 bit 6 */
+#define ADC_TR3_HT3_7 ((uint32_t)0x00800000) /*!< ADC HT3 bit 7 */
+
+/******************** Bit definition for ADC_SQR1 register ********************/
+#define ADC_SQR1_L ((uint32_t)0x0000000F) /*!< ADC regular channel sequence length */
+#define ADC_SQR1_L_0 ((uint32_t)0x00000001) /*!< ADC L bit 0 */
+#define ADC_SQR1_L_1 ((uint32_t)0x00000002) /*!< ADC L bit 1 */
+#define ADC_SQR1_L_2 ((uint32_t)0x00000004) /*!< ADC L bit 2 */
+#define ADC_SQR1_L_3 ((uint32_t)0x00000008) /*!< ADC L bit 3 */
+
+#define ADC_SQR1_SQ1 ((uint32_t)0x000007C0) /*!< ADC 1st conversion in regular sequence */
+#define ADC_SQR1_SQ1_0 ((uint32_t)0x00000040) /*!< ADC SQ1 bit 0 */
+#define ADC_SQR1_SQ1_1 ((uint32_t)0x00000080) /*!< ADC SQ1 bit 1 */
+#define ADC_SQR1_SQ1_2 ((uint32_t)0x00000100) /*!< ADC SQ1 bit 2 */
+#define ADC_SQR1_SQ1_3 ((uint32_t)0x00000200) /*!< ADC SQ1 bit 3 */
+#define ADC_SQR1_SQ1_4 ((uint32_t)0x00000400) /*!< ADC SQ1 bit 4 */
+
+#define ADC_SQR1_SQ2 ((uint32_t)0x0001F000) /*!< ADC 2nd conversion in regular sequence */
+#define ADC_SQR1_SQ2_0 ((uint32_t)0x00001000) /*!< ADC SQ2 bit 0 */
+#define ADC_SQR1_SQ2_1 ((uint32_t)0x00002000) /*!< ADC SQ2 bit 1 */
+#define ADC_SQR1_SQ2_2 ((uint32_t)0x00004000) /*!< ADC SQ2 bit 2 */
+#define ADC_SQR1_SQ2_3 ((uint32_t)0x00008000) /*!< ADC SQ2 bit 3 */
+#define ADC_SQR1_SQ2_4 ((uint32_t)0x00010000) /*!< ADC SQ2 bit 4 */
+
+#define ADC_SQR1_SQ3 ((uint32_t)0x007C0000) /*!< ADC 3rd conversion in regular sequence */
+#define ADC_SQR1_SQ3_0 ((uint32_t)0x00040000) /*!< ADC SQ3 bit 0 */
+#define ADC_SQR1_SQ3_1 ((uint32_t)0x00080000) /*!< ADC SQ3 bit 1 */
+#define ADC_SQR1_SQ3_2 ((uint32_t)0x00100000) /*!< ADC SQ3 bit 2 */
+#define ADC_SQR1_SQ3_3 ((uint32_t)0x00200000) /*!< ADC SQ3 bit 3 */
+#define ADC_SQR1_SQ3_4 ((uint32_t)0x00400000) /*!< ADC SQ3 bit 4 */
+
+#define ADC_SQR1_SQ4 ((uint32_t)0x1F000000) /*!< ADC 4th conversion in regular sequence */
+#define ADC_SQR1_SQ4_0 ((uint32_t)0x01000000) /*!< ADC SQ4 bit 0 */
+#define ADC_SQR1_SQ4_1 ((uint32_t)0x02000000) /*!< ADC SQ4 bit 1 */
+#define ADC_SQR1_SQ4_2 ((uint32_t)0x04000000) /*!< ADC SQ4 bit 2 */
+#define ADC_SQR1_SQ4_3 ((uint32_t)0x08000000) /*!< ADC SQ4 bit 3 */
+#define ADC_SQR1_SQ4_4 ((uint32_t)0x10000000) /*!< ADC SQ4 bit 4 */
+
+/******************** Bit definition for ADC_SQR2 register ********************/
+#define ADC_SQR2_SQ5 ((uint32_t)0x0000001F) /*!< ADC 5th conversion in regular sequence */
+#define ADC_SQR2_SQ5_0 ((uint32_t)0x00000001) /*!< ADC SQ5 bit 0 */
+#define ADC_SQR2_SQ5_1 ((uint32_t)0x00000002) /*!< ADC SQ5 bit 1 */
+#define ADC_SQR2_SQ5_2 ((uint32_t)0x00000004) /*!< ADC SQ5 bit 2 */
+#define ADC_SQR2_SQ5_3 ((uint32_t)0x00000008) /*!< ADC SQ5 bit 3 */
+#define ADC_SQR2_SQ5_4 ((uint32_t)0x00000010) /*!< ADC SQ5 bit 4 */
+
+#define ADC_SQR2_SQ6 ((uint32_t)0x000007C0) /*!< ADC 6th conversion in regular sequence */
+#define ADC_SQR2_SQ6_0 ((uint32_t)0x00000040) /*!< ADC SQ6 bit 0 */
+#define ADC_SQR2_SQ6_1 ((uint32_t)0x00000080) /*!< ADC SQ6 bit 1 */
+#define ADC_SQR2_SQ6_2 ((uint32_t)0x00000100) /*!< ADC SQ6 bit 2 */
+#define ADC_SQR2_SQ6_3 ((uint32_t)0x00000200) /*!< ADC SQ6 bit 3 */
+#define ADC_SQR2_SQ6_4 ((uint32_t)0x00000400) /*!< ADC SQ6 bit 4 */
+
+#define ADC_SQR2_SQ7 ((uint32_t)0x0001F000) /*!< ADC 7th conversion in regular sequence */
+#define ADC_SQR2_SQ7_0 ((uint32_t)0x00001000) /*!< ADC SQ7 bit 0 */
+#define ADC_SQR2_SQ7_1 ((uint32_t)0x00002000) /*!< ADC SQ7 bit 1 */
+#define ADC_SQR2_SQ7_2 ((uint32_t)0x00004000) /*!< ADC SQ7 bit 2 */
+#define ADC_SQR2_SQ7_3 ((uint32_t)0x00008000) /*!< ADC SQ7 bit 3 */
+#define ADC_SQR2_SQ7_4 ((uint32_t)0x00010000) /*!< ADC SQ7 bit 4 */
+
+#define ADC_SQR2_SQ8 ((uint32_t)0x007C0000) /*!< ADC 8th conversion in regular sequence */
+#define ADC_SQR2_SQ8_0 ((uint32_t)0x00040000) /*!< ADC SQ8 bit 0 */
+#define ADC_SQR2_SQ8_1 ((uint32_t)0x00080000) /*!< ADC SQ8 bit 1 */
+#define ADC_SQR2_SQ8_2 ((uint32_t)0x00100000) /*!< ADC SQ8 bit 2 */
+#define ADC_SQR2_SQ8_3 ((uint32_t)0x00200000) /*!< ADC SQ8 bit 3 */
+#define ADC_SQR2_SQ8_4 ((uint32_t)0x00400000) /*!< ADC SQ8 bit 4 */
+
+#define ADC_SQR2_SQ9 ((uint32_t)0x1F000000) /*!< ADC 9th conversion in regular sequence */
+#define ADC_SQR2_SQ9_0 ((uint32_t)0x01000000) /*!< ADC SQ9 bit 0 */
+#define ADC_SQR2_SQ9_1 ((uint32_t)0x02000000) /*!< ADC SQ9 bit 1 */
+#define ADC_SQR2_SQ9_2 ((uint32_t)0x04000000) /*!< ADC SQ9 bit 2 */
+#define ADC_SQR2_SQ9_3 ((uint32_t)0x08000000) /*!< ADC SQ9 bit 3 */
+#define ADC_SQR2_SQ9_4 ((uint32_t)0x10000000) /*!< ADC SQ9 bit 4 */
+
+/******************** Bit definition for ADC_SQR3 register ********************/
+#define ADC_SQR3_SQ10 ((uint32_t)0x0000001F) /*!< ADC 10th conversion in regular sequence */
+#define ADC_SQR3_SQ10_0 ((uint32_t)0x00000001) /*!< ADC SQ10 bit 0 */
+#define ADC_SQR3_SQ10_1 ((uint32_t)0x00000002) /*!< ADC SQ10 bit 1 */
+#define ADC_SQR3_SQ10_2 ((uint32_t)0x00000004) /*!< ADC SQ10 bit 2 */
+#define ADC_SQR3_SQ10_3 ((uint32_t)0x00000008) /*!< ADC SQ10 bit 3 */
+#define ADC_SQR3_SQ10_4 ((uint32_t)0x00000010) /*!< ADC SQ10 bit 4 */
+
+#define ADC_SQR3_SQ11 ((uint32_t)0x000007C0) /*!< ADC 11th conversion in regular sequence */
+#define ADC_SQR3_SQ11_0 ((uint32_t)0x00000040) /*!< ADC SQ11 bit 0 */
+#define ADC_SQR3_SQ11_1 ((uint32_t)0x00000080) /*!< ADC SQ11 bit 1 */
+#define ADC_SQR3_SQ11_2 ((uint32_t)0x00000100) /*!< ADC SQ11 bit 2 */
+#define ADC_SQR3_SQ11_3 ((uint32_t)0x00000200) /*!< ADC SQ11 bit 3 */
+#define ADC_SQR3_SQ11_4 ((uint32_t)0x00000400) /*!< ADC SQ11 bit 4 */
+
+#define ADC_SQR3_SQ12 ((uint32_t)0x0001F000) /*!< ADC 12th conversion in regular sequence */
+#define ADC_SQR3_SQ12_0 ((uint32_t)0x00001000) /*!< ADC SQ12 bit 0 */
+#define ADC_SQR3_SQ12_1 ((uint32_t)0x00002000) /*!< ADC SQ12 bit 1 */
+#define ADC_SQR3_SQ12_2 ((uint32_t)0x00004000) /*!< ADC SQ12 bit 2 */
+#define ADC_SQR3_SQ12_3 ((uint32_t)0x00008000) /*!< ADC SQ12 bit 3 */
+#define ADC_SQR3_SQ12_4 ((uint32_t)0x00010000) /*!< ADC SQ12 bit 4 */
+
+#define ADC_SQR3_SQ13 ((uint32_t)0x007C0000) /*!< ADC 13th conversion in regular sequence */
+#define ADC_SQR3_SQ13_0 ((uint32_t)0x00040000) /*!< ADC SQ13 bit 0 */
+#define ADC_SQR3_SQ13_1 ((uint32_t)0x00080000) /*!< ADC SQ13 bit 1 */
+#define ADC_SQR3_SQ13_2 ((uint32_t)0x00100000) /*!< ADC SQ13 bit 2 */
+#define ADC_SQR3_SQ13_3 ((uint32_t)0x00200000) /*!< ADC SQ13 bit 3 */
+#define ADC_SQR3_SQ13_4 ((uint32_t)0x00400000) /*!< ADC SQ13 bit 4 */
+
+#define ADC_SQR3_SQ14 ((uint32_t)0x1F000000) /*!< ADC 14th conversion in regular sequence */
+#define ADC_SQR3_SQ14_0 ((uint32_t)0x01000000) /*!< ADC SQ14 bit 0 */
+#define ADC_SQR3_SQ14_1 ((uint32_t)0x02000000) /*!< ADC SQ14 bit 1 */
+#define ADC_SQR3_SQ14_2 ((uint32_t)0x04000000) /*!< ADC SQ14 bit 2 */
+#define ADC_SQR3_SQ14_3 ((uint32_t)0x08000000) /*!< ADC SQ14 bit 3 */
+#define ADC_SQR3_SQ14_4 ((uint32_t)0x10000000) /*!< ADC SQ14 bit 4 */
+
+/******************** Bit definition for ADC_SQR4 register ********************/
+#define ADC_SQR4_SQ15 ((uint32_t)0x0000001F) /*!< ADC 15th conversion in regular sequence */
+#define ADC_SQR4_SQ15_0 ((uint32_t)0x00000001) /*!< ADC SQ15 bit 0 */
+#define ADC_SQR4_SQ15_1 ((uint32_t)0x00000002) /*!< ADC SQ15 bit 1 */
+#define ADC_SQR4_SQ15_2 ((uint32_t)0x00000004) /*!< ADC SQ15 bit 2 */
+#define ADC_SQR4_SQ15_3 ((uint32_t)0x00000008) /*!< ADC SQ15 bit 3 */
+#define ADC_SQR4_SQ15_4 ((uint32_t)0x00000010) /*!< ADC SQ105 bit 4 */
+
+#define ADC_SQR4_SQ16 ((uint32_t)0x000007C0) /*!< ADC 16th conversion in regular sequence */
+#define ADC_SQR4_SQ16_0 ((uint32_t)0x00000040) /*!< ADC SQ16 bit 0 */
+#define ADC_SQR4_SQ16_1 ((uint32_t)0x00000080) /*!< ADC SQ16 bit 1 */
+#define ADC_SQR4_SQ16_2 ((uint32_t)0x00000100) /*!< ADC SQ16 bit 2 */
+#define ADC_SQR4_SQ16_3 ((uint32_t)0x00000200) /*!< ADC SQ16 bit 3 */
+#define ADC_SQR4_SQ16_4 ((uint32_t)0x00000400) /*!< ADC SQ16 bit 4 */
+
+/* these defines are maintained for legacy purpose */
+#define ADC_SQR3_SQ15 ADC_SQR4_SQ15 /*!< ADC 15th conversion in regular sequence */
+#define ADC_SQR3_SQ15_0 ADC_SQR4_SQ15_0 /*!< ADC SQ15 bit 0 */
+#define ADC_SQR3_SQ15_1 ADC_SQR4_SQ15_1 /*!< ADC SQ15 bit 1 */
+#define ADC_SQR3_SQ15_2 ADC_SQR4_SQ15_2 /*!< ADC SQ15 bit 2 */
+#define ADC_SQR3_SQ15_3 ADC_SQR4_SQ15_3 /*!< ADC SQ15 bit 3 */
+#define ADC_SQR3_SQ15_4 ADC_SQR4_SQ15_4 /*!< ADC SQ105 bit 4 */
+
+#define ADC_SQR3_SQ16 ADC_SQR4_SQ16 /*!< ADC 16th conversion in regular sequence */
+#define ADC_SQR3_SQ16_0 ADC_SQR4_SQ16_0 /*!< ADC SQ16 bit 0 */
+#define ADC_SQR3_SQ16_1 ADC_SQR4_SQ16_1 /*!< ADC SQ16 bit 1 */
+#define ADC_SQR3_SQ16_2 ADC_SQR4_SQ16_2 /*!< ADC SQ16 bit 2 */
+#define ADC_SQR3_SQ16_3 ADC_SQR4_SQ16_3 /*!< ADC SQ16 bit 3 */
+#define ADC_SQR3_SQ16_4 ADC_SQR4_SQ16_4 /*!< ADC SQ16 bit 4 */
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_RDATA ((uint32_t)0x0000FFFF) /*!< ADC regular Data converted */
+#define ADC_DR_RDATA_0 ((uint32_t)0x00000001) /*!< ADC RDATA bit 0 */
+#define ADC_DR_RDATA_1 ((uint32_t)0x00000002) /*!< ADC RDATA bit 1 */
+#define ADC_DR_RDATA_2 ((uint32_t)0x00000004) /*!< ADC RDATA bit 2 */
+#define ADC_DR_RDATA_3 ((uint32_t)0x00000008) /*!< ADC RDATA bit 3 */
+#define ADC_DR_RDATA_4 ((uint32_t)0x00000010) /*!< ADC RDATA bit 4 */
+#define ADC_DR_RDATA_5 ((uint32_t)0x00000020) /*!< ADC RDATA bit 5 */
+#define ADC_DR_RDATA_6 ((uint32_t)0x00000040) /*!< ADC RDATA bit 6 */
+#define ADC_DR_RDATA_7 ((uint32_t)0x00000080) /*!< ADC RDATA bit 7 */
+#define ADC_DR_RDATA_8 ((uint32_t)0x00000100) /*!< ADC RDATA bit 8 */
+#define ADC_DR_RDATA_9 ((uint32_t)0x00000200) /*!< ADC RDATA bit 9 */
+#define ADC_DR_RDATA_10 ((uint32_t)0x00000400) /*!< ADC RDATA bit 10 */
+#define ADC_DR_RDATA_11 ((uint32_t)0x00000800) /*!< ADC RDATA bit 11 */
+#define ADC_DR_RDATA_12 ((uint32_t)0x00001000) /*!< ADC RDATA bit 12 */
+#define ADC_DR_RDATA_13 ((uint32_t)0x00002000) /*!< ADC RDATA bit 13 */
+#define ADC_DR_RDATA_14 ((uint32_t)0x00004000) /*!< ADC RDATA bit 14 */
+#define ADC_DR_RDATA_15 ((uint32_t)0x00008000) /*!< ADC RDATA bit 15 */
+
+/******************** Bit definition for ADC_JSQR register ********************/
+#define ADC_JSQR_JL ((uint32_t)0x00000003) /*!< ADC injected channel sequence length */
+#define ADC_JSQR_JL_0 ((uint32_t)0x00000001) /*!< ADC JL bit 0 */
+#define ADC_JSQR_JL_1 ((uint32_t)0x00000002) /*!< ADC JL bit 1 */
+
+#define ADC_JSQR_JEXTSEL ((uint32_t)0x0000003C) /*!< ADC external trigger selection for injected group */
+#define ADC_JSQR_JEXTSEL_0 ((uint32_t)0x00000004) /*!< ADC JEXTSEL bit 0 */
+#define ADC_JSQR_JEXTSEL_1 ((uint32_t)0x00000008) /*!< ADC JEXTSEL bit 1 */
+#define ADC_JSQR_JEXTSEL_2 ((uint32_t)0x00000010) /*!< ADC JEXTSEL bit 2 */
+#define ADC_JSQR_JEXTSEL_3 ((uint32_t)0x00000020) /*!< ADC JEXTSEL bit 3 */
+
+#define ADC_JSQR_JEXTEN ((uint32_t)0x000000C0) /*!< ADC external trigger enable and polarity selection for injected channels */
+#define ADC_JSQR_JEXTEN_0 ((uint32_t)0x00000040) /*!< ADC JEXTEN bit 0 */
+#define ADC_JSQR_JEXTEN_1 ((uint32_t)0x00000080) /*!< ADC JEXTEN bit 1 */
+
+#define ADC_JSQR_JSQ1 ((uint32_t)0x00001F00) /*!< ADC 1st conversion in injected sequence */
+#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000100) /*!< ADC JSQ1 bit 0 */
+#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000200) /*!< ADC JSQ1 bit 1 */
+#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000400) /*!< ADC JSQ1 bit 2 */
+#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000800) /*!< ADC JSQ1 bit 3 */
+#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00001000) /*!< ADC JSQ1 bit 4 */
+
+#define ADC_JSQR_JSQ2 ((uint32_t)0x0007C000) /*!< ADC 2nd conversion in injected sequence */
+#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00004000) /*!< ADC JSQ2 bit 0 */
+#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00008000) /*!< ADC JSQ2 bit 1 */
+#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00010000) /*!< ADC JSQ2 bit 2 */
+#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00020000) /*!< ADC JSQ2 bit 3 */
+#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00040000) /*!< ADC JSQ2 bit 4 */
+
+#define ADC_JSQR_JSQ3 ((uint32_t)0x01F00000) /*!< ADC 3rd conversion in injected sequence */
+#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00100000) /*!< ADC JSQ3 bit 0 */
+#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00200000) /*!< ADC JSQ3 bit 1 */
+#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00400000) /*!< ADC JSQ3 bit 2 */
+#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00800000) /*!< ADC JSQ3 bit 3 */
+#define ADC_JSQR_JSQ3_4 ((uint32_t)0x01000000) /*!< ADC JSQ3 bit 4 */
+
+#define ADC_JSQR_JSQ4 ((uint32_t)0x7C000000) /*!< ADC 4th conversion in injected sequence */
+#define ADC_JSQR_JSQ4_0 ((uint32_t)0x04000000) /*!< ADC JSQ4 bit 0 */
+#define ADC_JSQR_JSQ4_1 ((uint32_t)0x08000000) /*!< ADC JSQ4 bit 1 */
+#define ADC_JSQR_JSQ4_2 ((uint32_t)0x10000000) /*!< ADC JSQ4 bit 2 */
+#define ADC_JSQR_JSQ4_3 ((uint32_t)0x20000000) /*!< ADC JSQ4 bit 3 */
+#define ADC_JSQR_JSQ4_4 ((uint32_t)0x40000000) /*!< ADC JSQ4 bit 4 */
+
+/******************** Bit definition for ADC_OFR1 register ********************/
+#define ADC_OFR1_OFFSET1 ((uint32_t)0x00000FFF) /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
+#define ADC_OFR1_OFFSET1_0 ((uint32_t)0x00000001) /*!< ADC OFFSET1 bit 0 */
+#define ADC_OFR1_OFFSET1_1 ((uint32_t)0x00000002) /*!< ADC OFFSET1 bit 1 */
+#define ADC_OFR1_OFFSET1_2 ((uint32_t)0x00000004) /*!< ADC OFFSET1 bit 2 */
+#define ADC_OFR1_OFFSET1_3 ((uint32_t)0x00000008) /*!< ADC OFFSET1 bit 3 */
+#define ADC_OFR1_OFFSET1_4 ((uint32_t)0x00000010) /*!< ADC OFFSET1 bit 4 */
+#define ADC_OFR1_OFFSET1_5 ((uint32_t)0x00000020) /*!< ADC OFFSET1 bit 5 */
+#define ADC_OFR1_OFFSET1_6 ((uint32_t)0x00000040) /*!< ADC OFFSET1 bit 6 */
+#define ADC_OFR1_OFFSET1_7 ((uint32_t)0x00000080) /*!< ADC OFFSET1 bit 7 */
+#define ADC_OFR1_OFFSET1_8 ((uint32_t)0x00000100) /*!< ADC OFFSET1 bit 8 */
+#define ADC_OFR1_OFFSET1_9 ((uint32_t)0x00000200) /*!< ADC OFFSET1 bit 9 */
+#define ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400) /*!< ADC OFFSET1 bit 10 */
+#define ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800) /*!< ADC OFFSET1 bit 11 */
+
+#define ADC_OFR1_OFFSET1_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 1 */
+#define ADC_OFR1_OFFSET1_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET1_CH bit 0 */
+#define ADC_OFR1_OFFSET1_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET1_CH bit 1 */
+#define ADC_OFR1_OFFSET1_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET1_CH bit 2 */
+#define ADC_OFR1_OFFSET1_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET1_CH bit 3 */
+#define ADC_OFR1_OFFSET1_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET1_CH bit 4 */
+
+#define ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000) /*!< ADC offset 1 enable */
+
+/******************** Bit definition for ADC_OFR2 register ********************/
+#define ADC_OFR2_OFFSET2 ((uint32_t)0x00000FFF) /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
+#define ADC_OFR2_OFFSET2_0 ((uint32_t)0x00000001) /*!< ADC OFFSET2 bit 0 */
+#define ADC_OFR2_OFFSET2_1 ((uint32_t)0x00000002) /*!< ADC OFFSET2 bit 1 */
+#define ADC_OFR2_OFFSET2_2 ((uint32_t)0x00000004) /*!< ADC OFFSET2 bit 2 */
+#define ADC_OFR2_OFFSET2_3 ((uint32_t)0x00000008) /*!< ADC OFFSET2 bit 3 */
+#define ADC_OFR2_OFFSET2_4 ((uint32_t)0x00000010) /*!< ADC OFFSET2 bit 4 */
+#define ADC_OFR2_OFFSET2_5 ((uint32_t)0x00000020) /*!< ADC OFFSET2 bit 5 */
+#define ADC_OFR2_OFFSET2_6 ((uint32_t)0x00000040) /*!< ADC OFFSET2 bit 6 */
+#define ADC_OFR2_OFFSET2_7 ((uint32_t)0x00000080) /*!< ADC OFFSET2 bit 7 */
+#define ADC_OFR2_OFFSET2_8 ((uint32_t)0x00000100) /*!< ADC OFFSET2 bit 8 */
+#define ADC_OFR2_OFFSET2_9 ((uint32_t)0x00000200) /*!< ADC OFFSET2 bit 9 */
+#define ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400) /*!< ADC OFFSET2 bit 10 */
+#define ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800) /*!< ADC OFFSET2 bit 11 */
+
+#define ADC_OFR2_OFFSET2_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 2 */
+#define ADC_OFR2_OFFSET2_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET2_CH bit 0 */
+#define ADC_OFR2_OFFSET2_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET2_CH bit 1 */
+#define ADC_OFR2_OFFSET2_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET2_CH bit 2 */
+#define ADC_OFR2_OFFSET2_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET2_CH bit 3 */
+#define ADC_OFR2_OFFSET2_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET2_CH bit 4 */
+
+#define ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000) /*!< ADC offset 2 enable */
+
+/******************** Bit definition for ADC_OFR3 register ********************/
+#define ADC_OFR3_OFFSET3 ((uint32_t)0x00000FFF) /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
+#define ADC_OFR3_OFFSET3_0 ((uint32_t)0x00000001) /*!< ADC OFFSET3 bit 0 */
+#define ADC_OFR3_OFFSET3_1 ((uint32_t)0x00000002) /*!< ADC OFFSET3 bit 1 */
+#define ADC_OFR3_OFFSET3_2 ((uint32_t)0x00000004) /*!< ADC OFFSET3 bit 2 */
+#define ADC_OFR3_OFFSET3_3 ((uint32_t)0x00000008) /*!< ADC OFFSET3 bit 3 */
+#define ADC_OFR3_OFFSET3_4 ((uint32_t)0x00000010) /*!< ADC OFFSET3 bit 4 */
+#define ADC_OFR3_OFFSET3_5 ((uint32_t)0x00000020) /*!< ADC OFFSET3 bit 5 */
+#define ADC_OFR3_OFFSET3_6 ((uint32_t)0x00000040) /*!< ADC OFFSET3 bit 6 */
+#define ADC_OFR3_OFFSET3_7 ((uint32_t)0x00000080) /*!< ADC OFFSET3 bit 7 */
+#define ADC_OFR3_OFFSET3_8 ((uint32_t)0x00000100) /*!< ADC OFFSET3 bit 8 */
+#define ADC_OFR3_OFFSET3_9 ((uint32_t)0x00000200) /*!< ADC OFFSET3 bit 9 */
+#define ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400) /*!< ADC OFFSET3 bit 10 */
+#define ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800) /*!< ADC OFFSET3 bit 11 */
+
+#define ADC_OFR3_OFFSET3_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 3 */
+#define ADC_OFR3_OFFSET3_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET3_CH bit 0 */
+#define ADC_OFR3_OFFSET3_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET3_CH bit 1 */
+#define ADC_OFR3_OFFSET3_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET3_CH bit 2 */
+#define ADC_OFR3_OFFSET3_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET3_CH bit 3 */
+#define ADC_OFR3_OFFSET3_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET3_CH bit 4 */
+
+#define ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000) /*!< ADC offset 3 enable */
+
+/******************** Bit definition for ADC_OFR4 register ********************/
+#define ADC_OFR4_OFFSET4 ((uint32_t)0x00000FFF) /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
+#define ADC_OFR4_OFFSET4_0 ((uint32_t)0x00000001) /*!< ADC OFFSET4 bit 0 */
+#define ADC_OFR4_OFFSET4_1 ((uint32_t)0x00000002) /*!< ADC OFFSET4 bit 1 */
+#define ADC_OFR4_OFFSET4_2 ((uint32_t)0x00000004) /*!< ADC OFFSET4 bit 2 */
+#define ADC_OFR4_OFFSET4_3 ((uint32_t)0x00000008) /*!< ADC OFFSET4 bit 3 */
+#define ADC_OFR4_OFFSET4_4 ((uint32_t)0x00000010) /*!< ADC OFFSET4 bit 4 */
+#define ADC_OFR4_OFFSET4_5 ((uint32_t)0x00000020) /*!< ADC OFFSET4 bit 5 */
+#define ADC_OFR4_OFFSET4_6 ((uint32_t)0x00000040) /*!< ADC OFFSET4 bit 6 */
+#define ADC_OFR4_OFFSET4_7 ((uint32_t)0x00000080) /*!< ADC OFFSET4 bit 7 */
+#define ADC_OFR4_OFFSET4_8 ((uint32_t)0x00000100) /*!< ADC OFFSET4 bit 8 */
+#define ADC_OFR4_OFFSET4_9 ((uint32_t)0x00000200) /*!< ADC OFFSET4 bit 9 */
+#define ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400) /*!< ADC OFFSET4 bit 10 */
+#define ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800) /*!< ADC OFFSET4 bit 11 */
+
+#define ADC_OFR4_OFFSET4_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 4 */
+#define ADC_OFR4_OFFSET4_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET4_CH bit 0 */
+#define ADC_OFR4_OFFSET4_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET4_CH bit 1 */
+#define ADC_OFR4_OFFSET4_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET4_CH bit 2 */
+#define ADC_OFR4_OFFSET4_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET4_CH bit 3 */
+#define ADC_OFR4_OFFSET4_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET4_CH bit 4 */
+
+#define ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000) /*!< ADC offset 4 enable */
+
+/******************** Bit definition for ADC_JDR1 register ********************/
+#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
+#define ADC_JDR1_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
+#define ADC_JDR1_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
+#define ADC_JDR1_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
+#define ADC_JDR1_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
+#define ADC_JDR1_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
+#define ADC_JDR1_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
+#define ADC_JDR1_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
+#define ADC_JDR1_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
+#define ADC_JDR1_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
+#define ADC_JDR1_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
+#define ADC_JDR1_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
+#define ADC_JDR1_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
+#define ADC_JDR1_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
+#define ADC_JDR1_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
+#define ADC_JDR1_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
+#define ADC_JDR1_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
+
+/******************** Bit definition for ADC_JDR2 register ********************/
+#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
+#define ADC_JDR2_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
+#define ADC_JDR2_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
+#define ADC_JDR2_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
+#define ADC_JDR2_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
+#define ADC_JDR2_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
+#define ADC_JDR2_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
+#define ADC_JDR2_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
+#define ADC_JDR2_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
+#define ADC_JDR2_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
+#define ADC_JDR2_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
+#define ADC_JDR2_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
+#define ADC_JDR2_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
+#define ADC_JDR2_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
+#define ADC_JDR2_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
+#define ADC_JDR2_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
+#define ADC_JDR2_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
+
+/******************** Bit definition for ADC_JDR3 register ********************/
+#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
+#define ADC_JDR3_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
+#define ADC_JDR3_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
+#define ADC_JDR3_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
+#define ADC_JDR3_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
+#define ADC_JDR3_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
+#define ADC_JDR3_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
+#define ADC_JDR3_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
+#define ADC_JDR3_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
+#define ADC_JDR3_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
+#define ADC_JDR3_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
+#define ADC_JDR3_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
+#define ADC_JDR3_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
+#define ADC_JDR3_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
+#define ADC_JDR3_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
+#define ADC_JDR3_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
+#define ADC_JDR3_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
+
+/******************** Bit definition for ADC_JDR4 register ********************/
+#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
+#define ADC_JDR4_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
+#define ADC_JDR4_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
+#define ADC_JDR4_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
+#define ADC_JDR4_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
+#define ADC_JDR4_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
+#define ADC_JDR4_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
+#define ADC_JDR4_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
+#define ADC_JDR4_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
+#define ADC_JDR4_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
+#define ADC_JDR4_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
+#define ADC_JDR4_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
+#define ADC_JDR4_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
+#define ADC_JDR4_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
+#define ADC_JDR4_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
+#define ADC_JDR4_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
+#define ADC_JDR4_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
+
+/******************** Bit definition for ADC_AWD2CR register ********************/
+#define ADC_AWD2CR_AWD2CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
+#define ADC_AWD2CR_AWD2CH_0 ((uint32_t)0x00000002) /*!< ADC AWD2CH bit 0 */
+#define ADC_AWD2CR_AWD2CH_1 ((uint32_t)0x00000004) /*!< ADC AWD2CH bit 1 */
+#define ADC_AWD2CR_AWD2CH_2 ((uint32_t)0x00000008) /*!< ADC AWD2CH bit 2 */
+#define ADC_AWD2CR_AWD2CH_3 ((uint32_t)0x00000010) /*!< ADC AWD2CH bit 3 */
+#define ADC_AWD2CR_AWD2CH_4 ((uint32_t)0x00000020) /*!< ADC AWD2CH bit 4 */
+#define ADC_AWD2CR_AWD2CH_5 ((uint32_t)0x00000040) /*!< ADC AWD2CH bit 5 */
+#define ADC_AWD2CR_AWD2CH_6 ((uint32_t)0x00000080) /*!< ADC AWD2CH bit 6 */
+#define ADC_AWD2CR_AWD2CH_7 ((uint32_t)0x00000100) /*!< ADC AWD2CH bit 7 */
+#define ADC_AWD2CR_AWD2CH_8 ((uint32_t)0x00000200) /*!< ADC AWD2CH bit 8 */
+#define ADC_AWD2CR_AWD2CH_9 ((uint32_t)0x00000400) /*!< ADC AWD2CH bit 9 */
+#define ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000800) /*!< ADC AWD2CH bit 10 */
+#define ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00001000) /*!< ADC AWD2CH bit 11 */
+#define ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00002000) /*!< ADC AWD2CH bit 12 */
+#define ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00004000) /*!< ADC AWD2CH bit 13 */
+#define ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00008000) /*!< ADC AWD2CH bit 14 */
+#define ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00010000) /*!< ADC AWD2CH bit 15 */
+#define ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00020000) /*!< ADC AWD2CH bit 16 */
+#define ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00030000) /*!< ADC AWD2CH bit 17 */
+
+/******************** Bit definition for ADC_AWD3CR register ********************/
+#define ADC_AWD3CR_AWD3CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
+#define ADC_AWD3CR_AWD3CH_0 ((uint32_t)0x00000002) /*!< ADC AWD3CH bit 0 */
+#define ADC_AWD3CR_AWD3CH_1 ((uint32_t)0x00000004) /*!< ADC AWD3CH bit 1 */
+#define ADC_AWD3CR_AWD3CH_2 ((uint32_t)0x00000008) /*!< ADC AWD3CH bit 2 */
+#define ADC_AWD3CR_AWD3CH_3 ((uint32_t)0x00000010) /*!< ADC AWD3CH bit 3 */
+#define ADC_AWD3CR_AWD3CH_4 ((uint32_t)0x00000020) /*!< ADC AWD3CH bit 4 */
+#define ADC_AWD3CR_AWD3CH_5 ((uint32_t)0x00000040) /*!< ADC AWD3CH bit 5 */
+#define ADC_AWD3CR_AWD3CH_6 ((uint32_t)0x00000080) /*!< ADC AWD3CH bit 6 */
+#define ADC_AWD3CR_AWD3CH_7 ((uint32_t)0x00000100) /*!< ADC AWD3CH bit 7 */
+#define ADC_AWD3CR_AWD3CH_8 ((uint32_t)0x00000200) /*!< ADC AWD3CH bit 8 */
+#define ADC_AWD3CR_AWD3CH_9 ((uint32_t)0x00000400) /*!< ADC AWD3CH bit 9 */
+#define ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000800) /*!< ADC AWD3CH bit 10 */
+#define ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00001000) /*!< ADC AWD3CH bit 11 */
+#define ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00002000) /*!< ADC AWD3CH bit 12 */
+#define ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00004000) /*!< ADC AWD3CH bit 13 */
+#define ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00008000) /*!< ADC AWD3CH bit 14 */
+#define ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00010000) /*!< ADC AWD3CH bit 15 */
+#define ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00020000) /*!< ADC AWD3CH bit 16 */
+#define ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00030000) /*!< ADC AWD3CH bit 17 */
+
+/******************** Bit definition for ADC_DIFSEL register ********************/
+#define ADC_DIFSEL_DIFSEL ((uint32_t)0x0007FFFE) /*!< ADC differential modes for channels 1 to 18 */
+#define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000002) /*!< ADC DIFSEL bit 0 */
+#define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000004) /*!< ADC DIFSEL bit 1 */
+#define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000008) /*!< ADC DIFSEL bit 2 */
+#define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000010) /*!< ADC DIFSEL bit 3 */
+#define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000020) /*!< ADC DIFSEL bit 4 */
+#define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000040) /*!< ADC DIFSEL bit 5 */
+#define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000080) /*!< ADC DIFSEL bit 6 */
+#define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000100) /*!< ADC DIFSEL bit 7 */
+#define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000200) /*!< ADC DIFSEL bit 8 */
+#define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000400) /*!< ADC DIFSEL bit 9 */
+#define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000800) /*!< ADC DIFSEL bit 10 */
+#define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00001000) /*!< ADC DIFSEL bit 11 */
+#define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00002000) /*!< ADC DIFSEL bit 12 */
+#define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00004000) /*!< ADC DIFSEL bit 13 */
+#define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00008000) /*!< ADC DIFSEL bit 14 */
+#define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00010000) /*!< ADC DIFSEL bit 15 */
+#define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00020000) /*!< ADC DIFSEL bit 16 */
+#define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00030000) /*!< ADC DIFSEL bit 17 */
+
+/******************** Bit definition for ADC_CALFACT register ********************/
+#define ADC_CALFACT_CALFACT_S ((uint32_t)0x0000007F) /*!< ADC calibration factors in single-ended mode */
+#define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001) /*!< ADC CALFACT_S bit 0 */
+#define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002) /*!< ADC CALFACT_S bit 1 */
+#define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004) /*!< ADC CALFACT_S bit 2 */
+#define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008) /*!< ADC CALFACT_S bit 3 */
+#define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010) /*!< ADC CALFACT_S bit 4 */
+#define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020) /*!< ADC CALFACT_S bit 5 */
+#define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040) /*!< ADC CALFACT_S bit 6 */
+#define ADC_CALFACT_CALFACT_D ((uint32_t)0x007F0000) /*!< ADC calibration factors in differential mode */
+#define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000) /*!< ADC CALFACT_D bit 0 */
+#define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000) /*!< ADC CALFACT_D bit 1 */
+#define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000) /*!< ADC CALFACT_D bit 2 */
+#define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000) /*!< ADC CALFACT_D bit 3 */
+#define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000) /*!< ADC CALFACT_D bit 4 */
+#define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000) /*!< ADC CALFACT_D bit 5 */
+#define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000) /*!< ADC CALFACT_D bit 6 */
+
+/************************* ADC Common registers *****************************/
+/******************** Bit definition for ADC12_CSR register ********************/
+#define ADC12_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */
+#define ADC12_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */
+#define ADC12_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */
+#define ADC12_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */
+#define ADC12_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */
+#define ADC12_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */
+#define ADC12_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */
+#define ADC12_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */
+#define ADC12_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */
+#define ADC12_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */
+#define ADC12_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */
+#define ADC12_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */
+#define ADC12_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */
+#define ADC12_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */
+#define ADC12_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */
+#define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */
+#define ADC12_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */
+#define ADC12_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */
+#define ADC12_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */
+#define ADC12_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */
+#define ADC12_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */
+#define ADC12_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */
+
+/******************** Bit definition for ADC34_CSR register ********************/
+#define ADC34_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */
+#define ADC34_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */
+#define ADC34_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */
+#define ADC34_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */
+#define ADC34_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */
+#define ADC34_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */
+#define ADC34_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */
+#define ADC34_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */
+#define ADC34_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */
+#define ADC34_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */
+#define ADC34_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */
+#define ADC34_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */
+#define ADC34_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */
+#define ADC34_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */
+#define ADC34_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */
+#define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */
+#define ADC34_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */
+#define ADC34_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */
+#define ADC34_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */
+#define ADC34_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */
+#define ADC34_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */
+#define ADC34_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */
+
+/******************** Bit definition for ADC_CCR register ********************/
+#define ADC12_CCR_MULTI ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */
+#define ADC12_CCR_MULTI_0 ((uint32_t)0x00000001) /*!< MULTI bit 0 */
+#define ADC12_CCR_MULTI_1 ((uint32_t)0x00000002) /*!< MULTI bit 1 */
+#define ADC12_CCR_MULTI_2 ((uint32_t)0x00000004) /*!< MULTI bit 2 */
+#define ADC12_CCR_MULTI_3 ((uint32_t)0x00000008) /*!< MULTI bit 3 */
+#define ADC12_CCR_MULTI_4 ((uint32_t)0x00000010) /*!< MULTI bit 4 */
+#define ADC12_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */
+#define ADC12_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */
+#define ADC12_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */
+#define ADC12_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */
+#define ADC12_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */
+#define ADC12_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */
+#define ADC12_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */
+#define ADC12_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */
+#define ADC12_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */
+#define ADC12_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */
+#define ADC12_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */
+#define ADC12_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */
+#define ADC12_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */
+#define ADC12_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensor enable */
+#define ADC12_CCR_VBATEN ((uint32_t)0x01000000) /*!< VBAT enable */
+
+/******************** Bit definition for ADC_CCR register ********************/
+#define ADC34_CCR_MULTI ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */
+#define ADC34_CCR_MULTI_0 ((uint32_t)0x00000001) /*!< MULTI bit 0 */
+#define ADC34_CCR_MULTI_1 ((uint32_t)0x00000002) /*!< MULTI bit 1 */
+#define ADC34_CCR_MULTI_2 ((uint32_t)0x00000004) /*!< MULTI bit 2 */
+#define ADC34_CCR_MULTI_3 ((uint32_t)0x00000008) /*!< MULTI bit 3 */
+#define ADC34_CCR_MULTI_4 ((uint32_t)0x00000010) /*!< MULTI bit 4 */
+
+#define ADC34_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */
+#define ADC34_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */
+#define ADC34_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */
+#define ADC34_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */
+#define ADC34_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */
+
+#define ADC34_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */
+#define ADC34_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */
+#define ADC34_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */
+#define ADC34_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */
+
+#define ADC34_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */
+#define ADC34_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */
+#define ADC34_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */
+
+#define ADC34_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */
+
+/******************** Bit definition for ADC_CDR register ********************/
+#define ADC12_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */
+#define ADC12_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */
+#define ADC12_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */
+#define ADC12_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */
+#define ADC12_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */
+#define ADC12_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */
+#define ADC12_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */
+#define ADC12_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */
+#define ADC12_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */
+#define ADC12_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */
+#define ADC12_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */
+#define ADC12_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */
+#define ADC12_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */
+#define ADC12_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */
+#define ADC12_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */
+#define ADC12_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */
+#define ADC12_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */
+
+#define ADC12_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */
+#define ADC12_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */
+#define ADC12_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */
+#define ADC12_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */
+#define ADC12_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */
+#define ADC12_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */
+#define ADC12_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */
+#define ADC12_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */
+#define ADC12_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */
+#define ADC12_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */
+#define ADC12_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */
+#define ADC12_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */
+#define ADC12_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */
+#define ADC12_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */
+#define ADC12_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */
+#define ADC12_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */
+#define ADC12_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */
+
+/******************** Bit definition for ADC_CDR register ********************/
+#define ADC34_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */
+#define ADC34_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */
+#define ADC34_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */
+#define ADC34_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */
+#define ADC34_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */
+#define ADC34_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */
+#define ADC34_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */
+#define ADC34_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */
+#define ADC34_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */
+#define ADC34_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */
+#define ADC34_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */
+#define ADC34_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */
+#define ADC34_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */
+#define ADC34_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */
+#define ADC34_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */
+#define ADC34_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */
+#define ADC34_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */
+
+#define ADC34_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */
+#define ADC34_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */
+#define ADC34_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */
+#define ADC34_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */
+#define ADC34_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */
+#define ADC34_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */
+#define ADC34_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */
+#define ADC34_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */
+#define ADC34_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */
+#define ADC34_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */
+#define ADC34_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */
+#define ADC34_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */
+#define ADC34_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */
+#define ADC34_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */
+#define ADC34_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */
+#define ADC34_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */
+#define ADC34_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */
+
+/******************************************************************************/
+/* */
+/* Analog Comparators (COMP) */
+/* */
+/******************************************************************************/
+/********************** Bit definition for COMP1_CSR register ***************/
+#define COMP1_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
+#define COMP1_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */
+#define COMP1_CSR_COMP1MODE ((uint32_t)0x0000000C) /*!< COMP1 power mode */
+#define COMP1_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */
+#define COMP1_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */
+#define COMP1_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
+#define COMP1_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
+#define COMP1_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
+#define COMP1_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
+#define COMP1_CSR_COMP1NONINSEL ((uint32_t)0x00000080) /*!< COMP1 non inverting input select */
+#define COMP1_CSR_COMP1OUTSEL ((uint32_t)0x00003C00) /*!< COMP1 output select */
+#define COMP1_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP1 output select bit 0 */
+#define COMP1_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP1 output select bit 1 */
+#define COMP1_CSR_COMP1OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP1 output select bit 2 */
+#define COMP1_CSR_COMP1OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP1 output select bit 3 */
+#define COMP1_CSR_COMP1POL ((uint32_t)0x00008000) /*!< COMP1 output polarity */
+#define COMP1_CSR_COMP1HYST ((uint32_t)0x00030000) /*!< COMP1 hysteresis */
+#define COMP1_CSR_COMP1HYST_0 ((uint32_t)0x00010000) /*!< COMP1 hysteresis bit 0 */
+#define COMP1_CSR_COMP1HYST_1 ((uint32_t)0x00020000) /*!< COMP1 hysteresis bit 1 */
+#define COMP1_CSR_COMP1BLANKING ((uint32_t)0x000C0000) /*!< COMP1 blanking */
+#define COMP1_CSR_COMP1BLANKING_0 ((uint32_t)0x00040000) /*!< COMP1 blanking bit 0 */
+#define COMP1_CSR_COMP1BLANKING_1 ((uint32_t)0x00080000) /*!< COMP1 blanking bit 1 */
+#define COMP1_CSR_COMP1BLANKING_2 ((uint32_t)0x00100000) /*!< COMP1 blanking bit 2 */
+#define COMP1_CSR_COMP1OUT ((uint32_t)0x40000000) /*!< COMP1 output level */
+#define COMP1_CSR_COMP1LOCK ((uint32_t)0x80000000) /*!< COMP1 lock */
+
+/********************** Bit definition for COMP2_CSR register ***************/
+#define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
+#define COMP2_CSR_COMP2MODE ((uint32_t)0x0000000C) /*!< COMP2 power mode */
+#define COMP2_CSR_COMP2MODE_0 ((uint32_t)0x00000004) /*!< COMP2 power mode bit 0 */
+#define COMP2_CSR_COMP2MODE_1 ((uint32_t)0x00000008) /*!< COMP2 power mode bit 1 */
+#define COMP2_CSR_COMP2INSEL ((uint32_t)0x00000070) /*!< COMP2 inverting input select */
+#define COMP2_CSR_COMP2INSEL_0 ((uint32_t)0x00000010) /*!< COMP2 inverting input select bit 0 */
+#define COMP2_CSR_COMP2INSEL_1 ((uint32_t)0x00000020) /*!< COMP2 inverting input select bit 1 */
+#define COMP2_CSR_COMP2INSEL_2 ((uint32_t)0x00000040) /*!< COMP2 inverting input select bit 2 */
+#define COMP2_CSR_COMP2NONINSEL ((uint32_t)0x00000080) /*!< COMP2 non inverting input select */
+#define COMP2_CSR_COMP2WNDWEN ((uint32_t)0x00000200) /*!< COMP2 window mode enable */
+#define COMP2_CSR_COMP2OUTSEL ((uint32_t)0x00003C00) /*!< COMP2 output select */
+#define COMP2_CSR_COMP2OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP2 output select bit 0 */
+#define COMP2_CSR_COMP2OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP2 output select bit 1 */
+#define COMP2_CSR_COMP2OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP2 output select bit 2 */
+#define COMP2_CSR_COMP2OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP2 output select bit 3 */
+#define COMP2_CSR_COMP2POL ((uint32_t)0x00008000) /*!< COMP2 output polarity */
+#define COMP2_CSR_COMP2HYST ((uint32_t)0x00030000) /*!< COMP2 hysteresis */
+#define COMP2_CSR_COMP2HYST_0 ((uint32_t)0x00010000) /*!< COMP2 hysteresis bit 0 */
+#define COMP2_CSR_COMP2HYST_1 ((uint32_t)0x00020000) /*!< COMP2 hysteresis bit 1 */
+#define COMP2_CSR_COMP2BLANKING ((uint32_t)0x000C0000) /*!< COMP2 blanking */
+#define COMP2_CSR_COMP2BLANKING_0 ((uint32_t)0x00040000) /*!< COMP2 blanking bit 0 */
+#define COMP2_CSR_COMP2BLANKING_1 ((uint32_t)0x00080000) /*!< COMP2 blanking bit 1 */
+#define COMP2_CSR_COMP2BLANKING_2 ((uint32_t)0x00100000) /*!< COMP2 blanking bit 2 */
+#define COMP2_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
+#define COMP2_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
+
+/********************** Bit definition for COMP3_CSR register ***************/
+#define COMP3_CSR_COMP3EN ((uint32_t)0x00000001) /*!< COMP3 enable */
+#define COMP3_CSR_COMP3MODE ((uint32_t)0x0000000C) /*!< COMP3 power mode */
+#define COMP3_CSR_COMP3MODE_0 ((uint32_t)0x00000004) /*!< COMP3 power mode bit 0 */
+#define COMP3_CSR_COMP3MODE_1 ((uint32_t)0x00000008) /*!< COMP3 power mode bit 1 */
+#define COMP3_CSR_COMP3INSEL ((uint32_t)0x00000070) /*!< COMP3 inverting input select */
+#define COMP3_CSR_COMP3INSEL_0 ((uint32_t)0x00000010) /*!< COMP3 inverting input select bit 0 */
+#define COMP3_CSR_COMP3INSEL_1 ((uint32_t)0x00000020) /*!< COMP3 inverting input select bit 1 */
+#define COMP3_CSR_COMP3INSEL_2 ((uint32_t)0x00000040) /*!< COMP3 inverting input select bit 2 */
+#define COMP3_CSR_COMP3NONINSEL ((uint32_t)0x00000080) /*!< COMP3 non inverting input select */
+#define COMP3_CSR_COMP3OUTSEL ((uint32_t)0x00003C00) /*!< COMP3 output select */
+#define COMP3_CSR_COMP3OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP3 output select bit 0 */
+#define COMP3_CSR_COMP3OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP3 output select bit 1 */
+#define COMP3_CSR_COMP3OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP3 output select bit 2 */
+#define COMP3_CSR_COMP3OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP3 output select bit 3 */
+#define COMP3_CSR_COMP3POL ((uint32_t)0x00008000) /*!< COMP3 output polarity */
+#define COMP3_CSR_COMP3HYST ((uint32_t)0x00030000) /*!< COMP3 hysteresis */
+#define COMP3_CSR_COMP3HYST_0 ((uint32_t)0x00010000) /*!< COMP3 hysteresis bit 0 */
+#define COMP3_CSR_COMP3HYST_1 ((uint32_t)0x00020000) /*!< COMP3 hysteresis bit 1 */
+#define COMP3_CSR_COMP3BLANKING ((uint32_t)0x000C0000) /*!< COMP3 blanking */
+#define COMP3_CSR_COMP3BLANKING_0 ((uint32_t)0x00040000) /*!< COMP3 blanking bit 0 */
+#define COMP3_CSR_COMP3BLANKING_1 ((uint32_t)0x00080000) /*!< COMP3 blanking bit 1 */
+#define COMP3_CSR_COMP3BLANKING_2 ((uint32_t)0x00100000) /*!< COMP3 blanking bit 2 */
+#define COMP3_CSR_COMP3OUT ((uint32_t)0x40000000) /*!< COMP3 output level */
+#define COMP3_CSR_COMP3LOCK ((uint32_t)0x80000000) /*!< COMP3 lock */
+
+/********************** Bit definition for COMP4_CSR register ***************/
+#define COMP4_CSR_COMP4EN ((uint32_t)0x00000001) /*!< COMP4 enable */
+#define COMP4_CSR_COMP4MODE ((uint32_t)0x0000000C) /*!< COMP4 power mode */
+#define COMP4_CSR_COMP4MODE_0 ((uint32_t)0x00000004) /*!< COMP4 power mode bit 0 */
+#define COMP4_CSR_COMP4MODE_1 ((uint32_t)0x00000008) /*!< COMP4 power mode bit 1 */
+#define COMP4_CSR_COMP4INSEL ((uint32_t)0x00000070) /*!< COMP4 inverting input select */
+#define COMP4_CSR_COMP4INSEL_0 ((uint32_t)0x00000010) /*!< COMP4 inverting input select bit 0 */
+#define COMP4_CSR_COMP4INSEL_1 ((uint32_t)0x00000020) /*!< COMP4 inverting input select bit 1 */
+#define COMP4_CSR_COMP4INSEL_2 ((uint32_t)0x00000040) /*!< COMP4 inverting input select bit 2 */
+#define COMP4_CSR_COMP4NONINSEL ((uint32_t)0x00000080) /*!< COMP4 non inverting input select */
+#define COMP4_CSR_COMP4WNDWEN ((uint32_t)0x00000200) /*!< COMP4 window mode enable */
+#define COMP4_CSR_COMP4OUTSEL ((uint32_t)0x00003C00) /*!< COMP4 output select */
+#define COMP4_CSR_COMP4OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP4 output select bit 0 */
+#define COMP4_CSR_COMP4OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP4 output select bit 1 */
+#define COMP4_CSR_COMP4OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP4 output select bit 2 */
+#define COMP4_CSR_COMP4OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP4 output select bit 3 */
+#define COMP4_CSR_COMP4POL ((uint32_t)0x00008000) /*!< COMP4 output polarity */
+#define COMP4_CSR_COMP4HYST ((uint32_t)0x00030000) /*!< COMP4 hysteresis */
+#define COMP4_CSR_COMP4HYST_0 ((uint32_t)0x00010000) /*!< COMP4 hysteresis bit 0 */
+#define COMP4_CSR_COMP4HYST_1 ((uint32_t)0x00020000) /*!< COMP4 hysteresis bit 1 */
+#define COMP4_CSR_COMP4BLANKING ((uint32_t)0x000C0000) /*!< COMP4 blanking */
+#define COMP4_CSR_COMP4BLANKING_0 ((uint32_t)0x00040000) /*!< COMP4 blanking bit 0 */
+#define COMP4_CSR_COMP4BLANKING_1 ((uint32_t)0x00080000) /*!< COMP4 blanking bit 1 */
+#define COMP4_CSR_COMP4BLANKING_2 ((uint32_t)0x00100000) /*!< COMP4 blanking bit 2 */
+#define COMP4_CSR_COMP4OUT ((uint32_t)0x40000000) /*!< COMP4 output level */
+#define COMP4_CSR_COMP4LOCK ((uint32_t)0x80000000) /*!< COMP4 lock */
+
+/********************** Bit definition for COMP5_CSR register ***************/
+#define COMP5_CSR_COMP5EN ((uint32_t)0x00000001) /*!< COMP5 enable */
+#define COMP5_CSR_COMP5MODE ((uint32_t)0x0000000C) /*!< COMP5 power mode */
+#define COMP5_CSR_COMP5MODE_0 ((uint32_t)0x00000004) /*!< COMP5 power mode bit 0 */
+#define COMP5_CSR_COMP5MODE_1 ((uint32_t)0x00000008) /*!< COMP5 power mode bit 1 */
+#define COMP5_CSR_COMP5INSEL ((uint32_t)0x00000070) /*!< COMP5 inverting input select */
+#define COMP5_CSR_COMP5INSEL_0 ((uint32_t)0x00000010) /*!< COMP5 inverting input select bit 0 */
+#define COMP5_CSR_COMP5INSEL_1 ((uint32_t)0x00000020) /*!< COMP5 inverting input select bit 1 */
+#define COMP5_CSR_COMP5INSEL_2 ((uint32_t)0x00000040) /*!< COMP5 inverting input select bit 2 */
+#define COMP5_CSR_COMP5NONINSEL ((uint32_t)0x00000080) /*!< COMP5 non inverting input select */
+#define COMP5_CSR_COMP5OUTSEL ((uint32_t)0x00003C00) /*!< COMP5 output select */
+#define COMP5_CSR_COMP5OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP5 output select bit 0 */
+#define COMP5_CSR_COMP5OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP5 output select bit 1 */
+#define COMP5_CSR_COMP5OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP5 output select bit 2 */
+#define COMP5_CSR_COMP5OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP5 output select bit 3 */
+#define COMP5_CSR_COMP5POL ((uint32_t)0x00008000) /*!< COMP5 output polarity */
+#define COMP5_CSR_COMP5HYST ((uint32_t)0x00030000) /*!< COMP5 hysteresis */
+#define COMP5_CSR_COMP5HYST_0 ((uint32_t)0x00010000) /*!< COMP5 hysteresis bit 0 */
+#define COMP5_CSR_COMP5HYST_1 ((uint32_t)0x00020000) /*!< COMP5 hysteresis bit 1 */
+#define COMP5_CSR_COMP5BLANKING ((uint32_t)0x000C0000) /*!< COMP5 blanking */
+#define COMP5_CSR_COMP5BLANKING_0 ((uint32_t)0x00040000) /*!< COMP5 blanking bit 0 */
+#define COMP5_CSR_COMP5BLANKING_1 ((uint32_t)0x00080000) /*!< COMP5 blanking bit 1 */
+#define COMP5_CSR_COMP5BLANKING_2 ((uint32_t)0x00100000) /*!< COMP5 blanking bit 2 */
+#define COMP5_CSR_COMP5OUT ((uint32_t)0x40000000) /*!< COMP5 output level */
+#define COMP5_CSR_COMP5LOCK ((uint32_t)0x80000000) /*!< COMP5 lock */
+
+/********************** Bit definition for COMP6_CSR register ***************/
+#define COMP6_CSR_COMP6EN ((uint32_t)0x00000001) /*!< COMP6 enable */
+#define COMP6_CSR_COMP6MODE ((uint32_t)0x0000000C) /*!< COMP6 power mode */
+#define COMP6_CSR_COMP6MODE_0 ((uint32_t)0x00000004) /*!< COMP6 power mode bit 0 */
+#define COMP6_CSR_COMP6MODE_1 ((uint32_t)0x00000008) /*!< COMP6 power mode bit 1 */
+#define COMP6_CSR_COMP6INSEL ((uint32_t)0x00000070) /*!< COMP6 inverting input select */
+#define COMP6_CSR_COMP6INSEL_0 ((uint32_t)0x00000010) /*!< COMP6 inverting input select bit 0 */
+#define COMP6_CSR_COMP6INSEL_1 ((uint32_t)0x00000020) /*!< COMP6 inverting input select bit 1 */
+#define COMP6_CSR_COMP6INSEL_2 ((uint32_t)0x00000040) /*!< COMP6 inverting input select bit 2 */
+#define COMP6_CSR_COMP6NONINSEL ((uint32_t)0x00000080) /*!< COMP6 non inverting input select */
+#define COMP6_CSR_COMP6WNDWEN ((uint32_t)0x00000200) /*!< COMP6 window mode enable */
+#define COMP6_CSR_COMP6OUTSEL ((uint32_t)0x00003C00) /*!< COMP6 output select */
+#define COMP6_CSR_COMP6OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP6 output select bit 0 */
+#define COMP6_CSR_COMP6OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP6 output select bit 1 */
+#define COMP6_CSR_COMP6OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP6 output select bit 2 */
+#define COMP6_CSR_COMP6OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP6 output select bit 3 */
+#define COMP6_CSR_COMP6POL ((uint32_t)0x00008000) /*!< COMP6 output polarity */
+#define COMP6_CSR_COMP6HYST ((uint32_t)0x00030000) /*!< COMP6 hysteresis */
+#define COMP6_CSR_COMP6HYST_0 ((uint32_t)0x00010000) /*!< COMP6 hysteresis bit 0 */
+#define COMP6_CSR_COMP6HYST_1 ((uint32_t)0x00020000) /*!< COMP6 hysteresis bit 1 */
+#define COMP6_CSR_COMP6BLANKING ((uint32_t)0x000C0000) /*!< COMP6 blanking */
+#define COMP6_CSR_COMP6BLANKING_0 ((uint32_t)0x00040000) /*!< COMP6 blanking bit 0 */
+#define COMP6_CSR_COMP6BLANKING_1 ((uint32_t)0x00080000) /*!< COMP6 blanking bit 1 */
+#define COMP6_CSR_COMP6BLANKING_2 ((uint32_t)0x00100000) /*!< COMP6 blanking bit 2 */
+#define COMP6_CSR_COMP6OUT ((uint32_t)0x40000000) /*!< COMP6 output level */
+#define COMP6_CSR_COMP6LOCK ((uint32_t)0x80000000) /*!< COMP6 lock */
+
+/********************** Bit definition for COMP7_CSR register ***************/
+#define COMP7_CSR_COMP7EN ((uint32_t)0x00000001) /*!< COMP7 enable */
+#define COMP7_CSR_COMP7MODE ((uint32_t)0x0000000C) /*!< COMP7 power mode */
+#define COMP7_CSR_COMP7MODE_0 ((uint32_t)0x00000004) /*!< COMP7 power mode bit 0 */
+#define COMP7_CSR_COMP7MODE_1 ((uint32_t)0x00000008) /*!< COMP7 power mode bit 1 */
+#define COMP7_CSR_COMP7INSEL ((uint32_t)0x00000070) /*!< COMP7 inverting input select */
+#define COMP7_CSR_COMP7INSEL_0 ((uint32_t)0x00000010) /*!< COMP7 inverting input select bit 0 */
+#define COMP7_CSR_COMP7INSEL_1 ((uint32_t)0x00000020) /*!< COMP7 inverting input select bit 1 */
+#define COMP7_CSR_COMP7INSEL_2 ((uint32_t)0x00000040) /*!< COMP7 inverting input select bit 2 */
+#define COMP7_CSR_COMP7NONINSEL ((uint32_t)0x00000080) /*!< COMP7 non inverting input select */
+#define COMP7_CSR_COMP7OUTSEL ((uint32_t)0x00003C00) /*!< COMP7 output select */
+#define COMP7_CSR_COMP7OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP7 output select bit 0 */
+#define COMP7_CSR_COMP7OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP7 output select bit 1 */
+#define COMP7_CSR_COMP7OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP7 output select bit 2 */
+#define COMP7_CSR_COMP7OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP7 output select bit 3 */
+#define COMP7_CSR_COMP7POL ((uint32_t)0x00008000) /*!< COMP7 output polarity */
+#define COMP7_CSR_COMP7HYST ((uint32_t)0x00030000) /*!< COMP7 hysteresis */
+#define COMP7_CSR_COMP7HYST_0 ((uint32_t)0x00010000) /*!< COMP7 hysteresis bit 0 */
+#define COMP7_CSR_COMP7HYST_1 ((uint32_t)0x00020000) /*!< COMP7 hysteresis bit 1 */
+#define COMP7_CSR_COMP7BLANKING ((uint32_t)0x000C0000) /*!< COMP7 blanking */
+#define COMP7_CSR_COMP7BLANKING_0 ((uint32_t)0x00040000) /*!< COMP7 blanking bit 0 */
+#define COMP7_CSR_COMP7BLANKING_1 ((uint32_t)0x00080000) /*!< COMP7 blanking bit 1 */
+#define COMP7_CSR_COMP7BLANKING_2 ((uint32_t)0x00100000) /*!< COMP7 blanking bit 2 */
+#define COMP7_CSR_COMP7OUT ((uint32_t)0x40000000) /*!< COMP7 output level */
+#define COMP7_CSR_COMP7LOCK ((uint32_t)0x80000000) /*!< COMP7 lock */
+
+/********************** Bit definition for COMP_CSR register ****************/
+#define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
+#define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */
+#define COMP_CSR_COMPxMODE ((uint32_t)0x0000000C) /*!< COMPx power mode */
+#define COMP_CSR_COMPxMODE_0 ((uint32_t)0x00000004) /*!< COMPx power mode bit 0 */
+#define COMP_CSR_COMPxMODE_1 ((uint32_t)0x00000008) /*!< COMPx power mode bit 1 */
+#define COMP_CSR_COMPxINSEL ((uint32_t)0x00000070) /*!< COMPx inverting input select */
+#define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */
+#define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */
+#define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */
+#define COMP_CSR_COMPxNONINSEL ((uint32_t)0x00000080) /*!< COMPx non inverting input select */
+#define COMP_CSR_COMPxWNDWEN ((uint32_t)0x00000200) /*!< COMPx window mode enable */
+#define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00003C00) /*!< COMPx output select */
+#define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000400) /*!< COMPx output select bit 0 */
+#define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000800) /*!< COMPx output select bit 1 */
+#define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00001000) /*!< COMPx output select bit 2 */
+#define COMP_CSR_COMPxOUTSEL_3 ((uint32_t)0x00002000) /*!< COMPx output select bit 3 */
+#define COMP_CSR_COMPxPOL ((uint32_t)0x00008000) /*!< COMPx output polarity */
+#define COMP_CSR_COMPxHYST ((uint32_t)0x00030000) /*!< COMPx hysteresis */
+#define COMP_CSR_COMPxHYST_0 ((uint32_t)0x00010000) /*!< COMPx hysteresis bit 0 */
+#define COMP_CSR_COMPxHYST_1 ((uint32_t)0x00020000) /*!< COMPx hysteresis bit 1 */
+#define COMP_CSR_COMPxBLANKING ((uint32_t)0x000C0000) /*!< COMPx blanking */
+#define COMP_CSR_COMPxBLANKING_0 ((uint32_t)0x00040000) /*!< COMPx blanking bit 0 */
+#define COMP_CSR_COMPxBLANKING_1 ((uint32_t)0x00080000) /*!< COMPx blanking bit 1 */
+#define COMP_CSR_COMPxBLANKING_2 ((uint32_t)0x00100000) /*!< COMPx blanking bit 2 */
+#define COMP_CSR_COMPxINSEL_3 ((uint32_t)0x00400000) /*!< COMPx inverting input select bit 3 */
+#define COMP_CSR_COMPxOUT ((uint32_t)0x40000000) /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /*!< COMPx lock */
+
+/******************************************************************************/
+/* */
+/* Operational Amplifier (OPAMP) */
+/* */
+/******************************************************************************/
+/********************* Bit definition for OPAMP1_CSR register ***************/
+#define OPAMP1_CSR_OPAMP1EN ((uint32_t)0x00000001) /*!< OPAMP1 enable */
+#define OPAMP1_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP1_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
+#define OPAMP1_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define OPAMP1_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+#define OPAMP1_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
+#define OPAMP1_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define OPAMP1_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define OPAMP1_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
+#define OPAMP1_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
+#define OPAMP1_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
+#define OPAMP1_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define OPAMP1_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define OPAMP1_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
+#define OPAMP1_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
+#define OPAMP1_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define OPAMP1_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define OPAMP1_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
+#define OPAMP1_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define OPAMP1_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define OPAMP1_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
+#define OPAMP1_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
+#define OPAMP1_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
+#define OPAMP1_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
+#define OPAMP1_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
+#define OPAMP1_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
+#define OPAMP1_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP output status flag */
+#define OPAMP1_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
+
+/********************* Bit definition for OPAMP2_CSR register ***************/
+#define OPAMP2_CSR_OPAMP2EN ((uint32_t)0x00000001) /*!< OPAMP2 enable */
+#define OPAMP2_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP2_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
+#define OPAMP2_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define OPAMP2_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+#define OPAMP2_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
+#define OPAMP2_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define OPAMP2_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define OPAMP2_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
+#define OPAMP2_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
+#define OPAMP2_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
+#define OPAMP2_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define OPAMP2_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define OPAMP2_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
+#define OPAMP2_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
+#define OPAMP2_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define OPAMP2_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define OPAMP2_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
+#define OPAMP2_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define OPAMP2_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define OPAMP2_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
+#define OPAMP2_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
+#define OPAMP2_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
+#define OPAMP2_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
+#define OPAMP2_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
+#define OPAMP2_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
+#define OPAMP2_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP output status flag */
+#define OPAMP2_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
+
+/********************* Bit definition for OPAMP3_CSR register ***************/
+#define OPAMP3_CSR_OPAMP3EN ((uint32_t)0x00000001) /*!< OPAMP3 enable */
+#define OPAMP3_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP3_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
+#define OPAMP3_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define OPAMP3_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+#define OPAMP3_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
+#define OPAMP3_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define OPAMP3_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define OPAMP3_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
+#define OPAMP3_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
+#define OPAMP3_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
+#define OPAMP3_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define OPAMP3_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define OPAMP3_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
+#define OPAMP3_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
+#define OPAMP3_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define OPAMP3_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define OPAMP3_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
+#define OPAMP3_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define OPAMP3_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define OPAMP3_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
+#define OPAMP3_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
+#define OPAMP3_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
+#define OPAMP3_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
+#define OPAMP3_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
+#define OPAMP3_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
+#define OPAMP3_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP output status flag */
+#define OPAMP3_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
+
+/********************* Bit definition for OPAMP4_CSR register ***************/
+#define OPAMP4_CSR_OPAMP4EN ((uint32_t)0x00000001) /*!< OPAMP4 enable */
+#define OPAMP4_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP4_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
+#define OPAMP4_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define OPAMP4_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+#define OPAMP4_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
+#define OPAMP4_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define OPAMP4_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define OPAMP4_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
+#define OPAMP4_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
+#define OPAMP4_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
+#define OPAMP4_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define OPAMP4_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define OPAMP4_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
+#define OPAMP4_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
+#define OPAMP4_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define OPAMP4_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define OPAMP4_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
+#define OPAMP4_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define OPAMP4_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define OPAMP4_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
+#define OPAMP4_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
+#define OPAMP4_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
+#define OPAMP4_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
+#define OPAMP4_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
+#define OPAMP4_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
+#define OPAMP4_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP output status flag */
+#define OPAMP4_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
+
+/********************* Bit definition for OPAMPx_CSR register ***************/
+#define OPAMP_CSR_OPAMPxEN ((uint32_t)0x00000001) /*!< OPAMP enable */
+#define OPAMP_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
+#define OPAMP_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define OPAMP_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+#define OPAMP_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
+#define OPAMP_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define OPAMP_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define OPAMP_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
+#define OPAMP_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
+#define OPAMP_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
+#define OPAMP_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define OPAMP_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define OPAMP_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
+#define OPAMP_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
+#define OPAMP_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define OPAMP_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define OPAMP_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
+#define OPAMP_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define OPAMP_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define OPAMP_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
+#define OPAMP_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
+#define OPAMP_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
+#define OPAMP_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
+#define OPAMP_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
+#define OPAMP_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
+#define OPAMP_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP output status flag */
+#define OPAMP_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
+
+
+/******************************************************************************/
+/* */
+/* Controller Area Network (CAN ) */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */
+#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */
+
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */
+#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */
+#define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */
+#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */
+#define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
+
+#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
+#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
+#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
+#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
+#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
+#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
+#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
+#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
+#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
+#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
+#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */
+#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */
+#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */
+#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */
+#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */
+#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */
+#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */
+#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */
+#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */
+#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */
+#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */
+#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */
+#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */
+#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */
+#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */
+#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */
+#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */
+#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */
+#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */
+#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */
+#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */
+#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */
+#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */
+#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */
+#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */
+#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */
+#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */
+#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */
+#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
+#define CRC_CR_POLSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
+#define CRC_CR_POLSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
+#define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
+
+/******************* Bit definition for CRC_POL register ********************/
+#define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter (DAC) */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
+#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
+#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
+#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
+#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
+
+#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!< DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!< DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!< DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!< DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!< DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!< DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!< DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!< DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!< DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
+#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
+
+#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
+#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
+#define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00000004)
+#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00000008)
+#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00000010)
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
+#define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
+#define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
+#define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
+#define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+#define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_MR24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
+#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
+#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
+#define EXTI_EMR_MR24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */
+#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
+#define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
+#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
+#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
+#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
+#define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
+#define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
+#define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
+#define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
+#define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
+#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
+#define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
+#define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
+#define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
+#define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
+#define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
+#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
+#define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
+#define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
+#define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
+#define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
+#define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
+#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
+#define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
+#define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
+#define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
+#define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
+#define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!< LATENCY[2:0] bits (Latency) */
+#define FLASH_ACR_LATENCY_0 ((uint8_t)0x01) /*!< Bit 0 */
+#define FLASH_ACR_LATENCY_1 ((uint8_t)0x02) /*!< Bit 1 */
+
+#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!< Flash Half Cycle Access Enable */
+#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_PRFTBS ((uint8_t)0x20)
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
+
+#define RDP_KEY ((uint16_t)0x00A5) /*!< RDP Key */
+#define FLASH_KEY1 ((uint32_t)0x45670123) /*!< FPEC Key1 */
+#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< FPEC Key2 */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
+
+#define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
+#define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
+#define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
+#define FLASH_SR_WRPERR ((uint32_t)0x00000010) /*!< Write Protection Error */
+#define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
+#define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
+#define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
+#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
+#define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
+#define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
+#define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
+#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
+#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< OptionBytes Loader Launch */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
+#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
+
+#define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */
+#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
+#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for OB_RDP register **********************/
+#define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
+#define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
+
+/****************** Bit definition for OB_USER register *********************/
+#define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
+#define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
+
+/****************** Bit definition for FLASH_WRP0 register ******************/
+#define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP1 register ******************/
+#define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP2 register ******************/
+#define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP3 register ******************/
+#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+/******************************************************************************/
+/* */
+/* General Purpose I/O (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
+
+
+/****************** Bit definition for GPIO_OTYPER register *****************/
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
+
+
+/**************** Bit definition for GPIO_OSPEEDR register ******************/
+#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
+#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
+#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
+#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
+#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
+#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
+#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
+#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
+#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
+#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
+#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
+#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
+#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
+#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
+#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
+#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
+#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
+#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
+#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
+#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
+#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
+#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
+#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
+#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
+#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
+#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
+#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
+#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
+#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
+#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
+#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
+#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
+#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
+#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
+#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
+#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
+#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
+#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
+#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
+#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
+
+/******************* Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_0 ((uint32_t)0x00000001)
+#define GPIO_IDR_1 ((uint32_t)0x00000002)
+#define GPIO_IDR_2 ((uint32_t)0x00000004)
+#define GPIO_IDR_3 ((uint32_t)0x00000008)
+#define GPIO_IDR_4 ((uint32_t)0x00000010)
+#define GPIO_IDR_5 ((uint32_t)0x00000020)
+#define GPIO_IDR_6 ((uint32_t)0x00000040)
+#define GPIO_IDR_7 ((uint32_t)0x00000080)
+#define GPIO_IDR_8 ((uint32_t)0x00000100)
+#define GPIO_IDR_9 ((uint32_t)0x00000200)
+#define GPIO_IDR_10 ((uint32_t)0x00000400)
+#define GPIO_IDR_11 ((uint32_t)0x00000800)
+#define GPIO_IDR_12 ((uint32_t)0x00001000)
+#define GPIO_IDR_13 ((uint32_t)0x00002000)
+#define GPIO_IDR_14 ((uint32_t)0x00004000)
+#define GPIO_IDR_15 ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_ODR register ********************/
+#define GPIO_ODR_0 ((uint32_t)0x00000001)
+#define GPIO_ODR_1 ((uint32_t)0x00000002)
+#define GPIO_ODR_2 ((uint32_t)0x00000004)
+#define GPIO_ODR_3 ((uint32_t)0x00000008)
+#define GPIO_ODR_4 ((uint32_t)0x00000010)
+#define GPIO_ODR_5 ((uint32_t)0x00000020)
+#define GPIO_ODR_6 ((uint32_t)0x00000040)
+#define GPIO_ODR_7 ((uint32_t)0x00000080)
+#define GPIO_ODR_8 ((uint32_t)0x00000100)
+#define GPIO_ODR_9 ((uint32_t)0x00000200)
+#define GPIO_ODR_10 ((uint32_t)0x00000400)
+#define GPIO_ODR_11 ((uint32_t)0x00000800)
+#define GPIO_ODR_12 ((uint32_t)0x00001000)
+#define GPIO_ODR_13 ((uint32_t)0x00002000)
+#define GPIO_ODR_14 ((uint32_t)0x00004000)
+#define GPIO_ODR_15 ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_BSRR register ********************/
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
+#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
+#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
+#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
+#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
+#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
+#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
+#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
+#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
+#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
+#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
+#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
+#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
+#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
+#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_BRR register *********************/
+#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
+#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
+#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
+#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
+#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
+#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
+#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
+#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
+#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
+#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
+#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
+#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
+#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
+#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
+#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
+#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
+#define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
+#define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
+#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
+#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
+#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
+#define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
+#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
+#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
+#define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
+#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
+#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *****************/
+#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
+#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *****************/
+#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
+#define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
+#define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
+#define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
+#define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
+#define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
+#define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
+#define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
+#define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
+#define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
+#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register ********************/
+#define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
+
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */
+#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */
+#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU ((uint8_t)0x04) /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_WINR_WIN ((uint16_t)0x0FFF) /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPSDSR ((uint16_t)0x0001) /*!< Low-power deepsleep/sleep/low power run */
+#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */
+#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */
+#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */
+#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) /*!< PVD level 7 */
+
+#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */
+#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */
+#define PWR_CSR_VREFINTRDYF ((uint16_t)0x0008) /*!< Internal voltage reference (VREFINT) ready flag */
+
+#define PWR_CSR_EWUP1 ((uint16_t)0x0100) /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2 ((uint16_t)0x0200) /*!< Enable WKUP pin 2 */
+#define PWR_CSR_EWUP3 ((uint16_t)0x0400) /*!< Enable WKUP pin 3 */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION ((uint32_t)0x00000001)
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002)
+
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
+#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
+
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
+#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
+
+#define RCC_CR_HSEON ((uint32_t)0x00010000)
+#define RCC_CR_HSERDY ((uint32_t)0x00020000)
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
+#define RCC_CR_CSSON ((uint32_t)0x00080000)
+
+#define RCC_CR_PLLON ((uint32_t)0x01000000)
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000)
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+
+#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
+
+#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
+#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
+#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
+#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
+#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
+#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
+#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
+#define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
+#define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
+#define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
+#define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
+#define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
+#define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
+#define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
+
+/*!< USB configuration */
+#define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB prescaler */
+
+/*!< I2S configuration */
+#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000) /*!< I2S external clock source selection */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
+#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+
+#define RCC_CFGR_MCOF ((uint32_t)0x10000000) /*!< Microcontroller Clock Output Flag */
+
+#define RCC_CFGR_MCO_PRE ((uint32_t)0x70000000) /*!< MCO prescaler */
+#define RCC_CFGR_MCO_PRE_1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCO_PRE_4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCO_PRE_8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCO_PRE_16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */
+#define RCC_CFGR_MCO_PRE_32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 */
+#define RCC_CFGR_MCO_PRE_64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */
+#define RCC_CFGR_MCO_PRE_128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */
+
+#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
+
+/********************* Bit definition for RCC_CIR register ********************/
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
+
+/****************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG reset */
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000200) /*!< TIM1 reset */
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 reset */
+#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000200) /*!< TIM8 reset */
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
+#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 reset */
+#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 reset */
+#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 reset */
+#define RCC_APB2RSTR_HRTIM1RST ((uint32_t)0x20000000) /*!< HRTIM1 reset */
+
+/****************** Bit definition for RCC_APB1RSTR register ******************/
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
+#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
+#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 reset */
+#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI3 reset */
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
+#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
+#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
+#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
+#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB reset */
+#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN reset */
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR reset */
+#define RCC_APB1RSTR_DAC1RST ((uint32_t)0x20000000) /*!< DAC 1 reset */
+#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x40000000) /*!< I2C 3 reset */
+#define RCC_APB1RSTR_DAC2RST ((uint32_t)0x04000000) /*!< DAC 2 reset */
+#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DAC1RST /*!< DAC reset */
+
+/****************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
+#define RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) /*!< DMA2 clock enable */
+#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
+#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
+#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
+#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
+#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
+#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
+#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */
+#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
+#define RCC_AHBENR_TSEN ((uint32_t)0x01000000) /*!< TS clock enable */
+#define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /*!< ADC1/ ADC2 clock enable */
+#define RCC_AHBENR_ADC34EN ((uint32_t)0x20000000) /*!< ADC1/ ADC2 clock enable */
+
+/***************** Bit definition for RCC_APB2ENR register ******************/
+#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
+#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 clock enable */
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
+#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
+#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
+#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
+#define RCC_APB2ENR_HRTIM1 ((uint32_t)0x20000000) /*!< HRTIM1 clock enable */
+
+/****************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
+#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI3 clock enable */
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
+#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
+#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
+#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
+#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
+#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN clock enable */
+#define RCC_APB1ENR_DAC2EN ((uint32_t)0x04000000) /*!< DAC 2 clock enable */
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
+#define RCC_APB1ENR_DAC1EN ((uint32_t)0x20000000) /*!< DAC clock enable */
+#define RCC_APB1ENR_I2C3EN ((uint32_t)0x40000000) /*!< I2C 3 clock enable */
+#define RCC_APB1ENR_DACEN RCC_APB1ENR_DAC1EN
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+
+
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*!< RTC configuration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 32 used as RTC clock */
+
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
+#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
+
+/******************* Bit definition for RCC_AHBRSTR register ****************/
+#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA reset */
+#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB reset */
+#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC reset */
+#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00010000) /*!< GPIOD reset */
+#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00040000) /*!< GPIOF reset */
+#define RCC_AHBRSTR_TSRST ((uint32_t)0x00100000) /*!< TS reset */
+#define RCC_AHBRSTR_ADC12RST ((uint32_t)0x01000000) /*!< ADC1 & ADC2 reset */
+#define RCC_AHBRSTR_ADC34RST ((uint32_t)0x02000000) /*!< ADC3 & ADC4 reset */
+
+/******************* Bit definition for RCC_CFGR2 register ******************/
+/*!< PREDIV1 configuration */
+#define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */
+#define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
+#define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */
+#define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */
+#define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */
+#define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */
+#define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */
+#define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */
+#define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */
+#define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */
+#define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */
+#define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */
+#define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */
+#define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */
+#define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */
+#define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */
+#define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */
+
+/*!< ADCPRE12 configuration */
+#define RCC_CFGR2_ADCPRE12 ((uint32_t)0x000001F0) /*!< ADCPRE12[8:4] bits */
+#define RCC_CFGR2_ADCPRE12_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR2_ADCPRE12_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR2_ADCPRE12_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR2_ADCPRE12_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+#define RCC_CFGR2_ADCPRE12_4 ((uint32_t)0x00000100) /*!< Bit 4 */
+
+#define RCC_CFGR2_ADCPRE12_NO ((uint32_t)0x00000000) /*!< ADC12 clock disabled, ADC12 can use AHB clock */
+#define RCC_CFGR2_ADCPRE12_DIV1 ((uint32_t)0x00000100) /*!< ADC12 PLL clock divided by 1 */
+#define RCC_CFGR2_ADCPRE12_DIV2 ((uint32_t)0x00000110) /*!< ADC12 PLL clock divided by 2 */
+#define RCC_CFGR2_ADCPRE12_DIV4 ((uint32_t)0x00000120) /*!< ADC12 PLL clock divided by 4 */
+#define RCC_CFGR2_ADCPRE12_DIV6 ((uint32_t)0x00000130) /*!< ADC12 PLL clock divided by 6 */
+#define RCC_CFGR2_ADCPRE12_DIV8 ((uint32_t)0x00000140) /*!< ADC12 PLL clock divided by 8 */
+#define RCC_CFGR2_ADCPRE12_DIV10 ((uint32_t)0x00000150) /*!< ADC12 PLL clock divided by 10 */
+#define RCC_CFGR2_ADCPRE12_DIV12 ((uint32_t)0x00000160) /*!< ADC12 PLL clock divided by 12 */
+#define RCC_CFGR2_ADCPRE12_DIV16 ((uint32_t)0x00000170) /*!< ADC12 PLL clock divided by 16 */
+#define RCC_CFGR2_ADCPRE12_DIV32 ((uint32_t)0x00000180) /*!< ADC12 PLL clock divided by 32 */
+#define RCC_CFGR2_ADCPRE12_DIV64 ((uint32_t)0x00000190) /*!< ADC12 PLL clock divided by 64 */
+#define RCC_CFGR2_ADCPRE12_DIV128 ((uint32_t)0x000001A0) /*!< ADC12 PLL clock divided by 128 */
+#define RCC_CFGR2_ADCPRE12_DIV256 ((uint32_t)0x000001B0) /*!< ADC12 PLL clock divided by 256 */
+
+/*!< ADCPRE34 configuration */
+#define RCC_CFGR2_ADCPRE34 ((uint32_t)0x00003E00) /*!< ADCPRE34[13:5] bits */
+#define RCC_CFGR2_ADCPRE34_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define RCC_CFGR2_ADCPRE34_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define RCC_CFGR2_ADCPRE34_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+#define RCC_CFGR2_ADCPRE34_3 ((uint32_t)0x00001000) /*!< Bit 3 */
+#define RCC_CFGR2_ADCPRE34_4 ((uint32_t)0x00002000) /*!< Bit 4 */
+
+#define RCC_CFGR2_ADCPRE34_NO ((uint32_t)0x00000000) /*!< ADC34 clock disabled, ADC34 can use AHB clock */
+#define RCC_CFGR2_ADCPRE34_DIV1 ((uint32_t)0x00002000) /*!< ADC34 PLL clock divided by 1 */
+#define RCC_CFGR2_ADCPRE34_DIV2 ((uint32_t)0x00002200) /*!< ADC34 PLL clock divided by 2 */
+#define RCC_CFGR2_ADCPRE34_DIV4 ((uint32_t)0x00002400) /*!< ADC34 PLL clock divided by 4 */
+#define RCC_CFGR2_ADCPRE34_DIV6 ((uint32_t)0x00002600) /*!< ADC34 PLL clock divided by 6 */
+#define RCC_CFGR2_ADCPRE34_DIV8 ((uint32_t)0x00002800) /*!< ADC34 PLL clock divided by 8 */
+#define RCC_CFGR2_ADCPRE34_DIV10 ((uint32_t)0x00002A00) /*!< ADC34 PLL clock divided by 10 */
+#define RCC_CFGR2_ADCPRE34_DIV12 ((uint32_t)0x00002C00) /*!< ADC34 PLL clock divided by 12 */
+#define RCC_CFGR2_ADCPRE34_DIV16 ((uint32_t)0x00002E00) /*!< ADC34 PLL clock divided by 16 */
+#define RCC_CFGR2_ADCPRE34_DIV32 ((uint32_t)0x00003000) /*!< ADC34 PLL clock divided by 32 */
+#define RCC_CFGR2_ADCPRE34_DIV64 ((uint32_t)0x00003200) /*!< ADC34 PLL clock divided by 64 */
+#define RCC_CFGR2_ADCPRE34_DIV128 ((uint32_t)0x00003400) /*!< ADC34 PLL clock divided by 128 */
+#define RCC_CFGR2_ADCPRE34_DIV256 ((uint32_t)0x00003600) /*!< ADC34 PLL clock divided by 256 */
+
+/******************* Bit definition for RCC_CFGR3 register ******************/
+#define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
+#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR3_I2CSW ((uint32_t)0x00000070) /*!< I2CSW bits */
+#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
+#define RCC_CFGR3_I2C2SW ((uint32_t)0x00000020) /*!< I2C2SW bits */
+#define RCC_CFGR3_I2C3SW ((uint32_t)0x00000040) /*!< I2C3SW bits */
+
+#define RCC_CFGR3_TIMSW ((uint32_t)0x00002F00) /*!< TIMSW bits */
+#define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /*!< TIM1SW bits */
+#define RCC_CFGR3_TIM8SW ((uint32_t)0x00000200) /*!< TIM8SW bits */
+#define RCC_CFGR3_TIM15SW ((uint32_t)0x00000400) /*!< TIM15SW bits */
+#define RCC_CFGR3_TIM16SW ((uint32_t)0x00000800) /*!< TIM16SW bits */
+#define RCC_CFGR3_TIM17SW ((uint32_t)0x00002000) /*!< TIM17SW bits */
+
+#define RCC_CFGR3_HRTIM1SW ((uint32_t)0x00001000) /*!< HRTIM1SW bits */
+
+#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
+#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+#define RCC_CFGR3_USART3SW ((uint32_t)0x000C0000) /*!< USART3SW[1:0] bits */
+#define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+
+#define RCC_CFGR3_UART4SW ((uint32_t)0x00300000) /*!< UART4SW[1:0] bits */
+#define RCC_CFGR3_UART4SW_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define RCC_CFGR3_UART4SW_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+#define RCC_CFGR3_UART5SW ((uint32_t)0x00C00000) /*!< UART5SW[1:0] bits */
+#define RCC_CFGR3_UART5SW_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define RCC_CFGR3_UART5SW_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM ((uint32_t)0x00400000)
+#define RTC_TR_HT ((uint32_t)0x00300000)
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TR_HU ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TR_MNT ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TR_MNU ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TR_ST ((uint32_t)0x00000070)
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TR_SU ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)
+#define RTC_DR_YU ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)
+#define RTC_DR_WDU ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_DR_MT ((uint32_t)0x00001000)
+#define RTC_DR_MU ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)
+#define RTC_DR_DT ((uint32_t)0x00000030)
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)
+#define RTC_DR_DU ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE ((uint32_t)0x00800000)
+#define RTC_CR_OSEL ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
+#define RTC_CR_POL ((uint32_t)0x00100000)
+#define RTC_CR_COSEL ((uint32_t)0x00080000)
+#define RTC_CR_BCK ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)
+#define RTC_CR_TSIE ((uint32_t)0x00008000)
+#define RTC_CR_WUTIE ((uint32_t)0x00004000)
+#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
+#define RTC_CR_TSE ((uint32_t)0x00000800)
+#define RTC_CR_WUTE ((uint32_t)0x00000400)
+#define RTC_CR_ALRBE ((uint32_t)0x00000200)
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)
+#define RTC_CR_FMT ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
+#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
+#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
+#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
+#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
+#define RTC_ISR_TSF ((uint32_t)0x00000800)
+#define RTC_ISR_WUTF ((uint32_t)0x00000400)
+#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
+#define RTC_ISR_INIT ((uint32_t)0x00000080)
+#define RTC_ISR_INITF ((uint32_t)0x00000040)
+#define RTC_ISR_RSF ((uint32_t)0x00000020)
+#define RTC_ISR_INITS ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF ((uint32_t)0x00000008)
+#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
+#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM ((uint32_t)0x00400000)
+#define RTC_TSTR_HT ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TSTR_ST ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_TSDR_MT ((uint32_t)0x00001000)
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
+#define RTC_TSDR_DT ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
+#define RTC_CALR_CALM ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
+#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
+#define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
+#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */
+#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */
+#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */
+
+#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */
+#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */
+#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */
+
+#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */
+#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */
+#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */
+#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */
+#define SPI_CR1_CRCL ((uint16_t)0x0800) /*!< CRC Length */
+#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN ((uint16_t)0x0001) /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint16_t)0x0002) /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint16_t)0x0004) /*!< SS Output Enable */
+#define SPI_CR2_NSSP ((uint16_t)0x0008) /*!< NSS pulse management Enable */
+#define SPI_CR2_FRF ((uint16_t)0x0010) /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE ((uint16_t)0x0020) /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint16_t)0x0040) /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint16_t)0x0080) /*!< Tx buffer Empty Interrupt Enable */
+
+#define SPI_CR2_DS ((uint16_t)0x0F00) /*!< DS[3:0] Data Size */
+#define SPI_CR2_DS_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define SPI_CR2_DS_1 ((uint16_t)0x0200) /*!< Bit 1 */
+#define SPI_CR2_DS_2 ((uint16_t)0x0400) /*!< Bit 2 */
+#define SPI_CR2_DS_3 ((uint16_t)0x0800) /*!< Bit 3 */
+
+#define SPI_CR2_FRXTH ((uint16_t)0x1000) /*!< FIFO reception Threshold */
+#define SPI_CR2_LDMARX ((uint16_t)0x2000) /*!< Last DMA transfer for reception */
+#define SPI_CR2_LDMATX ((uint16_t)0x4000) /*!< Last DMA transfer for transmission */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE ((uint16_t)0x0001) /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint16_t)0x0002) /*!< Transmit buffer Empty */
+#define SPI_SR_CRCERR ((uint16_t)0x0010) /*!< CRC Error flag */
+#define SPI_SR_MODF ((uint16_t)0x0020) /*!< Mode fault */
+#define SPI_SR_OVR ((uint16_t)0x0040) /*!< Overrun flag */
+#define SPI_SR_BSY ((uint16_t)0x0080) /*!< Busy flag */
+#define SPI_SR_FRE ((uint16_t)0x0100) /*!< TI frame format error */
+#define SPI_SR_FRLVL ((uint16_t)0x0600) /*!< FIFO Reception Level */
+#define SPI_SR_FRLVL_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define SPI_SR_FRLVL_1 ((uint16_t)0x0400) /*!< Bit 1 */
+#define SPI_SR_FTLVL ((uint16_t)0x1800) /*!< FIFO Transmission Level */
+#define SPI_SR_FTLVL_0 ((uint16_t)0x0800) /*!< Bit 0 */
+#define SPI_SR_FTLVL_1 ((uint16_t)0x1000) /*!< Bit 1 */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* System Configuration(SYSCFG) */
+/* */
+/******************************************************************************/
+/***************** Bit definition for SYSCFG_CFGR1 register *****************/
+#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define SYSCFG_CFGR1_USB_IT_RMP ((uint32_t)0x00000020) /*!< USB interrupt remap */
+#define SYSCFG_CFGR1_TIM1_ITR3_RMP ((uint32_t)0x00000040) /*!< Timer 1 ITR3 selection */
+#define SYSCFG_CFGR1_DAC1_TRIG1_RMP ((uint32_t)0x00000080) /*!< DAC1 Trigger1 remap */
+#define SYSCFG_CFGR1_ADC24_DMA_RMP ((uint32_t)0x00000100) /*!< ADC2 and ADC4 DMA remap */
+#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
+#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
+#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */
+#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 CH2 DMA remap */
+#define SYSCFG_CFGR1_DAC2Ch1_DMA_RMP ((uint32_t)0x00008000) /*!< DAC2 CH1 DMA remap */
+#define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB9_FMP ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR1_I2C1_FMP ((uint32_t)0x00100000) /*!< I2C1 Fast mode plus */
+#define SYSCFG_CFGR1_I2C2_FMP ((uint32_t)0x00200000) /*!< I2C2 Fast mode plus */
+#define SYSCFG_CFGR1_ENCODER_MODE ((uint32_t)0x00C00000) /*!< Encoder Mode */
+#define SYSCFG_CFGR1_ENCODER_MODE_0 ((uint32_t)0x00400000) /*!< Encoder Mode 0 */
+#define SYSCFG_CFGR1_ENCODER_MODE_1 ((uint32_t)0x00800000) /*!< Encoder Mode 1 */
+#define SYSCFG_CFGR1_FPU_IE ((uint32_t)0xFC000000) /*!< Floating Point Unit Interrupt Enable */
+#define SYSCFG_CFGR1_FPU_IE_0 ((uint32_t)0x04000000) /*!< Floating Point Unit Interrupt Enable 0 */
+#define SYSCFG_CFGR1_FPU_IE_1 ((uint32_t)0x08000000) /*!< Floating Point Unit Interrupt Enable 1 */
+#define SYSCFG_CFGR1_FPU_IE_2 ((uint32_t)0x10000000) /*!< Floating Point Unit Interrupt Enable 2 */
+#define SYSCFG_CFGR1_FPU_IE_3 ((uint32_t)0x20000000) /*!< Floating Point Unit Interrupt Enable 3 */
+#define SYSCFG_CFGR1_FPU_IE_4 ((uint32_t)0x40000000) /*!< Floating Point Unit Interrupt Enable 4 */
+#define SYSCFG_CFGR1_FPU_IE_5 ((uint32_t)0x80000000) /*!< Floating Point Unit Interrupt Enable 5 */
+#define SYSCFG_CFGR1_DAC_TRIG_RMP SYSCFG_CFGR1_DAC1_TRIG1_RMP /*!< Old define maintained for legacy purpose */
+#define SYSCFG_CFGR1_TIM6DAC1 SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP /*!< Old define maintained for legacy purpose */
+#define SYSCFG_CFGR1_TIM7DAC2 SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP /*!< Old define maintained for legacy purpose */
+/***************** Bit definition for SYSCFG_RCR register *******************/
+#define SYSCFG_RCR_PAGE0 ((uint32_t)0x00000001) /*!< ICODE SRAM Write protection page 0 */
+#define SYSCFG_RCR_PAGE1 ((uint32_t)0x00000002) /*!< ICODE SRAM Write protection page 1 */
+#define SYSCFG_RCR_PAGE2 ((uint32_t)0x00000004) /*!< ICODE SRAM Write protection page 2 */
+#define SYSCFG_RCR_PAGE3 ((uint32_t)0x00000008) /*!< ICODE SRAM Write protection page 3 */
+#define SYSCFG_RCR_PAGE4 ((uint32_t)0x00000010) /*!< ICODE SRAM Write protection page 4 */
+#define SYSCFG_RCR_PAGE5 ((uint32_t)0x00000020) /*!< ICODE SRAM Write protection page 5 */
+#define SYSCFG_RCR_PAGE6 ((uint32_t)0x00000040) /*!< ICODE SRAM Write protection page 6 */
+#define SYSCFG_RCR_PAGE7 ((uint32_t)0x00000080) /*!< ICODE SRAM Write protection page 7 */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTIRCR_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTIRCR_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTIRCR_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTIRCR_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTIRCR_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
+#define SYSCFG_EXTIRCR_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
+#define SYSCFG_EXTIRCR_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
+#define SYSCFG_EXTIRCR_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
+#define SYSCFG_EXTIRCR_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
+#define SYSCFG_EXTIRCR_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTIRCR_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
+#define SYSCFG_EXTIRCR_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
+#define SYSCFG_EXTIRCR_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
+#define SYSCFG_EXTIRCR_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
+#define SYSCFG_EXTIRCR_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
+#define SYSCFG_EXTIRCR_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTIRCR_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
+#define SYSCFG_EXTIRCR_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
+#define SYSCFG_EXTIRCR_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
+#define SYSCFG_EXTIRCR_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
+#define SYSCFG_EXTIRCR_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
+#define SYSCFG_EXTIRCR_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTIRCR_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
+#define SYSCFG_EXTIRCR_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
+#define SYSCFG_EXTIRCR_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
+#define SYSCFG_EXTIRCR_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
+#define SYSCFG_EXTIRCR_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
+#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
+
+/***************** Bit definition for SYSCFG_CFGR2 register *****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
+#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17 */
+#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMER1/8/15/16/17 */
+#define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /*!< Disables the address parity check on RAM */
+#define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
+
+/***************** Bit definition for SYSCFG_CFGR3 register *****************/
+#define SYSCFG_CFGR3_SPI1_RX_DMA_RMP ((uint32_t)0x00000003) /*!< SPI1 RX DMA remap */
+#define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_0 ((uint32_t)0x00000001) /*!< SPI1 RX DMA remap bit 0 */
+#define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_1 ((uint32_t)0x00000002) /*!< SPI1 RX DMA remap bit 1 */
+#define SYSCFG_CFGR3_SPI1_TX_DMA_RMP ((uint32_t)0x0000000C) /*!< SPI1 TX DMA remap */
+#define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_0 ((uint32_t)0x00000004) /*!< SPI1 TX DMA remap bit 0 */
+#define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_1 ((uint32_t)0x00000008) /*!< SPI1 TX DMA remap bit 1 */
+#define SYSCFG_CFGR3_I2C1_RX_DMA_RMP ((uint32_t)0x00000030) /*!< I2C1 RX DMA remap */
+#define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_0 ((uint32_t)0x00000010) /*!< I2C1 RX DMA remap bit 0 */
+#define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_1 ((uint32_t)0x00000020) /*!< I2C1 RX DMA remap bit 1 */
+#define SYSCFG_CFGR3_I2C1_TX_DMA_RMP ((uint32_t)0x000000C0) /*!< I2C1 RX DMA remap */
+#define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_0 ((uint32_t)0x00000040) /*!< I2C1 TX DMA remap bit 0 */
+#define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_1 ((uint32_t)0x00000080) /*!< I2C1 TX DMA remap bit 1 */
+#define SYSCFG_CFGR3_ADC2_DMA_RMP ((uint32_t)0x00000300) /*!< ADC2 DMA remap */
+#define SYSCFG_CFGR3_ADC2_DMA_RMP_0 ((uint32_t)0x00000100) /*!< ADC2 DMA remap bit 0 */
+#define SYSCFG_CFGR3_ADC2_DMA_RMP_1 ((uint32_t)0x00000200) /*!< ADC2 DMA remap bit 1 */
+#define SYSCFG_CFGR3_DAC1_TRG3_RMP ((uint32_t)0x00010000) /*!< DAC1 TRG3 remap */
+#define SYSCFG_CFGR3_DAC1_TRG5_RMP ((uint32_t)0x00020000) /*!< DAC1 TRG5 remap */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */
+#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */
+#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */
+
+#define TIM_CR1_UIFREMAP ((uint16_t)0x0800) /*!<Update interrupt flag remap */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
+#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS5 ((uint32_t)0x00010000) /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS6 ((uint32_t)0x00020000) /*!<Output Idle state 4 (OC4 output) */
+
+#define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /*!<Bit 2 */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS ((uint32_t)0x00010007) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
+#define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */
+#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */
+#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */
+#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
+#define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
+#define TIM_SR_B2IF ((uint32_t)0x00000100) /*!<Break2 interrupt Flag */
+#define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Over capture Flag */
+#define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Over capture Flag */
+#define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Over capture Flag */
+#define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Over capture Flag */
+#define TIM_SR_CC5IF ((uint32_t)0x00010000) /*!<Capture/Compare 5 interrupt Flag */
+#define TIM_SR_CC6IF ((uint32_t)0x00020000) /*!<Capture/Compare 6 interrupt Flag */
+
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG ((uint16_t)0x0001) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint16_t)0x0002) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint16_t)0x0004) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint16_t)0x0008) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint16_t)0x0010) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG ((uint16_t)0x0020) /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG ((uint16_t)0x0040) /*!<Trigger Generation */
+#define TIM_EGR_BG ((uint16_t)0x0080) /*!<Break Generation */
+#define TIM_EGR_B2G ((uint16_t)0x0100) /*!<Break Generation */
+
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
+
+#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR2_OC4M_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+
+#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC ((uint16_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x00000004) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x00000008) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint16_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint16_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint16_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint16_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint16_t)0x00000080) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint16_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x00000400) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x00000800) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint16_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint16_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint16_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint16_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint16_t)0x00008000) /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
+#define TIM_CCER_CC5E ((uint32_t)0x00010000) /*!<Capture/Compare 5 output enable */
+#define TIM_CCER_CC5P ((uint32_t)0x00020000) /*!<Capture/Compare 5 output Polarity */
+#define TIM_CCER_CC6E ((uint32_t)0x00100000) /*!<Capture/Compare 6 output enable */
+#define TIM_CCER_CC6P ((uint32_t)0x00200000) /*!<Capture/Compare 6 output Polarity */
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
+#define TIM_CNT_UIFCPY ((uint32_t)0x80000000) /*!<Update interrupt flag copy */
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_CCR5 register *******************/
+#define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /*!<Capture/Compare 5 Value */
+#define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /*!<Group Channel 5 and Channel 1 */
+#define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /*!<Group Channel 5 and Channel 2 */
+#define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /*!<Group Channel 5 and Channel 3 */
+
+/******************* Bit definition for TIM_CCR6 register *******************/
+#define TIM_CCR6_CCR6 ((uint16_t)0xFFFF) /*!<Capture/Compare 6 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable for Break1 */
+#define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity for Break1 */
+#define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
+#define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
+
+#define TIM_BDTR_BKF ((uint32_t)0x000F0000) /*!<Break Filter for Break1 */
+#define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /*!<Break Filter for Break2 */
+
+#define TIM_BDTR_BK2E ((uint32_t)0x01000000) /*!<Break enable for Break2 */
+#define TIM_BDTR_BK2P ((uint32_t)0x02000000) /*!<Break Polarity for Break2 */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM16_OR register *********************/
+#define TIM16_OR_TI1_RMP ((uint16_t)0x00C0) /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */
+#define TIM16_OR_TI1_RMP_0 ((uint16_t)0x0040) /*!<Bit 0 */
+#define TIM16_OR_TI1_RMP_1 ((uint16_t)0x0080) /*!<Bit 1 */
+
+/******************* Bit definition for TIM1_OR register *********************/
+#define TIM1_OR_ETR_RMP ((uint16_t)0x000F) /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */
+#define TIM1_OR_ETR_RMP_0 ((uint16_t)0x0001) /*!<Bit 0 */
+#define TIM1_OR_ETR_RMP_1 ((uint16_t)0x0002) /*!<Bit 1 */
+#define TIM1_OR_ETR_RMP_2 ((uint16_t)0x0004) /*!<Bit 2 */
+#define TIM1_OR_ETR_RMP_3 ((uint16_t)0x0008) /*!<Bit 3 */
+
+/******************* Bit definition for TIM8_OR register *********************/
+#define TIM8_OR_ETR_RMP ((uint16_t)0x000F) /*!<ETR_RMP[3:0] bits (TIM8 ETR remap) */
+#define TIM8_OR_ETR_RMP_0 ((uint16_t)0x0001) /*!<Bit 0 */
+#define TIM8_OR_ETR_RMP_1 ((uint16_t)0x0002) /*!<Bit 1 */
+#define TIM8_OR_ETR_RMP_2 ((uint16_t)0x0004) /*!<Bit 2 */
+#define TIM8_OR_ETR_RMP_3 ((uint16_t)0x0008) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR3 register *******************/
+#define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /*!<Output Compare 5 Fast enable */
+#define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /*!<Output Compare 5 Preload enable */
+
+#define TIM_CCMR3_OC5M ((uint32_t)0x00000070) /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /*!<Output Compare 5 Clear Enable */
+
+#define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR3_OC6M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR3_OC6M_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+
+#define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
+#define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
+#define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
+#define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
+#define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
+#define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
+#define USART_CR1_M ((uint32_t)0x00001000) /*!< Word length */
+#define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
+#define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
+#define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
+#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
+#define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
+#define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
+#define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
+#define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
+#define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
+#define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
+#define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
+#define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
+#define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
+#define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
+#define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
+#define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
+#define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
+#define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
+#define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+#define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION ((uint16_t)0x000F) /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< GT[7:0] bits (Guard time value) */
+
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ ((uint16_t)0x0001) /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ ((uint16_t)0x0002) /*!< Send Break Request */
+#define USART_RQR_MMRQ ((uint16_t)0x0004) /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ ((uint16_t)0x0008) /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ ((uint16_t)0x0010) /*!< Transmit data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
+#define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
+#define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
+#define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
+#define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
+#define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
+#define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
+#define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
+#define USART_ISR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
+#define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
+#define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
+#define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
+#define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
+#define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
+#define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
+#define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T ((uint8_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T0 ((uint8_t)0x01) /*!<Bit 0 */
+#define WWDG_CR_T1 ((uint8_t)0x02) /*!<Bit 1 */
+#define WWDG_CR_T2 ((uint8_t)0x04) /*!<Bit 2 */
+#define WWDG_CR_T3 ((uint8_t)0x08) /*!<Bit 3 */
+#define WWDG_CR_T4 ((uint8_t)0x10) /*!<Bit 4 */
+#define WWDG_CR_T5 ((uint8_t)0x20) /*!<Bit 5 */
+#define WWDG_CR_T6 ((uint8_t)0x40) /*!<Bit 6 */
+
+#define WWDG_CR_WDGA ((uint8_t)0x80) /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W ((uint16_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!<Bit 0 */
+#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!<Bit 1 */
+#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!<Bit 2 */
+#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!<Bit 3 */
+#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!<Bit 4 */
+#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!<Bit 5 */
+#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!<Bit 6 */
+
+#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!<Bit 0 */
+#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!<Bit 1 */
+
+#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF ((uint8_t)0x01) /*!<Early Wakeup Interrupt Flag */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+#ifdef USE_STDPERIPH_DRIVER
+ #include "stm32f30x_conf.h"
+#endif /*!< USE_STDPERIPH_DRIVER */
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F30x_H */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_adc.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,2411 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_adc.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Analog to Digital Convertor (ADC) peripheral:
+ * + Initialization and Configuration
+ * + Analog Watchdog configuration
+ * + Temperature Sensor, Vbat & Vrefint (Internal Reference Voltage) management
+ * + Regular Channels Configuration
+ * + Regular Channels DMA Configuration
+ * + Injected channels Configuration
+ * + Interrupts and flags management
+ * + Dual mode configuration
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) select the ADC clock using the function RCC_ADCCLKConfig()
+ (#) Enable the ADC interface clock using RCC_AHBPeriphClockCmd();
+ (#) ADC pins configuration
+ (++) Enable the clock for the ADC GPIOs using the following function:
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOx, ENABLE);
+ (++) Configure these ADC pins in analog mode using GPIO_Init();
+ (#) Configure the ADC conversion resolution, data alignment, external
+ trigger and edge, sequencer lenght and Enable/Disable the continuous mode
+ using the ADC_Init() function.
+ (#) Activate the ADC peripheral using ADC_Cmd() function.
+
+ *** ADC channels group configuration ***
+ ========================================
+ [..]
+ (+) To configure the ADC channels features, use ADC_Init(), ADC_InjectedInit()
+ and/or ADC_RegularChannelConfig() functions.
+ (+) To activate the continuous mode, use the ADC_ContinuousModeCmd()
+ function.
+ (+) To activate the Discontinuous mode, use the ADC_DiscModeCmd() functions.
+ (+) To activate the overrun mode, use the ADC_OverrunModeCmd() functions.
+ (+) To activate the calibration mode, use the ADC_StartCalibration() functions.
+ (+) To read the ADC converted values, use the ADC_GetConversionValue()
+ function.
+
+ *** DMA for ADC channels features configuration ***
+ ===================================================
+ [..]
+ (+) To enable the DMA mode for ADC channels group, use the ADC_DMACmd() function.
+ (+) To configure the DMA transfer request, use ADC_DMAConfig() function.
+
+ @endverbatim
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_adc.h"
+#include "stm32f30x_rcc.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup ADC
+ * @brief ADC driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* CFGR register Mask */
+#define CFGR_CLEAR_Mask ((uint32_t)0xFDFFC007)
+
+/* JSQR register Mask */
+#define JSQR_CLEAR_Mask ((uint32_t)0x00000000)
+
+/* ADC ADON mask */
+#define CCR_CLEAR_MASK ((uint32_t)0xFFFC10E0)
+
+/* ADC JDRx registers offset */
+#define JDR_Offset ((uint8_t)0x80)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Functions
+ * @{
+ */
+
+/** @defgroup ADC_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to:
+ (#) Initialize and configure the ADC injected and/or regular channels and dual mode.
+ (#) Management of the calibration process
+ (#) ADC Power-on Power-off
+ (#) Single ended or differential mode
+ (#) Enabling the queue of context and the auto delay mode
+ (#) The number of ADC conversions that will be done using the sequencer for regular
+ channel group
+ (#) Enable or disable the ADC peripheral
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the ADCx peripheral registers to their default reset values.
+ * @param ADCx: where x can be 1, 2,3 or 4 to select the ADC peripheral.
+ * @retval None
+ */
+void ADC_DeInit(ADC_TypeDef* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+
+ if((ADCx == ADC1) || (ADCx == ADC2))
+ {
+ /* Enable ADC1/ADC2 reset state */
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ADC12, ENABLE);
+ /* Release ADC1/ADC2 from reset state */
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ADC12, DISABLE);
+ }
+ else if((ADCx == ADC3) || (ADCx == ADC4))
+ {
+ /* Enable ADC3/ADC4 reset state */
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ADC34, ENABLE);
+ /* Release ADC3/ADC4 from reset state */
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ADC34, DISABLE);
+ }
+}
+/**
+ * @brief Initializes the ADCx peripheral according to the specified parameters
+ * in the ADC_InitStruct.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains
+ * the configuration information for the specified ADC peripheral.
+ * @retval None
+ */
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
+{
+ uint32_t tmpreg1 = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_CONVMODE(ADC_InitStruct->ADC_ContinuousConvMode));
+ assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution));
+ assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConvEvent));
+ assert_param(IS_EXTERNALTRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigEventEdge));
+ assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
+ assert_param(IS_ADC_OVRUNMODE(ADC_InitStruct->ADC_OverrunMode));
+ assert_param(IS_ADC_AUTOINJECMODE(ADC_InitStruct->ADC_AutoInjMode));
+ assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfRegChannel));
+
+ /*---------------------------- ADCx CFGR Configuration -----------------*/
+ /* Get the ADCx CFGR value */
+ tmpreg1 = ADCx->CFGR;
+ /* Clear SCAN bit */
+ tmpreg1 &= CFGR_CLEAR_Mask;
+ /* Configure ADCx: scan conversion mode */
+ /* Set SCAN bit according to ADC_ScanConvMode value */
+ tmpreg1 |= (uint32_t)ADC_InitStruct->ADC_ContinuousConvMode |
+ ADC_InitStruct->ADC_Resolution|
+ ADC_InitStruct->ADC_ExternalTrigConvEvent|
+ ADC_InitStruct->ADC_ExternalTrigEventEdge|
+ ADC_InitStruct->ADC_DataAlign|
+ ADC_InitStruct->ADC_OverrunMode|
+ ADC_InitStruct->ADC_AutoInjMode;
+
+ /* Write to ADCx CFGR */
+ ADCx->CFGR = tmpreg1;
+
+ /*---------------------------- ADCx SQR1 Configuration -----------------*/
+ /* Get the ADCx SQR1 value */
+ tmpreg1 = ADCx->SQR1;
+ /* Clear L bits */
+ tmpreg1 &= ~(uint32_t)(ADC_SQR1_L);
+ /* Configure ADCx: regular channel sequence length */
+ /* Set L bits according to ADC_NbrOfRegChannel value */
+ tmpreg1 |= (uint32_t) (ADC_InitStruct->ADC_NbrOfRegChannel - 1);
+ /* Write to ADCx SQR1 */
+ ADCx->SQR1 = tmpreg1;
+
+}
+
+/**
+ * @brief Fills each ADC_InitStruct member with its default value.
+ * @param ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized.
+ * @retval None
+ */
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
+{
+ /* Reset ADC init structure parameters values */
+ ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
+ ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;
+ ADC_InitStruct->ADC_ExternalTrigConvEvent = ADC_ExternalTrigConvEvent_0;
+ ADC_InitStruct->ADC_ExternalTrigEventEdge = ADC_ExternalTrigEventEdge_None;
+ ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
+ ADC_InitStruct->ADC_OverrunMode = DISABLE;
+ ADC_InitStruct->ADC_AutoInjMode = DISABLE;
+ ADC_InitStruct->ADC_NbrOfRegChannel = 1;
+}
+
+/**
+ * @brief Initializes the ADCx peripheral according to the specified parameters
+ * in the ADC_InitStruct.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_InjectInitStruct: pointer to an ADC_InjecInitTypeDef structure that contains
+ * the configuration information for the specified ADC injected channel.
+ * @retval None
+ */
+void ADC_InjectedInit(ADC_TypeDef* ADCx, ADC_InjectedInitTypeDef* ADC_InjectedInitStruct)
+{
+ uint32_t tmpreg1 = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_InjectedInitStruct->ADC_ExternalTrigInjecConvEvent));
+ assert_param(IS_EXTERNALTRIGINJ_EDGE(ADC_InjectedInitStruct->ADC_ExternalTrigInjecEventEdge));
+ assert_param(IS_ADC_INJECTED_LENGTH(ADC_InjectedInitStruct->ADC_NbrOfInjecChannel));
+ assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedInitStruct->ADC_InjecSequence1));
+ assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedInitStruct->ADC_InjecSequence2));
+ assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedInitStruct->ADC_InjecSequence3));
+ assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedInitStruct->ADC_InjecSequence4));
+
+ /*---------------------------- ADCx JSQR Configuration -----------------*/
+ /* Get the ADCx JSQR value */
+ tmpreg1 = ADCx->JSQR;
+ /* Clear L bits */
+ tmpreg1 &= JSQR_CLEAR_Mask;
+ /* Configure ADCx: Injected channel sequence length, external trigger,
+ external trigger edge and sequences
+ */
+ tmpreg1 = (uint32_t) ((ADC_InjectedInitStruct->ADC_NbrOfInjecChannel - (uint8_t)1) |
+ ADC_InjectedInitStruct->ADC_ExternalTrigInjecConvEvent |
+ ADC_InjectedInitStruct->ADC_ExternalTrigInjecEventEdge |
+ (uint32_t)((ADC_InjectedInitStruct->ADC_InjecSequence1) << 8) |
+ (uint32_t)((ADC_InjectedInitStruct->ADC_InjecSequence2) << 14) |
+ (uint32_t)((ADC_InjectedInitStruct->ADC_InjecSequence3) << 20) |
+ (uint32_t)((ADC_InjectedInitStruct->ADC_InjecSequence4) << 26));
+ /* Write to ADCx SQR1 */
+ ADCx->JSQR = tmpreg1;
+}
+
+/**
+ * @brief Fills each ADC_InjectedInitStruct member with its default value.
+ * @param ADC_InjectedInitStruct : pointer to an ADC_InjectedInitTypeDef structure which will be initialized.
+ * @retval None
+ */
+void ADC_InjectedStructInit(ADC_InjectedInitTypeDef* ADC_InjectedInitStruct)
+{
+ ADC_InjectedInitStruct->ADC_ExternalTrigInjecConvEvent = ADC_ExternalTrigInjecConvEvent_0;
+ ADC_InjectedInitStruct->ADC_ExternalTrigInjecEventEdge = ADC_ExternalTrigInjecEventEdge_None;
+ ADC_InjectedInitStruct->ADC_NbrOfInjecChannel = 1;
+ ADC_InjectedInitStruct->ADC_InjecSequence1 = ADC_InjectedChannel_1;
+ ADC_InjectedInitStruct->ADC_InjecSequence2 = ADC_InjectedChannel_1;
+ ADC_InjectedInitStruct->ADC_InjecSequence3 = ADC_InjectedChannel_1;
+ ADC_InjectedInitStruct->ADC_InjecSequence4 = ADC_InjectedChannel_1;
+}
+
+/**
+ * @brief Initializes the ADCs peripherals according to the specified parameters
+ * in the ADC_CommonInitStruct.
+ * @param ADCx: where x can be 1 or 4 to select the ADC peripheral.
+ * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure
+ * that contains the configuration information for All ADCs peripherals.
+ * @retval None
+ */
+void ADC_CommonInit(ADC_TypeDef* ADCx, ADC_CommonInitTypeDef* ADC_CommonInitStruct)
+{
+ uint32_t tmpreg1 = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_MODE(ADC_CommonInitStruct->ADC_Mode));
+ assert_param(IS_ADC_CLOCKMODE(ADC_CommonInitStruct->ADC_Clock));
+ assert_param(IS_ADC_DMA_MODE(ADC_CommonInitStruct->ADC_DMAMode));
+ assert_param(IS_ADC_DMA_ACCESS_MODE(ADC_CommonInitStruct->ADC_DMAAccessMode));
+ assert_param(IS_ADC_TWOSAMPLING_DELAY(ADC_CommonInitStruct->ADC_TwoSamplingDelay));
+
+ if((ADCx == ADC1) || (ADCx == ADC2))
+ {
+ /* Get the ADC CCR value */
+ tmpreg1 = ADC1_2->CCR;
+
+ /* Clear MULTI, DELAY, DMA and ADCPRE bits */
+ tmpreg1 &= CCR_CLEAR_MASK;
+ }
+ else
+ {
+ /* Get the ADC CCR value */
+ tmpreg1 = ADC3_4->CCR;
+
+ /* Clear MULTI, DELAY, DMA and ADCPRE bits */
+ tmpreg1 &= CCR_CLEAR_MASK;
+ }
+ /*---------------------------- ADC CCR Configuration -----------------*/
+ /* Configure ADCx: Multi mode, Delay between two sampling time, ADC clock, DMA mode
+ and DMA access mode for dual mode */
+ /* Set MULTI bits according to ADC_Mode value */
+ /* Set CKMODE bits according to ADC_Clock value */
+ /* Set MDMA bits according to ADC_DMAAccessMode value */
+ /* Set DMACFG bits according to ADC_DMAMode value */
+ /* Set DELAY bits according to ADC_TwoSamplingDelay value */
+ tmpreg1 |= (uint32_t)(ADC_CommonInitStruct->ADC_Mode |
+ ADC_CommonInitStruct->ADC_Clock |
+ ADC_CommonInitStruct->ADC_DMAAccessMode |
+ (uint32_t)(ADC_CommonInitStruct->ADC_DMAMode << 12) |
+ (uint32_t)((uint32_t)ADC_CommonInitStruct->ADC_TwoSamplingDelay << 8));
+
+ if((ADCx == ADC1) || (ADCx == ADC2))
+ {
+ /* Write to ADC CCR */
+ ADC1_2->CCR = tmpreg1;
+ }
+ else
+ {
+ /* Write to ADC CCR */
+ ADC3_4->CCR = tmpreg1;
+ }
+}
+
+/**
+ * @brief Fills each ADC_CommonInitStruct member with its default value.
+ * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure
+ * which will be initialized.
+ * @retval None
+ */
+void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct)
+{
+ /* Initialize the ADC_Mode member */
+ ADC_CommonInitStruct->ADC_Mode = ADC_Mode_Independent;
+
+ /* initialize the ADC_Clock member */
+ ADC_CommonInitStruct->ADC_Clock = ADC_Clock_AsynClkMode;
+
+ /* Initialize the ADC_DMAAccessMode member */
+ ADC_CommonInitStruct->ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;
+
+ /* Initialize the ADC_DMAMode member */
+ ADC_CommonInitStruct->ADC_DMAMode = ADC_DMAMode_OneShot;
+
+ /* Initialize the ADC_TwoSamplingDelay member */
+ ADC_CommonInitStruct->ADC_TwoSamplingDelay = 0;
+
+}
+
+/**
+ * @brief Enables or disables the specified ADC peripheral.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param NewState: new state of the ADCx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Set the ADEN bit */
+ ADCx->CR |= ADC_CR_ADEN;
+ }
+ else
+ {
+ /* Disable the selected ADC peripheral: Set the ADDIS bit */
+ ADCx->CR |= ADC_CR_ADDIS;
+ }
+}
+
+/**
+ * @brief Starts the selected ADC calibration process.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @retval None
+ */
+void ADC_StartCalibration(ADC_TypeDef* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+ /* Set the ADCAL bit */
+ ADCx->CR |= ADC_CR_ADCAL;
+}
+
+/**
+ * @brief Returns the ADCx calibration value.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @retval None
+ */
+uint32_t ADC_GetCalibrationValue(ADC_TypeDef* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+ /* Return the selected ADC calibration value */
+ return (uint32_t)ADCx->CALFACT;
+}
+
+/**
+ * @brief Sets the ADCx calibration register.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @retval None
+ */
+void ADC_SetCalibrationValue(ADC_TypeDef* ADCx, uint32_t ADC_Calibration)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+ /* Set the ADC calibration register value */
+ ADCx->CALFACT = ADC_Calibration;
+}
+
+/**
+ * @brief Select the ADC calibration mode.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_CalibrationMode: the ADC calibration mode.
+ * This parameter can be one of the following values:
+ * @arg ADC_CalibrationMode_Single: to select the calibration for single channel
+ * @arg ADC_CalibrationMode_Differential: to select the calibration for differential channel
+ * @retval None
+ */
+void ADC_SelectCalibrationMode(ADC_TypeDef* ADCx, uint32_t ADC_CalibrationMode)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_CALIBRATION_MODE(ADC_CalibrationMode));
+ /* Set or Reset the ADCALDIF bit */
+ ADCx->CR &= (~ADC_CR_ADCALDIF);
+ ADCx->CR |= ADC_CalibrationMode;
+
+}
+
+/**
+ * @brief Gets the selected ADC calibration status.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @retval The new state of ADC calibration (SET or RESET).
+ */
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ /* Check the status of CAL bit */
+ if ((ADCx->CR & ADC_CR_ADCAL) != (uint32_t)RESET)
+ {
+ /* CAL bit is set: calibration on going */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAL bit is reset: end of calibration */
+ bitstatus = RESET;
+ }
+ /* Return the CAL bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief ADC Disable Command.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @retval None
+ */
+void ADC_DisableCmd(ADC_TypeDef* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+ /* Set the ADDIS bit */
+ ADCx->CR |= ADC_CR_ADDIS;
+}
+
+
+/**
+ * @brief Gets the selected ADC disable command Status.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @retval The new state of ADC ADC disable command (SET or RESET).
+ */
+FlagStatus ADC_GetDisableCmdStatus(ADC_TypeDef* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+ /* Check the status of ADDIS bit */
+ if ((ADCx->CR & ADC_CR_ADDIS) != (uint32_t)RESET)
+ {
+ /* ADDIS bit is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* ADDIS bit is reset */
+ bitstatus = RESET;
+ }
+ /* Return the ADDIS bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief Enables or disables the specified ADC Voltage Regulator.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param NewState: new state of the ADCx Voltage Regulator.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_VoltageRegulatorCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ /* set the intermediate state before moving the ADC voltage regulator
+ from enable state to disable state or from disable state to enable state */
+ ADCx->CR &= ~(ADC_CR_ADVREGEN);
+
+ if (NewState != DISABLE)
+ {
+ /* Set the ADVREGEN bit 0 */
+ ADCx->CR |= ADC_CR_ADVREGEN_0;
+ }
+ else
+ {
+ /* Set the ADVREGEN bit 1 */
+ ADCx->CR |=ADC_CR_ADVREGEN_1;
+ }
+}
+
+/**
+ * @brief Selectes the differential mode for a specific channel
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_Channel: the ADC channel to configure for the analog watchdog.
+ * This parameter can be one of the following values:
+ * @arg ADC_Channel_1: ADC Channel1 selected
+ * @arg ADC_Channel_2: ADC Channel2 selected
+ * @arg ADC_Channel_3: ADC Channel3 selected
+ * @arg ADC_Channel_4: ADC Channel4 selected
+ * @arg ADC_Channel_5: ADC Channel5 selected
+ * @arg ADC_Channel_6: ADC Channel6 selected
+ * @arg ADC_Channel_7: ADC Channel7 selected
+ * @arg ADC_Channel_8: ADC Channel8 selected
+ * @arg ADC_Channel_9: ADC Channel9 selected
+ * @arg ADC_Channel_10: ADC Channel10 selected
+ * @arg ADC_Channel_11: ADC Channel11 selected
+ * @arg ADC_Channel_12: ADC Channel12 selected
+ * @arg ADC_Channel_13: ADC Channel13 selected
+ * @arg ADC_Channel_14: ADC Channel14 selected
+ * @note : Channel 15, 16 and 17 are fixed to single-ended inputs mode.
+ * @retval None
+ */
+void ADC_SelectDifferentialMode(ADC_TypeDef* ADCx, uint8_t ADC_Channel, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_DIFFCHANNEL(ADC_Channel));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Set the DIFSEL bit */
+ ADCx->DIFSEL |= (uint32_t)(1 << ADC_Channel );
+ }
+ else
+ {
+ /* Reset the DIFSEL bit */
+ ADCx->DIFSEL &= ~(uint32_t)(1 << ADC_Channel);
+ }
+}
+
+/**
+ * @brief Selects the Queue Of Context Mode for injected channels.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param NewState: new state of the Queue Of Context Mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_SelectQueueOfContextMode(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Set the JQM bit */
+ ADCx->CFGR |= (uint32_t)(ADC_CFGR_JQM );
+ }
+ else
+ {
+ /* Reset the JQM bit */
+ ADCx->CFGR &= ~(uint32_t)(ADC_CFGR_JQM);
+ }
+}
+
+/**
+ * @brief Selects the ADC Delayed Conversion Mode.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param NewState: new state of the ADC Delayed Conversion Mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_AutoDelayCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Set the AUTDLY bit */
+ ADCx->CFGR |= (uint32_t)(ADC_CFGR_AUTDLY );
+ }
+ else
+ {
+ /* Reset the AUTDLY bit */
+ ADCx->CFGR &= ~(uint32_t)(ADC_CFGR_AUTDLY);
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Group2 Analog Watchdog configuration functions
+ * @brief Analog Watchdog configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Analog Watchdog configuration functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure the 3 Analog Watchdogs
+ (AWDG1, AWDG2 and AWDG3) in the ADC.
+
+ [..] A typical configuration Analog Watchdog is done following these steps :
+ (#) The ADC guarded channel(s) is (are) selected using the functions:
+ (++) ADC_AnalogWatchdog1SingleChannelConfig().
+ (++) ADC_AnalogWatchdog2SingleChannelConfig().
+ (++) ADC_AnalogWatchdog3SingleChannelConfig().
+
+ (#) The Analog watchdog lower and higher threshold are configured using the functions:
+ (++) ADC_AnalogWatchdog1ThresholdsConfig().
+ (++) ADC_AnalogWatchdog2ThresholdsConfig().
+ (++) ADC_AnalogWatchdog3ThresholdsConfig().
+
+ (#) The Analog watchdog is enabled and configured to enable the check, on one
+ or more channels, using the function:
+ (++) ADC_AnalogWatchdogCmd().
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the analog watchdog on single/all regular
+ * or injected channels
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration.
+ * This parameter can be one of the following values:
+ * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel
+ * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel
+ * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel
+ * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel
+ * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel
+ * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels
+ * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog
+ * @retval None
+ */
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
+ /* Get the old register value */
+ tmpreg = ADCx->CFGR;
+ /* Clear AWDEN, AWDENJ and AWDSGL bits */
+ tmpreg &= ~(uint32_t)(ADC_CFGR_AWD1SGL|ADC_CFGR_AWD1EN|ADC_CFGR_JAWD1EN);
+ /* Set the analog watchdog enable mode */
+ tmpreg |= ADC_AnalogWatchdog;
+ /* Store the new register value */
+ ADCx->CFGR = tmpreg;
+}
+
+/**
+ * @brief Configures the high and low thresholds of the analog watchdog1.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param HighThreshold: the ADC analog watchdog High threshold value.
+ * This parameter must be a 12bit value.
+ * @param LowThreshold: the ADC analog watchdog Low threshold value.
+ * This parameter must be a 12bit value.
+ * @retval None
+ */
+void ADC_AnalogWatchdog1ThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
+ uint16_t LowThreshold)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_THRESHOLD(HighThreshold));
+ assert_param(IS_ADC_THRESHOLD(LowThreshold));
+ /* Set the ADCx high threshold */
+ ADCx->TR1 &= ~(uint32_t)ADC_TR1_HT1;
+ ADCx->TR1 |= (uint32_t)((uint32_t)HighThreshold << 16);
+
+ /* Set the ADCx low threshold */
+ ADCx->TR1 &= ~(uint32_t)ADC_TR1_LT1;
+ ADCx->TR1 |= LowThreshold;
+}
+
+/**
+ * @brief Configures the high and low thresholds of the analog watchdog2.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param HighThreshold: the ADC analog watchdog High threshold value.
+ * This parameter must be a 8bit value.
+ * @param LowThreshold: the ADC analog watchdog Low threshold value.
+ * This parameter must be a 8bit value.
+ * @retval None
+ */
+void ADC_AnalogWatchdog2ThresholdsConfig(ADC_TypeDef* ADCx, uint8_t HighThreshold,
+ uint8_t LowThreshold)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+ /* Set the ADCx high threshold */
+ ADCx->TR2 &= ~(uint32_t)ADC_TR2_HT2;
+ ADCx->TR2 |= (uint32_t)((uint32_t)HighThreshold << 16);
+
+ /* Set the ADCx low threshold */
+ ADCx->TR2 &= ~(uint32_t)ADC_TR2_LT2;
+ ADCx->TR2 |= LowThreshold;
+}
+
+/**
+ * @brief Configures the high and low thresholds of the analog watchdog3.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param HighThreshold: the ADC analog watchdog High threshold value.
+ * This parameter must be a 8bit value.
+ * @param LowThreshold: the ADC analog watchdog Low threshold value.
+ * This parameter must be a 8bit value.
+ * @retval None
+ */
+void ADC_AnalogWatchdog3ThresholdsConfig(ADC_TypeDef* ADCx, uint8_t HighThreshold,
+ uint8_t LowThreshold)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+ /* Set the ADCx high threshold */
+ ADCx->TR3 &= ~(uint32_t)ADC_TR3_HT3;
+ ADCx->TR3 |= (uint32_t)((uint32_t)HighThreshold << 16);
+
+ /* Set the ADCx low threshold */
+ ADCx->TR3 &= ~(uint32_t)ADC_TR3_LT3;
+ ADCx->TR3 |= LowThreshold;
+}
+
+/**
+ * @brief Configures the analog watchdog 2 guarded single channel
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_Channel: the ADC channel to configure for the analog watchdog.
+ * This parameter can be one of the following values:
+ * @arg ADC_Channel_1: ADC Channel1 selected
+ * @arg ADC_Channel_2: ADC Channel2 selected
+ * @arg ADC_Channel_3: ADC Channel3 selected
+ * @arg ADC_Channel_4: ADC Channel4 selected
+ * @arg ADC_Channel_5: ADC Channel5 selected
+ * @arg ADC_Channel_6: ADC Channel6 selected
+ * @arg ADC_Channel_7: ADC Channel7 selected
+ * @arg ADC_Channel_8: ADC Channel8 selected
+ * @arg ADC_Channel_9: ADC Channel9 selected
+ * @arg ADC_Channel_10: ADC Channel10 selected
+ * @arg ADC_Channel_11: ADC Channel11 selected
+ * @arg ADC_Channel_12: ADC Channel12 selected
+ * @arg ADC_Channel_13: ADC Channel13 selected
+ * @arg ADC_Channel_14: ADC Channel14 selected
+ * @arg ADC_Channel_15: ADC Channel15 selected
+ * @arg ADC_Channel_16: ADC Channel16 selected
+ * @arg ADC_Channel_17: ADC Channel17 selected
+ * @arg ADC_Channel_18: ADC Channel18 selected
+ * @retval None
+ */
+void ADC_AnalogWatchdog1SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));
+ /* Get the old register value */
+ tmpreg = ADCx->CFGR;
+ /* Clear the Analog watchdog channel select bits */
+ tmpreg &= ~(uint32_t)ADC_CFGR_AWD1CH;
+ /* Set the Analog watchdog channel */
+ tmpreg |= (uint32_t)((uint32_t)ADC_Channel << 26);
+ /* Store the new register value */
+ ADCx->CFGR = tmpreg;
+}
+
+/**
+ * @brief Configures the analog watchdog 2 guarded single channel
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_Channel: the ADC channel to configure for the analog watchdog.
+ * This parameter can be one of the following values:
+ * @arg ADC_Channel_1: ADC Channel1 selected
+ * @arg ADC_Channel_2: ADC Channel2 selected
+ * @arg ADC_Channel_3: ADC Channel3 selected
+ * @arg ADC_Channel_4: ADC Channel4 selected
+ * @arg ADC_Channel_5: ADC Channel5 selected
+ * @arg ADC_Channel_6: ADC Channel6 selected
+ * @arg ADC_Channel_7: ADC Channel7 selected
+ * @arg ADC_Channel_8: ADC Channel8 selected
+ * @arg ADC_Channel_9: ADC Channel9 selected
+ * @arg ADC_Channel_10: ADC Channel10 selected
+ * @arg ADC_Channel_11: ADC Channel11 selected
+ * @arg ADC_Channel_12: ADC Channel12 selected
+ * @arg ADC_Channel_13: ADC Channel13 selected
+ * @arg ADC_Channel_14: ADC Channel14 selected
+ * @arg ADC_Channel_15: ADC Channel15 selected
+ * @arg ADC_Channel_16: ADC Channel16 selected
+ * @arg ADC_Channel_17: ADC Channel17 selected
+ * @arg ADC_Channel_18: ADC Channel18 selected
+ * @retval None
+ */
+void ADC_AnalogWatchdog2SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));
+ /* Get the old register value */
+ tmpreg = ADCx->AWD2CR;
+ /* Clear the Analog watchdog channel select bits */
+ tmpreg &= ~(uint32_t)ADC_AWD2CR_AWD2CH;
+ /* Set the Analog watchdog channel */
+ tmpreg |= (uint32_t)1 << (ADC_Channel);
+ /* Store the new register value */
+ ADCx->AWD2CR |= tmpreg;
+}
+
+/**
+ * @brief Configures the analog watchdog 3 guarded single channel
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_Channel: the ADC channel to configure for the analog watchdog.
+ * This parameter can be one of the following values:
+ * @arg ADC_Channel_1: ADC Channel1 selected
+ * @arg ADC_Channel_2: ADC Channel2 selected
+ * @arg ADC_Channel_3: ADC Channel3 selected
+ * @arg ADC_Channel_4: ADC Channel4 selected
+ * @arg ADC_Channel_5: ADC Channel5 selected
+ * @arg ADC_Channel_6: ADC Channel6 selected
+ * @arg ADC_Channel_7: ADC Channel7 selected
+ * @arg ADC_Channel_8: ADC Channel8 selected
+ * @arg ADC_Channel_9: ADC Channel9 selected
+ * @arg ADC_Channel_10: ADC Channel10 selected
+ * @arg ADC_Channel_11: ADC Channel11 selected
+ * @arg ADC_Channel_12: ADC Channel12 selected
+ * @arg ADC_Channel_13: ADC Channel13 selected
+ * @arg ADC_Channel_14: ADC Channel14 selected
+ * @arg ADC_Channel_15: ADC Channel15 selected
+ * @arg ADC_Channel_16: ADC Channel16 selected
+ * @arg ADC_Channel_17: ADC Channel17 selected
+ * @arg ADC_Channel_18: ADC Channel18 selected
+ * @retval None
+ */
+void ADC_AnalogWatchdog3SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));
+ /* Get the old register value */
+ tmpreg = ADCx->AWD3CR;
+ /* Clear the Analog watchdog channel select bits */
+ tmpreg &= ~(uint32_t)ADC_AWD3CR_AWD3CH;
+ /* Set the Analog watchdog channel */
+ tmpreg |= (uint32_t)1 << (ADC_Channel);
+ /* Store the new register value */
+ ADCx->AWD3CR |= tmpreg;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Group3 Temperature Sensor - Vrefint (Internal Reference Voltage) and VBAT management functions
+ * @brief Vbat, Temperature Sensor & Vrefint (Internal Reference Voltage) management function
+ *
+@verbatim
+ ====================================================================================================
+ ##### Temperature Sensor - Vrefint (Internal Reference Voltage) and VBAT management functions #####
+ ====================================================================================================
+
+ [..] This section provides a function allowing to enable/ disable the internal
+ connections between the ADC and the Vbat/2, Temperature Sensor and the Vrefint source.
+
+ [..] A typical configuration to get the Temperature sensor and Vrefint channels
+ voltages is done following these steps :
+ (#) Enable the internal connection of Vbat/2, Temperature sensor and Vrefint sources
+ with the ADC channels using:
+ (++) ADC_TempSensorCmd()
+ (++) ADC_VrefintCmd()
+ (++) ADC_VbatCmd()
+
+ (#) select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint and/or ADC_Channel_Vbat using
+ (++) ADC_RegularChannelConfig() or
+ (++) ADC_InjectedInit() functions
+
+ (#) Get the voltage values, using:
+ (++) ADC_GetConversionValue() or
+ (++) ADC_GetInjectedConversionValue().
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the temperature sensor channel.
+ * @param ADCx: where x can be 1 to select the ADC peripheral.
+ * @param NewState: new state of the temperature sensor.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_TempSensorCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the temperature sensor channel*/
+ ADC1_2->CCR |= ADC12_CCR_TSEN;
+ }
+ else
+ {
+ /* Disable the temperature sensor channel*/
+ ADC1_2->CCR &= ~(uint32_t)ADC12_CCR_TSEN;
+ }
+}
+
+/**
+ * @brief Enables or disables the Vrefint channel.
+ * @param ADCx: where x can be 1 or 4 to select the ADC peripheral.
+ * @param NewState: new state of the Vrefint.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_VrefintCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if((ADCx == ADC1) || (ADCx == ADC2))
+ {
+ if (NewState != DISABLE)
+ {
+ /* Enable the Vrefint channel*/
+ ADC1_2->CCR |= ADC12_CCR_VREFEN;
+ }
+ else
+ {
+ /* Disable the Vrefint channel*/
+ ADC1_2->CCR &= ~(uint32_t)ADC12_CCR_VREFEN;
+ }
+ }
+ else
+ {
+ if (NewState != DISABLE)
+ {
+ /* Enable the Vrefint channel*/
+ ADC3_4->CCR |= ADC34_CCR_VREFEN;
+ }
+ else
+ {
+ /* Disable the Vrefint channel*/
+ ADC3_4->CCR &= ~(uint32_t)ADC34_CCR_VREFEN;
+ }
+ }
+}
+
+/**
+ * @brief Enables or disables the Vbat channel.
+ * @param ADCx: where x can be 1 to select the ADC peripheral.
+ * @param NewState: new state of the Vbat.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_VbatCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the Vbat channel*/
+ ADC1_2->CCR |= ADC12_CCR_VBATEN;
+ }
+ else
+ {
+ /* Disable the Vbat channel*/
+ ADC1_2->CCR &= ~(uint32_t)ADC12_CCR_VBATEN;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Group4 Regular Channels Configuration functions
+ * @brief Regular Channels Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Channels Configuration functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to manage the ADC regular channels.
+
+ [..] To configure a regular sequence of channels use:
+ (#) ADC_RegularChannelConfig()
+ this fuction allows:
+ (++) Configure the rank in the regular group sequencer for each channel
+ (++) Configure the sampling time for each channel
+
+ (#) ADC_RegularChannelSequencerLengthConfig() to set the length of the regular sequencer
+
+ [..] The regular trigger is configured using the following functions:
+ (#) ADC_SelectExternalTrigger()
+ (#) ADC_ExternalTriggerPolarityConfig()
+
+ [..] The start and the stop conversion are controlled by:
+ (#) ADC_StartConversion()
+ (#) ADC_StopConversion()
+
+ [..]
+ (@)Please Note that the following features for regular channels are configurated
+ using the ADC_Init() function :
+ (++) continuous mode activation
+ (++) Resolution
+ (++) Data Alignement
+ (++) Overrun Mode.
+
+ [..] Get the conversion data: This subsection provides an important function in
+ the ADC peripheral since it returns the converted data of the current
+ regular channel. When the Conversion value is read, the EOC Flag is
+ automatically cleared.
+
+ [..] To configure the discontinous mode, the following functions should be used:
+ (#) ADC_DiscModeChannelCountConfig() to configure the number of discontinuous channel to be converted.
+ (#) ADC_DiscModeCmd() to enable the discontinuous mode.
+
+ [..] To configure and enable/disable the Channel offset use the functions:
+ (++) ADC_SetChannelOffset1()
+ (++) ADC_SetChannelOffset2()
+ (++) ADC_SetChannelOffset3()
+ (++) ADC_SetChannelOffset4()
+ (++) ADC_ChannelOffset1Cmd()
+ (++) ADC_ChannelOffset2Cmd()
+ (++) ADC_ChannelOffset3Cmd()
+ (++) ADC_ChannelOffset4Cmd()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures for the selected ADC regular channel its corresponding
+ * rank in the sequencer and its sample time.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_Channel: the ADC channel to configure.
+ * This parameter can be one of the following values:
+ * @arg ADC_Channel_1: ADC Channel1 selected
+ * @arg ADC_Channel_2: ADC Channel2 selected
+ * @arg ADC_Channel_3: ADC Channel3 selected
+ * @arg ADC_Channel_4: ADC Channel4 selected
+ * @arg ADC_Channel_5: ADC Channel5 selected
+ * @arg ADC_Channel_6: ADC Channel6 selected
+ * @arg ADC_Channel_7: ADC Channel7 selected
+ * @arg ADC_Channel_8: ADC Channel8 selected
+ * @arg ADC_Channel_9: ADC Channel9 selected
+ * @arg ADC_Channel_10: ADC Channel10 selected
+ * @arg ADC_Channel_11: ADC Channel11 selected
+ * @arg ADC_Channel_12: ADC Channel12 selected
+ * @arg ADC_Channel_13: ADC Channel13 selected
+ * @arg ADC_Channel_14: ADC Channel14 selected
+ * @arg ADC_Channel_15: ADC Channel15 selected
+ * @arg ADC_Channel_16: ADC Channel16 selected
+ * @arg ADC_Channel_17: ADC Channel17 selected
+ * @arg ADC_Channel_18: ADC Channel18 selected
+ * @param Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16.
+ * @param ADC_SampleTime: The sample time value to be set for the selected channel.
+ * This parameter can be one of the following values:
+ * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
+ * @arg ADC_SampleTime_2Cycles5: Sample time equal to 2.5 cycles
+ * @arg ADC_SampleTime_4Cycles5: Sample time equal to 4.5 cycles
+ * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
+ * @arg ADC_SampleTime_19Cycles5: Sample time equal to 19.5 cycles
+ * @arg ADC_SampleTime_61Cycles5: Sample time equal to 61.5 cycles
+ * @arg ADC_SampleTime_181Cycles5: Sample time equal to 181.5 cycles
+ * @arg ADC_SampleTime_601Cycles5: Sample time equal to 601.5 cycles
+ * @retval None
+ */
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));
+ assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
+
+ /* Regular sequence configuration */
+ /* For Rank 1 to 4 */
+ if (Rank < 5)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SQR1;
+ /* Calculate the mask to clear */
+ tmpreg2 = 0x1F << (6 * (Rank ));
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)(ADC_Channel) << (6 * (Rank));
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SQR1 = tmpreg1;
+ }
+ /* For Rank 5 to 9 */
+ else if (Rank < 10)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SQR2;
+ /* Calculate the mask to clear */
+ tmpreg2 = ADC_SQR2_SQ5 << (6 * (Rank - 5));
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)(ADC_Channel) << (6 * (Rank - 5));
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SQR2 = tmpreg1;
+ }
+ /* For Rank 10 to 14 */
+ else if (Rank < 15)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SQR3;
+ /* Calculate the mask to clear */
+ tmpreg2 = ADC_SQR3_SQ10 << (6 * (Rank - 10));
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)(ADC_Channel) << (6 * (Rank - 10));
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SQR3 = tmpreg1;
+ }
+ else
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SQR4;
+ /* Calculate the mask to clear */
+ tmpreg2 = ADC_SQR3_SQ15 << (6 * (Rank - 15));
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)(ADC_Channel) << (6 * (Rank - 15));
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SQR4 = tmpreg1;
+ }
+
+ /* Channel sampling configuration */
+ /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
+ if (ADC_Channel > ADC_Channel_9)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SMPR2;
+ /* Calculate the mask to clear */
+ tmpreg2 = ADC_SMPR2_SMP10 << (3 * (ADC_Channel - 10));
+ /* Clear the old channel sample time */
+ ADCx->SMPR2 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ ADCx->SMPR2 |= (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
+
+ }
+ else /* ADC_Channel include in ADC_Channel_[0..9] */
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SMPR1;
+ /* Calculate the mask to clear */
+ tmpreg2 = ADC_SMPR1_SMP1 << (3 * (ADC_Channel - 1));
+ /* Clear the old channel sample time */
+ ADCx->SMPR1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ ADCx->SMPR1 |= (uint32_t)ADC_SampleTime << (3 * (ADC_Channel));
+ }
+}
+
+/**
+ * @brief Sets the ADC regular channel sequence lenght.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param SequenceLength: The Regular sequence length. This parameter must be between 1 to 16.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_RegularChannelSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t SequencerLength)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+ /* Configure the ADC sequence lenght */
+ ADCx->SQR1 &= ~(uint32_t)ADC_SQR1_L;
+ ADCx->SQR1 |= (uint32_t)(SequencerLength - 1);
+}
+
+/**
+ * @brief External Trigger Enable and Polarity Selection for regular channels.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_ExternalTrigConvEvent: ADC external Trigger source.
+ * This parameter can be one of the following values:
+ * @arg ADC_ExternalTrigger_Event0: External trigger event 0
+ * @arg ADC_ExternalTrigger_Event1: External trigger event 1
+ * @arg ADC_ExternalTrigger_Event2: External trigger event 2
+ * @arg ADC_ExternalTrigger_Event3: External trigger event 3
+ * @arg ADC_ExternalTrigger_Event4: External trigger event 4
+ * @arg ADC_ExternalTrigger_Event5: External trigger event 5
+ * @arg ADC_ExternalTrigger_Event6: External trigger event 6
+ * @arg ADC_ExternalTrigger_Event7: External trigger event 7
+ * @arg ADC_ExternalTrigger_Event8: External trigger event 8
+ * @arg ADC_ExternalTrigger_Event9: External trigger event 9
+ * @arg ADC_ExternalTrigger_Event10: External trigger event 10
+ * @arg ADC_ExternalTrigger_Event11: External trigger event 11
+ * @arg ADC_ExternalTrigger_Event12: External trigger event 12
+ * @arg ADC_ExternalTrigger_Event13: External trigger event 13
+ * @arg ADC_ExternalTrigger_Event14: External trigger event 14
+ * @arg ADC_ExternalTrigger_Event15: External trigger event 15
+ * @param ADC_ExternalTrigEventEdge: ADC external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg ADC_ExternalTrigEventEdge_OFF: Hardware trigger detection disabled
+ * (conversions can be launched by software)
+ * @arg ADC_ExternalTrigEventEdge_RisingEdge: Hardware trigger detection on the rising edge
+ * @arg ADC_ExternalTrigEventEdge_FallingEdge: Hardware trigger detection on the falling edge
+ * @arg ADC_ExternalTrigEventEdge_BothEdge: Hardware trigger detection on both the rising and falling edges
+ * @retval None
+ */
+void ADC_ExternalTriggerConfig(ADC_TypeDef* ADCx, uint16_t ADC_ExternalTrigConvEvent, uint16_t ADC_ExternalTrigEventEdge)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_EXT_TRIG(ADC_ExternalTrigConvEvent));
+ assert_param(IS_EXTERNALTRIG_EDGE(ADC_ExternalTrigEventEdge));
+
+ /* Disable the selected ADC conversion on external event */
+ ADCx->CFGR &= ~(ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL);
+ ADCx->CFGR |= (uint32_t)(ADC_ExternalTrigEventEdge | ADC_ExternalTrigConvEvent);
+}
+
+/**
+ * @brief Enables or disables the selected ADC start conversion .
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @retval None
+ */
+void ADC_StartConversion(ADC_TypeDef* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+ /* Set the ADSTART bit */
+ ADCx->CR |= ADC_CR_ADSTART;
+}
+
+/**
+ * @brief Gets the selected ADC start conversion Status.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @retval The new state of ADC start conversion (SET or RESET).
+ */
+FlagStatus ADC_GetStartConversionStatus(ADC_TypeDef* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ /* Check the status of ADSTART bit */
+ if ((ADCx->CR & ADC_CR_ADSTART) != (uint32_t)RESET)
+ {
+ /* ADSTART bit is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* ADSTART bit is reset */
+ bitstatus = RESET;
+ }
+ /* Return the ADSTART bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief Stops the selected ADC ongoing conversion.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @retval None
+ */
+void ADC_StopConversion(ADC_TypeDef* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+ /* Set the ADSTP bit */
+ ADCx->CR |= ADC_CR_ADSTP;
+}
+
+
+/**
+ * @brief Configures the discontinuous mode for the selected ADC regular
+ * group channel.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Number: specifies the discontinuous mode regular channel
+ * count value. This number must be between 1 and 8.
+ * @retval None
+ */
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)
+{
+ uint32_t tmpreg1 = 0;
+ uint32_t tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));
+ /* Get the old register value */
+ tmpreg1 = ADCx->CFGR;
+ /* Clear the old discontinuous mode channel count */
+ tmpreg1 &= ~(uint32_t)(ADC_CFGR_DISCNUM);
+ /* Set the discontinuous mode channel count */
+ tmpreg2 = Number - 1;
+ tmpreg1 |= tmpreg2 << 17;
+ /* Store the new register value */
+ ADCx->CFGR = tmpreg1;
+}
+
+/**
+ * @brief Enables or disables the discontinuous mode on regular group
+ * channel for the specified ADC
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC discontinuous mode
+ * on regular group channel.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC regular discontinuous mode */
+ ADCx->CFGR |= ADC_CFGR_DISCEN;
+ }
+ else
+ {
+ /* Disable the selected ADC regular discontinuous mode */
+ ADCx->CFGR &= ~(uint32_t)(ADC_CFGR_DISCEN);
+ }
+}
+
+/**
+ * @brief Returns the last ADCx conversion result data for regular channel.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @retval The Data conversion value.
+ */
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ /* Return the selected ADC conversion value */
+ return (uint16_t) ADCx->DR;
+}
+
+/**
+ * @brief Returns the last ADC1, ADC2, ADC3 and ADC4 regular conversions results
+ * data in the selected dual mode.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @retval The Data conversion value.
+ * @note In dual mode, the value returned by this function is as following
+ * Data[15:0] : these bits contain the regular data of the Master ADC.
+ * Data[31:16]: these bits contain the regular data of the Slave ADC.
+ */
+uint32_t ADC_GetDualModeConversionValue(ADC_TypeDef* ADCx)
+{
+ uint32_t tmpreg1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+ if((ADCx == ADC1) || (ADCx== ADC2))
+ {
+ /* Get the dual mode conversion value */
+ tmpreg1 = ADC1_2->CDR;
+ }
+ else
+ {
+ /* Get the dual mode conversion value */
+ tmpreg1 = ADC3_4->CDR;
+ }
+ /* Return the dual mode conversion value */
+ return (uint32_t) tmpreg1;
+}
+
+/**
+ * @brief Set the ADC channels conversion value offset1
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_Channel: the ADC channel to configure.
+ * This parameter can be one of the following values:
+ * @arg ADC_Channel_1: ADC Channel1 selected
+ * @arg ADC_Channel_2: ADC Channel2 selected
+ * @arg ADC_Channel_3: ADC Channel3 selected
+ * @arg ADC_Channel_4: ADC Channel4 selected
+ * @arg ADC_Channel_5: ADC Channel5 selected
+ * @arg ADC_Channel_6: ADC Channel6 selected
+ * @arg ADC_Channel_7: ADC Channel7 selected
+ * @arg ADC_Channel_8: ADC Channel8 selected
+ * @arg ADC_Channel_9: ADC Channel9 selected
+ * @arg ADC_Channel_10: ADC Channel10 selected
+ * @arg ADC_Channel_11: ADC Channel11 selected
+ * @arg ADC_Channel_12: ADC Channel12 selected
+ * @arg ADC_Channel_13: ADC Channel13 selected
+ * @arg ADC_Channel_14: ADC Channel14 selected
+ * @arg ADC_Channel_15: ADC Channel15 selected
+ * @arg ADC_Channel_16: ADC Channel16 selected
+ * @arg ADC_Channel_17: ADC Channel17 selected
+ * @arg ADC_Channel_18: ADC Channel18 selected
+ * @param Offset: the offset value for the selected ADC Channel
+ * This parameter must be a 12bit value.
+ * @retval None
+ */
+void ADC_SetChannelOffset1(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));
+ assert_param(IS_ADC_OFFSET(Offset));
+
+ /* Select the Channel */
+ ADCx->OFR1 &= ~ (uint32_t) ADC_OFR1_OFFSET1_CH;
+ ADCx->OFR1 |= (uint32_t)((uint32_t)ADC_Channel << 26);
+
+ /* Set the data offset */
+ ADCx->OFR1 &= ~ (uint32_t) ADC_OFR1_OFFSET1;
+ ADCx->OFR1 |= (uint32_t)Offset;
+}
+
+/**
+ * @brief Set the ADC channels conversion value offset2
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_Channel: the ADC channel to configure.
+ * This parameter can be one of the following values:
+ * @arg ADC_Channel_1: ADC Channel1 selected
+ * @arg ADC_Channel_2: ADC Channel2 selected
+ * @arg ADC_Channel_3: ADC Channel3 selected
+ * @arg ADC_Channel_4: ADC Channel4 selected
+ * @arg ADC_Channel_5: ADC Channel5 selected
+ * @arg ADC_Channel_6: ADC Channel6 selected
+ * @arg ADC_Channel_7: ADC Channel7 selected
+ * @arg ADC_Channel_8: ADC Channel8 selected
+ * @arg ADC_Channel_9: ADC Channel9 selected
+ * @arg ADC_Channel_10: ADC Channel10 selected
+ * @arg ADC_Channel_11: ADC Channel11 selected
+ * @arg ADC_Channel_12: ADC Channel12 selected
+ * @arg ADC_Channel_13: ADC Channel13 selected
+ * @arg ADC_Channel_14: ADC Channel14 selected
+ * @arg ADC_Channel_15: ADC Channel15 selected
+ * @arg ADC_Channel_16: ADC Channel16 selected
+ * @arg ADC_Channel_17: ADC Channel17 selected
+ * @arg ADC_Channel_18: ADC Channel18 selected
+ * @param Offset: the offset value for the selected ADC Channel
+ * This parameter must be a 12bit value.
+ * @retval None
+ */
+void ADC_SetChannelOffset2(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));
+ assert_param(IS_ADC_OFFSET(Offset));
+
+ /* Select the Channel */
+ ADCx->OFR2 &= ~ (uint32_t) ADC_OFR2_OFFSET2_CH;
+ ADCx->OFR2 |= (uint32_t)((uint32_t)ADC_Channel << 26);
+
+ /* Set the data offset */
+ ADCx->OFR2 &= ~ (uint32_t) ADC_OFR2_OFFSET2;
+ ADCx->OFR2 |= (uint32_t)Offset;
+}
+
+/**
+ * @brief Set the ADC channels conversion value offset3
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_Channel: the ADC channel to configure.
+ * This parameter can be one of the following values:
+ * @arg ADC_Channel_1: ADC Channel1 selected
+ * @arg ADC_Channel_2: ADC Channel2 selected
+ * @arg ADC_Channel_3: ADC Channel3 selected
+ * @arg ADC_Channel_4: ADC Channel4 selected
+ * @arg ADC_Channel_5: ADC Channel5 selected
+ * @arg ADC_Channel_6: ADC Channel6 selected
+ * @arg ADC_Channel_7: ADC Channel7 selected
+ * @arg ADC_Channel_8: ADC Channel8 selected
+ * @arg ADC_Channel_9: ADC Channel9 selected
+ * @arg ADC_Channel_10: ADC Channel10 selected
+ * @arg ADC_Channel_11: ADC Channel11 selected
+ * @arg ADC_Channel_12: ADC Channel12 selected
+ * @arg ADC_Channel_13: ADC Channel13 selected
+ * @arg ADC_Channel_14: ADC Channel14 selected
+ * @arg ADC_Channel_15: ADC Channel15 selected
+ * @arg ADC_Channel_16: ADC Channel16 selected
+ * @arg ADC_Channel_17: ADC Channel17 selected
+ * @arg ADC_Channel_18: ADC Channel18 selected
+ * @param Offset: the offset value for the selected ADC Channel
+ * This parameter must be a 12bit value.
+ * @retval None
+ */
+void ADC_SetChannelOffset3(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));
+ assert_param(IS_ADC_OFFSET(Offset));
+
+ /* Select the Channel */
+ ADCx->OFR3 &= ~ (uint32_t) ADC_OFR3_OFFSET3_CH;
+ ADCx->OFR3 |= (uint32_t)((uint32_t)ADC_Channel << 26);
+
+ /* Set the data offset */
+ ADCx->OFR3 &= ~ (uint32_t) ADC_OFR3_OFFSET3;
+ ADCx->OFR3 |= (uint32_t)Offset;
+}
+
+/**
+ * @brief Set the ADC channels conversion value offset4
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_Channel: the ADC channel to configure.
+ * This parameter can be one of the following values:
+ * @arg ADC_Channel_1: ADC Channel1 selected
+ * @arg ADC_Channel_2: ADC Channel2 selected
+ * @arg ADC_Channel_3: ADC Channel3 selected
+ * @arg ADC_Channel_4: ADC Channel4 selected
+ * @arg ADC_Channel_5: ADC Channel5 selected
+ * @arg ADC_Channel_6: ADC Channel6 selected
+ * @arg ADC_Channel_7: ADC Channel7 selected
+ * @arg ADC_Channel_8: ADC Channel8 selected
+ * @arg ADC_Channel_9: ADC Channel9 selected
+ * @arg ADC_Channel_10: ADC Channel10 selected
+ * @arg ADC_Channel_11: ADC Channel11 selected
+ * @arg ADC_Channel_12: ADC Channel12 selected
+ * @arg ADC_Channel_13: ADC Channel13 selected
+ * @arg ADC_Channel_14: ADC Channel14 selected
+ * @arg ADC_Channel_15: ADC Channel15 selected
+ * @arg ADC_Channel_16: ADC Channel16 selected
+ * @arg ADC_Channel_17: ADC Channel17 selected
+ * @arg ADC_Channel_18: ADC Channel18 selected
+ * @param Offset: the offset value for the selected ADC Channel
+ * This parameter must be a 12bit value.
+ * @retval None
+ */
+void ADC_SetChannelOffset4(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));
+ assert_param(IS_ADC_OFFSET(Offset));
+
+ /* Select the Channel */
+ ADCx->OFR4 &= ~ (uint32_t) ADC_OFR4_OFFSET4_CH;
+ ADCx->OFR4 |= (uint32_t)((uint32_t)ADC_Channel << 26);
+
+ /* Set the data offset */
+ ADCx->OFR4 &= ~ (uint32_t) ADC_OFR4_OFFSET4;
+ ADCx->OFR4 |= (uint32_t)Offset;
+}
+
+/**
+ * @brief Enables or disables the Offset1.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param NewState: new state of the ADCx offset1.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_ChannelOffset1Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Set the OFFSET1_EN bit */
+ ADCx->OFR1 |= ADC_OFR1_OFFSET1_EN;
+ }
+ else
+ {
+ /* Reset the OFFSET1_EN bit */
+ ADCx->OFR1 &= ~(ADC_OFR1_OFFSET1_EN);
+ }
+}
+
+/**
+ * @brief Enables or disables the Offset2.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param NewState: new state of the ADCx offset2.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_ChannelOffset2Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Set the OFFSET1_EN bit */
+ ADCx->OFR2 |= ADC_OFR2_OFFSET2_EN;
+ }
+ else
+ {
+ /* Reset the OFFSET1_EN bit */
+ ADCx->OFR2 &= ~(ADC_OFR2_OFFSET2_EN);
+ }
+}
+
+/**
+ * @brief Enables or disables the Offset3.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param NewState: new state of the ADCx offset3.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_ChannelOffset3Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Set the OFFSET1_EN bit */
+ ADCx->OFR3 |= ADC_OFR3_OFFSET3_EN;
+ }
+ else
+ {
+ /* Reset the OFFSET1_EN bit */
+ ADCx->OFR3 &= ~(ADC_OFR3_OFFSET3_EN);
+ }
+}
+
+/**
+ * @brief Enables or disables the Offset4.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param NewState: new state of the ADCx offset4.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_ChannelOffset4Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Set the OFFSET1_EN bit */
+ ADCx->OFR4 |= ADC_OFR4_OFFSET4_EN;
+ }
+ else
+ {
+ /* Reset the OFFSET1_EN bit */
+ ADCx->OFR4 &= ~(ADC_OFR4_OFFSET4_EN);
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Group5 Regular Channels DMA Configuration functions
+ * @brief Regular Channels DMA Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Regular Channels DMA Configuration functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure the DMA for ADC regular
+ channels. Since converted regular channel values are stored into a unique data register,
+ it is useful to use DMA for conversion of more than one regular channel. This
+ avoids the loss of the data already stored in the ADC Data register.
+
+ (#) ADC_DMACmd() function is used to enable the ADC DMA mode, after each
+ conversion of a regular channel, a DMA request is generated.
+ (#) ADC_DMAConfig() function is used to select between the one shot DMA mode
+ or the circular DMA mode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the specified ADC DMA request.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC DMA transfer.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_DMA_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC DMA request */
+ ADCx->CFGR |= ADC_CFGR_DMAEN;
+ }
+ else
+ {
+ /* Disable the selected ADC DMA request */
+ ADCx->CFGR &= ~(uint32_t)ADC_CFGR_DMAEN;
+ }
+}
+
+/**
+ * @brief Configure ADC DMA mode.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_DMAMode: select the ADC DMA mode.
+ * This parameter can be one of the following values:
+ * @arg ADC_DMAMode_OneShot: ADC DMA Oneshot mode
+ * @arg ADC_DMAMode_Circular: ADC DMA circular mode
+ * @retval None
+ */
+void ADC_DMAConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMAMode)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_DMA_PERIPH(ADCx));
+ assert_param(IS_ADC_DMA_MODE(ADC_DMAMode));
+
+ /* Set or reset the DMACFG bit */
+ ADCx->CFGR &= ~(uint32_t)ADC_CFGR_DMACFG;
+ ADCx->CFGR |= ADC_DMAMode;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Group6 Injected channels Configuration functions
+ * @brief Injected channels Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Injected channels Configuration functions #####
+ ===============================================================================
+
+ [..] This section provide functions allowing to manage the ADC Injected channels,
+ it is composed of :
+
+ (#) Configuration functions for Injected channels sample time
+ (#) Functions to start and stop the injected conversion
+ (#) unction to select the discontinuous mode
+ (#) Function to get the Specified Injected channel conversion data: This subsection
+ provides an important function in the ADC peripheral since it returns the
+ converted data of the specific injected channel.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures for the selected ADC injected channel its corresponding
+ * sample time.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_Channel: the ADC channel to configure.
+ * This parameter can be one of the following values:
+ * @arg ADC_InjectedChannel_1: ADC Channel1 selected
+ * @arg ADC_InjectedChannel_2: ADC Channel2 selected
+ * @arg ADC_InjectedChannel_3: ADC Channel3 selected
+ * @arg ADC_InjectedChannel_4: ADC Channel4 selected
+ * @arg ADC_InjectedChannel_5: ADC Channel5 selected
+ * @arg ADC_InjectedChannel_6: ADC Channel6 selected
+ * @arg ADC_InjectedChannel_7: ADC Channel7 selected
+ * @arg ADC_InjectedChannel_8: ADC Channel8 selected
+ * @arg ADC_InjectedChannel_9: ADC Channel9 selected
+ * @arg ADC_InjectedChannel_10: ADC Channel10 selected
+ * @arg ADC_InjectedChannel_11: ADC Channel11 selected
+ * @arg ADC_InjectedChannel_12: ADC Channel12 selected
+ * @arg ADC_InjectedChannel_13: ADC Channel13 selected
+ * @arg ADC_InjectedChannel_14: ADC Channel14 selected
+ * @arg ADC_InjectedChannel_15: ADC Channel15 selected
+ * @arg ADC_InjectedChannel_16: ADC Channel16 selected
+ * @arg ADC_InjectedChannel_17: ADC Channel17 selected
+ * @arg ADC_InjectedChannel_18: ADC Channel18 selected
+ * @param ADC_SampleTime: The sample time value to be set for the selected channel.
+ * This parameter can be one of the following values:
+ * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
+ * @arg ADC_SampleTime_2Cycles5: Sample time equal to 2.5 cycles
+ * @arg ADC_SampleTime_4Cycles5: Sample time equal to 4.5 cycles
+ * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
+ * @arg ADC_SampleTime_19Cycles5: Sample time equal to 19.5 cycles
+ * @arg ADC_SampleTime_61Cycles5: Sample time equal to 61.5 cycles
+ * @arg ADC_SampleTime_181Cycles5: Sample time equal to 181.5 cycles
+ * @arg ADC_SampleTime_601Cycles5: Sample time equal to 601.5 cycles
+ * @retval None
+ */
+void ADC_InjectedChannelSampleTimeConfig(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint8_t ADC_SampleTime)
+{
+ uint32_t tmpreg1 = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
+ assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
+
+ /* Channel sampling configuration */
+ /* if ADC_InjectedChannel_10 ... ADC_InjectedChannel_18 is selected */
+ if (ADC_InjectedChannel > ADC_InjectedChannel_9)
+ {
+ /* Calculate the mask to clear */
+ tmpreg1 = ADC_SMPR2_SMP10 << (3 * (ADC_InjectedChannel - 10));
+ /* Clear the old channel sample time */
+ ADCx->SMPR2 &= ~tmpreg1;
+ /* Calculate the mask to set */
+ ADCx->SMPR2 |= (uint32_t)ADC_SampleTime << (3 * (ADC_InjectedChannel - 10));
+
+ }
+ else /* ADC_InjectedChannel include in ADC_InjectedChannel_[0..9] */
+ {
+ /* Calculate the mask to clear */
+ tmpreg1 = ADC_SMPR1_SMP1 << (3 * (ADC_InjectedChannel - 1));
+ /* Clear the old channel sample time */
+ ADCx->SMPR1 &= ~tmpreg1;
+ /* Calculate the mask to set */
+ ADCx->SMPR1 |= (uint32_t)ADC_SampleTime << (3 * (ADC_InjectedChannel));
+ }
+}
+
+/**
+ * @brief Enables or disables the selected ADC start of the injected
+ * channels conversion.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC software start injected conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_StartInjectedConversion(ADC_TypeDef* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+ /* Enable the selected ADC conversion for injected group on external event and start the selected
+ ADC injected conversion */
+ ADCx->CR |= ADC_CR_JADSTART;
+}
+
+/**
+ * @brief Stops the selected ADC ongoing injected conversion.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @retval None
+ */
+void ADC_StopInjectedConversion(ADC_TypeDef* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+ /* Set the JADSTP bit */
+ ADCx->CR |= ADC_CR_JADSTP;
+}
+
+/**
+ * @brief Gets the selected ADC Software start injected conversion Status.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @retval The new state of ADC start injected conversion (SET or RESET).
+ */
+FlagStatus ADC_GetStartInjectedConversionStatus(ADC_TypeDef* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+ /* Check the status of JADSTART bit */
+ if ((ADCx->CR & ADC_CR_JADSTART) != (uint32_t)RESET)
+ {
+ /* JADSTART bit is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* JADSTART bit is reset */
+ bitstatus = RESET;
+ }
+ /* Return the JADSTART bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief Enables or disables the selected ADC automatic injected group
+ * conversion after regular one.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC auto injected conversion
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC automatic injected group conversion */
+ ADCx->CFGR |= ADC_CFGR_JAUTO;
+ }
+ else
+ {
+ /* Disable the selected ADC automatic injected group conversion */
+ ADCx->CFGR &= ~ADC_CFGR_JAUTO;
+ }
+}
+
+/**
+ * @brief Enables or disables the discontinuous mode for injected group
+ * channel for the specified ADC
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC discontinuous mode
+ * on injected group channel.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC injected discontinuous mode */
+ ADCx->CFGR |= ADC_CFGR_JDISCEN;
+ }
+ else
+ {
+ /* Disable the selected ADC injected discontinuous mode */
+ ADCx->CFGR &= ~ADC_CFGR_JDISCEN;
+ }
+}
+
+/**
+ * @brief Returns the ADC injected channel conversion result
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_InjectedSequence: the converted ADC injected sequence.
+ * This parameter can be one of the following values:
+ * @arg ADC_InjectedSequence_1: Injected Sequence1 selected
+ * @arg ADC_InjectedSequence_2: Injected Sequence2 selected
+ * @arg ADC_InjectedSequence_3: Injected Sequence3 selected
+ * @arg ADC_InjectedSequence_4: Injected Sequence4 selected
+ * @retval The Data conversion value.
+ */
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedSequence)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_INJECTED_SEQUENCE(ADC_InjectedSequence));
+
+ tmp = (uint32_t)ADCx;
+ tmp += ((ADC_InjectedSequence - 1 )<< 2) + JDR_Offset;
+
+ /* Returns the selected injected channel conversion data value */
+ return (uint16_t) (*(__IO uint32_t*) tmp);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Group7 Interrupts and flags management functions
+ * @brief Interrupts and flags management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupts and flags management functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure the ADC Interrupts, get
+ the status and clear flags and Interrupts pending bits.
+
+ [..] The ADC provide 11 Interrupts sources and 11 Flags which can be divided into 3 groups:
+
+ (#) Flags and Interrupts for ADC regular channels
+ (##)Flags
+ (+) ADC_FLAG_RDY: ADC Ready flag
+ (+) ADC_FLAG_EOSMP: ADC End of Sampling flag
+ (+) ADC_FLAG_EOC: ADC End of Regular Conversion flag.
+ (+) ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag
+ (+) ADC_FLAG_OVR: ADC overrun flag
+
+ (##) Interrupts
+ (+) ADC_IT_RDY: ADC Ready interrupt source
+ (+) ADC_IT_EOSMP: ADC End of Sampling interrupt source
+ (+) ADC_IT_EOC: ADC End of Regular Conversion interrupt source
+ (+) ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt
+ (+) ADC_IT_OVR: ADC overrun interrupt source
+
+
+ (#) Flags and Interrupts for ADC regular channels
+ (##)Flags
+ (+) ADC_FLAG_JEOC: ADC Ready flag
+ (+) ADC_FLAG_JEOS: ADC End of Sampling flag
+ (+) ADC_FLAG_JQOVF: ADC End of Regular Conversion flag.
+
+ (##) Interrupts
+ (+) ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
+ (+) ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source
+ (+) ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source
+
+ (#) General Flags and Interrupts for the ADC
+ (##)Flags
+ (+) ADC_FLAG_AWD1: ADC Analog watchdog 1 flag
+ (+) ADC_FLAG_AWD2: ADC Analog watchdog 2 flag
+ (+) ADC_FLAG_AWD3: ADC Analog watchdog 3 flag
+
+ (##)Flags
+ (+) ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source
+ (+) ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source
+ (+) ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source
+
+ (#) Flags for ADC dual mode
+ (##)Flags for Master
+ (+) ADC_FLAG_MSTRDY: ADC master Ready (ADRDY) flag
+ (+) ADC_FLAG_MSTEOSMP: ADC master End of Sampling flag
+ (+) ADC_FLAG_MSTEOC: ADC master End of Regular Conversion flag
+ (+) ADC_FLAG_MSTEOS: ADC master End of Regular sequence of Conversions flag
+ (+) ADC_FLAG_MSTOVR: ADC master overrun flag
+ (+) ADC_FLAG_MSTJEOC: ADC master End of Injected Conversion flag
+ (+) ADC_FLAG_MSTJEOS: ADC master End of Injected sequence of Conversions flag
+ (+) ADC_FLAG_MSTAWD1: ADC master Analog watchdog 1 flag
+ (+) ADC_FLAG_MSTAWD2: ADC master Analog watchdog 2 flag
+ (+) ADC_FLAG_MSTAWD3: ADC master Analog watchdog 3 flag
+ (+) ADC_FLAG_MSTJQOVF: ADC master Injected Context Queue Overflow flag
+
+ (##) Flags for Slave
+ (+) ADC_FLAG_SLVRDY: ADC slave Ready (ADRDY) flag
+ (+) ADC_FLAG_SLVEOSMP: ADC slave End of Sampling flag
+ (+) ADC_FLAG_SLVEOC: ADC slave End of Regular Conversion flag
+ (+) ADC_FLAG_SLVEOS: ADC slave End of Regular sequence of Conversions flag
+ (+) ADC_FLAG_SLVOVR: ADC slave overrun flag
+ (+) ADC_FLAG_SLVJEOC: ADC slave End of Injected Conversion flag
+ (+) ADC_FLAG_SLVJEOS: ADC slave End of Injected sequence of Conversions flag
+ (+) ADC_FLAG_SLVAWD1: ADC slave Analog watchdog 1 flag
+ (+) ADC_FLAG_SLVAWD2: ADC slave Analog watchdog 2 flag
+ (+) ADC_FLAG_SLVAWD3: ADC slave Analog watchdog 3 flag
+ (+) ADC_FLAG_SLVJQOVF: ADC slave Injected Context Queue Overflow flag
+
+ The user should identify which mode will be used in his application to manage
+ the ADC controller events: Polling mode or Interrupt mode.
+
+ In the Polling Mode it is advised to use the following functions:
+ - ADC_GetFlagStatus() : to check if flags events occur.
+ - ADC_ClearFlag() : to clear the flags events.
+
+ In the Interrupt Mode it is advised to use the following functions:
+ - ADC_ITConfig() : to enable or disable the interrupt source.
+ - ADC_GetITStatus() : to check if Interrupt occurs.
+ - ADC_ClearITPendingBit() : to clear the Interrupt pending Bit
+ (corresponding Flag).
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the specified ADC interrupts.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg ADC_IT_RDY: ADC Ready (ADRDY) interrupt source
+ * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
+ * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
+ * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
+ * @arg ADC_IT_OVR: ADC overrun interrupt source
+ * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
+ * @arg ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source
+ * @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source
+ * @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source
+ * @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source
+ * @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source
+ * @param NewState: new state of the specified ADC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_ADC_IT(ADC_IT));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC interrupts */
+ ADCx->IER |= ADC_IT;
+ }
+ else
+ {
+ /* Disable the selected ADC interrupts */
+ ADCx->IER &= (~(uint32_t)ADC_IT);
+ }
+}
+
+/**
+ * @brief Checks whether the specified ADC flag is set or not.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg ADC_FLAG_RDY: ADC Ready (ADRDY) flag
+ * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag
+ * @arg ADC_FLAG_EOC: ADC End of Regular Conversion flag
+ * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag
+ * @arg ADC_FLAG_OVR: ADC overrun flag
+ * @arg ADC_FLAG_JEOC: ADC End of Injected Conversion flag
+ * @arg ADC_FLAG_JEOS: ADC End of Injected sequence of Conversions flag
+ * @arg ADC_FLAG_AWD1: ADC Analog watchdog 1 flag
+ * @arg ADC_FLAG_AWD2: ADC Analog watchdog 2 flag
+ * @arg ADC_FLAG_AWD3: ADC Analog watchdog 3 flag
+ * @arg ADC_FLAG_JQOVF: ADC Injected Context Queue Overflow flag
+ * @retval The new state of ADC_FLAG (SET or RESET).
+ */
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
+
+ /* Check the status of the specified ADC flag */
+ if ((ADCx->ISR & ADC_FLAG) != (uint32_t)RESET)
+ {
+ /* ADC_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* ADC_FLAG is reset */
+ bitstatus = RESET;
+ }
+ /* Return the ADC_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the ADCx's pending flags.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_FLAG: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg ADC_FLAG_RDY: ADC Ready (ADRDY) flag
+ * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag
+ * @arg ADC_FLAG_EOC: ADC End of Regular Conversion flag
+ * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag
+ * @arg ADC_FLAG_OVR: ADC overrun flag
+ * @arg ADC_FLAG_JEOC: ADC End of Injected Conversion flag
+ * @arg ADC_FLAG_JEOS: ADC End of Injected sequence of Conversions flag
+ * @arg ADC_FLAG_AWD1: ADC Analog watchdog 1 flag
+ * @arg ADC_FLAG_AWD2: ADC Analog watchdog 2 flag
+ * @arg ADC_FLAG_AWD3: ADC Analog watchdog 3 flag
+ * @arg ADC_FLAG_JQOVF: ADC Injected Context Queue Overflow flag
+ * @retval None
+ */
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
+ /* Clear the selected ADC flags */
+ ADCx->ISR = (uint32_t)ADC_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified ADC flag is set or not.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_FLAG: specifies the master or slave flag to check.
+ * This parameter can be one of the following values:
+ * @arg ADC_FLAG_MSTRDY: ADC master Ready (ADRDY) flag
+ * @arg ADC_FLAG_MSTEOSMP: ADC master End of Sampling flag
+ * @arg ADC_FLAG_MSTEOC: ADC master End of Regular Conversion flag
+ * @arg ADC_FLAG_MSTEOS: ADC master End of Regular sequence of Conversions flag
+ * @arg ADC_FLAG_MSTOVR: ADC master overrun flag
+ * @arg ADC_FLAG_MSTJEOC: ADC master End of Injected Conversion flag
+ * @arg ADC_FLAG_MSTJEOS: ADC master End of Injected sequence of Conversions flag
+ * @arg ADC_FLAG_MSTAWD1: ADC master Analog watchdog 1 flag
+ * @arg ADC_FLAG_MSTAWD2: ADC master Analog watchdog 2 flag
+ * @arg ADC_FLAG_MSTAWD3: ADC master Analog watchdog 3 flag
+ * @arg ADC_FLAG_MSTJQOVF: ADC master Injected Context Queue Overflow flag
+ * @arg ADC_FLAG_SLVRDY: ADC slave Ready (ADRDY) flag
+ * @arg ADC_FLAG_SLVEOSMP: ADC slave End of Sampling flag
+ * @arg ADC_FLAG_SLVEOC: ADC slave End of Regular Conversion flag
+ * @arg ADC_FLAG_SLVEOS: ADC slave End of Regular sequence of Conversions flag
+ * @arg ADC_FLAG_SLVOVR: ADC slave overrun flag
+ * @arg ADC_FLAG_SLVJEOC: ADC slave End of Injected Conversion flag
+ * @arg ADC_FLAG_SLVJEOS: ADC slave End of Injected sequence of Conversions flag
+ * @arg ADC_FLAG_SLVAWD1: ADC slave Analog watchdog 1 flag
+ * @arg ADC_FLAG_SLVAWD2: ADC slave Analog watchdog 2 flag
+ * @arg ADC_FLAG_SLVAWD3: ADC slave Analog watchdog 3 flag
+ * @arg ADC_FLAG_SLVJQOVF: ADC slave Injected Context Queue Overflow flag
+ * @retval The new state of ADC_FLAG (SET or RESET).
+ */
+FlagStatus ADC_GetCommonFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG)
+{
+ uint32_t tmpreg1 = 0;
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_GET_COMMONFLAG(ADC_FLAG));
+
+ if((ADCx == ADC1) || (ADCx == ADC2))
+ {
+ tmpreg1 = ADC1_2->CSR;
+ }
+ else
+ {
+ tmpreg1 = ADC3_4->CSR;
+ }
+ /* Check the status of the specified ADC flag */
+ if ((tmpreg1 & ADC_FLAG) != (uint32_t)RESET)
+ {
+ /* ADC_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* ADC_FLAG is reset */
+ bitstatus = RESET;
+ }
+ /* Return the ADC_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the ADCx's pending flags.
+ * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_FLAG: specifies the master or slave flag to clear.
+ * This parameter can be one of the following values:
+ * @arg ADC_FLAG_MSTRDY: ADC master Ready (ADRDY) flag
+ * @arg ADC_FLAG_MSTEOSMP: ADC master End of Sampling flag
+ * @arg ADC_FLAG_MSTEOC: ADC master End of Regular Conversion flag
+ * @arg ADC_FLAG_MSTEOS: ADC master End of Regular sequence of Conversions flag
+ * @arg ADC_FLAG_MSTOVR: ADC master overrun flag
+ * @arg ADC_FLAG_MSTJEOC: ADC master End of Injected Conversion flag
+ * @arg ADC_FLAG_MSTJEOS: ADC master End of Injected sequence of Conversions flag
+ * @arg ADC_FLAG_MSTAWD1: ADC master Analog watchdog 1 flag
+ * @arg ADC_FLAG_MSTAWD2: ADC master Analog watchdog 2 flag
+ * @arg ADC_FLAG_MSTAWD3: ADC master Analog watchdog 3 flag
+ * @arg ADC_FLAG_MSTJQOVF: ADC master Injected Context Queue Overflow flag
+ * @arg ADC_FLAG_SLVRDY: ADC slave Ready (ADRDY) flag
+ * @arg ADC_FLAG_SLVEOSMP: ADC slave End of Sampling flag
+ * @arg ADC_FLAG_SLVEOC: ADC slave End of Regular Conversion flag
+ * @arg ADC_FLAG_SLVEOS: ADC slave End of Regular sequence of Conversions flag
+ * @arg ADC_FLAG_SLVOVR: ADC slave overrun flag
+ * @arg ADC_FLAG_SLVJEOC: ADC slave End of Injected Conversion flag
+ * @arg ADC_FLAG_SLVJEOS: ADC slave End of Injected sequence of Conversions flag
+ * @arg ADC_FLAG_SLVAWD1: ADC slave Analog watchdog 1 flag
+ * @arg ADC_FLAG_SLVAWD2: ADC slave Analog watchdog 2 flag
+ * @arg ADC_FLAG_SLVAWD3: ADC slave Analog watchdog 3 flag
+ * @arg ADC_FLAG_SLVJQOVF: ADC slave Injected Context Queue Overflow flag
+ * @retval None
+ */
+void ADC_ClearCommonFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_CLEAR_COMMONFLAG(ADC_FLAG));
+
+ if((ADCx == ADC1) || (ADCx == ADC2))
+ {
+ /* Clear the selected ADC flags */
+ ADC1_2->CSR |= (uint32_t)ADC_FLAG;
+ }
+ else
+ {
+ /* Clear the selected ADC flags */
+ ADC3_4->CSR |= (uint32_t)ADC_FLAG;
+ }
+}
+
+/**
+ * @brief Checks whether the specified ADC interrupt has occurred or not.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_IT: specifies the ADC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg ADC_IT_RDY: ADC Ready (ADRDY) interrupt source
+ * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
+ * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
+ * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
+ * @arg ADC_IT_OVR: ADC overrun interrupt source
+ * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
+ * @arg ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source
+ * @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source
+ * @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source
+ * @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source
+ * @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source
+ * @retval The new state of ADC_IT (SET or RESET).
+ */
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint16_t itstatus = 0x0, itenable = 0x0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_GET_IT(ADC_IT));
+
+ itstatus = ADCx->ISR & ADC_IT;
+
+ itenable = ADCx->IER & ADC_IT;
+ if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the ADCx's interrupt pending bits.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_IT: specifies the ADC interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg ADC_IT_RDY: ADC Ready (ADRDY) interrupt source
+ * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
+ * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
+ * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
+ * @arg ADC_IT_OVR: ADC overrun interrupt source
+ * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
+ * @arg ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source
+ * @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source
+ * @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source
+ * @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source
+ * @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source
+ * @retval None
+ */
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_IT(ADC_IT));
+ /* Clear the selected ADC interrupt pending bit */
+ ADCx->ISR = (uint32_t)ADC_IT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_adc.h Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,830 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_adc.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the ADC firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_ADC_H
+#define __STM32F30x_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief ADC Init structure definition
+ */
+typedef struct
+{
+
+ uint32_t ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
+ Continuous or Single mode.
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t ADC_Resolution; /*!< Configures the ADC resolution.
+ This parameter can be a value of @ref ADC_resolution */
+ uint32_t ADC_ExternalTrigConvEvent; /*!< Defines the external trigger used to start the analog
+ to digital conversion of regular channels. This parameter
+ can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
+ uint32_t ADC_ExternalTrigEventEdge; /*!< Select the external trigger edge and enable the trigger of a regular group.
+ This parameter can be a value of
+ @ref ADC_external_trigger_edge_for_regular_channels_conversion */
+ uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
+ This parameter can be a value of @ref ADC_data_align */
+ uint32_t ADC_OverrunMode; /*!< Specifies the way data overrun are managed.
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t ADC_AutoInjMode; /*!< Enable/disable automatic injected group conversion after
+ regular group conversion.
+ This parameter can be set to ENABLE or DISABLE. */
+ uint8_t ADC_NbrOfRegChannel; /*!< Specifies the number of ADC channels that will be converted
+ using the sequencer for regular channel group.
+ This parameter must range from 1 to 16. */
+}ADC_InitTypeDef;
+
+/**
+ * @}
+ */
+/**
+ * @brief ADC Init structure definition
+ */
+typedef struct
+{
+
+ uint32_t ADC_ExternalTrigInjecConvEvent; /*!< Defines the external trigger used to start the analog
+ to digital conversion of injected channels. This parameter
+ can be a value of @ref ADC_external_trigger_sources_for_Injected_channels_conversion */
+ uint32_t ADC_ExternalTrigInjecEventEdge; /*!< Select the external trigger edge and enable the trigger of an injected group.
+ This parameter can be a value of
+ @ref ADC_external_trigger_edge_for_Injected_channels_conversion */
+ uint8_t ADC_NbrOfInjecChannel; /*!< Specifies the number of ADC channels that will be converted
+ using the sequencer for injected channel group.
+ This parameter must range from 1 to 4. */
+ uint32_t ADC_InjecSequence1;
+ uint32_t ADC_InjecSequence2;
+ uint32_t ADC_InjecSequence3;
+ uint32_t ADC_InjecSequence4;
+}ADC_InjectedInitTypeDef;
+
+/**
+ * @}
+ */
+typedef struct
+{
+ uint32_t ADC_Mode; /*!< Configures the ADC to operate in
+ independent or multi mode.
+ This parameter can be a value of @ref ADC_mode */
+ uint32_t ADC_Clock; /*!< Select the clock of the ADC. The clock is common for both master
+ and slave ADCs.
+ This parameter can be a value of @ref ADC_Clock */
+ uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode.
+ This parameter can be a value of
+ @ref ADC_Direct_memory_access_mode_for_multi_mode */
+ uint32_t ADC_DMAMode; /*!< Configures the DMA mode for ADC.
+ This parameter can be a value of @ref ADC_DMA_Mode_definition */
+ uint8_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
+ This parameter can be a value between 0x0 and 0xF */
+
+}ADC_CommonInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants
+ * @{
+ */
+
+#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
+ ((PERIPH) == ADC2) || \
+ ((PERIPH) == ADC3) || \
+ ((PERIPH) == ADC4))
+
+#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
+ ((PERIPH) == ADC2) || \
+ ((PERIPH) == ADC3) || \
+ ((PERIPH) == ADC4))
+
+/** @defgroup ADC_ContinuousConvMode
+ * @{
+ */
+#define ADC_ContinuousConvMode_Enable ((uint32_t)0x00002000) /*!< ADC continuous conversion mode enable */
+#define ADC_ContinuousConvMode_Disable ((uint32_t)0x00000000) /*!< ADC continuous conversion mode disable */
+#define IS_ADC_CONVMODE(MODE) (((MODE) == ADC_ContinuousConvMode_Enable) || \
+ ((MODE) == ADC_ContinuousConvMode_Disable))
+/**
+ * @}
+ */
+/** @defgroup ADC_OverunMode
+ * @{
+ */
+#define ADC_OverrunMode_Enable ((uint32_t)0x00001000) /*!< ADC Overrun Mode enable */
+#define ADC_OverrunMode_Disable ((uint32_t)0x00000000) /*!< ADC Overrun Mode disable */
+#define IS_ADC_OVRUNMODE(MODE) (((MODE) == ADC_OverrunMode_Enable) || \
+ ((MODE) == ADC_OverrunMode_Disable))
+/**
+ * @}
+ */
+/** @defgroup ADC_AutoInjecMode
+ * @{
+ */
+#define ADC_AutoInjec_Enable ((uint32_t)0x02000000) /*!< ADC Auto injected Mode enable */
+#define ADC_AutoInjec_Disable ((uint32_t)0x00000000) /*!< ADC Auto injected Mode disable */
+#define IS_ADC_AUTOINJECMODE(MODE) (((MODE) == ADC_AutoInjec_Enable) || \
+ ((MODE) == ADC_AutoInjec_Disable))
+/**
+ * @}
+ */
+/** @defgroup ADC_resolution
+ * @{
+ */
+#define ADC_Resolution_12b ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */
+#define ADC_Resolution_10b ((uint32_t)0x00000008) /*!< ADC 10-bit resolution */
+#define ADC_Resolution_8b ((uint32_t)0x00000010) /*!< ADC 8-bit resolution */
+#define ADC_Resolution_6b ((uint32_t)0x00000018) /*!< ADC 6-bit resolution */
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
+ ((RESOLUTION) == ADC_Resolution_10b) || \
+ ((RESOLUTION) == ADC_Resolution_8b) || \
+ ((RESOLUTION) == ADC_Resolution_6b))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion
+ * @{
+ */
+#define ADC_ExternalTrigEventEdge_None ((uint16_t)0x0000) /*!< ADC No external trigger for regular conversion */
+#define ADC_ExternalTrigEventEdge_RisingEdge ((uint16_t)0x0400) /*!< ADC external trigger rising edge for regular conversion */
+#define ADC_ExternalTrigEventEdge_FallingEdge ((uint16_t)0x0800) /*!< ADC ADC external trigger falling edge for regular conversion */
+#define ADC_ExternalTrigEventEdge_BothEdge ((uint16_t)0x0C00) /*!< ADC ADC external trigger both edges for regular conversion */
+
+#define IS_EXTERNALTRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigEventEdge_None) || \
+ ((EDGE) == ADC_ExternalTrigEventEdge_RisingEdge) || \
+ ((EDGE) == ADC_ExternalTrigEventEdge_FallingEdge) || \
+ ((EDGE) == ADC_ExternalTrigEventEdge_BothEdge))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_external_trigger_edge_for_Injected_channels_conversion
+ * @{
+ */
+#define ADC_ExternalTrigInjecEventEdge_None ((uint16_t)0x0000) /*!< ADC No external trigger for regular conversion */
+#define ADC_ExternalTrigInjecEventEdge_RisingEdge ((uint16_t)0x0040) /*!< ADC external trigger rising edge for injected conversion */
+#define ADC_ExternalTrigInjecEventEdge_FallingEdge ((uint16_t)0x0080) /*!< ADC external trigger falling edge for injected conversion */
+#define ADC_ExternalTrigInjecEventEdge_BothEdge ((uint16_t)0x00C0) /*!< ADC external trigger both edges for injected conversion */
+
+#define IS_EXTERNALTRIGINJ_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecEventEdge_None) || \
+ ((EDGE) == ADC_ExternalTrigInjecEventEdge_RisingEdge) || \
+ ((EDGE) == ADC_ExternalTrigInjecEventEdge_FallingEdge) || \
+ ((EDGE) == ADC_ExternalTrigInjecEventEdge_BothEdge))
+
+/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion
+ * @{
+ */
+#define ADC_ExternalTrigConvEvent_0 ((uint16_t)0x0000) /*!< ADC external trigger event 0 */
+#define ADC_ExternalTrigConvEvent_1 ((uint16_t)0x0040) /*!< ADC external trigger event 1 */
+#define ADC_ExternalTrigConvEvent_2 ((uint16_t)0x0080) /*!< ADC external trigger event 2 */
+#define ADC_ExternalTrigConvEvent_3 ((uint16_t)0x00C0) /*!< ADC external trigger event 3 */
+#define ADC_ExternalTrigConvEvent_4 ((uint16_t)0x0100) /*!< ADC external trigger event 4 */
+#define ADC_ExternalTrigConvEvent_5 ((uint16_t)0x0140) /*!< ADC external trigger event 5 */
+#define ADC_ExternalTrigConvEvent_6 ((uint16_t)0x0180) /*!< ADC external trigger event 6 */
+#define ADC_ExternalTrigConvEvent_7 ((uint16_t)0x01C0) /*!< ADC external trigger event 7 */
+#define ADC_ExternalTrigConvEvent_8 ((uint16_t)0x0200) /*!< ADC external trigger event 8 */
+#define ADC_ExternalTrigConvEvent_9 ((uint16_t)0x0240) /*!< ADC external trigger event 9 */
+#define ADC_ExternalTrigConvEvent_10 ((uint16_t)0x0280) /*!< ADC external trigger event 10 */
+#define ADC_ExternalTrigConvEvent_11 ((uint16_t)0x02C0) /*!< ADC external trigger event 11 */
+#define ADC_ExternalTrigConvEvent_12 ((uint16_t)0x0300) /*!< ADC external trigger event 12 */
+#define ADC_ExternalTrigConvEvent_13 ((uint16_t)0x0340) /*!< ADC external trigger event 13 */
+#define ADC_ExternalTrigConvEvent_14 ((uint16_t)0x0380) /*!< ADC external trigger event 14 */
+#define ADC_ExternalTrigConvEvent_15 ((uint16_t)0x03C0) /*!< ADC external trigger event 15 */
+
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConvEvent_0) || \
+ ((REGTRIG) == ADC_ExternalTrigConvEvent_1) || \
+ ((REGTRIG) == ADC_ExternalTrigConvEvent_2) || \
+ ((REGTRIG) == ADC_ExternalTrigConvEvent_3) || \
+ ((REGTRIG) == ADC_ExternalTrigConvEvent_4) || \
+ ((REGTRIG) == ADC_ExternalTrigConvEvent_5) || \
+ ((REGTRIG) == ADC_ExternalTrigConvEvent_6) || \
+ ((REGTRIG) == ADC_ExternalTrigConvEvent_7) || \
+ ((REGTRIG) == ADC_ExternalTrigConvEvent_8) || \
+ ((REGTRIG) == ADC_ExternalTrigConvEvent_9) || \
+ ((REGTRIG) == ADC_ExternalTrigConvEvent_10) || \
+ ((REGTRIG) == ADC_ExternalTrigConvEvent_11) || \
+ ((REGTRIG) == ADC_ExternalTrigConvEvent_12) || \
+ ((REGTRIG) == ADC_ExternalTrigConvEvent_13) || \
+ ((REGTRIG) == ADC_ExternalTrigConvEvent_14) || \
+ ((REGTRIG) == ADC_ExternalTrigConvEvent_15))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_external_trigger_sources_for_Injected_channels_conversion
+ * @{
+ */
+
+#define ADC_ExternalTrigInjecConvEvent_0 ((uint16_t)0x0000) /*!< ADC external trigger for injected conversion event 0 */
+#define ADC_ExternalTrigInjecConvEvent_1 ((uint16_t)0x0004) /*!< ADC external trigger for injected conversion event 1 */
+#define ADC_ExternalTrigInjecConvEvent_2 ((uint16_t)0x0008) /*!< ADC external trigger for injected conversion event 2 */
+#define ADC_ExternalTrigInjecConvEvent_3 ((uint16_t)0x000C) /*!< ADC external trigger for injected conversion event 3 */
+#define ADC_ExternalTrigInjecConvEvent_4 ((uint16_t)0x0010) /*!< ADC external trigger for injected conversion event 4 */
+#define ADC_ExternalTrigInjecConvEvent_5 ((uint16_t)0x0014) /*!< ADC external trigger for injected conversion event 5 */
+#define ADC_ExternalTrigInjecConvEvent_6 ((uint16_t)0x0018) /*!< ADC external trigger for injected conversion event 6 */
+#define ADC_ExternalTrigInjecConvEvent_7 ((uint16_t)0x001C) /*!< ADC external trigger for injected conversion event 7 */
+#define ADC_ExternalTrigInjecConvEvent_8 ((uint16_t)0x0020) /*!< ADC external trigger for injected conversion event 8 */
+#define ADC_ExternalTrigInjecConvEvent_9 ((uint16_t)0x0024) /*!< ADC external trigger for injected conversion event 9 */
+#define ADC_ExternalTrigInjecConvEvent_10 ((uint16_t)0x0028) /*!< ADC external trigger for injected conversion event 10 */
+#define ADC_ExternalTrigInjecConvEvent_11 ((uint16_t)0x002C) /*!< ADC external trigger for injected conversion event 11 */
+#define ADC_ExternalTrigInjecConvEvent_12 ((uint16_t)0x0030) /*!< ADC external trigger for injected conversion event 12 */
+#define ADC_ExternalTrigInjecConvEvent_13 ((uint16_t)0x0034) /*!< ADC external trigger for injected conversion event 13 */
+#define ADC_ExternalTrigInjecConvEvent_14 ((uint16_t)0x0038) /*!< ADC external trigger for injected conversion event 14 */
+#define ADC_ExternalTrigInjecConvEvent_15 ((uint16_t)0x003C) /*!< ADC external trigger for injected conversion event 15 */
+
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConvEvent_0) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_1) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_2) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_3) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_4) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_5) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_6) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_7) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_8) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_9) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_10) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_11) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_12) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_13) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_14) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_15))
+/**
+ * @}
+ */
+/** @defgroup ADC_data_align
+ * @{
+ */
+
+#define ADC_DataAlign_Right ((uint32_t)0x00000000) /*!< ADC Data alignment right */
+#define ADC_DataAlign_Left ((uint32_t)0x00000020) /*!< ADC Data alignment left */
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
+ ((ALIGN) == ADC_DataAlign_Left))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_channels
+ * @{
+ */
+
+#define ADC_Channel_1 ((uint8_t)0x01) /*!< ADC Channel 1 */
+#define ADC_Channel_2 ((uint8_t)0x02) /*!< ADC Channel 2 */
+#define ADC_Channel_3 ((uint8_t)0x03) /*!< ADC Channel 3 */
+#define ADC_Channel_4 ((uint8_t)0x04) /*!< ADC Channel 4 */
+#define ADC_Channel_5 ((uint8_t)0x05) /*!< ADC Channel 5 */
+#define ADC_Channel_6 ((uint8_t)0x06) /*!< ADC Channel 6 */
+#define ADC_Channel_7 ((uint8_t)0x07) /*!< ADC Channel 7 */
+#define ADC_Channel_8 ((uint8_t)0x08) /*!< ADC Channel 8 */
+#define ADC_Channel_9 ((uint8_t)0x09) /*!< ADC Channel 9 */
+#define ADC_Channel_10 ((uint8_t)0x0A) /*!< ADC Channel 10 */
+#define ADC_Channel_11 ((uint8_t)0x0B) /*!< ADC Channel 11 */
+#define ADC_Channel_12 ((uint8_t)0x0C) /*!< ADC Channel 12 */
+#define ADC_Channel_13 ((uint8_t)0x0D) /*!< ADC Channel 13 */
+#define ADC_Channel_14 ((uint8_t)0x0E) /*!< ADC Channel 14 */
+#define ADC_Channel_15 ((uint8_t)0x0F) /*!< ADC Channel 15 */
+#define ADC_Channel_16 ((uint8_t)0x10) /*!< ADC Channel 16 */
+#define ADC_Channel_17 ((uint8_t)0x11) /*!< ADC Channel 17 */
+#define ADC_Channel_18 ((uint8_t)0x12) /*!< ADC Channel 18 */
+
+#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
+#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_18)
+#define ADC_Channel_Vbat ((uint8_t)ADC_Channel_17)
+
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_1) || \
+ ((CHANNEL) == ADC_Channel_2) || \
+ ((CHANNEL) == ADC_Channel_3) || \
+ ((CHANNEL) == ADC_Channel_4) || \
+ ((CHANNEL) == ADC_Channel_5) || \
+ ((CHANNEL) == ADC_Channel_6) || \
+ ((CHANNEL) == ADC_Channel_7) || \
+ ((CHANNEL) == ADC_Channel_8) || \
+ ((CHANNEL) == ADC_Channel_9) || \
+ ((CHANNEL) == ADC_Channel_10) || \
+ ((CHANNEL) == ADC_Channel_11) || \
+ ((CHANNEL) == ADC_Channel_12) || \
+ ((CHANNEL) == ADC_Channel_13) || \
+ ((CHANNEL) == ADC_Channel_14) || \
+ ((CHANNEL) == ADC_Channel_15) || \
+ ((CHANNEL) == ADC_Channel_16) || \
+ ((CHANNEL) == ADC_Channel_17) || \
+ ((CHANNEL) == ADC_Channel_18))
+#define IS_ADC_DIFFCHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_1) || \
+ ((CHANNEL) == ADC_Channel_2) || \
+ ((CHANNEL) == ADC_Channel_3) || \
+ ((CHANNEL) == ADC_Channel_4) || \
+ ((CHANNEL) == ADC_Channel_5) || \
+ ((CHANNEL) == ADC_Channel_6) || \
+ ((CHANNEL) == ADC_Channel_7) || \
+ ((CHANNEL) == ADC_Channel_8) || \
+ ((CHANNEL) == ADC_Channel_9) || \
+ ((CHANNEL) == ADC_Channel_10) || \
+ ((CHANNEL) == ADC_Channel_11) || \
+ ((CHANNEL) == ADC_Channel_12) || \
+ ((CHANNEL) == ADC_Channel_13) || \
+ ((CHANNEL) == ADC_Channel_14))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_mode
+ * @{
+ */
+#define ADC_Mode_Independent ((uint32_t)0x00000000) /*!< ADC independent mode */
+#define ADC_Mode_CombRegSimulInjSimul ((uint32_t)0x00000001) /*!< ADC multi ADC mode: Combined Regular simultaneous injected simultaneous mode */
+#define ADC_Mode_CombRegSimulAltTrig ((uint32_t)0x00000002) /*!< ADC multi ADC mode: Combined Regular simultaneous Alternate trigger mode */
+#define ADC_Mode_InjSimul ((uint32_t)0x00000005) /*!< ADC multi ADC mode: Injected simultaneous mode */
+#define ADC_Mode_RegSimul ((uint32_t)0x00000006) /*!< ADC multi ADC mode: Regular simultaneous mode */
+#define ADC_Mode_Interleave ((uint32_t)0x00000007) /*!< ADC multi ADC mode: Interleave mode */
+#define ADC_Mode_AltTrig ((uint32_t)0x00000009) /*!< ADC multi ADC mode: Alternate Trigger mode */
+
+#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
+ ((MODE) == ADC_Mode_CombRegSimulInjSimul) || \
+ ((MODE) == ADC_Mode_CombRegSimulAltTrig) || \
+ ((MODE) == ADC_Mode_InjSimul) || \
+ ((MODE) == ADC_Mode_RegSimul) || \
+ ((MODE) == ADC_Mode_Interleave) || \
+ ((MODE) == ADC_Mode_AltTrig))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Clock
+ * @{
+ */
+#define ADC_Clock_AsynClkMode ((uint32_t)0x00000000) /*!< ADC Asynchronous clock mode */
+#define ADC_Clock_SynClkModeDiv1 ((uint32_t)0x00010000) /*!< Synchronous clock mode divided by 1 */
+#define ADC_Clock_SynClkModeDiv2 ((uint32_t)0x00020000) /*!< Synchronous clock mode divided by 2 */
+#define ADC_Clock_SynClkModeDiv4 ((uint32_t)0x00030000) /*!< Synchronous clock mode divided by 4 */
+#define IS_ADC_CLOCKMODE(CLOCK) (((CLOCK) == ADC_Clock_AsynClkMode) ||\
+ ((CLOCK) == ADC_Clock_SynClkModeDiv1) ||\
+ ((CLOCK) == ADC_Clock_SynClkModeDiv2)||\
+ ((CLOCK) == ADC_Clock_SynClkModeDiv4))
+/**
+ * @}
+ */
+/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode
+ * @{
+ */
+#define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /*!< DMA mode disabled */
+#define ADC_DMAAccessMode_1 ((uint32_t)0x00008000) /*!< DMA mode enabled for 12 and 10-bit resolution (6 bit) */
+#define ADC_DMAAccessMode_2 ((uint32_t)0x0000C000) /*!< DMA mode enabled for 8 and 6-bit resolution (8bit) */
+#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \
+ ((MODE) == ADC_DMAAccessMode_1) || \
+ ((MODE) == ADC_DMAAccessMode_2))
+
+/**
+ * @}
+ */
+/** @defgroup ADC_sampling_time
+ * @{
+ */
+
+#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) /*!< ADC sampling time 1.5 cycle */
+#define ADC_SampleTime_2Cycles5 ((uint8_t)0x01) /*!< ADC sampling time 2.5 cycles */
+#define ADC_SampleTime_4Cycles5 ((uint8_t)0x02) /*!< ADC sampling time 4.5 cycles */
+#define ADC_SampleTime_7Cycles5 ((uint8_t)0x03) /*!< ADC sampling time 7.5 cycles */
+#define ADC_SampleTime_19Cycles5 ((uint8_t)0x04) /*!< ADC sampling time 19.5 cycles */
+#define ADC_SampleTime_61Cycles5 ((uint8_t)0x05) /*!< ADC sampling time 61.5 cycles */
+#define ADC_SampleTime_181Cycles5 ((uint8_t)0x06) /*!< ADC sampling time 181.5 cycles */
+#define ADC_SampleTime_601Cycles5 ((uint8_t)0x07) /*!< ADC sampling time 601.5 cycles */
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
+ ((TIME) == ADC_SampleTime_2Cycles5) || \
+ ((TIME) == ADC_SampleTime_4Cycles5) || \
+ ((TIME) == ADC_SampleTime_7Cycles5) || \
+ ((TIME) == ADC_SampleTime_19Cycles5) || \
+ ((TIME) == ADC_SampleTime_61Cycles5) || \
+ ((TIME) == ADC_SampleTime_181Cycles5) || \
+ ((TIME) == ADC_SampleTime_601Cycles5))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_injected_Channel_selection
+ * @{
+ */
+
+#define ADC_InjectedChannel_1 ADC_Channel_1 /*!< ADC Injected channel 1 */
+#define ADC_InjectedChannel_2 ADC_Channel_2 /*!< ADC Injected channel 2 */
+#define ADC_InjectedChannel_3 ADC_Channel_3 /*!< ADC Injected channel 3 */
+#define ADC_InjectedChannel_4 ADC_Channel_4 /*!< ADC Injected channel 4 */
+#define ADC_InjectedChannel_5 ADC_Channel_5 /*!< ADC Injected channel 5 */
+#define ADC_InjectedChannel_6 ADC_Channel_6 /*!< ADC Injected channel 6 */
+#define ADC_InjectedChannel_7 ADC_Channel_7 /*!< ADC Injected channel 7 */
+#define ADC_InjectedChannel_8 ADC_Channel_8 /*!< ADC Injected channel 8 */
+#define ADC_InjectedChannel_9 ADC_Channel_9 /*!< ADC Injected channel 9 */
+#define ADC_InjectedChannel_10 ADC_Channel_10 /*!< ADC Injected channel 10 */
+#define ADC_InjectedChannel_11 ADC_Channel_11 /*!< ADC Injected channel 11 */
+#define ADC_InjectedChannel_12 ADC_Channel_12 /*!< ADC Injected channel 12 */
+#define ADC_InjectedChannel_13 ADC_Channel_13 /*!< ADC Injected channel 13 */
+#define ADC_InjectedChannel_14 ADC_Channel_14 /*!< ADC Injected channel 14 */
+#define ADC_InjectedChannel_15 ADC_Channel_15 /*!< ADC Injected channel 15 */
+#define ADC_InjectedChannel_16 ADC_Channel_16 /*!< ADC Injected channel 16 */
+#define ADC_InjectedChannel_17 ADC_Channel_17 /*!< ADC Injected channel 17 */
+#define ADC_InjectedChannel_18 ADC_Channel_18 /*!< ADC Injected channel 18 */
+
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
+ ((CHANNEL) == ADC_InjectedChannel_2) || \
+ ((CHANNEL) == ADC_InjectedChannel_3) || \
+ ((CHANNEL) == ADC_InjectedChannel_4) ||\
+ ((CHANNEL) == ADC_InjectedChannel_5) ||\
+ ((CHANNEL) == ADC_InjectedChannel_6) ||\
+ ((CHANNEL) == ADC_InjectedChannel_7) ||\
+ ((CHANNEL) == ADC_InjectedChannel_8) ||\
+ ((CHANNEL) == ADC_InjectedChannel_9) ||\
+ ((CHANNEL) == ADC_InjectedChannel_10) ||\
+ ((CHANNEL) == ADC_InjectedChannel_11) ||\
+ ((CHANNEL) == ADC_InjectedChannel_12) ||\
+ ((CHANNEL) == ADC_InjectedChannel_13) ||\
+ ((CHANNEL) == ADC_InjectedChannel_14) ||\
+ ((CHANNEL) == ADC_InjectedChannel_15) ||\
+ ((CHANNEL) == ADC_InjectedChannel_16) ||\
+ ((CHANNEL) == ADC_InjectedChannel_17) ||\
+ ((CHANNEL) == ADC_InjectedChannel_18))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_injected_Sequence_selection
+ * @{
+ */
+
+#define ADC_InjectedSequence_1 ADC_Channel_1 /*!< ADC Injected sequence 1 */
+#define ADC_InjectedSequence_2 ADC_Channel_2 /*!< ADC Injected sequence 2 */
+#define ADC_InjectedSequence_3 ADC_Channel_3 /*!< ADC Injected sequence 3 */
+#define ADC_InjectedSequence_4 ADC_Channel_4 /*!< ADC Injected sequence 4 */
+#define IS_ADC_INJECTED_SEQUENCE(SEQUENCE) (((SEQUENCE) == ADC_InjectedSequence_1) || \
+ ((SEQUENCE) == ADC_InjectedSequence_2) || \
+ ((SEQUENCE) == ADC_InjectedSequence_3) || \
+ ((SEQUENCE) == ADC_InjectedSequence_4))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_analog_watchdog_selection
+ * @{
+ */
+
+#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00C00000) /*!< ADC Analog watchdog single regular mode */
+#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x01400000) /*!< ADC Analog watchdog single injected mode */
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x01C00000) /*!< ADC Analog watchdog single regular or injected mode */
+#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) /*!< ADC Analog watchdog all regular mode */
+#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x01000000) /*!< ADC Analog watchdog all injected mode */
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x01800000) /*!< ADC Analog watchdog all regular and all injected mode */
+#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) /*!< ADC Analog watchdog off */
+
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_None))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Calibration_Mode_definition
+ * @{
+ */
+#define ADC_CalibrationMode_Single ((uint32_t)0x00000000) /*!< ADC Calibration for single ended channel */
+#define ADC_CalibrationMode_Differential ((uint32_t)0x40000000) /*!< ADC Calibration for differential channel */
+
+#define IS_ADC_CALIBRATION_MODE(MODE) (((MODE) == ADC_CalibrationMode_Single) ||((MODE) == ADC_CalibrationMode_Differential))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_DMA_Mode_definition
+ * @{
+ */
+#define ADC_DMAMode_OneShot ((uint32_t)0x00000000) /*!< ADC DMA Oneshot mode */
+#define ADC_DMAMode_Circular ((uint32_t)0x00000002) /*!< ADC DMA circular mode */
+
+#define IS_ADC_DMA_MODE(MODE) (((MODE) == ADC_DMAMode_OneShot) || ((MODE) == ADC_DMAMode_Circular))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_interrupts_definition
+ * @{
+ */
+
+#define ADC_IT_RDY ((uint16_t)0x0001) /*!< ADC Ready (ADRDY) interrupt source */
+#define ADC_IT_EOSMP ((uint16_t)0x0002) /*!< ADC End of Sampling interrupt source */
+#define ADC_IT_EOC ((uint16_t)0x0004) /*!< ADC End of Regular Conversion interrupt source */
+#define ADC_IT_EOS ((uint16_t)0x0008) /*!< ADC End of Regular sequence of Conversions interrupt source */
+#define ADC_IT_OVR ((uint16_t)0x0010) /*!< ADC overrun interrupt source */
+#define ADC_IT_JEOC ((uint16_t)0x0020) /*!< ADC End of Injected Conversion interrupt source */
+#define ADC_IT_JEOS ((uint16_t)0x0040) /*!< ADC End of Injected sequence of Conversions interrupt source */
+#define ADC_IT_AWD1 ((uint16_t)0x0080) /*!< ADC Analog watchdog 1 interrupt source */
+#define ADC_IT_AWD2 ((uint16_t)0x0100) /*!< ADC Analog watchdog 2 interrupt source */
+#define ADC_IT_AWD3 ((uint16_t)0x0200) /*!< ADC Analog watchdog 3 interrupt source */
+#define ADC_IT_JQOVF ((uint16_t)0x0400) /*!< ADC Injected Context Queue Overflow interrupt source */
+
+
+#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF800) == 0x0000) && ((IT) != 0x0000))
+
+#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_RDY) || ((IT) == ADC_IT_EOSMP) || \
+ ((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_EOS) || \
+ ((IT) == ADC_IT_OVR) || ((IT) == ADC_IT_EOS) || \
+ ((IT) == ADC_IT_JEOS) || ((IT) == ADC_IT_AWD1) || \
+ ((IT) == ADC_IT_AWD2) || ((IT) == ADC_IT_AWD3) || \
+ ((IT) == ADC_IT_JQOVF))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_flags_definition
+ * @{
+ */
+
+#define ADC_FLAG_RDY ((uint16_t)0x0001) /*!< ADC Ready (ADRDY) flag */
+#define ADC_FLAG_EOSMP ((uint16_t)0x0002) /*!< ADC End of Sampling flag */
+#define ADC_FLAG_EOC ((uint16_t)0x0004) /*!< ADC End of Regular Conversion flag */
+#define ADC_FLAG_EOS ((uint16_t)0x0008) /*!< ADC End of Regular sequence of Conversions flag */
+#define ADC_FLAG_OVR ((uint16_t)0x0010) /*!< ADC overrun flag */
+#define ADC_FLAG_JEOC ((uint16_t)0x0020) /*!< ADC End of Injected Conversion flag */
+#define ADC_FLAG_JEOS ((uint16_t)0x0040) /*!< ADC End of Injected sequence of Conversions flag */
+#define ADC_FLAG_AWD1 ((uint16_t)0x0080) /*!< ADC Analog watchdog 1 flag */
+#define ADC_FLAG_AWD2 ((uint16_t)0x0100) /*!< ADC Analog watchdog 2 flag */
+#define ADC_FLAG_AWD3 ((uint16_t)0x0200) /*!< ADC Analog watchdog 3 flag */
+#define ADC_FLAG_JQOVF ((uint16_t)0x0400) /*!< ADC Injected Context Queue Overflow flag */
+
+#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xF800) == 0x0000) && ((FLAG) != 0x0000))
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_RDY) || ((FLAG) == ADC_FLAG_EOSMP) || \
+ ((FLAG) == ADC_FLAG_EOC) || ((FLAG) == ADC_FLAG_EOS) || \
+ ((FLAG) == ADC_FLAG_OVR) || ((FLAG) == ADC_FLAG_JEOC) || \
+ ((FLAG) == ADC_FLAG_JEOS) || ((FLAG) == ADC_FLAG_AWD1) || \
+ ((FLAG) == ADC_FLAG_AWD2) || ((FLAG) == ADC_FLAG_AWD3) || \
+ ((FLAG) == ADC_FLAG_JQOVF))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Common_flags_definition
+ * @{
+ */
+
+#define ADC_FLAG_MSTRDY ((uint32_t)0x00000001) /*!< ADC Master Ready (ADRDY) flag */
+#define ADC_FLAG_MSTEOSMP ((uint32_t)0x00000002) /*!< ADC Master End of Sampling flag */
+#define ADC_FLAG_MSTEOC ((uint32_t)0x00000004) /*!< ADC Master End of Regular Conversion flag */
+#define ADC_FLAG_MSTEOS ((uint32_t)0x00000008) /*!< ADC Master End of Regular sequence of Conversions flag */
+#define ADC_FLAG_MSTOVR ((uint32_t)0x00000010) /*!< ADC Master overrun flag */
+#define ADC_FLAG_MSTJEOC ((uint32_t)0x00000020) /*!< ADC Master End of Injected Conversion flag */
+#define ADC_FLAG_MSTJEOS ((uint32_t)0x00000040) /*!< ADC Master End of Injected sequence of Conversions flag */
+#define ADC_FLAG_MSTAWD1 ((uint32_t)0x00000080) /*!< ADC Master Analog watchdog 1 flag */
+#define ADC_FLAG_MSTAWD2 ((uint32_t)0x00000100) /*!< ADC Master Analog watchdog 2 flag */
+#define ADC_FLAG_MSTAWD3 ((uint32_t)0x00000200) /*!< ADC Master Analog watchdog 3 flag */
+#define ADC_FLAG_MSTJQOVF ((uint32_t)0x00000400) /*!< ADC Master Injected Context Queue Overflow flag */
+
+#define ADC_FLAG_SLVRDY ((uint32_t)0x00010000) /*!< ADC Slave Ready (ADRDY) flag */
+#define ADC_FLAG_SLVEOSMP ((uint32_t)0x00020000) /*!< ADC Slave End of Sampling flag */
+#define ADC_FLAG_SLVEOC ((uint32_t)0x00040000) /*!< ADC Slave End of Regular Conversion flag */
+#define ADC_FLAG_SLVEOS ((uint32_t)0x00080000) /*!< ADC Slave End of Regular sequence of Conversions flag */
+#define ADC_FLAG_SLVOVR ((uint32_t)0x00100000) /*!< ADC Slave overrun flag */
+#define ADC_FLAG_SLVJEOC ((uint32_t)0x00200000) /*!< ADC Slave End of Injected Conversion flag */
+#define ADC_FLAG_SLVJEOS ((uint32_t)0x00400000) /*!< ADC Slave End of Injected sequence of Conversions flag */
+#define ADC_FLAG_SLVAWD1 ((uint32_t)0x00800000) /*!< ADC Slave Analog watchdog 1 flag */
+#define ADC_FLAG_SLVAWD2 ((uint32_t)0x01000000) /*!< ADC Slave Analog watchdog 2 flag */
+#define ADC_FLAG_SLVAWD3 ((uint32_t)0x02000000) /*!< ADC Slave Analog watchdog 3 flag */
+#define ADC_FLAG_SLVJQOVF ((uint32_t)0x04000000) /*!< ADC Slave Injected Context Queue Overflow flag */
+
+#define IS_ADC_CLEAR_COMMONFLAG(FLAG) ((((FLAG) & (uint32_t)0xF800F800) == 0x0000) && ((FLAG) != 0x00000000))
+#define IS_ADC_GET_COMMONFLAG(FLAG) (((FLAG) == ADC_FLAG_MSTRDY) || ((FLAG) == ADC_FLAG_MSTEOSMP) || \
+ ((FLAG) == ADC_FLAG_MSTEOC) || ((FLAG) == ADC_FLAG_MSTEOS) || \
+ ((FLAG) == ADC_FLAG_MSTOVR) || ((FLAG) == ADC_FLAG_MSTEOS) || \
+ ((FLAG) == ADC_FLAG_MSTJEOS) || ((FLAG) == ADC_FLAG_MSTAWD1) || \
+ ((FLAG) == ADC_FLAG_MSTAWD2) || ((FLAG) == ADC_FLAG_MSTAWD3) || \
+ ((FLAG) == ADC_FLAG_MSTJQOVF) || \
+ ((FLAG) == ADC_FLAG_SLVRDY) || ((FLAG) == ADC_FLAG_SLVEOSMP) || \
+ ((FLAG) == ADC_FLAG_SLVEOC) || ((FLAG) == ADC_FLAG_SLVEOS) || \
+ ((FLAG) == ADC_FLAG_SLVOVR) || ((FLAG) == ADC_FLAG_SLVEOS) || \
+ ((FLAG) == ADC_FLAG_SLVJEOS) || ((FLAG) == ADC_FLAG_SLVAWD1) || \
+ ((FLAG) == ADC_FLAG_SLVAWD2) || ((FLAG) == ADC_FLAG_SLVAWD3) || \
+ ((FLAG) == ADC_FLAG_SLVJQOVF))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_thresholds
+ * @{
+ */
+
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_injected_offset
+ * @{
+ */
+
+#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_injected_length
+ * @{
+ */
+
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_regular_length
+ * @{
+ */
+
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_discontinuous_mode_number
+ * @{
+ */
+
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_two_sampling_delay_number
+ * @{
+ */
+#define IS_ADC_TWOSAMPLING_DELAY(DELAY) (((DELAY) <= 0xF))
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the ADC configuration to the default reset state *****/
+void ADC_DeInit(ADC_TypeDef* ADCx);
+
+/* Initialization and Configuration functions *********************************/
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
+void ADC_InjectedInit(ADC_TypeDef* ADCx, ADC_InjectedInitTypeDef* ADC_InjectedInitStruct);
+void ADC_InjectedStructInit(ADC_InjectedInitTypeDef* ADC_InjectedInitStruct);
+void ADC_CommonInit(ADC_TypeDef* ADCx, ADC_CommonInitTypeDef* ADC_CommonInitStruct);
+void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
+
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_StartCalibration(ADC_TypeDef* ADCx);
+uint32_t ADC_GetCalibrationValue(ADC_TypeDef* ADCx);
+void ADC_SetCalibrationValue(ADC_TypeDef* ADCx, uint32_t ADC_Calibration);
+void ADC_SelectCalibrationMode(ADC_TypeDef* ADCx, uint32_t ADC_CalibrationMode);
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_DisableCmd(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetDisableCmdStatus(ADC_TypeDef* ADCx);
+void ADC_VoltageRegulatorCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_SelectDifferentialMode(ADC_TypeDef* ADCx, uint8_t ADC_Channel, FunctionalState NewState);
+void ADC_SelectQueueOfContextMode(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_AutoDelayCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+
+/* Analog Watchdog configuration functions ************************************/
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
+void ADC_AnalogWatchdog1ThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
+void ADC_AnalogWatchdog2ThresholdsConfig(ADC_TypeDef* ADCx, uint8_t HighThreshold, uint8_t LowThreshold);
+void ADC_AnalogWatchdog3ThresholdsConfig(ADC_TypeDef* ADCx, uint8_t HighThreshold, uint8_t LowThreshold);
+void ADC_AnalogWatchdog1SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
+void ADC_AnalogWatchdog2SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
+void ADC_AnalogWatchdog3SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
+
+/* Temperature Sensor, Vrefint and Vbat management function */
+void ADC_TempSensorCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_VrefintCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_VbatCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+
+/* Channels Configuration functions ***********************************/
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_RegularChannelSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t SequencerLength);
+void ADC_ExternalTriggerConfig(ADC_TypeDef* ADCx, uint16_t ADC_ExternalTrigConvEvent, uint16_t ADC_ExternalTrigEventEdge);
+
+void ADC_StartConversion(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetStartConversionStatus(ADC_TypeDef* ADCx);
+void ADC_StopConversion(ADC_TypeDef* ADCx);
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
+uint32_t ADC_GetDualModeConversionValue(ADC_TypeDef* ADCx);
+
+void ADC_SetChannelOffset1(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset);
+void ADC_SetChannelOffset2(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset);
+void ADC_SetChannelOffset3(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset);
+void ADC_SetChannelOffset4(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset);
+
+void ADC_ChannelOffset1Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ChannelOffset2Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ChannelOffset3Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ChannelOffset4Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+
+/* Regular Channels DMA Configuration functions *******************************/
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DMAConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMAMode);
+
+/* Injected channels Configuration functions **********************************/
+void ADC_InjectedChannelSampleTimeConfig(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint8_t ADC_SampleTime);
+void ADC_StartInjectedConversion(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetStartInjectedConversionStatus(ADC_TypeDef* ADCx);
+void ADC_StopInjectedConversion(ADC_TypeDef* ADCx);
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
+
+/* ADC Dual Modes Configuration functions *************************************/
+FlagStatus ADC_GetCommonFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
+void ADC_ClearCommonFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
+
+/* Interrupts and flags management functions **********************************/
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState);
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT);
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F30x_ADC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_can.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,1639 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_can.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Controller area network (CAN) peripheral:
+ * + Initialization and Configuration
+ * + CAN Frames Transmission
+ * + CAN Frames Reception
+ * + Operation modes switch
+ * + Error management
+ * + Interrupts and flags
+ *
+ @verbatim
+
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ (#) Enable the CAN controller interface clock using
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE);
+ (#) CAN pins configuration:
+ (++) Enable the clock for the CAN GPIOs using the following function:
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOx, ENABLE);
+ (++) Connect the involved CAN pins to AF9 using the following function
+ GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_CANx);
+ (++) Configure these CAN pins in alternate function mode by calling
+ the function GPIO_Init();
+ (#) Initialise and configure the CAN using CAN_Init() and
+ CAN_FilterInit() functions.
+ (#) Transmit the desired CAN frame using CAN_Transmit() function.
+ (#) Check the transmission of a CAN frame using CAN_TransmitStatus() function.
+ (#) Cancel the transmission of a CAN frame using CAN_CancelTransmit() function.
+ (#) Receive a CAN frame using CAN_Recieve() function.
+ (#) Release the receive FIFOs using CAN_FIFORelease() function.
+ (#) Return the number of pending received frames using CAN_MessagePending() function.
+ (#) To control CAN events you can use one of the following two methods:
+ (++) Check on CAN flags using the CAN_GetFlagStatus() function.
+ (++) Use CAN interrupts through the function CAN_ITConfig() at initialization
+ phase and CAN_GetITStatus() function into interrupt routines to check
+ if the event has occurred or not.
+ After checking on a flag you should clear it using CAN_ClearFlag()
+ function. And after checking on an interrupt event you should clear it
+ using CAN_ClearITPendingBit() function.
+
+ @endverbatim
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_can.h"
+#include "stm32f30x_rcc.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup CAN
+ * @brief CAN driver modules
+ * @{
+ */
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* CAN Master Control Register bits */
+#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */
+
+/* CAN Mailbox Transmit Request */
+#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */
+
+/* CAN Filter Master Register bits */
+#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */
+
+/* Time out for INAK bit */
+#define INAK_TIMEOUT ((uint32_t)0x00FFFFFF)
+/* Time out for SLAK bit */
+#define SLAK_TIMEOUT ((uint32_t)0x00FFFFFF)
+
+/* Flags in TSR register */
+#define CAN_FLAGS_TSR ((uint32_t)0x08000000)
+/* Flags in RF1R register */
+#define CAN_FLAGS_RF1R ((uint32_t)0x04000000)
+/* Flags in RF0R register */
+#define CAN_FLAGS_RF0R ((uint32_t)0x02000000)
+/* Flags in MSR register */
+#define CAN_FLAGS_MSR ((uint32_t)0x01000000)
+/* Flags in ESR register */
+#define CAN_FLAGS_ESR ((uint32_t)0x00F00000)
+
+/* Mailboxes definition */
+#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
+#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
+#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
+
+#define CAN_MODE_MASK ((uint32_t) 0x00000003)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);
+
+/** @defgroup CAN_Private_Functions
+ * @{
+ */
+
+/** @defgroup CAN_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the CAN peripherals : Prescaler, operating mode, the maximum
+ number of time quanta to perform resynchronization, the number of time
+ quanta in Bit Segment 1 and 2 and many other modes.
+ (+) Configure the CAN reception filter.
+ (+) Select the start bank filter for slave CAN.
+ (+) Enable or disable the Debug Freeze mode for CAN.
+ (+) Enable or disable the CAN Time Trigger Operation communication mode.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the CAN peripheral registers to their default reset values.
+ * @param CANx: where x can be 1 to select the CAN1 peripheral.
+ * @retval None.
+ */
+void CAN_DeInit(CAN_TypeDef* CANx)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Enable CAN1 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE);
+ /* Release CAN1 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE);
+}
+
+/**
+ * @brief Initializes the CAN peripheral according to the specified
+ * parameters in the CAN_InitStruct.
+ * @param CANx: where x can be 1 to select the CAN1 peripheral.
+ * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that contains
+ * the configuration information for the CAN peripheral.
+ * @retval Constant indicates initialization succeed which will be
+ * CAN_InitStatus_Failed or CAN_InitStatus_Success.
+ */
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)
+{
+ uint8_t InitStatus = CAN_InitStatus_Failed;
+ __IO uint32_t wait_ack = 0x00000000;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));
+ assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));
+ assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));
+ assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));
+ assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));
+ assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));
+
+ /* Exit from sleep mode */
+ CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
+
+ /* Request initialisation */
+ CANx->MCR |= CAN_MCR_INRQ ;
+
+ /* Wait the acknowledge */
+ while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
+ {
+ wait_ack++;
+ }
+
+ /* Check acknowledge */
+ if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
+ {
+ InitStatus = CAN_InitStatus_Failed;
+ }
+ else
+ {
+ /* Set the time triggered communication mode */
+ if (CAN_InitStruct->CAN_TTCM == ENABLE)
+ {
+ CANx->MCR |= CAN_MCR_TTCM;
+ }
+ else
+ {
+ CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM;
+ }
+
+ /* Set the automatic bus-off management */
+ if (CAN_InitStruct->CAN_ABOM == ENABLE)
+ {
+ CANx->MCR |= CAN_MCR_ABOM;
+ }
+ else
+ {
+ CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM;
+ }
+
+ /* Set the automatic wake-up mode */
+ if (CAN_InitStruct->CAN_AWUM == ENABLE)
+ {
+ CANx->MCR |= CAN_MCR_AWUM;
+ }
+ else
+ {
+ CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM;
+ }
+
+ /* Set the no automatic retransmission */
+ if (CAN_InitStruct->CAN_NART == ENABLE)
+ {
+ CANx->MCR |= CAN_MCR_NART;
+ }
+ else
+ {
+ CANx->MCR &= ~(uint32_t)CAN_MCR_NART;
+ }
+
+ /* Set the receive FIFO locked mode */
+ if (CAN_InitStruct->CAN_RFLM == ENABLE)
+ {
+ CANx->MCR |= CAN_MCR_RFLM;
+ }
+ else
+ {
+ CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM;
+ }
+
+ /* Set the transmit FIFO priority */
+ if (CAN_InitStruct->CAN_TXFP == ENABLE)
+ {
+ CANx->MCR |= CAN_MCR_TXFP;
+ }
+ else
+ {
+ CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP;
+ }
+
+ /* Set the bit timing register */
+ CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \
+ ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \
+ ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \
+ ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \
+ ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);
+
+ /* Request leave initialisation */
+ CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ;
+
+ /* Wait the acknowledge */
+ wait_ack = 0;
+
+ while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
+ {
+ wait_ack++;
+ }
+
+ /* ...and check acknowledged */
+ if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
+ {
+ InitStatus = CAN_InitStatus_Failed;
+ }
+ else
+ {
+ InitStatus = CAN_InitStatus_Success ;
+ }
+ }
+
+ /* At this step, return the status of initialization */
+ return InitStatus;
+}
+
+/**
+ * @brief Configures the CAN reception filter according to the specified
+ * parameters in the CAN_FilterInitStruct.
+ * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef structure that
+ * contains the configuration information.
+ * @retval None
+ */
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
+{
+ uint32_t filter_number_bit_pos = 0;
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));
+ assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));
+ assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));
+ assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));
+
+ filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber;
+
+ /* Initialisation mode for the filter */
+ CAN1->FMR |= FMR_FINIT;
+
+ /* Filter Deactivation */
+ CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos;
+
+ /* Filter Scale */
+ if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
+ {
+ /* 16-bit scale for the filter */
+ CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos;
+
+ /* First 16-bit identifier and First 16-bit mask */
+ /* Or First 16-bit identifier and Second 16-bit identifier */
+ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
+
+ /* Second 16-bit identifier and Second 16-bit mask */
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);
+ }
+
+ if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
+ {
+ /* 32-bit scale for the filter */
+ CAN1->FS1R |= filter_number_bit_pos;
+ /* 32-bit identifier or First 32-bit identifier */
+ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
+ /* 32-bit mask or Second 32-bit identifier */
+ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);
+ }
+
+ /* Filter Mode */
+ if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
+ {
+ /*Id/Mask mode for the filter*/
+ CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos;
+ }
+ else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
+ {
+ /*Identifier list mode for the filter*/
+ CAN1->FM1R |= (uint32_t)filter_number_bit_pos;
+ }
+
+ /* Filter FIFO assignment */
+ if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0)
+ {
+ /* FIFO 0 assignation for the filter */
+ CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos;
+ }
+
+ if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1)
+ {
+ /* FIFO 1 assignation for the filter */
+ CAN1->FFA1R |= (uint32_t)filter_number_bit_pos;
+ }
+
+ /* Filter activation */
+ if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
+ {
+ CAN1->FA1R |= filter_number_bit_pos;
+ }
+
+ /* Leave the initialisation mode for the filter */
+ CAN1->FMR &= ~FMR_FINIT;
+}
+
+/**
+ * @brief Fills each CAN_InitStruct member with its default value.
+ * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which ill be initialized.
+ * @retval None
+ */
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
+{
+ /* Reset CAN init structure parameters values */
+
+ /* Initialize the time triggered communication mode */
+ CAN_InitStruct->CAN_TTCM = DISABLE;
+
+ /* Initialize the automatic bus-off management */
+ CAN_InitStruct->CAN_ABOM = DISABLE;
+
+ /* Initialize the automatic wake-up mode */
+ CAN_InitStruct->CAN_AWUM = DISABLE;
+
+ /* Initialize the no automatic retransmission */
+ CAN_InitStruct->CAN_NART = DISABLE;
+
+ /* Initialize the receive FIFO locked mode */
+ CAN_InitStruct->CAN_RFLM = DISABLE;
+
+ /* Initialize the transmit FIFO priority */
+ CAN_InitStruct->CAN_TXFP = DISABLE;
+
+ /* Initialize the CAN_Mode member */
+ CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;
+
+ /* Initialize the CAN_SJW member */
+ CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;
+
+ /* Initialize the CAN_BS1 member */
+ CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;
+
+ /* Initialize the CAN_BS2 member */
+ CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;
+
+ /* Initialize the CAN_Prescaler member */
+ CAN_InitStruct->CAN_Prescaler = 1;
+}
+
+/**
+ * @brief Select the start bank filter for slave CAN.
+ * @param CAN_BankNumber: Select the start slave bank filter from 1..27.
+ * @retval None
+ */
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));
+
+ /* Enter Initialisation mode for the filter */
+ CAN1->FMR |= FMR_FINIT;
+
+ /* Select the start slave bank */
+ CAN1->FMR &= (uint32_t)0xFFFFC0F1 ;
+ CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8;
+
+ /* Leave Initialisation mode for the filter */
+ CAN1->FMR &= ~FMR_FINIT;
+}
+
+/**
+ * @brief Enables or disables the DBG Freeze for CAN.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param NewState: new state of the CAN peripheral.
+ * This parameter can be: ENABLE (CAN reception/transmission is frozen
+ * during debug. Reception FIFOs can still be accessed/controlled normally)
+ * or DISABLE (CAN is working during debug).
+ * @retval None
+ */
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable Debug Freeze */
+ CANx->MCR |= MCR_DBF;
+ }
+ else
+ {
+ /* Disable Debug Freeze */
+ CANx->MCR &= ~MCR_DBF;
+ }
+}
+
+/**
+ * @brief Enables or disables the CAN Time TriggerOperation communication mode.
+ * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be
+ * sent over the CAN bus.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param NewState: Mode new state. This parameter can be: ENABLE or DISABLE.
+ * When enabled, Time stamp (TIME[15:0]) value is sent in the last two
+ * data bytes of the 8-byte message: TIME[7:0] in data byte 6 and TIME[15:8]
+ * in data byte 7.
+ * @retval None
+ */
+void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the TTCM mode */
+ CANx->MCR |= CAN_MCR_TTCM;
+
+ /* Set TGT bits */
+ CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT);
+ CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT);
+ CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT);
+ }
+ else
+ {
+ /* Disable the TTCM mode */
+ CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM);
+
+ /* Reset TGT bits */
+ CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT);
+ CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT);
+ CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT);
+ }
+}
+/**
+ * @}
+ */
+
+
+/** @defgroup CAN_Group2 CAN Frames Transmission functions
+ * @brief CAN Frames Transmission functions
+ *
+@verbatim
+ ===============================================================================
+ ##### CAN Frames Transmission functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to
+ (+) Initiate and transmit a CAN frame message (if there is an empty mailbox).
+ (+) Check the transmission status of a CAN Frame.
+ (+) Cancel a transmit request.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initiates and transmits a CAN frame message.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data.
+ * @retval The number of the mailbox that is used for transmission or
+ * CAN_TxStatus_NoMailBox if there is no empty mailbox.
+ */
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)
+{
+ uint8_t transmit_mailbox = 0;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_IDTYPE(TxMessage->IDE));
+ assert_param(IS_CAN_RTR(TxMessage->RTR));
+ assert_param(IS_CAN_DLC(TxMessage->DLC));
+
+ /* Select one empty transmit mailbox */
+ if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
+ {
+ transmit_mailbox = 0;
+ }
+ else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
+ {
+ transmit_mailbox = 1;
+ }
+ else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
+ {
+ transmit_mailbox = 2;
+ }
+ else
+ {
+ transmit_mailbox = CAN_TxStatus_NoMailBox;
+ }
+
+ if (transmit_mailbox != CAN_TxStatus_NoMailBox)
+ {
+ /* Set up the Id */
+ CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ;
+ if (TxMessage->IDE == CAN_Id_Standard)
+ {
+ assert_param(IS_CAN_STDID(TxMessage->StdId));
+ CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \
+ TxMessage->RTR);
+ }
+ else
+ {
+ assert_param(IS_CAN_EXTID(TxMessage->ExtId));
+ CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \
+ TxMessage->IDE | \
+ TxMessage->RTR);
+ }
+
+ /* Set up the DLC */
+ TxMessage->DLC &= (uint8_t)0x0000000F;
+ CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0;
+ CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC;
+
+ /* Set up the data field */
+ CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) |
+ ((uint32_t)TxMessage->Data[2] << 16) |
+ ((uint32_t)TxMessage->Data[1] << 8) |
+ ((uint32_t)TxMessage->Data[0]));
+ CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) |
+ ((uint32_t)TxMessage->Data[6] << 16) |
+ ((uint32_t)TxMessage->Data[5] << 8) |
+ ((uint32_t)TxMessage->Data[4]));
+ /* Request transmission */
+ CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ;
+ }
+ return transmit_mailbox;
+}
+
+/**
+ * @brief Checks the transmission status of a CAN Frame.
+ * @param CANx: where x can be 1 to select the CAN1 peripheral.
+ * @param TransmitMailbox: the number of the mailbox that is used for transmission.
+ * @retval CAN_TxStatus_Ok if the CAN driver transmits the message,
+ * CAN_TxStatus_Failed in an other case.
+ */
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)
+{
+ uint32_t state = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
+
+ switch (TransmitMailbox)
+ {
+ case (CAN_TXMAILBOX_0):
+ state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0);
+ break;
+ case (CAN_TXMAILBOX_1):
+ state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1);
+ break;
+ case (CAN_TXMAILBOX_2):
+ state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2);
+ break;
+ default:
+ state = CAN_TxStatus_Failed;
+ break;
+ }
+ switch (state)
+ {
+ /* transmit pending */
+ case (0x0): state = CAN_TxStatus_Pending;
+ break;
+ /* transmit failed */
+ case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed;
+ break;
+ case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed;
+ break;
+ case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed;
+ break;
+ /* transmit succeeded */
+ case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok;
+ break;
+ case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok;
+ break;
+ case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok;
+ break;
+ default: state = CAN_TxStatus_Failed;
+ break;
+ }
+ return (uint8_t) state;
+}
+
+/**
+ * @brief Cancels a transmit request.
+ * @param CANx: where x can be 1 to select the CAN1 peripheral.
+ * @param Mailbox: Mailbox number.
+ * @retval None
+ */
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));
+ /* abort transmission */
+ switch (Mailbox)
+ {
+ case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0;
+ break;
+ case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1;
+ break;
+ case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2;
+ break;
+ default:
+ break;
+ }
+}
+/**
+ * @}
+ */
+
+
+/** @defgroup CAN_Group3 CAN Frames Reception functions
+ * @brief CAN Frames Reception functions
+ *
+@verbatim
+ ===============================================================================
+ ##### CAN Frames Reception functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to
+ (+) Receive a correct CAN frame.
+ (+) Release a specified receive FIFO (2 FIFOs are available).
+ (+) Return the number of the pending received CAN frames.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Receives a correct CAN frame.
+ * @param CANx: where x can be 1 to select the CAN1 peripheral.
+ * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @param RxMessage: pointer to a structure receive frame which contains CAN Id,
+ * CAN DLC, CAN data and FMI number.
+ * @retval None
+ */
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FIFO(FIFONumber));
+ /* Get the Id */
+ RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR;
+ if (RxMessage->IDE == CAN_Id_Standard)
+ {
+ RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21);
+ }
+ else
+ {
+ RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3);
+ }
+
+ RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR;
+ /* Get the DLC */
+ RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR;
+ /* Get the FMI */
+ RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8);
+ /* Get the data field */
+ RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR;
+ RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8);
+ RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16);
+ RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24);
+ RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR;
+ RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8);
+ RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16);
+ RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24);
+ /* Release the FIFO */
+ /* Release FIFO0 */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ CANx->RF0R |= CAN_RF0R_RFOM0;
+ }
+ /* Release FIFO1 */
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ CANx->RF1R |= CAN_RF1R_RFOM1;
+ }
+}
+
+/**
+ * @brief Releases the specified receive FIFO.
+ * @param CANx: where x can be 1 to select the CAN1 peripheral.
+ * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.
+ * @retval None
+ */
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FIFO(FIFONumber));
+ /* Release FIFO0 */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ CANx->RF0R |= CAN_RF0R_RFOM0;
+ }
+ /* Release FIFO1 */
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ CANx->RF1R |= CAN_RF1R_RFOM1;
+ }
+}
+
+/**
+ * @brief Returns the number of pending received messages.
+ * @param CANx: where x can be 1 to select the CAN1 peripheral.
+ * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @retval NbMessage : which is the number of pending message.
+ */
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)
+{
+ uint8_t message_pending=0;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FIFO(FIFONumber));
+ if (FIFONumber == CAN_FIFO0)
+ {
+ message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03);
+ }
+ else if (FIFONumber == CAN_FIFO1)
+ {
+ message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03);
+ }
+ else
+ {
+ message_pending = 0;
+ }
+ return message_pending;
+}
+/**
+ * @}
+ */
+
+
+/** @defgroup CAN_Group4 CAN Operation modes functions
+ * @brief CAN Operation modes functions
+ *
+@verbatim
+ ===============================================================================
+ ##### CAN Operation modes functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to select the CAN Operation modes:
+ (+) sleep mode.
+ (+) normal mode.
+ (+) initialization mode.
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Selects the CAN Operation mode.
+ * @param CAN_OperatingMode: CAN Operating Mode.
+ * This parameter can be one of @ref CAN_OperatingMode_TypeDef enumeration.
+ * @retval status of the requested mode which can be:
+ * - CAN_ModeStatus_Failed: CAN failed entering the specific mode
+ * - CAN_ModeStatus_Success: CAN Succeed entering the specific mode
+ */
+uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode)
+{
+ uint8_t status = CAN_ModeStatus_Failed;
+
+ /* Timeout for INAK or also for SLAK bits*/
+ uint32_t timeout = INAK_TIMEOUT;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode));
+
+ if (CAN_OperatingMode == CAN_OperatingMode_Initialization)
+ {
+ /* Request initialisation */
+ CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ);
+
+ /* Wait the acknowledge */
+ while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0))
+ {
+ timeout--;
+ }
+ if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK)
+ {
+ status = CAN_ModeStatus_Failed;
+ }
+ else
+ {
+ status = CAN_ModeStatus_Success;
+ }
+ }
+ else if (CAN_OperatingMode == CAN_OperatingMode_Normal)
+ {
+ /* Request leave initialisation and sleep mode and enter Normal mode */
+ CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ));
+
+ /* Wait the acknowledge */
+ while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0))
+ {
+ timeout--;
+ }
+ if ((CANx->MSR & CAN_MODE_MASK) != 0)
+ {
+ status = CAN_ModeStatus_Failed;
+ }
+ else
+ {
+ status = CAN_ModeStatus_Success;
+ }
+ }
+ else if (CAN_OperatingMode == CAN_OperatingMode_Sleep)
+ {
+ /* Request Sleep mode */
+ CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
+
+ /* Wait the acknowledge */
+ while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0))
+ {
+ timeout--;
+ }
+ if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK)
+ {
+ status = CAN_ModeStatus_Failed;
+ }
+ else
+ {
+ status = CAN_ModeStatus_Success;
+ }
+ }
+ else
+ {
+ status = CAN_ModeStatus_Failed;
+ }
+
+ return (uint8_t) status;
+}
+
+/**
+ * @brief Enters the Sleep (low power) mode.
+ * @param CANx: where x can be 1 to select the CAN1 peripheral.
+ * @retval CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed otherwise.
+ */
+uint8_t CAN_Sleep(CAN_TypeDef* CANx)
+{
+ uint8_t sleepstatus = CAN_Sleep_Failed;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Request Sleep mode */
+ CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
+
+ /* Sleep mode status */
+ if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)
+ {
+ /* Sleep mode not entered */
+ sleepstatus = CAN_Sleep_Ok;
+ }
+ /* return sleep mode status */
+ return (uint8_t)sleepstatus;
+}
+
+/**
+ * @brief Wakes up the CAN peripheral from sleep mode .
+ * @param CANx: where x can be 1 to select the CAN1 peripheral.
+ * @retval CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed otherwise.
+ */
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx)
+{
+ uint32_t wait_slak = SLAK_TIMEOUT;
+ uint8_t wakeupstatus = CAN_WakeUp_Failed;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Wake up request */
+ CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
+
+ /* Sleep mode status */
+ while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00))
+ {
+ wait_slak--;
+ }
+ if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)
+ {
+ /* wake up done : Sleep mode exited */
+ wakeupstatus = CAN_WakeUp_Ok;
+ }
+ /* return wakeup status */
+ return (uint8_t)wakeupstatus;
+}
+/**
+ * @}
+ */
+
+
+/** @defgroup CAN_Group5 CAN Bus Error management functions
+ * @brief CAN Bus Error management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### CAN Bus Error management functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to
+ (+) Return the CANx's last error code (LEC).
+ (+) Return the CANx Receive Error Counter (REC).
+ (+) Return the LSB of the 9-bit CANx Transmit Error Counter(TEC).
+ [..]
+ (@) If TEC is greater than 255, The CAN is in bus-off state.
+ (@) If REC or TEC are greater than 96, an Error warning flag occurs.
+ (@) If REC or TEC are greater than 127, an Error Passive Flag occurs.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the CANx's last error code (LEC).
+ * @param CANx: where x can be 1 to select the CAN1 peripheral.
+ * @retval Error code:
+ * - CAN_ERRORCODE_NoErr: No Error
+ * - CAN_ERRORCODE_StuffErr: Stuff Error
+ * - CAN_ERRORCODE_FormErr: Form Error
+ * - CAN_ERRORCODE_ACKErr : Acknowledgment Error
+ * - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error
+ * - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error
+ * - CAN_ERRORCODE_CRCErr: CRC Error
+ * - CAN_ERRORCODE_SoftwareSetErr: Software Set Error
+ */
+uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx)
+{
+ uint8_t errorcode=0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Get the error code*/
+ errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC);
+
+ /* Return the error code*/
+ return errorcode;
+}
+
+/**
+ * @brief Returns the CANx Receive Error Counter (REC).
+ * @note In case of an error during reception, this counter is incremented
+ * by 1 or by 8 depending on the error condition as defined by the CAN
+ * standard. After every successful reception, the counter is
+ * decremented by 1 or reset to 120 if its value was higher than 128.
+ * When the counter value exceeds 127, the CAN controller enters the
+ * error passive state.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @retval CAN Receive Error Counter.
+ */
+uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx)
+{
+ uint8_t counter=0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Get the Receive Error Counter*/
+ counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24);
+
+ /* Return the Receive Error Counter*/
+ return counter;
+}
+
+
+/**
+ * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @retval LSB of the 9-bit CAN Transmit Error Counter.
+ */
+uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx)
+{
+ uint8_t counter=0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
+ counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16);
+
+ /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
+ return counter;
+}
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Group6 Interrupts and flags management functions
+ * @brief Interrupts and flags management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupts and flags management functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to configure the CAN Interrupts
+ and to get the status and clear flags and Interrupts pending bits.
+ [..] The CAN provides 14 Interrupts sources and 15 Flags:
+
+ *** Flags ***
+ =============
+ [..] The 15 flags can be divided on 4 groups:
+ (+) Transmit Flags:
+ (++) CAN_FLAG_RQCP0.
+ (++) CAN_FLAG_RQCP1.
+ (++) CAN_FLAG_RQCP2: Request completed MailBoxes 0, 1 and 2 Flags
+ Set when when the last request (transmit or abort) has
+ been performed.
+ (+) Receive Flags:
+ (++) CAN_FLAG_FMP0.
+ (++) CAN_FLAG_FMP1: FIFO 0 and 1 Message Pending Flags;
+ Set to signal that messages are pending in the receive FIFO.
+ These Flags are cleared only by hardware.
+ (++) CAN_FLAG_FF0.
+ (++) CAN_FLAG_FF1: FIFO 0 and 1 Full Flags;
+ Set when three messages are stored in the selected FIFO.
+ (++) CAN_FLAG_FOV0.
+ (++) CAN_FLAG_FOV1: FIFO 0 and 1 Overrun Flags;
+ Set when a new message has been received and passed the filter
+ while the FIFO was full.
+ (+) Operating Mode Flags:
+ (++) CAN_FLAG_WKU: Wake up Flag;
+ Set to signal that a SOF bit has been detected while the CAN
+ hardware was in Sleep mode.
+ (++) CAN_FLAG_SLAK: Sleep acknowledge Flag;
+ Set to signal that the CAN has entered Sleep Mode.
+ (+) Error Flags:
+ (++) CAN_FLAG_EWG: Error Warning Flag;
+ Set when the warning limit has been reached (Receive Error Counter
+ or Transmit Error Counter greater than 96).
+ This Flag is cleared only by hardware.
+ (++) CAN_FLAG_EPV: Error Passive Flag;
+ Set when the Error Passive limit has been reached (Receive Error
+ Counter or Transmit Error Counter greater than 127).
+ This Flag is cleared only by hardware.
+ (++) CAN_FLAG_BOF: Bus-Off Flag;
+ Set when CAN enters the bus-off state. The bus-off state is
+ entered on TEC overflow, greater than 255.
+ This Flag is cleared only by hardware.
+ (++) CAN_FLAG_LEC: Last error code Flag;
+ Set If a message has been transferred (reception or transmission)
+ with error, and the error code is hold.
+
+ *** Interrupts ***
+ ==================
+ [..] The 14 interrupts can be divided on 4 groups:
+ (+) Transmit interrupt:
+ (++) CAN_IT_TME: Transmit mailbox empty Interrupt;
+ If enabled, this interrupt source is pending when no transmit
+ request are pending for Tx mailboxes.
+ (+) Receive Interrupts:
+ (++) CAN_IT_FMP0.
+ (++) CAN_IT_FMP1: FIFO 0 and FIFO1 message pending Interrupts;
+ If enabled, these interrupt sources are pending when messages
+ are pending in the receive FIFO.
+ The corresponding interrupt pending bits are cleared only by hardware.
+ (++) CAN_IT_FF0.
+ (++) CAN_IT_FF1: FIFO 0 and FIFO1 full Interrupts;
+ If enabled, these interrupt sources are pending when three messages
+ are stored in the selected FIFO.
+ (++) CAN_IT_FOV0.
+ (++) CAN_IT_FOV1: FIFO 0 and FIFO1 overrun Interrupts;
+ If enabled, these interrupt sources are pending when a new message
+ has been received and passed the filter while the FIFO was full.
+ (+) Operating Mode Interrupts:
+ (++) CAN_IT_WKU: Wake-up Interrupt;
+ If enabled, this interrupt source is pending when a SOF bit has
+ been detected while the CAN hardware was in Sleep mode.
+ (++) CAN_IT_SLK: Sleep acknowledge Interrupt:
+ If enabled, this interrupt source is pending when the CAN has
+ entered Sleep Mode.
+ (+) Error Interrupts:
+ (++) CAN_IT_EWG: Error warning Interrupt;
+ If enabled, this interrupt source is pending when the warning limit
+ has been reached (Receive Error Counter or Transmit Error Counter=96).
+ (++) CAN_IT_EPV: Error passive Interrupt;
+ If enabled, this interrupt source is pending when the Error Passive
+ limit has been reached (Receive Error Counter or Transmit Error Counter>127).
+ (++) CAN_IT_BOF: Bus-off Interrupt;
+ If enabled, this interrupt source is pending when CAN enters
+ the bus-off state. The bus-off state is entered on TEC overflow,
+ greater than 255.
+ This Flag is cleared only by hardware.
+ (++) CAN_IT_LEC: Last error code Interrupt;
+ If enabled, this interrupt source is pending when a message has
+ been transferred (reception or transmission) with error and the
+ error code is hold.
+ (++) CAN_IT_ERR: Error Interrupt;
+ If enabled, this interrupt source is pending when an error condition
+ is pending.
+ [..] Managing the CAN controller events:
+ The user should identify which mode will be used in his application to manage
+ the CAN controller events: Polling mode or Interrupt mode.
+ (+) In the Polling Mode it is advised to use the following functions:
+ (++) CAN_GetFlagStatus() : to check if flags events occur.
+ (++) CAN_ClearFlag() : to clear the flags events.
+ (+) In the Interrupt Mode it is advised to use the following functions:
+ (++) CAN_ITConfig() : to enable or disable the interrupt source.
+ (++) CAN_GetITStatus() : to check if Interrupt occurs.
+ (++) CAN_ClearITPendingBit() : to clear the Interrupt pending Bit
+ (corresponding Flag).
+ This function has no impact on CAN_IT_FMP0 and CAN_IT_FMP1 Interrupts
+ pending bits since there are cleared only by hardware.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Enables or disables the specified CANx interrupts.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg CAN_IT_TME: Transmit mailbox empty Interrupt
+ * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt
+ * @arg CAN_IT_FF0: FIFO 0 full Interrupt
+ * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
+ * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt
+ * @arg CAN_IT_FF1: FIFO 1 full Interrupt
+ * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
+ * @arg CAN_IT_WKU: Wake-up Interrupt
+ * @arg CAN_IT_SLK: Sleep acknowledge Interrupt
+ * @arg CAN_IT_EWG: Error warning Interrupt
+ * @arg CAN_IT_EPV: Error passive Interrupt
+ * @arg CAN_IT_BOF: Bus-off Interrupt
+ * @arg CAN_IT_LEC: Last error code Interrupt
+ * @arg CAN_IT_ERR: Error Interrupt
+ * @param NewState: new state of the CAN interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_IT(CAN_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected CANx interrupt */
+ CANx->IER |= CAN_IT;
+ }
+ else
+ {
+ /* Disable the selected CANx interrupt */
+ CANx->IER &= ~CAN_IT;
+ }
+}
+/**
+ * @brief Checks whether the specified CAN flag is set or not.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag
+ * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag
+ * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag
+ * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
+ * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
+ * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
+ * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
+ * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
+ * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
+ * @arg CAN_FLAG_WKU: Wake up Flag
+ * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
+ * @arg CAN_FLAG_EWG: Error Warning Flag
+ * @arg CAN_FLAG_EPV: Error Passive Flag
+ * @arg CAN_FLAG_BOF: Bus-Off Flag
+ * @arg CAN_FLAG_LEC: Last error code Flag
+ * @retval The new state of CAN_FLAG (SET or RESET).
+ */
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_GET_FLAG(CAN_FLAG));
+
+
+ if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET)
+ {
+ /* Check the status of the specified CAN flag */
+ if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET)
+ {
+ /* Check the status of the specified CAN flag */
+ if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET)
+ {
+ /* Check the status of the specified CAN flag */
+ if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET)
+ {
+ /* Check the status of the specified CAN flag */
+ if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */
+ {
+ /* Check the status of the specified CAN flag */
+ if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ /* Return the CAN_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the CAN's pending flags.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_FLAG: specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag
+ * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag
+ * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag
+ * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
+ * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
+ * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
+ * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
+ * @arg CAN_FLAG_WKU: Wake up Flag
+ * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
+ * @arg CAN_FLAG_LEC: Last error code Flag
+ * @retval None
+ */
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
+{
+ uint32_t flagtmp=0;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG));
+
+ if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */
+ {
+ /* Clear the selected CAN flags */
+ CANx->ESR = (uint32_t)RESET;
+ }
+ else /* MSR or TSR or RF0R or RF1R */
+ {
+ flagtmp = CAN_FLAG & 0x000FFFFF;
+
+ if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET)
+ {
+ /* Receive Flags */
+ CANx->RF0R = (uint32_t)(flagtmp);
+ }
+ else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET)
+ {
+ /* Receive Flags */
+ CANx->RF1R = (uint32_t)(flagtmp);
+ }
+ else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET)
+ {
+ /* Transmit Flags */
+ CANx->TSR = (uint32_t)(flagtmp);
+ }
+ else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */
+ {
+ /* Operating mode Flags */
+ CANx->MSR = (uint32_t)(flagtmp);
+ }
+ }
+}
+
+/**
+ * @brief Checks whether the specified CANx interrupt has occurred or not.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_IT: specifies the CAN interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg CAN_IT_TME: Transmit mailbox empty Interrupt
+ * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt
+ * @arg CAN_IT_FF0: FIFO 0 full Interrupt
+ * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
+ * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt
+ * @arg CAN_IT_FF1: FIFO 1 full Interrupt
+ * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
+ * @arg CAN_IT_WKU: Wake-up Interrupt
+ * @arg CAN_IT_SLK: Sleep acknowledge Interrupt
+ * @arg CAN_IT_EWG: Error warning Interrupt
+ * @arg CAN_IT_EPV: Error passive Interrupt
+ * @arg CAN_IT_BOF: Bus-off Interrupt
+ * @arg CAN_IT_LEC: Last error code Interrupt
+ * @arg CAN_IT_ERR: Error Interrupt
+ * @retval The current state of CAN_IT (SET or RESET).
+ */
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)
+{
+ ITStatus itstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_IT(CAN_IT));
+
+ /* check the interrupt enable bit */
+ if((CANx->IER & CAN_IT) != RESET)
+ {
+ /* in case the Interrupt is enabled, .... */
+ switch (CAN_IT)
+ {
+ case CAN_IT_TME:
+ /* Check CAN_TSR_RQCPx bits */
+ itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2);
+ break;
+ case CAN_IT_FMP0:
+ /* Check CAN_RF0R_FMP0 bit */
+ itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0);
+ break;
+ case CAN_IT_FF0:
+ /* Check CAN_RF0R_FULL0 bit */
+ itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0);
+ break;
+ case CAN_IT_FOV0:
+ /* Check CAN_RF0R_FOVR0 bit */
+ itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0);
+ break;
+ case CAN_IT_FMP1:
+ /* Check CAN_RF1R_FMP1 bit */
+ itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1);
+ break;
+ case CAN_IT_FF1:
+ /* Check CAN_RF1R_FULL1 bit */
+ itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1);
+ break;
+ case CAN_IT_FOV1:
+ /* Check CAN_RF1R_FOVR1 bit */
+ itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1);
+ break;
+ case CAN_IT_WKU:
+ /* Check CAN_MSR_WKUI bit */
+ itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI);
+ break;
+ case CAN_IT_SLK:
+ /* Check CAN_MSR_SLAKI bit */
+ itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI);
+ break;
+ case CAN_IT_EWG:
+ /* Check CAN_ESR_EWGF bit */
+ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF);
+ break;
+ case CAN_IT_EPV:
+ /* Check CAN_ESR_EPVF bit */
+ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF);
+ break;
+ case CAN_IT_BOF:
+ /* Check CAN_ESR_BOFF bit */
+ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF);
+ break;
+ case CAN_IT_LEC:
+ /* Check CAN_ESR_LEC bit */
+ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC);
+ break;
+ case CAN_IT_ERR:
+ /* Check CAN_MSR_ERRI bit */
+ itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI);
+ break;
+ default:
+ /* in case of error, return RESET */
+ itstatus = RESET;
+ break;
+ }
+ }
+ else
+ {
+ /* in case the Interrupt is not enabled, return RESET */
+ itstatus = RESET;
+ }
+
+ /* Return the CAN_IT status */
+ return itstatus;
+}
+
+/**
+ * @brief Clears the CANx's interrupt pending bits.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_IT: specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg CAN_IT_TME: Transmit mailbox empty Interrupt
+ * @arg CAN_IT_FF0: FIFO 0 full Interrupt
+ * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
+ * @arg CAN_IT_FF1: FIFO 1 full Interrupt
+ * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
+ * @arg CAN_IT_WKU: Wake-up Interrupt
+ * @arg CAN_IT_SLK: Sleep acknowledge Interrupt
+ * @arg CAN_IT_EWG: Error warning Interrupt
+ * @arg CAN_IT_EPV: Error passive Interrupt
+ * @arg CAN_IT_BOF: Bus-off Interrupt
+ * @arg CAN_IT_LEC: Last error code Interrupt
+ * @arg CAN_IT_ERR: Error Interrupt
+ * @retval None
+ */
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_CLEAR_IT(CAN_IT));
+
+ switch (CAN_IT)
+ {
+ case CAN_IT_TME:
+ /* Clear CAN_TSR_RQCPx (rc_w1)*/
+ CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2;
+ break;
+ case CAN_IT_FF0:
+ /* Clear CAN_RF0R_FULL0 (rc_w1)*/
+ CANx->RF0R = CAN_RF0R_FULL0;
+ break;
+ case CAN_IT_FOV0:
+ /* Clear CAN_RF0R_FOVR0 (rc_w1)*/
+ CANx->RF0R = CAN_RF0R_FOVR0;
+ break;
+ case CAN_IT_FF1:
+ /* Clear CAN_RF1R_FULL1 (rc_w1)*/
+ CANx->RF1R = CAN_RF1R_FULL1;
+ break;
+ case CAN_IT_FOV1:
+ /* Clear CAN_RF1R_FOVR1 (rc_w1)*/
+ CANx->RF1R = CAN_RF1R_FOVR1;
+ break;
+ case CAN_IT_WKU:
+ /* Clear CAN_MSR_WKUI (rc_w1)*/
+ CANx->MSR = CAN_MSR_WKUI;
+ break;
+ case CAN_IT_SLK:
+ /* Clear CAN_MSR_SLAKI (rc_w1)*/
+ CANx->MSR = CAN_MSR_SLAKI;
+ break;
+ case CAN_IT_EWG:
+ /* Clear CAN_MSR_ERRI (rc_w1) */
+ CANx->MSR = CAN_MSR_ERRI;
+ /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
+ break;
+ case CAN_IT_EPV:
+ /* Clear CAN_MSR_ERRI (rc_w1) */
+ CANx->MSR = CAN_MSR_ERRI;
+ /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
+ break;
+ case CAN_IT_BOF:
+ /* Clear CAN_MSR_ERRI (rc_w1) */
+ CANx->MSR = CAN_MSR_ERRI;
+ /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
+ break;
+ case CAN_IT_LEC:
+ /* Clear LEC bits */
+ CANx->ESR = RESET;
+ /* Clear CAN_MSR_ERRI (rc_w1) */
+ CANx->MSR = CAN_MSR_ERRI;
+ break;
+ case CAN_IT_ERR:
+ /*Clear LEC bits */
+ CANx->ESR = RESET;
+ /* Clear CAN_MSR_ERRI (rc_w1) */
+ CANx->MSR = CAN_MSR_ERRI;
+ /* @note BOFF, EPVF and EWGF Flags are cleared by hardware depending on the CAN Bus status*/
+ break;
+ default:
+ break;
+ }
+}
+ /**
+ * @}
+ */
+
+/**
+ * @brief Checks whether the CAN interrupt has occurred or not.
+ * @param CAN_Reg: specifies the CAN interrupt register to check.
+ * @param It_Bit: specifies the interrupt source bit to check.
+ * @retval The new state of the CAN Interrupt (SET or RESET).
+ */
+static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)
+{
+ ITStatus pendingbitstatus = RESET;
+
+ if ((CAN_Reg & It_Bit) != (uint32_t)RESET)
+ {
+ /* CAN_IT is set */
+ pendingbitstatus = SET;
+ }
+ else
+ {
+ /* CAN_IT is reset */
+ pendingbitstatus = RESET;
+ }
+ return pendingbitstatus;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_can.h Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,653 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_can.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the CAN firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_CAN_H
+#define __STM32F30x_CAN_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CAN
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1))
+
+/**
+ * @brief CAN init structure definition
+ */
+typedef struct
+{
+ uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum.
+ It ranges from 1 to 1024. */
+
+ uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.
+ This parameter can be a value of @ref CAN_operating_mode */
+
+ uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta
+ the CAN hardware is allowed to lengthen or
+ shorten a bit to perform resynchronization.
+ This parameter can be a value of @ref CAN_synchronisation_jump_width */
+
+ uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit
+ Segment 1. This parameter can be a value of
+ @ref CAN_time_quantum_in_bit_segment_1 */
+
+ uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
+
+ FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode.
+ This parameter can be set either to ENABLE or DISABLE. */
+
+ FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management.
+ This parameter can be set either to ENABLE or DISABLE. */
+
+ FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode.
+ This parameter can be set either to ENABLE or DISABLE. */
+
+ FunctionalState CAN_NART; /*!< Enable or disable the non-automatic retransmission mode.
+ This parameter can be set either to ENABLE or DISABLE. */
+
+ FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
+ This parameter can be set either to ENABLE or DISABLE. */
+
+ FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority.
+ This parameter can be set either to ENABLE or DISABLE. */
+} CAN_InitTypeDef;
+
+/**
+ * @brief CAN filter init structure definition
+ */
+typedef struct
+{
+ uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
+ configuration, first one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
+ configuration, second one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
+ according to the mode (MSBs for a 32-bit configuration,
+ first one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
+ according to the mode (LSBs for a 32-bit configuration,
+ second one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
+ This parameter can be a value of @ref CAN_filter_FIFO */
+
+ uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
+
+ uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.
+ This parameter can be a value of @ref CAN_filter_mode */
+
+ uint8_t CAN_FilterScale; /*!< Specifies the filter scale.
+ This parameter can be a value of @ref CAN_filter_scale */
+
+ FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
+ This parameter can be set either to ENABLE or DISABLE. */
+} CAN_FilterInitTypeDef;
+
+/**
+ * @brief CAN Tx message structure definition
+ */
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter can be a value between 0 to 0x7FF. */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+ uint8_t IDE; /*!< Specifies the type of identifier for the message that
+ will be transmitted. This parameter can be a value
+ of @ref CAN_identifier_type */
+
+ uint8_t RTR; /*!< Specifies the type of frame for the message that will
+ be transmitted. This parameter can be a value of
+ @ref CAN_remote_transmission_request */
+
+ uint8_t DLC; /*!< Specifies the length of the frame that will be
+ transmitted. This parameter can be a value between
+ 0 to 8 */
+
+ uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
+ to 0xFF. */
+} CanTxMsg;
+
+/**
+ * @brief CAN Rx message structure definition
+ */
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter can be a value between 0 to 0x7FF. */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+ uint8_t IDE; /*!< Specifies the type of identifier for the message that
+ will be received. This parameter can be a value of
+ @ref CAN_identifier_type */
+
+ uint8_t RTR; /*!< Specifies the type of frame for the received message.
+ This parameter can be a value of
+ @ref CAN_remote_transmission_request */
+
+ uint8_t DLC; /*!< Specifies the length of the frame that will be received.
+ This parameter can be a value between 0 to 8 */
+
+ uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
+ 0xFF. */
+
+ uint8_t FMI; /*!< Specifies the index of the filter the message stored in
+ the mailbox passes through. This parameter can be a
+ value between 0 to 0xFF */
+} CanRxMsg;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CAN_Exported_Constants
+ * @{
+ */
+
+/** @defgroup CAN_InitStatus
+ * @{
+ */
+
+#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */
+#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */
+
+
+/* Legacy defines */
+#define CANINITFAILED CAN_InitStatus_Failed
+#define CANINITOK CAN_InitStatus_Success
+/**
+ * @}
+ */
+
+/** @defgroup CAN_operating_mode
+ * @{
+ */
+
+#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */
+#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */
+#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */
+#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */
+
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
+ ((MODE) == CAN_Mode_LoopBack)|| \
+ ((MODE) == CAN_Mode_Silent) || \
+ ((MODE) == CAN_Mode_Silent_LoopBack))
+/**
+ * @}
+ */
+
+
+ /**
+ * @defgroup CAN_operating_mode
+ * @{
+ */
+#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */
+#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */
+#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */
+
+
+#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
+ ((MODE) == CAN_OperatingMode_Normal)|| \
+ ((MODE) == CAN_OperatingMode_Sleep))
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CAN_operating_mode_status
+ * @{
+ */
+
+#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */
+#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_synchronisation_jump_width
+ * @{
+ */
+#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */
+
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
+ ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_1
+ * @{
+ */
+#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */
+#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */
+#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */
+#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */
+#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */
+#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */
+#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */
+#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */
+#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */
+#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */
+#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */
+#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */
+#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */
+
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
+/**
+ * @}
+ */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_2
+ * @{
+ */
+#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */
+#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */
+#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */
+#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */
+#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */
+
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
+/**
+ * @}
+ */
+
+/** @defgroup CAN_clock_prescaler
+ * @{
+ */
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_number
+ * @{
+ */
+#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_mode
+ * @{
+ */
+#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */
+#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */
+
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
+ ((MODE) == CAN_FilterMode_IdList))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_scale
+ * @{
+ */
+#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */
+#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */
+
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
+ ((SCALE) == CAN_FilterScale_32bit))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_FIFO
+ * @{
+ */
+#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
+ ((FIFO) == CAN_FilterFIFO1))
+
+/* Legacy defines */
+#define CAN_FilterFIFO0 CAN_Filter_FIFO0
+#define CAN_FilterFIFO1 CAN_Filter_FIFO1
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Start_bank_filter_for_slave_CAN
+ * @{
+ */
+#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Tx
+ * @{
+ */
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_identifier_type
+ * @{
+ */
+#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */
+#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
+ ((IDTYPE) == CAN_Id_Extended))
+
+/* Legacy defines */
+#define CAN_ID_STD CAN_Id_Standard
+#define CAN_ID_EXT CAN_Id_Extended
+/**
+ * @}
+ */
+
+/** @defgroup CAN_remote_transmission_request
+ * @{
+ */
+#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */
+#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
+
+/* Legacy defines */
+#define CAN_RTR_DATA CAN_RTR_Data
+#define CAN_RTR_REMOTE CAN_RTR_Remote
+/**
+ * @}
+ */
+
+/** @defgroup CAN_transmit_constants
+ * @{
+ */
+#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */
+#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */
+#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */
+#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide
+ an empty mailbox */
+/* Legacy defines */
+#define CANTXFAILED CAN_TxStatus_Failed
+#define CANTXOK CAN_TxStatus_Ok
+#define CANTXPENDING CAN_TxStatus_Pending
+#define CAN_NO_MB CAN_TxStatus_NoMailBox
+/**
+ * @}
+ */
+
+/** @defgroup CAN_receive_FIFO_number_constants
+ * @{
+ */
+#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
+#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
+
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_sleep_constants
+ * @{
+ */
+#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
+#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */
+
+/* Legacy defines */
+#define CANSLEEPFAILED CAN_Sleep_Failed
+#define CANSLEEPOK CAN_Sleep_Ok
+/**
+ * @}
+ */
+
+/** @defgroup CAN_wake_up_constants
+ * @{
+ */
+#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
+#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
+
+/* Legacy defines */
+#define CANWAKEUPFAILED CAN_WakeUp_Failed
+#define CANWAKEUPOK CAN_WakeUp_Ok
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CAN_Error_Code_constants
+ * @{
+ */
+#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */
+#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */
+#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */
+#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */
+#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */
+#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */
+#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */
+#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_flags
+ * @{
+ */
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
+ and CAN_ClearFlag() functions. */
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with
+ CAN_GetFlagStatus() function. */
+
+/* Transmit Flags */
+#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
+#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
+#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
+
+/* Receive Flags */
+#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
+#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */
+#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */
+#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
+#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */
+#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */
+#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
+/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
+ In this case the SLAK bit can be polled.*/
+
+/* Error Flags */
+#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */
+#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */
+#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */
+#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */
+
+#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \
+ ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \
+ ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \
+ ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \
+ ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \
+ ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
+ ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
+ ((FLAG) == CAN_FLAG_SLAK ))
+
+#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
+ ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
+ ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\
+ ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
+ ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
+/**
+ * @}
+ */
+
+
+/** @defgroup CAN_interrupts
+ * @{
+ */
+#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
+
+/* Receive Interrupts */
+#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
+#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
+#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
+#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
+#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
+#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
+
+/* Operating Mode Interrupts */
+#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
+#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
+
+/* Error Interrupts */
+#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
+#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
+#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
+#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
+#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/
+
+/* Flags named as Interrupts : kept only for FW compatibility */
+#define CAN_IT_RQCP0 CAN_IT_TME
+#define CAN_IT_RQCP1 CAN_IT_TME
+#define CAN_IT_RQCP2 CAN_IT_TME
+
+
+#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
+ ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
+ ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
+ ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
+ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+
+#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
+ ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
+ ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
+ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* Function used to set the CAN configuration to the default reset state *****/
+void CAN_DeInit(CAN_TypeDef* CANx);
+
+/* Initialization and Configuration functions *********************************/
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
+void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
+
+/* CAN Frames Transmission functions ******************************************/
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
+
+/* CAN Frames Reception functions *********************************************/
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
+
+/* Operation modes functions **************************************************/
+uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
+uint8_t CAN_Sleep(CAN_TypeDef* CANx);
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
+
+/* CAN Bus Error management functions *****************************************/
+uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
+uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
+uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
+
+/* Interrupts and flags management functions **********************************/
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F30x_CAN_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_comp.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,514 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_comp.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the 7 analog comparators (COMP1, COMP2...COMP7) peripheral:
+ * + Comparators configuration
+ * + Window mode control
+ *
+ @verbatim
+
+ ==============================================================================
+ ##### COMP Peripheral features #####
+ ==============================================================================
+ [..]
+ The device integrates 7 analog comparators COMP1, COMP2...COMP7:
+ (#) The non inverting input and inverting input can be set to GPIO pins
+ as shown in table1. COMP Inputs below.
+
+ (#) The COMP output is internally is available using COMP_GetOutputLevel()
+ and can be set on GPIO pins. Refer to table 2. COMP Outputs below.
+
+ (#) The COMP output can be redirected to embedded timers (TIM1, TIM2, TIM3...)
+ Refer to table 3. COMP Outputs redirection to embedded timers below.
+
+ (#) The comparators COMP1 and COMP2, COMP3 and COMP4, COMP5 and COMP6 can be combined in window
+ mode and only COMP1, COMP3 and COMP5 non inverting input can be used as non-inverting input.
+
+ (#) The seven comparators have interrupt capability with wake-up
+ from Sleep and Stop modes (through the EXTI controller):
+ (++) COMP1 is internally connected to EXTI Line 21
+ (++) COMP2 is internally connected to EXTI Line 22
+ (++) COMP3 is internally connected to EXTI Line 29
+ (++) COMP4 is internally connected to EXTI Line 30
+ (++) COMP5 is internally connected to EXTI Line 31
+ (++) COMP6 is internally connected to EXTI Line 32
+ (++) COMP7 is internally connected to EXTI Line 33
+
+ [..] Table 1. COMP Inputs
+ +------------------------------------------------------------------------------------------+
+ | | | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
+ |-----------------|----------------|---------------|---------------------------------------|
+ | | 1/4 VREFINT | OK | OK | OK | OK | OK | OK | OK |
+ | | 1/2 VREFINT | OK | OK | OK | OK | OK | OK | OK |
+ | | 3/4 VREFINT | OK | OK | OK | OK | OK | OK | OK |
+ | Inverting Input | VREFINT | OK | OK | OK | OK | OK | OK | OK |
+ | | DAC1 OUT1(PA4) | OK | OK | OK | OK | OK | OK | OK |
+ | | DAC1 OUT2(PA5) | OK | OK | OK | OK | OK | OK | OK |
+ | | IO1 | PA0 | PA2 | PD15 | PE8 | PD13 | PD10 | PC0 |
+ | | IO2 | --- | --- | PB12 | PB2 | PB10 | PB15 | --- |
+ | | DAC2 OUT1(PA6) | --- | OK | --- | OK | --- | OK | --- |
+ |-----------------|----------------|-------|-------|-------|-------|-------|-------|-------|
+ | Non Inverting | IO1 | PA1 | PA7 | PB14 | PB0 | PD12 | PD11 | PA0 |
+ | Input | IO2 | --- | PA3 | PD14 | PE7 | PB13 | PB11 | PC1 |
+ +------------------------------------------------------------------------------------------+
+
+ [..] Table 2. COMP Outputs
+ +-------------------------------------------------------+
+ | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
+ |-------|-------|-------|-------|-------|-------|-------|
+ | PA0 | PA2 | PB1 | PC8 | PC7 | PA10 | PC2 |
+ | PF4 | PA7 | --- | PA8 | PA9 | PC6 | --- |
+ | PA6 | PA12 | --- | --- | --- | --- | --- |
+ | PA11 | PB9 | --- | --- | --- | --- | --- |
+ | PB8 | --- | --- | --- | --- | --- | --- |
+ +-------------------------------------------------------+
+
+ [..] Table 3. COMP Outputs redirection to embedded timers
+ +----------------------------------------------------------------------------------------------------------------------+
+ | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
+ |----------------|----------------|----------------|----------------|----------------|----------------|----------------|
+ | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN |
+ | | | | | | | |
+ | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 |
+ | | | | | | | |
+ | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN |
+ | | | | | | | |
+ | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 |
+ | | | | | | | |
+ | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 |
+ | + | + | + | + | + | + | + |
+ | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 |
+ | | | | | | | |
+ | TIM1 OCREFCLR | TIM1 OCREFCLR | TIM1 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM1 OCREFCLR |
+ | | | | | | | |
+ | TIM1 IC1 | TIM1 IC1 | TIM2 OCREFCLR | TIM3 IC3 | TIM2 IC1 | TIM2 IC2 | TIM8 OCREFCLR |
+ | | | | | | | |
+ | TIM2 IC4 | TIM2 IC4 | TIM3 IC2 | TIM3 OCREFCLR | TIM3 OCREFCLR | TIM2 OCREFCLR | TIM2 IC3 |
+ | | | | | | | |
+ | TIM2 OCREFCLR | TIM2 OCREFCLR | TIM4 IC1 | TIM4 IC2 | TIM4 IC3 | TIM16 OCREFCLR| TIM1 IC2 |
+ | | | | | | | |
+ | TIM3 IC1 | TIM3 IC1 | TIM15 IC1 | TIM15 OCREFCLR| TIM16 BKIN | TIM16 IC1 | TIM17 OCREFCLR|
+ | | | | | | | |
+ | TIM3 OCREFCLR | TIM3 OCREFCLR | TIM15 BKIN | TIM15 IC2 | TIM17 IC1 | TIM4 IC4 | TIM17 BKIN |
+ +----------------------------------------------------------------------------------------------------------------------+
+
+ [..] Table 4. COMP Outputs blanking sources
+ +----------------------------------------------------------------------------------------------------------------------+
+ | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
+ |----------------|----------------|----------------|----------------|----------------|----------------|----------------|
+ | TIM1 OC5 | TIM1 OC5 | TIM1 OC5 | TIM3 OC4 | TIM3 OC3 | TIM2 OC4 | TIM1 OC5 |
+ | | | | | | | |
+ | TIM2 OC3 | TIM2 OC3 | -------- | TIM8 OC5 | TIM8 OC5 | TIM8 OC5 | TIM8 OC5 |
+ | | | | | | | |
+ | TIM3 OC3 | TIM3 OC3 | TIM2 OC4 | TIM15 OC1 | TIM8 BKIN | TIM15 OC2 | TIM15 OC2 |
+ | | | | | | | |
+ +----------------------------------------------------------------------------------------------------------------------+
+
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver provides functions to configure and program the Comparators
+ of all STM32F30x devices.
+
+ To use the comparator, perform the following steps:
+
+ (#) Enable the SYSCFG APB clock to get write access to comparator
+ register using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+
+ (#) Configure the comparator input in analog mode using GPIO_Init()
+
+ (#) Configure the comparator output in alternate function mode
+ using GPIO_Init() and use GPIO_PinAFConfig() function to map the
+ comparator output to the GPIO pin
+
+ (#) Configure the comparator using COMP_Init() function:
+ (++) Select the inverting input
+ (++) Select the non-inverting input
+ (++) Select the output polarity
+ (++) Select the output redirection
+ (++) Select the hysteresis level
+ (++) Select the power mode
+
+ (#) Enable the comparator using COMP_Cmd() function
+
+ (#) If required enable the COMP interrupt by configuring and enabling
+ EXTI line in Interrupt mode and selecting the desired sensitivity
+ level using EXTI_Init() function. After that enable the comparator
+ interrupt vector using NVIC_Init() function.
+
+ @endverbatim
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_comp.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup COMP
+ * @brief COMP driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* CSR register Mask */
+#define COMP_CSR_CLEAR_MASK ((uint32_t)0x00000003)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup COMP_Private_Functions
+ * @{
+ */
+
+/** @defgroup COMP_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes COMP peripheral registers to their default reset values.
+ * @note Deinitialization can't be performed if the COMP configuration is locked.
+ * To unlock the configuration, perform a system reset.
+ * @param COMP_Selection: the selected comparator.
+ * This parameter can be COMP_Selection_COMPx where x can be 1 to 7
+ * to select the COMP peripheral.
+ * @param None
+ * @retval None
+ */
+void COMP_DeInit(uint32_t COMP_Selection)
+{
+ /*!< Set COMP_CSR register to reset value */
+ *(__IO uint32_t *) (COMP_BASE + COMP_Selection) = ((uint32_t)0x00000000);
+}
+
+/**
+ * @brief Initializes the COMP peripheral according to the specified parameters
+ * in COMP_InitStruct
+ * @note If the selected comparator is locked, initialization can't be performed.
+ * To unlock the configuration, perform a system reset.
+ * @note By default, PA1 is selected as COMP1 non inverting input.
+ * To use PA4 as COMP1 non inverting input call COMP_SwitchCmd() after COMP_Init()
+ * @param COMP_Selection: the selected comparator.
+ * This parameter can be COMP_Selection_COMPx where x can be 1 to 7
+ * to select the COMP peripheral.
+ * @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure that contains
+ * the configuration information for the specified COMP peripheral.
+ * - COMP_InvertingInput specifies the inverting input of COMP
+ * - COMP_NonInvertingInput specifies the non inverting input of COMP
+ * - COMP_Output connect COMP output to selected timer
+ * input (Input capture / Output Compare Reference Clear / Break Input)
+ * - COMP_BlankingSrce specifies the blanking source of COMP
+ * - COMP_OutputPol select output polarity
+ * - COMP_Hysteresis configures COMP hysteresis value
+ * - COMP_Mode configures COMP power mode
+ * @retval None
+ */
+void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+ assert_param(IS_COMP_INVERTING_INPUT(COMP_InitStruct->COMP_InvertingInput));
+ assert_param(IS_COMP_NONINVERTING_INPUT(COMP_InitStruct->COMP_NonInvertingInput));
+ assert_param(IS_COMP_OUTPUT(COMP_InitStruct->COMP_Output));
+ assert_param(IS_COMP_BLANKING_SOURCE(COMP_InitStruct->COMP_BlankingSrce));
+ assert_param(IS_COMP_OUTPUT_POL(COMP_InitStruct->COMP_OutputPol));
+ assert_param(IS_COMP_HYSTERESIS(COMP_InitStruct->COMP_Hysteresis));
+ assert_param(IS_COMP_MODE(COMP_InitStruct->COMP_Mode));
+
+ /*!< Get the COMPx_CSR register value */
+ tmpreg = *(__IO uint32_t *) (COMP_BASE + COMP_Selection);
+
+ /*!< Clear the COMP1SW1, COMPxINSEL, COMPxOUTSEL, COMPxPOL, COMPxHYST and COMPxMODE bits */
+ tmpreg &= (uint32_t) (COMP_CSR_CLEAR_MASK);
+
+ /*!< Configure COMP: inverting input, output redirection, hysteresis value and power mode */
+ /*!< Set COMPxINSEL bits according to COMP_InitStruct->COMP_InvertingInput value */
+ /*!< Set COMPxNONINSEL bits according to COMP_InitStruct->COMP_NonInvertingInput value */
+ /*!< Set COMPxBLANKING bits according to COMP_InitStruct->COMP_BlankingSrce value */
+ /*!< Set COMPxOUTSEL bits according to COMP_InitStruct->COMP_Output value */
+ /*!< Set COMPxPOL bit according to COMP_InitStruct->COMP_OutputPol value */
+ /*!< Set COMPxHYST bits according to COMP_InitStruct->COMP_Hysteresis value */
+ /*!< Set COMPxMODE bits according to COMP_InitStruct->COMP_Mode value */
+ tmpreg |= (uint32_t)(COMP_InitStruct->COMP_InvertingInput | COMP_InitStruct->COMP_NonInvertingInput |
+ COMP_InitStruct->COMP_Output | COMP_InitStruct->COMP_OutputPol | COMP_InitStruct->COMP_BlankingSrce |
+ COMP_InitStruct->COMP_Hysteresis | COMP_InitStruct->COMP_Mode);
+
+ /*!< Write to COMPx_CSR register */
+ *(__IO uint32_t *) (COMP_BASE + COMP_Selection) = tmpreg;
+}
+
+/**
+ * @brief Fills each COMP_InitStruct member with its default value.
+ * @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct)
+{
+ COMP_InitStruct->COMP_InvertingInput = COMP_InvertingInput_1_4VREFINT;
+ COMP_InitStruct->COMP_NonInvertingInput = COMP_NonInvertingInput_IO1;
+ COMP_InitStruct->COMP_Output = COMP_Output_None;
+ COMP_InitStruct->COMP_BlankingSrce = COMP_BlankingSrce_None;
+ COMP_InitStruct->COMP_OutputPol = COMP_OutputPol_NonInverted;
+ COMP_InitStruct->COMP_Hysteresis = COMP_Hysteresis_No;
+ COMP_InitStruct->COMP_Mode = COMP_Mode_UltraLowPower;
+}
+
+/**
+ * @brief Enable or disable the COMP peripheral.
+ * @note If the selected comparator is locked, enable/disable can't be performed.
+ * To unlock the configuration, perform a system reset.
+ * @param COMP_Selection: the selected comparator.
+ * This parameter can be COMP_Selection_COMPx where x can be 1 to 7
+ * to select the COMP peripheral.
+ * @param NewState: new state of the COMP peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * When enabled, the comparator compares the non inverting input with
+ * the inverting input and the comparison result is available
+ * on comparator output.
+ * When disabled, the comparator doesn't perform comparison and the
+ * output level is low.
+ * @retval None
+ */
+void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected COMPx peripheral */
+ *(__IO uint32_t *) (COMP_BASE + COMP_Selection) |= (uint32_t) (COMP_CSR_COMPxEN);
+ }
+ else
+ {
+ /* Disable the selected COMP peripheral */
+ *(__IO uint32_t *) (COMP_BASE + COMP_Selection) &= (uint32_t)(~COMP_CSR_COMPxEN);
+ }
+}
+
+/**
+ * @brief Close or Open the SW1 switch.
+ * @note If the COMP1 is locked, Close/Open the SW1 switch can't be performed.
+ * To unlock the configuration, perform a system reset.
+ * @note This switch is solely intended to redirect signals onto high
+ * impedance input, such as COMP1 non-inverting input (highly resistive switch)
+ * @param NewState: New state of the analog switch.
+ * This parameter can be
+ * ENABLE so the SW1 is closed; PA1 is connected to PA4
+ * or DISABLE so the SW1 switch is open; PA1 is disconnected from PA4
+ * @retval None
+ */
+void COMP_SwitchCmd(uint32_t COMP_Selection, FunctionalState NewState)
+{
+ /* Check the parameter */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Close SW1 switch */
+ *(__IO uint32_t *) (COMP_BASE + COMP_Selection) |= (uint32_t) (COMP_CSR_COMP1SW1);
+ }
+ else
+ {
+ /* Open SW1 switch */
+ *(__IO uint32_t *) (COMP_BASE + COMP_Selection) &= (uint32_t)(~COMP_CSR_COMP1SW1);
+ }
+}
+
+/**
+ * @brief Return the output level (high or low) of the selected comparator.
+ * The output level depends on the selected polarity.
+ * If the polarity is not inverted:
+ * - Comparator output is low when the non-inverting input is at a lower
+ * voltage than the inverting input
+ * - Comparator output is high when the non-inverting input is at a higher
+ * voltage than the inverting input
+ * If the polarity is inverted:
+ * - Comparator output is high when the non-inverting input is at a lower
+ * voltage than the inverting input
+ * - Comparator output is low when the non-inverting input is at a higher
+ * voltage than the inverting input
+ * @param COMP_Selection: the selected comparator.
+ * This parameter can be COMP_Selection_COMPx where x can be 1 to 7
+ * to select the COMP peripheral.
+ * @retval Returns the selected comparator output level: low or high.
+ *
+ */
+uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection)
+{
+ uint32_t compout = 0x0;
+
+ /* Check the parameters */
+ assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+
+ /* Check if selected comparator output is high */
+ if ((*(__IO uint32_t *) (COMP_BASE + COMP_Selection) & (COMP_CSR_COMPxOUT)) != 0)
+ {
+ compout = COMP_OutputLevel_High;
+ }
+ else
+ {
+ compout = COMP_OutputLevel_Low;
+ }
+
+ /* Return the comparator output level */
+ return (uint32_t)(compout);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_Group2 Window mode control function
+ * @brief Window mode control function
+ *
+@verbatim
+ ===============================================================================
+ ##### Window mode control function #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the window mode.
+ * Window mode for comparators makes use of two comparators:
+ * COMP1 and COM2, COMP3 and COMP4, COMP5 and COMP6.
+ * In window mode, COMPx and COMPx-1 (where x can be 2, 4 or 6)
+ * non inverting inputs are connected together and only COMPx-1 non
+ * inverting input can be used.
+ * e.g When window mode enabled for COMP4, COMP3 non inverting input (PB14 or PD14)
+ * is to be used.
+ * @note If the COMPx is locked, ENABLE/DISABLE the window mode can't be performed.
+ * To unlock the configuration, perform a system reset.
+ * @param COMP_Selection: the selected comparator.
+ * This parameter can be COMP_Selection_COMPx where x can be 2, 4 or 6
+ * to select the COMP peripheral.
+ * param NewState: new state of the window mode.
+ * This parameter can be ENABLE or DISABLE.
+ * When enbaled, COMPx and COMPx-1 non inverting inputs are connected together.
+ * When disabled, COMPx and COMPx-1 non inverting inputs are disconnected.
+ * @retval None
+ */
+void COMP_WindowCmd(uint32_t COMP_Selection, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_COMP_WINDOW(COMP_Selection));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the window mode */
+ *(__IO uint32_t *) (COMP_BASE + COMP_Selection) |= (uint32_t) COMP_CSR_COMPxWNDWEN;
+ }
+ else
+ {
+ /* Disable the window mode */
+ *(__IO uint32_t *) (COMP_BASE + COMP_Selection) &= (uint32_t)(~COMP_CSR_COMPxWNDWEN);
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_Group3 COMP configuration locking function
+ * @brief COMP1, COMP2,...COMP7 configuration locking function
+ * COMP1, COMP2,...COMP7 configuration can be locked each separately.
+ * Unlocking is performed by system reset.
+ *
+@verbatim
+ ===============================================================================
+ ##### Configuration Lock function #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Lock the selected comparator (COMP1/COMP2) configuration.
+ * @note Locking the configuration means that all control bits are read-only.
+ * To unlock the comparator configuration, perform a system reset.
+ * @param COMP_Selection: the selected comparator.
+ * This parameter can be COMP_Selection_COMPx where x can be 1 to 7
+ * to select the COMP peripheral.
+ * @retval None
+ */
+void COMP_LockConfig(uint32_t COMP_Selection)
+{
+ /* Check the parameter */
+ assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+
+ /* Set the lock bit corresponding to selected comparator */
+ *(__IO uint32_t *) (COMP_BASE + COMP_Selection) |= (uint32_t) (COMP_CSR_COMPxLOCK);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_comp.h Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,436 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_comp.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the COMP firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_COMP_H
+#define __STM32F30x_COMP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup COMP
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief COMP Init structure definition
+ */
+
+typedef struct
+{
+
+ uint32_t COMP_InvertingInput; /*!< Selects the inverting input of the comparator.
+ This parameter can be a value of @ref COMP_InvertingInput */
+
+ uint32_t COMP_NonInvertingInput; /*!< Selects the non inverting input of the comparator.
+ This parameter can be a value of @ref COMP_NonInvertingInput */
+
+ uint32_t COMP_Output; /*!< Selects the output redirection of the comparator.
+ This parameter can be a value of @ref COMP_Output */
+
+ uint32_t COMP_BlankingSrce; /*!< Selects the output blanking source of the comparator.
+ This parameter can be a value of @ref COMP_BlankingSrce */
+
+ uint32_t COMP_OutputPol; /*!< Selects the output polarity of the comparator.
+ This parameter can be a value of @ref COMP_OutputPoloarity */
+
+ uint32_t COMP_Hysteresis; /*!< Selects the hysteresis voltage of the comparator.
+ This parameter can be a value of @ref COMP_Hysteresis */
+
+ uint32_t COMP_Mode; /*!< Selects the operating mode of the comparator
+ and allows to adjust the speed/consumption.
+ This parameter can be a value of @ref COMP_Mode */
+}COMP_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup COMP_Exported_Constants
+ * @{
+ */
+
+/** @defgroup COMP_Selection
+ * @{
+ */
+
+#define COMP_Selection_COMP1 ((uint32_t)0x00000000) /*!< COMP1 Selection */
+#define COMP_Selection_COMP2 ((uint32_t)0x00000004) /*!< COMP2 Selection */
+#define COMP_Selection_COMP3 ((uint32_t)0x00000008) /*!< COMP3 Selection */
+#define COMP_Selection_COMP4 ((uint32_t)0x0000000C) /*!< COMP4 Selection */
+#define COMP_Selection_COMP5 ((uint32_t)0x00000010) /*!< COMP5 Selection */
+#define COMP_Selection_COMP6 ((uint32_t)0x00000014) /*!< COMP6 Selection */
+#define COMP_Selection_COMP7 ((uint32_t)0x00000018) /*!< COMP7 Selection */
+
+#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \
+ ((PERIPH) == COMP_Selection_COMP2) || \
+ ((PERIPH) == COMP_Selection_COMP3) || \
+ ((PERIPH) == COMP_Selection_COMP4) || \
+ ((PERIPH) == COMP_Selection_COMP5) || \
+ ((PERIPH) == COMP_Selection_COMP6) || \
+ ((PERIPH) == COMP_Selection_COMP7))
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_InvertingInput
+ * @{
+ */
+
+#define COMP_InvertingInput_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */
+#define COMP_InvertingInput_1_2VREFINT COMP_CSR_COMPxINSEL_0 /*!< 1/2 VREFINT connected to comparator inverting input */
+#define COMP_InvertingInput_3_4VREFINT COMP_CSR_COMPxINSEL_1 /*!< 3/4 VREFINT connected to comparator inverting input */
+#define COMP_InvertingInput_VREFINT ((uint32_t)0x00000030) /*!< VREFINT connected to comparator inverting input */
+#define COMP_InvertingInput_DAC1OUT1 COMP_CSR_COMPxINSEL_2 /*!< DAC1_OUT1 (PA4) connected to comparator inverting input */
+#define COMP_InvertingInput_DAC1OUT2 ((uint32_t)0x00000050) /*!< DAC1_OUT2 (PA5) connected to comparator inverting input */
+
+#define COMP_InvertingInput_IO1 ((uint32_t)0x00000060) /*!< I/O1 (PA0 for COMP1, PA2 for COMP2, PD15 for COMP3,
+ PE8 for COMP4, PD13 for COMP5, PD10 for COMP6,
+ PC0 for COMP7) connected to comparator inverting input */
+
+#define COMP_InvertingInput_IO2 COMP_CSR_COMPxINSEL /*!< I/O2 (PB12 for COMP3, PB2 for COMP4, PB10 for COMP5,
+ PB15 for COMP6) connected to comparator inverting input */
+
+#define COMP_InvertingInput_DAC2OUT1 COMP_CSR_COMPxINSEL_3 /*!< DAC2_OUT1 (PA6) connected to comparator inverting input */
+
+#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_1_4VREFINT) || \
+ ((INPUT) == COMP_InvertingInput_1_2VREFINT) || \
+ ((INPUT) == COMP_InvertingInput_3_4VREFINT) || \
+ ((INPUT) == COMP_InvertingInput_VREFINT) || \
+ ((INPUT) == COMP_InvertingInput_DAC1OUT1) || \
+ ((INPUT) == COMP_InvertingInput_DAC1OUT2) || \
+ ((INPUT) == COMP_InvertingInput_IO1) || \
+ ((INPUT) == COMP_InvertingInput_IO2) || \
+ ((INPUT) == COMP_InvertingInput_DAC2OUT1))
+/**
+ * @}
+ */
+
+/** @defgroup COMP_NonInvertingInput
+ * @{
+ */
+
+#define COMP_NonInvertingInput_IO1 ((uint32_t)0x00000000) /*!< I/O1 (PA1 for COMP1, PA7 for COMP2, PB14 for COMP3,
+ PB0 for COMP4, PD12 for COMP5, PD11 for COMP6,
+ PA0 for COMP7) connected to comparator non inverting input */
+
+#define COMP_NonInvertingInput_IO2 COMP_CSR_COMPxNONINSEL /*!< I/O2 (PA3 for COMP2, PD14 for COMP3, PE7 for COMP4, PB13 for COMP5,
+ PB11 for COMP6, PC1 for COMP7) connected to comparator non inverting input */
+
+#define IS_COMP_NONINVERTING_INPUT(INPUT) (((INPUT) == COMP_NonInvertingInput_IO1) || \
+ ((INPUT) == COMP_NonInvertingInput_IO2))
+/**
+ * @}
+ */
+
+/** @defgroup COMP_Output
+ * @{
+ */
+
+#define COMP_Output_None ((uint32_t)0x00000000) /*!< COMP output isn't connected to other peripherals */
+
+/* Output Redirection common for all comparators COMP1...COMP7 */
+#define COMP_Output_TIM1BKIN COMP_CSR_COMPxOUTSEL_0 /*!< COMP output connected to TIM1 Break Input (BKIN) */
+#define COMP_Output_TIM1BKIN2 ((uint32_t)0x00000800) /*!< COMP output connected to TIM1 Break Input 2 (BKIN2) */
+#define COMP_Output_TIM8BKIN ((uint32_t)0x00000C00) /*!< COMP output connected to TIM8 Break Input (BKIN) */
+#define COMP_Output_TIM8BKIN2 ((uint32_t)0x00001000) /*!< COMP output connected to TIM8 Break Input 2 (BKIN2) */
+#define COMP_Output_TIM1BKIN2_TIM8BKIN2 ((uint32_t)0x00001400) /*!< COMP output connected to TIM1 Break Input 2 and TIM8 Break Input 2 */
+
+/* Output Redirection common for COMP1 and COMP2 */
+#define COMP_Output_TIM1OCREFCLR ((uint32_t)0x00001800) /*!< COMP output connected to TIM1 OCREF Clear */
+#define COMP_Output_TIM1IC1 ((uint32_t)0x00001C00) /*!< COMP output connected to TIM1 Input Capture 1 */
+#define COMP_Output_TIM2IC4 ((uint32_t)0x00002000) /*!< COMP output connected to TIM2 Input Capture 4 */
+#define COMP_Output_TIM2OCREFCLR ((uint32_t)0x00002400) /*!< COMP output connected to TIM2 OCREF Clear */
+#define COMP_Output_TIM3IC1 ((uint32_t)0x00002800) /*!< COMP output connected to TIM3 Input Capture 1 */
+#define COMP_Output_TIM3OCREFCLR ((uint32_t)0x00002C00) /*!< COMP output connected to TIM3 OCREF Clear */
+
+/* Output Redirection specific to COMP2 */
+#define COMP_Output_HRTIM1_FLT6 ((uint32_t)0x00003000) /*!< COMP output connected to HRTIM1 FLT6 */
+#define COMP_Output_HRTIM1_EE1_2 ((uint32_t)0x00003400) /*!< COMP output connected to HRTIM1 EE1_2*/
+#define COMP_Output_HRTIM1_EE6_2 ((uint32_t)0x00003800) /*!< COMP output connected to HRTIM1 EE6_2 */
+
+/* Output Redirection specific to COMP3 */
+#define COMP_Output_TIM4IC1 ((uint32_t)0x00001C00) /*!< COMP output connected to TIM4 Input Capture 1 */
+#define COMP_Output_TIM3IC2 ((uint32_t)0x00002000) /*!< COMP output connected to TIM3 Input Capture 2 */
+#define COMP_Output_TIM15IC1 ((uint32_t)0x00002800) /*!< COMP output connected to TIM15 Input Capture 1 */
+#define COMP_Output_TIM15BKIN ((uint32_t)0x00002C00) /*!< COMP output connected to TIM15 Break Input (BKIN) */
+
+/* Output Redirection specific to COMP4 */
+#define COMP_Output_TIM3IC3 ((uint32_t)0x00001800) /*!< COMP output connected to TIM3 Input Capture 3 */
+#define COMP_Output_TIM8OCREFCLR ((uint32_t)0x00001C00) /*!< COMP output connected to TIM8 OCREF Clear */
+#define COMP_Output_TIM15IC2 ((uint32_t)0x00002000) /*!< COMP output connected to TIM15 Input Capture 2 */
+#define COMP_Output_TIM4IC2 ((uint32_t)0x00002400) /*!< COMP output connected to TIM4 Input Capture 2 */
+#define COMP_Output_TIM15OCREFCLR ((uint32_t)0x00002800) /*!< COMP output connected to TIM15 OCREF Clear */
+
+#define COMP_Output_HRTIM1_FLT7 ((uint32_t)0x00003000) /*!< COMP output connected to HRTIM1 FLT7 */
+#define COMP_Output_HRTIM1_EE2_2 ((uint32_t)0x00003400) /*!< COMP output connected to HRTIM1 EE2_2*/
+#define COMP_Output_HRTIM1_EE7_2 ((uint32_t)0x00003800) /*!< COMP output connected to HRTIM1 EE7_2 */
+
+/* Output Redirection specific to COMP5 */
+#define COMP_Output_TIM2IC1 ((uint32_t)0x00001800) /*!< COMP output connected to TIM2 Input Capture 1 */
+#define COMP_Output_TIM17IC1 ((uint32_t)0x00002000) /*!< COMP output connected to TIM17 Input Capture 1 */
+#define COMP_Output_TIM4IC3 ((uint32_t)0x00002400) /*!< COMP output connected to TIM4 Input Capture 3 */
+#define COMP_Output_TIM16BKIN ((uint32_t)0x00002800) /*!< COMP output connected to TIM16 Break Input (BKIN) */
+
+/* Output Redirection specific to COMP6 */
+#define COMP_Output_TIM2IC2 ((uint32_t)0x00001800) /*!< COMP output connected to TIM2 Input Capture 2 */
+#define COMP_Output_COMP6TIM2OCREFCLR ((uint32_t)0x00002000) /*!< COMP output connected to TIM2 OCREF Clear */
+#define COMP_Output_TIM16OCREFCLR ((uint32_t)0x00002400) /*!< COMP output connected to TIM16 OCREF Clear */
+#define COMP_Output_TIM16IC1 ((uint32_t)0x00002800) /*!< COMP output connected to TIM16 Input Capture 1 */
+#define COMP_Output_TIM4IC4 ((uint32_t)0x00002C00) /*!< COMP output connected to TIM4 Input Capture 4 */
+
+#define COMP_Output_HRTIM1_FLT8 ((uint32_t)0x00003000) /*!< COMP output connected to HRTIM1 FLT8 */
+#define COMP_Output_HRTIM1_EE3_2 ((uint32_t)0x00003400) /*!< COMP output connected to HRTIM1 EE3_2*/
+#define COMP_Output_HRTIM1_EE8_2 ((uint32_t)0x00003800) /*!< COMP output connected to HRTIM1 EE8_2 */
+
+/* Output Redirection specific to COMP7 */
+#define COMP_Output_TIM2IC3 ((uint32_t)0x00002000) /*!< COMP output connected to TIM2 Input Capture 3 */
+#define COMP_Output_TIM1IC2 ((uint32_t)0x00002400) /*!< COMP output connected to TIM1 Input Capture 2 */
+#define COMP_Output_TIM17OCREFCLR ((uint32_t)0x00002800) /*!< COMP output connected to TIM16 OCREF Clear */
+#define COMP_Output_TIM17BKIN ((uint32_t)0x00002C00) /*!< COMP output connected to TIM16 Break Input (BKIN) */
+
+#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_Output_None) || \
+ ((OUTPUT) == COMP_Output_TIM1BKIN) || \
+ ((OUTPUT) == COMP_Output_TIM1IC1) || \
+ ((OUTPUT) == COMP_Output_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_Output_TIM2IC4) || \
+ ((OUTPUT) == COMP_Output_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_Output_COMP6TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_Output_TIM3IC1) || \
+ ((OUTPUT) == COMP_Output_TIM3OCREFCLR) || \
+ ((OUTPUT) == COMP_Output_TIM8BKIN) || \
+ ((OUTPUT) == COMP_Output_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_Output_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_Output_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_Output_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_Output_TIM3IC2) || \
+ ((OUTPUT) == COMP_Output_TIM4IC1) || \
+ ((OUTPUT) == COMP_Output_TIM15IC1) || \
+ ((OUTPUT) == COMP_Output_TIM15BKIN) || \
+ ((OUTPUT) == COMP_Output_TIM8OCREFCLR) || \
+ ((OUTPUT) == COMP_Output_TIM3IC3) || \
+ ((OUTPUT) == COMP_Output_TIM4IC1) || \
+ ((OUTPUT) == COMP_Output_TIM15IC1) || \
+ ((OUTPUT) == COMP_Output_TIM2IC1) || \
+ ((OUTPUT) == COMP_Output_TIM4IC3) || \
+ ((OUTPUT) == COMP_Output_TIM16BKIN) || \
+ ((OUTPUT) == COMP_Output_TIM17IC1) || \
+ ((OUTPUT) == COMP_Output_TIM2IC2) || \
+ ((OUTPUT) == COMP_Output_TIM16IC1) || \
+ ((OUTPUT) == COMP_Output_TIM4IC4) || \
+ ((OUTPUT) == COMP_Output_TIM16OCREFCLR) || \
+ ((OUTPUT) == COMP_Output_TIM2IC3) || \
+ ((OUTPUT) == COMP_Output_TIM1IC2) || \
+ ((OUTPUT) == COMP_Output_TIM17BKIN) || \
+ ((OUTPUT) == COMP_Output_TIM17OCREFCLR) || \
+ ((OUTPUT) == COMP_Output_HRTIM1_FLT6) || \
+ ((OUTPUT) == COMP_Output_HRTIM1_EE1_2) || \
+ ((OUTPUT) == COMP_Output_HRTIM1_EE6_2) || \
+ ((OUTPUT) == COMP_Output_HRTIM1_FLT7) || \
+ ((OUTPUT) == COMP_Output_HRTIM1_EE2_2) || \
+ ((OUTPUT) == COMP_Output_HRTIM1_EE7_2) || \
+ ((OUTPUT) == COMP_Output_HRTIM1_FLT8) || \
+ ((OUTPUT) == COMP_Output_HRTIM1_EE3_2) || \
+ ((OUTPUT) == COMP_Output_HRTIM1_EE8_2))
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_BlankingSrce
+ * @{
+ */
+
+/* No blanking source can be selected for all comparators */
+#define COMP_BlankingSrce_None ((uint32_t)0x00000000) /*!< No blanking source */
+
+/* Blanking source common for COMP1, COMP2, COMP3 and COMP7 */
+#define COMP_BlankingSrce_TIM1OC5 COMP_CSR_COMPxBLANKING_0 /*!< TIM1 OC5 selected as blanking source for compartor */
+
+/* Blanking source common for COMP1 and COMP2 */
+#define COMP_BlankingSrce_TIM2OC3 COMP_CSR_COMPxBLANKING_1 /*!< TIM2 OC5 selected as blanking source for compartor */
+
+/* Blanking source common for COMP1, COMP2 and COMP5 */
+#define COMP_BlankingSrce_TIM3OC3 ((uint32_t)0x000C0000) /*!< TIM2 OC3 selected as blanking source for compartor */
+
+/* Blanking source common for COMP3 and COMP6 */
+#define COMP_BlankingSrce_TIM2OC4 ((uint32_t)0x000C0000) /*!< TIM2 OC4 selected as blanking source for compartor */
+
+/* Blanking source common for COMP4, COMP5, COMP6 and COMP7 */
+#define COMP_BlankingSrce_TIM8OC5 COMP_CSR_COMPxBLANKING_1 /*!< TIM8 OC5 selected as blanking source for compartor */
+
+/* Blanking source for COMP4 */
+#define COMP_BlankingSrce_TIM3OC4 COMP_CSR_COMPxBLANKING_0 /*!< TIM3 OC4 selected as blanking source for compartor */
+#define COMP_BlankingSrce_TIM15OC1 ((uint32_t)0x000C0000) /*!< TIM15 OC1 selected as blanking source for compartor */
+
+/* Blanking source common for COMP6 and COMP7 */
+#define COMP_BlankingSrce_TIM15OC2 COMP_CSR_COMPxBLANKING_2 /*!< TIM15 OC2 selected as blanking source for compartor */
+
+#define IS_COMP_BLANKING_SOURCE(SOURCE) (((SOURCE) == COMP_BlankingSrce_None) || \
+ ((SOURCE) == COMP_BlankingSrce_TIM1OC5) || \
+ ((SOURCE) == COMP_BlankingSrce_TIM2OC3) || \
+ ((SOURCE) == COMP_BlankingSrce_TIM3OC3) || \
+ ((SOURCE) == COMP_BlankingSrce_TIM2OC4) || \
+ ((SOURCE) == COMP_BlankingSrce_TIM8OC5) || \
+ ((SOURCE) == COMP_BlankingSrce_TIM3OC4) || \
+ ((SOURCE) == COMP_BlankingSrce_TIM15OC1) || \
+ ((SOURCE) == COMP_BlankingSrce_TIM15OC2))
+/**
+ * @}
+ */
+
+/** @defgroup COMP_OutputPoloarity
+ * @{
+ */
+#define COMP_OutputPol_NonInverted ((uint32_t)0x00000000) /*!< COMP output on GPIO isn't inverted */
+#define COMP_OutputPol_Inverted COMP_CSR_COMPxPOL /*!< COMP output on GPIO is inverted */
+
+#define IS_COMP_OUTPUT_POL(POL) (((POL) == COMP_OutputPol_NonInverted) || \
+ ((POL) == COMP_OutputPol_Inverted))
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_Hysteresis
+ * @{
+ */
+/* Please refer to the electrical characteristics in the device datasheet for
+ the hysteresis level */
+#define COMP_Hysteresis_No 0x00000000 /*!< No hysteresis */
+#define COMP_Hysteresis_Low COMP_CSR_COMPxHYST_0 /*!< Hysteresis level low */
+#define COMP_Hysteresis_Medium COMP_CSR_COMPxHYST_1 /*!< Hysteresis level medium */
+#define COMP_Hysteresis_High COMP_CSR_COMPxHYST /*!< Hysteresis level high */
+
+#define IS_COMP_HYSTERESIS(HYSTERESIS) (((HYSTERESIS) == COMP_Hysteresis_No) || \
+ ((HYSTERESIS) == COMP_Hysteresis_Low) || \
+ ((HYSTERESIS) == COMP_Hysteresis_Medium) || \
+ ((HYSTERESIS) == COMP_Hysteresis_High))
+/**
+ * @}
+ */
+
+/** @defgroup COMP_Mode
+ * @{
+ */
+/* Please refer to the electrical characteristics in the device datasheet for
+ the power consumption values */
+#define COMP_Mode_HighSpeed 0x00000000 /*!< High Speed */
+#define COMP_Mode_MediumSpeed COMP_CSR_COMPxMODE_0 /*!< Medium Speed */
+#define COMP_Mode_LowPower COMP_CSR_COMPxMODE_1 /*!< Low power mode */
+#define COMP_Mode_UltraLowPower COMP_CSR_COMPxMODE /*!< Ultra-low power mode */
+
+#define IS_COMP_MODE(MODE) (((MODE) == COMP_Mode_UltraLowPower) || \
+ ((MODE) == COMP_Mode_LowPower) || \
+ ((MODE) == COMP_Mode_MediumSpeed) || \
+ ((MODE) == COMP_Mode_HighSpeed))
+/**
+ * @}
+ */
+
+/** @defgroup COMP_OutputLevel
+ * @{
+ */
+/* When output polarity is not inverted, comparator output is high when
+ the non-inverting input is at a higher voltage than the inverting input */
+#define COMP_OutputLevel_High COMP_CSR_COMPxOUT
+/* When output polarity is not inverted, comparator output is low when
+ the non-inverting input is at a lower voltage than the inverting input*/
+#define COMP_OutputLevel_Low ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_WindowMode
+ * @{
+ */
+#define IS_COMP_WINDOW(WINDOW) (((WINDOW) == COMP_Selection_COMP2) || \
+ ((WINDOW) == COMP_Selection_COMP4) || \
+ ((WINDOW) == COMP_Selection_COMP6))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the COMP configuration to the default reset state ****/
+void COMP_DeInit(uint32_t COMP_Selection);
+
+/* Initialization and Configuration functions *********************************/
+void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct);
+void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct);
+void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState);
+void COMP_SwitchCmd(uint32_t COMP_Selection, FunctionalState NewState);
+uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection);
+
+/* Window mode control function ***********************************************/
+void COMP_WindowCmd(uint32_t COMP_Selection, FunctionalState NewState);
+
+/* COMP configuration locking function ****************************************/
+void COMP_LockConfig(uint32_t COMP_Selection);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F30x_COMP_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_conf.h Tue Apr 08 09:15:06 2014 +0100 @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file stm32f30x_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 27-February-2014 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F30X_CONF_H +#define __STM32F30X_CONF_H + + +/* Includes ------------------------------------------------------------------*/ +/* Comment the line below to disable peripheral header file inclusion */ +#include "stm32f30x_adc.h" +#include "stm32f30x_can.h" +#include "stm32f30x_crc.h" +#include "stm32f30x_comp.h" +#include "stm32f30x_dac.h" +#include "stm32f30x_dbgmcu.h" +#include "stm32f30x_dma.h" +#include "stm32f30x_exti.h" +#include "stm32f30x_flash.h" +#include "stm32f30x_gpio.h" +#include "stm32f30x_hrtim.h" +#include "stm32f30x_syscfg.h" +#include "stm32f30x_i2c.h" +#include "stm32f30x_iwdg.h" +#include "stm32f30x_opamp.h" +#include "stm32f30x_pwr.h" +#include "stm32f30x_rcc.h" +#include "stm32f30x_rtc.h" +#include "stm32f30x_spi.h" +#include "stm32f30x_tim.h" +#include "stm32f30x_usart.h" +#include "stm32f30x_wwdg.h" +#include "stm32f30x_misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F30X_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_crc.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,364 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_crc.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of CRC computation unit peripheral:
+ * + Configuration of the CRC computation unit
+ * + CRC computation of one/many 32-bit data
+ * + CRC Independent register (IDR) access
+ *
+ @verbatim
+
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ (#) Enable CRC AHB clock using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_CRC, ENABLE)
+ function.
+ (#) Select the polynomial size: 7-bit, 8-bit, 16-bit or 32-bit.
+ (#) Set the polynomial coefficients using CRC_SetPolynomial();
+ (#) If required, select the reverse operation on input data
+ using CRC_ReverseInputDataSelect();
+ (#) If required, enable the reverse operation on output data
+ using CRC_ReverseOutputDataCmd(Enable);
+ (#) If required, set the initialization remainder value using
+ CRC_SetInitRegister();
+ (#) use CRC_CalcCRC() function to compute the CRC of a 32-bit data
+ or use CRC_CalcBlockCRC() function to compute the CRC if a 32-bit
+ data buffer.
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_crc.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup CRC
+ * @brief CRC driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup CRC_Private_Functions
+ * @{
+ */
+
+/** @defgroup CRC_Group1 Configuration of the CRC computation unit functions
+ * @brief Configuration of the CRC computation unit functions
+ *
+@verbatim
+ ===============================================================================
+ ##### CRC configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes CRC peripheral registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void CRC_DeInit(void)
+{
+ /* Set DR register to reset value */
+ CRC->DR = 0xFFFFFFFF;
+ /* Set the POL register to the reset value: 0x04C11DB7 */
+ CRC->POL = 0x04C11DB7;
+ /* Reset IDR register */
+ CRC->IDR = 0x00;
+ /* Set INIT register to reset value */
+ CRC->INIT = 0xFFFFFFFF;
+ /* Reset the CRC calculation unit */
+ CRC->CR = CRC_CR_RESET;
+}
+
+/**
+ * @brief Resets the CRC calculation unit and sets INIT register content in DR register.
+ * @param None
+ * @retval None
+ */
+void CRC_ResetDR(void)
+{
+ /* Reset CRC generator */
+ CRC->CR |= CRC_CR_RESET;
+}
+
+/**
+ * @brief Selects the polynomial size.
+ * @param CRC_PolSize: Specifies the polynomial size.
+ * This parameter can be:
+ * @arg CRC_PolSize_7: 7-bit polynomial for CRC calculation
+ * @arg CRC_PolSize_8: 8-bit polynomial for CRC calculation
+ * @arg CRC_PolSize_16: 16-bit polynomial for CRC calculation
+ * @arg CRC_PolSize_32: 32-bit polynomial for CRC calculation
+ * @retval None
+ */
+void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize)
+{
+ uint32_t tmpcr = 0;
+
+ /* Check the parameter */
+ assert_param(IS_CRC_POL_SIZE(CRC_PolSize));
+
+ /* Get CR register value */
+ tmpcr = CRC->CR;
+
+ /* Reset POL_SIZE bits */
+ tmpcr &= (uint32_t)~((uint32_t)CRC_CR_POLSIZE);
+ /* Set the polynomial size */
+ tmpcr |= (uint32_t)CRC_PolSize;
+
+ /* Write to CR register */
+ CRC->CR = (uint32_t)tmpcr;
+}
+
+/**
+ * @brief Selects the reverse operation to be performed on input data.
+ * @param CRC_ReverseInputData: Specifies the reverse operation on input data.
+ * This parameter can be:
+ * @arg CRC_ReverseInputData_No: No reverse operation is performed
+ * @arg CRC_ReverseInputData_8bits: reverse operation performed on 8 bits
+ * @arg CRC_ReverseInputData_16bits: reverse operation performed on 16 bits
+ * @arg CRC_ReverseInputData_32bits: reverse operation performed on 32 bits
+ * @retval None
+ */
+void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData)
+{
+ uint32_t tmpcr = 0;
+
+ /* Check the parameter */
+ assert_param(IS_CRC_REVERSE_INPUT_DATA(CRC_ReverseInputData));
+
+ /* Get CR register value */
+ tmpcr = CRC->CR;
+
+ /* Reset REV_IN bits */
+ tmpcr &= (uint32_t)~((uint32_t)CRC_CR_REV_IN);
+ /* Set the reverse operation */
+ tmpcr |= (uint32_t)CRC_ReverseInputData;
+
+ /* Write to CR register */
+ CRC->CR = (uint32_t)tmpcr;
+}
+
+/**
+ * @brief Enables or disable the reverse operation on output data.
+ * The reverse operation on output data is performed on 32-bit.
+ * @param NewState: new state of the reverse operation on output data.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void CRC_ReverseOutputDataCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable reverse operation on output data */
+ CRC->CR |= CRC_CR_REV_OUT;
+ }
+ else
+ {
+ /* Disable reverse operation on output data */
+ CRC->CR &= (uint32_t)~((uint32_t)CRC_CR_REV_OUT);
+ }
+}
+
+/**
+ * @brief Initializes the INIT register.
+ * @note After resetting CRC calculation unit, CRC_InitValue is stored in DR register
+ * @param CRC_InitValue: Programmable initial CRC value
+ * @retval None
+ */
+void CRC_SetInitRegister(uint32_t CRC_InitValue)
+{
+ CRC->INIT = CRC_InitValue;
+}
+
+/**
+ * @brief Initializes the polynomail coefficients.
+ * @param CRC_Pol: Polynomial to be used for CRC calculation.
+ * @retval None
+ */
+void CRC_SetPolynomial(uint32_t CRC_Pol)
+{
+ CRC->POL = CRC_Pol;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Group2 CRC computation of one/many 32-bit data functions
+ * @brief CRC computation of one/many 32-bit data functions
+ *
+@verbatim
+ ===============================================================================
+ ##### CRC computation functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Computes the 32-bit CRC of a given data word(32-bit).
+ * @param CRC_Data: data word(32-bit) to compute its CRC
+ * @retval 32-bit CRC
+ */
+uint32_t CRC_CalcCRC(uint32_t CRC_Data)
+{
+ CRC->DR = CRC_Data;
+
+ return (CRC->DR);
+}
+
+/**
+ * @brief Computes the 16-bit CRC of a given 16-bit data.
+ * @param CRC_Data: data half-word(16-bit) to compute its CRC
+ * @retval 16-bit CRC
+ */
+uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data)
+{
+ *(uint16_t*)(CRC_BASE) = (uint16_t) CRC_Data;
+
+ return (CRC->DR);
+}
+
+/**
+ * @brief Computes the 8-bit CRC of a given 8-bit data.
+ * @param CRC_Data: 8-bit data to compute its CRC
+ * @retval 8-bit CRC
+ */
+uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data)
+{
+ *(uint8_t*)(CRC_BASE) = (uint8_t) CRC_Data;
+
+ return (CRC->DR);
+}
+
+/**
+ * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
+ * @param pBuffer: pointer to the buffer containing the data to be computed
+ * @param BufferLength: length of the buffer to be computed
+ * @retval 32-bit CRC
+ */
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t index = 0;
+
+ for(index = 0; index < BufferLength; index++)
+ {
+ CRC->DR = pBuffer[index];
+ }
+ return (CRC->DR);
+}
+
+/**
+ * @brief Returns the current CRC value.
+ * @param None
+ * @retval 32-bit CRC
+ */
+uint32_t CRC_GetCRC(void)
+{
+ return (CRC->DR);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Group3 CRC Independent Register (IDR) access functions
+ * @brief CRC Independent Register (IDR) access (write/read) functions
+ *
+@verbatim
+ ===============================================================================
+ ##### CRC Independent Register (IDR) access functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Stores an 8-bit data in the Independent Data(ID) register.
+ * @param CRC_IDValue: 8-bit value to be stored in the ID register
+ * @retval None
+ */
+void CRC_SetIDRegister(uint8_t CRC_IDValue)
+{
+ CRC->IDR = CRC_IDValue;
+}
+
+/**
+ * @brief Returns the 8-bit data stored in the Independent Data(ID) register
+ * @param None
+ * @retval 8-bit value of the ID register
+ */
+uint8_t CRC_GetIDRegister(void)
+{
+ return (CRC->IDR);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_crc.h Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,131 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_crc.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the CRC firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_CRC_H
+#define __STM32F30x_CRC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*!< Includes ----------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CRC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CRC_ReverseInputData
+ * @{
+ */
+#define CRC_ReverseInputData_No ((uint32_t)0x00000000) /*!< No reverse operation of Input Data */
+#define CRC_ReverseInputData_8bits CRC_CR_REV_IN_0 /*!< Reverse operation of Input Data on 8 bits */
+#define CRC_ReverseInputData_16bits CRC_CR_REV_IN_1 /*!< Reverse operation of Input Data on 16 bits */
+#define CRC_ReverseInputData_32bits CRC_CR_REV_IN /*!< Reverse operation of Input Data on 32 bits */
+
+#define IS_CRC_REVERSE_INPUT_DATA(DATA) (((DATA) == CRC_ReverseInputData_No) || \
+ ((DATA) == CRC_ReverseInputData_8bits) || \
+ ((DATA) == CRC_ReverseInputData_16bits) || \
+ ((DATA) == CRC_ReverseInputData_32bits))
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_PolynomialSize
+ * @{
+ */
+#define CRC_PolSize_7 CRC_CR_POLSIZE /*!< 7-bit polynomial for CRC calculation */
+#define CRC_PolSize_8 CRC_CR_POLSIZE_1 /*!< 8-bit polynomial for CRC calculation */
+#define CRC_PolSize_16 CRC_CR_POLSIZE_0 /*!< 16-bit polynomial for CRC calculation */
+#define CRC_PolSize_32 ((uint32_t)0x00000000)/*!< 32-bit polynomial for CRC calculation */
+
+#define IS_CRC_POL_SIZE(SIZE) (((SIZE) == CRC_PolSize_7) || \
+ ((SIZE) == CRC_PolSize_8) || \
+ ((SIZE) == CRC_PolSize_16) || \
+ ((SIZE) == CRC_PolSize_32))
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* Configuration of the CRC computation unit **********************************/
+void CRC_DeInit(void);
+void CRC_ResetDR(void);
+void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize);
+void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData);
+void CRC_ReverseOutputDataCmd(FunctionalState NewState);
+void CRC_SetInitRegister(uint32_t CRC_InitValue);
+void CRC_SetPolynomial(uint32_t CRC_Pol);
+
+/* CRC computation ************************************************************/
+uint32_t CRC_CalcCRC(uint32_t CRC_Data);
+uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data);
+uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data);
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t CRC_GetCRC(void);
+
+/* Independent register (IDR) access (write/read) *****************************/
+void CRC_SetIDRegister(uint8_t CRC_IDValue);
+uint8_t CRC_GetIDRegister(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F30x_CRC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_dac.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,764 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_dac.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Digital-to-Analog Converter (DAC) peripheral:
+ * + DAC channels configuration: trigger, output buffer, data format
+ * + DMA management
+ * + Interrupts and flags management
+ *
+ @verbatim
+
+ ===============================================================================
+ ##### DAC Peripheral features #####
+ ===============================================================================
+ [..] The device integrates two 12-bit Digital Analog Converters that can
+ be used independently or simultaneously (dual mode):
+ (#) DAC1 integrates two DAC channels:
+ (++) DAC1 channel 1 with DAC1_OUT1 as output
+ (++) DAC1 channel 2 with DAC1_OUT2 as output
+ (++) The two channels can be used independently or simultaneously (dual mode)
+
+ (#) DAC2 integrates only one channel DAC2 channel 1 with DAC2_OUT1 as output
+
+ [..] Digital to Analog conversion can be non-triggered using DAC_Trigger_None
+ and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register using
+ DAC_SetChannel1Data()/DAC_SetChannel2Data.
+
+ [..] Digital to Analog conversion can be triggered by:
+ (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
+ The used pin (GPIOx_Pin9) must be configured in input mode.
+
+ (#) Timers TRGO: TIM2, TIM8/TIM3, TIM4, TIM6, TIM7, and TIM15
+ (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...)
+ The timer TRGO event should be selected using TIM_SelectOutputTrigger()
+ (++) To trigger DAC conversions by TIM3 instead of TIM8 follow
+ this sequence:
+ (+++) Enable SYSCFG APB clock by calling
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+ (+++) Select DAC_Trigger_T3_TRGO when calling DAC_Init()
+ (+++) Remap the DAC trigger from TIM8 to TIM3 by calling
+ SYSCFG_TriggerRemapConfig(SYSCFG_TriggerRemap_DACTIM3, ENABLE)
+ (#) Software using DAC_Trigger_Software
+
+ [..] Each DAC channel integrates an output buffer that can be used to
+ reduce the output impedance, and to drive external loads directly
+ without having to add an external operational amplifier.
+ To enable, the output buffer use
+ DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+
+ [..] Refer to the device datasheet for more details about output impedance
+ value with and without output buffer.
+
+ [..] Both DAC channels can be used to generate:
+ (+) Noise wave using DAC_WaveGeneration_Noise
+ (+) Triangle wave using DAC_WaveGeneration_Triangle
+
+ [..] Wave generation can be disabled using DAC_WaveGeneration_None
+
+ [..] The DAC data format can be:
+ (+) 8-bit right alignment using DAC_Align_8b_R
+ (+) 12-bit left alignment using DAC_Align_12b_L
+ (+) 12-bit right alignment using DAC_Align_12b_R
+
+ [..] The analog output voltage on each DAC channel pin is determined
+ by the following equation:
+ (+) DAC_OUTx = VREF+ * DOR / 4095 with DOR is the Data Output Register.
+ VREF+ is the input voltage reference (refer to the device datasheet)
+ e.g. To set DAC_OUT1 to 0.7V, use DAC_SetChannel1Data(DAC_Align_12b_R, 868);
+ Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
+
+ [..] A DMA1 request can be generated when an external trigger (but not
+ a software trigger) occurs if DMA1 requests are enabled using
+ DAC_DMACmd()
+ DMA1 requests are mapped as following:
+ (+) DAC channel1 is mapped on DMA1 channel3 which must be already
+ configured
+ (+) DAC channel2 is mapped on DMA1 channel4 which must be already
+ configured
+
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ (+) Enable DAC APB1 clock to get write access to DAC registers
+ using RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)
+
+ (+) Configure DACx_OUTy (DAC1_OUT1: PA4, DAC1_OUT2: PA5, DAC2_OUT1: PA6)
+ in analog mode.
+
+ (+) Configure the DAC channel using DAC_Init()
+
+ (+) Enable the DAC channel using DAC_Cmd()
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_dac.h"
+#include "stm32f30x_rcc.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup DAC
+ * @brief DAC driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* CR register Mask */
+#define CR_CLEAR_MASK ((uint32_t)0x00000FFE)
+
+/* DAC Dual Channels SWTRIG masks */
+#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)
+#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)
+
+/* DHR registers offsets */
+#define DHR12R1_OFFSET ((uint32_t)0x00000008)
+#define DHR12R2_OFFSET ((uint32_t)0x00000014)
+#define DHR12RD_OFFSET ((uint32_t)0x00000020)
+
+/* DOR register offset */
+#define DOR_OFFSET ((uint32_t)0x0000002C)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DAC_Private_Functions
+ * @{
+ */
+
+/** @defgroup DAC_Group1 DAC channels configuration
+ * @brief DAC channels configuration: trigger, output buffer, data format
+ *
+@verbatim
+ ===============================================================================
+ ##### DAC channels configuration: trigger, output buffer, data format #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the DAC peripheral registers to their default reset values.
+ * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
+ * @retval None
+ */
+void DAC_DeInit(DAC_TypeDef* DACx)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_PERIPH(DACx));
+
+ if (DACx == DAC1)
+ {
+ /* Enable DAC1 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC1, ENABLE);
+ /* Release DAC1 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC1, DISABLE);
+ }
+ else
+ {
+ /* Enable DAC2 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC2, ENABLE);
+ /* Release DAC2 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC2, DISABLE);
+ }
+}
+
+/**
+ * @brief Initializes the DAC peripheral according to the specified
+ * parameters in the DAC_InitStruct.
+ * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
+ * contains the configuration information for the specified DAC channel.
+ * @retval None
+ */
+void DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;
+
+ /* Check the DAC parameters */
+ assert_param(IS_DAC_ALL_PERIPH(DACx));
+ assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
+ assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
+ assert_param(IS_DAC_BUFFER_SWITCH_STATE(DAC_InitStruct->DAC_Buffer_Switch));
+
+/*---------------------------- DAC CR Configuration --------------------------*/
+ /* Get the DAC CR value */
+ tmpreg1 = DACx->CR;
+ /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
+ tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
+ /* Configure for the selected DAC channel: buffer output, trigger, wave generation,
+ mask/amplitude for wave generation */
+
+ /* Set TSELx and TENx bits according to DAC_Trigger value */
+ /* Set WAVEx bits according to DAC_WaveGeneration value */
+ /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
+ /* Set BOFFx OUTENx bit according to DAC_Buffer_Switch value */
+ tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
+ DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_Buffer_Switch);
+
+ /* Calculate CR register value depending on DAC_Channel */
+ tmpreg1 |= tmpreg2 << DAC_Channel;
+ /* Write to DAC CR */
+ DACx->CR = tmpreg1;
+}
+
+/**
+ * @brief Fills each DAC_InitStruct member with its default value.
+ * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
+{
+/*--------------- Reset DAC init structure parameters values -----------------*/
+ /* Initialize the DAC_Trigger member */
+ DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
+ /* Initialize the DAC_WaveGeneration member */
+ DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
+ /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
+ DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
+ /* Initialize the DAC_Buffer_Switch member */
+ DAC_InitStruct->DAC_Buffer_Switch = DAC_BufferSwitch_Enable;
+}
+
+/**
+ * @brief Enables or disables the specified DAC channel.
+ * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
+ * @param DAC_Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param NewState: new state of the DAC channel.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note When the DAC channel is enabled the trigger source can no more
+ * be modified.
+ * @retval None
+ */
+void DAC_Cmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_PERIPH(DACx));
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DAC channel */
+ DACx->CR |= (DAC_CR_EN1 << DAC_Channel);
+ }
+ else
+ {
+ /* Disable the selected DAC channel */
+ DACx->CR &= (~(DAC_CR_EN1 << DAC_Channel));
+ }
+}
+
+/**
+ * @brief Enables or disables the selected DAC channel software trigger.
+ * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param NewState: new state of the selected DAC channel software trigger.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DAC_SoftwareTriggerCmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_PERIPH(DACx));
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable software trigger for the selected DAC channel */
+ DACx->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
+ }
+ else
+ {
+ /* Disable software trigger for the selected DAC channel */
+ DACx->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
+ }
+}
+
+/**
+ * @brief Enables or disables simultaneously the two DAC channels software
+ * triggers.
+ * @param DACx: where x can be 1 to select the DAC1 peripheral.
+ * @note Dual trigger is not applicable for DAC2 (DAC2 integrates one channel).
+ * @param NewState: new state of the DAC channels software triggers.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DAC_DualSoftwareTriggerCmd(DAC_TypeDef* DACx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_LIST1_PERIPH(DACx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable software trigger for both DAC channels */
+ DACx->SWTRIGR |= DUAL_SWTRIG_SET;
+ }
+ else
+ {
+ /* Disable software trigger for both DAC channels */
+ DACx->SWTRIGR &= DUAL_SWTRIG_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the selected DAC channel wave generation.
+ * @param DACx: where x can be 1 to select the DAC1 peripheral.
+ * @note Wave generation is not available in DAC2.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param DAC_Wave: Specifies the wave type to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg DAC_Wave_Noise: noise wave generation
+ * @arg DAC_Wave_Triangle: triangle wave generation
+ * @param NewState: new state of the selected DAC channel wave generation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note
+ * @retval None
+ */
+void DAC_WaveGenerationCmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_LIST1_PERIPH(DACx));
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_DAC_WAVE(DAC_Wave));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected wave generation for the selected DAC channel */
+ DACx->CR |= DAC_Wave << DAC_Channel;
+ }
+ else
+ {
+ /* Disable the selected wave generation for the selected DAC channel */
+ DACx->CR &= ~(DAC_Wave << DAC_Channel);
+ }
+}
+
+/**
+ * @brief Set the specified data holding register value for DAC channel1.
+ * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
+ * @param DAC_Align: Specifies the data alignment for DAC channel1.
+ * This parameter can be one of the following values:
+ * @arg DAC_Align_8b_R: 8bit right data alignment selected
+ * @arg DAC_Align_12b_L: 12bit left data alignment selected
+ * @arg DAC_Align_12b_R: 12bit right data alignment selected
+ * @param Data: Data to be loaded in the selected data holding register.
+ * @retval None
+ */
+void DAC_SetChannel1Data(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_PERIPH(DACx));
+ assert_param(IS_DAC_ALIGN(DAC_Align));
+ assert_param(IS_DAC_DATA(Data));
+
+ tmp = (uint32_t)DACx;
+ tmp += DHR12R1_OFFSET + DAC_Align;
+
+ /* Set the DAC channel1 selected data holding register */
+ *(__IO uint32_t *) tmp = Data;
+}
+
+/**
+ * @brief Set the specified data holding register value for DAC channel2.
+ * @param DACx: where x can be 1 to select the DAC peripheral.
+ * @note This function is available only for DAC1.
+ * @param DAC_Align: Specifies the data alignment for DAC channel2.
+ * This parameter can be one of the following values:
+ * @arg DAC_Align_8b_R: 8bit right data alignment selected
+ * @arg DAC_Align_12b_L: 12bit left data alignment selected
+ * @arg DAC_Align_12b_R: 12bit right data alignment selected
+ * @param Data : Data to be loaded in the selected data holding register.
+ * @retval None
+ */
+void DAC_SetChannel2Data(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_LIST1_PERIPH(DACx));
+ assert_param(IS_DAC_ALIGN(DAC_Align));
+ assert_param(IS_DAC_DATA(Data));
+
+ tmp = (uint32_t)DACx;
+ tmp += DHR12R2_OFFSET + DAC_Align;
+
+ /* Set the DAC channel2 selected data holding register */
+ *(__IO uint32_t *)tmp = Data;
+}
+
+/**
+ * @brief Set the specified data holding register value for dual channel DAC.
+ * @param DACx: where x can be 1 to select the DAC peripheral.
+ * @note This function isn't applicable for DAC2.
+ * @param DAC_Align: Specifies the data alignment for dual channel DAC.
+ * This parameter can be one of the following values:
+ * @arg DAC_Align_8b_R: 8bit right data alignment selected
+ * @arg DAC_Align_12b_L: 12bit left data alignment selected
+ * @arg DAC_Align_12b_R: 12bit right data alignment selected
+ * @param Data2: Data for DAC Channel2 to be loaded in the selected data
+ * holding register.
+ * @param Data1: Data for DAC Channel1 to be loaded in the selected data
+ * holding register.
+ * @note In dual mode, a unique register access is required to write in both
+ * DAC channels at the same time.
+ * @retval None
+ */
+void DAC_SetDualChannelData(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
+{
+ uint32_t data = 0, tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_LIST1_PERIPH(DACx));
+ assert_param(IS_DAC_ALIGN(DAC_Align));
+ assert_param(IS_DAC_DATA(Data1));
+ assert_param(IS_DAC_DATA(Data2));
+
+ /* Calculate and set dual DAC data holding register value */
+ if (DAC_Align == DAC_Align_8b_R)
+ {
+ data = ((uint32_t)Data2 << 8) | Data1;
+ }
+ else
+ {
+ data = ((uint32_t)Data2 << 16) | Data1;
+ }
+
+ tmp = (uint32_t)DACx;
+ tmp += DHR12RD_OFFSET + DAC_Align;
+
+ /* Set the dual DAC selected data holding register */
+ *(__IO uint32_t *)tmp = data;
+}
+
+/**
+ * @brief Returns the last data output value of the selected DAC channel.
+ * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @retval The selected DAC channel data output value.
+ */
+uint16_t DAC_GetDataOutputValue(DAC_TypeDef* DACx, uint32_t DAC_Channel)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_PERIPH(DACx));
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+
+ tmp = (uint32_t) DACx;
+ tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
+
+ /* Returns the DAC channel data output register value */
+ return (uint16_t) (*(__IO uint32_t*) tmp);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Group2 DMA management functions
+ * @brief DMA management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### DMA management functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the specified DAC channel DMA request.
+ * When enabled DMA1 is generated when an external trigger (EXTI Line9,
+ * TIM2, TIM4, TIM6, TIM7 or TIM9 but not a software trigger) occurs
+ * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param NewState: new state of the selected DAC channel DMA request.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note The DAC channel1 (channel2) is mapped on DMA1 channel3 (channel4) which
+ * must be already configured.
+ * @retval None
+ */
+void DAC_DMACmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_PERIPH(DACx));
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DAC channel DMA request */
+ DACx->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
+ }
+ else
+ {
+ /* Disable the selected DAC channel DMA request */
+ DACx->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Group3 Interrupts and flags management functions
+ * @brief Interrupts and flags management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupts and flags management functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the specified DAC interrupts.
+ * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
+ * @note The DMA underrun occurs when a second external trigger arrives before
+ * the acknowledgement for the first external trigger is received (first request).
+ * @param NewState: new state of the specified DAC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DAC_ITConfig(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_PERIPH(DACx));
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_DAC_IT(DAC_IT));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DAC interrupts */
+ DACx->CR |= (DAC_IT << DAC_Channel);
+ }
+ else
+ {
+ /* Disable the selected DAC interrupts */
+ DACx->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
+ }
+}
+
+/**
+ * @brief Checks whether the specified DAC flag is set or not.
+ * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
+ * @param DAC_Channel: thee selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param DAC_FLAG: specifies the flag to check.
+ * This parameter can be:
+ * @arg DAC_FLAG_DMAUDR: DMA underrun flag
+ * @note The DMA underrun occurs when a second external trigger arrives before
+ * the acknowledgement for the first external trigger is received (first request).
+ * @retval The new state of DAC_FLAG (SET or RESET).
+ */
+FlagStatus DAC_GetFlagStatus(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_PERIPH(DACx));
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_DAC_FLAG(DAC_FLAG));
+
+ /* Check the status of the specified DAC flag */
+ if ((DACx->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
+ {
+ /* DAC_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* DAC_FLAG is reset */
+ bitstatus = RESET;
+ }
+ /* Return the DAC_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the DAC channel's pending flags.
+ * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param DAC_FLAG: specifies the flag to clear.
+ * This parameter can be:
+ * @arg DAC_FLAG_DMAUDR: DMA underrun flag
+ * @retval None
+ */
+void DAC_ClearFlag(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_PERIPH(DACx));
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_DAC_FLAG(DAC_FLAG));
+
+ /* Clear the selected DAC flags */
+ DACx->SR = (DAC_FLAG << DAC_Channel);
+}
+
+/**
+ * @brief Checks whether the specified DAC interrupt has occurred or not.
+ * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param DAC_IT: specifies the DAC interrupt source to check.
+ * This parameter can be:
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
+ * @note The DMA underrun occurs when a second external trigger arrives before
+ * the acknowledgement for the first external trigger is received (first request).
+ * @retval The new state of DAC_IT (SET or RESET).
+ */
+ITStatus DAC_GetITStatus(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint32_t enablestatus = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_PERIPH(DACx));
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_DAC_IT(DAC_IT));
+
+ /* Get the DAC_IT enable bit status */
+ enablestatus = (DACx->CR & (DAC_IT << DAC_Channel)) ;
+
+ /* Check the status of the specified DAC interrupt */
+ if (((DACx->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
+ {
+ /* DAC_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* DAC_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the DAC_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the DAC channel's interrupt pending bits.
+ * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param DAC_IT: specifies the DAC interrupt pending bit to clear.
+ * This parameter can be the following values:
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
+ * @retval None
+ */
+void DAC_ClearITPendingBit(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_PERIPH(DACx));
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_DAC_IT(DAC_IT));
+
+ /* Clear the selected DAC interrupt pending bits */
+ DACx->SR = (DAC_IT << DAC_Channel);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_dac.h Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,332 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_dac.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the DAC firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_DAC_H
+#define __STM32F30x_DAC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DAC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+#define DAC_CR_DMAUDRIE ((uint32_t)0x00002000) /*!< DAC channel DMA underrun interrupt enable */
+
+/**
+ * @brief DAC Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
+ This parameter can be a value of @ref DAC_trigger_selection */
+
+ uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
+ are generated, or whether no wave is generated.
+ This parameter can be a value of @ref DAC_wave_generation */
+
+ uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
+ the maximum amplitude triangle generation for the DAC channel.
+ This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
+
+ uint32_t DAC_Buffer_Switch; /*!< Specifies whether the DAC channel output buffer is enabled or disabled or
+ the DAC channel output switch is enabled or disabled.
+ This parameter can be a value of @ref DAC_buffer_switch */
+}DAC_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Constants
+ * @{
+ */
+
+#define IS_DAC_ALL_PERIPH(PERIPH) (((PERIPH) == DAC1) || \
+ ((PERIPH) == DAC2))
+
+#define IS_DAC_LIST1_PERIPH(PERIPH) (((PERIPH) == DAC1))
+
+/** @defgroup DAC_trigger_selection
+ * @{
+ */
+
+#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+ has been loaded, and not by external trigger */
+#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
+#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM3 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
+#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC1 channel1/2 */
+#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
+#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
+#define DAC_Trigger_HRTIM1_DACTRG1 ((uint32_t)0x0000001C) /*!< HRTIM1 DACTRG1 selected as external conversion trigger for DAC1 channel1/2 */
+#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
+#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_HRTIM1_DACTRG2 ((uint32_t)0x0000002C) /*!< HRTIM1 DACTRG2 selected as external conversion trigger for DAC1 channel1/2 */
+#define DAC_Trigger_HRTIM1_DACTRG3 ((uint32_t)0x0000002C) /*!< HRTIM1 DACTRG3 selected as external conversion trigger for DAC2 channel1 */
+#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC1/2 channel1/2 */
+#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC1/2 channel1/2 */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
+ ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T3_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T8_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T15_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_HRTIM1_DACTRG1)|| \
+ ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_HRTIM1_DACTRG2)|| \
+ ((TRIGGER) == DAC_Trigger_HRTIM1_DACTRG3)|| \
+ ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
+ ((TRIGGER) == DAC_Trigger_Software))
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_wave_generation
+ * @{
+ */
+
+#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
+#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
+#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
+
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
+ ((WAVE) == DAC_WaveGeneration_Noise) || \
+ ((WAVE) == DAC_WaveGeneration_Triangle))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_lfsrunmask_triangleamplitude
+ * @{
+ */
+
+#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
+#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
+#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
+#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
+#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
+#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
+#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
+#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
+#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
+ ((VALUE) == DAC_TriangleAmplitude_1) || \
+ ((VALUE) == DAC_TriangleAmplitude_3) || \
+ ((VALUE) == DAC_TriangleAmplitude_7) || \
+ ((VALUE) == DAC_TriangleAmplitude_15) || \
+ ((VALUE) == DAC_TriangleAmplitude_31) || \
+ ((VALUE) == DAC_TriangleAmplitude_63) || \
+ ((VALUE) == DAC_TriangleAmplitude_127) || \
+ ((VALUE) == DAC_TriangleAmplitude_255) || \
+ ((VALUE) == DAC_TriangleAmplitude_511) || \
+ ((VALUE) == DAC_TriangleAmplitude_1023) || \
+ ((VALUE) == DAC_TriangleAmplitude_2047) || \
+ ((VALUE) == DAC_TriangleAmplitude_4095))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_buffer_switch
+ * @{
+ */
+
+#define DAC_BufferSwitch_Disable ((uint32_t)0x00000000)
+#define DAC_BufferSwitch_Enable ((uint32_t)0x00000002)
+
+#define IS_DAC_BUFFER_SWITCH_STATE(STATE) (((STATE) == DAC_BufferSwitch_Enable) || \
+ ((STATE) == DAC_BufferSwitch_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Channel_selection
+ * @{
+ */
+#define DAC_Channel_1 ((uint32_t)0x00000000)
+#define DAC_Channel_2 ((uint32_t)0x00000010)
+
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
+ ((CHANNEL) == DAC_Channel_2))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_data_alignement
+ * @{
+ */
+
+#define DAC_Align_12b_R ((uint32_t)0x00000000)
+#define DAC_Align_12b_L ((uint32_t)0x00000004)
+#define DAC_Align_8b_R ((uint32_t)0x00000008)
+
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
+ ((ALIGN) == DAC_Align_12b_L) || \
+ ((ALIGN) == DAC_Align_8b_R))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_wave_generation
+ * @{
+ */
+
+#define DAC_Wave_Noise ((uint32_t)0x00000040)
+#define DAC_Wave_Triangle ((uint32_t)0x00000080)
+
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
+ ((WAVE) == DAC_Wave_Triangle))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_data
+ * @{
+ */
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
+/**
+ * @}
+ */
+
+/** @defgroup DAC_interrupts_definition
+ * @{
+ */
+#define DAC_IT_DMAUDR ((uint32_t)0x00002000)
+#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_flags_definition
+ * @{
+ */
+
+#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000)
+#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* Function used to set the DAC configuration to the default reset state *****/
+void DAC_DeInit(DAC_TypeDef* DACx);
+
+/* DAC channels configuration: trigger, output buffer, data format functions */
+void DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
+void DAC_Cmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_SoftwareTriggerCmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_DualSoftwareTriggerCmd(DAC_TypeDef* DACx, FunctionalState NewState);
+void DAC_WaveGenerationCmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
+void DAC_SetChannel1Data(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data);
+void DAC_SetChannel2Data(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data);
+void DAC_SetDualChannelData(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
+uint16_t DAC_GetDataOutputValue(DAC_TypeDef* DACx, uint32_t DAC_Channel);
+
+/* DMA management functions ***************************************************/
+void DAC_DMACmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void DAC_ITConfig(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
+FlagStatus DAC_GetFlagStatus(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_FLAG);
+void DAC_ClearFlag(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_FLAG);
+ITStatus DAC_GetITStatus(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT);
+void DAC_ClearITPendingBit(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F30x_DAC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_dbgmcu.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,223 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_dbgmcu.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Debug MCU (DBGMCU) peripheral:
+ * + Device and Revision ID management
+ * + Peripherals Configuration
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_dbgmcu.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup DBGMCU
+ * @brief DBGMCU driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DBGMCU_Private_Functions
+ * @{
+ */
+
+/** @defgroup DBGMCU_Group1 Device and Revision ID management functions
+ * @brief Device and Revision ID management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Device and Revision ID management functions #####
+ ==============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the device revision identifier.
+ * @param None
+ * @retval Device revision identifier
+ */
+uint32_t DBGMCU_GetREVID(void)
+{
+ return(DBGMCU->IDCODE >> 16);
+}
+
+/**
+ * @brief Returns the device identifier.
+ * @param None
+ * @retval Device identifier
+ */
+uint32_t DBGMCU_GetDEVID(void)
+{
+ return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Group2 Peripherals Configuration functions
+ * @brief Peripherals Configuration
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripherals Configuration functions #####
+ ==============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures low power mode behavior when the MCU is in Debug mode.
+ * @param DBGMCU_Periph: specifies the low power mode.
+ * This parameter can be any combination of the following values:
+ * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode.
+ * @arg DBGMCU_STOP: Keep debugger connection during STOP mode.
+ * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode.
+ * @param NewState: new state of the specified low power mode in Debug mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ DBGMCU->CR |= DBGMCU_Periph;
+ }
+ else
+ {
+ DBGMCU->CR &= ~DBGMCU_Periph;
+ }
+}
+
+/**
+ * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode.
+ * @param DBGMCU_Periph: specifies the APB1 peripheral.
+ * This parameter can be any combination of the following values:
+ * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted.
+ * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted.
+ * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted.
+ * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted.
+ * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted.
+ * @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter are stopped when
+ * Core is halted.
+ * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted.
+ * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted.
+ * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when
+ * Core is halted.
+ * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when
+ * Core is halted.
+ * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted.
+ * @param NewState: new state of the specified APB1 peripheral in Debug mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ DBGMCU->APB1FZ |= DBGMCU_Periph;
+ }
+ else
+ {
+ DBGMCU->APB1FZ &= ~DBGMCU_Periph;
+ }
+}
+
+/**
+ * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode.
+ * @param DBGMCU_Periph: specifies the APB2 peripheral.
+ * This parameter can be any combination of the following values:
+ * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted.
+ * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted.
+ * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted.
+ * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted.
+ * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted.
+ * @param NewState: new state of the specified APB2 peripheral in Debug mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ DBGMCU->APB2FZ |= DBGMCU_Periph;
+ }
+ else
+ {
+ DBGMCU->APB2FZ &= ~DBGMCU_Periph;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_dbgmcu.h Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,118 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_dbgmcu.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the DBGMCU firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_DBGMCU_H
+#define __STM32F30x_DBGMCU_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DBGMCU
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DBGMCU_Exported_Constants
+ * @{
+ */
+#define DBGMCU_SLEEP ((uint32_t)0x00000001)
+#define DBGMCU_STOP ((uint32_t)0x00000002)
+#define DBGMCU_STANDBY ((uint32_t)0x00000004)
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))
+
+#define DBGMCU_TIM2_STOP ((uint32_t)0x00000001)
+#define DBGMCU_TIM3_STOP ((uint32_t)0x00000002)
+#define DBGMCU_TIM4_STOP ((uint32_t)0x00000004)
+#define DBGMCU_TIM6_STOP ((uint32_t)0x00000010)
+#define DBGMCU_TIM7_STOP ((uint32_t)0x00000020)
+#define DBGMCU_RTC_STOP ((uint32_t)0x00000400)
+#define DBGMCU_WWDG_STOP ((uint32_t)0x00000800)
+#define DBGMCU_IWDG_STOP ((uint32_t)0x00001000)
+#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
+#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
+#define DBGMCU_CAN1_STOP ((uint32_t)0x02000000)
+
+#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFD9FE3C8) == 0x00) && ((PERIPH) != 0x00))
+
+#define DBGMCU_TIM1_STOP ((uint32_t)0x00000001)
+#define DBGMCU_TIM8_STOP ((uint32_t)0x00000002)
+#define DBGMCU_TIM15_STOP ((uint32_t)0x00000004)
+#define DBGMCU_TIM16_STOP ((uint32_t)0x00000008)
+#define DBGMCU_TIM17_STOP ((uint32_t)0x00000010)
+#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFE0) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/* Device and Revision ID management functions ********************************/
+uint32_t DBGMCU_GetREVID(void);
+uint32_t DBGMCU_GetDEVID(void);
+
+/* Peripherals Configuration functions ****************************************/
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
+void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
+void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F30x_DBGMCU_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_dma.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,876 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_dma.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Direct Memory Access controller (DMA):
+ * + Initialization and Configuration
+ * + Data Counter
+ * + Interrupts and flags management
+ *
+ @verbatim
+
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ (#) Enable The DMA controller clock using
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE) function for DMA1 or
+ using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE) function for DMA2.
+ (#) Enable and configure the peripheral to be connected to the DMA channel
+ (except for internal SRAM / FLASH memories: no initialization is necessary).
+ (#) For a given Channel, program the Source and Destination addresses,
+ the transfer Direction, the Buffer Size, the Peripheral and Memory
+ Incrementation mode and Data Size, the Circular or Normal mode,
+ the channel transfer Priority and the Memory-to-Memory transfer
+ mode (if needed) using the DMA_Init() function.
+ (#) Enable the NVIC and the corresponding interrupt(s) using the function
+ DMA_ITConfig() if you need to use DMA interrupts.
+ (#) Enable the DMA channel using the DMA_Cmd() function.
+ (#) Activate the needed channel Request using PPP_DMACmd() function for
+ any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...)
+ The function allowing this operation is provided in each PPP peripheral
+ driver (ie. SPI_DMACmd for SPI peripheral).
+ (#) Optionally, you can configure the number of data to be transferred
+ when the channel is disabled (ie. after each Transfer Complete event
+ or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().
+ And you can get the number of remaining data to be transferred using
+ the function DMA_GetCurrDataCounter() at run time (when the DMA channel is
+ enabled and running).
+ (#) To control DMA events you can use one of the following two methods:
+ (##) Check on DMA channel flags using the function DMA_GetFlagStatus().
+ (##) Use DMA interrupts through the function DMA_ITConfig() at initialization
+ phase and DMA_GetITStatus() function into interrupt routines in
+ communication phase.
+ After checking on a flag you should clear it using DMA_ClearFlag()
+ function. And after checking on an interrupt event you should
+ clear it using DMA_ClearITPendingBit() function.
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_dma.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup DMA
+ * @brief DMA driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F) /* DMA Channel config registers Masks */
+#define FLAG_Mask ((uint32_t)0x10000000) /* DMA2 FLAG mask */
+
+
+/* DMA1 Channelx interrupt pending bit masks */
+#define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
+#define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
+#define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
+#define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
+#define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
+#define DMA1_CHANNEL6_IT_MASK ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
+#define DMA1_CHANNEL7_IT_MASK ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
+
+/* DMA2 Channelx interrupt pending bit masks */
+#define DMA2_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
+#define DMA2_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
+#define DMA2_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
+#define DMA2_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
+#define DMA2_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DMA_Private_Functions
+ * @{
+ */
+
+/** @defgroup DMA_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..] This subsection provides functions allowing to initialize the DMA channel
+ source and destination addresses, incrementation and data sizes, transfer
+ direction, buffer size, circular/normal mode selection, memory-to-memory
+ mode selection and channel priority value.
+ [..] The DMA_Init() function follows the DMA configuration procedures as described
+ in reference manual (RM00316).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the DMAy Channelx registers to their default reset
+ * values.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @retval None
+ */
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+
+ /* Disable the selected DMAy Channelx */
+ DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
+
+ /* Reset DMAy Channelx control register */
+ DMAy_Channelx->CCR = 0;
+
+ /* Reset DMAy Channelx remaining bytes register */
+ DMAy_Channelx->CNDTR = 0;
+
+ /* Reset DMAy Channelx peripheral address register */
+ DMAy_Channelx->CPAR = 0;
+
+ /* Reset DMAy Channelx memory address register */
+ DMAy_Channelx->CMAR = 0;
+
+ if (DMAy_Channelx == DMA1_Channel1)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel1 */
+ DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK;
+ }
+ else if (DMAy_Channelx == DMA1_Channel2)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel2 */
+ DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK;
+ }
+ else if (DMAy_Channelx == DMA1_Channel3)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel3 */
+ DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK;
+ }
+ else if (DMAy_Channelx == DMA1_Channel4)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel4 */
+ DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK;
+ }
+ else if (DMAy_Channelx == DMA1_Channel5)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel5 */
+ DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK;
+ }
+ else if (DMAy_Channelx == DMA1_Channel6)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel6 */
+ DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK;
+ }
+ else if (DMAy_Channelx == DMA1_Channel7)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel7 */
+ DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK;
+ }
+ else if (DMAy_Channelx == DMA2_Channel1)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel1 */
+ DMA2->IFCR |= DMA2_CHANNEL1_IT_MASK;
+ }
+ else if (DMAy_Channelx == DMA2_Channel2)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel2 */
+ DMA2->IFCR |= DMA2_CHANNEL2_IT_MASK;
+ }
+ else if (DMAy_Channelx == DMA2_Channel3)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel3 */
+ DMA2->IFCR |= DMA2_CHANNEL3_IT_MASK;
+ }
+ else if (DMAy_Channelx == DMA2_Channel4)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel4 */
+ DMA2->IFCR |= DMA2_CHANNEL4_IT_MASK;
+ }
+ else
+ {
+ if (DMAy_Channelx == DMA2_Channel5)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel5 */
+ DMA2->IFCR |= DMA2_CHANNEL5_IT_MASK;
+ }
+ }
+}
+
+/**
+ * @brief Initializes the DMAy Channelx according to the specified parameters
+ * in the DMA_InitStruct.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval None
+ */
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+ assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
+ assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
+ assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
+ assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
+ assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
+ assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
+ assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
+ assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
+
+/*--------------------------- DMAy Channelx CCR Configuration ----------------*/
+ /* Get the DMAy_Channelx CCR value */
+ tmpreg = DMAy_Channelx->CCR;
+
+ /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
+ tmpreg &= CCR_CLEAR_MASK;
+
+ /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
+ /* Set DIR bit according to DMA_DIR value */
+ /* Set CIRC bit according to DMA_Mode value */
+ /* Set PINC bit according to DMA_PeripheralInc value */
+ /* Set MINC bit according to DMA_MemoryInc value */
+ /* Set PSIZE bits according to DMA_PeripheralDataSize value */
+ /* Set MSIZE bits according to DMA_MemoryDataSize value */
+ /* Set PL bits according to DMA_Priority value */
+ /* Set the MEM2MEM bit according to DMA_M2M value */
+ tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
+ DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
+ DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
+ DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
+
+ /* Write to DMAy Channelx CCR */
+ DMAy_Channelx->CCR = tmpreg;
+
+/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
+ /* Write to DMAy Channelx CNDTR */
+ DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
+
+/*--------------------------- DMAy Channelx CPAR Configuration ---------------*/
+ /* Write to DMAy Channelx CPAR */
+ DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
+
+/*--------------------------- DMAy Channelx CMAR Configuration ---------------*/
+ /* Write to DMAy Channelx CMAR */
+ DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
+}
+
+/**
+ * @brief Fills each DMA_InitStruct member with its default value.
+ * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
+{
+/*-------------- Reset DMA init structure parameters values ------------------*/
+ /* Initialize the DMA_PeripheralBaseAddr member */
+ DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
+ /* Initialize the DMA_MemoryBaseAddr member */
+ DMA_InitStruct->DMA_MemoryBaseAddr = 0;
+ /* Initialize the DMA_DIR member */
+ DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
+ /* Initialize the DMA_BufferSize member */
+ DMA_InitStruct->DMA_BufferSize = 0;
+ /* Initialize the DMA_PeripheralInc member */
+ DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+ /* Initialize the DMA_MemoryInc member */
+ DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
+ /* Initialize the DMA_PeripheralDataSize member */
+ DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+ /* Initialize the DMA_MemoryDataSize member */
+ DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
+ /* Initialize the DMA_Mode member */
+ DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
+ /* Initialize the DMA_Priority member */
+ DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
+ /* Initialize the DMA_M2M member */
+ DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
+}
+
+/**
+ * @brief Enables or disables the specified DMAy Channelx.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @param NewState: new state of the DMAy Channelx.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DMAy Channelx */
+ DMAy_Channelx->CCR |= DMA_CCR_EN;
+ }
+ else
+ {
+ /* Disable the selected DMAy Channelx */
+ DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Group2 Data Counter functions
+ * @brief Data Counter functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Data Counter functions #####
+ ===============================================================================
+ [..] This subsection provides function allowing to configure and read the buffer
+ size (number of data to be transferred).The DMA data counter can be written
+ only when the DMA channel is disabled (ie. after transfer complete event).
+ [..] The following function can be used to write the Channel data counter value:
+ (+) void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber).
+ [..]
+ (@) It is advised to use this function rather than DMA_Init() in situations
+ where only the Data buffer needs to be reloaded.
+ [..] The DMA data counter can be read to indicate the number of remaining transfers
+ for the relative DMA channel. This counter is decremented at the end of each
+ data transfer and when the transfer is complete:
+ (+) If Normal mode is selected: the counter is set to 0.
+ (+) If Circular mode is selected: the counter is reloaded with the initial
+ value(configured before enabling the DMA channel).
+ [..] The following function can be used to read the Channel data counter value:
+ (+) uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Sets the number of data units in the current DMAy Channelx transfer.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @param DataNumber: The number of data units in the current DMAy Channelx
+ * transfer.
+ * @note This function can only be used when the DMAy_Channelx is disabled.
+ * @retval None.
+ */
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+
+/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
+ /* Write to DMAy Channelx CNDTR */
+ DMAy_Channelx->CNDTR = DataNumber;
+}
+
+/**
+ * @brief Returns the number of remaining data units in the current
+ * DMAy Channelx transfer.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @retval The number of remaining data units in the current DMAy Channelx
+ * transfer.
+ */
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+ /* Return the number of remaining data units for DMAy Channelx */
+ return ((uint16_t)(DMAy_Channelx->CNDTR));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Group3 Interrupts and flags management functions
+ * @brief Interrupts and flags management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupts and flags management functions #####
+ ===============================================================================
+ [..] This subsection provides functions allowing to configure the DMA Interrupt
+ sources and check or clear the flags or pending bits status.
+ The user should identify which mode will be used in his application to manage
+ the DMA controller events: Polling mode or Interrupt mode.
+
+ *** Polling Mode ***
+ ====================
+ [..] Each DMA channel can be managed through 4 event Flags (y : DMA Controller
+ number, x : DMA channel number):
+ (#) DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred.
+ (#) DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occurred.
+ (#) DMAy_FLAG_TEx : to indicate that a Transfer Error occurred.
+ (#) DMAy_FLAG_GLx : to indicate that at least one of the events described
+ above occurred.
+ [..]
+ (@) Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the
+ same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
+ [..] In this Mode it is advised to use the following functions:
+ (+) FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
+ (+) void DMA_ClearFlag(uint32_t DMA_FLAG);
+
+ *** Interrupt Mode ***
+ ======================
+ [..] Each DMA channel can be managed through 4 Interrupts:
+ (+) Interrupt Source
+ (##) DMA_IT_TC: specifies the interrupt source for the Transfer Complete
+ event.
+ (##) DMA_IT_HT: specifies the interrupt source for the Half-transfer Complete
+ event.
+ (##) DMA_IT_TE: specifies the interrupt source for the transfer errors event.
+ (##) DMA_IT_GL: to indicate that at least one of the interrupts described
+ above occurred.
+ -@@- Clearing DMA_IT_GL interrupt results in clearing all other interrupts of
+ the same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE).
+ [..] In this Mode it is advised to use the following functions:
+ (+) void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
+ (+) ITStatus DMA_GetITStatus(uint32_t DMA_IT);
+ (+) void DMA_ClearITPendingBit(uint32_t DMA_IT);
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the specified DMAy Channelx interrupts.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @param DMA_IT: specifies the DMA interrupts sources to be enabled
+ * or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask
+ * @arg DMA_IT_HT: Half transfer interrupt mask
+ * @arg DMA_IT_TE: Transfer error interrupt mask
+ * @param NewState: new state of the specified DMA interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+ assert_param(IS_DMA_CONFIG_IT(DMA_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DMA interrupts */
+ DMAy_Channelx->CCR |= DMA_IT;
+ }
+ else
+ {
+ /* Disable the selected DMA interrupts */
+ DMAy_Channelx->CCR &= ~DMA_IT;
+ }
+}
+
+/**
+ * @brief Checks whether the specified DMAy Channelx flag is set or not.
+ * @param DMAy_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
+ * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
+ * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
+ * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
+ * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
+ * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
+ * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
+ * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
+ * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
+ * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
+ * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
+ * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
+ * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
+ * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
+ * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
+ * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
+ * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
+ * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
+ * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
+ * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
+ * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
+ * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
+ * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
+ * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
+ * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
+ * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
+ * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
+ * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
+ * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
+ * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
+ * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
+ * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
+ * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
+ * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
+ * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
+ * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
+ * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
+ * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
+ * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
+ * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
+ * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
+ * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
+ * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
+ * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
+ * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
+ * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
+ * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
+ * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
+ *
+ * @note
+ * The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags
+ * relative to the same channel is set (Transfer Complete, Half-transfer
+ * Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or
+ * DMAy_FLAG_TEx).
+ *
+ * @retval The new state of DMAy_FLAG (SET or RESET).
+ */
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
+
+ /* Calculate the used DMAy */
+ if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
+ {
+ /* Get DMA2 ISR register value */
+ tmpreg = DMA2->ISR ;
+ }
+ else
+ {
+ /* Get DMA1 ISR register value */
+ tmpreg = DMA1->ISR ;
+ }
+
+ /* Check the status of the specified DMAy flag */
+ if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
+ {
+ /* DMAy_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* DMAy_FLAG is reset */
+ bitstatus = RESET;
+ }
+
+ /* Return the DMAy_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the DMAy Channelx's pending flags.
+ * @param DMAy_FLAG: specifies the flag to clear.
+ * This parameter can be any combination (for the same DMA) of the following values:
+ * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
+ * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
+ * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
+ * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
+ * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
+ * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
+ * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
+ * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
+ * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
+ * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
+ * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
+ * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
+ * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
+ * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
+ * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
+ * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
+ * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
+ * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
+ * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
+ * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
+ * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
+ * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
+ * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
+ * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
+ * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
+ * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
+ * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
+ * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
+ * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
+ * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
+ * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
+ * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
+ * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
+ * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
+ * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
+ * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
+ * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
+ * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
+ * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
+ * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
+ * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
+ * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
+ * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
+ * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
+ * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
+ * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
+ * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
+ * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
+ *
+ * @note
+ * Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags
+ * relative to the same channel (Transfer Complete, Half-transfer Complete and
+ * Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
+ *
+ * @retval None
+ */
+void DMA_ClearFlag(uint32_t DMAy_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
+
+/* Calculate the used DMAy */
+ if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
+ {
+ /* Clear the selected DMAy flags */
+ DMA2->IFCR = DMAy_FLAG;
+ }
+ else
+ {
+ /* Clear the selected DMAy flags */
+ DMA1->IFCR = DMAy_FLAG;
+ }
+}
+
+/**
+ * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
+ * @param DMAy_IT: specifies the DMAy interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
+ * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
+ * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
+ * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
+ * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
+ * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
+ * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
+ * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
+ * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
+ * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
+ * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
+ * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
+ * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
+ * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
+ * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
+ * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
+ * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
+ * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
+ * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
+ * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
+ * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
+ * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
+ * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
+ * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
+ * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
+ * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
+ * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
+ * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
+ * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
+ * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
+ * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
+ * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
+ * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
+ * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
+ * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
+ * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
+ * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
+ * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
+ * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
+ * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
+ * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
+ * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
+ * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
+ * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
+ * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
+ * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
+ * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
+ * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
+ *
+ * @note
+ * The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other
+ * interrupts relative to the same channel is set (Transfer Complete,
+ * Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx,
+ * DMAy_IT_HTx or DMAy_IT_TEx).
+ *
+ * @retval The new state of DMAy_IT (SET or RESET).
+ */
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_GET_IT(DMAy_IT));
+
+ /* Calculate the used DMA */
+ if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
+ {
+ /* Get DMA2 ISR register value */
+ tmpreg = DMA2->ISR;
+ }
+ else
+ {
+ /* Get DMA1 ISR register value */
+ tmpreg = DMA1->ISR;
+ }
+
+ /* Check the status of the specified DMAy interrupt */
+ if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
+ {
+ /* DMAy_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* DMAy_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the DMAy_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the DMAy Channelx's interrupt pending bits.
+ * @param DMAy_IT: specifies the DMAy interrupt pending bit to clear.
+ * This parameter can be any combination (for the same DMA) of the following values:
+ * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
+ * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
+ * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
+ * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
+ * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
+ * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
+ * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
+ * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
+ * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
+ * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
+ * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
+ * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
+ * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
+ * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
+ * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
+ * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
+ * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
+ * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
+ * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
+ * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
+ * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
+ * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
+ * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
+ * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
+ * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
+ * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
+ * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
+ * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
+ * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
+ * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
+ * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
+ * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
+ * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
+ * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
+ * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
+ * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
+ * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
+ * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
+ * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
+ * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
+ * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
+ * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
+ * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
+ * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
+ * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
+ * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
+ * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
+ * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
+ *
+ * @note
+ * Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other
+ * interrupts relative to the same channel (Transfer Complete, Half-transfer
+ * Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and
+ * DMAy_IT_TEx).
+ *
+ * @retval None
+ */
+void DMA_ClearITPendingBit(uint32_t DMAy_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
+
+ /* Calculate the used DMAy */
+ if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
+ {
+ /* Clear the selected DMAy interrupt pending bits */
+ DMA2->IFCR = DMAy_IT;
+ }
+ else
+ {
+ /* Clear the selected DMAy interrupt pending bits */
+ DMA1->IFCR = DMAy_IT;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_dma.h Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,446 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_dma.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the DMA firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_DMA_H
+#define __STM32F30x_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief DMA Init structures definition
+ */
+typedef struct
+{
+ uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
+
+ uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
+
+ uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
+ This parameter can be a value of @ref DMA_data_transfer_direction */
+
+ uint16_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
+ The data unit is equal to the configuration set in DMA_PeripheralDataSize
+ or DMA_MemoryDataSize members depending in the transfer direction. */
+
+ uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
+ This parameter can be a value of @ref DMA_peripheral_incremented_mode */
+
+ uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
+ This parameter can be a value of @ref DMA_memory_incremented_mode */
+
+ uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
+ This parameter can be a value of @ref DMA_peripheral_data_size */
+
+ uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
+ This parameter can be a value of @ref DMA_memory_data_size */
+
+ uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
+ This parameter can be a value of @ref DMA_circular_normal_mode
+ @note: The circular buffer mode cannot be used if the memory-to-memory
+ data transfer is configured on the selected Channel */
+
+ uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
+ This parameter can be a value of @ref DMA_priority_level */
+
+ uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
+ This parameter can be a value of @ref DMA_memory_to_memory */
+}DMA_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants
+ * @{
+ */
+
+#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
+ ((PERIPH) == DMA1_Channel2) || \
+ ((PERIPH) == DMA1_Channel3) || \
+ ((PERIPH) == DMA1_Channel4) || \
+ ((PERIPH) == DMA1_Channel5) || \
+ ((PERIPH) == DMA1_Channel6) || \
+ ((PERIPH) == DMA1_Channel7) || \
+ ((PERIPH) == DMA2_Channel1) || \
+ ((PERIPH) == DMA2_Channel2) || \
+ ((PERIPH) == DMA2_Channel3) || \
+ ((PERIPH) == DMA2_Channel4) || \
+ ((PERIPH) == DMA2_Channel5))
+
+/** @defgroup DMA_data_transfer_direction
+ * @{
+ */
+
+#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
+#define DMA_DIR_PeripheralDST DMA_CCR_DIR
+
+#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \
+ ((DIR) == DMA_DIR_PeripheralDST))
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_peripheral_incremented_mode
+ * @{
+ */
+
+#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
+#define DMA_PeripheralInc_Enable DMA_CCR_PINC
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \
+ ((STATE) == DMA_PeripheralInc_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_memory_incremented_mode
+ * @{
+ */
+
+#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
+#define DMA_MemoryInc_Enable DMA_CCR_MINC
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \
+ ((STATE) == DMA_MemoryInc_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_peripheral_data_size
+ * @{
+ */
+
+#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
+#define DMA_PeripheralDataSize_HalfWord DMA_CCR_PSIZE_0
+#define DMA_PeripheralDataSize_Word DMA_CCR_PSIZE_1
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
+ ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
+ ((SIZE) == DMA_PeripheralDataSize_Word))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_memory_data_size
+ * @{
+ */
+
+#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
+#define DMA_MemoryDataSize_HalfWord DMA_CCR_MSIZE_0
+#define DMA_MemoryDataSize_Word DMA_CCR_MSIZE_1
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
+ ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
+ ((SIZE) == DMA_MemoryDataSize_Word))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_circular_normal_mode
+ * @{
+ */
+
+#define DMA_Mode_Normal ((uint32_t)0x00000000)
+#define DMA_Mode_Circular DMA_CCR_CIRC
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_priority_level
+ * @{
+ */
+
+#define DMA_Priority_VeryHigh DMA_CCR_PL
+#define DMA_Priority_High DMA_CCR_PL_1
+#define DMA_Priority_Medium DMA_CCR_PL_0
+#define DMA_Priority_Low ((uint32_t)0x00000000)
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
+ ((PRIORITY) == DMA_Priority_High) || \
+ ((PRIORITY) == DMA_Priority_Medium) || \
+ ((PRIORITY) == DMA_Priority_Low))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_memory_to_memory
+ * @{
+ */
+
+#define DMA_M2M_Disable ((uint32_t)0x00000000)
+#define DMA_M2M_Enable DMA_CCR_MEM2MEM
+
+#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable))
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_interrupts_definition
+ * @{
+ */
+
+#define DMA_IT_TC ((uint32_t)0x00000002)
+#define DMA_IT_HT ((uint32_t)0x00000004)
+#define DMA_IT_TE ((uint32_t)0x00000008)
+#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
+
+#define DMA1_IT_GL1 ((uint32_t)0x00000001)
+#define DMA1_IT_TC1 ((uint32_t)0x00000002)
+#define DMA1_IT_HT1 ((uint32_t)0x00000004)
+#define DMA1_IT_TE1 ((uint32_t)0x00000008)
+#define DMA1_IT_GL2 ((uint32_t)0x00000010)
+#define DMA1_IT_TC2 ((uint32_t)0x00000020)
+#define DMA1_IT_HT2 ((uint32_t)0x00000040)
+#define DMA1_IT_TE2 ((uint32_t)0x00000080)
+#define DMA1_IT_GL3 ((uint32_t)0x00000100)
+#define DMA1_IT_TC3 ((uint32_t)0x00000200)
+#define DMA1_IT_HT3 ((uint32_t)0x00000400)
+#define DMA1_IT_TE3 ((uint32_t)0x00000800)
+#define DMA1_IT_GL4 ((uint32_t)0x00001000)
+#define DMA1_IT_TC4 ((uint32_t)0x00002000)
+#define DMA1_IT_HT4 ((uint32_t)0x00004000)
+#define DMA1_IT_TE4 ((uint32_t)0x00008000)
+#define DMA1_IT_GL5 ((uint32_t)0x00010000)
+#define DMA1_IT_TC5 ((uint32_t)0x00020000)
+#define DMA1_IT_HT5 ((uint32_t)0x00040000)
+#define DMA1_IT_TE5 ((uint32_t)0x00080000)
+#define DMA1_IT_GL6 ((uint32_t)0x00100000)
+#define DMA1_IT_TC6 ((uint32_t)0x00200000)
+#define DMA1_IT_HT6 ((uint32_t)0x00400000)
+#define DMA1_IT_TE6 ((uint32_t)0x00800000)
+#define DMA1_IT_GL7 ((uint32_t)0x01000000)
+#define DMA1_IT_TC7 ((uint32_t)0x02000000)
+#define DMA1_IT_HT7 ((uint32_t)0x04000000)
+#define DMA1_IT_TE7 ((uint32_t)0x08000000)
+
+#define DMA2_IT_GL1 ((uint32_t)0x10000001)
+#define DMA2_IT_TC1 ((uint32_t)0x10000002)
+#define DMA2_IT_HT1 ((uint32_t)0x10000004)
+#define DMA2_IT_TE1 ((uint32_t)0x10000008)
+#define DMA2_IT_GL2 ((uint32_t)0x10000010)
+#define DMA2_IT_TC2 ((uint32_t)0x10000020)
+#define DMA2_IT_HT2 ((uint32_t)0x10000040)
+#define DMA2_IT_TE2 ((uint32_t)0x10000080)
+#define DMA2_IT_GL3 ((uint32_t)0x10000100)
+#define DMA2_IT_TC3 ((uint32_t)0x10000200)
+#define DMA2_IT_HT3 ((uint32_t)0x10000400)
+#define DMA2_IT_TE3 ((uint32_t)0x10000800)
+#define DMA2_IT_GL4 ((uint32_t)0x10001000)
+#define DMA2_IT_TC4 ((uint32_t)0x10002000)
+#define DMA2_IT_HT4 ((uint32_t)0x10004000)
+#define DMA2_IT_TE4 ((uint32_t)0x10008000)
+#define DMA2_IT_GL5 ((uint32_t)0x10010000)
+#define DMA2_IT_TC5 ((uint32_t)0x10020000)
+#define DMA2_IT_HT5 ((uint32_t)0x10040000)
+#define DMA2_IT_TE5 ((uint32_t)0x10080000)
+
+#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
+
+#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
+ ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
+ ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
+ ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
+ ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
+ ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
+ ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
+ ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
+ ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
+ ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
+ ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
+ ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
+ ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
+ ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
+ ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
+ ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
+ ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
+ ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
+ ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
+ ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
+ ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
+ ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
+ ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
+ ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_flags_definition
+ * @{
+ */
+
+#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
+#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
+#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
+#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
+#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
+#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
+#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
+#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
+#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
+#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
+#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
+#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
+#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
+#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
+#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
+#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
+#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
+#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
+#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
+#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
+#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
+#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
+#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
+#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
+#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
+#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
+#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
+#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
+
+#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
+#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
+#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
+#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
+#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
+#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
+#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
+#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
+#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
+#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
+#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
+#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
+#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
+#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
+#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
+#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
+#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
+#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
+#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
+#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
+
+#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
+
+#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
+ ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
+ ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
+ ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
+ ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
+ ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
+ ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
+ ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
+ ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
+ ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
+ ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
+ ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
+ ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
+ ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
+ ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
+ ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
+ ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
+ ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
+ ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
+ ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
+ ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
+ ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
+ ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
+ ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the DMA configuration to the default reset state ******/
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
+
+/* Initialization and Configuration functions *********************************/
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
+
+/* Data Counter functions******************************************************/
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
+
+/* Interrupts and flags management functions **********************************/
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
+void DMA_ClearFlag(uint32_t DMAy_FLAG);
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
+void DMA_ClearITPendingBit(uint32_t DMAy_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F30x_DMA_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_exti.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,359 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_exti.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the EXTI peripheral:
+ * + Initialization and Configuration
+ * + Interrupts and flags management
+ *
+ @verbatim
+ ===============================================================================
+ ##### EXTI features #####
+ ===============================================================================
+ [..] External interrupt/event lines are mapped as following:
+ (#) All available GPIO pins are connected to the 16 external
+ interrupt/event lines from EXTI0 to EXTI15.
+ (#) EXTI line 16 is connected to the PVD output
+ (#) EXTI line 17 is connected to the RTC Alarm event
+ (#) EXTI line 18 is connected to USB Device wakeup event
+ (#) EXTI line 19 is connected to the RTC Tamper and TimeStamp events
+ (#) EXTI line 20 is connected to the RTC wakeup event
+ (#) EXTI line 21 is connected to the Comparator 1 wakeup event
+ (#) EXTI line 22 is connected to the Comparator 2 wakeup event
+ (#) EXTI line 23 is connected to the I2C1 wakeup event
+ (#) EXTI line 24 is connected to the I2C2 wakeup event
+ (#) EXTI line 25 is connected to the USART1 wakeup event
+ (#) EXTI line 26 is connected to the USART2 wakeup event
+ (#) EXTI line 27 is reserved
+ (#) EXTI line 28 is connected to the USART3 wakeup event
+ (#) EXTI line 29 is connected to the Comparator 3 event
+ (#) EXTI line 30 is connected to the Comparator 4 event
+ (#) EXTI line 31 is connected to the Comparator 5 event
+ (#) EXTI line 32 is connected to the Comparator 6 event
+ (#) EXTI line 33 is connected to the Comparator 7 event
+ (#) EXTI line 34 is connected for thr UART4 wakeup event
+ (#) EXTI line 35 is connected for the UART5 wakeup event
+
+ ##### How to use this driver #####
+ ===============================================================================
+ [..] In order to use an I/O pin as an external interrupt source,
+ follow steps below:
+ (#) Configure the I/O in input mode using GPIO_Init().
+ (#) Select the input source pin for the EXTI line using
+ SYSCFG_EXTILineConfig().
+ (#) Select the mode(interrupt, event) and configure the trigger
+ selection (Rising, falling or both) using EXTI_Init(). For the
+ internal interrupt, the trigger selection is not needed
+ (the active edge is always the rising one).
+ (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init().
+ (#) Optionally, you can generate a software interrupt using the function
+ EXTI_GenerateSWInterrupt().
+ [..]
+ (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
+ registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_exti.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup EXTI
+ * @brief EXTI driver modules
+ * @{
+ */
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup EXTI_Private_Functions
+ * @{
+ */
+
+/** @defgroup EXTI_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the EXTI peripheral registers to their default reset
+ * values.
+ * @param None
+ * @retval None
+ */
+void EXTI_DeInit(void)
+{
+ EXTI->IMR = 0x1F800000;
+ EXTI->EMR = 0x00000000;
+ EXTI->RTSR = 0x00000000;
+ EXTI->FTSR = 0x00000000;
+ EXTI->SWIER = 0x00000000;
+ EXTI->PR = 0xE07FFFFF;
+ EXTI->IMR2 = 0x0000000C;
+ EXTI->EMR2 = 0x00000000;
+ EXTI->RTSR2 = 0x00000000;
+ EXTI->FTSR2 = 0x00000000;
+ EXTI->SWIER2 = 0x00000000;
+ EXTI->PR2 = 0x00000003;
+}
+
+/**
+ * @brief Initializes the EXTI peripheral according to the specified
+ * parameters in the EXTI_InitStruct.
+ * EXTI_Line specifies the EXTI line (EXTI0....EXTI35).
+ * EXTI_Mode specifies which EXTI line is used as interrupt or an event.
+ * EXTI_Trigger selects the trigger. When the trigger occurs, interrupt
+ * pending bit will be set.
+ * EXTI_LineCmd controls (Enable/Disable) the EXTI line.
+ * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure that
+ * contains the configuration information for the EXTI peripheral.
+ * @retval None
+ */
+
+
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+ uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
+ assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
+ assert_param(IS_EXTI_LINE_ALL(EXTI_InitStruct->EXTI_Line));
+ assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
+
+ tmp = (uint32_t)EXTI_BASE;
+
+ if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
+ {
+ /* Clear EXTI line configuration */
+ *(__IO uint32_t *) (((uint32_t) &(EXTI->IMR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
+ *(__IO uint32_t *) (((uint32_t) &(EXTI->EMR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
+
+ tmp += EXTI_InitStruct->EXTI_Mode + (((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20);
+
+ *(__IO uint32_t *) tmp |= (uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
+
+ tmp = (uint32_t)EXTI_BASE;
+
+ /* Clear Rising Falling edge configuration */
+ *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
+ *(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
+
+ /* Select the trigger for the selected interrupts */
+ if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
+ {
+ /* Rising Falling edge */
+ *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) |= (uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
+ *(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) |= (uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
+ }
+ else
+ {
+ tmp += EXTI_InitStruct->EXTI_Trigger + (((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20);
+
+ *(__IO uint32_t *) tmp |= (uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
+ }
+ }
+
+ else
+ {
+ tmp += EXTI_InitStruct->EXTI_Mode + (((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20);
+
+ /* Disable the selected external lines */
+ *(__IO uint32_t *) tmp &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
+ }
+
+}
+
+/**
+ * @brief Fills each EXTI_InitStruct member with its reset value.
+ * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+ EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
+ EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
+ EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Rising_Falling;
+ EXTI_InitStruct->EXTI_LineCmd = DISABLE;
+}
+
+/**
+ * @brief Generates a Software interrupt on selected EXTI line.
+ * @param EXTI_Line: specifies the EXTI line on which the software interrupt
+ * will be generated.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..20).
+ * @retval None
+ */
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE_EXT(EXTI_Line));
+
+ *(__IO uint32_t *) (((uint32_t) &(EXTI->SWIER)) + ((EXTI_Line) >> 5 ) * 0x20) |= (uint32_t)(1 << (EXTI_Line & 0x1F));
+
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Group2 Interrupts and flags management functions
+ * @brief EXTI Interrupts and flags management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupts and flags management functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to configure the EXTI Interrupts
+ sources and check or clear the flags or pending bits status.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Checks whether the specified EXTI line flag is set or not.
+ * @param EXTI_Line: specifies the EXTI line flag to check.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..20).
+ * @retval The new state of EXTI_Line (SET or RESET).
+ */
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+ if ((*(__IO uint32_t *) (((uint32_t) &(EXTI->PR)) + ((EXTI_Line) >> 5 ) * 0x20)& (uint32_t)(1 << (EXTI_Line & 0x1F))) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the EXTI's line pending flags.
+ * @param EXTI_Line: specifies the EXTI lines flags to clear.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..20).
+ * @retval None
+ */
+void EXTI_ClearFlag(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE_EXT(EXTI_Line));
+
+ *(__IO uint32_t *) (((uint32_t) &(EXTI->PR)) + ((EXTI_Line) >> 5 ) * 0x20) = (1 << (EXTI_Line & 0x1F));
+}
+
+/**
+ * @brief Checks whether the specified EXTI line is asserted or not.
+ * @param EXTI_Line: specifies the EXTI line to check.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..20).
+ * @retval The new state of EXTI_Line (SET or RESET).
+ */
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
+{
+ ITStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+ if ((*(__IO uint32_t *) (((uint32_t) &(EXTI->PR)) + ((EXTI_Line) >> 5 ) * 0x20)& (uint32_t)(1 << (EXTI_Line & 0x1F))) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+
+}
+
+/**
+ * @brief Clears the EXTI's line pending bits.
+ * @param EXTI_Line: specifies the EXTI lines to clear.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..20).
+ * @retval None
+ */
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE_EXT(EXTI_Line));
+
+ *(__IO uint32_t *) (((uint32_t) &(EXTI->PR)) + ((EXTI_Line) >> 5 ) * 0x20) = (1 << (EXTI_Line & 0x1F));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_exti.h Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,244 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_exti.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the EXTI
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_EXTI_H
+#define __STM32F30x_EXTI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup EXTI
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief EXTI mode enumeration
+ */
+
+typedef enum
+{
+ EXTI_Mode_Interrupt = 0x00,
+ EXTI_Mode_Event = 0x04
+}EXTIMode_TypeDef;
+
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
+
+/**
+ * @brief EXTI Trigger enumeration
+ */
+
+typedef enum
+{
+ EXTI_Trigger_Rising = 0x08,
+ EXTI_Trigger_Falling = 0x0C,
+ EXTI_Trigger_Rising_Falling = 0x10
+}EXTITrigger_TypeDef;
+
+#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
+ ((TRIGGER) == EXTI_Trigger_Falling) || \
+ ((TRIGGER) == EXTI_Trigger_Rising_Falling))
+/**
+ * @brief EXTI Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
+ This parameter can be any combination of @ref EXTI_Lines */
+
+ EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
+ This parameter can be a value of @ref EXTIMode_TypeDef */
+
+ EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
+ This parameter can be a value of @ref EXTITrigger_TypeDef */
+
+ FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
+ This parameter can be set either to ENABLE or DISABLE */
+}EXTI_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup EXTI_Exported_Constants
+ * @{
+ */
+/** @defgroup EXTI_Lines
+ * @{
+ */
+
+#define EXTI_Line0 ((uint32_t)0x00) /*!< External interrupt line 0 */
+#define EXTI_Line1 ((uint32_t)0x01) /*!< External interrupt line 1 */
+#define EXTI_Line2 ((uint32_t)0x02) /*!< External interrupt line 2 */
+#define EXTI_Line3 ((uint32_t)0x03) /*!< External interrupt line 3 */
+#define EXTI_Line4 ((uint32_t)0x04) /*!< External interrupt line 4 */
+#define EXTI_Line5 ((uint32_t)0x05) /*!< External interrupt line 5 */
+#define EXTI_Line6 ((uint32_t)0x06) /*!< External interrupt line 6 */
+#define EXTI_Line7 ((uint32_t)0x07) /*!< External interrupt line 7 */
+#define EXTI_Line8 ((uint32_t)0x08) /*!< External interrupt line 8 */
+#define EXTI_Line9 ((uint32_t)0x09) /*!< External interrupt line 9 */
+#define EXTI_Line10 ((uint32_t)0x0A) /*!< External interrupt line 10 */
+#define EXTI_Line11 ((uint32_t)0x0B) /*!< External interrupt line 11 */
+#define EXTI_Line12 ((uint32_t)0x0C) /*!< External interrupt line 12 */
+#define EXTI_Line13 ((uint32_t)0x0D) /*!< External interrupt line 13 */
+#define EXTI_Line14 ((uint32_t)0x0E) /*!< External interrupt line 14 */
+#define EXTI_Line15 ((uint32_t)0x0F) /*!< External interrupt line 15 */
+#define EXTI_Line16 ((uint32_t)0x10) /*!< External interrupt line 16
+ Connected to the PVD Output */
+#define EXTI_Line17 ((uint32_t)0x11) /*!< Internal interrupt line 17
+ Connected to the RTC Alarm
+ event */
+#define EXTI_Line18 ((uint32_t)0x12) /*!< Internal interrupt line 18
+ Connected to the USB Device
+ Wakeup from suspend event */
+#define EXTI_Line19 ((uint32_t)0x13) /*!< Internal interrupt line 19
+ Connected to the RTC Tamper
+ and Time Stamp events */
+#define EXTI_Line20 ((uint32_t)0x14) /*!< Internal interrupt line 20
+ Connected to the RTC wakeup
+ event */
+#define EXTI_Line21 ((uint32_t)0x15) /*!< Internal interrupt line 21
+ Connected to the Comparator 1
+ event */
+#define EXTI_Line22 ((uint32_t)0x16) /*!< Internal interrupt line 22
+ Connected to the Comparator 2
+ event */
+#define EXTI_Line23 ((uint32_t)0x17) /*!< Internal interrupt line 23
+ Connected to the I2C1 wakeup
+ event */
+#define EXTI_Line24 ((uint32_t)0x18) /*!< Internal interrupt line 24
+ Connected to the I2C2 wakeup
+ event */
+#define EXTI_Line25 ((uint32_t)0x19) /*!< Internal interrupt line 25
+ Connected to the USART1 wakeup
+ event */
+#define EXTI_Line26 ((uint32_t)0x1A) /*!< Internal interrupt line 26
+ Connected to the USART2 wakeup
+ event */
+#define EXTI_Line27 ((uint32_t)0x1B) /*!< Internal interrupt line 27
+ reserved */
+#define EXTI_Line28 ((uint32_t)0x1C) /*!< Internal interrupt line 28
+ Connected to the USART3 wakeup
+ event */
+#define EXTI_Line29 ((uint32_t)0x1D) /*!< Internal interrupt line 29
+ Connected to the Comparator 3
+ event */
+#define EXTI_Line30 ((uint32_t)0x1E) /*!< Internal interrupt line 30
+ Connected to the Comparator 4
+ event */
+#define EXTI_Line31 ((uint32_t)0x1F) /*!< Internal interrupt line 31
+ Connected to the Comparator 5
+ event */
+#define EXTI_Line32 ((uint32_t)0x20) /*!< Internal interrupt line 32
+ Connected to the Comparator 6
+ event */
+#define EXTI_Line33 ((uint32_t)0x21) /*!< Internal interrupt line 33
+ Connected to the Comparator 7
+ event */
+#define EXTI_Line34 ((uint32_t)0x22) /*!< Internal interrupt line 34
+ Connected to the USART4 wakeup
+ event */
+#define EXTI_Line35 ((uint32_t)0x23) /*!< Internal interrupt line 35
+ Connected to the USART5 wakeup
+ event */
+
+#define IS_EXTI_LINE_ALL(LINE) ((LINE) <= 0x23)
+#define IS_EXTI_LINE_EXT(LINE) (((LINE) <= 0x16) || (((LINE) == EXTI_Line29) || ((LINE) == EXTI_Line30) || \
+ ((LINE) == EXTI_Line31) || ((LINE) == EXTI_Line32) || ((LINE) == EXTI_Line33)))
+
+#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
+ ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
+ ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
+ ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
+ ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
+ ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
+ ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
+ ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
+ ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
+ ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
+ ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \
+ ((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line29) || \
+ ((LINE) == EXTI_Line30) || ((LINE) == EXTI_Line31) || \
+ ((LINE) == EXTI_Line32) || ((LINE) == EXTI_Line33))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* Function used to set the EXTI configuration to the default reset state *****/
+void EXTI_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
+
+/* Interrupts and flags management functions **********************************/
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
+void EXTI_ClearFlag(uint32_t EXTI_Line);
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F30x_EXTI_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_flash.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,1180 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_flash.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the FLASH peripheral:
+ * + FLASH Interface configuration
+ * + FLASH Memory Programming
+ * + Option Bytes Programming
+ * + Interrupts and flags management
+ *
+ @verbatim
+
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..] This driver provides functions to configure and program the FLASH
+ memory of all STM32F30x devices. These functions are split in 4 groups:
+ (#) FLASH Interface configuration functions: this group includes the
+ management of following features:
+ (++) Set the latency.
+ (++) Enable/Disable the Half Cycle Access.
+ (++) Enable/Disable the prefetch buffer.
+ (#) FLASH Memory Programming functions: this group includes all needed
+ functions to erase and program the main memory:
+ (++) Lock and Unlock the FLASH interface.
+ (++) Erase function: Erase page, erase all pages.
+ (++) Program functions: Half Word and Word write.
+ (#) FLASH Option Bytes Programming functions: this group includes all
+ needed functions to manage the Option Bytes:
+ (++) Lock and Unlock the Flash Option bytes.
+ (++) Launch the Option Bytes loader
+ (++) Erase the Option Bytes
+ (++) Set/Reset the write protection
+ (++) Set the Read protection Level
+ (++) Program the user option Bytes
+ (++) Set/Reset the BOOT1 bit
+ (++) Enable/Disable the VDDA Analog Monitoring
+ (++) Enable/Disable the SRAM parity
+ (++) Get the user option bytes
+ (++) Get the Write protection
+ (++) Get the read protection status
+ (#) FLASH Interrupts and flags management functions: this group includes
+ all needed functions to:
+ (++) Enable/Disable the FLASH interrupt sources.
+ (++) Get flags status.
+ (++) Clear flags.
+ (++) Get FLASH operation status.
+ (++) Wait for last FLASH operation.
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_flash.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup FLASH
+ * @brief FLASH driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* FLASH Mask */
+#define RDPRT_MASK ((uint32_t)0x00000002)
+#define WRP01_MASK ((uint32_t)0x0000FFFF)
+#define WRP23_MASK ((uint32_t)0xFFFF0000)
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup FLASH_Private_Functions
+ * @{
+ */
+
+/** @defgroup FLASH_Group1 FLASH Interface configuration functions
+ * @brief FLASH Interface configuration functions
+ *
+
+@verbatim
+ ===============================================================================
+ ##### FLASH Interface configuration functions #####
+ ===============================================================================
+ [..] This group includes the following functions:
+ (+) void FLASH_SetLatency(uint32_t FLASH_Latency);
+ (+) void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);
+ (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState);
+ [..] The unlock sequence is not needed for these functions.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Sets the code latency value.
+ * @param FLASH_Latency: specifies the FLASH Latency value.
+ * This parameter can be one of the following values:
+ * @arg FLASH_Latency_0: FLASH Zero Latency cycle
+ * @arg FLASH_Latency_1: FLASH One Latency cycle
+ * @arg FLASH_Latency_2: FLASH Two Latency cycles
+ * @retval None
+ */
+void FLASH_SetLatency(uint32_t FLASH_Latency)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_LATENCY(FLASH_Latency));
+
+ /* Read the ACR register */
+ tmpreg = FLASH->ACR;
+
+ /* Sets the Latency value */
+ tmpreg &= (uint32_t) (~((uint32_t)FLASH_ACR_LATENCY));
+ tmpreg |= FLASH_Latency;
+
+ /* Write the ACR register */
+ FLASH->ACR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the Half cycle flash access.
+ * @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode.
+ * This parameter can be one of the following values:
+ * @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable
+ * @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable
+ * @retval None
+ */
+void FLASH_HalfCycleAccessCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if(NewState != DISABLE)
+ {
+ FLASH->ACR |= FLASH_ACR_HLFCYA;
+ }
+ else
+ {
+ FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_HLFCYA));
+ }
+}
+
+/**
+ * @brief Enables or disables the Prefetch Buffer.
+ * @param NewState: new state of the Prefetch Buffer.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FLASH_PrefetchBufferCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if(NewState != DISABLE)
+ {
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+ }
+ else
+ {
+ FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_PRFTBE));
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Group2 FLASH Memory Programming functions
+ * @brief FLASH Memory Programming functions
+ *
+@verbatim
+ ===============================================================================
+ ##### FLASH Memory Programming functions #####
+ ===============================================================================
+ [..] This group includes the following functions:
+ (+) void FLASH_Unlock(void);
+ (+) void FLASH_Lock(void);
+ (+) FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
+ (+) FLASH_Status FLASH_EraseAllPages(void);
+ (+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+ (+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
+ [..] Any operation of erase or program should follow these steps:
+ (#) Call the FLASH_Unlock() function to enable the FLASH control register
+ program memory access.
+ (#) Call the desired function to erase page or program data.
+ (#) Call the FLASH_Lock() function to disable the FLASH control register
+ access (recommended to protect the FLASH memory against possible
+ unwanted operation).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Unlocks the FLASH control register access
+ * @param None
+ * @retval None
+ */
+void FLASH_Unlock(void)
+{
+ if((FLASH->CR & FLASH_CR_LOCK) != RESET)
+ {
+ /* Authorize the FLASH Registers access */
+ FLASH->KEYR = FLASH_KEY1;
+ FLASH->KEYR = FLASH_KEY2;
+ }
+}
+
+/**
+ * @brief Locks the FLASH control register access
+ * @param None
+ * @retval None
+ */
+void FLASH_Lock(void)
+{
+ /* Set the LOCK Bit to lock the FLASH Registers access */
+ FLASH->CR |= FLASH_CR_LOCK;
+}
+
+/**
+ * @brief Erases a specified page in program memory.
+ * @note To correctly run this function, the FLASH_Unlock() function
+ * must be called before.
+ * @note Call the FLASH_Lock() to disable the flash memory access
+ * (recommended to protect the FLASH memory against possible unwanted operation)
+ * @param Page_Address: The page address in program memory to be erased.
+ * @note A Page is erased in the Program memory only if the address to load
+ * is the start address of a page (multiple of 1024 bytes).
+ * @retval FLASH Status: The returned value can be:
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Page_Address));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* If the previous operation is completed, proceed to erase the page */
+ FLASH->CR |= FLASH_CR_PER;
+ FLASH->AR = Page_Address;
+ FLASH->CR |= FLASH_CR_STRT;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ /* Disable the PER Bit */
+ FLASH->CR &= ~FLASH_CR_PER;
+ }
+
+ /* Return the Erase Status */
+ return status;
+}
+
+/**
+ * @brief Erases all FLASH pages.
+ * @note To correctly run this function, the FLASH_Unlock() function
+ * must be called before.
+ * all the FLASH_Lock() to disable the flash memory access
+ * (recommended to protect the FLASH memory against possible unwanted operation)
+ * @param None
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EraseAllPages(void)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to erase all pages */
+ FLASH->CR |= FLASH_CR_MER;
+ FLASH->CR |= FLASH_CR_STRT;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ /* Disable the MER Bit */
+ FLASH->CR &= ~FLASH_CR_MER;
+ }
+
+ /* Return the Erase Status */
+ return status;
+}
+
+/**
+ * @brief Programs a word at a specified address.
+ * @note To correctly run this function, the FLASH_Unlock() function
+ * must be called before.
+ * Call the FLASH_Lock() to disable the flash memory access
+ * (recommended to protect the FLASH memory against possible unwanted operation)
+ * @param Address: specifies the address to be programmed.
+ * @param Data: specifies the data to be programmed.
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* If the previous operation is completed, proceed to program the new first
+ half word */
+ FLASH->CR |= FLASH_CR_PG;
+
+ *(__IO uint16_t*)Address = (uint16_t)Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* If the previous operation is completed, proceed to program the new second
+ half word */
+ tmp = Address + 2;
+
+ *(__IO uint16_t*) tmp = Data >> 16;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ /* Disable the PG Bit */
+ FLASH->CR &= ~FLASH_CR_PG;
+ }
+ else
+ {
+ /* Disable the PG Bit */
+ FLASH->CR &= ~FLASH_CR_PG;
+ }
+ }
+
+ /* Return the Program Status */
+ return status;
+}
+
+/**
+ * @brief Programs a half word at a specified address.
+ * @note To correctly run this function, the FLASH_Unlock() function
+ * must be called before.
+ * Call the FLASH_Lock() to disable the flash memory access
+ * (recommended to protect the FLASH memory against possible unwanted operation)
+ * @param Address: specifies the address to be programmed.
+ * @param Data: specifies the data to be programmed.
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* If the previous operation is completed, proceed to program the new data */
+ FLASH->CR |= FLASH_CR_PG;
+
+ *(__IO uint16_t*)Address = Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ /* Disable the PG Bit */
+ FLASH->CR &= ~FLASH_CR_PG;
+ }
+
+ /* Return the Program Status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Group3 Option Bytes Programming functions
+ * @brief Option Bytes Programming functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Option Bytes Programming functions #####
+ ===============================================================================
+ [..] This group includes the following functions:
+ (+) void FLASH_OB_Unlock(void);
+ (+) void FLASH_OB_Lock(void);
+ (+) void FLASH_OB_Erase(void);
+ (+) FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
+ (+) FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
+ (+) FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
+ (+) FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1);
+ (+) FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG);
+ (+) FLASH_Status FLASH_OB_SRMParityConfig(uint8_t OB_SRAM_Parity);
+ (+) FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER);
+ (+) FLASH_Status FLASH_OB_Launch(void);
+ (+) uint32_t FLASH_OB_GetUser(void);
+ (+) uint8_t FLASH_OB_GetWRP(void);
+ (+) uint8_t FLASH_OB_GetRDP(void);
+ [..] Any operation of erase or program should follow these steps:
+ (#) Call the FLASH_OB_Unlock() function to enable the FLASH option control
+ register access.
+ (#) Call one or several functions to program the desired Option Bytes:
+ (++) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
+ => to Enable/Disable the desired sector write protection.
+ (++) FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the
+ desired read Protection Level.
+ (++) FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
+ => to configure the user Option Bytes.
+ (++) FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1);
+ => to set the boot1 mode
+ (++) FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG);
+ => to Enable/Disable the VDDA monotoring.
+ (++) FLASH_Status FLASH_OB_SRMParityConfig(uint8_t OB_SRAM_Parity);
+ => to Enable/Disable the SRAM Parity check.
+ (++) FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER);
+ => to write all user option bytes: OB_IWDG, OB_STOP, OB_STDBY,
+ OB_BOOT1, OB_VDDA_ANALOG and OB_VDD_SD12.
+ (#) Once all needed Option Bytes to be programmed are correctly written,
+ call the FLASH_OB_Launch() function to launch the Option Bytes
+ programming process.
+ (#@) When changing the IWDG mode from HW to SW or from SW to HW, a system
+ reset is needed to make the change effective.
+ (#) Call the FLASH_OB_Lock() function to disable the FLASH option control
+ register access (recommended to protect the Option Bytes against
+ possible unwanted operations).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Unlocks the option bytes block access.
+ * @param None
+ * @retval None
+ */
+void FLASH_OB_Unlock(void)
+{
+ if((FLASH->CR & FLASH_CR_OPTWRE) == RESET)
+ {
+ /* Unlocking the option bytes block access */
+ FLASH->OPTKEYR = FLASH_OPTKEY1;
+ FLASH->OPTKEYR = FLASH_OPTKEY2;
+ }
+}
+
+/**
+ * @brief Locks the option bytes block access.
+ * @param None
+ * @retval None
+ */
+void FLASH_OB_Lock(void)
+{
+ /* Set the OPTWREN Bit to lock the option bytes block access */
+ FLASH->CR &= ~FLASH_CR_OPTWRE;
+}
+
+/**
+ * @brief Launch the option byte loading.
+ * @param None
+ * @retval None
+ */
+void FLASH_OB_Launch(void)
+{
+ /* Set the OBL_Launch bit to launch the option byte loading */
+ FLASH->CR |= FLASH_CR_OBL_LAUNCH;
+}
+
+/**
+ * @brief Erases the FLASH option bytes.
+ * @note This functions erases all option bytes except the Read protection (RDP).
+ * @param None
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_OB_Erase(void)
+{
+ uint16_t rdptmp = OB_RDP_Level_0;
+
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Get the actual read protection Option Byte value */
+ if(FLASH_OB_GetRDP() != RESET)
+ {
+ rdptmp = 0x00;
+ }
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* If the previous operation is completed, proceed to erase the option bytes */
+ FLASH->CR |= FLASH_CR_OPTER;
+ FLASH->CR |= FLASH_CR_STRT;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* If the erase operation is completed, disable the OPTER Bit */
+ FLASH->CR &= ~FLASH_CR_OPTER;
+
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CR |= FLASH_CR_OPTPG;
+
+ /* Restore the last read protection Option Byte value */
+ OB->RDP = (uint16_t)rdptmp;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= ~FLASH_CR_OPTPG;
+ }
+ }
+ else
+ {
+ if (status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTPG Bit */
+ FLASH->CR &= ~FLASH_CR_OPTPG;
+ }
+ }
+ }
+ /* Return the erase status */
+ return status;
+}
+
+/**
+ * @brief Write protects the desired pages
+ * @note To correctly run this function, the FLASH_OB_Unlock() function
+ * must be called before.
+ * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes
+ * (recommended to protect the FLASH memory against possible unwanted operation)
+ * @param OB_WRP: specifies the address of the pages to be write protected.
+ * This parameter can be:
+ * @arg value between OB_WRP_Pages0to35 and OB_WRP_Pages60to63
+ * @arg OB_WRP_AllPages
+ * @retval FLASH Status: The returned value can be:
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP)
+{
+ uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF;
+
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check the parameters */
+ assert_param(IS_OB_WRP(OB_WRP));
+
+ OB_WRP = (uint32_t)(~OB_WRP);
+ WRP0_Data = (uint16_t)(OB_WRP & OB_WRP0_WRP0);
+ WRP1_Data = (uint16_t)((OB_WRP & OB_WRP0_nWRP0) >> 8);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status == FLASH_COMPLETE)
+ {
+ FLASH->CR |= FLASH_CR_OPTPG;
+
+ if(WRP0_Data != 0xFF)
+ {
+ OB->WRP0 = WRP0_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+ }
+ if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))
+ {
+ OB->WRP1 = WRP1_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+ }
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= ~FLASH_CR_OPTPG;
+ }
+ }
+ /* Return the write protection operation Status */
+ return status;
+}
+
+/**
+ * @brief Enables or disables the read out protection.
+ * @note To correctly run this function, the FLASH_OB_Unlock() function
+ * must be called before.
+ * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes
+ * (recommended to protect the FLASH memory against possible unwanted operation)
+ * @param FLASH_ReadProtection_Level: specifies the read protection level.
+ * This parameter can be:
+ * @arg OB_RDP_Level_0: No protection
+ * @arg OB_RDP_Level_1: Read protection of the memory
+ * @arg OB_RDP_Level_2: Chip protection
+ * @retval FLASH Status: The returned value can be:
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check the parameters */
+ assert_param(IS_OB_RDP(OB_RDP));
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status == FLASH_COMPLETE)
+ {
+ FLASH->CR |= FLASH_CR_OPTER;
+ FLASH->CR |= FLASH_CR_STRT;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* If the erase operation is completed, disable the OPTER Bit */
+ FLASH->CR &= ~FLASH_CR_OPTER;
+
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CR |= FLASH_CR_OPTPG;
+
+ OB->RDP = OB_RDP;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= ~FLASH_CR_OPTPG;
+ }
+ }
+ else
+ {
+ if(status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTER Bit */
+ FLASH->CR &= ~FLASH_CR_OPTER;
+ }
+ }
+ }
+ /* Return the protection operation Status */
+ return status;
+}
+
+/**
+ * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
+ * @param OB_IWDG: Selects the IWDG mode
+ * This parameter can be one of the following values:
+ * @arg OB_IWDG_SW: Software IWDG selected
+ * @arg OB_IWDG_HW: Hardware IWDG selected
+ * @param OB_STOP: Reset event when entering STOP mode.
+ * This parameter can be one of the following values:
+ * @arg OB_STOP_NoRST: No reset generated when entering in STOP
+ * @arg OB_STOP_RST: Reset generated when entering in STOP
+ * @param OB_STDBY: Reset event when entering Standby mode.
+ * This parameter can be one of the following values:
+ * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
+ * @arg OB_STDBY_RST: Reset generated when entering in STANDBY
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check the parameters */
+ assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
+ assert_param(IS_OB_STOP_SOURCE(OB_STOP));
+ assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
+
+ /* Authorize the small information block programming */
+ FLASH->OPTKEYR = FLASH_KEY1;
+ FLASH->OPTKEYR = FLASH_KEY2;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CR |= FLASH_CR_OPTPG;
+
+ OB->USER = (uint8_t)((uint8_t)(OB_IWDG | OB_STOP) | (uint8_t)(OB_STDBY |0xF8));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= ~FLASH_CR_OPTPG;
+ }
+ }
+ /* Return the Option Byte program Status */
+ return status;
+}
+
+/**
+ * @brief Sets or resets the BOOT1.
+ * @param OB_BOOT1: Set or Reset the BOOT1.
+ * This parameter can be one of the following values:
+ * @arg OB_BOOT1_RESET: BOOT1 Reset
+ * @arg OB_BOOT1_SET: BOOT1 Set
+ * @retval None
+ */
+FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check the parameters */
+ assert_param(IS_OB_BOOT1(OB_BOOT1));
+
+ /* Authorize the small information block programming */
+ FLASH->OPTKEYR = FLASH_KEY1;
+ FLASH->OPTKEYR = FLASH_KEY2;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CR |= FLASH_CR_OPTPG;
+
+ OB->USER = OB_BOOT1|0xEF;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= ~FLASH_CR_OPTPG;
+ }
+ }
+ /* Return the Option Byte program Status */
+ return status;
+}
+
+/**
+ * @brief Sets or resets the analogue monitoring on VDDA Power source.
+ * @param OB_VDDA_ANALOG: Selects the analog monitoring on VDDA Power source.
+ * This parameter can be one of the following values:
+ * @arg OB_VDDA_ANALOG_ON: Analog monitoring on VDDA Power source ON
+ * @arg OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source OFF
+ * @retval None
+ */
+FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check the parameters */
+ assert_param(IS_OB_VDDA_ANALOG(OB_VDDA_ANALOG));
+
+ /* Authorize the small information block programming */
+ FLASH->OPTKEYR = FLASH_KEY1;
+ FLASH->OPTKEYR = FLASH_KEY2;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CR |= FLASH_CR_OPTPG;
+
+ OB->USER = OB_VDDA_ANALOG |0xDF;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= ~FLASH_CR_OPTPG;
+ }
+ }
+ /* Return the Option Byte program Status */
+ return status;
+}
+
+/**
+ * @brief Sets or resets the SRAM partiy.
+ * @param OB_SRAM_Parity: Set or Reset the SRAM partiy enable bit.
+ * This parameter can be one of the following values:
+ * @arg OB_SRAM_PARITY_SET: Set SRAM partiy.
+ * @arg OB_SRAM_PARITY_RESET: Reset SRAM partiy.
+ * @retval None
+ */
+FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check the parameters */
+ assert_param(IS_OB_SRAM_PARITY(OB_SRAM_Parity));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CR |= FLASH_CR_OPTPG;
+
+ OB->USER = OB_SRAM_Parity | 0xBF;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= ~FLASH_CR_OPTPG;
+ }
+ }
+ /* Return the Option Byte program Status */
+ return status;
+}
+
+/**
+ * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY/ BOOT1 and OB_VDDA_ANALOG.
+ * @note To correctly run this function, the FLASH_OB_Unlock() function
+ * must be called before.
+ * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes
+ * (recommended to protect the FLASH memory against possible unwanted operation)
+ * @param OB_USER: Selects all user option bytes
+ * This parameter is a combination of the following values:
+ * @arg OB_IWDG_SW / OB_IWDG_HW: Software / Hardware WDG selected
+ * @arg OB_STOP_NoRST / OB_STOP_RST: No reset / Reset generated when entering in STOP
+ * @arg OB_STDBY_NoRST / OB_STDBY_RST: No reset / Reset generated when entering in STANDBY
+ * @arg OB_BOOT1_RESET / OB_BOOT1_SET: BOOT1 Reset / Set
+ * @arg OB_VDDA_ANALOG_ON / OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source ON / OFF
+ * @retval FLASH Status: The returned value can be:
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Authorize the small information block programming */
+ FLASH->OPTKEYR = FLASH_KEY1;
+ FLASH->OPTKEYR = FLASH_KEY2;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CR |= FLASH_CR_OPTPG;
+
+ OB->USER = OB_USER | 0x88;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= ~FLASH_CR_OPTPG;
+ }
+ }
+ /* Return the Option Byte program Status */
+ return status;
+
+}
+
+/**
+ * @brief Programs a half word at a specified Option Byte Data address.
+ * @note To correctly run this function, the FLASH_OB_Unlock() function
+ * must be called before.
+ * Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes
+ * (recommended to protect the FLASH memory against possible unwanted operation)
+ * @param Address: specifies the address to be programmed.
+ * This parameter can be 0x1FFFF804 or 0x1FFFF806.
+ * @param Data: specifies the data to be programmed.
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+ /* Check the parameters */
+ assert_param(IS_OB_DATA_ADDRESS(Address));
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* Enables the Option Bytes Programming operation */
+ FLASH->CR |= FLASH_CR_OPTPG;
+ *(__IO uint16_t*)Address = Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status != FLASH_TIMEOUT)
+ {
+ /* If the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= ~FLASH_CR_OPTPG;
+ }
+ }
+ /* Return the Option Byte Data Program Status */
+ return status;
+}
+
+/**
+ * @brief Returns the FLASH User Option Bytes values.
+ * @param None
+ * @retval The FLASH User Option Bytes .
+ */
+uint8_t FLASH_OB_GetUser(void)
+{
+ /* Return the User Option Byte */
+ return (uint8_t)(FLASH->OBR >> 8);
+}
+
+/**
+ * @brief Returns the FLASH Write Protection Option Bytes value.
+ * @param None
+ * @retval The FLASH Write Protection Option Bytes value
+ */
+uint32_t FLASH_OB_GetWRP(void)
+{
+ /* Return the FLASH write protection Register value */
+ return (uint32_t)(FLASH->WRPR);
+}
+
+/**
+ * @brief Checks whether the FLASH Read out Protection Status is set or not.
+ * @param None
+ * @retval FLASH ReadOut Protection Status(SET or RESET)
+ */
+FlagStatus FLASH_OB_GetRDP(void)
+{
+ FlagStatus readstatus = RESET;
+
+ if ((uint8_t)(FLASH->OBR & (FLASH_OBR_RDPRT1 | FLASH_OBR_RDPRT2)) != RESET)
+ {
+ readstatus = SET;
+ }
+ else
+ {
+ readstatus = RESET;
+ }
+ return readstatus;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Group4 Interrupts and flags management functions
+ * @brief Interrupts and flags management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupts and flags management functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the specified FLASH interrupts.
+ * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or
+ * disabled.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_EOP: FLASH end of programming Interrupt
+ * @arg FLASH_IT_ERR: FLASH Error Interrupt
+ * @retval None
+ */
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_IT(FLASH_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if(NewState != DISABLE)
+ {
+ /* Enable the interrupt sources */
+ FLASH->CR |= FLASH_IT;
+ }
+ else
+ {
+ /* Disable the interrupt sources */
+ FLASH->CR &= ~(uint32_t)FLASH_IT;
+ }
+}
+
+/**
+ * @brief Checks whether the specified FLASH flag is set or not.
+ * @param FLASH_FLAG: specifies the FLASH flag to check.
+ * This parameter can be one of the following values:
+ * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag
+ * @arg FLASH_FLAG_PGERR: FLASH Programming error flag flag
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
+ * @arg FLASH_FLAG_EOP: FLASH End of Programming flag
+ * @retval The new state of FLASH_FLAG (SET or RESET).
+ */
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));
+
+ if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the new state of FLASH_FLAG (SET or RESET) */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the FLASH's pending flags.
+ * @param FLASH_FLAG: specifies the FLASH flags to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_FLAG_PGERR: FLASH Programming error flag flag
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
+ * @arg FLASH_FLAG_EOP: FLASH End of Programming flag
+ * @retval None
+ */
+void FLASH_ClearFlag(uint32_t FLASH_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));
+
+ /* Clear the flags */
+ FLASH->SR = FLASH_FLAG;
+}
+
+/**
+ * @brief Returns the FLASH Status.
+ * @param None
+ * @retval FLASH Status: The returned value can be:
+ * FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE.
+ */
+FLASH_Status FLASH_GetStatus(void)
+{
+ FLASH_Status FLASHstatus = FLASH_COMPLETE;
+
+ if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
+ {
+ FLASHstatus = FLASH_BUSY;
+ }
+ else
+ {
+ if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00)
+ {
+ FLASHstatus = FLASH_ERROR_WRP;
+ }
+ else
+ {
+ if((FLASH->SR & (uint32_t)(FLASH_SR_PGERR)) != (uint32_t)0x00)
+ {
+ FLASHstatus = FLASH_ERROR_PROGRAM;
+ }
+ else
+ {
+ FLASHstatus = FLASH_COMPLETE;
+ }
+ }
+ }
+ /* Return the FLASH Status */
+ return FLASHstatus;
+}
+
+/**
+ * @brief Waits for a FLASH operation to complete or a TIMEOUT to occur.
+ * @param Timeout: FLASH programming Timeout
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY,
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check for the FLASH Status */
+ status = FLASH_GetStatus();
+
+ /* Wait for a FLASH operation to complete or a TIMEOUT to occur */
+ while((status == FLASH_BUSY) && (Timeout != 0x00))
+ {
+ status = FLASH_GetStatus();
+ Timeout--;
+ }
+
+ if(Timeout == 0x00 )
+ {
+ status = FLASH_TIMEOUT;
+ }
+ /* Return the operation status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_flash.h Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,339 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_flash.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the FLASH
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_FLASH_H
+#define __STM32F30x_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/**
+ * @brief FLASH Status
+ */
+typedef enum
+{
+ FLASH_BUSY = 1,
+ FLASH_ERROR_WRP,
+ FLASH_ERROR_PROGRAM,
+ FLASH_COMPLETE,
+ FLASH_TIMEOUT
+}FLASH_Status;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FLASH_Exported_Constants
+ * @{
+ */
+
+/** @defgroup Flash_Latency
+ * @{
+ */
+#define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */
+#define FLASH_Latency_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
+#define FLASH_Latency_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */
+
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
+ ((LATENCY) == FLASH_Latency_1) || \
+ ((LATENCY) == FLASH_Latency_2))
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Interrupts
+ * @{
+ */
+
+#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of programming interrupt source */
+#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error interrupt source */
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
+/**
+ * @}
+ */
+/** @defgroup FLASH_Address
+ * @{
+ */
+
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0803FFFF))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_OB_DATA_ADDRESS
+ * @{
+ */
+#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
+
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_Write_Protection
+ * @{
+ */
+
+#define OB_WRP_Pages0to1 ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */
+#define OB_WRP_Pages2to3 ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */
+#define OB_WRP_Pages4to5 ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */
+#define OB_WRP_Pages6to7 ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */
+#define OB_WRP_Pages8to9 ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */
+#define OB_WRP_Pages10to11 ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */
+#define OB_WRP_Pages12to13 ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */
+#define OB_WRP_Pages14to15 ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */
+#define OB_WRP_Pages16to17 ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */
+#define OB_WRP_Pages18to19 ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */
+#define OB_WRP_Pages20to21 ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */
+#define OB_WRP_Pages22to23 ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */
+#define OB_WRP_Pages24to25 ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */
+#define OB_WRP_Pages26to27 ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */
+#define OB_WRP_Pages28to29 ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */
+#define OB_WRP_Pages30to31 ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */
+#define OB_WRP_Pages32to33 ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */
+#define OB_WRP_Pages34to35 ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */
+#define OB_WRP_Pages36to37 ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */
+#define OB_WRP_Pages38to39 ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */
+#define OB_WRP_Pages40to41 ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */
+#define OB_WRP_Pages42to43 ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */
+#define OB_WRP_Pages44to45 ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */
+#define OB_WRP_Pages46to47 ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */
+#define OB_WRP_Pages48to49 ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */
+#define OB_WRP_Pages50to51 ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */
+#define OB_WRP_Pages52to53 ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */
+#define OB_WRP_Pages54to55 ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */
+#define OB_WRP_Pages56to57 ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */
+#define OB_WRP_Pages58to59 ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */
+#define OB_WRP_Pages60to61 ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */
+#define OB_WRP_Pages62to127 ((uint32_t)0x80000000) /* Write protection of page 62 to 127 */
+
+#define OB_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
+
+#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
+
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_Read_Protection
+ * @{
+ */
+
+/**
+ * @brief Read Protection Level
+ */
+#define OB_RDP_Level_0 ((uint8_t)0xAA)
+#define OB_RDP_Level_1 ((uint8_t)0xBB)
+/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2
+ it's no more possible to go back to level 1 or 0 */
+
+#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
+ ((LEVEL) == OB_RDP_Level_1))/*||\
+ ((LEVEL) == OB_RDP_Level_2))*/
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_IWatchdog
+ * @{
+ */
+
+#define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */
+#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_nRST_STOP
+ * @{
+ */
+
+#define OB_STOP_NoRST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
+
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_nRST_STDBY
+ * @{
+ */
+
+#define OB_STDBY_NoRST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
+
+/**
+ * @}
+ */
+/** @defgroup Option_Bytes_BOOT1
+ * @{
+ */
+
+#define OB_BOOT1_RESET ((uint8_t)0x00) /*!< BOOT1 Reset */
+#define OB_BOOT1_SET ((uint8_t)0x10) /*!< BOOT1 Set */
+#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
+
+/**
+ * @}
+ */
+/** @defgroup Option_Bytes_VDDA_Analog_Monitoring
+ * @{
+ */
+
+#define OB_VDDA_ANALOG_ON ((uint8_t)0x20) /*!< Analog monitoring on VDDA Power source ON */
+#define OB_VDDA_ANALOG_OFF ((uint8_t)0x00) /*!< Analog monitoring on VDDA Power source OFF */
+
+#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Option_Bytes_SRAM_Parity_Enable
+ * @{
+ */
+
+#define OB_SRAM_PARITY_SET ((uint8_t)0x00) /*!< SRAM parity enable Set */
+#define OB_SRAM_PARITY_RESET ((uint8_t)0x40) /*!< SRAM parity enable reset */
+
+#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Flags
+ * @{
+ */
+
+#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
+#define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */
+#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */
+
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCB) == 0x00000000) && ((FLAG) != 0x00000000))
+
+#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PGERR) || \
+ ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP))
+/**
+ * @}
+ */
+/** @defgroup Timeout_definition
+ * @{
+ */
+#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x000B0000)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* FLASH Interface configuration functions ************************************/
+void FLASH_SetLatency(uint32_t FLASH_Latency);
+void FLASH_HalfCycleAccessCmd(FunctionalState NewState);
+void FLASH_PrefetchBufferCmd(FunctionalState NewState);
+
+/* FLASH Memory Programming functions *****************************************/
+void FLASH_Unlock(void);
+void FLASH_Lock(void);
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
+FLASH_Status FLASH_EraseAllPages(void);
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
+
+/* Option Bytes Programming functions *****************************************/
+void FLASH_OB_Unlock(void);
+void FLASH_OB_Lock(void);
+void FLASH_OB_Launch(void);
+FLASH_Status FLASH_OB_Erase(void);
+FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP);
+FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
+FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
+FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1);
+FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG);
+FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity);
+FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER);
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
+uint8_t FLASH_OB_GetUser(void);
+uint32_t FLASH_OB_GetWRP(void);
+FlagStatus FLASH_OB_GetRDP(void);
+
+/* Interrupts and flags management functions **********************************/
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);
+FLASH_Status FLASH_GetStatus(void);
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F30x_FLASH_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_gpio.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,545 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_gpio.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the GPIO peripheral:
+ * + Initialization and Configuration functions
+ * + GPIO Read and Write functions
+ * + GPIO Alternate functions configuration functions
+ *
+ * @verbatim
+
+
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ (#) Enable the GPIO AHB clock using RCC_AHBPeriphClockCmd()
+ (#) Configure the GPIO pin(s) using GPIO_Init()
+ Four possible configuration are available for each pin:
+ (++) Input: Floating, Pull-up, Pull-down.
+ (++) Output: Push-Pull (Pull-up, Pull-down or no Pull),
+ Open Drain (Pull-up, Pull-down or no Pull).
+ In output mode, the speed is configurable: Low, Medium, Fast or High.
+ (++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull),
+ Open Drain (Pull-up, Pull-down or no Pull).
+ (++) Analog: required mode when a pin is to be used as ADC channel,
+ DAC output or comparator input.
+ (#) Peripherals alternate function:
+ (++) For ADC, DAC and comparators, configure the desired pin in
+ analog mode using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN
+ (++) For other peripherals (TIM, USART...):
+ (+++) Connect the pin to the desired peripherals' Alternate
+ Function (AF) using GPIO_PinAFConfig() function.
+ (+++) Configure the desired pin in alternate function mode using
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+ (+++) Select the type, pull-up/pull-down and output speed via
+ GPIO_PuPd, GPIO_OType and GPIO_Speed members.
+ (+++) Call GPIO_Init() function.
+ (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
+ (#) To set/reset the level of a pin configured in output mode use
+ GPIO_SetBits()/GPIO_ResetBits()
+ (#) During and just after reset, the alternate functions are not active
+ and the GPIO pins are configured in input floating mode (except JTAG pins).
+ (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as
+ general-purpose (PC14 and PC15, respectively) when the LSE
+ oscillator is off. The LSE has priority over the GPIO function.
+ (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose
+ (PF0 and PF1 respectively) when the HSE oscillator is off. The HSE has
+ the priority over the GPIO function.
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_gpio.h"
+#include "stm32f30x_rcc.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup GPIO
+ * @brief GPIO driver modules
+ * @{
+ */
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup GPIO_Private_Functions
+ * @{
+ */
+
+/** @defgroup GPIO_Group1 Initialization and Configuration
+ * @brief Initialization and Configuration
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the GPIOx peripheral registers to their default reset
+ * values.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @retval None
+ */
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ if(GPIOx == GPIOA)
+ {
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE);
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE);
+ }
+ else if(GPIOx == GPIOB)
+ {
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE);
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE);
+ }
+ else if(GPIOx == GPIOC)
+ {
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE);
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE);
+ }
+ else if(GPIOx == GPIOD)
+ {
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE);
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE);
+ }
+ else if(GPIOx == GPIOE)
+ {
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, ENABLE);
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, DISABLE);
+ }
+ else
+ {
+ if(GPIOx == GPIOF)
+ {
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, ENABLE);
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, DISABLE);
+ }
+ }
+}
+
+/**
+ * @brief Initializes the GPIOx peripheral according to the specified
+ * parameters in the GPIO_InitStruct.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
+ * contains the configuration information for the specified GPIO
+ * peripheral.
+ * @note GPIO_Pin: selects the pin to be configured:
+ * GPIO_Pin_0->GPIO_Pin_15 for GPIOA, GPIOB, GPIOC, GPIOD and GPIOE;
+ * GPIO_Pin_0->GPIO_Pin_2, GPIO_Pin_4, GPIO_Pin_6, GPIO_Pin_9
+ * and GPIO_Pin_10 for GPIOF.
+ * @retval None
+ */
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
+{
+ uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
+ uint32_t tmpreg = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
+ assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
+ assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
+
+ /*-------------------------- Configure the port pins -----------------------*/
+ /*-- GPIO Mode Configuration --*/
+ for (pinpos = 0x00; pinpos < 0x10; pinpos++)
+ {
+ pos = ((uint32_t)0x01) << pinpos;
+
+ /* Get the port pins position */
+ currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
+
+ if (currentpin == pos)
+ {
+ if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
+ {
+ /* Check Speed mode parameters */
+ assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
+
+ /* Speed mode configuration */
+ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
+ GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
+
+ /* Check Output mode parameters */
+ assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
+
+ /* Output mode configuration */
+ GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos));
+ GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
+ }
+
+ GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
+
+ GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
+
+ /* Use temporary variable to update PUPDR register configuration, to avoid
+ unexpected transition in the GPIO pin configuration. */
+ tmpreg = GPIOx->PUPDR;
+ tmpreg &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
+ tmpreg |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
+ GPIOx->PUPDR = tmpreg;
+ }
+ }
+}
+
+/**
+ * @brief Fills each GPIO_InitStruct member with its default value.
+ * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
+{
+ /* Reset GPIO init structure parameters values */
+ GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
+ GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
+ GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
+ GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
+}
+
+/**
+ * @brief Locks GPIO Pins configuration registers.
+ * The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+ * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+ * @note The configuration of the locked GPIO pins can no longer be modified
+ * until the next reset.
+ * @param GPIOx: where x can be (A or B or D) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bit to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * @retval None
+ */
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ uint32_t tmp = 0x00010000;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_LIST_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ tmp |= GPIO_Pin;
+ /* Set LCKK bit */
+ GPIOx->LCKR = tmp;
+ /* Reset LCKK bit */
+ GPIOx->LCKR = GPIO_Pin;
+ /* Set LCKK bit */
+ GPIOx->LCKR = tmp;
+ /* Read LCKK bit */
+ tmp = GPIOx->LCKR;
+ /* Read LCKK bit */
+ tmp = GPIOx->LCKR;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Group2 GPIO Read and Write
+ * @brief GPIO Read and Write
+ *
+@verbatim
+ ===============================================================================
+ ##### GPIO Read and Write #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Reads the specified input port pin.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bit to read.
+ * @note This parameter can be GPIO_Pin_x where x can be :
+ * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
+ * (0..2, 4, 6, 9..10) for GPIOF.
+ * @retval The input port pin value.
+ */
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ uint8_t bitstatus = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+ if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
+ {
+ bitstatus = (uint8_t)Bit_SET;
+ }
+ else
+ {
+ bitstatus = (uint8_t)Bit_RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Reads the specified input port pin.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @retval The input port pin value.
+ */
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ return ((uint16_t)GPIOx->IDR);
+}
+
+/**
+ * @brief Reads the specified output data port bit.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @param GPIO_Pin: Specifies the port bit to read.
+ * @note This parameter can be GPIO_Pin_x where x can be :
+ * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
+ * (0..2, 4, 6, 9..10) for GPIOF.
+ * @retval The output port pin value.
+ */
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ uint8_t bitstatus = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+ if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
+ {
+ bitstatus = (uint8_t)Bit_SET;
+ }
+ else
+ {
+ bitstatus = (uint8_t)Bit_RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Reads the specified GPIO output data port.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @retval GPIO output data port value.
+ */
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ return ((uint16_t)GPIOx->ODR);
+}
+
+/**
+ * @brief Sets the selected data port bits.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bits to be written.
+ * @note This parameter can be GPIO_Pin_x where x can be :
+ * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
+ * (0..2, 4, 6, 9..10) for GPIOF.
+ * @retval None
+ */
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ GPIOx->BSRR = GPIO_Pin;
+}
+
+/**
+ * @brief Clears the selected data port bits.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bits to be written.
+ * @note This parameter can be GPIO_Pin_x where x can be :
+ * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
+ * (0..2, 4, 6, 9..10) for GPIOF.
+ * @retval None
+ */
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ GPIOx->BRR = GPIO_Pin;
+}
+
+/**
+ * @brief Sets or clears the selected data port bit.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bit to be written.
+ * @note This parameter can be GPIO_Pin_x where x can be :
+ * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
+ * (0..2, 4, 6, 9..10) for GPIOF.
+ * @param BitVal: specifies the value to be written to the selected bit.
+ * This parameter can be one of the BitAction enumeration values:
+ * @arg Bit_RESET: to clear the port pin
+ * @arg Bit_SET: to set the port pin
+ * @retval None
+ */
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+ assert_param(IS_GPIO_BIT_ACTION(BitVal));
+
+ if (BitVal != Bit_RESET)
+ {
+ GPIOx->BSRR = GPIO_Pin;
+ }
+ else
+ {
+ GPIOx->BRR = GPIO_Pin ;
+ }
+}
+
+/**
+ * @brief Writes data to the specified GPIO data port.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @param PortVal: specifies the value to be written to the port output data
+ * register.
+ * @retval None
+ */
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ GPIOx->ODR = PortVal;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Group3 GPIO Alternate functions configuration functions
+ * @brief GPIO Alternate functions configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### GPIO Alternate functions configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Writes data to the specified GPIO data port.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @param GPIO_PinSource: specifies the pin for the Alternate function.
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).
+ * @param GPIO_AF: selects the pin to be used as Alternate function.
+ * This parameter can be one of the following value:
+ * @arg GPIO_AF_0: JTCK-SWCLK, JTDI, JTDO/TRACESW0, JTMS-SWDAT, MCO, NJTRST,
+ * TRACED, TRACECK.
+ * @arg GPIO_AF_1: OUT, TIM2, TIM15, TIM16, TIM17.
+ * @arg GPIO_AF_2: COMP1_OUT, TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16.
+ * @arg GPIO_AF_3: COMP7_OUT, TIM8, TIM15, Touch, HRTIM.
+ * @arg GPIO_AF_4: I2C1, I2C2, TIM1, TIM8, TIM16, TIM17.
+ * @arg GPIO_AF_5: IR_OUT, I2S2, I2S3, SPI1, SPI2, TIM8, USART4, USART5
+ * @arg GPIO_AF_6: IR_OUT, I2S2, I2S3, SPI2, SPI3, TIM1, TIM8
+ * @arg GPIO_AF_7: AOP2_OUT, CAN, COMP3_OUT, COMP5_OUT, COMP6_OUT, USART1,
+ * USART2, USART3.
+ * @arg GPIO_AF_8: COMP1_OUT, COMP2_OUT, COMP3_OUT, COMP4_OUT, COMP5_OUT,
+ * COMP6_OUT.
+ * @arg GPIO_AF_9: AOP4_OUT, CAN, TIM1, TIM8, TIM15.
+ * @arg GPIO_AF_10: AOP1_OUT, AOP3_OUT, TIM2, TIM3, TIM4, TIM8, TIM17.
+ * @arg GPIO_AF_11: TIM1, TIM8.
+ * @arg GPIO_AF_12: TIM1, HRTIM.
+ * @arg GPIO_AF_13: HRTIM, AOP2_OUT.
+ * @arg GPIO_AF_14: USBDM, USBDP.
+ * @arg GPIO_AF_15: OUT.
+ * @note The pin should already been configured in Alternate Function mode(AF)
+ * using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+ * @note Refer to the Alternate function mapping table in the device datasheet
+ * for the detailed mapping of the system and peripherals alternate
+ * function I/O pins.
+ * @retval None
+ */
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
+{
+ uint32_t temp = 0x00;
+ uint32_t temp_2 = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
+ assert_param(IS_GPIO_AF(GPIO_AF));
+
+ temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
+ GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
+ temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
+ GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_gpio.h Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,410 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_gpio.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the GPIO
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_GPIO_H
+#define __STM32F30x_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+ ((PERIPH) == GPIOB) || \
+ ((PERIPH) == GPIOC) || \
+ ((PERIPH) == GPIOD) || \
+ ((PERIPH) == GPIOE) || \
+ ((PERIPH) == GPIOF))
+
+#define IS_GPIO_LIST_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+ ((PERIPH) == GPIOB) || \
+ ((PERIPH) == GPIOD))
+/** @defgroup Configuration_Mode_enumeration
+ * @{
+ */
+typedef enum
+{
+ GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
+ GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
+ GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */
+ GPIO_Mode_AN = 0x03 /*!< GPIO Analog In/Out Mode */
+}GPIOMode_TypeDef;
+
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)|| ((MODE) == GPIO_Mode_OUT) || \
+ ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
+/**
+ * @}
+ */
+
+/** @defgroup Output_type_enumeration
+ * @{
+ */
+typedef enum
+{
+ GPIO_OType_PP = 0x00,
+ GPIO_OType_OD = 0x01
+}GPIOOType_TypeDef;
+
+#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
+
+/**
+ * @}
+ */
+
+/** @defgroup Output_Maximum_frequency_enumeration
+ * @{
+ */
+typedef enum
+{
+ GPIO_Speed_Level_1 = 0x01, /*!< Fast Speed */
+ GPIO_Speed_Level_2 = 0x02, /*!< Meduim Speed */
+ GPIO_Speed_Level_3 = 0x03 /*!< High Speed */
+}GPIOSpeed_TypeDef;
+
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_Level_1) || ((SPEED) == GPIO_Speed_Level_2) || \
+ ((SPEED) == GPIO_Speed_Level_3))
+/**
+ * @}
+ */
+
+/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration
+ * @{
+ */
+typedef enum
+{
+ GPIO_PuPd_NOPULL = 0x00,
+ GPIO_PuPd_UP = 0x01,
+ GPIO_PuPd_DOWN = 0x02
+}GPIOPuPd_TypeDef;
+
+#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
+ ((PUPD) == GPIO_PuPd_DOWN))
+/**
+ * @}
+ */
+
+/** @defgroup Bit_SET_and_Bit_RESET_enumeration
+ * @{
+ */
+typedef enum
+{
+ Bit_RESET = 0,
+ Bit_SET
+}BitAction;
+
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
+/**
+ * @}
+ */
+
+/**
+ * @brief GPIO Init structure definition
+ */
+typedef struct
+{
+ uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_pins_define */
+
+ GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIOMode_TypeDef */
+
+ GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIOSpeed_TypeDef */
+
+ GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.
+ This parameter can be a value of @ref GPIOOType_TypeDef */
+
+ GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+ This parameter can be a value of @ref GPIOPuPd_TypeDef */
+}GPIO_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants
+ * @{
+ */
+
+/** @defgroup GPIO_pins_define
+ * @{
+ */
+#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
+#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
+#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
+#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
+#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
+#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
+#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
+#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
+#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
+#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
+#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
+#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
+#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
+#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
+#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
+#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
+#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
+
+#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)
+
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
+ ((PIN) == GPIO_Pin_1) || \
+ ((PIN) == GPIO_Pin_2) || \
+ ((PIN) == GPIO_Pin_3) || \
+ ((PIN) == GPIO_Pin_4) || \
+ ((PIN) == GPIO_Pin_5) || \
+ ((PIN) == GPIO_Pin_6) || \
+ ((PIN) == GPIO_Pin_7) || \
+ ((PIN) == GPIO_Pin_8) || \
+ ((PIN) == GPIO_Pin_9) || \
+ ((PIN) == GPIO_Pin_10) || \
+ ((PIN) == GPIO_Pin_11) || \
+ ((PIN) == GPIO_Pin_12) || \
+ ((PIN) == GPIO_Pin_13) || \
+ ((PIN) == GPIO_Pin_14) || \
+ ((PIN) == GPIO_Pin_15))
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Pin_sources
+ * @{
+ */
+#define GPIO_PinSource0 ((uint8_t)0x00)
+#define GPIO_PinSource1 ((uint8_t)0x01)
+#define GPIO_PinSource2 ((uint8_t)0x02)
+#define GPIO_PinSource3 ((uint8_t)0x03)
+#define GPIO_PinSource4 ((uint8_t)0x04)
+#define GPIO_PinSource5 ((uint8_t)0x05)
+#define GPIO_PinSource6 ((uint8_t)0x06)
+#define GPIO_PinSource7 ((uint8_t)0x07)
+#define GPIO_PinSource8 ((uint8_t)0x08)
+#define GPIO_PinSource9 ((uint8_t)0x09)
+#define GPIO_PinSource10 ((uint8_t)0x0A)
+#define GPIO_PinSource11 ((uint8_t)0x0B)
+#define GPIO_PinSource12 ((uint8_t)0x0C)
+#define GPIO_PinSource13 ((uint8_t)0x0D)
+#define GPIO_PinSource14 ((uint8_t)0x0E)
+#define GPIO_PinSource15 ((uint8_t)0x0F)
+
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
+ ((PINSOURCE) == GPIO_PinSource1) || \
+ ((PINSOURCE) == GPIO_PinSource2) || \
+ ((PINSOURCE) == GPIO_PinSource3) || \
+ ((PINSOURCE) == GPIO_PinSource4) || \
+ ((PINSOURCE) == GPIO_PinSource5) || \
+ ((PINSOURCE) == GPIO_PinSource6) || \
+ ((PINSOURCE) == GPIO_PinSource7) || \
+ ((PINSOURCE) == GPIO_PinSource8) || \
+ ((PINSOURCE) == GPIO_PinSource9) || \
+ ((PINSOURCE) == GPIO_PinSource10) || \
+ ((PINSOURCE) == GPIO_PinSource11) || \
+ ((PINSOURCE) == GPIO_PinSource12) || \
+ ((PINSOURCE) == GPIO_PinSource13) || \
+ ((PINSOURCE) == GPIO_PinSource14) || \
+ ((PINSOURCE) == GPIO_PinSource15))
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Alternate_function_selection_define
+ * @{
+ */
+
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF_0 ((uint8_t)0x00) /* JTCK-SWCLK, JTDI, JTDO/TRACESW0, JTMS-SWDAT,
+ MCO, NJTRST, TRACED, TRACECK */
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF_1 ((uint8_t)0x01) /* OUT, TIM2, TIM15, TIM16, TIM17 */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF_2 ((uint8_t)0x02) /* COMP1_OUT, TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16 */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF_3 ((uint8_t)0x03) /* COMP7_OUT, TIM8, TIM15, Touch, HRTIM1 */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF_4 ((uint8_t)0x04) /* I2C1, I2C2, TIM1, TIM8, TIM16, TIM17 */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF_5 ((uint8_t)0x05) /* IR_OUT, I2S2, I2S3, SPI1, SPI2, TIM8, USART4, USART5 */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF_6 ((uint8_t)0x06) /* IR_OUT, I2S2, I2S3, SPI2, SPI3, TIM1, TIM8 */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF_7 ((uint8_t)0x07) /* AOP2_OUT, CAN, COMP3_OUT, COMP5_OUT, COMP6_OUT,
+ USART1, USART2, USART3 */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF_8 ((uint8_t)0x08) /* COMP1_OUT, COMP2_OUT, COMP3_OUT, COMP4_OUT,
+ COMP5_OUT, COMP6_OUT */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF_9 ((uint8_t)0x09) /* AOP4_OUT, CAN, TIM1, TIM8, TIM15 */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF_10 ((uint8_t)0x0A) /* AOP1_OUT, AOP3_OUT, TIM2, TIM3, TIM4, TIM8, TIM17 */
+
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF_11 ((uint8_t)0x0B) /* TIM1, TIM8 */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF_12 ((uint8_t)0x0C) /* TIM1, HRTIM1 */
+
+/**
+ * @brief AF 13 selection
+ */
+#define GPIO_AF_13 ((uint8_t)0x0D) /* HRTIM1, AOP2_OUT */
+
+/**
+ * @brief AF 14 selection
+ */
+#define GPIO_AF_14 ((uint8_t)0x0E) /* USBDM, USBDP */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF_15 ((uint8_t)0x0F) /* OUT */
+
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_0)||((AF) == GPIO_AF_1)||\
+ ((AF) == GPIO_AF_2)||((AF) == GPIO_AF_3)||\
+ ((AF) == GPIO_AF_4)||((AF) == GPIO_AF_5)||\
+ ((AF) == GPIO_AF_6)||((AF) == GPIO_AF_7)||\
+ ((AF) == GPIO_AF_8)||((AF) == GPIO_AF_9)||\
+ ((AF) == GPIO_AF_10)||((AF) == GPIO_AF_11)||\
+ ((AF) == GPIO_AF_12)||((AF) == GPIO_AF_13)||\
+ ((AF) == GPIO_AF_14)||((AF) == GPIO_AF_15))
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Speed_Legacy
+ * @{
+ */
+
+#define GPIO_Speed_10MHz GPIO_Speed_Level_1 /*!< Fast Speed:10MHz */
+#define GPIO_Speed_2MHz GPIO_Speed_Level_2 /*!< Medium Speed:2MHz */
+#define GPIO_Speed_50MHz GPIO_Speed_Level_3 /*!< High Speed:50MHz */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* Function used to set the GPIO configuration to the default reset state *****/
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);
+
+/* Initialization and Configuration functions *********************************/
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+
+/* GPIO Read and Write functions **********************************************/
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
+
+/* GPIO Alternate functions configuration functions ***************************/
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F30x_GPIO_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_hrtim.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,3968 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_hrtim.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief HRTIMx module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the HRTIMx peripheral:
+ * + Initialization/de-initialization methods
+ * + I/O operation methods
+ * + Peripheral Control methods
+ *
+ @verbatim
+================================================================================
+ ##### <HRTIM specific features> #####
+================================================================================
+
+ [..] < HRTIM introduction:
+ (#) The high-resolution timer can generate up to 10 digital signals with
+ highly accurate timings.
+ It is primarily intended to drive power conversion systems such as
+ switch mode power supplies or lighting systems,
+ but can be of general purpose usage, whenever a very fine timing
+ resolution is expected.
+
+ (#) Its modular architecture allows to generate either independent or
+ coupled waveforms.
+ The wave-shape is defined by self-contained timings
+ (using counters and compare units) and a broad range of external events,
+ such as analog or digital feedbacks and synchronisation signals.
+ This allows to produce a large variety of control signal (PWM, phase-shifted,
+ constant Ton,...) and address most of conversion topologies.
+
+ (#) For control and monitoring purposes, the timer has also timing measure
+ capabilities and links to built-in ADC and DAC converters.
+ Last, it features light-load management mode and is able to handle
+ various fault schemes for safe shut-down purposes.
+
+
+ ##### How to use this driver #####
+================================================================================
+ [..] This driver provides functions to configure and program the HRTIM
+ of all stm32f33x devices.
+ These functions are split in 9 groups:
+
+ (#) HRTIM Simple TimeBase management: this group includes all needed functions
+ to configure the HRTIM Timebase unit:
+ (++) Initializes the HRTIMx timer in simple time base mode
+ (++) Start/Stop the time base generation
+ (++) Deinitialize the HRTIM peripheral
+
+
+ (#) HRTIM simple Output Compare management: this group includes all needed
+ functions to configure the Compare unit used in Output compare mode:
+ (++) Initializes the HRTIMx timer time base unit
+ (++) Configure the compare unit in in simple Output Compare mode
+ (++) Start/Stop the Output compare generation
+
+ (#) HRTIM simple PWM management: this group includes all needed
+ functions to configure the Compare unit used in PWM mode:
+ (++) Initializes the HRTIMx timer time base unit
+ (++) Configure the compare unit in in simple PWM mode
+ (++) Start/Stop the PWM generation
+
+ (#) HRTIM simple Capture management: this group includes all needed
+ functions to configure the Capture unit used in Capture mode:
+ (++) Initializes the HRTIMx timer time base unit
+ (++) Configure the compare unit in in simple Capture mode
+ (++) Start/Stop the Capture mode
+
+ (#) HRTIM simple One Pulse management: this group includes all needed
+ functions to configure the Capture unit and Compare unit used in One Pulse mode:
+ (++) Initializes the HRTIMx timer time base unit
+ (++) Configure the compare unit and the capture unit in in simple One Pulse mode
+ (++) Start/Stop the One Pulse mode generation
+
+ (#) HRTIM Waveform management: this group includes all needed
+ functions to configure the HRTIM possible waveform mode:
+ (++) Initializes the HRTIMx timer Master time base unit
+ (++) Initializes the HRTIMx timer Slaves time base unit
+ (++) Configures the HRTIMx timer Compare unit
+ (++) Configures the HRTIMx Slave timer Capture unit
+ (++) Configures the HRTIMx timer Output unit
+ (++) Configures the HRTIMx timer DeadTime / Chopper / Burst features
+ (++) Configures the HRTIMx timer Fault / External event features
+ (++) Configures the HRTIMx timer Synchronization features: Internal/External connection, DACs,...
+ (++) Configures the HRTIMx timer Synchronization features: ADCs Triggers
+ (++) HRTIMx timer Outputs Start/Stop
+ (++) Start/Stop the HRTIMx Timer counters
+
+ (#) HRTIM interrupts, DMA and flags management
+ (++) Enable/Disable interrupt sources
+ (++) Get flags status
+ (++) Clear flags/ Pending bits
+ (++) Enable/Disable DMA requests
+ (++) Configure DMA burst mode
+
+ (#) TIM specific interface management, this group includes all
+ needed functions to use the specific TIM interface:
+ (++) HRTIMx timer DLL calibration
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_hrtim.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup HRTIM
+ * @brief HRTIM driver module
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define HRTIM_FLTR_FLTxEN (HRTIM_FLTR_FLT1EN |\
+ HRTIM_FLTR_FLT2EN |\
+ HRTIM_FLTR_FLT3EN |\
+ HRTIM_FLTR_FLT4EN | \
+ HRTIM_FLTR_FLT5EN)
+
+#define HRTIM_TIMCR_TIMUPDATETRIGGER (HRTIM_TIMUPDATETRIGGER_MASTER |\
+ HRTIM_TIMUPDATETRIGGER_TIMER_A |\
+ HRTIM_TIMUPDATETRIGGER_TIMER_B |\
+ HRTIM_TIMUPDATETRIGGER_TIMER_C |\
+ HRTIM_TIMUPDATETRIGGER_TIMER_D |\
+ HRTIM_TIMUPDATETRIGGER_TIMER_E)
+
+#define HRTIM_TIM_OFFSET (uint32_t)0x00000080
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static uint32_t TimerIdxToTimerId[] =
+{
+ HRTIM_TIMERID_TIMER_A,
+ HRTIM_TIMERID_TIMER_B,
+ HRTIM_TIMERID_TIMER_C,
+ HRTIM_TIMERID_TIMER_D,
+ HRTIM_TIMERID_TIMER_E,
+ HRTIM_TIMERID_MASTER,
+};
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+static void HRTIM_MasterBase_Config(HRTIM_TypeDef* HRTIMx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruc);
+static void HRTIM_TimingUnitBase_Config(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
+static void HRTIM_MasterWaveform_Config(HRTIM_TypeDef * HRTIMx, HRTIM_TimerInitTypeDef * TimerInit);
+static void HRTIM_TimingUnitWaveform_Config(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ HRTIM_TimerInitTypeDef * TimerInit);
+static void HRTIM_CompareUnitConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t CompareUnit,
+ HRTIM_CompareCfgTypeDef * CompareCfg);
+static void HRTIM_CaptureUnitConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t CaptureUnit,
+ uint32_t Event);
+static void HRTIM_OutputConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t Output,
+ HRTIM_OutputCfgTypeDef * OutputCfg);
+static void HRTIM_ExternalEventConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t Event,
+ HRTIM_EventCfgTypeDef * EventCfg);
+static void HRTIM_TIM_ResetConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t Event);
+ /** @defgroup HRTIM_Private_Functions
+ * @{
+ */
+
+/** @defgroup HRTIM_Group1 Initialization/de-initialization methods
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization/de-initialization methods #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+)Initializes timer in basic time base mode
+ (+)Initializes timer in basic OC mode
+ (+)Initializes timer in basic PWM mode
+ (+)Initializes timer in basic Capture mode
+ (+)Initializes timer in One Pulse mode
+ (+)Initializes a timer operating in waveform mode
+ (+)De-initializes the HRTIMx timer
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the HRTIMx timer in basic time base mode
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 for master timer
+ * @arg 0x1 to 0x5 for timers A to E
+ * @note The time-base unit initialization parameters specify:
+ * The timer counter operating mode (continuous, one shot)
+ * The timer clock prescaler
+ * The timer period
+ * The timer repetition counter.
+ * @retval None
+ */
+void HRTIM_SimpleBase_Init(HRTIM_TypeDef* HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+ assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode));
+
+ if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+ {
+ /* Configure master timer */
+ HRTIM_MasterBase_Config(HRTIMx, HRTIM_BaseInitStruct);
+ }
+ else
+ {
+ /* Configure timing unit */
+ HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
+ }
+}
+
+/**
+ * @brief De-initializes a timer operating in all mode
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @retval None
+ */
+void HRTIM_DeInit(HRTIM_TypeDef* HRTIMx)
+{
+ /* Check the parameters */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_HRTIM1, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_HRTIM1, DISABLE);
+ }
+
+/**
+ * @brief Initializes the HRTIMx timer in basic output compare mode
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x1 to 0x5 for timers A to E
+ * @note Initializes the time-base unit of the timer and prepare it to
+ * operate in output compare mode
+ * @retval None
+ */
+void HRTIM_SimpleOC_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+ assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode));
+
+ /* Configure timing unit */
+ HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
+}
+
+/**
+ * @brief Initializes the HRTIMx timer in basic PWM mode
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x1 to 0x5 for timers A to E
+ * @note Initializes the time-base unit of the timer and prepare it to
+ * operate in capture mode
+ * @retval None
+ */
+void HRTIM_SimplePWM_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+ assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode));
+
+ /* Configure timing unit */
+ HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
+}
+
+/**
+ * @brief Initializes a timer operating in basic capture mode
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x1 to 0x5 for timers A to E
+ * @retval None
+ */
+void HRTIM_SimpleCapture_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+ assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode));
+
+ /* Configure timing unit */
+ HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
+}
+
+/**
+ * @brief Initializes the HRTIMx timer in basic one pulse mode
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x1 to 0x5 for timers A to E
+ * @note Initializes the time-base unit of the timer and prepare it to
+ * operate in one pulse mode. In this mode the counter operates
+ * in single shot mode (retriggerable or not)
+ * @retval None
+ */
+void HRTIM_SimpleOnePulse_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+ assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode));
+
+ /* Configure timing unit */
+ HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
+}
+
+/**
+ * @brief Initializes a timer operating in waveform mode
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 for master timer
+ * @arg 0x1 to 0x5 for timers A to E
+ * @param pTimerInit: pointer to the timer initialization data structure
+ * @retval None
+ */
+void HRTIM_Waveform_Init(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct,
+ HRTIM_TimerInitTypeDef* HRTIM_TimerInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_HALFMODE(HRTIM_TimerInitStruct->HalfModeEnable));
+ assert_param(IS_HRTIM_SYNCSTART(HRTIM_TimerInitStruct->StartOnSync));
+ assert_param(IS_HRTIM_SYNCRESET(HRTIM_TimerInitStruct->ResetOnSync));
+ assert_param(IS_HRTIM_DACSYNC(HRTIM_TimerInitStruct->DACSynchro));
+ assert_param(IS_HRTIM_PRELOAD(HRTIM_TimerInitStruct->PreloadEnable));
+ assert_param(IS_HRTIM_TIMERBURSTMODE(HRTIM_TimerInitStruct->BurstMode));
+ assert_param(IS_HRTIM_UPDATEONREPETITION(HRTIM_TimerInitStruct->RepetitionUpdate));
+
+ if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+ {
+ /* Check parameters */
+ assert_param(IS_HRTIM_UPDATEGATING_MASTER(HRTIM_TimerInitStruct->UpdateGating));
+
+ /* Configure master timer */
+ HRTIM_MasterBase_Config(HRTIMx, HRTIM_BaseInitStruct);
+ HRTIM_MasterWaveform_Config(HRTIMx, HRTIM_TimerInitStruct);
+ }
+ else
+ {
+ /* Check parameters */
+ assert_param(IS_HRTIM_UPDATEGATING_TIM(HRTIM_TimerInitStruct->UpdateGating));
+
+ /* Configure timing unit */
+ HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
+ HRTIM_TimingUnitWaveform_Config(HRTIMx, TimerIdx, HRTIM_TimerInitStruct);
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Group2 I/O operation methods
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation methods #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the HRTIMx data
+ transfers.
+ (+) Starts the DLL calibration.
+ (+) Starts / stops the counter of a timer operating in basic time base mode
+ (+) Starts / stops the output compare signal generation on the designed timer output
+ (+) Starts / stops the PWM output signal generation on the designed timer output
+ (+) Enables / disables a basic capture on the designed capture unit
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the DLL calibration
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param CalibrationRate: DLL calibration period
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CALIBRATIONRATE_7300: 7.3 ms
+ * @arg HRTIM_CALIBRATIONRATE_910: 910 us
+ * @arg HRTIM_CALIBRATIONRATE_114: 114 us
+ * @arg HRTIM_CALIBRATIONRATE_14: 14 us
+ * @retval None
+ */
+void HRTIM_DLLCalibrationStart(HRTIM_TypeDef * HRTIMx, uint32_t CalibrationRate)
+{
+ uint32_t HRTIM_dllcr;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
+
+ /* Configure DLL Calibration */
+ HRTIM_dllcr = (HRTIMx->HRTIM_COMMON).DLLCR;
+
+ /* Set the Calibration rate */
+ HRTIM_dllcr &= ~(HRTIM_DLLCR_CALRTE);
+ HRTIM_dllcr |= CalibrationRate;
+
+ /* Start DLL calibration */
+ HRTIM_dllcr |= HRTIM_DLLCR_CAL;
+
+ /* Update HRTIMx register */
+ (HRTIMx->HRTIM_COMMON).DLLCR = HRTIM_dllcr;
+
+}
+/**
+ * @brief Starts the counter of a timer operating in basic time base mode
+ * @param HRTIMx: pointer to HRTIM peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x5 for master timer
+ * @arg 0x0 to 0x4 for timers A to E
+ * @retval None
+ */
+void HRTIM_SimpleBaseStart(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+
+ /* Enable the timer counter */
+ __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
+}
+
+/**
+ * @brief Stops the counter of a timer operating in basic time base mode
+ * @param HRTIMx: pointer to HRTIM peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x5 for master timer
+ * @arg 0x0 to 0x4 for timers A to E
+ * @retval None
+ */
+void HRTIM_SimpleBaseStop(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+
+ /* Disable the timer counter */
+ __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
+}
+
+/**
+ * @brief Starts the output compare signal generation on the designed timer output
+ * @param HRTIMx: pointer to HRTIM peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param OCChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval None
+ */
+void HRTIM_SimpleOCStart(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t OCChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
+
+ /* Enable the timer output */
+ (HRTIMx->HRTIM_COMMON).OENR |= OCChannel;
+
+ /* Enable the timer counter */
+ __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
+
+}
+
+/**
+ * @brief Stops the output compare signal generation on the designed timer output
+ * @param HRTIMx: pointer to HRTIM peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param OCChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval None
+ */
+void HRTIM_SimpleOCStop(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t OCChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
+
+ /* Disable the timer output */
+ HRTIMx->HRTIM_COMMON.DISR |= OCChannel;
+
+ /* Disable the timer counter */
+ __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
+}
+
+/**
+ * @brief Starts the PWM output signal generation on the designed timer output
+ * @param HRTIMx: pointer to HRTIM peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param PWMChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval None
+ */
+void HRTIM_SimplePWMStart(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
+
+ /* Enable the timer output */
+ HRTIMx->HRTIM_COMMON.OENR |= PWMChannel;
+
+ /* Enable the timer counter */
+ __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
+}
+
+/**
+ * @brief Stops the PWM output signal generation on the designed timer output
+ * @param HRTIMx: pointer to HRTIM peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param PWMChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval None
+ */
+void HRTIM_SimplePWMStop(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
+
+ /* Disable the timer output */
+ HRTIMx->HRTIM_COMMON.DISR |= PWMChannel;
+
+ /* Disable the timer counter */
+ __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
+}
+
+/**
+ * @brief Enables a basic capture on the designed capture unit
+ * @param HRTIMx: pointer to HRTIM peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param CaptureChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+ * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+ * @retval None
+ * @note The external event triggering the capture is available for all timing
+ * units. It can be used directly and is active as soon as the timing
+ * unit counter is enabled.
+ */
+void HRTIM_SimpleCaptureStart(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel)
+{
+ /* Enable the timer counter */
+ __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
+
+}
+
+/**
+ * @brief Disables a basic capture on the designed capture unit
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param CaptureChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+ * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+ * @retval None
+ */
+void HRTIM_SimpleCaptureStop(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
+
+ /* Set the capture unit trigger */
+ switch (CaptureChannel)
+ {
+ case HRTIM_CAPTUREUNIT_1:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
+ }
+ break;
+ case HRTIM_CAPTUREUNIT_2:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Disable the timer counter */
+ if ((HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR == HRTIM_CAPTURETRIGGER_NONE) &&
+ (HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR == HRTIM_CAPTURETRIGGER_NONE))
+ {
+ __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
+ }
+
+}
+
+/**
+ * @brief Enables the basic one pulse signal generation on the designed output
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param OnePulseChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval None
+ */
+void HRTIM_SimpleOnePulseStart(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t OnePulseChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
+
+ /* Enable the timer output */
+ HRTIMx->HRTIM_COMMON.OENR |= OnePulseChannel;
+
+ /* Enable the timer counter */
+ __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
+}
+
+/**
+ * @brief Disables the basic one pulse signal generation on the designed output
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param OnePulseChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval None
+ */
+void HRTIM_SimpleOnePulseStop(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t OnePulseChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
+
+ /* Disable the timer output */
+ HRTIMx->HRTIM_COMMON.DISR |= OnePulseChannel;
+
+ /* Disable the timer counter */
+ __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
+}
+
+/**
+ * @brief Starts the counter of the designated timer(s) operating in waveform mode
+ * Timers can be combined (ORed) to allow for simultaneous counter start
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimersToStart: Timer counter(s) to start
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_TIMERID_MASTER
+ * @arg HRTIM_TIMERID_TIMER_A
+ * @arg HRTIM_TIMERID_TIMER_B
+ * @arg HRTIM_TIMERID_TIMER_C
+ * @arg HRTIM_TIMERID_TIMER_D
+ * @arg HRTIM_TIMERID_TIMER_E
+ * @retval None
+ */
+void HRTIM_WaveformCounterStart(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimersToStart)
+{
+ /* Enable timer(s) counter */
+ HRTIMx->HRTIM_MASTER.MCR |= TimersToStart;
+}
+
+/**
+ * @brief Stops the counter of the designated timer(s) operating in waveform mode
+ * Timers can be combined (ORed) to allow for simultaneous counter stop
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimersToStop: Timer counter(s) to stop
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_TIMER_MASTER
+ * @arg HRTIM_TIMER_A
+ * @arg HRTIM_TIMER_B
+ * @arg HRTIM_TIMER_C
+ * @arg HRTIM_TIMER_D
+ * @arg HRTIM_TIMER_E
+ * @retval None
+ */
+void HRTIM_WaveformCounterStop(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimersToStop)
+{
+ /* Disable timer(s) counter */
+ HRTIMx->HRTIM_MASTER.MCR &= ~TimersToStop;
+}
+
+/**
+ * @brief Enables the generation of the waveform signal on the designated output(s)
+ * Outputs can be combined (ORed) to allow for simultaneous output enabling
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param OutputsToStart: Timer output(s) to enable
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval None
+ */
+void HRTIM_WaveformOutputStart(HRTIM_TypeDef * HRTIMx,
+ uint32_t OutputsToStart)
+{
+ /* Enable the HRTIM outputs */
+ HRTIMx->HRTIM_COMMON.OENR = OutputsToStart;
+}
+
+/**
+ * @brief Disables the generation of the waveform signal on the designated output(s)
+ * Outputs can be combined (ORed) to allow for simultaneous output disabling
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param OutputsToStop: Timer output(s) to disable
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval None
+ */
+void HRTIM_WaveformOutputStop(HRTIM_TypeDef * HRTIMx,
+ uint32_t OutputsToStop)
+{
+ /* Disable the HRTIM outputs */
+ HRTIMx->HRTIM_COMMON.DISR = OutputsToStop;
+}
+
+/**
+ * @brief Enables or disables the Master and slaves interrupt request
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param HRTIM_IT: specifies the HRTIM interrupts sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt source
+ * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt source
+ * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt Interrupt source
+ * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 Interrupt source
+ * @arg HRTIM_MASTER_IT_MREP: Master Repetition Interrupt source
+ * @arg HRTIM_MASTER_IT_SYNC: Synchronization input Interrupt source
+ * @arg HRTIM_MASTER_IT_MUPD: Master update Interrupt source
+ * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 Interrupt source
+ * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 Interrupt source
+ * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 Interrupt source
+ * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 Interrupt source
+ * @arg HRTIM_TIM_IT_REP: Timer repetition Interrupt source
+ * @arg HRTIM_TIM_IT_UPD: Timer update Interrupt source
+ * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 Interrupt source
+ * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 Interrupt source
+ * @arg HRTIM_TIM_IT_SET1: Timer output 1 set Interrupt source
+ * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset Interrupt source
+ * @arg HRTIM_TIM_IT_SET2: Timer output 2 set Interrupt source
+ * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset Interrupt source
+ * @arg HRTIM_TIM_IT_RST: Timer reset Interrupt source
+ * @arg HRTIM_TIM_IT_DLYPRT1: Timer delay protection Interrupt source
+ * @param NewState: new state of the TIM interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void HRTIM_ITConfig(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT, FunctionalState NewState)
+{
+ if(TimerIdx != HRTIM_TIMERINDEX_MASTER)
+ {
+ if(NewState != DISABLE)
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER |= HRTIM_IT;
+ }
+ else
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER &= ~HRTIM_IT;
+ }
+ }
+ else
+ {
+ if(NewState != DISABLE)
+ {
+ HRTIMx->HRTIM_MASTER.MDIER |= HRTIM_IT;
+ }
+ else
+ {
+ HRTIMx->HRTIM_MASTER.MDIER &= ~HRTIM_IT;
+ }
+ }
+}
+
+/**
+ * @brief Enables or disables the common interrupt request
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param HRTIM_IT: specifies the HRTIM interrupts sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_IT_FLT1: Fault 1 interrupt source
+ * @arg HRTIM_IT_FLT2: Fault 2 interrupt source
+ * @arg HRTIM_IT_FLT3: Fault 3 interrupt Interrupt source
+ * @arg HRTIM_IT_FLT4: Fault 4 Interrupt source
+ * @arg HRTIM_IT_FLT5: Fault 5 Interrupt source
+ * @arg HRTIM_IT_SYSFLT: System Fault Interrupt source
+ * @arg HRTIM_IT_DLLRDY: DLL ready Interrupt source
+ * @arg HRTIM_IT_BMPER: Burst mode period Interrupt source
+ * @param NewState: new state of the TIM interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void HRTIM_ITCommonConfig(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT, FunctionalState NewState)
+{
+ if(NewState != DISABLE)
+ {
+ HRTIMx->HRTIM_COMMON.IER |= HRTIM_CommonIT;
+ }
+ else
+ {
+ HRTIMx->HRTIM_COMMON.IER &= ~HRTIM_CommonIT;
+ }
+}
+
+/**
+ * @brief Clears the Master and slaves interrupt flags
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param HRTIM_FLAG: specifies the HRTIM flags sources to be cleared.
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_MASTER_FLAG_MCMP1: Master compare 1 interrupt flag
+ * @arg HRTIM_MASTER_FLAG_MCMP2: Master compare 2 interrupt flag
+ * @arg HRTIM_MASTER_FLAG_MCMP3: Master compare 3 interrupt Interrupt flag
+ * @arg HRTIM_MASTER_FLAG_MCMP4: Master compare 4 Interrupt flag
+ * @arg HRTIM_MASTER_FLAG_MREP: Master Repetition Interrupt flag
+ * @arg HRTIM_MASTER_FLAG_SYNC: Synchronization input Interrupt flag
+ * @arg HRTIM_MASTER_FLAG_MUPD: Master update Interrupt flag
+ * @arg HRTIM_TIM_FLAG_CMP1: Timer compare 1 Interrupt flag
+ * @arg HRTIM_TIM_FLAG_CMP2: Timer compare 2 Interrupt flag
+ * @arg HRTIM_TIM_FLAG_CMP3: Timer compare 3 Interrupt flag
+ * @arg HRTIM_TIM_FLAG_CMP4: Timer compare 4 Interrupt flag
+ * @arg HRTIM_TIM_FLAG_REP: Timer repetition Interrupt flag
+ * @arg HRTIM_TIM_FLAG_UPD: Timer update Interrupt flag
+ * @arg HRTIM_TIM_FLAG_CPT1: Timer capture 1 Interrupt flag
+ * @arg HRTIM_TIM_FLAG_CPT2: Timer capture 2 Interrupt flag
+ * @arg HRTIM_TIM_FLAG_SET1: Timer output 1 set Interrupt flag
+ * @arg HRTIM_TIM_FLAG_RST1: Timer output 1 reset Interrupt flag
+ * @arg HRTIM_TIM_FLAG_SET2: Timer output 2 set Interrupt flag
+ * @arg HRTIM_TIM_FLAG_RST2: Timer output 2 reset Interrupt flag
+ * @arg HRTIM_TIM_FLAG_RST: Timer reset Interrupt flag
+ * @arg HRTIM_TIM_FLAG_DLYPRT1: Timer delay protection Interrupt flag
+ * @retval None
+ */
+void HRTIM_ClearFlag(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG)
+{
+ if(TimerIdx != HRTIM_TIMERINDEX_MASTER)
+ {
+ HRTIMx->HRTIM_MASTER.MICR |= HRTIM_FLAG;
+ }
+ else
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxICR |= HRTIM_FLAG;
+ }
+}
+
+/**
+ * @brief Clears the common interrupt flags
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param HRTIM_FLAG: specifies the HRTIM flags to be cleared.
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_FLAG_FLT1: Fault 1 interrupt flag
+ * @arg HRTIM_FLAG_FLT2: Fault 2 interrupt flag
+ * @arg HRTIM_FLAG_FLT3: Fault 3 interrupt Interrupt flag
+ * @arg HRTIM_FLAG_FLT4: Fault 4 Interrupt flag
+ * @arg HRTIM_FLAG_FLT5: Fault 5 Interrupt flag
+ * @arg HRTIM_FLAG_SYSFLT: System Fault Interrupt flag
+ * @arg HRTIM_FLAG_DLLRDY: DLL ready Interrupt flag
+ * @arg HRTIM_FLAG_BMPER: Burst mode period Interrupt flag
+ * @retval None
+ */
+void HRTIM_ClearCommonFlag(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonFLAG)
+{
+ HRTIMx->HRTIM_COMMON.ICR |= HRTIM_CommonFLAG;
+}
+
+/**
+ * @brief Clears the Master and slaves interrupt request pending bits
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param HRTIM_IT: specifies the HRTIM interrupts sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt source
+ * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt source
+ * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt Interrupt source
+ * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 Interrupt source
+ * @arg HRTIM_MASTER_IT_MREP: Master Repetition Interrupt source
+ * @arg HRTIM_MASTER_IT_SYNC: Synchronization input Interrupt source
+ * @arg HRTIM_MASTER_IT_MUPD: Master update Interrupt source
+ * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 Interrupt source
+ * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 Interrupt source
+ * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 Interrupt source
+ * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 Interrupt source
+ * @arg HRTIM_TIM_IT_REP: Timer repetition Interrupt source
+ * @arg HRTIM_TIM_IT_UPD: Timer update Interrupt source
+ * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 Interrupt source
+ * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 Interrupt source
+ * @arg HRTIM_TIM_IT_SET1: Timer output 1 set Interrupt source
+ * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset Interrupt source
+ * @arg HRTIM_TIM_IT_SET2: Timer output 2 set Interrupt source
+ * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset Interrupt source
+ * @arg HRTIM_TIM_IT_RST: Timer reset Interrupt source
+ * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection Interrupt source
+ * @retval None
+ */
+void HRTIM_ClearITPendingBit(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT)
+{
+ if(TimerIdx != HRTIM_TIMERINDEX_MASTER)
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxICR |= HRTIM_IT;
+ }
+ else
+ {
+ HRTIMx->HRTIM_MASTER.MICR |= HRTIM_IT;
+ }
+}
+
+/**
+ * @brief Clears the common interrupt pending bits
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param HRTIM_IT: specifies the HRTIM interrupts sources to be cleared.
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_IT_FLT1: Fault 1 interrupt source
+ * @arg HRTIM_IT_FLT2: Fault 2 interrupt source
+ * @arg HRTIM_IT_FLT3: Fault 3 interrupt Interrupt source
+ * @arg HRTIM_IT_FLT4: Fault 4 Interrupt source
+ * @arg HRTIM_IT_FLT5: Fault 5 Interrupt source
+ * @arg HRTIM_IT_SYSFLT: System Fault Interrupt source
+ * @arg HRTIM_IT_DLLRDY: DLL ready Interrupt source
+ * @arg HRTIM_IT_BMPER: Burst mode period Interrupt source
+ * @retval None
+ */
+void HRTIM_ClearCommonITPendingBit(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT)
+{
+ HRTIMx->HRTIM_COMMON.ICR |= HRTIM_CommonIT;
+}
+
+
+/**
+ * @brief Checks whether the specified HRTIM flag is set or not.
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param HRTIM_FLAG: specifies the HRTIM flags to check.
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_MASTER_FLAG_MCMP1: Master compare 1 interrupt flag
+ * @arg HRTIM_MASTER_FLAG_MCMP2: Master compare 2 interrupt flag
+ * @arg HRTIM_MASTER_FLAG_MCMP3: Master compare 3 interrupt Interrupt flag
+ * @arg HRTIM_MASTER_FLAG_MCMP4: Master compare 4 Interrupt flag
+ * @arg HRTIM_MASTER_FLAG_MREP: Master Repetition Interrupt flag
+ * @arg HRTIM_MASTER_FLAG_SYNC: Synchronization input Interrupt flag
+ * @arg HRTIM_MASTER_FLAG_MUPD: Master update Interrupt flag
+ * @arg HRTIM_TIM_FLAG_CMP1: Timer compare 1 Interrupt flag
+ * @arg HRTIM_TIM_FLAG_CMP2: Timer compare 2 Interrupt flag
+ * @arg HRTIM_TIM_FLAG_CMP3: Timer compare 3 Interrupt flag
+ * @arg HRTIM_TIM_FLAG_CMP4: Timer compare 4 Interrupt flag
+ * @arg HRTIM_TIM_FLAG_REP: Timer repetition Interrupt flag
+ * @arg HRTIM_TIM_FLAG_UPD: Timer update Interrupt flag
+ * @arg HRTIM_TIM_FLAG_CPT1: Timer capture 1 Interrupt flag
+ * @arg HRTIM_TIM_FLAG_CPT2: Timer capture 2 Interrupt flag
+ * @arg HRTIM_TIM_FLAG_SET1: Timer output 1 set Interrupt flag
+ * @arg HRTIM_TIM_FLAG_RST1: Timer output 1 reset Interrupt flag
+ * @arg HRTIM_TIM_FLAG_SET2: Timer output 2 set Interrupt flag
+ * @arg HRTIM_TIM_FLAG_RST2: Timer output 2 reset Interrupt flag
+ * @arg HRTIM_TIM_FLAG_RST: Timer reset Interrupt flag
+ * @arg HRTIM_TIM_FLAG_DLYPRT: Timer delay protection Interrupt flag
+ * @retval The new state of HRTIM_FLAG (SET or RESET).
+ */
+FlagStatus HRTIM_GetFlagStatus(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ if(TimerIdx != HRTIM_TIMERINDEX_MASTER)
+ {
+ if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_FLAG) != RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+ else
+ {
+ if ((HRTIMx->HRTIM_MASTER.MISR & HRTIM_FLAG) != RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Checks whether the specified HRTIM common flag is set or not.
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param HRTIM_FLAG: specifies the HRTIM flags to check.
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_FLAG_FLT1: Fault 1 interrupt flag
+ * @arg HRTIM_FLAG_FLT2: Fault 2 interrupt flag
+ * @arg HRTIM_FLAG_FLT3: Fault 3 interrupt Interrupt flag
+ * @arg HRTIM_FLAG_FLT4: Fault 4 Interrupt flag
+ * @arg HRTIM_FLAG_FLT5: Fault 5 Interrupt flag
+ * @arg HRTIM_FLAG_SYSFLT: System Fault Interrupt flag
+ * @arg HRTIM_FLAG_DLLRDY: DLL ready Interrupt flag
+ * @arg HRTIM_FLAG_BMPER: Burst mode period Interrupt flag
+ * @retval The new state of HRTIM_FLAG (SET or RESET).
+ */
+FlagStatus HRTIM_GetCommonFlagStatus(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonFLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ if((HRTIMx->HRTIM_COMMON.ISR & HRTIM_CommonFLAG) != RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Checks whether the specified HRTIM interrupt has occurred or not.
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param HRTIM_IT: specifies the HRTIM flags sources to be cleared.
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt
+ * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt
+ * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt Interrupt
+ * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 Interrupt
+ * @arg HRTIM_MASTER_IT_MREP: Master Repetition Interrupt
+ * @arg HRTIM_MASTER_IT_SYNC: Synchronization input Interrupt
+ * @arg HRTIM_MASTER_IT_MUPD: Master update Interrupt
+ * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 Interrupt
+ * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 Interrupt
+ * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 Interrupt
+ * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 Interrupt
+ * @arg HRTIM_TIM_IT_REP: Timer repetition Interrupt
+ * @arg HRTIM_TIM_IT_UPD: Timer update Interrupt
+ * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 Interrupt
+ * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 Interrupt
+ * @arg HRTIM_TIM_IT_SET1: Timer output 1 set Interrupt
+ * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset Interrupt
+ * @arg HRTIM_TIM_IT_SET2: Timer output 2 set Interrupt
+ * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset Interrupt
+ * @arg HRTIM_TIM_IT_RST: Timer reset Interrupt
+ * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection Interrupt
+ * @retval The new state of the HRTIM_IT(SET or RESET).
+ */
+ITStatus HRTIM_GetITStatus(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint16_t itstatus = 0x0, itenable = 0x0;
+
+ if(TimerIdx != HRTIM_TIMERINDEX_MASTER)
+ {
+ itstatus = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_IT;
+
+ itenable = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER & HRTIM_IT;
+ if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+ else
+ {
+ itstatus = HRTIMx->HRTIM_MASTER.MISR & HRTIM_IT;
+
+ itenable = HRTIMx->HRTIM_MASTER.MDIER & HRTIM_IT;
+ if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Checks whether the specified HRTIM common interrupt has occurred or not.
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param HRTIM_IT: specifies the HRTIM interrupt source to check.
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_IT_FLT1: Fault 1 interrupt
+ * @arg HRTIM_IT_FLT2: Fault 2 interrupt
+ * @arg HRTIM_IT_FLT3: Fault 3 interrupt Interrupt
+ * @arg HRTIM_IT_FLT4: Fault 4 Interrupt
+ * @arg HRTIM_IT_FLT5: Fault 5 Interrupt
+ * @arg HRTIM_IT_SYSFLT: System Fault Interrupt
+ * @arg HRTIM_IT_DLLRDY: DLL ready Interrupt flag
+ * @arg HRTIM_IT_BMPER: Burst mode period Interrupt
+ * @retval The new state of HRTIM_FLAG (SET or RESET).
+ */
+ITStatus HRTIM_GetCommonITStatus(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT)
+{
+ ITStatus bitstatus = RESET;
+ uint16_t itstatus = 0x0, itenable = 0x0;
+
+ itstatus = HRTIMx->HRTIM_COMMON.ISR & HRTIM_CommonIT;
+ itenable = HRTIMx->HRTIM_COMMON.IER & HRTIM_CommonIT;
+
+ if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ return bitstatus;
+}
+
+/**
+ * @brief Enables or disables the HRTIMx's DMA Requests.
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param HRTIM_DMA: specifies the DMA Request sources.
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA request source
+ * @arg HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA request source
+ * @arg HRTIM_MASTER_DMA_MCMP3: Master compare 3 DMA request source
+ * @arg HRTIM_MASTER_DMA_MCMP4: Master compare 4 DMA request source
+ * @arg HRTIM_MASTER_DMA_MREP: Master Repetition DMA request source
+ * @arg HRTIM_MASTER_DMA_SYNC: Synchronization input DMA request source
+ * @arg HRTIM_MASTER_DMA_MUPD:Master update DMA request source
+ * @arg HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA request source
+ * @arg HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA request source
+ * @arg HRTIM_TIM_DMA_CMP3: Timer compare 3 DMA request source
+ * @arg HRTIM_TIM_DMA_CMP4: Timer compare 4 DMA request source
+ * @arg HRTIM_TIM_DMA_REP: Timer repetition DMA request source
+ * @arg HRTIM_TIM_DMA_UPD: Timer update DMA request source
+ * @arg HRTIM_TIM_DMA_CPT1: Timer capture 1 DMA request source
+ * @arg HRTIM_TIM_DMA_CPT2: Timer capture 2 DMA request source
+ * @arg HRTIM_TIM_DMA_SET1: Timer output 1 set DMA request source
+ * @arg HRTIM_TIM_DMA_RST1: Timer output 1 reset DMA request source
+ * @arg HRTIM_TIM_DMA_SET2: Timer output 2 set DMA request source
+ * @arg HRTIM_TIM_DMA_RST2: Timer output 2 reset DMA request source
+ * @arg HRTIM_TIM_DMA_RST: Timer reset DMA request source
+ * @arg HRTIM_TIM_DMA_DLYPRT: Timer delay protection DMA request source
+ * @param NewState: new state of the DMA Request sources.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void HRTIM_DMACmd(HRTIM_TypeDef* HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_DMA, FunctionalState NewState)
+{
+ if(TimerIdx != HRTIM_TIMERINDEX_MASTER)
+ {
+ if(NewState != DISABLE)
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER |= HRTIM_DMA;
+ }
+ else
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER &= ~HRTIM_DMA;
+ }
+ }
+ else
+ {
+ if(NewState != DISABLE)
+ {
+ HRTIMx->HRTIM_MASTER.MDIER |= HRTIM_DMA;
+ }
+ else
+ {
+ HRTIMx->HRTIM_MASTER.MDIER &= ~HRTIM_DMA;
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Group3 Peripheral Control methods
+ * @brief management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control methods #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the HRTIMx data
+ transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures an output in basic output compare mode
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param OCChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @param pBasicOCChannelCfg: pointer to the basic output compare output configuration structure
+ * @note When the timer operates in basic output compare mode:
+ * Output 1 is implicitely controled by the compare unit 1
+ * Output 2 is implicitely controled by the compare unit 2
+ * Output Set/Reset crossbar is set according to the selected output compare mode:
+ * Toggle: SETxyR = RSTxyR = CMPy
+ * Active: SETxyR = CMPy, RSTxyR = 0
+ * Inactive: SETxy =0, RSTxy = CMPy
+ * @retval None
+ */
+void HRTIM_SimpleOCChannelConfig(HRTIM_TypeDef * HRTIM_,
+ uint32_t TimerIdx,
+ uint32_t OCChannel,
+ HRTIM_BasicOCChannelCfgTypeDef* pBasicOCChannelCfg)
+{
+ uint32_t CompareUnit = HRTIM_COMPAREUNIT_1;
+ HRTIM_CompareCfgTypeDef CompareCfg;
+ HRTIM_OutputCfgTypeDef OutputCfg;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
+ assert_param(IS_HRTIM_BASICOCMODE(pBasicOCChannelCfg->Mode));
+ assert_param(IS_HRTIM_OUTPUTPOLARITY(pBasicOCChannelCfg->Polarity));
+ assert_param(IS_HRTIM_OUTPUTIDLESTATE(pBasicOCChannelCfg->IdleState));
+
+ /* Configure timer compare unit */
+ switch (OCChannel)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ CompareUnit = HRTIM_COMPAREUNIT_1;
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ CompareUnit = HRTIM_COMPAREUNIT_2;
+ }
+ break;
+ default:
+ break;
+ }
+
+ CompareCfg.CompareValue = pBasicOCChannelCfg->Pulse;
+ CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
+ CompareCfg.AutoDelayedTimeout = 0;
+
+ HRTIM_CompareUnitConfig(HRTIM_,
+ TimerIdx,
+ CompareUnit,
+ &CompareCfg);
+
+ /* Configure timer output */
+ OutputCfg.Polarity = pBasicOCChannelCfg->Polarity;
+ OutputCfg.IdleState = pBasicOCChannelCfg->IdleState;
+ OutputCfg.FaultState = HRTIM_OUTPUTFAULTSTATE_NONE;
+ OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
+ OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
+ OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
+
+ switch (pBasicOCChannelCfg->Mode)
+ {
+ case HRTIM_BASICOCMODE_TOGGLE:
+ {
+ if (CompareUnit == HRTIM_COMPAREUNIT_1)
+ {
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
+ }
+ else
+ {
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
+ }
+ OutputCfg.ResetSource = OutputCfg.SetSource;
+ }
+ break;
+ case HRTIM_BASICOCMODE_ACTIVE:
+ {
+ if (CompareUnit == HRTIM_COMPAREUNIT_1)
+ {
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
+ }
+ else
+ {
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
+ }
+ OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
+ }
+ break;
+ case HRTIM_BASICOCMODE_INACTIVE:
+ {
+ if (CompareUnit == HRTIM_COMPAREUNIT_1)
+ {
+ OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP1;
+ }
+ else
+ {
+ OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP2;
+ }
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
+ }
+ break;
+ default:
+ break;
+ }
+
+ HRTIM_OutputConfig(HRTIM_, TimerIdx, OCChannel, &OutputCfg);
+}
+
+/**
+ * @brief Configures an output in basic PWM mode
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param PWMChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @param pBasicPWMChannelCfg: pointer to the basic PWM output configuration structure
+ * @note When the timer operates in basic PWM output mode:
+ * Output 1 is implicitly controled by the compare unit 1
+ * Output 2 is implicitly controled by the compare unit 2
+ * Output Set/Reset crossbar is set as follows:
+ * Output 1: SETx1R = CMP1, RSTx1R = PER
+ * Output 2: SETx2R = CMP2, RST2R = PER
+ * @retval None
+ */
+void HRTIM_SimplePWMChannelConfig(HRTIM_TypeDef * HRTIM_,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel,
+ HRTIM_BasicPWMChannelCfgTypeDef* pBasicPWMChannelCfg)
+{
+ uint32_t CompareUnit = HRTIM_COMPAREUNIT_1;
+ HRTIM_CompareCfgTypeDef CompareCfg;
+ HRTIM_OutputCfgTypeDef OutputCfg;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
+ assert_param(IS_HRTIM_OUTPUTPOLARITY(pBasicPWMChannelCfg->Polarity));
+ assert_param(IS_HRTIM_OUTPUTIDLESTATE(pBasicPWMChannelCfg->IdleState));
+
+ /* Configure timer compare unit */
+ switch (PWMChannel)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ CompareUnit = HRTIM_COMPAREUNIT_1;
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ CompareUnit = HRTIM_COMPAREUNIT_2;
+ }
+ break;
+ default:
+ break;
+ }
+
+ CompareCfg.CompareValue = pBasicPWMChannelCfg->Pulse;
+ CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
+ CompareCfg.AutoDelayedTimeout = 0;
+
+ HRTIM_CompareUnitConfig(HRTIM_,
+ TimerIdx,
+ CompareUnit,
+ &CompareCfg);
+
+ /* Configure timer output */
+ OutputCfg.Polarity = pBasicPWMChannelCfg->Polarity;
+ OutputCfg.IdleState = pBasicPWMChannelCfg->IdleState;
+ OutputCfg.FaultState = HRTIM_OUTPUTFAULTSTATE_NONE;
+ OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
+ OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
+ OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
+
+ if (CompareUnit == HRTIM_COMPAREUNIT_1)
+ {
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
+ }
+ else
+ {
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
+ }
+ OutputCfg.ResetSource = HRTIM_OUTPUTSET_TIMPER;
+
+ HRTIM_OutputConfig(HRTIM_, TimerIdx, PWMChannel, &OutputCfg);
+}
+
+/**
+ * @brief Configures a basic capture
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param CaptureChannel: Capture unit
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+ * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+ * @param pBasicCaptureChannelCfg: pointer to the basic capture configuration structure
+ * @note When the timer operates in basic capture mode the capture is triggered
+ * by the designated external event and GPIO input is implicitly used as event source.
+ * The cature can be triggered by a rising edge, a falling edge or both
+ * edges on event channel.
+ * @retval None
+ */
+void HRTIM_SimpleCaptureChannelConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel,
+ HRTIM_BasicCaptureChannelCfgTypeDef* pBasicCaptureChannelCfg)
+{
+ HRTIM_EventCfgTypeDef EventCfg;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
+ assert_param(IS_HRTIM_EVENT(pBasicCaptureChannelCfg->Event));
+ assert_param(IS_HRTIM_EVENTPOLARITY(pBasicCaptureChannelCfg->EventPolarity));
+ assert_param(IS_HRTIM_EVENTSENSITIVITY(pBasicCaptureChannelCfg->EventSensitivity));
+ assert_param(IS_HRTIM_EVENTFILTER(pBasicCaptureChannelCfg->EventFilter));
+
+ /* Configure external event channel */
+ EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
+ EventCfg.Filter = pBasicCaptureChannelCfg->EventFilter;
+ EventCfg.Polarity = pBasicCaptureChannelCfg->EventPolarity;
+ EventCfg.Sensitivity = pBasicCaptureChannelCfg->EventSensitivity;
+ EventCfg.Source = HRTIM_EVENTSRC_1;
+
+ HRTIM_ExternalEventConfig(HRTIMx,
+ pBasicCaptureChannelCfg->Event,
+ &EventCfg);
+
+ /* Memorize capture trigger (will be configured when the capture is started */
+ HRTIM_CaptureUnitConfig(HRTIMx,
+ TimerIdx,
+ CaptureChannel,
+ pBasicCaptureChannelCfg->Event);
+}
+
+/**
+ * @brief Configures an output basic one pulse mode
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param OnePulseChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @param pBasicOnePulseChannelCfg: pointer to the basic one pulse output configuration structure
+ * @note When the timer operates in basic one pulse mode:
+ * the timer counter is implicitly started by the reset event,
+ * the reset of the timer counter is triggered by the designated external event
+ * GPIO input is implicitly used as event source,
+ * Output 1 is implicitly controled by the compare unit 1,
+ * Output 2 is implicitly controled by the compare unit 2.
+ * Output Set/Reset crossbar is set as follows:
+ * Output 1: SETx1R = CMP1, RSTx1R = PER
+ * Output 2: SETx2R = CMP2, RST2R = PER
+ * The counter mode should be HRTIM_MODE_SINGLESHOT_RETRIGGERABLE
+ * @retval None
+ */
+void HRTIM_SimpleOnePulseChannelConfig(HRTIM_TypeDef * HRTIM_,
+ uint32_t TimerIdx,
+ uint32_t OnePulseChannel,
+ HRTIM_BasicOnePulseChannelCfgTypeDef* pBasicOnePulseChannelCfg)
+{
+ uint32_t CompareUnit = HRTIM_COMPAREUNIT_1;
+ HRTIM_CompareCfgTypeDef CompareCfg;
+ HRTIM_OutputCfgTypeDef OutputCfg;
+ HRTIM_EventCfgTypeDef EventCfg;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
+ assert_param(IS_HRTIM_OUTPUTPOLARITY(pBasicOnePulseChannelCfg->OutputPolarity));
+ assert_param(IS_HRTIM_OUTPUTIDLESTATE(pBasicOnePulseChannelCfg->OutputIdleState));
+ assert_param(IS_HRTIM_EVENT(pBasicOnePulseChannelCfg->Event));
+ assert_param(IS_HRTIM_EVENTPOLARITY(pBasicOnePulseChannelCfg->EventPolarity));
+ assert_param(IS_HRTIM_EVENTSENSITIVITY(pBasicOnePulseChannelCfg->EventSensitivity));
+ assert_param(IS_HRTIM_EVENTFILTER(pBasicOnePulseChannelCfg->EventFilter));
+
+ /* Configure timer compare unit */
+ switch (OnePulseChannel)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ CompareUnit = HRTIM_COMPAREUNIT_1;
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ CompareUnit = HRTIM_COMPAREUNIT_2;
+ }
+ break;
+ default:
+ break;
+ }
+
+ CompareCfg.CompareValue = pBasicOnePulseChannelCfg->Pulse;
+ CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
+ CompareCfg.AutoDelayedTimeout = 0;
+
+ HRTIM_CompareUnitConfig(HRTIM_,
+ TimerIdx,
+ CompareUnit,
+ &CompareCfg);
+
+ /* Configure timer output */
+ OutputCfg.Polarity = pBasicOnePulseChannelCfg->OutputPolarity;
+ OutputCfg.IdleState = pBasicOnePulseChannelCfg->OutputIdleState;
+ OutputCfg.FaultState = HRTIM_OUTPUTFAULTSTATE_NONE;
+ OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
+ OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
+ OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
+
+ if (CompareUnit == HRTIM_COMPAREUNIT_1)
+ {
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
+ }
+ else
+ {
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
+ }
+ OutputCfg.ResetSource = HRTIM_OUTPUTSET_TIMPER;
+
+ HRTIM_OutputConfig(HRTIM_,
+ TimerIdx,
+ OnePulseChannel,
+ &OutputCfg);
+
+ /* Configure external event channel */
+ EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
+ EventCfg.Filter = pBasicOnePulseChannelCfg->EventFilter;
+ EventCfg.Polarity = pBasicOnePulseChannelCfg->EventPolarity;
+ EventCfg.Sensitivity = pBasicOnePulseChannelCfg->EventSensitivity;
+ EventCfg.Source = HRTIM_EVENTSRC_1;
+
+ HRTIM_ExternalEventConfig(HRTIM_,
+ pBasicOnePulseChannelCfg->Event,
+ &EventCfg);
+
+ /* Configure the timer reset register */
+ HRTIM_TIM_ResetConfig(HRTIM_,
+ TimerIdx,
+ pBasicOnePulseChannelCfg->Event);
+}
+
+/**
+ * @brief Configures the general behavior of a timer operating in waveform mode
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param pTimerCfg: pointer to the timer configuration structure
+ * @note When the timer operates in waveform mode, all the features supported by
+ * the HRTIMx are available without any limitation.
+ * @retval None
+ */
+void HRTIM_WaveformTimerConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ HRTIM_TimerCfgTypeDef * pTimerCfg)
+{
+ uint32_t HRTIM_timcr;
+ uint32_t HRTIM_timfltr;
+ uint32_t HRTIM_timoutr;
+ uint32_t HRTIM_timrstr;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_TIMPUSHPULLMODE(pTimerCfg->PushPull));
+ assert_param(IS_HRTIM_TIMFAULTENABLE(pTimerCfg->FaultEnable));
+ assert_param(IS_HRTIM_TIMFAULTLOCK(pTimerCfg->FaultLock));
+ assert_param(IS_HRTIM_TIMDEADTIMEINSERTION(pTimerCfg->DeadTimeInsertion));
+ assert_param(IS_HRTIM_TIMDELAYEDPROTECTION(pTimerCfg->DelayedProtectionMode));
+ assert_param(IS_HRTIM_TIMUPDATETRIGGER(pTimerCfg->UpdateTrigger));
+ assert_param(IS_HRTIM_TIMRESETTRIGGER(pTimerCfg->ResetTrigger));
+ assert_param(IS_HRTIM_TIMUPDATEONRESET(pTimerCfg->ResetUpdate));
+
+ /* Configure timing unit (Timer A to Timer E) */
+ HRTIM_timcr = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR;
+ HRTIM_timfltr = HRTIMx->HRTIM_TIMERx[TimerIdx].FLTxR;
+ HRTIM_timoutr = HRTIMx->HRTIM_TIMERx[TimerIdx].OUTxR;
+ HRTIM_timrstr = HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR;
+
+ /* Set the push-pull mode */
+ HRTIM_timcr &= ~(HRTIM_TIMCR_PSHPLL);
+ HRTIM_timcr |= pTimerCfg->PushPull;
+
+ /* Enable/Disable registers update on timer counter reset */
+ HRTIM_timcr &= ~(HRTIM_TIMCR_TRSTU);
+ HRTIM_timcr |= pTimerCfg->ResetUpdate;
+
+ /* Set the timer update trigger */
+ HRTIM_timcr &= ~(HRTIM_TIMCR_TIMUPDATETRIGGER);
+ HRTIM_timcr |= pTimerCfg->UpdateTrigger;
+
+ /* Enable/Disable the fault channel at timer level */
+ HRTIM_timfltr &= ~(HRTIM_FLTR_FLTxEN);
+ HRTIM_timfltr |= (pTimerCfg->FaultEnable & HRTIM_FLTR_FLTxEN);
+
+ /* Lock/Unlock fault sources at timer level */
+ HRTIM_timfltr &= ~(HRTIM_FLTR_FLTCLK);
+ HRTIM_timfltr |= pTimerCfg->FaultLock;
+
+ /* Enable/Disable dead time insertion at timer level */
+ HRTIM_timoutr &= ~(HRTIM_OUTR_DTEN);
+ HRTIM_timoutr |= pTimerCfg->DeadTimeInsertion;
+
+ /* Enable/Disable delayed protection at timer level */
+ HRTIM_timoutr &= ~(HRTIM_OUTR_DLYPRT| HRTIM_OUTR_DLYPRTEN);
+ HRTIM_timoutr |= pTimerCfg->DelayedProtectionMode;
+
+ /* Set the timer counter reset trigger */
+ HRTIM_timrstr = pTimerCfg->ResetTrigger;
+
+ /* Update the HRTIMx registers */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR = HRTIM_timcr;
+ HRTIMx->HRTIM_TIMERx[TimerIdx].FLTxR = HRTIM_timfltr;
+ HRTIMx->HRTIM_TIMERx[TimerIdx].OUTxR = HRTIM_timoutr;
+ HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_timrstr;
+ }
+
+/**
+ * @brief Configures the compare unit of a timer operating in waveform mode
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * 0xFF for master timer
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param CompareUnit: Compare unit to configure
+ * This parameter can be one of the following values:
+ * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
+ * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
+ * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
+ * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
+ * @param pCompareCfg: pointer to the compare unit configuration structure
+ * @note When auto delayed mode is required for compare unit 2 or compare unit 4,
+ * application has to configure separately the capture unit. Capture unit
+ * to configure in that case depends on the compare unit auto delayed mode
+ * is applied to (see below):
+ * Auto delayed on output compare 2: capture unit 1 must be configured
+ * Auto delayed on output compare 4: capture unit 2 must be configured
+ * @retval None
+ */
+ void HRTIM_WaveformCompareConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t CompareUnit,
+ HRTIM_CompareCfgTypeDef* pCompareCfg)
+{
+ uint32_t HRTIM_timcr;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
+
+ /* Configure the compare unit */
+ switch (CompareUnit)
+ {
+ case HRTIM_COMPAREUNIT_1:
+ {
+ /* Set the compare value */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_2:
+ {
+ /* Set the compare value */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
+
+ if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
+ {
+ /* Configure auto-delayed mode */
+ HRTIM_timcr = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR;
+ HRTIM_timcr &= ~HRTIM_TIMCR_DELCMP2;
+ HRTIM_timcr |= pCompareCfg->AutoDelayedMode;
+ HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR = HRTIM_timcr;
+
+ /* Set the compare value for timeout compare unit (if any) */
+ if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
+ }
+ else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
+ }
+ }
+ }
+ break;
+ case HRTIM_COMPAREUNIT_3:
+ {
+ /* Set the compare value */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_4:
+ {
+ /* Set the compare value */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
+
+ if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
+ {
+ /* Configure auto-delayed mode */
+ HRTIM_timcr = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR;
+ HRTIM_timcr &= ~HRTIM_TIMCR_DELCMP4;
+ HRTIM_timcr |= (pCompareCfg->AutoDelayedMode << 2);
+ HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR = HRTIM_timcr;
+
+ /* Set the compare value for timeout compare unit (if any) */
+ if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
+ }
+ else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
+ }
+ }
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Sets the HRTIMx Master Comparex Register value
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param CompareUnit: Compare unit to configure
+ * This parameter can be one of the following values:
+ * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
+ * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
+ * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
+ * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
+ * @param Compare: specifies the Comparex register new value
+ * @retval None
+ */
+void HRTIM_MasterSetCompare(HRTIM_TypeDef * HRTIMx,
+ uint32_t CompareUnit,
+ uint32_t Compare)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_COMPAREUNIT(CompareUnit));
+
+ /* Configure the compare unit */
+ switch (CompareUnit)
+ {
+ case HRTIM_COMPAREUNIT_1:
+ {
+ /* Set the compare value */
+ HRTIMx->HRTIM_MASTER.MCMP1R = Compare;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_2:
+ {
+ /* Set the compare value */
+ HRTIMx->HRTIM_MASTER.MCMP2R = Compare;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_3:
+ {
+ /* Set the compare value */
+ HRTIMx->HRTIM_MASTER.MCMP3R = Compare;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_4:
+ {
+ /* Set the compare value */
+ HRTIMx->HRTIM_MASTER.MCMP4R = Compare;
+ }
+ break;
+ default:
+ break;
+ }
+}
+/**
+ * @brief Configures the capture unit of a timer operating in waveform mode
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param CaptureChannel: Capture unit to configure
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+ * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+ * @param pCaptureCfg: pointer to the compare unit configuration structure
+ * @retval None
+ */
+void HRTIM_WaveformCaptureConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t CaptureUnit,
+ HRTIM_CaptureCfgTypeDef* pCaptureCfg)
+{
+ /* Configure the capture unit */
+ switch (CaptureUnit)
+ {
+ case HRTIM_CAPTUREUNIT_1:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR = pCaptureCfg->Trigger;
+ }
+ break;
+ case HRTIM_CAPTUREUNIT_2:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR = pCaptureCfg->Trigger;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Configures the output of a timer operating in waveform mode
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param Output: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @param pOutputCfg: pointer to the timer output configuration structure
+ * @retval None
+ */
+void HRTIM_WaveformOutputConfig(HRTIM_TypeDef * HRTIM_,
+ uint32_t TimerIdx,
+ uint32_t Output,
+ HRTIM_OutputCfgTypeDef * pOutputCfg)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
+ assert_param(IS_HRTIM_OUTPUTPOLARITY(pOutputCfg->Polarity));
+ assert_param(IS_HRTIM_OUTPUTIDLESTATE(pOutputCfg->IdleState));
+ assert_param(IS_HRTIM_OUTPUTIDLEMODE(pOutputCfg->IdleMode));
+ assert_param(IS_HRTIM_OUTPUTFAULTSTATE(pOutputCfg->FaultState));
+ assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable));
+ assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed));
+
+ /* Configure the timer output */
+ HRTIM_OutputConfig(HRTIM_, TimerIdx, Output, pOutputCfg);
+}
+
+/**
+ * @brief Configures the event filtering capabilities of a timer (blanking, windowing)
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param Event: external event for which timer event filtering must be configured
+ * This parameter can be one of the following values:
+ * @arg HRTIM_EVENT_1: External event 1
+ * @arg HRTIM_EVENT_2: External event 2
+ * @arg HRTIM_EVENT_3: External event 3
+ * @arg HRTIM_EVENT_4: External event 4
+ * @arg HRTIM_EVENT_5: External event 5
+ * @arg HRTIM_EVENT_6: External event 6
+ * @arg HRTIM_EVENT_7: External event 7
+ * @arg HRTIM_EVENT_8: External event 8
+ * @arg HRTIM_EVENT_9: External event 9
+ * @arg HRTIM_EVENT_10: External event 10
+ * @param pTimerEventFilteringCfg: pointer to the timer event filtering configuration structure
+ * @retval None
+ */
+void HRTIM_TimerEventFilteringConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t Event,
+ HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg)
+{
+ uint32_t HRTIM_eefr;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_EVENT(Event));
+ assert_param(IS_HRTIM_TIMEVENTFILTER(pTimerEventFilteringCfg->Filter));
+ assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch));
+
+ /* Configure timer event filtering capabilities */
+ switch (Event)
+ {
+ case HRTIM_TIMEVENTFILTER_NONE:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = 0;
+ HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = 0;
+ }
+ break;
+ case HRTIM_EVENT_1:
+ {
+ HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1;
+ HRTIM_eefr &= ~(HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH);
+ HRTIM_eefr |= (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch);
+ HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr;
+ }
+ break;
+ case HRTIM_EVENT_2:
+ {
+ HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1;
+ HRTIM_eefr &= ~(HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH);
+ HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6);
+ HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr;
+ }
+ break;
+ case HRTIM_EVENT_3:
+ {
+ HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1;
+ HRTIM_eefr &= ~(HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH);
+ HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12);
+ HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr;
+ }
+ break;
+ case HRTIM_EVENT_4:
+ {
+ HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1;
+ HRTIM_eefr &= ~(HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH);
+ HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18);
+ HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr;
+ }
+ break;
+ case HRTIM_EVENT_5:
+ {
+ HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1;
+ HRTIM_eefr &= ~(HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH);
+ HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24);
+ HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr;
+ }
+ break;
+ case HRTIM_EVENT_6:
+ {
+ HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2;
+ HRTIM_eefr &= ~(HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH);
+ HRTIM_eefr |= (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch);
+ HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr;
+ }
+ break;
+ case HRTIM_EVENT_7:
+ {
+ HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2;
+ HRTIM_eefr &= ~(HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH);
+ HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6);
+ HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr;
+ }
+ break;
+ case HRTIM_EVENT_8:
+ {
+ HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2;
+ HRTIM_eefr &= ~(HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH);
+ HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12);
+ HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr;
+ }
+ break;
+ case HRTIM_EVENT_9:
+ {
+ HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2;
+ HRTIM_eefr &= ~(HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH);
+ HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18);
+ HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr;
+ }
+ break;
+ case HRTIM_EVENT_10:
+ {
+ HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2;
+ HRTIM_eefr &= ~(HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH);
+ HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24);
+ HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Configures the dead time insertion feature for a timer
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param pDeadTimeCfg: pointer to the dead time insertion configuration structure
+ * @retval None
+ */
+void HRTIM_DeadTimeConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg)
+{
+ uint32_t HRTIM_dtr;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGN(pDeadTimeCfg->RisingSign));
+ assert_param(IS_HRTIM_TIMDEADTIME_RISINGLOCK(pDeadTimeCfg->RisingLock));
+ assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(pDeadTimeCfg->RisingSignLock));
+ assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGN(pDeadTimeCfg->FallingSign));
+ assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock));
+ assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock));
+
+ HRTIM_dtr = HRTIMx->HRTIM_TIMERx[TimerIdx].DTxR;
+
+ /* Clear timer dead times configuration */
+ HRTIM_dtr &= ~(HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC |
+ HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_SDTF |
+ HRTIM_DTR_SDTR | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK);
+
+ /* Set timer dead times configuration */
+ HRTIM_dtr |= (pDeadTimeCfg->Prescaler << 10);
+ HRTIM_dtr |= pDeadTimeCfg->RisingValue;
+ HRTIM_dtr |= pDeadTimeCfg->RisingSign;
+ HRTIM_dtr |= pDeadTimeCfg->RisingSignLock;
+ HRTIM_dtr |= pDeadTimeCfg->RisingLock;
+ HRTIM_dtr |= (pDeadTimeCfg->FallingValue << 16);
+ HRTIM_dtr |= pDeadTimeCfg->FallingSign;
+ HRTIM_dtr |= pDeadTimeCfg->FallingSignLock;
+ HRTIM_dtr |= pDeadTimeCfg->FallingLock;
+
+ /* Update the HRTIMx registers */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].DTxR = HRTIM_dtr;
+}
+
+/**
+ * @brief Configures the chopper mode feature for a timer
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param pChopperModeCfg: pointer to the chopper mode configuration structure
+ * @retval None
+ */
+void HRTIM_ChopperModeConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg)
+{
+ uint32_t HRTIM_chpr;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+
+ HRTIM_chpr = HRTIMx->HRTIM_TIMERx[TimerIdx].CHPxR;
+
+ /* Clear timer chopper mode configuration */
+ HRTIM_chpr &= ~(HRTIM_CHPR_CARFRQ | HRTIM_CHPR_CARDTY | HRTIM_CHPR_STRPW);
+
+ /* Set timer chopper mode configuration */
+ HRTIM_chpr |= pChopperModeCfg->CarrierFreq;
+ HRTIM_chpr |= (pChopperModeCfg->DutyCycle << 4);
+ HRTIM_chpr |= (pChopperModeCfg->StartPulse << 7);
+
+ /* Update the HRTIMx registers */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CHPxR = HRTIM_chpr;
+}
+
+/**
+ * @brief Configures the burst DMA controller for a timer
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x5 for master timer
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param RegistersToUpdate: registers to be written by DMA
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_BURSTDMA_CR: HRTIM_MCR or HRTIM_TIMxCR
+ * @arg HRTIM_BURSTDMA_ICR: HRTIM_MICR or HRTIM_TIMxICR
+ * @arg HRTIM_BURSTDMA_DIER: HRTIM_MDIER or HRTIM_TIMxDIER
+ * @arg HRTIM_BURSTDMA_CNT: HRTIM_MCNT or HRTIM_TIMxCNT
+ * @arg HRTIM_BURSTDMA_PER: HRTIM_MPER or HRTIM_TIMxPER
+ * @arg HRTIM_BURSTDMA_REP: HRTIM_MREP or HRTIM_TIMxREP
+ * @arg HRTIM_BURSTDMA_CMP1: HRTIM_MCMP1 or HRTIM_TIMxCMP1
+ * @arg HRTIM_BURSTDMA_CMP2: HRTIM_MCMP2 or HRTIM_TIMxCMP2
+ * @arg HRTIM_BURSTDMA_CMP3: HRTIM_MCMP3 or HRTIM_TIMxCMP3
+ * @arg HRTIM_BURSTDMA_CMP4: HRTIM_MCMP4 or HRTIM_TIMxCMP4
+ * @arg HRTIM_BURSTDMA_DTR: HRTIM_TIMxDTR
+ * @arg HRTIM_BURSTDMA_SET1R: HRTIM_TIMxSET1R
+ * @arg HRTIM_BURSTDMA_RST1R: HRTIM_TIMxRST1R
+ * @arg HRTIM_BURSTDMA_SET2R: HRTIM_TIMxSET2R
+ * @arg HRTIM_BURSTDMA_RST2R: HRTIM_TIMxRST2R
+ * @arg HRTIM_BURSTDMA_EEFR1: HRTIM_TIMxEEFR1
+ * @arg HRTIM_BURSTDMA_EEFR2: HRTIM_TIMxEEFR2
+ * @arg HRTIM_BURSTDMA_RSTR: HRTIM_TIMxRSTR
+ * @arg HRTIM_BURSTDMA_CHPR: HRTIM_TIMxCHPR
+ * @arg HRTIM_BURSTDMA_OUTR: HRTIM_TIMxOUTR
+ * @arg HRTIM_BURSTDMA_FLTR: HRTIM_TIMxFLTR
+ * @retval None
+ */
+void HRTIM_BurstDMAConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t RegistersToUpdate)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate));
+
+ /* Set the burst DMA timer update register */
+ switch (TimerIdx)
+ {
+ case HRTIM_TIMERINDEX_TIMER_A:
+ {
+ HRTIMx->HRTIM_COMMON.BDTAUPR = RegistersToUpdate;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_B:
+ {
+ HRTIMx->HRTIM_COMMON.BDTBUPR = RegistersToUpdate;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_C:
+ {
+ HRTIMx->HRTIM_COMMON.BDTCUPR = RegistersToUpdate;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_D:
+ {
+ HRTIMx->HRTIM_COMMON.BDTDUPR = RegistersToUpdate;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_E:
+ {
+ HRTIMx->HRTIM_COMMON.BDTEUPR = RegistersToUpdate;
+ }
+ break;
+ case HRTIM_TIMERINDEX_MASTER:
+ {
+ HRTIMx->HRTIM_COMMON.BDMUPDR = RegistersToUpdate;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Configures the external input/output synchronization of the HRTIMx
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param pSynchroCfg: pointer to the input/output synchronization configuration structure
+ * @retval None
+ */
+void HRTIM_SynchronizationConfig(HRTIM_TypeDef *HRTIMx, HRTIM_SynchroCfgTypeDef * pSynchroCfg)
+{
+ uint32_t HRTIM_mcr;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_SYNCINPUTSOURCE(pSynchroCfg->SyncInputSource));
+ assert_param(IS_HRTIM_SYNCOUTPUTSOURCE(pSynchroCfg->SyncOutputSource));
+ assert_param(IS_HRTIM_SYNCOUTPUTPOLARITY(pSynchroCfg->SyncOutputPolarity));
+
+ HRTIM_mcr = HRTIMx->HRTIM_MASTER.MCR;
+
+ /* Set the synchronization input source */
+ HRTIM_mcr &= ~(HRTIM_MCR_SYNC_IN);
+ HRTIM_mcr |= pSynchroCfg->SyncInputSource;
+
+ /* Set the event to be sent on the synchronization output */
+ HRTIM_mcr &= ~(HRTIM_MCR_SYNC_SRC);
+ HRTIM_mcr |= pSynchroCfg->SyncOutputSource;
+
+ /* Set the polarity of the synchronization output */
+ HRTIM_mcr &= ~(HRTIM_MCR_SYNC_OUT);
+ HRTIM_mcr |= pSynchroCfg->SyncOutputPolarity;
+
+ /* Update the HRTIMx registers */
+ HRTIMx->HRTIM_MASTER.MCR = HRTIM_mcr;
+}
+
+/**
+ * @brief Configures the burst mode feature of the HRTIMx
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param pBurstModeCfg: pointer to the burst mode configuration structure
+ * @retval None
+ */
+void HRTIM_BurstModeConfig(HRTIM_TypeDef * HRTIMx,
+ HRTIM_BurstModeCfgTypeDef* pBurstModeCfg)
+{
+ uint32_t HRTIM_bmcr;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_BURSTMODE(pBurstModeCfg->Mode));
+ assert_param(IS_HRTIM_BURSTMODECLOCKSOURCE(pBurstModeCfg->ClockSource));
+ assert_param(IS_HRTIM_HRTIM_BURSTMODEPRESCALER(pBurstModeCfg->Prescaler));
+ assert_param(IS_HRTIM_BURSTMODEPRELOAD(pBurstModeCfg->PreloadEnable));
+
+ HRTIM_bmcr = HRTIMx->HRTIM_COMMON.BMCR;
+
+ /* Set the burst mode operating mode */
+ HRTIM_bmcr &= ~(HRTIM_BMCR_BMOM);
+ HRTIM_bmcr |= pBurstModeCfg->Mode;
+
+ /* Set the burst mode clock source */
+ HRTIM_bmcr &= ~(HRTIM_BMCR_BMCLK);
+ HRTIM_bmcr |= pBurstModeCfg->ClockSource;
+
+ /* Set the burst mode prescaler */
+ HRTIM_bmcr &= ~(HRTIM_BMCR_BMPSC);
+ HRTIM_bmcr |= pBurstModeCfg->Prescaler;
+
+ /* Enable/disable burst mode registers preload */
+ HRTIM_bmcr &= ~(HRTIM_BMCR_BMPREN);
+ HRTIM_bmcr |= pBurstModeCfg->PreloadEnable;
+
+ /* Set the burst mode trigger */
+ HRTIMx->HRTIM_COMMON.BMTRGR = pBurstModeCfg->Trigger;
+
+ /* Set the burst mode compare value */
+ HRTIMx->HRTIM_COMMON.BMCMPR = pBurstModeCfg->IdleDuration;
+
+ /* Set the burst mode period */
+ HRTIMx->HRTIM_COMMON.BMPER = pBurstModeCfg->Period;
+
+ /* Update the HRTIMx registers */
+ HRTIMx->HRTIM_COMMON.BMCR = HRTIM_bmcr;
+}
+
+/**
+ * @brief Configures the conditioning of an external event
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param Event: external event to configure
+ * This parameter can be one of the following values:
+ * @arg HRTIM_EVENT_1: External event 1
+ * @arg HRTIM_EVENT_2: External event 2
+ * @arg HRTIM_EVENT_3: External event 3
+ * @arg HRTIM_EVENT_4: External event 4
+ * @arg HRTIM_EVENT_5: External event 5
+ * @arg HRTIM_EVENT_6: External event 6
+ * @arg HRTIM_EVENT_7: External event 7
+ * @arg HRTIM_EVENT_8: External event 8
+ * @arg HRTIM_EVENT_9: External event 9
+ * @arg HRTIM_EVENT_10: External event 10
+ * @param pEventCfg: pointer to the event conditioning configuration structure
+ * @retval None
+ */
+void HRTIM_EventConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t Event,
+ HRTIM_EventCfgTypeDef* pEventCfg)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_EVENTSRC(pEventCfg->Source));
+ assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Polarity));
+ assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity));
+ assert_param(IS_HRTIM_EVENTFASTMODE(pEventCfg->FastMode));
+ assert_param(IS_HRTIM_EVENTFILTER(pEventCfg->Filter));
+
+ /* Configure the event channel */
+ HRTIM_ExternalEventConfig(HRTIMx, Event, pEventCfg);
+
+}
+
+/**
+ * @brief Configures the external event conditioning block prescaler
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param Prescaler: Prescaler value
+ * This parameter can be one of the following values:
+ * @arg HRTIM_EVENTPRESCALER_DIV1: fEEVS=fHRTIMx
+ * @arg HRTIM_EVENTPRESCALER_DIV2: fEEVS=fHRTIMx / 2
+ * @arg HRTIM_EVENTPRESCALER_DIV4: fEEVS=fHRTIMx / 4
+ * @arg HRTIM_EVENTPRESCALER_DIV8: fEEVS=fHRTIMx / 8
+ * @retval None
+ */
+void HRTIM_EventPrescalerConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t Prescaler)
+{
+ uint32_t HRTIM_eecr3;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler));
+
+ /* Set the external event prescaler */
+ HRTIM_eecr3 = HRTIMx->HRTIM_COMMON.EECR3;
+ HRTIM_eecr3 &= ~(HRTIM_EECR3_EEVSD);
+ HRTIM_eecr3 |= Prescaler;
+
+ /* Update the HRTIMx registers */
+ HRTIMx->HRTIM_COMMON.EECR3 = HRTIM_eecr3;
+}
+
+/**
+ * @brief Configures the conditioning of fault input
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param Fault: fault input to configure
+ * This parameter can be one of the following values:
+ * @arg HRTIM_FAULT_1: Fault input 1
+ * @arg HRTIM_FAULT_2: Fault input 2
+ * @arg HRTIM_FAULT_3: Fault input 3
+ * @arg HRTIM_FAULT_4: Fault input 4
+ * @arg HRTIM_FAULT_5: Fault input 5
+ * @param pFaultCfg: pointer to the fault conditioning configuration structure
+ * @retval None
+ */
+void HRTIM_FaultConfig(HRTIM_TypeDef * HRTIMx,
+ HRTIM_FaultCfgTypeDef* pFaultCfg,
+ uint32_t Fault)
+{
+ uint32_t HRTIM_fltinr1;
+ uint32_t HRTIM_fltinr2;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_FAULT(Fault));
+ assert_param(IS_HRTIM_FAULTSOURCE(pFaultCfg->Source));
+ assert_param(IS_HRTIM_FAULTPOLARITY(pFaultCfg->Polarity));
+ assert_param(IS_HRTIM_FAULTFILTER(pFaultCfg->Filter));
+ assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock));
+
+ /* Configure fault channel */
+ HRTIM_fltinr1 = HRTIMx->HRTIM_COMMON.FLTINxR1;
+ HRTIM_fltinr2 = HRTIMx->HRTIM_COMMON.FLTINxR2;
+
+ switch (Fault)
+ {
+ case HRTIM_FAULT_1:
+ {
+ HRTIM_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK);
+ HRTIM_fltinr1 |= pFaultCfg->Polarity;
+ HRTIM_fltinr1 |= pFaultCfg->Source;
+ HRTIM_fltinr1 |= pFaultCfg->Filter;
+ HRTIM_fltinr1 |= pFaultCfg->Lock;
+ }
+ break;
+ case HRTIM_FAULT_2:
+ {
+ HRTIM_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK);
+ HRTIM_fltinr1 |= (pFaultCfg->Polarity << 8);
+ HRTIM_fltinr1 |= (pFaultCfg->Source << 8);
+ HRTIM_fltinr1 |= (pFaultCfg->Filter << 8);
+ HRTIM_fltinr1 |= (pFaultCfg->Lock << 8);
+ }
+ break;
+ case HRTIM_FAULT_3:
+ {
+ HRTIM_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK);
+ HRTIM_fltinr1 |= (pFaultCfg->Polarity << 16);
+ HRTIM_fltinr1 |= (pFaultCfg->Source << 16);
+ HRTIM_fltinr1 |= (pFaultCfg->Filter << 16);
+ HRTIM_fltinr1 |= (pFaultCfg->Lock << 16);
+ }
+ break;
+ case HRTIM_FAULT_4:
+ {
+ HRTIM_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK);
+ HRTIM_fltinr1 |= (pFaultCfg->Polarity << 24);
+ HRTIM_fltinr1 |= (pFaultCfg->Source << 24);
+ HRTIM_fltinr1 |= (pFaultCfg->Filter << 24);
+ HRTIM_fltinr1 |= (pFaultCfg->Lock << 24);
+ }
+ break;
+ case HRTIM_FAULT_5:
+ {
+ HRTIM_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK);
+ HRTIM_fltinr2 |= pFaultCfg->Polarity;
+ HRTIM_fltinr2 |= pFaultCfg->Source;
+ HRTIM_fltinr2 |= pFaultCfg->Filter;
+ HRTIM_fltinr2 |= pFaultCfg->Lock;
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Update the HRTIMx registers */
+ HRTIMx->HRTIM_COMMON.FLTINxR1 = HRTIM_fltinr1;
+ HRTIMx->HRTIM_COMMON.FLTINxR2 = HRTIM_fltinr2;
+}
+
+/**
+ * @brief Configures the fault conditioning block prescaler
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param Prescaler: Prescaler value
+ * This parameter can be one of the following values:
+ * @arg HRTIM_FAULTPRESCALER_DIV1: fFLTS=fHRTIMx
+ * @arg HRTIM_FAULTPRESCALER_DIV2: fFLTS=fHRTIMx / 2
+ * @arg HRTIM_FAULTPRESCALER_DIV4: fFLTS=fHRTIMx / 4
+ * @arg HRTIM_FAULTPRESCALER_DIV8: fFLTS=fHRTIMx / 8
+ * @retval None
+ */
+void HRTIM_FaultPrescalerConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t Prescaler)
+{
+ uint32_t HRTIM_fltinr2;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_FAULTPRESCALER(Prescaler));
+
+ /* Set the external event prescaler */
+ HRTIM_fltinr2 = HRTIMx->HRTIM_COMMON.FLTINxR2;
+ HRTIM_fltinr2 &= ~(HRTIM_FLTINR2_FLTSD);
+ HRTIM_fltinr2 |= Prescaler;
+
+ /* Update the HRTIMx registers */
+ HRTIMx->HRTIM_COMMON.FLTINxR2 = HRTIM_fltinr2;
+}
+
+/**
+ * @brief Enables or disables the HRTIMx Fault mode.
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param Fault: fault input to configure
+ * This parameter can be one of the following values:
+ * @arg HRTIM_FAULT_1: Fault input 1
+ * @arg HRTIM_FAULT_2: Fault input 2
+ * @arg HRTIM_FAULT_3: Fault input 3
+ * @arg HRTIM_FAULT_4: Fault input 4
+ * @arg HRTIM_FAULT_5: Fault input 5
+ * @param Enable: Fault mode controller enabling
+ * This parameter can be one of the following values:
+ * @arg HRTIM_FAULT_ENABLED: Fault mode enabled
+ * @arg HRTIM_FAULT_DISABLED: Fault mode disabled
+ * @retval None
+ */
+void HRTIM_FaultModeCtl(HRTIM_TypeDef * HRTIMx, uint32_t Fault, uint32_t Enable)
+{
+ uint32_t HRTIM_fltinr1;
+ uint32_t HRTIM_fltinr2;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_FAULT(Fault));
+ assert_param(IS_HRTIM_FAULTCTL(Enable));
+
+ /* Configure fault channel */
+ HRTIM_fltinr1 = HRTIMx->HRTIM_COMMON.FLTINxR1;
+ HRTIM_fltinr2 = HRTIMx->HRTIM_COMMON.FLTINxR2;
+
+ switch (Fault)
+ {
+ case HRTIM_FAULT_1:
+ {
+ HRTIM_fltinr1 &= ~HRTIM_FLTINR1_FLT1E;
+ HRTIM_fltinr1 |= Enable;
+ }
+ break;
+ case HRTIM_FAULT_2:
+ {
+ HRTIM_fltinr1 &= ~HRTIM_FLTINR1_FLT2E;
+ HRTIM_fltinr1 |= (Enable<< 8);
+ }
+ break;
+ case HRTIM_FAULT_3:
+ {
+ HRTIM_fltinr1 &= ~HRTIM_FLTINR1_FLT3E;
+ HRTIM_fltinr1 |= (Enable << 16);
+ }
+ break;
+ case HRTIM_FAULT_4:
+ {
+ HRTIM_fltinr1 &= ~HRTIM_FLTINR1_FLT4E;
+ HRTIM_fltinr1 |= (Enable << 24);
+ }
+ break;
+ case HRTIM_FAULT_5:
+ {
+ HRTIM_fltinr2 &= ~HRTIM_FLTINR2_FLT5E;
+ HRTIM_fltinr2 |= Enable;
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Update the HRTIMx registers */
+ HRTIMx->HRTIM_COMMON.FLTINxR1 = HRTIM_fltinr1;
+ HRTIMx->HRTIM_COMMON.FLTINxR2 = HRTIM_fltinr2;
+}
+
+/**
+ * @brief Configures both the ADC trigger register update source and the ADC
+ * trigger source.
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param ADC trigger: ADC trigger to configure
+ * This parameter can be one of the following values:
+ * @arg HRTIM_ADCTRIGGER_1: ADC trigger 1
+ * @arg HRTIM_ADCTRIGGER_2: ADC trigger 2
+ * @arg HRTIM_ADCTRIGGER_3: ADC trigger 3
+ * @arg HRTIM_ADCTRIGGER_4: ADC trigger 4
+ * @param pADCTriggerCfg: pointer to the ADC trigger configuration structure
+ * @retval None
+ */
+void HRTIM_ADCTriggerConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t ADCTrigger,
+ HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg)
+{
+ uint32_t HRTIM_cr1;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger));
+ assert_param(IS_HRTIM_ADCTRIGGERUPDATE(pADCTriggerCfg->UpdateSource));
+
+ /* Set the ADC trigger update source */
+ HRTIM_cr1 = HRTIMx->HRTIM_COMMON.CR1;
+
+ switch (ADCTrigger)
+ {
+ case HRTIM_ADCTRIGGER_1:
+ {
+ HRTIM_cr1 &= ~(HRTIM_CR1_ADC1USRC);
+ HRTIM_cr1 |= pADCTriggerCfg->UpdateSource;
+
+ /* Set the ADC trigger 1 source */
+ HRTIMx->HRTIM_COMMON.ADC1R = pADCTriggerCfg->Trigger;
+ }
+ break;
+ case HRTIM_ADCTRIGGER_2:
+ {
+ HRTIM_cr1 &= ~(HRTIM_CR1_ADC2USRC);
+ HRTIM_cr1 |= (pADCTriggerCfg->UpdateSource << 3);
+
+ /* Set the ADC trigger 2 source */
+ HRTIMx->HRTIM_COMMON.ADC2R = pADCTriggerCfg->Trigger;
+ }
+ break;
+ case HRTIM_ADCTRIGGER_3:
+ {
+ HRTIM_cr1 &= ~(HRTIM_CR1_ADC3USRC);
+ HRTIM_cr1 |= (pADCTriggerCfg->UpdateSource << 6);
+
+ /* Set the ADC trigger 3 source */
+ HRTIMx->HRTIM_COMMON.ADC3R = pADCTriggerCfg->Trigger;
+ }
+ case HRTIM_ADCTRIGGER_4:
+ {
+ HRTIM_cr1 &= ~(HRTIM_CR1_ADC4USRC);
+ HRTIM_cr1 |= (pADCTriggerCfg->UpdateSource << 9);
+
+ /* Set the ADC trigger 4 source */
+ HRTIMx->HRTIM_COMMON.ADC4R = pADCTriggerCfg->Trigger;
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Update the HRTIMx registers */
+ HRTIMx->HRTIM_COMMON.CR1 = HRTIM_cr1;
+}
+
+
+/**
+ * @brief Enables or disables the HRTIMx burst mode controller.
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param Enable: Burst mode controller enabling
+ * This parameter can be one of the following values:
+ * @arg HRTIM_BURSTMODECTL_ENABLED: Burst mode enabled
+ * @arg HRTIM_BURSTMODECTL_DISABLED: Burst mode disabled
+ * @retval None
+ */
+void HRTIM_BurstModeCtl(HRTIM_TypeDef * HRTIMx, uint32_t Enable)
+{
+ uint32_t HRTIM_bmcr;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_BURSTMODECTL(Enable));
+
+ /* Enable/Disable the burst mode controller */
+ HRTIM_bmcr = HRTIMx->HRTIM_COMMON.BMCR;
+ HRTIM_bmcr &= ~(HRTIM_BMCR_BME);
+ HRTIM_bmcr |= Enable;
+
+ /* Update the HRTIMx registers */
+ HRTIMx->HRTIM_COMMON.BMCR = HRTIM_bmcr;
+}
+
+/**
+ * @brief Triggers a software capture on the designed capture unit
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param CaptureUnit: Capture unit to trig
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+ * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+ * @retval None
+ * @note The 'software capture' bit in the capure configuration register is
+ * automatically reset by hardware
+ */
+void HRTIM_SoftwareCapture(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t CaptureUnit)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
+
+ /* Force a software capture on concerned capture unit */
+ switch (CaptureUnit)
+ {
+ case HRTIM_CAPTUREUNIT_1:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR |= HRTIM_CPT1CR_SWCPT;
+ }
+ break;
+ case HRTIM_CAPTUREUNIT_2:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR |= HRTIM_CPT2CR_SWCPT;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Triggers the update of the registers of one or several timers
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimersToUpdate: timers concerned with the software register update
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_TIMERUPDATE_MASTER
+ * @arg HRTIM_TIMERUPDATE_A
+ * @arg HRTIM_TIMERUPDATE_B
+ * @arg HRTIM_TIMERUPDATE_C
+ * @arg HRTIM_TIMERUPDATE_D
+ * @arg HRTIM_TIMERUPDATE_E
+ * @retval None
+ * @note The 'software update' bits in the HRTIMx control register 2 register are
+ * automatically reset by hardware
+ */
+void HRTIM_SoftwareUpdate(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimersToUpdate)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMERUPDATE(TimersToUpdate));
+
+ /* Force timer(s) registers update */
+ HRTIMx->HRTIM_COMMON.CR2 |= TimersToUpdate;
+
+}
+
+/**
+ * @brief Triggers the reset of one or several timers
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimersToUpdate: timers concerned with the software counter reset
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_TIMER_MASTER
+ * @arg HRTIM_TIMER_A
+ * @arg HRTIM_TIMER_B
+ * @arg HRTIM_TIMER_C
+ * @arg HRTIM_TIMER_D
+ * @arg HRTIM_TIMER_E
+ * @retval None
+ * @note The 'software reset' bits in the HRTIMx control register 2 are
+ * automatically reset by hardware
+ */
+void HRTIM_SoftwareReset(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimersToReset)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMERRESET(TimersToReset));
+
+ /* Force timer(s) registers update */
+ HRTIMx->HRTIM_COMMON.CR2 |= TimersToReset;
+
+}
+
+/**
+ * @brief Forces the timer output to its active or inactive state
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param Output: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @param OutputLevel: indicates whether the output is forced to its active or inactive state
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUTLEVEL_ACTIVE: output is forced to its active state
+ * @arg HRTIM_OUTPUTLEVEL_INACTIVE: output is forced to its inactive state
+ * @retval None
+ * @note The 'software set/reset trigger' bit in the output set/reset registers
+ * is automatically reset by hardware
+ */
+void HRTIM_WaveformSetOutputLevel(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t Output,
+ uint32_t OutputLevel)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
+ assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel));
+
+ /* Force timer output level */
+ switch (Output)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
+ {
+ /* Force output to its active state */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].SETx1R |= HRTIM_SET1R_SST;
+ }
+ else
+ {
+ /* Force output to its inactive state */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].RSTx1R |= HRTIM_RST1R_SRT;
+ }
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
+ {
+ /* Force output to its active state */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].SETx2R |= HRTIM_SET2R_SST;
+ }
+ else
+ {
+ /* Force output to its inactive state */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].RSTx2R |= HRTIM_RST2R_SRT;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Group4 Peripheral State methods
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State methods #####
+ ===============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns actual value of the capture register of the designated capture unit
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param CaptureUnit: Capture unit to trig
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+ * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+ * @retval Captured value
+ */
+uint32_t HRTIM_GetCapturedValue(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t CaptureUnit)
+{
+ uint32_t captured_value = 0;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
+
+ /* Read captured value */
+ switch (CaptureUnit)
+ {
+ case HRTIM_CAPTUREUNIT_1:
+ {
+ captured_value = HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xR;
+ }
+ break;
+ case HRTIM_CAPTUREUNIT_2:
+ {
+ captured_value = HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xR;
+ }
+ break;
+ default:
+ break;
+ }
+
+ return captured_value;
+}
+
+/**
+ * @brief Returns actual level (active or inactive) of the designated output
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param Output: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval Output level
+ * @note Returned output level is taken before the output stage (chopper,
+ * polarity).
+ */
+uint32_t HRTIM_WaveformGetOutputLevel(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t Output)
+{
+ uint32_t output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
+
+ /* Read the output level */
+ switch (Output)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != RESET)
+ {
+ output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
+ }
+ else
+ {
+ output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
+ }
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != RESET)
+ {
+ output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
+ }
+ else
+ {
+ output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+
+ return output_level;
+}
+
+/**
+ * @brief Returns actual state (RUN, IDLE, FAULT) of the designated output
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param Output: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval Output state
+ */
+uint32_t HRTIM_WaveformGetOutputState(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t Output)
+{
+ uint32_t output_bit = 0;
+ uint32_t output_state = HRTIM_OUTPUTSTATE_IDLE;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
+
+ /* Set output state according to output control status and output disable status */
+ switch (Output)
+ {
+ case HRTIM_OUTPUT_TA1:
+ {
+ output_bit = HRTIM_OENR_TA1OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ {
+ output_bit = HRTIM_OENR_TA2OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TB1:
+ {
+ output_bit = HRTIM_OENR_TB1OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TB2:
+ {
+ output_bit = HRTIM_OENR_TB2OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TC1:
+ {
+ output_bit = HRTIM_OENR_TC1OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TC2:
+ {
+ output_bit = HRTIM_OENR_TC2OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TD1:
+ {
+ output_bit = HRTIM_OENR_TD1OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TD2:
+ {
+ output_bit = HRTIM_OENR_TD2OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TE1:
+ {
+ output_bit = HRTIM_OENR_TE1OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TE2:
+ {
+ output_bit = HRTIM_OENR_TE2OEN;
+ }
+ break;
+ default:
+ break;
+ }
+
+ if ((HRTIMx->HRTIM_COMMON.OENR & output_bit) != RESET)
+ {
+ /* Output is enabled: output in RUN state (whatever ouput disable status is)*/
+ output_state = HRTIM_OUTPUTSTATE_RUN;
+ }
+ else
+ {
+ if ((HRTIMx->HRTIM_COMMON.ODSR & output_bit) != RESET)
+ {
+ /* Output is disabled: output in FAULT state */
+ output_state = HRTIM_OUTPUTSTATE_FAULT;
+ }
+ else
+ {
+ /* Output is disabled: output in IDLE state */
+ output_state = HRTIM_OUTPUTSTATE_IDLE;
+ }
+ }
+
+ return(output_state);
+}
+
+/**
+ * @brief Returns the level (active or inactive) of the designated output
+ * when the delayed protection was triggered
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param Output: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer E - Output 2
+ * @retval Delayed protection status
+ */
+uint32_t HRTIM_GetDelayedProtectionStatus(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t Output)
+{
+ uint32_t delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
+
+ /* Read the delayed protection status */
+ switch (Output)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != RESET)
+ {
+ /* Output 1 was active when the delayed idle protection was triggered */
+ delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
+ }
+ else
+ {
+ /* Output 1 was inactive when the delayed idle protection was triggered */
+ delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
+ }
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != RESET)
+ {
+ /* Output 2 was active when the delayed idle protection was triggered */
+ delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
+ }
+ else
+ {
+ /* Output 2 was inactive when the delayed idle protection was triggered */
+ delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+
+ return delayed_protection_status;
+}
+
+/**
+ * @brief Returns the actual status (active or inactive) of the burst mode controller
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @retval Burst mode controller status
+ */
+uint32_t HRTIM_GetBurstStatus(HRTIM_TypeDef * HRTIMx)
+{
+ uint32_t burst_mode_status;
+
+ /* Read burst mode status */
+ burst_mode_status = (HRTIMx->HRTIM_COMMON.BMCR & HRTIM_BMCR_BMSTAT);
+
+ return burst_mode_status;
+}
+
+/**
+ * @brief Indicates on which output the signal is currently active (when the
+ * push pull mode is enabled)
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @retval Burst mode controller status
+ */
+uint32_t HRTIM_GetCurrentPushPullStatus(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx)
+{
+ uint32_t current_pushpull_status;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+
+ /* Read current push pull status */
+ current_pushpull_status = (HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_CPPSTAT);
+
+ return current_pushpull_status;
+}
+
+
+/**
+ * @brief Indicates on which output the signal was applied, in push-pull mode
+ balanced fault mode or delayed idle mode, when the protection was triggered
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @retval Idle Push Pull Status
+ */
+uint32_t HRTIM_GetIdlePushPullStatus(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx)
+{
+ uint32_t idle_pushpull_status;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+
+ /* Read current push pull status */
+ idle_pushpull_status = (HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_IPPSTAT);
+
+ return idle_pushpull_status;
+}
+
+/**
+ * @brief Configures the master timer time base
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @retval None
+ */
+void HRTIM_MasterBase_Config(HRTIM_TypeDef * HRTIMx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
+{
+ /* Set the prescaler ratio */
+ HRTIMx->HRTIM_MASTER.MCR &= (uint32_t) ~(HRTIM_MCR_CK_PSC);
+ HRTIMx->HRTIM_MASTER.MCR |= (uint32_t)HRTIM_BaseInitStruct->PrescalerRatio;
+
+ /* Set the operating mode */
+ HRTIMx->HRTIM_MASTER.MCR &= (uint32_t) ~(HRTIM_MCR_CONT | HRTIM_MCR_RETRIG);
+ HRTIMx->HRTIM_MASTER.MCR |= (uint32_t)HRTIM_BaseInitStruct->Mode;
+
+ /* Update the HRTIMx registers */
+ HRTIMx->HRTIM_MASTER.MPER = HRTIM_BaseInitStruct->Period;
+ HRTIMx->HRTIM_MASTER.MREP = HRTIM_BaseInitStruct->RepetitionCounter;
+}
+
+/**
+ * @brief Configures timing unit (timer A to timer E) time base
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * @retval None
+ */
+void HRTIM_TimingUnitBase_Config(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
+{
+ /* Set the prescaler ratio */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR &= (uint32_t) ~(HRTIM_TIMCR_CK_PSC);
+ HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR |= (uint32_t)HRTIM_BaseInitStruct->PrescalerRatio;
+
+ /* Set the operating mode */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR &= (uint32_t) ~(HRTIM_TIMCR_CONT | HRTIM_TIMCR_RETRIG);
+ HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR |= (uint32_t)HRTIM_BaseInitStruct->Mode;
+
+ /* Update the HRTIMx registers */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].PERxR = HRTIM_BaseInitStruct->Period;
+ HRTIMx->HRTIM_TIMERx[TimerIdx].REPxR = HRTIM_BaseInitStruct->RepetitionCounter;
+}
+
+/**
+ * @brief Configures the master timer in waveform mode
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * @param pTimerInit: pointer to the timer initialization data structure
+ * @retval None
+ */
+void HRTIM_MasterWaveform_Config(HRTIM_TypeDef * HRTIMx,
+ HRTIM_TimerInitTypeDef * pTimerInit)
+{
+ uint32_t HRTIM_mcr;
+ uint32_t HRTIM_bmcr;
+
+ /* Configure master timer */
+ HRTIM_mcr = HRTIMx->HRTIM_MASTER.MCR;
+ HRTIM_bmcr = HRTIMx->HRTIM_COMMON.BMCR;
+
+ /* Enable/Disable the half mode */
+ HRTIM_mcr &= ~(HRTIM_MCR_HALF);
+ HRTIM_mcr |= pTimerInit->HalfModeEnable;
+
+ /* Enable/Disable the timer start upon synchronization event reception */
+ HRTIM_mcr &= ~(HRTIM_MCR_SYNCSTRTM);
+ HRTIM_mcr |= pTimerInit->StartOnSync;
+
+ /* Enable/Disable the timer reset upon synchronization event reception */
+ HRTIM_mcr &= ~(HRTIM_MCR_SYNCRSTM);
+ HRTIM_mcr |= pTimerInit->ResetOnSync;
+
+ /* Enable/Disable the DAC synchronization event generation */
+ HRTIM_mcr &= ~(HRTIM_MCR_DACSYNC);
+ HRTIM_mcr |= pTimerInit->DACSynchro;
+
+ /* Enable/Disable preload mechanism for timer registers */
+ HRTIM_mcr &= ~(HRTIM_MCR_PREEN);
+ HRTIM_mcr |= pTimerInit->PreloadEnable;
+
+ /* Master timer registers update handling */
+ HRTIM_mcr &= ~(HRTIM_MCR_BRSTDMA);
+ HRTIM_mcr |= (pTimerInit->UpdateGating << 2);
+
+ /* Enable/Disable registers update on repetition */
+ HRTIM_mcr &= ~(HRTIM_MCR_MREPU);
+ HRTIM_mcr |= pTimerInit->RepetitionUpdate;
+
+ /* Set the timer burst mode */
+ HRTIM_bmcr &= ~(HRTIM_BMCR_MTBM);
+ HRTIM_bmcr |= pTimerInit->BurstMode;
+
+ /* Update the HRTIMx registers */
+ HRTIMx->HRTIM_MASTER.MCR = HRTIM_mcr;
+ HRTIMx->HRTIM_COMMON.BMCR = HRTIM_bmcr;
+
+}
+
+/**
+ * @brief Configures timing unit (timer A to timer E) in waveform mode
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * @param pTimerInit: pointer to the timer initialization data structure
+ * @retval None
+ */
+void HRTIM_TimingUnitWaveform_Config(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ HRTIM_TimerInitTypeDef * pTimerInit)
+{
+ uint32_t HRTIM_timcr;
+ uint32_t HRTIM_bmcr;
+
+ /* Configure timing unit */
+ HRTIM_timcr = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR;
+ HRTIM_bmcr = HRTIMx->HRTIM_COMMON.BMCR;
+
+ /* Enable/Disable the half mode */
+ HRTIM_timcr &= ~(HRTIM_TIMCR_HALF);
+ HRTIM_timcr |= pTimerInit->HalfModeEnable;
+
+ /* Enable/Disable the timer start upon synchronization event reception */
+ HRTIM_timcr &= ~(HRTIM_TIMCR_SYNCSTRT);
+ HRTIM_timcr |= pTimerInit->StartOnSync;
+
+ /* Enable/Disable the timer reset upon synchronization event reception */
+ HRTIM_timcr &= ~(HRTIM_TIMCR_SYNCRST);
+ HRTIM_timcr |= pTimerInit->ResetOnSync;
+
+ /* Enable/Disable the DAC synchronization event generation */
+ HRTIM_timcr &= ~(HRTIM_TIMCR_DACSYNC);
+ HRTIM_timcr |= pTimerInit->DACSynchro;
+
+ /* Enable/Disable preload mechanism for timer registers */
+ HRTIM_timcr &= ~(HRTIM_TIMCR_PREEN);
+ HRTIM_timcr |= pTimerInit->PreloadEnable;
+
+ /* Timing unit registers update handling */
+ HRTIM_timcr &= ~(HRTIM_TIMCR_UPDGAT);
+ HRTIM_timcr |= pTimerInit->UpdateGating;
+
+ /* Enable/Disable registers update on repetition */
+ HRTIM_timcr &= ~(HRTIM_TIMCR_TREPU);
+ if (pTimerInit->RepetitionUpdate == HRTIM_UPDATEONREPETITION_ENABLED)
+ {
+ HRTIM_timcr |= HRTIM_TIMCR_TREPU;
+ }
+
+ /* Set the timer burst mode */
+ switch (TimerIdx)
+ {
+ case HRTIM_TIMERINDEX_TIMER_A:
+ {
+ HRTIM_bmcr &= ~(HRTIM_BMCR_TABM);
+ HRTIM_bmcr |= ( pTimerInit->BurstMode << 1);
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_B:
+ {
+ HRTIM_bmcr &= ~(HRTIM_BMCR_TBBM);
+ HRTIM_bmcr |= ( pTimerInit->BurstMode << 2);
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_C:
+ {
+ HRTIM_bmcr &= ~(HRTIM_BMCR_TCBM);
+ HRTIM_bmcr |= ( pTimerInit->BurstMode << 3);
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_D:
+ {
+ HRTIM_bmcr &= ~(HRTIM_BMCR_TDBM);
+ HRTIM_bmcr |= ( pTimerInit->BurstMode << 4);
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_E:
+ {
+ HRTIM_bmcr &= ~(HRTIM_BMCR_TEBM);
+ HRTIM_bmcr |= ( pTimerInit->BurstMode << 5);
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Update the HRTIMx registers */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR = HRTIM_timcr;
+ HRTIMx->HRTIM_COMMON.BMCR = HRTIM_bmcr;
+}
+
+/**
+ * @brief Configures a compare unit
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * @param CompareUnit: Compare unit identifier
+ * @param pCompareCfg: pointer to the compare unit configuration data structure
+ * @retval None
+ */
+void HRTIM_CompareUnitConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t CompareUnit,
+ HRTIM_CompareCfgTypeDef * pCompareCfg)
+{
+ if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+ {
+ /* Configure the compare unit of the master timer */
+ switch (CompareUnit)
+ {
+ case HRTIM_COMPAREUNIT_1:
+ {
+ HRTIMx->HRTIM_MASTER.MCMP1R = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_2:
+ {
+ HRTIMx->HRTIM_MASTER.MCMP2R = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_3:
+ {
+ HRTIMx->HRTIM_MASTER.MCMP3R = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_4:
+ {
+ HRTIMx->HRTIM_MASTER.MCMP4R = pCompareCfg->CompareValue;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+ else
+ {
+ /* Configure the compare unit of the timing unit */
+ switch (CompareUnit)
+ {
+ case HRTIM_COMPAREUNIT_1:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_2:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_3:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_4:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+/**
+ * @brief Configures a capture unit
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * @param CaptureUnit: Capture unit identifier
+ * @param pCaptureCfg: pointer to the compare unit configuration data structure
+ * @retval None
+ */
+void HRTIM_CaptureUnitConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t CaptureUnit,
+ uint32_t Event)
+{
+ uint32_t CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1;
+
+ switch (Event)
+ {
+ case HRTIM_EVENT_1:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1;
+ }
+ break;
+ case HRTIM_EVENT_2:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2;
+ }
+ break;
+ case HRTIM_EVENT_3:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3;
+ }
+ break;
+ case HRTIM_EVENT_4:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4;
+ }
+ break;
+ case HRTIM_EVENT_5:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5;
+ }
+ break;
+ case HRTIM_EVENT_6:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6;
+ }
+ break;
+ case HRTIM_EVENT_7:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7;
+ }
+ break;
+ case HRTIM_EVENT_8:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8;
+ }
+ break;
+ case HRTIM_EVENT_9:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9;
+ }
+ break;
+ case HRTIM_EVENT_10:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10;
+ }
+ break;
+ default:
+ break;
+
+ }
+ switch (CaptureUnit)
+ {
+ case HRTIM_CAPTUREUNIT_1:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR = CaptureTrigger;
+ }
+ break;
+ case HRTIM_CAPTUREUNIT_2:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR = CaptureTrigger;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Configures the output of a timing unit
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * @param Output: timing unit output identifier
+ * @param pOutputCfg: pointer to the output configuration data structure
+ * @retval None
+ */
+void HRTIM_OutputConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t Output,
+ HRTIM_OutputCfgTypeDef * pOutputCfg)
+{
+ uint32_t HRTIM_outr;
+ uint32_t shift = 0;
+
+ HRTIM_outr = HRTIMx->HRTIM_TIMERx[TimerIdx].OUTxR;
+
+ switch (Output)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ /* Set the output set/reset crossbar */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].SETx1R = pOutputCfg->SetSource;
+ HRTIMx->HRTIM_TIMERx[TimerIdx].RSTx1R = pOutputCfg->ResetSource;
+
+ shift = 0;
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ /* Set the output set/reset crossbar */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].SETx2R = pOutputCfg->SetSource;
+ HRTIMx->HRTIM_TIMERx[TimerIdx].RSTx2R = pOutputCfg->ResetSource;
+
+ shift = 16;
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Clear output config */
+ HRTIM_outr &= ~((HRTIM_OUTR_POL1 |
+ HRTIM_OUTR_IDLM1 |
+ HRTIM_OUTR_IDLES1|
+ HRTIM_OUTR_FAULT1|
+ HRTIM_OUTR_CHP1 |
+ HRTIM_OUTR_DIDL1) << shift);
+
+ /* Set the polarity */
+ HRTIM_outr |= (pOutputCfg->Polarity << shift);
+
+ /* Set the IDLE mode */
+ HRTIM_outr |= (pOutputCfg->IdleMode << shift);
+
+ /* Set the IDLE state */
+ HRTIM_outr |= (pOutputCfg->IdleState << shift);
+
+ /* Set the FAULT state */
+ HRTIM_outr |= (pOutputCfg->FaultState << shift);
+
+ /* Set the chopper mode */
+ HRTIM_outr |= (pOutputCfg->ChopperModeEnable << shift);
+
+ /* Set the burst mode entry mode */
+ HRTIM_outr |= (pOutputCfg->BurstModeEntryDelayed << shift);
+
+ /* Update HRTIMx register */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].OUTxR = HRTIM_outr;
+}
+
+/**
+ * @brief Configures an external event channel
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param Event: Event channel identifier
+ * @param pEventCfg: pointer to the event channel configuration data structure
+ * @retval None
+ */
+static void HRTIM_ExternalEventConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t Event,
+ HRTIM_EventCfgTypeDef *pEventCfg)
+{
+ uint32_t hrtim_eecr1;
+ uint32_t hrtim_eecr2;
+ uint32_t hrtim_eecr3;
+
+ /* Configure external event channel */
+ hrtim_eecr1 = HRTIMx->HRTIM_COMMON.EECR1;
+ hrtim_eecr2 = HRTIMx->HRTIM_COMMON.EECR2;
+ hrtim_eecr3 = HRTIMx->HRTIM_COMMON.EECR3;
+
+ switch (Event)
+ {
+ case HRTIM_EVENT_1:
+ {
+ hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST);
+ hrtim_eecr1 |= pEventCfg->Source;
+ hrtim_eecr1 |= pEventCfg->Polarity;
+ hrtim_eecr1 |= pEventCfg->Sensitivity;
+ /* Update the HRTIM registers (all bit fields but EE1FAST bit) */
+ HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
+ /* Update the HRTIM registers (EE1FAST bit) */
+ hrtim_eecr1 |= pEventCfg->FastMode;
+ HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
+ }
+ break;
+ case HRTIM_EVENT_2:
+ {
+ hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST);
+ hrtim_eecr1 |= (pEventCfg->Source << 6);
+ hrtim_eecr1 |= (pEventCfg->Polarity << 6);
+ hrtim_eecr1 |= (pEventCfg->Sensitivity << 6);
+ /* Update the HRTIM registers (all bit fields but EE2FAST bit) */
+ HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
+ /* Update the HRTIM registers (EE2FAST bit) */
+ hrtim_eecr1 |= (pEventCfg->FastMode << 6);
+ HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
+ }
+ break;
+ case HRTIM_EVENT_3:
+ {
+ hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST);
+ hrtim_eecr1 |= (pEventCfg->Source << 12);
+ hrtim_eecr1 |= (pEventCfg->Polarity << 12);
+ hrtim_eecr1 |= (pEventCfg->Sensitivity << 12);
+ /* Update the HRTIM registers (all bit fields but EE3FAST bit) */
+ HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
+ /* Update the HRTIM registers (EE3FAST bit) */
+ hrtim_eecr1 |= (pEventCfg->FastMode << 12);
+ HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
+ }
+ break;
+ case HRTIM_EVENT_4:
+ {
+ hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST);
+ hrtim_eecr1 |= (pEventCfg->Source << 18);
+ hrtim_eecr1 |= (pEventCfg->Polarity << 18);
+ hrtim_eecr1 |= (pEventCfg->Sensitivity << 18);
+ /* Update the HRTIM registers (all bit fields but EE4FAST bit) */
+ HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
+ /* Update the HRTIM registers (EE4FAST bit) */
+ hrtim_eecr1 |= (pEventCfg->FastMode << 18);
+ HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
+ }
+ break;
+ case HRTIM_EVENT_5:
+ {
+ hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST);
+ hrtim_eecr1 |= (pEventCfg->Source << 24);
+ hrtim_eecr1 |= (pEventCfg->Polarity << 24);
+ hrtim_eecr1 |= (pEventCfg->Sensitivity << 24);
+ /* Update the HRTIM registers (all bit fields but EE5FAST bit) */
+ HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
+ /* Update the HRTIM registers (EE5FAST bit) */
+ hrtim_eecr1 |= (pEventCfg->FastMode << 24);
+ HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
+ }
+ break;
+ case HRTIM_EVENT_6:
+ {
+ hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS);
+ hrtim_eecr2 |= pEventCfg->Source;
+ hrtim_eecr2 |= pEventCfg->Polarity;
+ hrtim_eecr2 |= pEventCfg->Sensitivity;
+ hrtim_eecr3 &= ~(HRTIM_EECR3_EE6F);
+ hrtim_eecr3 |= pEventCfg->Filter;
+ /* Update the HRTIM registers */
+ HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2;
+ HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3;
+ }
+ break;
+ case HRTIM_EVENT_7:
+ {
+ hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS);
+ hrtim_eecr2 |= (pEventCfg->Source << 6);
+ hrtim_eecr2 |= (pEventCfg->Polarity << 6);
+ hrtim_eecr2 |= (pEventCfg->Sensitivity << 6);
+ hrtim_eecr3 &= ~(HRTIM_EECR3_EE7F);
+ hrtim_eecr3 |= (pEventCfg->Filter << 6);
+ /* Update the HRTIM registers */
+ HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2;
+ HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3;
+ }
+ break;
+ case HRTIM_EVENT_8:
+ {
+ hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS);
+ hrtim_eecr2 |= (pEventCfg->Source << 12);
+ hrtim_eecr2 |= (pEventCfg->Polarity << 12);
+ hrtim_eecr2 |= (pEventCfg->Sensitivity << 12);
+ hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F);
+ hrtim_eecr3 |= (pEventCfg->Filter << 12);
+ /* Update the HRTIM registers */
+ HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2;
+ HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3;
+ }
+ break;
+ case HRTIM_EVENT_9:
+ {
+ hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS);
+ hrtim_eecr2 |= (pEventCfg->Source << 18);
+ hrtim_eecr2 |= (pEventCfg->Polarity << 18);
+ hrtim_eecr2 |= (pEventCfg->Sensitivity << 18);
+ hrtim_eecr3 &= ~(HRTIM_EECR3_EE9F);
+ hrtim_eecr3 |= (pEventCfg->Filter << 18);
+ /* Update the HRTIM registers */
+ HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2;
+ HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3;
+ }
+ break;
+ case HRTIM_EVENT_10:
+ {
+ hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS);
+ hrtim_eecr2 |= (pEventCfg->Source << 24);
+ hrtim_eecr2 |= (pEventCfg->Polarity << 24);
+ hrtim_eecr2 |= (pEventCfg->Sensitivity << 24);
+ hrtim_eecr3 &= ~(HRTIM_EECR3_EE10F);
+ hrtim_eecr3 |= (pEventCfg->Filter << 24);
+ /* Update the HRTIM registers */
+ HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2;
+ HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Configures the timer counter reset
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * @param Event: Event channel identifier
+ * @retval None
+ */
+void HRTIM_TIM_ResetConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t Event)
+{
+ switch (Event)
+ {
+ case HRTIM_EVENT_1:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1;
+ }
+ break;
+ case HRTIM_EVENT_2:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2;
+ }
+ break;
+ case HRTIM_EVENT_3:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3;
+ }
+ break;
+ case HRTIM_EVENT_4:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4;
+ }
+ break;
+ case HRTIM_EVENT_5:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5;
+ }
+ break;
+ case HRTIM_EVENT_6:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6;
+ }
+ break;
+ case HRTIM_EVENT_7:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7;
+ }
+ break;
+ case HRTIM_EVENT_8:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8;
+ }
+ break;
+ case HRTIM_EVENT_9:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9;
+ }
+ break;
+ case HRTIM_EVENT_10:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10;
+ }
+ break;
+ default:
+ break;
+ }
+}
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_hrtim.h Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,2723 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_hrtim.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the HRTIM firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_HRTIM_H
+#define __STM32F30x_HRTIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HRTIM Configuration Structure definition - Time base related parameters
+ */
+typedef struct
+{
+ uint32_t Period; /*!< Specifies the timer period
+ The period value must be above 3 periods of the fHRTIM clock.
+ Maximum value is = 0xFFDF */
+ uint32_t RepetitionCounter; /*!< Specifies the timer repetition period
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+ uint32_t PrescalerRatio; /*!< Specifies the timer clock prescaler ratio.
+ This parameter can be any value of @ref HRTIM_PrescalerRatio */
+ uint32_t Mode; /*!< Specifies the counter operating mode
+ This parameter can be any value of @ref HRTIM_Mode */
+} HRTIM_BaseInitTypeDef;
+/**
+ * @brief Waveform mode initialization parameters definition
+ */
+typedef struct {
+ uint32_t HalfModeEnable; /*!< Specifies whether or not half mode is enabled
+ This parameter can be a combination of @ref HRTIM_HalfModeEnable */
+ uint32_t StartOnSync; /*!< Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled)
+ This parameter can be a combination of @ref HRTIM_StartOnSyncInputEvent */
+ uint32_t ResetOnSync; /*!< Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled)
+ This parameter can be a combination of @ref HRTIM_ResetOnSyncInputEvent */
+ uint32_t DACSynchro; /*!< Indicates whether or not the a DAC synchronization event is generated
+ This parameter can be any value of @ref HRTIM_DACSynchronization */
+ uint32_t PreloadEnable; /*!< Specifies whether or not register preload is enabled
+ This parameter can be a combination of @ref HRTIM_RegisterPreloadEnable */
+ uint32_t UpdateGating; /*!< Specifies how the update occurs with respect to a burst DMA transaction or
+ update enable inputs (Slave timers only)
+ This parameter can be any value of @ref HRTIM_UpdateGating */
+ uint32_t BurstMode; /*!< Specifies how the timer behaves during a burst mode operation
+ This parameter can be a combination of @ref HRTIM_TimerBurstMode */
+ uint32_t RepetitionUpdate; /*!< Specifies whether or not registers update is triggered by the repetition event
+ This parameter can be a combination of @ref HRTIM_TimerRepetitionUpdate */
+} HRTIM_TimerInitTypeDef;
+
+/**
+ * @brief Basic output compare mode configuration definition
+ */
+typedef struct {
+ uint32_t Mode; /*!< Specifies the output compare mode (toggle, active, inactive)
+ This parameter can be a combination of @ref HRTIM_BasicOCMode */
+ uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
+ The compare value must be above or equal to 3 periods of the fHRTIM clock */
+ uint32_t Polarity; /*!< Specifies the output polarity
+ This parameter can be any value of @ref HRTIM_Output_Polarity */
+ uint32_t IdleState; /*!< Specifies whether the output level is active or inactive when in IDLE state
+ This parameter can be any value of @ref HRTIM_OutputIDLEState */
+} HRTIM_BasicOCChannelCfgTypeDef;
+
+/**
+ * @brief Basic PWM output mode configuration definition
+ */
+typedef struct {
+ uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
+ The compare value must be above or equal to 3 periods of the fHRTIM clock */
+ uint32_t Polarity; /*!< Specifies the output polarity
+ This parameter can be any value of @ref HRTIM_OutputPolarity */
+ uint32_t IdleState; /*!< Specifies whether the output level is active or inactive when in IDLE state
+ This parameter can be any value of @ref HRTIM_OutputIDLEState */
+} HRTIM_BasicPWMChannelCfgTypeDef;
+
+/**
+ * @brief Basic capture mode configuration definition
+ */
+typedef struct {
+ uint32_t CaptureUnit; /*!< Specifies the external event Channel
+ This parameter can be any 'EEVx' value of @ref HRTIM_CaptureUnit */
+ uint32_t Event; /*!< Specifies the external event triggering the capture
+ This parameter can be any 'EEVx' value of @ref HRTIM_ExternalEventChannels */
+ uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity)
+ This parameter can be a value of @ref HRTIM_ExternalEventPolarity */
+ uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event
+ This parameter can be a value of @ref HRTIM_ExternalEventSensitivity */
+ uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter
+ This parameter can be a value of @ref HRTIM_ExternalEventFilter */
+} HRTIM_BasicCaptureChannelCfgTypeDef;
+
+/**
+ * @brief Basic One Pulse mode configuration definition
+ */
+typedef struct {
+ uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
+ The compare value must be above or equal to 3 periods of the fHRTIM clock */
+ uint32_t OutputPolarity; /*!< Specifies the output polarity
+ This parameter can be any value of @ref HRTIM_Output_Polarity */
+ uint32_t OutputIdleState; /*!< Specifies whether the output level is active or inactive when in IDLE state
+ This parameter can be any value of @ref HRTIM_Output_IDLE_State */
+ uint32_t Event; /*!< Specifies the external event triggering the pulse generation
+ This parameter can be any 'EEVx' value of @ref HRTIM_Capture_Unit_Trigger */
+ uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity)
+ This parameter can be a value of @ref HRTIM_ExternalEventPolarity */
+ uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event
+ This parameter can be a value of @ref HRTIM_ExternalEventSensitivity */
+ uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter
+ This parameter can be a value of @ref HRTIM_ExternalEventFilter */
+} HRTIM_BasicOnePulseChannelCfgTypeDef;
+
+/**
+ * @brief Timer configuration definition
+ */
+typedef struct {
+ uint32_t PushPull; /*!< Specifies whether or not the push-pull mode is enabled
+ This parameter can be a value of @ref HRTIM_TimerPushPullMode */
+ uint32_t FaultEnable; /*!< Specifies which fault channels are enabled for the timer
+ This parameter can be a combination of @ref HRTIM_TimerFaultEnabling */
+ uint32_t FaultLock; /*!< Specifies whether or not fault enabling status is write protected
+ This parameter can be a value of @ref HRTIM_TimerFaultLock */
+ uint32_t DeadTimeInsertion; /*!< Specifies whether or not dead time insertion is enabled for the timer
+ This parameter can be a value of @ref HRTIM_TimerDeadtimeInsertion */
+ uint32_t DelayedProtectionMode; /*!< Specifies the delayed protection mode
+ This parameter can be a value of @ref HRTIM_TimerDelayedProtectionMode */
+ uint32_t UpdateTrigger; /*!< Specifies source(s) triggering the timer registers update
+ This parameter can be a combination of @ref HRTIM_TimerUpdateTrigger */
+ uint32_t ResetTrigger; /*!< Specifies source(s) triggering the timer counter reset
+ This parameter can be a combination of @ref HRTIM_TimerResetTrigger */
+ uint32_t ResetUpdate; /*!< Specifies whether or not registers update is triggered when the timer counter is reset
+ This parameter can be a combination of @ref HRTIM_TimerResetUpdate */
+} HRTIM_TimerCfgTypeDef;
+
+/**
+ * @brief Compare unit configuration definition
+ */
+typedef struct {
+ uint32_t CompareValue; /*!< Specifies the compare value of the timer compare unit
+ the minimum value must be greater than or equal to 3 periods of the fHRTIM clock
+ the maximum value must be less than or equal to 0xFFFF - 1 periods of the fHRTIM clock */
+ uint32_t AutoDelayedMode; /*!< Specifies the auto delayed mode for compare unit 2 or 4
+ This parameter can be a value of @ref HRTIM_CompareUnitAutoDelayedMode */
+ uint32_t AutoDelayedTimeout; /*!< Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected
+ CompareValue + AutoDelayedTimeout must be less than 0xFFFF */
+} HRTIM_CompareCfgTypeDef;
+
+/**
+ * @brief Capture unit configuration definition
+ */
+typedef struct {
+ uint32_t Trigger; /*!< Specifies source(s) triggering the capture
+ This parameter can be a combination of @ref HRTIM_CaptureUnitTrigger */
+} HRTIM_CaptureCfgTypeDef;
+
+/**
+ * @brief Output configuration definition
+ */
+typedef struct {
+ uint32_t Polarity; /*!< Specifies the output polarity
+ This parameter can be any value of @ref HRTIM_Output_Polarity */
+ uint32_t SetSource; /*!< Specifies the event(s) transitioning the output from its inactive level to its active level
+ This parameter can be any value of @ref HRTIM_OutputSetSource */
+ uint32_t ResetSource; /*!< Specifies the event(s) transitioning the output from its active level to its inactive level
+ This parameter can be any value of @ref HRTIM_OutputResetSource */
+ uint32_t IdleMode; /*!< Specifies whether or not the output is affected by a burst mode operation
+ This parameter can be any value of @ref HRTIM_OutputIdleMode */
+ uint32_t IdleState; /*!< Specifies whether the output level is active or inactive when in IDLE state
+ This parameter can be any value of @ref HRTIM_OutputIDLEState */
+ uint32_t FaultState; /*!< Specifies whether the output level is active or inactive when in FAULT state
+ This parameter can be any value of @ref HRTIM_OutputFAULTState */
+ uint32_t ChopperModeEnable; /*!< Indicates whether or not the chopper mode is enabled
+ This parameter can be any value of @ref HRTIM_OutputChopperModeEnable */
+ uint32_t BurstModeEntryDelayed; /* !<Indicates whether or not deadtime is inserted when entering the IDLE state
+ during a burst mode operation
+ This parameters can be any value of @ref HRTIM_OutputBurstModeEntryDelayed */
+} HRTIM_OutputCfgTypeDef;
+
+/**
+ * @brief External event filtering in timing units configuration definition
+ */
+typedef struct {
+ uint32_t Filter; /*!< Specifies the type of event filtering within the timing unit
+ This parameter can be a value of @ref HRTIM_TimerExternalEventFilter */
+ uint32_t Latch; /*!< Specifies whether or not the signal is latched
+ This parameter can be a value of @ref HRTIM_TimerExternalEventLatch */
+} HRTIM_TimerEventFilteringCfgTypeDef;
+
+/**
+ * @brief Dead time feature configuration definition
+ */
+typedef struct {
+ uint32_t Prescaler; /*!< Specifies the Deadtime Prescaler
+ This parameter can be a number between 0x0 and = 0x7 */
+ uint32_t RisingValue; /*!< Specifies the Deadtime following a rising edge
+ This parameter can be a number between 0x0 and 0xFF */
+ uint32_t RisingSign; /*!< Specifies whether the deadtime is positive or negative on rising edge
+ This parameter can be a value of @ref HRTIM_DeadtimeRisingSign */
+ uint32_t RisingLock; /*!< Specifies whether or not deadtime rising settings (value and sign) are write protected
+ This parameter can be a value of @ref HRTIM_DeadtimeRisingLock */
+ uint32_t RisingSignLock; /*!< Specifies whether or not deadtime rising sign is write protected
+ This parameter can be a value of @ref HRTIM_DeadtimeRisingSignLock */
+ uint32_t FallingValue; /*!< Specifies the Deadtime following a falling edge
+ This parameter can be a number between 0x0 and 0xFF */
+ uint32_t FallingSign; /*!< Specifies whether the deadtime is positive or negative on falling edge
+ This parameter can be a value of @ref HRTIM_DeadtimeFallingSign */
+ uint32_t FallingLock; /*!< Specifies whether or not deadtime falling settings (value and sign) are write protected
+ This parameter can be a value of @ref HRTIM_DeadtimeFallingLock */
+ uint32_t FallingSignLock; /*!< Specifies whether or not deadtime falling sign is write protected
+ This parameter can be a value of @ref HRTIM_DeadtimeFallingSignLock */
+} HRTIM_DeadTimeCfgTypeDef;
+
+/**
+ * @brief Chopper mode configuration definition
+ */
+typedef struct {
+ uint32_t CarrierFreq; /*!< Specifies the Timer carrier frequency value.
+ This parameter can be a value between 0 and 0xF */
+ uint32_t DutyCycle; /*!< Specifies the Timer chopper duty cycle value.
+ This parameter can be a value between 0 and 0x7 */
+ uint32_t StartPulse; /*!< Specifies the Timer pulse width value.
+ This parameter can be a value between 0 and 0xF */
+} HRTIM_ChopperModeCfgTypeDef;
+
+/**
+ * @brief Master synchronization configuration definition
+ */
+typedef struct {
+ uint32_t SyncInputSource; /*!< Specifies the external synchronization input source
+ This parameter can be a value of @ref HRTIM_SynchronizationInputSource */
+ uint32_t SyncOutputSource; /*!< Specifies the source and event to be sent on the external synchronization outputs
+ This parameter can be a value of @ref HRTIM_SynchronizationOutputSource */
+ uint32_t SyncOutputPolarity; /*!< Specifies the conditioning of the event to be sent on the external synchronization outputs
+ This parameter can be a value of @ref HRTIM_SynchronizationOutputPolarity */
+} HRTIM_SynchroCfgTypeDef;
+
+/**
+ * @brief External event channel configuration definition
+ */
+typedef struct {
+ uint32_t Source; /*!< Identifies the source of the external event
+ This parameter can be a value of @ref HRTIM_ExternalEventSources */
+ uint32_t Polarity; /*!< Specifies the polarity of the external event (in case of level sensitivity)
+ This parameter can be a value of @ref HRTIM_ExternalEventPolarity */
+ uint32_t Sensitivity; /*!< Specifies the sensitivity of the external event
+ This parameter can be a value of @ref HRTIM_ExternalEventSensitivity */
+ uint32_t Filter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter
+ This parameter can be a value of @ref HRTIM_ExternalEventFilter */
+ uint32_t FastMode; /*!< Indicates whether or not low latency mode is enabled for the external event
+ This parameter can be a value of @ref HRTIM_ExternalEventFastMode */
+} HRTIM_EventCfgTypeDef;
+
+/**
+ * @brief Fault channel configuration definition
+ */
+typedef struct {
+ uint32_t Source; /*!< Identifies the source of the fault
+ This parameter can be a value of @ref HRTIM_FaultSources */
+ uint32_t Polarity; /*!< Specifies the polarity of the fault event
+ This parameter can be a value of @ref HRTIM_FaultPolarity */
+ uint32_t Filter; /*!< Defines the frequency used to sample the Fault input and the length of the digital filter
+ This parameter can be a value of @ref HRTIM_FaultFilter */
+ uint32_t Lock; /*!< Indicates whether or not fault programming bits are write protected
+ This parameter can be a value of @ref HRTIM_FaultLock */
+} HRTIM_FaultCfgTypeDef;
+
+/**
+ * @brief Burst mode configuration definition
+ */
+typedef struct {
+ uint32_t Mode; /*!< Specifies the burst mode operating mode
+ This parameter can be a value of @ref HRTIM_BurstModeOperatingMode */
+ uint32_t ClockSource; /*!< Specifies the burst mode clock source
+ This parameter can be a value of @ref HRTIM_BurstModeClockSource */
+ uint32_t Prescaler; /*!< Specifies the burst mode prescaler
+ This parameter can be a value of @ref HRTIM_BurstModePrescaler */
+ uint32_t PreloadEnable; /*!< Specifies whether or not preload is enabled for burst mode related registers (HRTIM_BMCMPR and HRTIM_BMPER)
+ This parameter can be a combination of @ref HRTIM_BurstModeRegisterPreloadEnable */
+ uint32_t Trigger; /*!< Specifies the event(s) triggering the burst operation
+ This parameter can be a combination of @ref HRTIM_BurstModeTrigger */
+ uint32_t IdleDuration; /*!< Specifies number of periods during which the selected timers are in idle state
+ This parameter can be a number between 0x0 and 0xFFFF */
+ uint32_t Period; /*!< Specifies burst mode repetition period
+ This parameter can be a number between 0x1 and 0xFFFF */
+} HRTIM_BurstModeCfgTypeDef;
+
+/**
+ * @brief ADC trigger configuration definition
+ */
+typedef struct {
+ uint32_t UpdateSource; /*!< Specifies the ADC trigger update source
+ This parameter can be a combination of @ref HRTIM_ADCTriggerUpdateSource */
+ uint32_t Trigger; /*!< Specifies the event(s) triggering the ADC conversion
+ This parameter can be a combination of @ref HRTIM_ADCTriggerEvent */
+} HRTIM_ADCTriggerCfgTypeDef;
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup HRTIM_Exported_Constants
+ * @{
+ */
+
+/** @defgroup HRTIM_TimerIndex
+ * @{
+ * @brief Constants defining the timer indexes
+ */
+#define HRTIM_TIMERINDEX_TIMER_A (uint32_t)0x0 /*!< Index associated to timer A */
+#define HRTIM_TIMERINDEX_TIMER_B (uint32_t)0x1 /*!< Index associated to timer B */
+#define HRTIM_TIMERINDEX_TIMER_C (uint32_t)0x2 /*!< Index associated to timer C */
+#define HRTIM_TIMERINDEX_TIMER_D (uint32_t)0x3 /*!< Index associated to timer D */
+#define HRTIM_TIMERINDEX_TIMER_E (uint32_t)0x4 /*!< Index associated to timer E */
+#define HRTIM_TIMERINDEX_MASTER (uint32_t)0x5 /*!< Index associated to master timer */
+#define HRTIM_COMMONINDEX (uint32_t)0x6 /*!< Index associated to Common space */
+
+#define IS_HRTIM_TIMERINDEX(TIMERINDEX)\
+ (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) || \
+ ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \
+ ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \
+ ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \
+ ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \
+ ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
+
+#define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\
+ (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \
+ ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \
+ ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \
+ ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \
+ ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_TimerIdentifier
+ * @{
+ * @brief Constants defining timer identifiers
+ */
+#define HRTIM_TIMERID_MASTER (HRTIM_MCR_MCEN) /*!< Master identifier*/
+#define HRTIM_TIMERID_TIMER_A (HRTIM_MCR_TACEN) /*!< Timer A identifier */
+#define HRTIM_TIMERID_TIMER_B (HRTIM_MCR_TBCEN) /*!< Timer B identifier */
+#define HRTIM_TIMERID_TIMER_C (HRTIM_MCR_TCCEN) /*!< Timer C identifier */
+#define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN) /*!< Timer D identifier */
+#define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN) /*!< Timer E identifier */
+
+#define IS_HRTIM_TIMERID(TIMERID)\
+ (((TIMERID) == HRTIM_TIMERID_MASTER) || \
+ ((TIMERID) == HRTIM_TIMERID_TIMER_A) || \
+ ((TIMERID) == HRTIM_TIMERID_TIMER_B) || \
+ ((TIMERID) == HRTIM_TIMERID_TIMER_C) || \
+ ((TIMERID) == HRTIM_TIMERID_TIMER_D) || \
+ ((TIMERID) == HRTIM_TIMERID_TIMER_E))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_CompareUnit
+ * @{
+ * @brief Constants defining compare unit identifiers
+ */
+#define HRTIM_COMPAREUNIT_1 (uint32_t)0x00000001 /*!< Compare unit 1 identifier */
+#define HRTIM_COMPAREUNIT_2 (uint32_t)0x00000002 /*!< Compare unit 2 identifier */
+#define HRTIM_COMPAREUNIT_3 (uint32_t)0x00000004 /*!< Compare unit 3 identifier */
+#define HRTIM_COMPAREUNIT_4 (uint32_t)0x00000008 /*!< Compare unit 4 identifier */
+
+#define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\
+ (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) || \
+ ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) || \
+ ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) || \
+ ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4))
+ /**
+ * @}
+ */
+
+/** @defgroup HRTIM_CaptureUnit
+ * @{
+ * @brief Constants defining capture unit identifiers
+ */
+#define HRTIM_CAPTUREUNIT_1 (uint32_t)0x00000001 /*!< Capture unit 1 identifier */
+#define HRTIM_CAPTUREUNIT_2 (uint32_t)0x00000002 /*!< Capture unit 2 identifier */
+
+#define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\
+ (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) || \
+ ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_TimerOutput
+ * @{
+ * @brief Constants defining timer output identifiers
+ */
+#define HRTIM_OUTPUT_TA1 (uint32_t)0x00000001 /*!< Timer A - Ouput 1 identifier */
+#define HRTIM_OUTPUT_TA2 (uint32_t)0x00000002 /*!< Timer A - Ouput 2 identifier */
+#define HRTIM_OUTPUT_TB1 (uint32_t)0x00000004 /*!< Timer B - Ouput 1 identifier */
+#define HRTIM_OUTPUT_TB2 (uint32_t)0x00000008 /*!< Timer B - Ouput 2 identifier */
+#define HRTIM_OUTPUT_TC1 (uint32_t)0x00000010 /*!< Timer C - Ouput 1 identifier */
+#define HRTIM_OUTPUT_TC2 (uint32_t)0x00000020 /*!< Timer C - Ouput 2 identifier */
+#define HRTIM_OUTPUT_TD1 (uint32_t)0x00000040 /*!< Timer D - Ouput 1 identifier */
+#define HRTIM_OUTPUT_TD2 (uint32_t)0x00000080 /*!< Timer D - Ouput 2 identifier */
+#define HRTIM_OUTPUT_TE1 (uint32_t)0x00000100 /*!< Timer E - Ouput 1 identifier */
+#define HRTIM_OUTPUT_TE2 (uint32_t)0x00000200 /*!< Timer E - Ouput 2 identifier */
+
+#define IS_HRTIM_OUTPUT(OUTPUT)\
+ (((OUTPUT) == HRTIM_OUTPUT_TA1) || \
+ ((OUTPUT) == HRTIM_OUTPUT_TA2) || \
+ ((OUTPUT) == HRTIM_OUTPUT_TB1) || \
+ ((OUTPUT) == HRTIM_OUTPUT_TB2) || \
+ ((OUTPUT) == HRTIM_OUTPUT_TC1) || \
+ ((OUTPUT) == HRTIM_OUTPUT_TC2) || \
+ ((OUTPUT) == HRTIM_OUTPUT_TD1) || \
+ ((OUTPUT) == HRTIM_OUTPUT_TD2) || \
+ ((OUTPUT) == HRTIM_OUTPUT_TE1) || \
+ ((OUTPUT) == HRTIM_OUTPUT_TE2))
+
+#define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\
+ ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
+ (((OUTPUT) == HRTIM_OUTPUT_TA1) || \
+ ((OUTPUT) == HRTIM_OUTPUT_TA2))) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
+ (((OUTPUT) == HRTIM_OUTPUT_TB1) || \
+ ((OUTPUT) == HRTIM_OUTPUT_TB2))) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
+ (((OUTPUT) == HRTIM_OUTPUT_TC1) || \
+ ((OUTPUT) == HRTIM_OUTPUT_TC2))) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
+ (((OUTPUT) == HRTIM_OUTPUT_TD1) || \
+ ((OUTPUT) == HRTIM_OUTPUT_TD2))) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
+ (((OUTPUT) == HRTIM_OUTPUT_TE1) || \
+ ((OUTPUT) == HRTIM_OUTPUT_TE2))))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_ADCTrigger
+ * @{
+ * @brief Constants defining ADC triggers identifiers
+ */
+#define HRTIM_ADCTRIGGER_1 (uint32_t)0x00000001 /*!< ADC trigger 1 identifier */
+#define HRTIM_ADCTRIGGER_2 (uint32_t)0x00000002 /*!< ADC trigger 1 identifier */
+#define HRTIM_ADCTRIGGER_3 (uint32_t)0x00000004 /*!< ADC trigger 1 identifier */
+#define HRTIM_ADCTRIGGER_4 (uint32_t)0x00000008 /*!< ADC trigger 1 identifier */
+
+#define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\
+ (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \
+ ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) || \
+ ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) || \
+ ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_ExternalEventChannels
+ * @{
+ * @brief Constants defining external event channel identifiers
+ */
+#define HRTIM_EVENT_NONE ((uint32_t)0x00000000) /*!< Undefined event channel */
+#define HRTIM_EVENT_1 ((uint32_t)0x00000001) /*!< External event channel 1 identifier */
+#define HRTIM_EVENT_2 ((uint32_t)0x00000002) /*!< External event channel 2 identifier */
+#define HRTIM_EVENT_3 ((uint32_t)0x00000004) /*!< External event channel 3 identifier */
+#define HRTIM_EVENT_4 ((uint32_t)0x00000008) /*!< External event channel 4 identifier */
+#define HRTIM_EVENT_5 ((uint32_t)0x00000010) /*!< External event channel 5 identifier */
+#define HRTIM_EVENT_6 ((uint32_t)0x00000020) /*!< External event channel 6 identifier */
+#define HRTIM_EVENT_7 ((uint32_t)0x00000040) /*!< External event channel 7 identifier */
+#define HRTIM_EVENT_8 ((uint32_t)0x00000080) /*!< External event channel 8 identifier */
+#define HRTIM_EVENT_9 ((uint32_t)0x00000100) /*!< External event channel 9 identifier */
+#define HRTIM_EVENT_10 ((uint32_t)0x00000200) /*!< External event channel 10 identifier */
+
+#define IS_HRTIM_EVENT(EVENT)\
+ (((EVENT) == HRTIM_EVENT_1) || \
+ ((EVENT) == HRTIM_EVENT_2) || \
+ ((EVENT) == HRTIM_EVENT_3) || \
+ ((EVENT) == HRTIM_EVENT_4) || \
+ ((EVENT) == HRTIM_EVENT_5) || \
+ ((EVENT) == HRTIM_EVENT_6) || \
+ ((EVENT) == HRTIM_EVENT_7) || \
+ ((EVENT) == HRTIM_EVENT_8) || \
+ ((EVENT) == HRTIM_EVENT_9) || \
+ ((EVENT) == HRTIM_EVENT_10))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_FaultChannel
+ * @{
+ * @brief Constants defining fault channel identifiers
+ */
+#define HRTIM_FAULT_1 ((uint32_t)0x01) /*!< Fault channel 1 identifier */
+#define HRTIM_FAULT_2 ((uint32_t)0x02) /*!< Fault channel 2 identifier */
+#define HRTIM_FAULT_3 ((uint32_t)0x04) /*!< Fault channel 3 identifier */
+#define HRTIM_FAULT_4 ((uint32_t)0x08) /*!< Fault channel 4 identifier */
+#define HRTIM_FAULT_5 ((uint32_t)0x10) /*!< Fault channel 5 identifier */
+
+#define IS_HRTIM_FAULT(FAULT)\
+ (((FAULT) == HRTIM_FAULT_1) || \
+ ((FAULT) == HRTIM_FAULT_2) || \
+ ((FAULT) == HRTIM_FAULT_3) || \
+ ((FAULT) == HRTIM_FAULT_4) || \
+ ((FAULT) == HRTIM_FAULT_5))
+/**
+ * @}
+ */
+
+
+ /** @defgroup HRTIM_PrescalerRatio
+ * @{
+ * @brief Constants defining timer high-resolution clock prescaler ratio.
+ */
+#define HRTIM_PRESCALERRATIO_MUL32 ((uint32_t)0x00000000) /*!< fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */
+#define HRTIM_PRESCALERRATIO_MUL16 ((uint32_t)0x00000001) /*!< fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */
+#define HRTIM_PRESCALERRATIO_MUL8 ((uint32_t)0x00000002) /*!< fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */
+#define HRTIM_PRESCALERRATIO_MUL4 ((uint32_t)0x00000003) /*!< fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */
+#define HRTIM_PRESCALERRATIO_MUL2 ((uint32_t)0x00000004) /*!< fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */
+#define HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005) /*!< fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */
+#define HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006) /*!< fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */
+#define HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007) /*!< fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */
+
+#define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\
+ (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) || \
+ ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) || \
+ ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8) || \
+ ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4) || \
+ ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2) || \
+ ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \
+ ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \
+ ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Mode
+ * @{
+ * @brief Constants defining timer counter operating mode.
+ */
+#define HRTIM_MODE_CONTINOUS ((uint32_t)0x00000008) /*!< The timer operates in continuous (free-running) mode */
+#define HRTIM_MODE_SINGLESHOT ((uint32_t)0x00000000) /*!< The timer operates in non retriggerable single-shot mode */
+#define HRTIM_MODE_SINGLESHOT_RETRIGGERABLE ((uint32_t)0x00000010) /*!< The timer operates in retriggerable single-shot mode */
+
+#define IS_HRTIM_MODE(MODE)\
+ (((MODE) == HRTIM_MODE_CONTINOUS) || \
+ ((MODE) == HRTIM_MODE_SINGLESHOT) || \
+ ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
+
+#define IS_HRTIM_MODE_ONEPULSE(MODE)\
+ (((MODE) == HRTIM_MODE_SINGLESHOT) || \
+ ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_HalfModeEnable
+ * @{
+ * @brief Constants defining half mode enabling status.
+ */
+#define HRTIM_HALFMODE_DISABLED ((uint32_t)0x00000000) /*!< Half mode is disabled */
+#define HRTIM_HALFMODE_ENABLED ((uint32_t)0x00000020) /*!< Half mode is enabled */
+
+#define IS_HRTIM_HALFMODE(HALFMODE)\
+ (((HALFMODE) == HRTIM_HALFMODE_DISABLED) || \
+ ((HALFMODE) == HRTIM_HALFMODE_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_StartOnSyncInputEvent
+ * @{
+ * @brief Constants defining the timer behavior following the synchronization event
+ */
+#define HRTIM_SYNCSTART_DISABLED ((uint32_t)0x00000000) /*!< Synchronization input event has effect on the timer */
+#define HRTIM_SYNCSTART_ENABLED (HRTIM_MCR_SYNCSTRTM) /*!< Synchronization input event starts the timer */
+
+#define IS_HRTIM_SYNCSTART(SYNCSTART)\
+ (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) || \
+ ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_ResetOnSyncInputEvent
+ * @{
+ * @brief Constants defining the timer behavior following the synchronization event
+ */
+#define HRTIM_SYNCRESET_DISABLED ((uint32_t)0x00000000) /*!< Synchronization input event has effect on the timer */
+#define HRTIM_SYNCRESET_ENABLED (HRTIM_MCR_SYNCRSTM) /*!< Synchronization input event resets the timer */
+
+#define IS_HRTIM_SYNCRESET(SYNCRESET)\
+ (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) || \
+ ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_DACSynchronization
+ * @{
+ * @brief Constants defining on which output the DAC synchronization event is sent
+ */
+#define HRTIM_DACSYNC_NONE (uint32_t)0x00000000 /*!< No DAC synchronization event generated */
+#define HRTIM_DACSYNC_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */
+#define HRTIM_DACSYNC_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */
+#define HRTIM_DACSYNC_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC update generated on DACTrigOut3 output upon timer update */
+
+#define IS_HRTIM_DACSYNC(DACSYNC)\
+ (((DACSYNC) == HRTIM_DACSYNC_NONE) || \
+ ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) || \
+ ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) || \
+ ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_RegisterPreloadEnable
+ * @{
+ * @brief Constants defining whether a write access into a preloadable
+ * register is done into the active or the preload register.
+ */
+#define HRTIM_PRELOAD_DISABLED ((uint32_t)0x00000000) /*!< Preload disabled: the write access is directly done into the active register */
+#define HRTIM_PRELOAD_ENABLED (HRTIM_MCR_PREEN) /*!< Preload enabled: the write access is done into the preload register */
+
+#define IS_HRTIM_PRELOAD(PRELOAD)\
+ (((PRELOAD) == HRTIM_PRELOAD_DISABLED) || \
+ ((PRELOAD) == HRTIM_PRELOAD_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_UpdateGating
+ * @{
+ * @brief Constants defining how the update occurs relatively to the burst DMA
+ * transaction and the external update request on update enable inputs 1 to 3.
+ */
+#define HRTIM_UPDATEGATING_INDEPENDENT (uint32_t)0x00000000 /*!< Update done independently from the DMA burst transfer completion */
+#define HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /*!< Update done when the DMA burst transfer is completed */
+#define HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /*!< Update done on timer roll-over following a DMA burst transfer completion*/
+#define HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1 */
+#define HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2 */
+#define HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3 */
+#define HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1 */
+#define HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2 */
+#define HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3 */
+
+#define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\
+ (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \
+ ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \
+ ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE))
+
+#define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\
+ (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \
+ ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \
+ ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) || \
+ ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) || \
+ ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) || \
+ ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) || \
+ ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) || \
+ ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) || \
+ ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_TimerBurstMode
+ * @{
+ * @brief Constants defining how the timer behaves during a burst
+ mode operation.
+ */
+#define HRTIM_TIMERBURSTMODE_MAINTAINCLOCK (uint32_t)0x000000 /*!< Timer counter clock is maintained and the timer operates normally */
+#define HRTIM_TIMERBURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /*!< Timer counter clock is stopped and the counter is reset */
+
+#define IS_HRTIM_TIMERBURSTMODE(TIMERBURSTMODE) \
+ (((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) || \
+ ((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_TimerRepetitionUpdate
+ * @{
+ * @brief Constants defining whether registers are updated when the timer
+ * repetition period is completed (either due to roll-over or
+ * reset events)
+ */
+#define HRTIM_UPDATEONREPETITION_DISABLED (uint32_t)0x00000000 /*!< Update on repetition disabled */
+#define HRTIM_UPDATEONREPETITION_ENABLED (HRTIM_MCR_MREPU) /*!< Update on repetition enabled */
+
+#define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION) \
+ (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) || \
+ ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED))
+/**
+ * @}
+ */
+
+
+/** @defgroup HRTIM_TimerPushPullMode
+ * @{
+ * @brief Constants defining whether or not the push-pull mode is enabled for
+ * a timer.
+ */
+#define HRTIM_TIMPUSHPULLMODE_DISABLED ((uint32_t)0x00000000) /*!< Push-Pull mode disabled */
+#define HRTIM_TIMPUSHPULLMODE_ENABLED ((uint32_t)HRTIM_TIMCR_PSHPLL) /*!< Push-Pull mode enabled */
+
+#define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\
+ (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \
+ ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_TimerFaultEnabling
+ * @{
+ * @brief Constants defining whether a faut channel is enabled for a timer
+ */
+#define HRTIM_TIMFAULTENABLE_NONE (uint32_t)0x00000000 /*!< No fault enabled */
+#define HRTIM_TIMFAULTENABLE_FAULT1 (HRTIM_FLTR_FLT1EN) /*!< Fault 1 enabled */
+#define HRTIM_TIMFAULTENABLE_FAULT2 (HRTIM_FLTR_FLT2EN) /*!< Fault 2 enabled */
+#define HRTIM_TIMFAULTENABLE_FAULT3 (HRTIM_FLTR_FLT3EN) /*!< Fault 3 enabled */
+#define HRTIM_TIMFAULTENABLE_FAULT4 (HRTIM_FLTR_FLT4EN) /*!< Fault 4 enabled */
+#define HRTIM_TIMFAULTENABLE_FAULT5 (HRTIM_FLTR_FLT5EN) /*!< Fault 5 enabled */
+
+#define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0) == 0x00000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_TimerFaultLock
+ * @{
+ * @brief Constants defining whether or not fault enabling bits are write
+ * protected for a timer
+ */
+#define HRTIM_TIMFAULTLOCK_READWRITE ((uint32_t)0x00000000) /*!< Timer fault enabling bits are read/write */
+#define HRTIM_TIMFAULTLOCK_READONLY (HRTIM_FLTR_FLTCLK) /*!< Timer fault enabling bits are read only */
+
+#define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\
+ (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \
+ ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_TimerDeadtimeInsertion
+ * @{
+ * @brief Constants defining whether or not fault the dead time insertion
+ * feature is enabled for a timer
+ */
+#define HRTIM_TIMDEADTIMEINSERTION_DISABLED ((uint32_t)0x00000000) /*!< Output 1 and output 2 signals are independent */
+#define HRTIM_TIMDEADTIMEINSERTION_ENABLED HRTIM_OUTR_DTEN /*!< Deadtime is inserted between output 1 and output 2 */
+
+#define IS_HRTIM_TIMDEADTIMEINSERTION(TIMDEADTIMEINSERTION)\
+ (((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \
+ ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_TimerDelayedProtectionMode
+ * @{
+ * @brief Constants defining all possible delayed protection modes
+ * for a timer. Also define the source and outputs on which the delayed
+ * protection schemes are applied
+ */
+#define HRTIM_TIMDELAYEDPROTECTION_DISABLED ((uint32_t)0x00000000) /*!< No action */
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 (HRTIM_OUTR_DLYPRTEN) /*!< Output 1 delayed Idle on external Event 6 or 8 */
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Output 2 delayed Idle on external Event 6 or 8 */
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Output 1 and output 2 delayed Idle on external Event 6 or 8 */
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Balanced Idle on external Event 6 or 8 */
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Output 1 delayed Idle on external Event 7 or 9 */
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Output 2 delayed Idle on external Event 7 or 9 */
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Output 1 and output2 delayed Idle on external Event 7 or 9 */
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Balanced Idle on external Event 7 or 9 */
+
+#define IS_HRTIM_TIMDELAYEDPROTECTION(TIMDELAYEDPROTECTION)\
+ (((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DISABLED) || \
+ ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68) || \
+ ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68) || \
+ ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68) || \
+ ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68) || \
+ ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79) || \
+ ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79) || \
+ ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79) || \
+ ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_TimerUpdateTrigger
+ * @{
+ * @brief Constants defining whether the registers update is done synchronously
+ * with any other timer or master update
+ */
+#define HRTIM_TIMUPDATETRIGGER_NONE (uint32_t)0x00000000 /*!< Register update is disabled */
+#define HRTIM_TIMUPDATETRIGGER_MASTER (HRTIM_TIMCR_MSTU) /*!< Register update is triggered by the master timer update */
+#define HRTIM_TIMUPDATETRIGGER_TIMER_A (HRTIM_TIMCR_TAU) /*!< Register update is triggered by the timer A update */
+#define HRTIM_TIMUPDATETRIGGER_TIMER_B (HRTIM_TIMCR_TBU) /*!< Register update is triggered by the timer B update */
+#define HRTIM_TIMUPDATETRIGGER_TIMER_C (HRTIM_TIMCR_TCU) /*!< Register update is triggered by the timer C update*/
+#define HRTIM_TIMUPDATETRIGGER_TIMER_D (HRTIM_TIMCR_TDU) /*!< Register update is triggered by the timer D update */
+#define HRTIM_TIMUPDATETRIGGER_TIMER_E (HRTIM_TIMCR_TEU) /*!< Register update is triggered by the timer E update */
+
+#define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFF) == 0x00000000)
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_TimerResetTrigger
+ * @{
+ * @brief Constants defining the events that can be selected to trigger the reset
+ * of the timer counter
+ */
+#define HRTIM_TIMRESETTRIGGER_NONE (uint32_t)0x00000000 /*!< No counter reset trigger */
+#define HRTIM_TIMRESETTRIGGER_UPDATE (HRTIM_RSTR_UPDATE) /*!< The timer counter is reset upon update event */
+#define HRTIM_TIMRESETTRIGGER_CMP2 (HRTIM_RSTR_CMP2) /*!< The timer counter is reset upon Timer Compare 2 event */
+#define HRTIM_TIMRESETTRIGGER_CMP4 (HRTIM_RSTR_CMP4) /*!< The timer counter is reset upon Timer Compare 4 event */
+#define HRTIM_TIMRESETTRIGGER_MASTER_PER (HRTIM_RSTR_MSTPER) /*!< The timer counter is reset upon master timer period event */
+#define HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1) /*!< The timer counter is reset upon master timer Compare 1 event */
+#define HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2) /*!< The timer counter is reset upon master timer Compare 2 event */
+#define HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3) /*!< The timer counter is reset upon master timer Compare 3 event */
+#define HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4) /*!< The timer counter is reset upon master timer Compare 4 event */
+#define HRTIM_TIMRESETTRIGGER_EEV_1 (HRTIM_RSTR_EXTEVNT1) /*!< The timer counter is reset upon external event 1 */
+#define HRTIM_TIMRESETTRIGGER_EEV_2 (HRTIM_RSTR_EXTEVNT2) /*!< The timer counter is reset upon external event 2 */
+#define HRTIM_TIMRESETTRIGGER_EEV_3 (HRTIM_RSTR_EXTEVNT3) /*!< The timer counter is reset upon external event 3 */
+#define HRTIM_TIMRESETTRIGGER_EEV_4 (HRTIM_RSTR_EXTEVNT4) /*!< The timer counter is reset upon external event 4 */
+#define HRTIM_TIMRESETTRIGGER_EEV_5 (HRTIM_RSTR_EXTEVNT5) /*!< The timer counter is reset upon external event 5 */
+#define HRTIM_TIMRESETTRIGGER_EEV_6 (HRTIM_RSTR_EXTEVNT6) /*!< The timer counter is reset upon external event 6 */
+#define HRTIM_TIMRESETTRIGGER_EEV_7 (HRTIM_RSTR_EXTEVNT7) /*!< The timer counter is reset upon external event 7 */
+#define HRTIM_TIMRESETTRIGGER_EEV_8 (HRTIM_RSTR_EXTEVNT8) /*!< The timer counter is reset upon external event 8 */
+#define HRTIM_TIMRESETTRIGGER_EEV_9 (HRTIM_RSTR_EXTEVNT9) /*!< The timer counter is reset upon external event 9 */
+#define HRTIM_TIMRESETTRIGGER_EEV_10 (HRTIM_RSTR_EXTEVNT10) /*!< The timer counter is reset upon external event 10 */
+#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
+
+#define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x800000001) == 0x00000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_TimerResetUpdate
+ * @{
+ * @brief Constants defining whether the register are updated upon Timerx
+ * counter reset or rollover to 0 after reaching the period value
+ * in continuous mode
+ */
+#define HRTIM_TIMUPDATEONRESET_DISABLED (uint32_t)0x00000000 /*!< Update by timer x reset / rollover disabled */
+#define HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU) /*!< Update by timer x reset / rollover enabled */
+
+#define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET) \
+ (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \
+ ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_CompareUnitAutoDelayedMode
+ * @{
+ * @brief Constants defining whether the compare register is behaving in
+ * regular mode (compare match issued as soon as counter equal compare),
+ * or in auto-delayed mode
+ */
+#define HRTIM_AUTODELAYEDMODE_REGULAR ((uint32_t)0x00000000) /*!< standard compare mode */
+#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated only if a capture has occured */
+#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1) /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */
+#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */
+
+#define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\
+ (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
+ ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
+ ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
+ ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))
+
+/* Auto delayed mode is only available for compare units 2 and 4 */
+#define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE) \
+ ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) && \
+ ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)) \
+ || \
+ (((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \
+ (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
+ ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
+ ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
+ ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \
+ || \
+ (((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) && \
+ ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)) \
+ || \
+ (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \
+ (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
+ ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
+ ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
+ ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_BasicOCMode
+ * @{
+ * @brief Constants defining the behavior of the output signal when the timer
+ operates in basic output compare mode
+ */
+#define HRTIM_BASICOCMODE_TOGGLE ((uint32_t)0x00000001) /*!< Output toggles when the timer counter reaches the compare value */
+#define HRTIM_BASICOCMODE_INACTIVE ((uint32_t)0x00000002) /*!< Output forced to active level when the timer counter reaches the compare value */
+#define HRTIM_BASICOCMODE_ACTIVE ((uint32_t)0x00000003) /*!< Output forced to inactive level when the timer counter reaches the compare value */
+
+#define IS_HRTIM_BASICOCMODE(BASICOCMODE)\
+ (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) || \
+ ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \
+ ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_OutputPolarity
+ * @{
+ * @brief Constants defining the polarity of a timer output
+ */
+#define HRTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000) /*!< Output is active HIGH */
+#define HRTIM_OUTPUTPOLARITY_LOW (HRTIM_OUTR_POL1) /*!< Output is active LOW */
+
+#define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\
+ (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \
+ ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_OutputSetSource
+ * @{
+ * @brief Constants defining the events that can be selected to configure the
+ * set crossbar of a timer output
+ */
+#define HRTIM_OUTPUTSET_NONE (uint32_t)0x00000000 /*!< Reset the output set crossbar */
+#define HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces the output to its active state */
+#define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces the output to its active state */
+#define HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces the output to its active state */
+
+#define IS_HRTIM_OUTPUTSET(OUTPUTSET)\
+ (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_OutputResetSource
+ * @{
+ * @brief Constants defining the events that can be selected to configure the
+ * set crossbar of a timer output
+ */
+#define HRTIM_OUTPUTRESET_NONE (uint32_t)0x00000000 /*!< Reset the output reset crossbar */
+#define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /*!< Timer period event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /*!< Timer compare 1 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /*!< Timer compare 2 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /*!< Timer compare 3 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /*!< Timer compare 4 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /*!< The master timer period event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /*!< External event 4 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /*!< External event 5 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /*!< External event 6 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /*!< External event 7 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /*!< External event 8 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /*!< External event 9 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /*!< External event 10 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /*!< Timer register update event forces the output to its inactive state */
+
+#define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\
+ (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_OutputIdleMode
+ * @{
+ * @brief Constants defining whether or not the timer output transition to its
+ IDLE state when burst mode is entered
+ */
+#define HRTIM_OUTPUTIDLEMODE_NONE (uint32_t)0x00000000 /*!< The output is not affected by the burst mode operation */
+#define HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */
+
+#define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\
+ (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \
+ ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE))
+ /**
+ * @}
+ */
+
+/** @defgroup HRTIM_OutputIDLEState
+ * @{
+ * @brief Constants defining the IDLE state of a timer output
+ */
+#define HRTIM_OUTPUTIDLESTATE_INACTIVE (uint32_t)0x00000000 /*!< Output at inactive level when in IDLE state */
+#define HRTIM_OUTPUTIDLESTATE_ACTIVE (HRTIM_OUTR_IDLES1) /*!< Output at active level when in IDLE state */
+
+#define IS_HRTIM_OUTPUTIDLESTATE(OUTPUTIDLESTATE)\
+ (((OUTPUTIDLESTATE) == HRTIM_OUTPUTIDLESTATE_INACTIVE) || \
+ ((OUTPUTIDLESTATE) == HRTIM_OUTPUTIDLESTATE_ACTIVE))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_OutputFAULTState
+ * @{
+ * @brief Constants defining the FAULT state of a timer output
+ */
+#define HRTIM_OUTPUTFAULTSTATE_NONE (uint32_t)0x00000000 /*!< The output is not affected by the fault input */
+#define HRTIM_OUTPUTFAULTSTATE_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */
+#define HRTIM_OUTPUTFAULTSTATE_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */
+#define HRTIM_OUTPUTFAULTSTATE_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) /*!< Output is tri-stated when in FAULT state */
+
+#define IS_HRTIM_OUTPUTFAULTSTATE(OUTPUTFAULTSTATE)\
+ (((OUTPUTFAULTSTATE) == HRTIM_OUTPUTFAULTSTATE_NONE) || \
+ ((OUTPUTFAULTSTATE) == HRTIM_OUTPUTFAULTSTATE_ACTIVE) || \
+ ((OUTPUTFAULTSTATE) == HRTIM_OUTPUTFAULTSTATE_INACTIVE) || \
+ ((OUTPUTFAULTSTATE) == HRTIM_OUTPUTFAULTSTATE_HIGHZ))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_OutputChopperModeEnable
+ * @{
+ * @brief Constants defining whether or not chopper mode is enabled for a timer
+ output
+ */
+#define HRTIM_OUTPUTCHOPPERMODE_DISABLED (uint32_t)0x00000000 /*!< The output is not affected by the fault input */
+#define HRTIM_OUTPUTCHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /*!< Output at active level when in FAULT state */
+
+#define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\
+ (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) || \
+ ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_OutputBurstModeEntryDelayed
+ * @{
+ * @brief Constants defining the idle mode entry is delayed by forcing a
+ deadtime insertion before switching the outputs to their idle state
+ */
+#define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR (uint32_t)0x00000000 /*!< The programmed Idle state is applied immediately to the Output */
+#define HRTIM_OUTPUTBURSTMODEENTRY_DELAYED (HRTIM_OUTR_DIDL1) /*!< Deadtime is inserted on output before entering the idle mode */
+
+#define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\
+ (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) || \
+ ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_CaptureUnitTrigger
+ * @{
+ * @brief Constants defining the events that can be selected to trigger the
+ * capture of the timing unit counter
+ */
+#define HRTIM_CAPTURETRIGGER_NONE (uint32_t)0x00000000 /*!< Capture trigger is disabled */
+#define HRTIM_CAPTURETRIGGER_UPDATE (HRTIM_CPT1CR_UPDCPT) /*!< The update event triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_1 (HRTIM_CPT1CR_EXEV1CPT) /*!< The External event 1 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_2 (HRTIM_CPT1CR_EXEV2CPT) /*!< The External event 2 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_3 (HRTIM_CPT1CR_EXEV3CPT) /*!< The External event 3 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_4 (HRTIM_CPT1CR_EXEV4CPT) /*!< The External event 4 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_5 (HRTIM_CPT1CR_EXEV5CPT) /*!< The External event 5 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_6 (HRTIM_CPT1CR_EXEV6CPT) /*!< The External event 6 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_7 (HRTIM_CPT1CR_EXEV7CPT) /*!< The External event 7 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_8 (HRTIM_CPT1CR_EXEV8CPT) /*!< The External event 8 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_9 (HRTIM_CPT1CR_EXEV9CPT) /*!< The External event 9 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_10 (HRTIM_CPT1CR_EXEV10CPT) /*!< The External event 10 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_TA1_SET (HRTIM_CPT1CR_TA1SET) /*!< Capture is triggered by TA1 output inactive to active transition */
+#define HRTIM_CAPTURETRIGGER_TA1_RESET (HRTIM_CPT1CR_TA1RST) /*!< Capture is triggered by TA1 output active to inactive transition */
+#define HRTIM_CAPTURETRIGGER_TIMERA_CMP1 (HRTIM_CPT1CR_TA1CMP1) /*!< Timer A Compare 1 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TIMERA_CMP2 (HRTIM_CPT1CR_TA1CMP2) /*!< Timer A Compare 2 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TB1_SET (HRTIM_CPT1CR_TB1SET) /*!< Capture is triggered by TB1 output inactive to active transition */
+#define HRTIM_CAPTURETRIGGER_TB1_RESET (HRTIM_CPT1CR_TB1RST) /*!< Capture is triggered by TB1 output active to inactive transition */
+#define HRTIM_CAPTURETRIGGER_TIMERB_CMP1 (HRTIM_CPT1CR_TB1CMP1) /*!< Timer B Compare 1 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TIMERB_CMP2 (HRTIM_CPT1CR_TB1CMP2) /*!< Timer B Compare 2 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TC1_SET (HRTIM_CPT1CR_TC1SET) /*!< Capture is triggered by TC1 output inactive to active transition */
+#define HRTIM_CAPTURETRIGGER_TC1_RESET (HRTIM_CPT1CR_TC1RST) /*!< Capture is triggered by TC1 output active to inactive transition */
+#define HRTIM_CAPTURETRIGGER_TIMERC_CMP1 (HRTIM_CPT1CR_TC1CMP1) /*!< Timer C Compare 1 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TIMERC_CMP2 (HRTIM_CPT1CR_TC1CMP2) /*!< Timer C Compare 2 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TD1_SET (HRTIM_CPT1CR_TD1SET) /*!< Capture is triggered by TD1 output inactive to active transition */
+#define HRTIM_CAPTURETRIGGER_TD1_RESET (HRTIM_CPT1CR_TD1RST) /*!< Capture is triggered by TD1 output active to inactive transition */
+#define HRTIM_CAPTURETRIGGER_TIMERD_CMP1 (HRTIM_CPT1CR_TD1CMP1) /*!< Timer D Compare 1 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TIMERD_CMP2 (HRTIM_CPT1CR_TD1CMP2) /*!< Timer D Compare 2 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TE1_SET (HRTIM_CPT1CR_TE1SET) /*!< Capture is triggered by TE1 output inactive to active transition */
+#define HRTIM_CAPTURETRIGGER_TE1_RESET (HRTIM_CPT1CR_TE1RST) /*!< Capture is triggered by TE1 output active to inactive transition */
+#define HRTIM_CAPTURETRIGGER_TIMERE_CMP1 (HRTIM_CPT1CR_TE1CMP1) /*!< Timer E Compare 1 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TIMERE_CMP2 (HRTIM_CPT1CR_TE1CMP2) /*!< Timer E Compare 2 triggers Capture */
+
+#define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER) \
+ (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_3) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_4) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_5) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_6) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_7) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_8) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_9) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
+ (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2))) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
+ (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2))) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
+ (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2))) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
+ (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2))) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
+ (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_TimerExternalEventFilter
+ * @{
+ * @brief Constants defining the event filtering applied to external events
+ * by a timer
+ */
+#define HRTIM_TIMEVENTFILTER_NONE (0x00000000)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1 */
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2 */
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3 */
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4 */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2 */
+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3 */
+#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */
+
+#define IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER)\
+ (((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_TimerExternalEventLatch
+ * @{
+ * @brief Constants defining whether or not the external event is
+ * memorized (latched) and generated as soon as the blanking period
+ * is completed or the window ends
+ */
+#define HRTIM_TIMEVENTLATCH_DISABLED ((uint32_t)0x00000000) /*!< Event is ignored if it happens during a blank, or passed through during a window */
+#define HRTIM_TIMEVENTLATCH_ENABLED HRTIM_EEFR1_EE1LTCH /*!< Event 1 is latched and delayed till the end of the blanking or windowing period */ /*!< Blanking from counter reset/roll-over to Compare 1 */
+
+#define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\
+ (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \
+ ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_DeadtimeRisingSign
+ * @{
+ * @brief Constants defining whether the deadtime is positive or negative
+ * (overlapping signal) on rising edge
+ */
+#define HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE ((uint32_t)0x00000000) /*!< Positive deadtime on rising edge */
+#define HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE (HRTIM_DTR_SDTR) /*!< Negative deadtime on rising edge */
+
+#define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\
+ (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) || \
+ ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_DeadtimeRisingLock
+ * @{
+ * @brief Constants defining whether or not the deadtime (rising sign and
+ * value) is write protected
+ */
+#define HRTIM_TIMDEADTIME_RISINGLOCK_WRITE ((uint32_t)0x00000000) /*!< Deadtime rising value and sign is writable */
+#define HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK) /*!< Deadtime rising value and sign is read-only */
+
+#define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\
+ (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) || \
+ ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_DeadtimeRisingSignLock
+ * @{
+ * @brief Constants defining whether or not the deadtime rising sign is write
+ * protected
+ */
+#define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE ((uint32_t)0x00000000) /*!< Deadtime rising sign is writable */
+#define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK) /*!< Deadtime rising sign is read-only */
+
+#define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\
+ (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) || \
+ ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_DeadtimeFallingSign
+ * @{
+ * @brief Constants defining whether the deadtime is positive or negative
+ * (overlapping signal) on falling edge
+ */
+#define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE ((uint32_t)0x00000000) /*!< Positive deadtime on falling edge */
+#define HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE (HRTIM_DTR_SDTF) /*!< Negative deadtime on falling edge */
+
+#define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\
+ (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) || \
+ ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_DeadtimeFallingLock
+ * @{
+ * @brief Constants defining whether or not the deadtime (falling sign and
+ * value) is write protected
+ */
+#define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE ((uint32_t)0x00000000) /*!< Deadtime falling value and sign is writable */
+#define HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK) /*!< Deadtime falling value and sign is read-only */
+
+#define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\
+ (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) || \
+ ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_DeadtimeFallingSignLock
+ * @{
+ * @brief Constants defining whether or not the deadtime falling sign is write
+ * protected
+ */
+#define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE ((uint32_t)0x00000000) /*!< Deadtime falling sign is writable */
+#define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK) /*!< Deadtime falling sign is read-only */
+
+#define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\
+ (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) || \
+ ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_SynchronizationInputSource
+ * @{
+ * @brief Constants defining defining the synchronization input source
+ */
+#define HRTIM_SYNCINPUTSOURCE_NONE (uint32_t)0x00000000 /*!< disabled. HRTIM is not synchronized and runs in standalone mode */
+#define HRTIM_SYNCINPUTSOURCE_INTERNALEVENT HRTIM_MCR_SYNC_IN_1 /*!< The HRTIM is synchronized with the on-chip timer */
+#define HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */
+
+#define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\
+ (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) || \
+ ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) || \
+ ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_SynchronizationOutputSource
+ * @{
+ * @brief Constants defining the source and event to be sent on the
+ * synchronization outputs
+ */
+#define HRTIM_SYNCOUTPUTSOURCE_MASTER_START (uint32_t)0x00000000 /*!< A pulse is sent on the SYNCOUT output (16x fHRTIM clock cycles) upon master timer start event */
+#define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output (16x fHRTIM clock cycles) upon master timer compare 1 event*/
+#define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on the SYNCOUT output (16x fHRTIM clock cycles) upon timer A start or reset events */
+#define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output (16x fHRTIM clock cycles) upon timer A compare 1 event */
+
+#define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\
+ (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) || \
+ ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) || \
+ ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) || \
+ ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_SynchronizationOutputPolarity
+ * @{
+ * @brief Constants defining the routing and conditioning of the synchronization output event
+ */
+#define HRTIM_SYNCOUTPUTPOLARITY_NONE (uint32_t)0x00000000 /*!< Synchronization output event is disabled */
+#define HRTIM_SYNCOUTPUTPOLARITY_POSITIVE (HRTIM_MCR_SYNC_OUT_0) /*!< Positive pulse on SCOUT output (16x fHRTIM clock cycles) */
+#define HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< Positive pulse on SCOUT output (16x fHRTIM clock cycles) */
+
+#define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\
+ (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) || \
+ ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \
+ ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_ExternalEventSources
+ * @{
+ * @brief Constants defining available sources associated to external events
+ */
+#define HRTIM_EVENTSRC_1 ((uint32_t)0x00000000) /*!< External event source 1 */
+#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 */
+#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 */
+#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 */
+
+#define IS_HRTIM_EVENTSRC(EVENTSRC)\
+ (((EVENTSRC) == HRTIM_EVENTSRC_1) || \
+ ((EVENTSRC) == HRTIM_EVENTSRC_2) || \
+ ((EVENTSRC) == HRTIM_EVENTSRC_3) || \
+ ((EVENTSRC) == HRTIM_EVENTSRC_4))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_ExternalEventPolarity
+ * @{
+ * @brief Constants defining the polarity of an external event
+ */
+#define HRTIM_EVENTPOLARITY_HIGH ((uint32_t)0x00000000) /*!< External event is active high */
+#define HRTIM_EVENTPOLARITY_LOW (HRTIM_EECR1_EE1POL) /*!< External event is active low */
+
+#define IS_HRTIM_EVENTPOLARITY(EVENTPOLARITY)\
+ (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) || \
+ ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_ExternalEventSensitivity
+ * @{
+ * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive)
+ * of an external event
+ */
+#define HRTIM_EVENTSENSITIVITY_LEVEL ((uint32_t)0x00000000) /*!< External event is active on level */
+#define HRTIM_EVENTSENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising edge */
+#define HRTIM_EVENTSENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /*!< External event is active on Falling edge */
+#define HRTIM_EVENTSENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising and Falling edges */
+
+#define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\
+ (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) || \
+ ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \
+ ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \
+ ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_ExternalEventFastMode
+ * @{
+ * @brief Constants defining whether or not an external event is programmed in
+ fast mode
+ */
+#define HRTIM_EVENTFASTMODE_DISABLE ((uint32_t)0x00000000) /*!< External Event is acting asynchronously on outputs (low latency mode) */
+#define HRTIM_EVENTFASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
+
+#define IS_HRTIM_EVENTFASTMODE(EVENTFASTMODE)\
+ (((EVENTFASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \
+ ((EVENTFASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))
+
+#define IS_HRTIM_FASTMODE_AVAILABLE(EVENT)\
+ (((EVENT) == HRTIM_EVENT_1) || \
+ ((EVENT) == HRTIM_EVENT_2) || \
+ ((EVENT) == HRTIM_EVENT_3) || \
+ ((EVENT) == HRTIM_EVENT_4) || \
+ ((EVENT) == HRTIM_EVENT_5))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_ExternalEventFilter
+ * @{
+ * @brief Constants defining the frequency used to sample an external event 6
+ * input and the length (N) of the digital filter applied
+ */
+#define HRTIM_EVENTFILTER_NONE ((uint32_t)0x00000000) /*!< Filter disabled */
+#define HRTIM_EVENTFILTER_1 (HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=2 */
+#define HRTIM_EVENTFILTER_2 (HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fHRTIM, N=4 */
+#define HRTIM_EVENTFILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=8 */
+#define HRTIM_EVENTFILTER_4 (HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/2, N=6 */
+#define HRTIM_EVENTFILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/2, N=8 */
+#define HRTIM_EVENTFILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/4, N=6 */
+#define HRTIM_EVENTFILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/4, N=8 */
+#define HRTIM_EVENTFILTER_8 (HRTIM_EECR3_EE6F_3) /*!< fSAMPLING= fEEVS/8, N=6 */
+#define HRTIM_EVENTFILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/8, N=8 */
+#define HRTIM_EVENTFILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/16, N=5 */
+#define HRTIM_EVENTFILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/16, N=6 */
+#define HRTIM_EVENTFILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/16, N=8 */
+#define HRTIM_EVENTFILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32, N=5 */
+#define HRTIM_EVENTFILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/32, N=6 */
+#define HRTIM_EVENTFILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32, N=8 */
+
+#define IS_HRTIM_EVENTFILTER(EVENTFILTER)\
+ (((EVENTFILTER) == HRTIM_EVENTFILTER_NONE) || \
+ ((EVENTFILTER) == HRTIM_EVENTFILTER_1) || \
+ ((EVENTFILTER) == HRTIM_EVENTFILTER_2) || \
+ ((EVENTFILTER) == HRTIM_EVENTFILTER_3) || \
+ ((EVENTFILTER) == HRTIM_EVENTFILTER_4) || \
+ ((EVENTFILTER) == HRTIM_EVENTFILTER_5) || \
+ ((EVENTFILTER) == HRTIM_EVENTFILTER_6) || \
+ ((EVENTFILTER) == HRTIM_EVENTFILTER_7) || \
+ ((EVENTFILTER) == HRTIM_EVENTFILTER_8) || \
+ ((EVENTFILTER) == HRTIM_EVENTFILTER_9) || \
+ ((EVENTFILTER) == HRTIM_EVENTFILTER_10) || \
+ ((EVENTFILTER) == HRTIM_EVENTFILTER_11) || \
+ ((EVENTFILTER) == HRTIM_EVENTFILTER_12) || \
+ ((EVENTFILTER) == HRTIM_EVENTFILTER_13) || \
+ ((EVENTFILTER) == HRTIM_EVENTFILTER_14) || \
+ ((EVENTFILTER) == HRTIM_EVENTFILTER_15))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_ ExternalEventPrescaler
+ * @{
+ * @brief Constants defining division ratio between the timer clock frequency
+ * fHRTIM) and the external event signal sampling clock (fEEVS)
+ * used by the digital filters
+ */
+#define HRTIM_EVENTPRESCALER_DIV1 ((uint32_t)0x00000000) /*!< fEEVS=fHRTIM */
+#define HRTIM_EVENTPRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 2 */
+#define HRTIM_EVENTPRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /*!< fEEVS=fHRTIM / 4 */
+#define HRTIM_EVENTPRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 8 */
+
+#define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\
+ (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) || \
+ ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) || \
+ ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) || \
+ ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_FaultSources
+ * @{
+ * @brief Constants defining whether a faults is be triggered by any external
+ * or internal fault source
+ */
+#define HRTIM_FAULTSOURCE_DIGITALINPUT ((uint32_t)0x00000000) /*!< Fault input is FLT input pin */
+#define HRTIM_FAULTSOURCE_INTERNAL (HRTIM_FLTINR1_FLT1SRC) /*!< Fault input is FLT_Int signal (e.g. internal comparator) */
+
+
+#define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\
+ (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \
+ ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_FaultPolarity
+ * @{
+ * @brief Constants defining the polarity of a fault event
+ */
+#define HRTIM_FAULTPOLARITY_LOW ((uint32_t)0x00000000) /*!< Fault input is active low */
+#define HRTIM_FAULTPOLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /*!< Fault input is active high */
+
+#define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\
+ (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \
+ ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_FaultFilter
+ * @{
+ * @ brief Constants defining the frequency used to sample the fault input and
+ * the length (N) of the digital filter applied
+ */
+#define HRTIM_FAULTFILTER_NONE ((uint32_t)0x00000000) /*!< Filter disabled */
+#define HRTIM_FAULTFILTER_1 (HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=2 */
+#define HRTIM_FAULTFILTER_2 (HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fHRTIM, N=4 */
+#define HRTIM_FAULTFILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=8 */
+#define HRTIM_FAULTFILTER_4 (HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/2, N=6 */
+#define HRTIM_FAULTFILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/2, N=8 */
+#define HRTIM_FAULTFILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/4, N=6 */
+#define HRTIM_FAULTFILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/4, N=8 */
+#define HRTIM_FAULTFILTER_8 (HRTIM_FLTINR1_FLT1F_3) /*!< fSAMPLING= fFLTS/8, N=6 */
+#define HRTIM_FAULTFILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/8, N=8 */
+#define HRTIM_FAULTFILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/16, N=5 */
+#define HRTIM_FAULTFILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/16, N=6 */
+#define HRTIM_FAULTFILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/16, N=8 */
+#define HRTIM_FAULTFILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=5 */
+#define HRTIM_FAULTFILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/32, N=6 */
+#define HRTIM_FAULTFILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=8 */
+
+#define IS_HRTIM_FAULTFILTER(FAULTFILTER)\
+ (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_1) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_2) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_3) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_4) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_5) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_6) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_7) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_8) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_9) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_10) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_11) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_12) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_13) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_14) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_15))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_FaultLock
+ * @{
+ * @brief Constants defining whether or not the fault programming bits are
+ write protected
+ */
+#define HRTIM_FAULTLOCK_READWRITE ((uint32_t)0x00000000) /*!< Fault settings bits are read/write */
+#define HRTIM_FAULTLOCK_READONLY (HRTIM_FLTINR1_FLT1LCK) /*!< Fault settings bits are read only */
+
+#define IS_HRTIM_FAULTLOCK(FAULTLOCK)\
+ (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \
+ ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_ExternalFaultPrescaler
+ * @{
+ * @brief Constants defining the division ratio between the timer clock
+ * frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used
+ * by the digital filters.
+ */
+#define HRTIM_FAULTPRESCALER_DIV1 ((uint32_t)0x00000000) /*!< fFLTS=fHRTIM */
+#define HRTIM_FAULTPRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 2 */
+#define HRTIM_FAULTPRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /*!< fFLTS=fHRTIM / 4 */
+#define HRTIM_FAULTPRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 8 */
+
+#define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\
+ (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) || \
+ ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) || \
+ ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) || \
+ ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_BurstModeOperatingmode
+ * @{
+ * @brief Constants defining if the burst mode is entered once or if it is
+ * continuously operating
+ */
+#define HRTIM_BURSTMODE_SINGLESHOT ((uint32_t)0x00000000) /*!< Burst mode operates in single shot mode */
+#define HRTIM_BURSTMODE_CONTINOUS (HRTIM_BMCR_BMOM) /*!< Burst mode operates in continuous mode */
+
+#define IS_HRTIM_BURSTMODE(BURSTMODE)\
+ (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) || \
+ ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_BurstModeClockSource
+ * @{
+ * @brief Constants defining the clock source for the burst mode counter
+ */
+#define HRTIM_BURSTMODECLOCKSOURCE_MASTER ((uint32_t)0x00000000) /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
+#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_A (HRTIM_BMCR_BMCLK_0) /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */
+#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_B (HRTIM_BMCR_BMCLK_1) /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */
+#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */
+#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_D (HRTIM_BMCR_BMCLK_2) /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */
+#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */
+#define HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_1 (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1) /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */
+#define HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_2 (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */
+#define HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_3 (HRTIM_BMCR_BMCLK_3) /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */
+#define HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_4 (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 4 (BMClk[4]), acting as a burst mode counter clock */
+#define HRTIM_BURSTMODECLOCKSOURCE_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1) /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */
+
+#define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\
+ (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) || \
+ ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) || \
+ ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) || \
+ ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) || \
+ ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) || \
+ ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) || \
+ ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_1) || \
+ ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_2) || \
+ ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_3) || \
+ ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_4) || \
+ ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_BurstModePrescaler
+ * @{
+ * @brief Constants defining the prescaling ratio of the fHRTIM clock
+ * for the burst mode controller
+ */
+#define HRTIM_BURSTMODEPRESCALER_DIV1 ((uint32_t)0x00000000) /*!< fBRST = fHRTIM */
+#define HRTIM_BURSTMODEPRESCALER_DIV2 (HRTIM_BMCR_BMPSC_0) /*!< fBRST = fHRTIM/2 */
+#define HRTIM_BURSTMODEPRESCALER_DIV4 (HRTIM_BMCR_BMPSC_1) /*!< fBRST = fHRTIM/4 */
+#define HRTIM_BURSTMODEPRESCALER_DIV8 (HRTIM_BMCR_BMPSC_1 | HRTIM_BMCR_BMPSC_0) /*!< fBRST = fHRTIM/8 */
+#define HRTIM_BURSTMODEPRESCALER_DIV16 (HRTIM_BMCR_BMPSC_2) /*!< fBRST = fHRTIM/16 */
+#define HRTIM_BURSTMODEPRESCALER_DIV32 (HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_0) /*!< fBRST = fHRTIM/32 */
+#define HRTIM_BURSTMODEPRESCALER_DIV64 (HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_1) /*!< fBRST = fHRTIM/64 */
+#define HRTIM_BURSTMODEPRESCALER_DIV128 (HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_1 | HRTIM_BMCR_BMPSC_0) /*!< fBRST = fHRTIM/128 */
+#define HRTIM_BURSTMODEPRESCALER_DIV256 (HRTIM_BMCR_BMPSC_3) /*!< fBRST = fHRTIM/256 */
+#define HRTIM_BURSTMODEPRESCALER_DIV512 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_0) /*!< fBRST = fHRTIM/512 */
+#define HRTIM_BURSTMODEPRESCALER_DIV1024 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_1) /*!< fBRST = fHRTIM/1024 */
+#define HRTIM_BURSTMODEPRESCALER_DIV2048 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_1 | HRTIM_BMCR_BMPSC_0) /*!< fBRST = fHRTIM/2048*/
+#define HRTIM_BURSTMODEPRESCALER_DIV4096 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_2) /*!< fBRST = fHRTIM/4096 */
+#define HRTIM_BURSTMODEPRESCALER_DIV8192 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_0) /*!< fBRST = fHRTIM/8192 */
+#define HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_1) /*!< fBRST = fHRTIM/16384 */
+#define HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_1 | HRTIM_BMCR_BMPSC_0) /*!< fBRST = fHRTIM/32768 */
+
+#define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\
+ (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_BurstModeRegisterPreloadEnable
+ * @{
+ * @brief Constants defining whether or not burst mode registers preload
+ mechanism is enabled, i.e. a write access into a preloadable register
+ (HRTIM_BMCMPR, HRTIM_BMPER) is done into the active or the preload register
+ */
+#define HRIM_BURSTMODEPRELOAD_DISABLED ((uint32_t)0x00000000) /*!< Preload disabled: the write access is directly done into active registers */
+#define HRIM_BURSTMODEPRELOAD_ENABLED (HRTIM_BMCR_BMPREN) /*!< Preload enabled: the write access is done into preload registers */
+
+#define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\
+ (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) || \
+ ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_BurstModeTrigger
+ * @{
+ * @brief Constants defining the events that can be used tor trig the burst
+ * mode operation
+ */
+#define HRTIM_BURSTMODETRIGGER_SOFTWARE (uint32_t)0x00000000 /*!< Software trigger */
+#define HRTIM_BURSTMODETRIGGER_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /*!< Master reset */
+#define HRTIM_BURSTMODETRIGGER_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /*!< Master repetition */
+#define HRTIM_BURSTMODETRIGGER_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /*!< Master compare 1 */
+#define HRTIM_BURSTMODETRIGGER_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /*!< Master compare 2 */
+#define HRTIM_BURSTMODETRIGGER_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /*!< Master compare 3 */
+#define HRTIM_BURSTMODETRIGGER_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /*!< Master compare 4 */
+#define HRTIM_BURSTMODETRIGGER_TIMERA_RESET (HRTIM_BMTRGR_TARST) /*!< Timer A reset */
+#define HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION (HRTIM_BMTRGR_TAREP) /*!< Timer A repetition */
+#define HRTIM_BURSTMODETRIGGER_TIMERA_CMP1 (HRTIM_BMTRGR_TACMP1) /*!< Timer A compare 1 */
+#define HRTIM_BURSTMODETRIGGER_TIMERA_CMP2 (HRTIM_BMTRGR_TACMP2) /*!< Timer A compare 2 */
+#define HRTIM_BURSTMODETRIGGER_TIMERB_RESET (HRTIM_BMTRGR_TBRST) /*!< Timer B reset */
+#define HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION (HRTIM_BMTRGR_TBREP) /*!< Timer B repetition */
+#define HRTIM_BURSTMODETRIGGER_TIMERB_CMP1 (HRTIM_BMTRGR_TBCMP1) /*!< Timer B compare 1 */
+#define HRTIM_BURSTMODETRIGGER_TIMERB_CMP2 (HRTIM_BMTRGR_TBCMP2) /*!< Timer B compare 2 */
+#define HRTIM_BURSTMODETRIGGER_TIMERC_RESET (HRTIM_BMTRGR_TCRST) /*!< Timer C reset */
+#define HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION (HRTIM_BMTRGR_TCREP) /*!< Timer C repetition */
+#define HRTIM_BURSTMODETRIGGER_TIMERC_CMP1 (HRTIM_BMTRGR_TCCMP1) /*!< Timer C compare 1 */
+#define HRTIM_BURSTMODETRIGGER_TIMERC_CMP2 (HRTIM_BMTRGR_TCCMP2) /*!< Timer C compare 2 */
+#define HRTIM_BURSTMODETRIGGER_TIMERD_RESET (HRTIM_BMTRGR_TDRST) /*!< Timer D reset */
+#define HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION (HRTIM_BMTRGR_TDREP) /*!< Timer D repetition */
+#define HRTIM_BURSTMODETRIGGER_TIMERD_CMP1 (HRTIM_BMTRGR_TDCMP1) /*!< Timer D compare 1 */
+#define HRTIM_BURSTMODETRIGGER_TIMERD_CMP2 (HRTIM_BMTRGR_TDCMP2) /*!< Timer D compare 2 */
+#define HRTIM_BURSTMODETRIGGER_TIMERE_RESET (HRTIM_BMTRGR_TERST) /*!< Timer E reset */
+#define HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION (HRTIM_BMTRGR_TEREP) /*!< Timer E repetition */
+#define HRTIM_BURSTMODETRIGGER_TIMERE_CMP1 (HRTIM_BMTRGR_TECMP1) /*!< Timer E compare 1 */
+#define HRTIM_BURSTMODETRIGGER_TIMERE_CMP2 (HRTIM_BMTRGR_TECMP2) /*!< Timer E compare 2 */
+#define HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /*!< Timer A period following External Event 7 */
+#define HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /*!< Timer D period following External Event 8 */
+#define HRTIM_BURSTMODETRIGGER_EVENT_7 (HRTIM_BMTRGR_EEV7) /*!< External Event 7 */
+#define HRTIM_BURSTMODETRIGGER_EVENT_8 (HRTIM_BMTRGR_EEV8) /*!< External Event 8 */
+#define HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /*!< On-chip Event */
+
+#define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\
+ (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP2) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP1) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_RESET) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_ADCTriggerUpdateSource
+ * @{
+ * @brief constants defining the source triggering the update of the
+ HRTIM_ADCxR register (transfer from preload to active register).
+ */
+#define HRTIM_ADCTRIGGERUPDATE_MASTER (uint32_t)0x00000000 /*!< Master timer */
+#define HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0) /*!< Timer A */
+#define HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1) /*!< Timer B */
+#define HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< Timer C */
+#define HRTIM_ADCTRIGGERUPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2) /*!< Timer D */
+#define HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< Timer E */
+
+#define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\
+ (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) || \
+ ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) || \
+ ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) || \
+ ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) || \
+ ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) || \
+ ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_ADCTriggerEvent
+ * @{
+ * @brief constants defining the events triggering ADC conversion.
+ * HRTIM_ADCTRIGGEREVENT13_*: ADC Triggers 1 and 3
+ * HRTIM_ADCTRIGGEREVENT24_*: ADC Triggers 2 and 4
+ */
+#define HRTIM_ADCTRIGGEREVENT13_NONE (uint32_t)0x00000000 /*!< No ADC trigger event */
+#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1 (HRTIM_ADC1R_AD1MC1) /*!< ADC Trigger on master compare 1 */
+#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2 (HRTIM_ADC1R_AD1MC2) /*!< ADC Trigger on master compare 2 */
+#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3 (HRTIM_ADC1R_AD1MC3) /*!< ADC Trigger on master compare 3 */
+#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4 (HRTIM_ADC1R_AD1MC4) /*!< ADC Trigger on master compare 4 */
+#define HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD (HRTIM_ADC1R_AD1MPER) /*!< ADC Trigger on master period */
+#define HRTIM_ADCTRIGGEREVENT13_EVENT_1 (HRTIM_ADC1R_AD1EEV1) /*!< ADC Trigger on external event 1 */
+#define HRTIM_ADCTRIGGEREVENT13_EVENT_2 (HRTIM_ADC1R_AD1EEV2) /*!< ADC Trigger on external event 2 */
+#define HRTIM_ADCTRIGGEREVENT13_EVENT_3 (HRTIM_ADC1R_AD1EEV3) /*!< ADC Trigger on external event 3 */
+#define HRTIM_ADCTRIGGEREVENT13_EVENT_4 (HRTIM_ADC1R_AD1EEV4) /*!< ADC Trigger on external event 4 */
+#define HRTIM_ADCTRIGGEREVENT13_EVENT_5 (HRTIM_ADC1R_AD1EEV5) /*!< ADC Trigger on external event 5 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP2 (HRTIM_ADC1R_AD1TAC2) /*!< ADC Trigger on Timer A compare 2 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3 (HRTIM_ADC1R_AD1TAC3) /*!< ADC Trigger on Timer A compare 3 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4 (HRTIM_ADC1R_AD1TAC4) /*!< ADC Trigger on Timer A compare 4 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD (HRTIM_ADC1R_AD1TAPER) /*!< ADC Trigger on Timer A period */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET (HRTIM_ADC1R_AD1TARST) /*!< ADC Trigger on Timer A reset */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP2 (HRTIM_ADC1R_AD1TBC2) /*!< ADC Trigger on Timer B compare 2 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3 (HRTIM_ADC1R_AD1TBC3) /*!< ADC Trigger on Timer B compare 3 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4 (HRTIM_ADC1R_AD1TBC4) /*!< ADC Trigger on Timer B compare 4 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD (HRTIM_ADC1R_AD1TBPER) /*!< ADC Trigger on Timer B period */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET (HRTIM_ADC1R_AD1TBRST) /*!< ADC Trigger on Timer B reset */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP2 (HRTIM_ADC1R_AD1TCC2) /*!< ADC Trigger on Timer C compare 2 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3 (HRTIM_ADC1R_AD1TCC3) /*!< ADC Trigger on Timer C compare 3 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4 (HRTIM_ADC1R_AD1TCC4) /*!< ADC Trigger on Timer C compare 4 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD (HRTIM_ADC1R_AD1TCPER) /*!< ADC Trigger on Timer C period */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP2 (HRTIM_ADC1R_AD1TDC2) /*!< ADC Trigger on Timer D compare 2 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3 (HRTIM_ADC1R_AD1TDC3) /*!< ADC Trigger on Timer D compare 3 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4 (HRTIM_ADC1R_AD1TDC4) /*!< ADC Trigger on Timer D compare 4 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD (HRTIM_ADC1R_AD1TDPER) /*!< ADC Trigger on Timer D period */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP2 (HRTIM_ADC1R_AD1TEC2) /*!< ADC Trigger on Timer E compare 2 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3 (HRTIM_ADC1R_AD1TEC3) /*!< ADC Trigger on Timer E compare 3 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4 (HRTIM_ADC1R_AD1TEC4) /*!< ADC Trigger on Timer E compare 4 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD (HRTIM_ADC1R_AD1TEPER) /*!< ADC Trigger on Timer E period */
+
+#define HRTIM_ADCTRIGGEREVENT24_NONE (uint32_t)0x00000000 /*!< No ADC trigger event */
+#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1 (HRTIM_ADC2R_AD2MC1) /*!< ADC Trigger on master compare 1 */
+#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2 (HRTIM_ADC2R_AD2MC2) /*!< ADC Trigger on master compare 2 */
+#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3 (HRTIM_ADC2R_AD2MC3) /*!< ADC Trigger on master compare 3 */
+#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4 (HRTIM_ADC2R_AD2MC4) /*!< ADC Trigger on master compare 4 */
+#define HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD (HRTIM_ADC2R_AD2MPER) /*!< ADC Trigger on master period */
+#define HRTIM_ADCTRIGGEREVENT24_EVENT_6 (HRTIM_ADC2R_AD2EEV6) /*!< ADC Trigger on external event 6 */
+#define HRTIM_ADCTRIGGEREVENT24_EVENT_7 (HRTIM_ADC2R_AD2EEV7) /*!< ADC Trigger on external event 7 */
+#define HRTIM_ADCTRIGGEREVENT24_EVENT_8 (HRTIM_ADC2R_AD2EEV8) /*!< ADC Trigger on external event 8 */
+#define HRTIM_ADCTRIGGEREVENT24_EVENT_9 (HRTIM_ADC2R_AD2EEV9) /*!< ADC Trigger on external event 9 */
+#define HRTIM_ADCTRIGGEREVENT24_EVENT_10 (HRTIM_ADC2R_AD2EEV10) /*!< ADC Trigger on external event 10 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2 (HRTIM_ADC2R_AD2TAC2) /*!< ADC Trigger on Timer A compare 2 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP3 (HRTIM_ADC2R_AD2TAC3) /*!< ADC Trigger on Timer A compare 3 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4 (HRTIM_ADC2R_AD2TAC4) /*!< ADC Trigger on Timer A compare 4 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD (HRTIM_ADC2R_AD2TAPER) /*!< ADC Trigger on Timer A period */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2 (HRTIM_ADC2R_AD2TBC2) /*!< ADC Trigger on Timer B compare 2 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP3 (HRTIM_ADC2R_AD2TBC3) /*!< ADC Trigger on Timer B compare 3 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4 (HRTIM_ADC2R_AD2TBC4) /*!< ADC Trigger on Timer B compare 4 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD (HRTIM_ADC2R_AD2TBPER) /*!< ADC Trigger on Timer B period */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2 (HRTIM_ADC2R_AD2TCC2) /*!< ADC Trigger on Timer C compare 2 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP3 (HRTIM_ADC2R_AD2TCC3) /*!< ADC Trigger on Timer C compare 3 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4 (HRTIM_ADC2R_AD2TCC4) /*!< ADC Trigger on Timer C compare 4 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD (HRTIM_ADC2R_AD2TCPER) /*!< ADC Trigger on Timer C period */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET (HRTIM_ADC2R_AD2TCRST) /*!< ADC Trigger on Timer C reset */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2 (HRTIM_ADC2R_AD2TDC2) /*!< ADC Trigger on Timer D compare 2 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP3 (HRTIM_ADC2R_AD2TDC3) /*!< ADC Trigger on Timer D compare 3 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4 (HRTIM_ADC2R_AD2TDC4) /*!< ADC Trigger on Timer D compare 4 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD (HRTIM_ADC2R_AD2TDPER) /*!< ADC Trigger on Timer D period */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET (HRTIM_ADC2R_AD2TDRST) /*!< ADC Trigger on Timer D reset */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2 (HRTIM_ADC2R_AD2TEC2) /*!< ADC Trigger on Timer E compare 2 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3 (HRTIM_ADC2R_AD2TEC3) /*!< ADC Trigger on Timer E compare 3 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4 (HRTIM_ADC2R_AD2TEC4) /*!< ADC Trigger on Timer E compare 4 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET (HRTIM_ADC2R_AD2TERST) /*!< ADC Trigger on Timer E reset */
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_DLLCalibrationRate
+ * @{
+ * @brief Constants defining the DLL calibration periods (in micro seconds)
+ */
+
+#define HRTIM_CALIBRATIONRATE_7300 (uint32_t)0x00000000 /*!< 1048576 * tHRTIM (7.3 ms) */
+#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) /*!< 131072 * tHRTIM (910 µs) */
+#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) /*!< 131072 * tHRTIM (910 µs) */
+#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) /*!< 131072 * tHRTIM (910 µs) */
+
+#define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\
+ (((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) || \
+ ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910) || \
+ ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114) || \
+ ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_BurstDMARegistersUpdate
+ * @{
+ * @brief Constants defining the registers that can be written during a burst
+ * DMA operation
+ */
+#define HRTIM_BURSTDMA_NONE (uint32_t)0x00000000 /*!< No register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_CR (HRTIM_BDTUPR_TIMCR) /*!< MCR or TIMxCR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_ICR (HRTIM_BDTUPR_TIMICR) /*!< MICR or TIMxICR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_DIER (HRTIM_BDTUPR_TIMDIER) /*!< MDIER or TIMxDIER register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_CNT (HRTIM_BDTUPR_TIMCNT) /*!< MCNTR or CNTxCR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_PER (HRTIM_BDTUPR_TIMPER) /*!< MPER or PERxR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_REP (HRTIM_BDTUPR_TIMREP) /*!< MREPR or REPxR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_CMP1 (HRTIM_BDTUPR_TIMCMP1) /*!< MCMP1R or CMP1xR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_CMP2 (HRTIM_BDTUPR_TIMCMP2) /*!< MCMP2R or CMP2xR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_CMP3 (HRTIM_BDTUPR_TIMCMP3) /*!< MCMP3R or CMP3xR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_CMP4 (HRTIM_BDTUPR_TIMCMP4) /*!< MCMP4R or CMP4xR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_DTR (HRTIM_BDTUPR_TIMDTR) /*!< TDxR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R) /*!< SET1R register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R) /*!< RST1R register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R) /*!< SET2R register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R) /*!< RST1R register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1) /*!< EEFxR1 register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2) /*!< EEFxR2 register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_RSTR (HRTIM_BDTUPR_TIMRSTR) /*!< RSTxR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_CHPR (HRTIM_BDTUPR_TIMCHPR) /*!< CHPxR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_OUTR (HRTIM_BDTUPR_TIMOUTR) /*!< OUTxR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_FLTR (HRTIM_BDTUPR_TIMFLTR) /*!< FLTxR register is updated by Burst DMA accesses */
+
+#define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \
+ ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFFC000) == 0x00000000)) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_BursttModeControl
+ * @{
+ * @brief Constants used to enable or disable the burst mode controller
+ */
+#define HRTIM_BURSTMODECTL_DISABLED (uint32_t)0x00000000 /*!< Burst mode disabled */
+#define HRTIM_BURSTMODECTL_ENABLED (HRTIM_BMCR_BME) /*!< Burst mode enabled */
+
+#define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\
+ (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \
+ ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_FaultModeControl
+ * @{
+ * @brief Constants used to enable or disable the Fault mode
+ */
+#define HRTIM_FAULT_DISABLED (uint32_t)0x00000000 /*!< Fault mode disabled */
+#define HRTIM_FAULT_ENABLED (HRTIM_FLTINR1_FLT1E) /*!< Fault mode enabled */
+
+#define IS_HRTIM_FAULTCTL(FAULTCTL)\
+ (((FAULTCTL) == HRTIM_FAULT_DISABLED) || \
+ ((FAULTCTL) == HRTIM_FAULT_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_SoftwareTimerUpdate
+ * @{
+ * @brief Constants used to force timer registers update
+ */
+#define HRTIM_TIMERUPDATE_MASTER (HRTIM_CR2_MSWU) /*!< Forces an immediate transfer from the preload to the active register in the master timer */
+#define HRTIM_TIMERUPDATE_A (HRTIM_CR2_TASWU) /*!< Forces an immediate transfer from the preload to the active register in the timer A */
+#define HRTIM_TIMERUPDATE_B (HRTIM_CR2_TBSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer B */
+#define HRTIM_TIMERUPDATE_C (HRTIM_CR2_TCSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer C */
+#define HRTIM_TIMERUPDATE_D (HRTIM_CR2_TDSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer D */
+#define HRTIM_TIMERUPDATE_E (HRTIM_CR2_TESWU) /*!< Forces an immediate transfer from the preload to the active register in the timer E */
+
+#define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0) == 0x00000000)
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_SoftwareTimerReset
+ * @{
+ * @brief Constants used to force timer counter reset
+ */
+#define HRTIM_TIMERRESET_MASTER (HRTIM_CR2_MRST) /*!< Resets the master timer counter */
+#define HRTIM_TIMERRESET_A (HRTIM_CR2_TARST) /*!< Resets the timer A counter */
+#define HRTIM_TIMERRESET_B (HRTIM_CR2_TBRST) /*!< Resets the timer B counter */
+#define HRTIM_TIMERRESET_C (HRTIM_CR2_TCRST) /*!< Resets the timer C counter */
+#define HRTIM_TIMERRESET_D (HRTIM_CR2_TDRST) /*!< Resets the timer D counter */
+#define HRTIM_TIMERRESET_E (HRTIM_CR2_TERST) /*!< Resets the timer E counter */
+
+#define IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFFC0FF) == 0x00000000)
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_OutputLevel
+ * @{
+ * @brief Constants defining the level of a timer output
+ */
+#define HRTIM_OUTPUTLEVEL_ACTIVE (uint32_t)0x00000001 /*!< Forces the output to its active state */
+#define HRTIM_OUTPUTLEVEL_INACTIVE (uint32_t)0x00000002 /*!< Forces the output to its inactive state */
+
+#define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\
+ (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) || \
+ ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_OutputState
+ * @{
+ * @brief Constants defining the state of a timer output
+ */
+#define HRTIM_OUTPUTSTATE_IDLE (uint32_t)0x00000001 /*!< Main operating mode, where the output can take the active or
+ inactive level as programmed in the crossbar unit */
+#define HRTIM_OUTPUTSTATE_RUN (uint32_t)0x00000002 /*!< Default operating state (e.g. after an HRTIM reset, when the
+ outputs are disabled by software or during a burst mode operation */
+#define HRTIM_OUTPUTSTATE_FAULT (uint32_t)0x00000003 /*!< Safety state, entered in case of a shut-down request on
+ FAULTx inputs */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_BurstModeStatus
+ * @{
+ * @brief Constants defining the operating state of the burst mode controller
+ */
+#define HRTIM_BURSTMODESTATUS_NORMAL (uint32_t) 0x00000000 /*!< Normal operation */
+#define HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT) /*!< Burst operation on-going */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_CurrentPushPullStatus
+ * @{
+ * @brief Constants defining on which output the signal is currently applied
+ * in push-pull mode
+ */
+#define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1 (uint32_t) 0x00000000 /*!< Signal applied on output 1 and output 2 forced inactive */
+#define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /*!< Signal applied on output 2 and output 1 forced inactive */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_IdlePushPullStatus
+ * @{
+ * @brief Constants defining on which output the signal was applied, in
+ * push-pull mode balanced fault mode or delayed idle mode, when the
+ * protection was triggered
+ */
+#define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1 (uint32_t) 0x00000000 /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
+#define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /*!< Protection occurred when the output 2 was active and output 1 forced inactive */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_CommonInterrupt
+ * @{
+ */
+#define HRTIM_IT_FLT1 HRTIM_ISR_FLT1 /*!< Fault 1 interrupt flag */
+#define HRTIM_IT_FLT2 HRTIM_ISR_FLT2 /*!< Fault 2 interrupt flag */
+#define HRTIM_IT_FLT3 HRTIM_ISR_FLT3 /*!< Fault 3 interrupt flag */
+#define HRTIM_IT_FLT4 HRTIM_ISR_FLT4 /*!< Fault 4 interrupt flag */
+#define HRTIM_IT_FLT5 HRTIM_ISR_FLT5 /*!< Fault 5 interrupt flag */
+#define HRTIM_IT_SYSFLT HRTIM_ISR_SYSFLT /*!< System Fault interrupt flag */
+#define HRTIM_IT_DLLRDY HRTIM_ISR_DLLRDY /*!< DLL ready interrupt flag */
+#define HRTIM_IT_BMPER HRTIM_ISR_BMPER /*!< Burst mode period interrupt flag */
+
+#define IS_HRTIM_IT(IT)\
+ (((IT) == HRTIM_ISR_FLT1) || \
+ ((IT) == HRTIM_ISR_FLT2) || \
+ ((IT) == HRTIM_ISR_FLT3) || \
+ ((IT) == HRTIM_ISR_FLT4) || \
+ ((IT) == HRTIM_ISR_FLT5) || \
+ ((IT) == HRTIM_ISR_SYSFLT) || \
+ ((IT) == HRTIM_ISR_DLLRDY) || \
+ ((IT) == HRTIM_ISR_BMPER))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_MasterInterrupt
+ * @{
+ */
+#define HRTIM_MASTER_IT_MCMP1 HRTIM_MDIER_MCMP1IE /*!< Master compare 1 interrupt flag */
+#define HRTIM_MASTER_IT_MCMP2 HRTIM_MDIER_MCMP2IE /*!< Master compare 2 interrupt flag */
+#define HRTIM_MASTER_IT_MCMP3 HRTIM_MDIER_MCMP3IE /*!< Master compare 3 interrupt flag */
+#define HRTIM_MASTER_IT_MCMP4 HRTIM_MDIER_MCMP4IE /*!< Master compare 4 interrupt flag */
+#define HRTIM_MASTER_IT_MREP HRTIM_MDIER_MREPIE /*!< Master Repetition interrupt flag */
+#define HRTIM_MASTER_IT_SYNC HRTIM_MDIER_SYNCIE /*!< Synchronization input interrupt flag */
+#define HRTIM_MASTER_IT_MUPD HRTIM_MDIER_MUPDIE /*!< Master update interrupt flag */
+
+#define IS_HRTIM_MASTER_IT(IT)\
+ (((IT) == HRTIM_MDIER_MCMP1IE) || \
+ ((IT) == HRTIM_MDIER_MCMP2IE) || \
+ ((IT) == HRTIM_MDIER_MCMP3IE) || \
+ ((IT) == HRTIM_MDIER_MCMP4IE) || \
+ ((IT) == HRTIM_MDIER_MREPIE) || \
+ ((IT) == HRTIM_MDIER_SYNCIE) || \
+ ((IT) == HRTIM_MDIER_MUPDIE))
+
+/** @defgroup HRTIM_MasterFlag
+ * @{
+ */
+#define HRTIM_MASTER_FLAG_MCMP1 HRTIM_MISR_MCMP1 /*!< Master compare 1 interrupt flag */
+#define HRTIM_MASTER_FLAG_MCMP2 HRTIM_MISR_MCMP2 /*!< Master compare 2 interrupt flag */
+#define HRTIM_MASTER_FLAG_MCMP3 HRTIM_MISR_MCMP3 /*!< Master compare 3 interrupt flag */
+#define HRTIM_MASTER_FLAG_MCMP4 HRTIM_MISR_MCMP4 /*!< Master compare 4 interrupt flag */
+#define HRTIM_MASTER_FLAG_MREP HRTIM_MISR_MREP /*!< Master Repetition interrupt flag */
+#define HRTIM_MASTER_FLAG_SYNC HRTIM_MISR_SYNC /*!< Synchronization input interrupt flag */
+#define HRTIM_MASTER_FLAG_MUPD HRTIM_MISR_MUPD /*!< Master update interrupt flag */
+
+#define IS_HRTIM_MASTER_FLAG(FLAG)\
+ (((FLAG) == HRTIM_MISR_MCMP1) || \
+ ((FLAG) == HRTIM_MISR_MCMP2) || \
+ ((FLAG) == HRTIM_MISR_MCMP3) || \
+ ((FLAG) == HRTIM_MISR_MCMP4) || \
+ ((FLAG) == HRTIM_MISR_MREP) || \
+ ((FLAG) == HRTIM_MISR_SYNC) || \
+ ((FLAG) == HRTIM_MISR_MUPD))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_TimingUnitInterrupt
+ * @{
+ */
+#define HRTIM_TIM_IT_CMP1 HRTIM_TIMDIER_CMP1IE /*!< Timer compare 1 interrupt flag */
+#define HRTIM_TIM_IT_CMP2 HRTIM_TIMDIER_CMP2IE /*!< Timer compare 2 interrupt flag */
+#define HRTIM_TIM_IT_CMP3 HRTIM_TIMDIER_CMP3IE /*!< Timer compare 3 interrupt flag */
+#define HRTIM_TIM_IT_CMP4 HRTIM_TIMDIER_CMP4IE /*!< Timer compare 4 interrupt flag */
+#define HRTIM_TIM_IT_REP HRTIM_TIMDIER_REPIE /*!< Timer repetition interrupt flag */
+#define HRTIM_TIM_IT_UPD HRTIM_TIMDIER_UPDIE /*!< Timer update interrupt flag */
+#define HRTIM_TIM_IT_CPT1 HRTIM_TIMDIER_CPT1IE /*!< Timer capture 1 interrupt flag */
+#define HRTIM_TIM_IT_CPT2 HRTIM_TIMDIER_CPT2IE /*!< Timer capture 2 interrupt flag */
+#define HRTIM_TIM_IT_SET1 HRTIM_TIMDIER_SET1IE /*!< Timer output 1 set interrupt flag */
+#define HRTIM_TIM_IT_RST1 HRTIM_TIMDIER_RST1IE /*!< Timer output 1 reset interrupt flag */
+#define HRTIM_TIM_IT_SET2 HRTIM_TIMDIER_SET2IE /*!< Timer output 2 set interrupt flag */
+#define HRTIM_TIM_IT_RST2 HRTIM_TIMDIER_RST2IE /*!< Timer output 2 reset interrupt flag */
+#define HRTIM_TIM_IT_RST HRTIM_TIMDIER_RSTIE /*!< Timer reset interrupt flag */
+#define HRTIM_TIM_IT_DLYPRT HRTIM_TIMDIER_DLYPRT1IE /*!< Timer delay protection interrupt flag */
+
+#define IS_HRTIM_TIM_IT(IT)\
+ (((IT) == HRTIM_TIMDIER_CMP1IE) || \
+ ((IT) == HRTIM_TIMDIER_CMP2IE) || \
+ ((IT) == HRTIM_TIMDIER_CMP3IE) || \
+ ((IT) == HRTIM_TIMDIER_CMP4IE) || \
+ ((IT) == HRTIM_TIMDIER_REPIE) || \
+ ((IT) == HRTIM_TIMDIER_UPDIE) || \
+ ((IT) == HRTIM_TIMDIER_CPT1IE) || \
+ ((IT) == HRTIM_TIMDIER_CPT2IE) || \
+ ((IT) == HRTIM_TIMDIER_SET1IE) || \
+ ((IT) == HRTIM_TIMDIER_RST1IE) || \
+ ((IT) == HRTIM_TIMDIER_SET2IE) || \
+ ((IT) == HRTIM_TIMDIER_RST2IE) || \
+ ((IT) == HRTIM_TIMDIER_RSTIE) || \
+ ((IT) == HRTIM_TIMDIER_DLYPRTIE))
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_TimingUnitFlag
+ * @{
+ */
+#define HRTIM_TIM_FLAG_CMP1 HRTIM_TIMISR_CMP1 /*!< Timer compare 1 interrupt flag */
+#define HRTIM_TIM_FLAG_CMP2 HRTIM_TIMISR_CMP2 /*!< Timer compare 2 interrupt flag */
+#define HRTIM_TIM_FLAG_CMP3 HRTIM_TIMISR_CMP3 /*!< Timer compare 3 interrupt flag */
+#define HRTIM_TIM_FLAG_CMP4 HRTIM_TIMISR_CMP4 /*!< Timer compare 4 interrupt flag */
+#define HRTIM_TIM_FLAG_REP HRTIM_TIMISR_REP /*!< Timer repetition interrupt flag */
+#define HRTIM_TIM_FLAG_UPD HRTIM_TIMISR_UPD /*!< Timer update interrupt flag */
+#define HRTIM_TIM_FLAG_CPT1 HRTIM_TIMISR_CPT1 /*!< Timer capture 1 interrupt flag */
+#define HRTIM_TIM_FLAG_CPT2 HRTIM_TIMISR_CPT2 /*!< Timer capture 2 interrupt flag */
+#define HRTIM_TIM_FLAG_SET1 HRTIM_TIMISR_SET1 /*!< Timer output 1 set interrupt flag */
+#define HRTIM_TIM_FLAG_RST1 HRTIM_TIMISR_RST1 /*!< Timer output 1 reset interrupt flag */
+#define HRTIM_TIM_FLAG_SET2 HRTIM_TIMISR_SET2 /*!< Timer output 2 set interrupt flag */
+#define HRTIM_TIM_FLAG_RST2 HRTIM_TIMISR_RST2 /*!< Timer output 2 reset interrupt flag */
+#define HRTIM_TIM_FLAG_RST HRTIM_TIMDIER_RSTIE /*!< Timer reset interrupt flag */
+#define HRTIM_TIM_FLAG_DLYPRT1 HRTIM_TIMISR_DLYPRT /*!< Timer delay protection interrupt flag */
+
+#define IS_HRTIM_TIM_FLAG(FLAG)\
+ (((FLAG) == HRTIM_TIM_FLAG_CMP1) || \
+ ((FLAG) == HRTIM_TIM_FLAG_CMP2) || \
+ ((FLAG) == HRTIM_TIM_FLAG_CMP3) || \
+ ((FLAG) == HRTIM_TIM_FLAG_CMP4) || \
+ ((FLAG) == HRTIM_TIM_FLAG_REP) || \
+ ((FLAG) == HRTIM_TIM_FLAG_UPD) || \
+ ((FLAG) == HRTIM_TIM_FLAG_CPT1) || \
+ ((FLAG) == HRTIM_TIM_FLAG_CPT2) || \
+ ((FLAG) == HRTIM_TIM_FLAG_SET1) || \
+ ((FLAG) == HRTIM_TIM_FLAG_RST1) || \
+ ((FLAG) == HRTIM_TIM_FLAG_SET2) || \
+ ((FLAG) == HRTIM_TIM_FLAG_RST2) || \
+ ((FLAG) == HRTIM_TIM_FLAG_RST) || \
+ ((FLAG) == HRTIM_TIM_FLAG_DLYPRT1))
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_MasterDMARequest
+ * @{
+ */
+#define HRTIM_MASTER_DMA_MCMP1 HRTIM_MDIER_MCMP1DE /*!< Master compare 1 DMA request flag */
+#define HRTIM_MASTER_DMA_MCMP2 HRTIM_MDIER_MCMP2DE /*!< Master compare 2 DMA request flag */
+#define HRTIM_MASTER_DMA_MCMP3 HRTIM_MDIER_MCMP3DE /*!< Master compare 3 DMA request flag */
+#define HRTIM_MASTER_DMA_MCMP4 HRTIM_MDIER_MCMP4DE /*!< Master compare 4 DMA request flag */
+#define HRTIM_MASTER_DMA_MREP HRTIM_MDIER_MREPDE /*!< Master Repetition DMA request flag */
+#define HRTIM_MASTER_DMA_SYNC HRTIM_MDIER_SYNCDE /*!< Synchronization input DMA request flag */
+#define HRTIM_MASTER_DMA_MUPD HRTIM_MDIER_MUPDDE /*!< Master update DMA request flag */
+
+#define IS_HRTIM_MASTER_DMA(DMA)\
+ (((DMA) == HRTIM_MDIER_MCMP1DE) || \
+ ((DMA) == HRTIM_MDIER_MCMP2DE) || \
+ ((DMA) == HRTIM_MDIER_MCMP3DE) || \
+ ((DMA) == HRTIM_MDIER_MCMP4DE) || \
+ ((DMA) == HRTIM_MDIER_MREPDE) || \
+ ((DMA) == HRTIM_MDIER_SYNCDE) || \
+ ((DMA) == HRTIM_MDIER_MUPDDE))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_TimingUnitDMARequest
+ * @{
+ */
+#define HRTIM_TIM_DMA_CMP1 HRTIM_TIMDIER_CMP1DE /*!< Timer compare 1 interrupt flag */
+#define HRTIM_TIM_DMA_CMP2 HRTIM_TIMDIER_CMP2DE /*!< Timer compare 2 interrupt flag */
+#define HRTIM_TIM_DMA_CMP3 HRTIM_TIMDIER_CMP3DE /*!< Timer compare 3 interrupt flag */
+#define HRTIM_TIM_DMA_CMP4 HRTIM_TIMDIER_CMP4DE /*!< Timer compare 4 interrupt flag */
+#define HRTIM_TIM_DMA_REP HRTIM_TIMDIER_REPDE /*!< Timer repetition interrupt flag */
+#define HRTIM_TIM_DMA_UPD HRTIM_TIMDIER_UPDDE /*!< Timer update interrupt flag */
+#define HRTIM_TIM_DMA_CPT1 HRTIM_TIMDIER_CPT1DE /*!< Timer capture 1 interrupt flag */
+#define HRTIM_TIM_DMA_CPT2 HRTIM_TIMDIER_CPT2DE /*!< Timer capture 2 interrupt flag */
+#define HRTIM_TIM_DMA_SET1 HRTIM_TIMDIER_SET1DE /*!< Timer output 1 set interrupt flag */
+#define HRTIM_TIM_DMA_RST1 HRTIM_TIMDIER_RST1DE /*!< Timer output 1 reset interrupt flag */
+#define HRTIM_TIM_DMA_SET2 HRTIM_TIMDIER_SET2DE /*!< Timer output 2 set interrupt flag */
+#define HRTIM_TIM_DMA_RST2 HRTIM_TIMDIER_RST2DE /*!< Timer output 2 reset interrupt flag */
+#define HRTIM_TIM_DMA_RST HRTIM_TIMDIER_RSTDE /*!< Timer reset interrupt flag */
+#define HRTIM_TIM_DMA_DLYPRT HRTIM_TIMDIER_DLYPRTDE /*!< Timer delay protection interrupt flag */
+
+#define IS_HRTIM_TIM_DMA(DMA)\
+ (((DMA) == HRTIM_TIMDIER_CMP1DE) || \
+ ((DMA) == HRTIM_TIMDIER_CMP2DE) || \
+ ((DMA) == HRTIM_TIMDIER_CMP3DE) || \
+ ((DMA) == HRTIM_TIMDIER_CMP4DE) || \
+ ((DMA) == HRTIM_TIMDIER_REPDE) || \
+ ((DMA) == HRTIM_TIMDIER_UPDDE) || \
+ ((DMA) == HRTIM_TIMDIER_CPT1DE) || \
+ ((DMA) == HRTIM_TIMDIER_CPT2DE) || \
+ ((DMA) == HRTIM_TIMDIER_SET1DE) || \
+ ((DMA) == HRTIM_TIMDIER_RST1DE) || \
+ ((DMA) == HRTIM_TIMDIER_SET2DE) || \
+ ((DMA) == HRTIM_TIMDIER_RST2DE) || \
+ ((DMA) == HRTIM_TIMDIER_RSTDE) || \
+ ((DMA) == HRTIM_TIMDIER_DLYPRTDE))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Instancedefinition
+ * @{
+ */
+#define IS_HRTIM_INSTANCE(INSTANCE) (INSTANCE) == HRTIM1)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+
+/** @brief Enables or disables the timer counter(s)
+ * @param __HANDLE__: specifies the HRTIM Handle.
+ * @param __TIMERS__: timersto enable/disable
+ * This parameter can be any combinations of the following values:
+ * @arg HRTIM_TIMERID_MASTER: Master timer identifier
+ * @arg HRTIM_TIMERID_TIMER_A: Timer A identifier
+ * @arg HRTIM_TIMERID_TIMER_B: Timer B identifier
+ * @arg HRTIM_TIMERID_TIMER_C: Timer C identifier
+ * @arg HRTIM_TIMERID_TIMER_D: Timer D identifier
+ * @arg HRTIM_TIMERID_TIMER_E: Timer E identifier
+ * @retval None
+ */
+#define __HRTIM_ENABLE(__HANDLE__, __TIMERS__) ((__HANDLE__)->HRTIM_MASTER.MCR |= (__TIMERS__))
+
+/* The counter of a timing unit is disabled only if all the timer outputs */
+/* are disabled and no capture is configured */
+#define HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN | HRTIM_OENR_TA1OEN)
+#define HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN | HRTIM_OENR_TB1OEN)
+#define HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN | HRTIM_OENR_TC1OEN)
+#define HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN | HRTIM_OENR_TD1OEN)
+#define HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN | HRTIM_OENR_TE1OEN)
+#define __HRTIM_DISABLE(__HANDLE__, __TIMERS__)\
+ do {\
+ if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\
+ {\
+ ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_MASTER);\
+ }\
+ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\
+ {\
+ if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TAOEN_MASK) == RESET)\
+ {\
+ ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_A);\
+ }\
+ }\
+ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\
+ {\
+ if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TBOEN_MASK) == RESET)\
+ {\
+ ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_B);\
+ }\
+ }\
+ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\
+ {\
+ if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TCOEN_MASK) == RESET)\
+ {\
+ ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_C);\
+ }\
+ }\
+ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\
+ {\
+ if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TDOEN_MASK) == RESET)\
+ {\
+ ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_D);\
+ }\
+ }\
+ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\
+ {\
+ if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TEOEN_MASK) == RESET)\
+ {\
+ ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_E);\
+ }\
+ }\
+ } while(0)
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Simple time base related functions *****************************************/
+void HRTIM_SimpleBase_Init(HRTIM_TypeDef* HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
+
+void HRTIM_DeInit(HRTIM_TypeDef* HRTIMx);
+
+void HRTIM_SimpleBaseStart(HRTIM_TypeDef *hrtim, uint32_t TimerIdx);
+void HRTIM_SimpleBaseStop(HRTIM_TypeDef *hrtim, uint32_t TimerIdx);
+
+/* Simple output compare related functions ************************************/
+void HRTIM_SimpleOC_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
+
+void HRTIM_SimpleOCChannelConfig(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel,
+ HRTIM_BasicOCChannelCfgTypeDef* pBasicOCChannelCfg);
+
+void HRTIM_SimpleOCStart(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel);
+void HRTIM_SimpleOCStop(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t OCChannel);
+/* Simple PWM output related functions ****************************************/
+void HRTIM_SimplePWM_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
+
+void HRTIM_SimplePWMChannelConfig(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel,
+ HRTIM_BasicPWMChannelCfgTypeDef* pBasicPWMChannelCfg);
+
+void HRTIM_SimplePWMStart(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel);
+void HRTIM_SimplePWMStop(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel);
+/* Simple capture related functions *******************************************/
+void HRTIM_SimpleCapture_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
+
+void HRTIM_SimpleCaptureChannelConfig(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel,
+ HRTIM_BasicCaptureChannelCfgTypeDef* pBasicCaptureChannelCfg);
+
+void HRTIM_SimpleCaptureStart(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel);
+void HRTIM_SimpleCaptureStop(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel);
+/* SImple one pulse related functions *****************************************/
+void HRTIM_SimpleOnePulse_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
+
+void HRTIM_SimpleOnePulseChannelConfig(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ uint32_t OnePulseChannel,
+ HRTIM_BasicOnePulseChannelCfgTypeDef* pBasicOnePulseChannelCfg);
+
+void HRTIM_SimpleOnePulseStart(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t OnePulseChannel);
+void HRTIM_SimpleOnePulseStop(HRTIM_TypeDef * HRTIM_,
+ uint32_t TimerIdx,
+ uint32_t OnePulseChannel);
+/* Waveform related functions *************************************************/
+void HRTIM_Waveform_Init(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct,
+ HRTIM_TimerInitTypeDef* HRTIM_TimerInitStruct);
+
+void HRTIM_WaveformTimerConfig(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ HRTIM_TimerCfgTypeDef * HRTIM_TimerCfgStruct);
+
+void HRTIM_WaveformCompareConfig(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ uint32_t CompareUnit,
+ HRTIM_CompareCfgTypeDef* pCompareCfg);
+
+void HRTIM_MasterSetCompare(HRTIM_TypeDef * HRTIMx,
+ uint32_t CompareUnit,
+ uint32_t Compare);
+void HRTIM_WaveformCaptureConfig(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureUnit,
+ HRTIM_CaptureCfgTypeDef* pCaptureCfg);
+
+void HRTIM_WaveformOuputConfig(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ uint32_t Output,
+ HRTIM_OutputCfgTypeDef * pOutputCfg);
+
+void HRTIM_TimerEventFilteringConfig(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ uint32_t Event,
+ HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg);
+
+void HRTIM_DeadTimeConfig(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg);
+
+void HRTIM_ChopperModeConfig(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg);
+
+void HRTIM_BurstDMAConfig(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ uint32_t RegistersToUpdate);
+
+void HRTIM_SynchronizationConfig(HRTIM_TypeDef *HRTIMx,
+ HRTIM_SynchroCfgTypeDef * pSynchroCfg);
+
+void HRTIM_BurstModeConfig(HRTIM_TypeDef *hrtim,
+ HRTIM_BurstModeCfgTypeDef* pBurstModeCfg);
+
+void HRTIM_EventConfig(HRTIM_TypeDef *hrtim,
+ uint32_t Event,
+ HRTIM_EventCfgTypeDef* pEventCfg);
+
+void HRTIM_EventPrescalerConfig(HRTIM_TypeDef *hrtim,
+ uint32_t Prescaler);
+
+void HRTIM_FaultConfig(HRTIM_TypeDef *hrtim,
+ HRTIM_FaultCfgTypeDef* pFaultCfg,
+ uint32_t Fault);
+
+void HRTIM_FaultPrescalerConfig(HRTIM_TypeDef *hrtim,
+ uint32_t Prescaler);
+void HRTIM_FaultModeCtl(HRTIM_TypeDef * HRTIMx, uint32_t Fault, uint32_t Enable);
+
+void HRTIM_ADCTriggerConfig(HRTIM_TypeDef *hrtim,
+ uint32_t ADCTrigger,
+ HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg);
+
+void HRTIM_WaveformCounterStart(HRTIM_TypeDef *hrtim,
+ uint32_t TimersToStart);
+
+void HRTIM_WaveformCounterStop(HRTIM_TypeDef *hrtim,
+ uint32_t TimersToStop);
+
+void HRTIM_WaveformOutputStart(HRTIM_TypeDef *hrtim,
+ uint32_t OuputsToStart);
+void HRTIM_WaveformOutputStop(HRTIM_TypeDef * HRTIM_,
+ uint32_t OuputsToStop);
+
+void HRTIM_DLLCalibrationStart(HRTIM_TypeDef *hrtim,
+ uint32_t CalibrationRate);
+
+/* Interrupt/flags and DMA management */
+void HRTIM_ITConfig(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_TIM_IT, FunctionalState NewState);
+void HRTIM_ITCommonConfig(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT, FunctionalState NewState);
+
+void HRTIM_ClearFlag(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG);
+void HRTIM_ClearCommonFlag(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonFLAG);
+
+void HRTIM_ClearITPendingBit(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT);
+void HRTIM_ClearCommonITPendingBit(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT);
+
+FlagStatus HRTIM_GetFlagStatus(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG);
+FlagStatus HRTIM_GetCommonFlagStatus(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonFLAG);
+
+ITStatus HRTIM_GetITStatus(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT);
+ITStatus HRTIM_GetCommonITStatus(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT);
+
+
+void HRTIM_DMACmd(HRTIM_TypeDef* HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_DMA, FunctionalState NewState);
+
+void HRTIM_BurstModeCtl(HRTIM_TypeDef *hrtim,
+ uint32_t Enable);
+
+void HRTIM_SoftwareCapture(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureUnit);
+
+void HRTIM_SoftwareUpdate(HRTIM_TypeDef *hrtim,
+ uint32_t TimersToUpdate);
+
+void HRTIM_SoftwareReset(HRTIM_TypeDef *hrtim,
+ uint32_t TimersToReset);
+
+
+uint32_t HRTIM_GetCapturedValue(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureUnit);
+
+void HRTIM_WaveformOutputConfig(HRTIM_TypeDef * HRTIM_,
+ uint32_t TimerIdx,
+ uint32_t Output,
+ HRTIM_OutputCfgTypeDef * pOutputCfg);
+
+void HRTIM_WaveformSetOutputLevel(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ uint32_t Output,
+ uint32_t OutputLevel);
+
+uint32_t HRTIM_WaveformGetOutputLevel(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ uint32_t Output);
+
+uint32_t HRTIM_WaveformGetOutputState(HRTIM_TypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Output);
+
+uint32_t HRTIM_GetDelayedProtectionStatus(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ uint32_t Output);
+
+uint32_t HRTIM_GetBurstStatus(HRTIM_TypeDef *hrtim);
+
+uint32_t HRTIM_GetCurrentPushPullStatus(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx);
+
+uint32_t HRTIM_GetIdlePushPullStatus(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F30x_HRTIM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_i2c.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,1595 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_i2c.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Inter-Integrated circuit (I2C):
+ * + Initialization and Configuration
+ * + Communications handling
+ * + SMBUS management
+ * + I2C registers management
+ * + Data transfers management
+ * + DMA transfers management
+ * + Interrupts and flags management
+ *
+ * @verbatim
+ ============================================================================
+ ##### How to use this driver #####
+ ============================================================================
+ [..]
+ (#) Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE)
+ function for I2C1 or I2C2.
+ (#) Enable SDA, SCL and SMBA (when used) GPIO clocks using
+ RCC_AHBPeriphClockCmd() function.
+ (#) Peripherals alternate function:
+ (++) Connect the pin to the desired peripherals' Alternate
+ Function (AF) using GPIO_PinAFConfig() function.
+ (++) Configure the desired pin in alternate function by:
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+ (++) Select the type, OpenDrain and speed via
+ GPIO_PuPd, GPIO_OType and GPIO_Speed members
+ (++) Call GPIO_Init() function.
+ (#) Program the Mode, Timing , Own address, Ack and Acknowledged Address
+ using the I2C_Init() function.
+ (#) Optionally you can enable/configure the following parameters without
+ re-initialization (i.e there is no need to call again I2C_Init() function):
+ (++) Enable the acknowledge feature using I2C_AcknowledgeConfig() function.
+ (++) Enable the dual addressing mode using I2C_DualAddressCmd() function.
+ (++) Enable the general call using the I2C_GeneralCallCmd() function.
+ (++) Enable the clock stretching using I2C_StretchClockCmd() function.
+ (++) Enable the PEC Calculation using I2C_CalculatePEC() function.
+ (++) For SMBus Mode:
+ (+++) Enable the SMBusAlert pin using I2C_SMBusAlertCmd() function.
+ (#) Enable the NVIC and the corresponding interrupt using the function
+ I2C_ITConfig() if you need to use interrupt mode.
+ (#) When using the DMA mode
+ (++) Configure the DMA using DMA_Init() function.
+ (++) Active the needed channel Request using I2C_DMACmd() function.
+ (#) Enable the I2C using the I2C_Cmd() function.
+ (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the
+ transfers.
+ [..]
+ (@) When using I2C in Fast Mode Plus, SCL and SDA pin 20mA current drive capability
+ must be enabled by setting the driving capability control bit in SYSCFG.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_i2c.h"
+#include "stm32f30x_rcc.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup I2C
+ * @brief I2C driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+#define CR1_CLEAR_MASK ((uint32_t)0x00CFE0FF) /*<! I2C CR1 clear register Mask */
+#define CR2_CLEAR_MASK ((uint32_t)0x07FF7FFF) /*<! I2C CR2 clear register Mask */
+#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*<! I2C TIMING clear register Mask */
+#define ERROR_IT_MASK ((uint32_t)0x00003F00) /*<! I2C Error interrupt register Mask */
+#define TC_IT_MASK ((uint32_t)0x000000C0) /*<! I2C TC interrupt register Mask */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup I2C_Private_Functions
+ * @{
+ */
+
+
+/** @defgroup I2C_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..] This section provides a set of functions allowing to initialize the I2C Mode,
+ I2C Timing, I2C filters, I2C Addressing mode, I2C OwnAddress1.
+
+ [..] The I2C_Init() function follows the I2C configuration procedures (these procedures
+ are available in reference manual).
+
+ [..] When the Software Reset is performed using I2C_SoftwareResetCmd() function, the internal
+ states machines are reset and communication control bits, as well as status bits come
+ back to their reset value.
+
+ [..] Before enabling Stop mode using I2C_StopModeCmd() I2C Clock source must be set to
+ HSI and Digital filters must be disabled.
+
+ [..] Before enabling Own Address 2 via I2C_DualAddressCmd() function, OA2 and mask should be
+ configured using I2C_OwnAddress2Config() function.
+
+ [..] I2C_SlaveByteControlCmd() enable Slave byte control that allow user to get control of
+ each byte in slave mode when NBYTES is set to 0x01.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the I2Cx peripheral registers to their default reset values.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @retval None
+ */
+void I2C_DeInit(I2C_TypeDef* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+ if (I2Cx == I2C1)
+ {
+ /* Enable I2C1 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
+ /* Release I2C1 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
+ }
+ else
+ {
+ /* Enable I2C2 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
+ /* Release I2C2 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
+ }
+}
+
+/**
+ * @brief Initializes the I2Cx peripheral according to the specified
+ * parameters in the I2C_InitStruct.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
+ * contains the configuration information for the specified I2C peripheral.
+ * @retval None
+ */
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_ANALOG_FILTER(I2C_InitStruct->I2C_AnalogFilter));
+ assert_param(IS_I2C_DIGITAL_FILTER(I2C_InitStruct->I2C_DigitalFilter));
+ assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
+ assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
+ assert_param(IS_I2C_ACK(I2C_InitStruct->I2C_Ack));
+ assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
+
+ /* Disable I2Cx Peripheral */
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
+
+ /*---------------------------- I2Cx FILTERS Configuration ------------------*/
+ /* Get the I2Cx CR1 value */
+ tmpreg = I2Cx->CR1;
+ /* Clear I2Cx CR1 register */
+ tmpreg &= CR1_CLEAR_MASK;
+ /* Configure I2Cx: analog and digital filter */
+ /* Set ANFOFF bit according to I2C_AnalogFilter value */
+ /* Set DFN bits according to I2C_DigitalFilter value */
+ tmpreg |= (uint32_t)I2C_InitStruct->I2C_AnalogFilter |(I2C_InitStruct->I2C_DigitalFilter << 8);
+
+ /* Write to I2Cx CR1 */
+ I2Cx->CR1 = tmpreg;
+
+ /*---------------------------- I2Cx TIMING Configuration -------------------*/
+ /* Configure I2Cx: Timing */
+ /* Set TIMINGR bits according to I2C_Timing */
+ /* Write to I2Cx TIMING */
+ I2Cx->TIMINGR = I2C_InitStruct->I2C_Timing & TIMING_CLEAR_MASK;
+
+ /* Enable I2Cx Peripheral */
+ I2Cx->CR1 |= I2C_CR1_PE;
+
+ /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
+ /* Clear tmpreg local variable */
+ tmpreg = 0;
+ /* Clear OAR1 register */
+ I2Cx->OAR1 = (uint32_t)tmpreg;
+ /* Clear OAR2 register */
+ I2Cx->OAR2 = (uint32_t)tmpreg;
+ /* Configure I2Cx: Own Address1 and acknowledged address */
+ /* Set OA1MODE bit according to I2C_AcknowledgedAddress value */
+ /* Set OA1 bits according to I2C_OwnAddress1 value */
+ tmpreg = (uint32_t)((uint32_t)I2C_InitStruct->I2C_AcknowledgedAddress | \
+ (uint32_t)I2C_InitStruct->I2C_OwnAddress1);
+ /* Write to I2Cx OAR1 */
+ I2Cx->OAR1 = tmpreg;
+ /* Enable Own Address1 acknowledgement */
+ I2Cx->OAR1 |= I2C_OAR1_OA1EN;
+
+ /*---------------------------- I2Cx MODE Configuration ---------------------*/
+ /* Configure I2Cx: mode */
+ /* Set SMBDEN and SMBHEN bits according to I2C_Mode value */
+ tmpreg = I2C_InitStruct->I2C_Mode;
+ /* Write to I2Cx CR1 */
+ I2Cx->CR1 |= tmpreg;
+
+ /*---------------------------- I2Cx ACK Configuration ----------------------*/
+ /* Get the I2Cx CR2 value */
+ tmpreg = I2Cx->CR2;
+ /* Clear I2Cx CR2 register */
+ tmpreg &= CR2_CLEAR_MASK;
+ /* Configure I2Cx: acknowledgement */
+ /* Set NACK bit according to I2C_Ack value */
+ tmpreg |= I2C_InitStruct->I2C_Ack;
+ /* Write to I2Cx CR2 */
+ I2Cx->CR2 = tmpreg;
+}
+
+/**
+ * @brief Fills each I2C_InitStruct member with its default value.
+ * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
+ * @retval None
+ */
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
+{
+ /*---------------- Reset I2C init structure parameters values --------------*/
+ /* Initialize the I2C_Timing member */
+ I2C_InitStruct->I2C_Timing = 0;
+ /* Initialize the I2C_AnalogFilter member */
+ I2C_InitStruct->I2C_AnalogFilter = I2C_AnalogFilter_Enable;
+ /* Initialize the I2C_DigitalFilter member */
+ I2C_InitStruct->I2C_DigitalFilter = 0;
+ /* Initialize the I2C_Mode member */
+ I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
+ /* Initialize the I2C_OwnAddress1 member */
+ I2C_InitStruct->I2C_OwnAddress1 = 0;
+ /* Initialize the I2C_Ack member */
+ I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
+ /* Initialize the I2C_AcknowledgedAddress member */
+ I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+}
+
+/**
+ * @brief Enables or disables the specified I2C peripheral.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C peripheral */
+ I2Cx->CR1 |= I2C_CR1_PE;
+ }
+ else
+ {
+ /* Disable the selected I2C peripheral */
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
+ }
+}
+
+
+/**
+ * @brief Enables or disables the specified I2C software reset.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @retval None
+ */
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+ /* Disable peripheral */
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
+
+ /* Perform a dummy read to delay the disable of peripheral for minimum
+ 3 APB clock cycles to perform the software reset functionality */
+ *(__IO uint32_t *)(uint32_t)I2Cx;
+
+ /* Enable peripheral */
+ I2Cx->CR1 |= I2C_CR1_PE;
+}
+
+/**
+ * @brief Enables or disables the specified I2C interrupts.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_IT_ERRI: Error interrupt mask
+ * @arg I2C_IT_TCI: Transfer Complete interrupt mask
+ * @arg I2C_IT_STOPI: Stop Detection interrupt mask
+ * @arg I2C_IT_NACKI: Not Acknowledge received interrupt mask
+ * @arg I2C_IT_ADDRI: Address Match interrupt mask
+ * @arg I2C_IT_RXI: RX interrupt mask
+ * @arg I2C_IT_TXI: TX interrupt mask
+ * @param NewState: new state of the specified I2C interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_I2C_CONFIG_IT(I2C_IT));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C interrupts */
+ I2Cx->CR1 |= I2C_IT;
+ }
+ else
+ {
+ /* Disable the selected I2C interrupts */
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_IT);
+ }
+}
+
+/**
+ * @brief Enables or disables the I2C Clock stretching.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx Clock stretching.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable clock stretching */
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_NOSTRETCH);
+ }
+ else
+ {
+ /* Disable clock stretching */
+ I2Cx->CR1 |= I2C_CR1_NOSTRETCH;
+ }
+}
+
+/**
+ * @brief Enables or disables I2C wakeup from stop mode.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx stop mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable wakeup from stop mode */
+ I2Cx->CR1 |= I2C_CR1_WUPEN;
+ }
+ else
+ {
+ /* Disable wakeup from stop mode */
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_WUPEN);
+ }
+}
+
+/**
+ * @brief Enables or disables the I2C own address 2.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C own address 2.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable own address 2 */
+ I2Cx->OAR2 |= I2C_OAR2_OA2EN;
+ }
+ else
+ {
+ /* Disable own address 2 */
+ I2Cx->OAR2 &= (uint32_t)~((uint32_t)I2C_OAR2_OA2EN);
+ }
+}
+
+/**
+ * @brief Configures the I2C slave own address 2 and mask.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param Address: specifies the slave address to be programmed.
+ * @param Mask: specifies own address 2 mask to be programmed.
+ * This parameter can be one of the following values:
+ * @arg I2C_OA2_NoMask: no mask.
+ * @arg I2C_OA2_Mask01: OA2[1] is masked and don't care.
+ * @arg I2C_OA2_Mask02: OA2[2:1] are masked and don't care.
+ * @arg I2C_OA2_Mask03: OA2[3:1] are masked and don't care.
+ * @arg I2C_OA2_Mask04: OA2[4:1] are masked and don't care.
+ * @arg I2C_OA2_Mask05: OA2[5:1] are masked and don't care.
+ * @arg I2C_OA2_Mask06: OA2[6:1] are masked and don't care.
+ * @arg I2C_OA2_Mask07: OA2[7:1] are masked and don't care.
+ * @retval None
+ */
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_OWN_ADDRESS2(Address));
+ assert_param(IS_I2C_OWN_ADDRESS2_MASK(Mask));
+
+ /* Get the old register value */
+ tmpreg = I2Cx->OAR2;
+
+ /* Reset I2Cx OA2 bit [7:1] and OA2MSK bit [1:0] */
+ tmpreg &= (uint32_t)~((uint32_t)(I2C_OAR2_OA2 | I2C_OAR2_OA2MSK));
+
+ /* Set I2Cx SADD */
+ tmpreg |= (uint32_t)(((uint32_t)Address & I2C_OAR2_OA2) | \
+ (((uint32_t)Mask << 8) & I2C_OAR2_OA2MSK)) ;
+
+ /* Store the new register value */
+ I2Cx->OAR2 = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the I2C general call mode.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C general call mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable general call mode */
+ I2Cx->CR1 |= I2C_CR1_GCEN;
+ }
+ else
+ {
+ /* Disable general call mode */
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_GCEN);
+ }
+}
+
+/**
+ * @brief Enables or disables the I2C slave byte control.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C slave byte control.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable slave byte control */
+ I2Cx->CR1 |= I2C_CR1_SBC;
+ }
+ else
+ {
+ /* Disable slave byte control */
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_SBC);
+ }
+}
+
+/**
+ * @brief Configures the slave address to be transmitted after start generation.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param Address: specifies the slave address to be programmed.
+ * @note This function should be called before generating start condition.
+ * @retval None
+ */
+void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_SLAVE_ADDRESS(Address));
+
+ /* Get the old register value */
+ tmpreg = I2Cx->CR2;
+
+ /* Reset I2Cx SADD bit [9:0] */
+ tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_SADD);
+
+ /* Set I2Cx SADD */
+ tmpreg |= (uint32_t)((uint32_t)Address & I2C_CR2_SADD);
+
+ /* Store the new register value */
+ I2Cx->CR2 = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the I2C 10-bit addressing mode for the master.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C 10-bit addressing mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note This function should be called before generating start condition.
+ * @retval None
+ */
+void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable 10-bit addressing mode */
+ I2Cx->CR2 |= I2C_CR2_ADD10;
+ }
+ else
+ {
+ /* Disable 10-bit addressing mode */
+ I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_ADD10);
+ }
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup I2C_Group2 Communications handling functions
+ * @brief Communications handling functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Communications handling functions #####
+ ===============================================================================
+ [..] This section provides a set of functions that handles I2C communication.
+
+ [..] Automatic End mode is enabled using I2C_AutoEndCmd() function. When Reload
+ mode is enabled via I2C_ReloadCmd() AutoEnd bit has no effect.
+
+ [..] I2C_NumberOfBytesConfig() function set the number of bytes to be transferred,
+ this configuration should be done before generating start condition in master
+ mode.
+
+ [..] When switching from master write operation to read operation in 10Bit addressing
+ mode, master can only sends the 1st 7 bits of the 10 bit address, followed by
+ Read direction by enabling HEADR bit using I2C_10BitAddressHeader() function.
+
+ [..] In master mode, when transferring more than 255 bytes Reload mode should be used
+ to handle communication. In the first phase of transfer, Nbytes should be set to
+ 255. After transferring these bytes TCR flag is set and I2C_TransferHandling()
+ function should be called to handle remaining communication.
+
+ [..] In master mode, when software end mode is selected when all data is transferred
+ TC flag is set I2C_TransferHandling() function should be called to generate STOP
+ or generate ReStart.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the I2C automatic end mode (stop condition is
+ * automatically sent when nbytes data are transferred).
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C automatic end mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note This function has effect if Reload mode is disabled.
+ * @retval None
+ */
+void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable Auto end mode */
+ I2Cx->CR2 |= I2C_CR2_AUTOEND;
+ }
+ else
+ {
+ /* Disable Auto end mode */
+ I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_AUTOEND);
+ }
+}
+
+/**
+ * @brief Enables or disables the I2C nbytes reload mode.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the nbytes reload mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable Auto Reload mode */
+ I2Cx->CR2 |= I2C_CR2_RELOAD;
+ }
+ else
+ {
+ /* Disable Auto Reload mode */
+ I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RELOAD);
+ }
+}
+
+/**
+ * @brief Configures the number of bytes to be transmitted/received.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param Number_Bytes: specifies the number of bytes to be programmed.
+ * @retval None
+ */
+void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+ /* Get the old register value */
+ tmpreg = I2Cx->CR2;
+
+ /* Reset I2Cx Nbytes bit [7:0] */
+ tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_NBYTES);
+
+ /* Set I2Cx Nbytes */
+ tmpreg |= (uint32_t)(((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES);
+
+ /* Store the new register value */
+ I2Cx->CR2 = tmpreg;
+}
+
+/**
+ * @brief Configures the type of transfer request for the master.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_Direction: specifies the transfer request direction to be programmed.
+ * This parameter can be one of the following values:
+ * @arg I2C_Direction_Transmitter: Master request a write transfer
+ * @arg I2C_Direction_Receiver: Master request a read transfer
+ * @retval None
+ */
+void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction)
+{
+/* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_DIRECTION(I2C_Direction));
+
+ /* Test on the direction to set/reset the read/write bit */
+ if (I2C_Direction == I2C_Direction_Transmitter)
+ {
+ /* Request a write Transfer */
+ I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RD_WRN);
+ }
+ else
+ {
+ /* Request a read Transfer */
+ I2Cx->CR2 |= I2C_CR2_RD_WRN;
+ }
+}
+
+/**
+ * @brief Generates I2Cx communication START condition.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C START condition generation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Generate a START condition */
+ I2Cx->CR2 |= I2C_CR2_START;
+ }
+ else
+ {
+ /* Disable the START condition generation */
+ I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_START);
+ }
+}
+
+/**
+ * @brief Generates I2Cx communication STOP condition.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C STOP condition generation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Generate a STOP condition */
+ I2Cx->CR2 |= I2C_CR2_STOP;
+ }
+ else
+ {
+ /* Disable the STOP condition generation */
+ I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_STOP);
+ }
+}
+
+/**
+ * @brief Enables or disables the I2C 10-bit header only mode with read direction.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C 10-bit header only mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note This mode can be used only when switching from master transmitter mode
+ * to master receiver mode.
+ * @retval None
+ */
+void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable 10-bit header only mode */
+ I2Cx->CR2 |= I2C_CR2_HEAD10R;
+ }
+ else
+ {
+ /* Disable 10-bit header only mode */
+ I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_HEAD10R);
+ }
+}
+
+/**
+ * @brief Generates I2C communication Acknowledge.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the Acknowledge.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable ACK generation */
+ I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_NACK);
+ }
+ else
+ {
+ /* Enable NACK generation */
+ I2Cx->CR2 |= I2C_CR2_NACK;
+ }
+}
+
+/**
+ * @brief Returns the I2C slave matched address .
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @retval The value of the slave matched address .
+ */
+uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+ /* Return the slave matched address in the SR1 register */
+ return (uint8_t)(((uint32_t)I2Cx->ISR & I2C_ISR_ADDCODE) >> 16) ;
+}
+
+/**
+ * @brief Returns the I2C slave received request.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @retval The value of the received request.
+ */
+uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx)
+{
+ uint32_t tmpreg = 0;
+ uint16_t direction = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+ /* Return the slave matched address in the SR1 register */
+ tmpreg = (uint32_t)(I2Cx->ISR & I2C_ISR_DIR);
+
+ /* If write transfer is requested */
+ if (tmpreg == 0)
+ {
+ /* write transfer is requested */
+ direction = I2C_Direction_Transmitter;
+ }
+ else
+ {
+ /* Read transfer is requested */
+ direction = I2C_Direction_Receiver;
+ }
+ return direction;
+}
+
+/**
+ * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param Address: specifies the slave address to be programmed.
+ * @param Number_Bytes: specifies the number of bytes to be programmed.
+ * This parameter must be a value between 0 and 255.
+ * @param ReloadEndMode: new state of the I2C START condition generation.
+ * This parameter can be one of the following values:
+ * @arg I2C_Reload_Mode: Enable Reload mode .
+ * @arg I2C_AutoEnd_Mode: Enable Automatic end mode.
+ * @arg I2C_SoftEnd_Mode: Enable Software end mode.
+ * @param StartStopMode: new state of the I2C START condition generation.
+ * This parameter can be one of the following values:
+ * @arg I2C_No_StartStop: Don't Generate stop and start condition.
+ * @arg I2C_Generate_Stop: Generate stop condition (Number_Bytes should be set to 0).
+ * @arg I2C_Generate_Start_Read: Generate Restart for read request.
+ * @arg I2C_Generate_Start_Write: Generate Restart for write request.
+ * @retval None
+ */
+void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_SLAVE_ADDRESS(Address));
+ assert_param(IS_RELOAD_END_MODE(ReloadEndMode));
+ assert_param(IS_START_STOP_MODE(StartStopMode));
+
+ /* Get the CR2 register value */
+ tmpreg = I2Cx->CR2;
+
+ /* clear tmpreg specific bits */
+ tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
+
+ /* update tmpreg */
+ tmpreg |= (uint32_t)(((uint32_t)Address & I2C_CR2_SADD) | (((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES) | \
+ (uint32_t)ReloadEndMode | (uint32_t)StartStopMode);
+
+ /* update CR2 register */
+ I2Cx->CR2 = tmpreg;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup I2C_Group3 SMBUS management functions
+ * @brief SMBUS management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### SMBUS management functions #####
+ ===============================================================================
+ [..] This section provides a set of functions that handles SMBus communication
+ and timeouts detection.
+
+ [..] The SMBus Device default address (0b1100 001) is enabled by calling I2C_Init()
+ function and setting I2C_Mode member of I2C_InitTypeDef() structure to
+ I2C_Mode_SMBusDevice.
+
+ [..] The SMBus Host address (0b0001 000) is enabled by calling I2C_Init()
+ function and setting I2C_Mode member of I2C_InitTypeDef() structure to
+ I2C_Mode_SMBusHost.
+
+ [..] The Alert Response Address (0b0001 100) is enabled using I2C_SMBusAlertCmd()
+ function.
+
+ [..] To detect cumulative SCL stretch in master and slave mode, TIMEOUTB should be
+ configured (in accordance to SMBus specification) using I2C_TimeoutBConfig()
+ function then I2C_ExtendedClockTimeoutCmd() function should be called to enable
+ the detection.
+
+ [..] SCL low timeout is detected by configuring TIMEOUTB using I2C_TimeoutBConfig()
+ function followed by the call of I2C_ClockTimeoutCmd(). When adding to this
+ procedure the call of I2C_IdleClockTimeoutCmd() function, Bus Idle condition
+ (both SCL and SDA high) is detected also.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables I2C SMBus alert.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx SMBus alert.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable SMBus alert */
+ I2Cx->CR1 |= I2C_CR1_ALERTEN;
+ }
+ else
+ {
+ /* Disable SMBus alert */
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_ALERTEN);
+ }
+}
+
+/**
+ * @brief Enables or disables I2C Clock Timeout (SCL Timeout detection).
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx clock Timeout.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable Clock Timeout */
+ I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIMOUTEN;
+ }
+ else
+ {
+ /* Disable Clock Timeout */
+ I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMOUTEN);
+ }
+}
+
+/**
+ * @brief Enables or disables I2C Extended Clock Timeout (SCL cumulative Timeout detection).
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx Extended clock Timeout.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable Clock Timeout */
+ I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TEXTEN;
+ }
+ else
+ {
+ /* Disable Clock Timeout */
+ I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TEXTEN);
+ }
+}
+
+/**
+ * @brief Enables or disables I2C Idle Clock Timeout (Bus idle SCL and SDA
+ * high detection).
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx Idle clock Timeout.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable Clock Timeout */
+ I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIDLE;
+ }
+ else
+ {
+ /* Disable Clock Timeout */
+ I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIDLE);
+ }
+}
+
+/**
+ * @brief Configures the I2C Bus Timeout A (SCL Timeout when TIDLE = 0 or Bus
+ * idle SCL and SDA high when TIDLE = 1).
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param Timeout: specifies the TimeoutA to be programmed.
+ * @retval None
+ */
+void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_TIMEOUT(Timeout));
+
+ /* Get the old register value */
+ tmpreg = I2Cx->TIMEOUTR;
+
+ /* Reset I2Cx TIMEOUTA bit [11:0] */
+ tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTA);
+
+ /* Set I2Cx TIMEOUTA */
+ tmpreg |= (uint32_t)((uint32_t)Timeout & I2C_TIMEOUTR_TIMEOUTA) ;
+
+ /* Store the new register value */
+ I2Cx->TIMEOUTR = tmpreg;
+}
+
+/**
+ * @brief Configures the I2C Bus Timeout B (SCL cumulative Timeout).
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param Timeout: specifies the TimeoutB to be programmed.
+ * @retval None
+ */
+void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_TIMEOUT(Timeout));
+
+ /* Get the old register value */
+ tmpreg = I2Cx->TIMEOUTR;
+
+ /* Reset I2Cx TIMEOUTB bit [11:0] */
+ tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTB);
+
+ /* Set I2Cx TIMEOUTB */
+ tmpreg |= (uint32_t)(((uint32_t)Timeout << 16) & I2C_TIMEOUTR_TIMEOUTB) ;
+
+ /* Store the new register value */
+ I2Cx->TIMEOUTR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables I2C PEC calculation.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx PEC calculation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable PEC calculation */
+ I2Cx->CR1 |= I2C_CR1_PECEN;
+ }
+ else
+ {
+ /* Disable PEC calculation */
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PECEN);
+ }
+}
+
+/**
+ * @brief Enables or disables I2C PEC transmission/reception request.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx PEC request.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable PEC transmission/reception request */
+ I2Cx->CR1 |= I2C_CR2_PECBYTE;
+ }
+ else
+ {
+ /* Disable PEC transmission/reception request */
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR2_PECBYTE);
+ }
+}
+
+/**
+ * @brief Returns the I2C PEC.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @retval The value of the PEC .
+ */
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+ /* Return the slave matched address in the SR1 register */
+ return (uint8_t)((uint32_t)I2Cx->PECR & I2C_PECR_PEC);
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup I2C_Group4 I2C registers management functions
+ * @brief I2C registers management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### I2C registers management functions #####
+ ===============================================================================
+ [..] This section provides a functions that allow user the management of
+ I2C registers.
+
+@endverbatim
+ * @{
+ */
+
+ /**
+ * @brief Reads the specified I2C register and returns its value.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_Register: specifies the register to read.
+ * This parameter can be one of the following values:
+ * @arg I2C_Register_CR1: CR1 register.
+ * @arg I2C_Register_CR2: CR2 register.
+ * @arg I2C_Register_OAR1: OAR1 register.
+ * @arg I2C_Register_OAR2: OAR2 register.
+ * @arg I2C_Register_TIMINGR: TIMING register.
+ * @arg I2C_Register_TIMEOUTR: TIMEOUTR register.
+ * @arg I2C_Register_ISR: ISR register.
+ * @arg I2C_Register_ICR: ICR register.
+ * @arg I2C_Register_PECR: PECR register.
+ * @arg I2C_Register_RXDR: RXDR register.
+ * @arg I2C_Register_TXDR: TXDR register.
+ * @retval The value of the read register.
+ */
+uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_REGISTER(I2C_Register));
+
+ tmp = (uint32_t)I2Cx;
+ tmp += I2C_Register;
+
+ /* Return the selected register value */
+ return (*(__IO uint32_t *) tmp);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Group5 Data transfers management functions
+ * @brief Data transfers management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Data transfers management functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to manage
+ the I2C data transfers.
+
+ [..] The read access of the I2C_RXDR register can be done using
+ the I2C_ReceiveData() function and returns the received value.
+ Whereas a write access to the I2C_TXDR can be done using I2C_SendData()
+ function and stores the written data into TXDR.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Sends a data byte through the I2Cx peripheral.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param Data: Byte to be transmitted..
+ * @retval None
+ */
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+ /* Write in the DR register the data to be sent */
+ I2Cx->TXDR = (uint8_t)Data;
+}
+
+/**
+ * @brief Returns the most recent received data by the I2Cx peripheral.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @retval The value of the received data.
+ */
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+ /* Return the data in the DR register */
+ return (uint8_t)I2Cx->RXDR;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup I2C_Group6 DMA transfers management functions
+ * @brief DMA transfers management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### DMA transfers management functions #####
+ ===============================================================================
+ [..] This section provides two functions that can be used only in DMA mode.
+ [..] In DMA Mode, the I2C communication can be managed by 2 DMA Channel
+ requests:
+ (#) I2C_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
+ (#) I2C_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
+ [..] In this Mode it is advised to use the following function:
+ (+) I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState);
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the I2C DMA interface.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_DMAReq: specifies the I2C DMA transfer request to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_DMAReq_Tx: Tx DMA transfer request
+ * @arg I2C_DMAReq_Rx: Rx DMA transfer request
+ * @param NewState: new state of the selected I2C DMA transfer request.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_I2C_DMA_REQ(I2C_DMAReq));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C DMA requests */
+ I2Cx->CR1 |= I2C_DMAReq;
+ }
+ else
+ {
+ /* Disable the selected I2C DMA requests */
+ I2Cx->CR1 &= (uint32_t)~I2C_DMAReq;
+ }
+}
+/**
+ * @}
+ */
+
+
+/** @defgroup I2C_Group7 Interrupts and flags management functions
+ * @brief Interrupts and flags management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupts and flags management functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to configure the I2C Interrupts
+ sources and check or clear the flags or pending bits status.
+ The user should identify which mode will be used in his application to manage
+ the communication: Polling mode, Interrupt mode or DMA mode(refer I2C_Group6) .
+
+ *** Polling Mode ***
+ ====================
+ [..] In Polling Mode, the I2C communication can be managed by 15 flags:
+ (#) I2C_FLAG_TXE: to indicate the status of Transmit data register empty flag.
+ (#) I2C_FLAG_TXIS: to indicate the status of Transmit interrupt status flag .
+ (#) I2C_FLAG_RXNE: to indicate the status of Receive data register not empty flag.
+ (#) I2C_FLAG_ADDR: to indicate the status of Address matched flag (slave mode).
+ (#) I2C_FLAG_NACKF: to indicate the status of NACK received flag.
+ (#) I2C_FLAG_STOPF: to indicate the status of STOP detection flag.
+ (#) I2C_FLAG_TC: to indicate the status of Transfer complete flag(master mode).
+ (#) I2C_FLAG_TCR: to indicate the status of Transfer complete reload flag.
+ (#) I2C_FLAG_BERR: to indicate the status of Bus error flag.
+ (#) I2C_FLAG_ARLO: to indicate the status of Arbitration lost flag.
+ (#) I2C_FLAG_OVR: to indicate the status of Overrun/Underrun flag.
+ (#) I2C_FLAG_PECERR: to indicate the status of PEC error in reception flag.
+ (#) I2C_FLAG_TIMEOUT: to indicate the status of Timeout or Tlow detection flag.
+ (#) I2C_FLAG_ALERT: to indicate the status of SMBus Alert flag.
+ (#) I2C_FLAG_BUSY: to indicate the status of Bus busy flag.
+
+ [..] In this Mode it is advised to use the following functions:
+ (+) FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+ (+) void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+
+ [..]
+ (@)Do not use the BUSY flag to handle each data transmission or reception.It is
+ better to use the TXIS and RXNE flags instead.
+
+ *** Interrupt Mode ***
+ ======================
+ [..] In Interrupt Mode, the I2C communication can be managed by 7 interrupt sources
+ and 15 pending bits:
+ [..] Interrupt Source:
+ (#) I2C_IT_ERRI: specifies the interrupt source for the Error interrupt.
+ (#) I2C_IT_TCI: specifies the interrupt source for the Transfer Complete interrupt.
+ (#) I2C_IT_STOPI: specifies the interrupt source for the Stop Detection interrupt.
+ (#) I2C_IT_NACKI: specifies the interrupt source for the Not Acknowledge received interrupt.
+ (#) I2C_IT_ADDRI: specifies the interrupt source for the Address Match interrupt.
+ (#) I2C_IT_RXI: specifies the interrupt source for the RX interrupt.
+ (#) I2C_IT_TXI: specifies the interrupt source for the TX interrupt.
+
+ [..] Pending Bits:
+ (#) I2C_IT_TXIS: to indicate the status of Transmit interrupt status flag.
+ (#) I2C_IT_RXNE: to indicate the status of Receive data register not empty flag.
+ (#) I2C_IT_ADDR: to indicate the status of Address matched flag (slave mode).
+ (#) I2C_IT_NACKF: to indicate the status of NACK received flag.
+ (#) I2C_IT_STOPF: to indicate the status of STOP detection flag.
+ (#) I2C_IT_TC: to indicate the status of Transfer complete flag (master mode).
+ (#) I2C_IT_TCR: to indicate the status of Transfer complete reload flag.
+ (#) I2C_IT_BERR: to indicate the status of Bus error flag.
+ (#) I2C_IT_ARLO: to indicate the status of Arbitration lost flag.
+ (#) I2C_IT_OVR: to indicate the status of Overrun/Underrun flag.
+ (#) I2C_IT_PECERR: to indicate the status of PEC error in reception flag.
+ (#) I2C_IT_TIMEOUT: to indicate the status of Timeout or Tlow detection flag.
+ (#) I2C_IT_ALERT: to indicate the status of SMBus Alert flag.
+
+ [..] In this Mode it is advised to use the following functions:
+ (+) void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+ (+) ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Checks whether the specified I2C flag is set or not.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg I2C_FLAG_TXE: Transmit data register empty
+ * @arg I2C_FLAG_TXIS: Transmit interrupt status
+ * @arg I2C_FLAG_RXNE: Receive data register not empty
+ * @arg I2C_FLAG_ADDR: Address matched (slave mode)
+ * @arg I2C_FLAG_NACKF: NACK received flag
+ * @arg I2C_FLAG_STOPF: STOP detection flag
+ * @arg I2C_FLAG_TC: Transfer complete (master mode)
+ * @arg I2C_FLAG_TCR: Transfer complete reload
+ * @arg I2C_FLAG_BERR: Bus error
+ * @arg I2C_FLAG_ARLO: Arbitration lost
+ * @arg I2C_FLAG_OVR: Overrun/Underrun
+ * @arg I2C_FLAG_PECERR: PEC error in reception
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
+ * @arg I2C_FLAG_ALERT: SMBus Alert
+ * @arg I2C_FLAG_BUSY: Bus busy
+ * @retval The new state of I2C_FLAG (SET or RESET).
+ */
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
+{
+ uint32_t tmpreg = 0;
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
+
+ /* Get the ISR register value */
+ tmpreg = I2Cx->ISR;
+
+ /* Get flag status */
+ tmpreg &= I2C_FLAG;
+
+ if(tmpreg != 0)
+ {
+ /* I2C_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* I2C_FLAG is reset */
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the I2Cx's pending flags.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_FLAG: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_FLAG_ADDR: Address matched (slave mode)
+ * @arg I2C_FLAG_NACKF: NACK received flag
+ * @arg I2C_FLAG_STOPF: STOP detection flag
+ * @arg I2C_FLAG_BERR: Bus error
+ * @arg I2C_FLAG_ARLO: Arbitration lost
+ * @arg I2C_FLAG_OVR: Overrun/Underrun
+ * @arg I2C_FLAG_PECERR: PEC error in reception
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
+ * @arg I2C_FLAG_ALERT: SMBus Alert
+ * @retval The new state of I2C_FLAG (SET or RESET).
+ */
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
+
+ /* Clear the selected flag */
+ I2Cx->ICR = I2C_FLAG;
+ }
+
+/**
+ * @brief Checks whether the specified I2C interrupt has occurred or not.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT: specifies the interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg I2C_IT_TXIS: Transmit interrupt status
+ * @arg I2C_IT_RXNE: Receive data register not empty
+ * @arg I2C_IT_ADDR: Address matched (slave mode)
+ * @arg I2C_IT_NACKF: NACK received flag
+ * @arg I2C_IT_STOPF: STOP detection flag
+ * @arg I2C_IT_TC: Transfer complete (master mode)
+ * @arg I2C_IT_TCR: Transfer complete reload
+ * @arg I2C_IT_BERR: Bus error
+ * @arg I2C_IT_ARLO: Arbitration lost
+ * @arg I2C_IT_OVR: Overrun/Underrun
+ * @arg I2C_IT_PECERR: PEC error in reception
+ * @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag
+ * @arg I2C_IT_ALERT: SMBus Alert
+ * @retval The new state of I2C_IT (SET or RESET).
+ */
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
+{
+ uint32_t tmpreg = 0;
+ ITStatus bitstatus = RESET;
+ uint32_t enablestatus = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_GET_IT(I2C_IT));
+
+ /* Check if the interrupt source is enabled or not */
+ /* If Error interrupt */
+ if((uint32_t)(I2C_IT & ERROR_IT_MASK))
+ {
+ enablestatus = (uint32_t)((I2C_CR1_ERRIE) & (I2Cx->CR1));
+ }
+ /* If TC interrupt */
+ else if((uint32_t)(I2C_IT & TC_IT_MASK))
+ {
+ enablestatus = (uint32_t)((I2C_CR1_TCIE) & (I2Cx->CR1));
+ }
+ else
+ {
+ enablestatus = (uint32_t)((I2C_IT) & (I2Cx->CR1));
+ }
+
+ /* Get the ISR register value */
+ tmpreg = I2Cx->ISR;
+
+ /* Get flag status */
+ tmpreg &= I2C_IT;
+
+ /* Check the status of the specified I2C flag */
+ if((tmpreg != RESET) && enablestatus)
+ {
+ /* I2C_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* I2C_IT is reset */
+ bitstatus = RESET;
+ }
+
+ /* Return the I2C_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the I2Cx's interrupt pending bits.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT: specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_IT_ADDR: Address matched (slave mode)
+ * @arg I2C_IT_NACKF: NACK received flag
+ * @arg I2C_IT_STOPF: STOP detection flag
+ * @arg I2C_IT_BERR: Bus error
+ * @arg I2C_IT_ARLO: Arbitration lost
+ * @arg I2C_IT_OVR: Overrun/Underrun
+ * @arg I2C_IT_PECERR: PEC error in reception
+ * @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag
+ * @arg I2C_IT_ALERT: SMBus Alert
+ * @retval The new state of I2C_IT (SET or RESET).
+ */
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_CLEAR_IT(I2C_IT));
+
+ /* Clear the selected flag */
+ I2Cx->ICR = I2C_IT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_i2c.h Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,487 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_i2c.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the I2C firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_I2C_H
+#define __STM32F30x_I2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup I2C
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief I2C Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t I2C_Timing; /*!< Specifies the I2C_TIMINGR_register value.
+ This parameter calculated by referring to I2C initialization
+ section in Reference manual*/
+
+ uint32_t I2C_AnalogFilter; /*!< Enables or disables analog noise filter.
+ This parameter can be a value of @ref I2C_Analog_Filter */
+
+ uint32_t I2C_DigitalFilter; /*!< Configures the digital noise filter.
+ This parameter can be a number between 0x00 and 0x0F */
+
+ uint32_t I2C_Mode; /*!< Specifies the I2C mode.
+ This parameter can be a value of @ref I2C_mode */
+
+ uint32_t I2C_OwnAddress1; /*!< Specifies the device own address 1.
+ This parameter can be a 7-bit or 10-bit address */
+
+ uint32_t I2C_Ack; /*!< Enables or disables the acknowledgement.
+ This parameter can be a value of @ref I2C_acknowledgement */
+
+ uint32_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
+ This parameter can be a value of @ref I2C_acknowledged_address */
+}I2C_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+
+/** @defgroup I2C_Exported_Constants
+ * @{
+ */
+
+#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
+ ((PERIPH) == I2C2))
+
+/** @defgroup I2C_Analog_Filter
+ * @{
+ */
+
+#define I2C_AnalogFilter_Enable ((uint32_t)0x00000000)
+#define I2C_AnalogFilter_Disable I2C_CR1_ANFOFF
+
+#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_AnalogFilter_Enable) || \
+ ((FILTER) == I2C_AnalogFilter_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Digital_Filter
+ * @{
+ */
+
+#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_mode
+ * @{
+ */
+
+#define I2C_Mode_I2C ((uint32_t)0x00000000)
+#define I2C_Mode_SMBusDevice I2C_CR1_SMBDEN
+#define I2C_Mode_SMBusHost I2C_CR1_SMBHEN
+
+#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
+ ((MODE) == I2C_Mode_SMBusDevice) || \
+ ((MODE) == I2C_Mode_SMBusHost))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_acknowledgement
+ * @{
+ */
+
+#define I2C_Ack_Enable ((uint32_t)0x00000000)
+#define I2C_Ack_Disable I2C_CR2_NACK
+
+#define IS_I2C_ACK(ACK) (((ACK) == I2C_Ack_Enable) || \
+ ((ACK) == I2C_Ack_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_acknowledged_address
+ * @{
+ */
+
+#define I2C_AcknowledgedAddress_7bit ((uint32_t)0x00000000)
+#define I2C_AcknowledgedAddress_10bit I2C_OAR1_OA1MODE
+
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
+ ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_own_address1
+ * @{
+ */
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_transfer_direction
+ * @{
+ */
+
+#define I2C_Direction_Transmitter ((uint16_t)0x0000)
+#define I2C_Direction_Receiver ((uint16_t)0x0400)
+
+#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
+ ((DIRECTION) == I2C_Direction_Receiver))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_DMA_transfer_requests
+ * @{
+ */
+
+#define I2C_DMAReq_Tx I2C_CR1_TXDMAEN
+#define I2C_DMAReq_Rx I2C_CR1_RXDMAEN
+
+#define IS_I2C_DMA_REQ(REQ) ((((REQ) & (uint32_t)0xFFFF3FFF) == 0x00) && ((REQ) != 0x00))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_slave_address
+ * @{
+ */
+
+#define IS_I2C_SLAVE_ADDRESS(ADDRESS) ((ADDRESS) <= (uint16_t)0x03FF)
+/**
+ * @}
+ */
+
+
+/** @defgroup I2C_own_address2
+ * @{
+ */
+
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_own_address2_mask
+ * @{
+ */
+
+#define I2C_OA2_NoMask ((uint8_t)0x00)
+#define I2C_OA2_Mask01 ((uint8_t)0x01)
+#define I2C_OA2_Mask02 ((uint8_t)0x02)
+#define I2C_OA2_Mask03 ((uint8_t)0x03)
+#define I2C_OA2_Mask04 ((uint8_t)0x04)
+#define I2C_OA2_Mask05 ((uint8_t)0x05)
+#define I2C_OA2_Mask06 ((uint8_t)0x06)
+#define I2C_OA2_Mask07 ((uint8_t)0x07)
+
+#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NoMask) || \
+ ((MASK) == I2C_OA2_Mask01) || \
+ ((MASK) == I2C_OA2_Mask02) || \
+ ((MASK) == I2C_OA2_Mask03) || \
+ ((MASK) == I2C_OA2_Mask04) || \
+ ((MASK) == I2C_OA2_Mask05) || \
+ ((MASK) == I2C_OA2_Mask06) || \
+ ((MASK) == I2C_OA2_Mask07))
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_timeout
+ * @{
+ */
+
+#define IS_I2C_TIMEOUT(TIMEOUT) ((TIMEOUT) <= (uint16_t)0x0FFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_registers
+ * @{
+ */
+
+#define I2C_Register_CR1 ((uint8_t)0x00)
+#define I2C_Register_CR2 ((uint8_t)0x04)
+#define I2C_Register_OAR1 ((uint8_t)0x08)
+#define I2C_Register_OAR2 ((uint8_t)0x0C)
+#define I2C_Register_TIMINGR ((uint8_t)0x10)
+#define I2C_Register_TIMEOUTR ((uint8_t)0x14)
+#define I2C_Register_ISR ((uint8_t)0x18)
+#define I2C_Register_ICR ((uint8_t)0x1C)
+#define I2C_Register_PECR ((uint8_t)0x20)
+#define I2C_Register_RXDR ((uint8_t)0x24)
+#define I2C_Register_TXDR ((uint8_t)0x28)
+
+#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
+ ((REGISTER) == I2C_Register_CR2) || \
+ ((REGISTER) == I2C_Register_OAR1) || \
+ ((REGISTER) == I2C_Register_OAR2) || \
+ ((REGISTER) == I2C_Register_TIMINGR) || \
+ ((REGISTER) == I2C_Register_TIMEOUTR) || \
+ ((REGISTER) == I2C_Register_ISR) || \
+ ((REGISTER) == I2C_Register_ICR) || \
+ ((REGISTER) == I2C_Register_PECR) || \
+ ((REGISTER) == I2C_Register_RXDR) || \
+ ((REGISTER) == I2C_Register_TXDR))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_interrupts_definition
+ * @{
+ */
+
+#define I2C_IT_ERRI I2C_CR1_ERRIE
+#define I2C_IT_TCI I2C_CR1_TCIE
+#define I2C_IT_STOPI I2C_CR1_STOPIE
+#define I2C_IT_NACKI I2C_CR1_NACKIE
+#define I2C_IT_ADDRI I2C_CR1_ADDRIE
+#define I2C_IT_RXI I2C_CR1_RXIE
+#define I2C_IT_TXI I2C_CR1_TXIE
+
+#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint32_t)0xFFFFFF01) == 0x00) && ((IT) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_flags_definition
+ * @{
+ */
+
+#define I2C_FLAG_TXE I2C_ISR_TXE
+#define I2C_FLAG_TXIS I2C_ISR_TXIS
+#define I2C_FLAG_RXNE I2C_ISR_RXNE
+#define I2C_FLAG_ADDR I2C_ISR_ADDR
+#define I2C_FLAG_NACKF I2C_ISR_NACKF
+#define I2C_FLAG_STOPF I2C_ISR_STOPF
+#define I2C_FLAG_TC I2C_ISR_TC
+#define I2C_FLAG_TCR I2C_ISR_TCR
+#define I2C_FLAG_BERR I2C_ISR_BERR
+#define I2C_FLAG_ARLO I2C_ISR_ARLO
+#define I2C_FLAG_OVR I2C_ISR_OVR
+#define I2C_FLAG_PECERR I2C_ISR_PECERR
+#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
+#define I2C_FLAG_ALERT I2C_ISR_ALERT
+#define I2C_FLAG_BUSY I2C_ISR_BUSY
+
+#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFF4000) == 0x00) && ((FLAG) != 0x00))
+
+#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_TXIS) || \
+ ((FLAG) == I2C_FLAG_RXNE) || ((FLAG) == I2C_FLAG_ADDR) || \
+ ((FLAG) == I2C_FLAG_NACKF) || ((FLAG) == I2C_FLAG_STOPF) || \
+ ((FLAG) == I2C_FLAG_TC) || ((FLAG) == I2C_FLAG_TCR) || \
+ ((FLAG) == I2C_FLAG_BERR) || ((FLAG) == I2C_FLAG_ARLO) || \
+ ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_PECERR) || \
+ ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_ALERT) || \
+ ((FLAG) == I2C_FLAG_BUSY))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup I2C_interrupts_definition
+ * @{
+ */
+
+#define I2C_IT_TXIS I2C_ISR_TXIS
+#define I2C_IT_RXNE I2C_ISR_RXNE
+#define I2C_IT_ADDR I2C_ISR_ADDR
+#define I2C_IT_NACKF I2C_ISR_NACKF
+#define I2C_IT_STOPF I2C_ISR_STOPF
+#define I2C_IT_TC I2C_ISR_TC
+#define I2C_IT_TCR I2C_ISR_TCR
+#define I2C_IT_BERR I2C_ISR_BERR
+#define I2C_IT_ARLO I2C_ISR_ARLO
+#define I2C_IT_OVR I2C_ISR_OVR
+#define I2C_IT_PECERR I2C_ISR_PECERR
+#define I2C_IT_TIMEOUT I2C_ISR_TIMEOUT
+#define I2C_IT_ALERT I2C_ISR_ALERT
+
+#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFFFFC001) == 0x00) && ((IT) != 0x00))
+
+#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_TXIS) || ((IT) == I2C_IT_RXNE) || \
+ ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_NACKF) || \
+ ((IT) == I2C_IT_STOPF) || ((IT) == I2C_IT_TC) || \
+ ((IT) == I2C_IT_TCR) || ((IT) == I2C_IT_BERR) || \
+ ((IT) == I2C_IT_ARLO) || ((IT) == I2C_IT_OVR) || \
+ ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_TIMEOUT) || \
+ ((IT) == I2C_IT_ALERT))
+
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_ReloadEndMode_definition
+ * @{
+ */
+
+#define I2C_Reload_Mode I2C_CR2_RELOAD
+#define I2C_AutoEnd_Mode I2C_CR2_AUTOEND
+#define I2C_SoftEnd_Mode ((uint32_t)0x00000000)
+
+
+#define IS_RELOAD_END_MODE(MODE) (((MODE) == I2C_Reload_Mode) || \
+ ((MODE) == I2C_AutoEnd_Mode) || \
+ ((MODE) == I2C_SoftEnd_Mode))
+
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_StartStopMode_definition
+ * @{
+ */
+
+#define I2C_No_StartStop ((uint32_t)0x00000000)
+#define I2C_Generate_Stop I2C_CR2_STOP
+#define I2C_Generate_Start_Read (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
+#define I2C_Generate_Start_Write I2C_CR2_START
+
+
+#define IS_START_STOP_MODE(MODE) (((MODE) == I2C_Generate_Stop) || \
+ ((MODE) == I2C_Generate_Start_Read) || \
+ ((MODE) == I2C_Generate_Start_Write) || \
+ ((MODE) == I2C_No_StartStop))
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+
+/* Initialization and Configuration functions *********************************/
+void I2C_DeInit(I2C_TypeDef* I2Cx);
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx);
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState);
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask);
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address);
+void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+
+/* Communications handling functions ******************************************/
+void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes);
+void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction);
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
+uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx);
+uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx);
+void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode);
+
+/* SMBUS management functions ************************************************/
+void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);
+void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
+
+/* I2C registers management functions *****************************************/
+uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
+
+/* Data transfers management functions ****************************************/
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
+
+/* DMA transfers management functions *****************************************/
+void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F30x_I2C_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_iwdg.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,298 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_iwdg.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Independent watchdog (IWDG) peripheral:
+ * + Prescaler and Counter configuration
+ * + IWDG activation
+ * + Flag management
+ *
+ @verbatim
+
+ ===============================================================================
+ ##### IWDG features #####
+ ===============================================================================
+ [..] The IWDG can be started by either software or hardware (configurable
+ through option byte).
+ [..] The IWDG is clocked by its own dedicated low-speed clock (LSI) and
+ thus stays active even if the main clock fails.
+ Once the IWDG is started, the LSI is forced ON and cannot be disabled
+ (LSI cannot be disabled too), and the counter starts counting down from
+ the reset value of 0xFFF. When it reaches the end of count value (0x000)
+ a system reset is generated.
+ The IWDG counter should be reloaded at regular intervals to prevent
+ an MCU reset.
+ [..] The IWDG is implemented in the VDD voltage domain that is still functional
+ in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
+ [..] IWDGRST flag in RCC_CSR register can be used to inform when a IWDG
+ reset occurs.
+ [..] Min-max timeout value @41KHz (LSI): ~0.1ms / ~25.5s
+ The IWDG timeout may vary due to LSI frequency dispersion. STM32F30x
+ devices provide the capability to measure the LSI frequency (LSI clock
+ connected internally to TIM16 CH1 input capture). The measured value
+ can be used to have an IWDG timeout with an acceptable accuracy.
+ For more information, please refer to the STM32F30x Reference manual.
+
+ ##### How to use this driver #####
+ ===============================================================================
+ [..] This driver allows to use IWDG peripheral with either window option enabled
+ or disabled. To do so follow one of the two procedures below.
+ (#) Window option is enabled:
+ (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used
+ in software mode (no need to enable the LSI, it will be enabled
+ by hardware).
+ (++) Enable write access to IWDG_PR and IWDG_RLR registers using
+ IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.
+ (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function.
+ (++) Configure the IWDG counter value using IWDG_SetReload() function.
+ This value will be loaded in the IWDG counter each time the counter
+ is reloaded, then the IWDG will start counting down from this value.
+ (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function.
+ (++) Configure the IWDG refresh window using IWDG_SetWindowValue() function.
+
+ (#) Window option is disabled:
+ (++) Enable write access to IWDG_PR and IWDG_RLR registers using
+ IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.
+ (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function.
+ (++) Configure the IWDG counter value using IWDG_SetReload() function.
+ This value will be loaded in the IWDG counter each time the counter
+ is reloaded, then the IWDG will start counting down from this value.
+ (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function.
+ (++) reload the IWDG counter at regular intervals during normal operation
+ to prevent an MCU reset, using IWDG_ReloadCounter() function.
+ (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used
+ in software mode (no need to enable the LSI, it will be enabled
+ by hardware).
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_iwdg.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup IWDG
+ * @brief IWDG driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ---------------------- IWDG registers bit mask ----------------------------*/
+/* KR register bit mask */
+#define KR_KEY_RELOAD ((uint16_t)0xAAAA)
+#define KR_KEY_ENABLE ((uint16_t)0xCCCC)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup IWDG_Private_Functions
+ * @{
+ */
+
+/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions
+ * @brief Prescaler and Counter configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Prescaler and Counter configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
+ * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
+ * This parameter can be one of the following values:
+ * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
+ * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
+ * @retval None
+ */
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
+ IWDG->KR = IWDG_WriteAccess;
+}
+
+/**
+ * @brief Sets IWDG Prescaler value.
+ * @param IWDG_Prescaler: specifies the IWDG Prescaler value.
+ * This parameter can be one of the following values:
+ * @arg IWDG_Prescaler_4: IWDG prescaler set to 4
+ * @arg IWDG_Prescaler_8: IWDG prescaler set to 8
+ * @arg IWDG_Prescaler_16: IWDG prescaler set to 16
+ * @arg IWDG_Prescaler_32: IWDG prescaler set to 32
+ * @arg IWDG_Prescaler_64: IWDG prescaler set to 64
+ * @arg IWDG_Prescaler_128: IWDG prescaler set to 128
+ * @arg IWDG_Prescaler_256: IWDG prescaler set to 256
+ * @retval None
+ */
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
+ IWDG->PR = IWDG_Prescaler;
+}
+
+/**
+ * @brief Sets IWDG Reload value.
+ * @param Reload: specifies the IWDG Reload value.
+ * This parameter must be a number between 0 and 0x0FFF.
+ * @retval None
+ */
+void IWDG_SetReload(uint16_t Reload)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_RELOAD(Reload));
+ IWDG->RLR = Reload;
+}
+
+/**
+ * @brief Reloads IWDG counter with value defined in the reload register
+ * (write access to IWDG_PR and IWDG_RLR registers disabled).
+ * @param None
+ * @retval None
+ */
+void IWDG_ReloadCounter(void)
+{
+ IWDG->KR = KR_KEY_RELOAD;
+}
+
+
+/**
+ * @brief Sets the IWDG window value.
+ * @param WindowValue: specifies the window value to be compared to the downcounter.
+ * @retval None
+ */
+void IWDG_SetWindowValue(uint16_t WindowValue)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_WINDOW_VALUE(WindowValue));
+ IWDG->WINR = WindowValue;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Group2 IWDG activation function
+ * @brief IWDG activation function
+ *
+@verbatim
+ ===============================================================================
+ ##### IWDG activation function #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
+ * @param None
+ * @retval None
+ */
+void IWDG_Enable(void)
+{
+ IWDG->KR = KR_KEY_ENABLE;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Group3 Flag management function
+ * @brief Flag management function
+ *
+@verbatim
+ ===============================================================================
+ ##### Flag management function #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Checks whether the specified IWDG flag is set or not.
+ * @param IWDG_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg IWDG_FLAG_PVU: Prescaler Value Update on going
+ * @arg IWDG_FLAG_RVU: Reload Value Update on going
+ * @arg IWDG_FLAG_WVU: Counter Window Value Update on going
+ * @retval The new state of IWDG_FLAG (SET or RESET).
+ */
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_IWDG_FLAG(IWDG_FLAG));
+ if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_iwdg.h Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,163 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_iwdg.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the IWDG
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_IWDG_H
+#define __STM32F30x_IWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup IWDG
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup IWDG_Exported_Constants
+ * @{
+ */
+
+/** @defgroup IWDG_WriteAccess
+ * @{
+ */
+
+#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
+#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
+#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
+ ((ACCESS) == IWDG_WriteAccess_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_prescaler
+ * @{
+ */
+
+#define IWDG_Prescaler_4 ((uint8_t)0x00)
+#define IWDG_Prescaler_8 ((uint8_t)0x01)
+#define IWDG_Prescaler_16 ((uint8_t)0x02)
+#define IWDG_Prescaler_32 ((uint8_t)0x03)
+#define IWDG_Prescaler_64 ((uint8_t)0x04)
+#define IWDG_Prescaler_128 ((uint8_t)0x05)
+#define IWDG_Prescaler_256 ((uint8_t)0x06)
+#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
+ ((PRESCALER) == IWDG_Prescaler_8) || \
+ ((PRESCALER) == IWDG_Prescaler_16) || \
+ ((PRESCALER) == IWDG_Prescaler_32) || \
+ ((PRESCALER) == IWDG_Prescaler_64) || \
+ ((PRESCALER) == IWDG_Prescaler_128)|| \
+ ((PRESCALER) == IWDG_Prescaler_256))
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Flag
+ * @{
+ */
+
+#define IWDG_FLAG_PVU ((uint16_t)0x0001)
+#define IWDG_FLAG_RVU ((uint16_t)0x0002)
+#define IWDG_FLAG_WVU ((uint16_t)0x0002)
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU) || \
+ ((FLAG) == IWDG_FLAG_WVU))
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Reload_Value
+ * @{
+ */
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_CounterWindow_Value
+ * @{
+ */
+#define IS_IWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0xFFF)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* Prescaler and Counter configuration functions ******************************/
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
+void IWDG_SetReload(uint16_t Reload);
+void IWDG_ReloadCounter(void);
+void IWDG_SetWindowValue(uint16_t WindowValue);
+
+/* IWDG activation function ***************************************************/
+void IWDG_Enable(void);
+
+/* Flag management function ***************************************************/
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F30x_IWDG_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_misc.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,240 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_misc.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file provides all the miscellaneous firmware functions (add-on
+ * to CMSIS functions).
+ *
+ @verbatim
+
+ ===============================================================================
+ ##### How to configure Interrupts using driver #####
+ ===============================================================================
+ [..] This section provide functions allowing to configure the NVIC interrupts
+ (IRQ). The Cortex-M4 exceptions are managed by CMSIS functions.
+ (#) Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig()
+ function according to the following table.
+ The table below gives the allowed values of the pre-emption priority
+ and subpriority according to the Priority Grouping configuration
+ performed by NVIC_PriorityGroupConfig function.
+
+ (#) Enable and Configure the priority of the selected IRQ Channels.
+ [..]
+ (@) When the NVIC_PriorityGroup_0 is selected, it will no any nested interrupt,
+ the IRQ priority will be managed only by subpriority.
+ The sub-priority is only used to sort pending exception priorities,
+ and does not affect active exceptions.
+ (@) Lower priority values gives higher priority.
+ (@) Priority Order:
+ (#@) Lowest Preemption priority.
+ (#@) Lowest Subpriority.
+ (#@) Lowest hardware priority (IRQn position).
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_misc.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup MISC
+ * @brief MISC driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup MISC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Configures the priority grouping: pre-emption priority and subpriority.
+ * @param NVIC_PriorityGroup: specifies the priority grouping bits length.
+ * This parameter can be one of the following values:
+ * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority.
+ * 4 bits for subpriority.
+ * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority.
+ * 3 bits for subpriority.
+ * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority.
+ * 2 bits for subpriority.
+ * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority.
+ * 1 bits for subpriority.
+ * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority.
+ * 0 bits for subpriority.
+ * @note When NVIC_PriorityGroup_0 is selected, it will no be any nested
+ * interrupt. This interrupts priority is managed only with subpriority.
+ * @retval None
+ */
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
+
+ /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
+ SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
+}
+
+/**
+ * @brief Initializes the NVIC peripheral according to the specified
+ * parameters in the NVIC_InitStruct.
+ * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+ * function should be called before.
+ * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
+ * the configuration information for the specified NVIC peripheral.
+ * @retval None
+ */
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
+{
+ uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
+
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
+ assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
+
+ if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+ {
+ /* Compute the Corresponding IRQ Priority --------------------------------*/
+ tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
+ tmppre = (0x4 - tmppriority);
+ tmpsub = tmpsub >> tmppriority;
+
+ tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
+ tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
+ tmppriority = tmppriority << 0x04;
+
+ NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
+
+ /* Enable the Selected IRQ Channels --------------------------------------*/
+ NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+ (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+ }
+ else
+ {
+ /* Disable the Selected IRQ Channels -------------------------------------*/
+ NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+ (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+ }
+}
+
+/**
+ * @brief Sets the vector table location and Offset.
+ * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
+ * This parameter can be one of the following values:
+ * @arg NVIC_VectTab_RAM
+ * @arg NVIC_VectTab_FLASH
+ * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200.
+ * @retval None
+ */
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
+ assert_param(IS_NVIC_OFFSET(Offset));
+
+ SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
+}
+
+/**
+ * @brief Selects the condition for the system to enter low power mode.
+ * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
+ * This parameter can be one of the following values:
+ * @arg NVIC_LP_SEVONPEND
+ * @arg NVIC_LP_SLEEPDEEP
+ * @arg NVIC_LP_SLEEPONEXIT
+ * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_LP(LowPowerMode));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ SCB->SCR |= LowPowerMode;
+ }
+ else
+ {
+ SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
+ }
+}
+
+/**
+ * @brief Configures the SysTick clock source.
+ * @param SysTick_CLKSource: specifies the SysTick clock source.
+ * This parameter can be one of the following values:
+ * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
+ * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
+ * @retval None
+ */
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
+ if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
+ {
+ SysTick->CTRL |= SysTick_CLKSource_HCLK;
+ }
+ else
+ {
+ SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_misc.h Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,214 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_misc.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the miscellaneous
+ * firmware library functions (add-on to CMSIS functions).
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_MISC_H
+#define __STM32F30x_MISC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup MISC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief NVIC Init Structure definition
+ */
+
+typedef struct
+{
+ uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
+ This parameter can be a value of @ref IRQn_Type (For
+ the complete STM32 Devices IRQ Channels list, please
+ refer to stm32f30x.h file) */
+
+ uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
+ specified in NVIC_IRQChannel. This parameter can be a value
+ between 0 and 15.
+ A lower priority value indicates a higher priority */
+
+
+ uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
+ in NVIC_IRQChannel. This parameter can be a value
+ between 0 and 15.
+ A lower priority value indicates a higher priority */
+
+ FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
+ will be enabled or disabled.
+ This parameter can be set either to ENABLE or DISABLE */
+} NVIC_InitTypeDef;
+
+/**
+ *
+@verbatim
+ The table below gives the allowed values of the pre-emption priority and subpriority according
+ to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
+ ============================================================================================================================
+ NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
+ ============================================================================================================================
+ NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
+ | | | 4 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
+ | | | 3 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
+ | | | 2 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
+ | | | 1 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
+ | | | 0 bits for subpriority
+ ============================================================================================================================
+@endverbatim
+*/
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup MISC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup MISC_Vector_Table_Base
+ * @{
+ */
+
+#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
+#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
+ ((VECTTAB) == NVIC_VectTab_FLASH))
+/**
+ * @}
+ */
+
+/** @defgroup MISC_System_Low_Power
+ * @{
+ */
+
+#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
+ ((LP) == NVIC_LP_SLEEPDEEP) || \
+ ((LP) == NVIC_LP_SLEEPONEXIT))
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Preemption_Priority_Group
+ * @{
+ */
+
+#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
+ 4 bits for subpriority */
+#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
+ 3 bits for subpriority */
+#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
+ 2 bits for subpriority */
+#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
+ 1 bits for subpriority */
+#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
+ 0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
+ ((GROUP) == NVIC_PriorityGroup_1) || \
+ ((GROUP) == NVIC_PriorityGroup_2) || \
+ ((GROUP) == NVIC_PriorityGroup_3) || \
+ ((GROUP) == NVIC_PriorityGroup_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_SysTick_clock_source
+ */
+
+#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
+ ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F30x_MISC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_opamp.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,585 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_opamp.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the operational amplifiers (OPAMP1,...OPAMP4) peripheral:
+ * + OPAMP Configuration
+ * + OPAMP calibration
+ *
+ @verbatim
+
+ ==============================================================================
+ ##### OPAMP Peripheral Features #####
+ ==============================================================================
+
+ [..]
+ The device integrates 4 operational amplifiers OPAMP1, OPAMP2, OPAMP3 and OPAMP4:
+
+ (+) The OPAMPs non inverting input can be selected among the list shown by
+ table below.
+
+ (+) The OPAMPs inverting input can be selected among the list shown by
+ table below.
+
+ (+) The OPAMPs outputs can be internally connected to the inverting input
+ (follower mode)
+ (+) The OPAMPs outputs can be internally connected to resistor feedback
+ output (Programmable Gain Amplifier mode)
+
+ (+) The OPAMPs outputs can be internally connected to ADC
+
+ (+) The OPAMPs can be calibrated to compensate the offset compensation
+
+ (+) Timer-controlled Mux for automatic switch of inverting and
+ non-inverting input
+
+ OPAMPs inverting/non-inverting inputs:
+ +--------------------------------------------------------------+
+ | | | OPAMP1 | OPAMP2 | OPAMP3 | OPAMP4 |
+ |-----------------|--------|--------|--------|--------|--------|
+ | | PGA | OK | OK | OK | OK |
+ | Inverting Input | Vout | OK | OK | OK | OK |
+ | | IO1 | PC5 | PC5 | PB10 | PB10 |
+ | | IO2 | PA3 | PA5 | PB2 | PD8 |
+ |-----------------|--------|--------|--------|--------|--------|
+ | | IO1 | PA7 | PD14 | PB13 | PD11 |
+ | Non Inverting | IO2 | PA5 | PB14 | PA5 | PB11 |
+ | Input | IO3 | PA3 | PB0 | PA1 | PA4 |
+ | | IO4 | PA1 | PA7 | PB0 | PB13 |
+ +--------------------------------------------------------------+
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver provides functions to configure and program the OPAMP
+ of all STM32F30x devices.
+
+ To use the OPAMP, perform the following steps:
+
+ (#) Enable the SYSCFG APB clock to get write access to OPAMP
+ register using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+
+ (#) Configure the OPAMP input in analog mode using GPIO_Init()
+
+ (#) Configure the OPAMP using OPAMP_Init() function:
+ (++) Select the inverting input
+ (++) Select the non-inverting inverting input
+
+ (#) Enable the OPAMP using OPAMP_Cmd() function
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_opamp.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup OPAMP
+ * @brief OPAMP driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define OPAMP_CSR_DEFAULT_MASK ((uint32_t)0xFFFFFF93)
+#define OPAMP_CSR_TIMERMUX_MASK ((uint32_t)0xFFFFF8FF)
+#define OPAMP_CSR_TRIMMING_MASK ((uint32_t)0x0000001F)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup OPAMP_Private_Functions
+ * @{
+ */
+
+/** @defgroup OPAMP_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes OPAMP peripheral registers to their default reset values.
+ * @note Deinitialization can't be performed if the OPAMP configuration is locked.
+ * To unlock the configuration, perform a system reset.
+ * @param OPAMP_Selection: the selected OPAMP.
+ * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+ * to select the OPAMP peripheral.
+ * @param None
+ * @retval None
+ */
+void OPAMP_DeInit(uint32_t OPAMP_Selection)
+{
+ /*!< Set OPAMP_CSR register to reset value */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = ((uint32_t)0x00000000);
+}
+
+/**
+ * @brief Initializes the OPAMP peripheral according to the specified parameters
+ * in OPAMP_InitStruct
+ * @note If the selected OPAMP is locked, initialization can't be performed.
+ * To unlock the configuration, perform a system reset.
+ * @param OPAMP_Selection: the selected OPAMP.
+ * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+ * to select the OPAMP peripheral.
+ * @param OPAMP_InitStruct: pointer to an OPAMP_InitTypeDef structure that contains
+ * the configuration information for the specified OPAMP peripheral.
+ * - OPAMP_InvertingInput specifies the inverting input of OPAMP
+ * - OPAMP_NonInvertingInput specifies the non inverting input of OPAMP
+ * @retval None
+ */
+void OPAMP_Init(uint32_t OPAMP_Selection, OPAMP_InitTypeDef* OPAMP_InitStruct)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+ assert_param(IS_OPAMP_INVERTING_INPUT(OPAMP_InitStruct->OPAMP_InvertingInput));
+ assert_param(IS_OPAMP_NONINVERTING_INPUT(OPAMP_InitStruct->OPAMP_NonInvertingInput));
+
+ /*!< Get the OPAMPx_CSR register value */
+ tmpreg = *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection);
+
+ /*!< Clear the inverting and non inverting bits selection bits */
+ tmpreg &= (uint32_t) (OPAMP_CSR_DEFAULT_MASK);
+
+ /*!< Configure OPAMP: inverting and non inverting inputs */
+ tmpreg |= (uint32_t)(OPAMP_InitStruct->OPAMP_InvertingInput | OPAMP_InitStruct->OPAMP_NonInvertingInput);
+
+ /*!< Write to OPAMPx_CSR register */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = tmpreg;
+}
+
+/**
+ * @brief Fills each OPAMP_InitStruct member with its default value.
+ * @param OPAMP_InitStruct: pointer to an OPAMP_InitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void OPAMP_StructInit(OPAMP_InitTypeDef* OPAMP_InitStruct)
+{
+ OPAMP_InitStruct->OPAMP_NonInvertingInput = OPAMP_NonInvertingInput_IO1;
+ OPAMP_InitStruct->OPAMP_InvertingInput = OPAMP_InvertingInput_IO1;
+}
+
+/**
+ * @brief Configure the feedback resistor gain.
+ * @note If the selected OPAMP is locked, gain configuration can't be performed.
+ * To unlock the configuration, perform a system reset.
+ * @param OPAMP_Selection: the selected OPAMP.
+ * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+ * to select the OPAMP peripheral.
+ * @param NewState: new state of the OPAMP peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void OPAMP_PGAConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_PGAGain, uint32_t OPAMP_PGAConnect)
+{
+ /* Check the parameters */
+ assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+ assert_param(IS_OPAMP_PGAGAIN(OPAMP_PGAGain));
+ assert_param(IS_OPAMP_PGACONNECT(OPAMP_PGAConnect));
+
+ /* Reset the configuration bits */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_PGGAIN);
+
+ /* Set the new configuration */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_PGAGain | OPAMP_PGAConnect);
+}
+
+/**
+ * @brief Configure the OPAMP's internal reference.
+ * @note This feature is used when calibration enabled or OPAMP's reference
+ * connected to the non inverting input.
+ * @note If the selected OPAMP is locked, Vref configuration can't be performed.
+ * To unlock the configuration, perform a system reset.
+ * @param OPAMP_Selection: the selected OPAMP.
+ * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+ * to select the OPAMP peripheral.
+ * @param OPAMP_Vref: This parameter can be:
+ * OPAMP_Vref_3VDDA: OPMAP Vref = 3.3% VDDA
+ * OPAMP_Vref_10VDDA: OPMAP Vref = 10% VDDA
+ * OPAMP_Vref_50VDDA: OPMAP Vref = 50% VDDA
+ * OPAMP_Vref_90VDDA: OPMAP Vref = 90% VDDA
+ * @retval None
+ */
+void OPAMP_VrefConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Vref)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+ assert_param(IS_OPAMP_VREF(OPAMP_Vref));
+
+ /*!< Get the OPAMPx_CSR register value */
+ tmpreg = *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection);
+
+ /*!< Clear the CALSEL bits */
+ tmpreg &= (uint32_t) (~OPAMP_CSR_CALSEL);
+
+ /*!< Configure OPAMP reference */
+ tmpreg |= (uint32_t)(OPAMP_Vref);
+
+ /*!< Write to OPAMPx_CSR register */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = tmpreg;
+}
+
+/**
+ * @brief Connnect the internal reference to the OPAMP's non inverting input.
+ * @note If the selected OPAMP is locked, Vref configuration can't be performed.
+ * To unlock the configuration, perform a system reset.
+ * @param OPAMP_Selection: the selected OPAMP.
+ * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+ * to select the OPAMP peripheral.
+ * @param NewState: new state of the OPAMP peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void OPAMP_VrefConnectNonInvertingInput(uint32_t OPAMP_Selection, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Connnect the internal reference to the OPAMP's non inverting input */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_FORCEVP);
+ }
+ else
+ {
+ /* Disconnnect the internal reference to the OPAMP's non inverting input */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_FORCEVP);
+ }
+}
+
+/**
+ * @brief Enables or disables connecting the OPAMP's internal reference to ADC.
+ * @note If the selected OPAMP is locked, Vref connection can't be performed.
+ * To unlock the configuration, perform a system reset.
+ * @param NewState: new state of the Vrefint output.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void OPAMP_VrefConnectADCCmd(uint32_t OPAMP_Selection, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable output internal reference */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_TSTREF);
+ }
+ else
+ {
+ /* Disable output internal reference */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_TSTREF);
+ }
+}
+
+/**
+ * @brief Configure the OPAMP peripheral (secondary inputs) for timer-controlled
+ * mux mode according to the specified parameters in OPAMP_InitStruct.
+ * @note If the selected OPAMP is locked, timer-controlled mux configuration
+ * can't be performed.
+ * To unlock the configuration, perform a system reset.
+ * @param OPAMP_Selection: the selected OPAMP.
+ * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+ * to select the OPAMP peripheral.
+ * @param OPAMP_InitStruct: pointer to an OPAMP_InitTypeDef structure that contains
+ * the configuration information for the specified OPAMP peripheral.
+ * - OPAMP_InvertingInput specifies the inverting input of OPAMP
+ * - OPAMP_NonInvertingInput specifies the non inverting input of OPAMP
+ * @note PGA and Vout can't be selected as seconadry inverting input.
+ * @retval None
+ */
+void OPAMP_TimerControlledMuxConfig(uint32_t OPAMP_Selection, OPAMP_InitTypeDef* OPAMP_InitStruct)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+ assert_param(IS_OPAMP_SECONDARY_INVINPUT(OPAMP_InitStruct->OPAMP_InvertingInput));
+ assert_param(IS_OPAMP_NONINVERTING_INPUT(OPAMP_InitStruct->OPAMP_NonInvertingInput));
+
+ /*!< Get the OPAMPx_CSR register value */
+ tmpreg = *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection);
+
+ /*!< Clear the secondary inverting bit, secondary non inverting bit and TCMEN bits */
+ tmpreg &= (uint32_t) (OPAMP_CSR_TIMERMUX_MASK);
+
+ /*!< Configure OPAMP: secondary inverting and non inverting inputs */
+ tmpreg |= (uint32_t)((uint32_t)(OPAMP_InitStruct->OPAMP_InvertingInput<<3) | (uint32_t)(OPAMP_InitStruct->OPAMP_NonInvertingInput<<7));
+
+ /*!< Write to OPAMPx_CSR register */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = tmpreg;
+}
+
+/**
+ * @brief Enable or disable the timer-controlled mux mode.
+ * @note If the selected OPAMP is locked, enable/disable can't be performed.
+ * To unlock the configuration, perform a system reset.
+ * @param OPAMP_Selection: the selected OPAMP.
+ * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+ * to select the OPAMP peripheral.
+ * @param NewState: new state of the OPAMP peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void OPAMP_TimerControlledMuxCmd(uint32_t OPAMP_Selection, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the timer-controlled Mux mode */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_TCMEN);
+ }
+ else
+ {
+ /* Disable the timer-controlled Mux mode */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_TCMEN);
+ }
+}
+
+/**
+ * @brief Enable or disable the OPAMP peripheral.
+ * @note If the selected OPAMP is locked, enable/disable can't be performed.
+ * To unlock the configuration, perform a system reset.
+ * @param OPAMP_Selection: the selected OPAMP.
+ * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+ * to select the OPAMP peripheral.
+ * @param NewState: new state of the OPAMP peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void OPAMP_Cmd(uint32_t OPAMP_Selection, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected OPAMPx peripheral */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_OPAMPxEN);
+ }
+ else
+ {
+ /* Disable the selected OPAMPx peripheral */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_OPAMPxEN);
+ }
+}
+
+/**
+ * @brief Return the output level (high or low) during calibration of the selected OPAMP.
+ * @param OPAMP_Selection: the selected OPAMP.
+ * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+ * to select the OPAMP peripheral.
+ * - OPAMP output is low when the non-inverting input is at a lower
+ * voltage than the inverting input
+ * - OPAMP output is high when the non-inverting input is at a higher
+ * voltage than the inverting input
+ * @note OPAMP ouput level is provided only during calibration phase.
+ * @retval Returns the selected OPAMP output level: low or high.
+ *
+ */
+uint32_t OPAMP_GetOutputLevel(uint32_t OPAMP_Selection)
+{
+ uint32_t opampout = 0x0;
+
+ /* Check the parameters */
+ assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+
+ /* Check if selected OPAMP output is high */
+ if ((*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) & (OPAMP_CSR_OUTCAL)) != 0)
+ {
+ opampout = OPAMP_OutputLevel_High;
+ }
+ else
+ {
+ opampout = OPAMP_OutputLevel_Low;
+ }
+
+ /* Return the OPAMP output level */
+ return (uint32_t)(opampout);
+}
+
+/**
+ * @brief Select the trimming mode.
+ * @param OffsetTrimming: the selected offset trimming mode.
+ * This parameter can be one of the following values:
+ * @arg OPAMP_Trimming_Factory: factory trimming values are used for offset
+ * calibration
+ * @arg OPAMP_Trimming_User: user trimming values are used for offset
+ * calibration
+ * @note When OffsetTrimming_User is selected, use OPAMP_OffsetTrimConfig()
+ * function or OPAMP_OffsetTrimLowPowerConfig() function to adjust
+ * trimming value.
+ * @retval None
+ */
+void OPAMP_OffsetTrimModeSelect(uint32_t OPAMP_Selection, uint32_t OPAMP_Trimming)
+{
+ /* Check the parameters */
+ assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+ assert_param(IS_OPAMP_TRIMMING(OPAMP_Trimming));
+
+ /* Reset USERTRIM bit */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (~(uint32_t) (OPAMP_CSR_USERTRIM));
+
+ /* Select trimming mode */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= OPAMP_Trimming;
+}
+
+/**
+ * @brief Configure the trimming value of the OPAMP.
+ * @param OPAMP_Selection: the selected OPAMP.
+ * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+ * to select the OPAMP peripheral.
+ * @param OPAMP_Input: the selected OPAMP input.
+ * This parameter can be one of the following values:
+ * @arg OPAMP_Input_Inverting: Inverting input is selected to configure the trimming value
+ * @arg OPAMP_Input_NonInverting: Non inverting input is selected to configure the trimming value
+ * @param OPAMP_TrimValue: the trimming value. This parameter can be any value lower
+ * or equal to 0x0000001F.
+ * @retval None
+ */
+void OPAMP_OffsetTrimConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+ assert_param(IS_OPAMP_INPUT(OPAMP_Input));
+ assert_param(IS_OPAMP_TRIMMINGVALUE(OPAMP_TrimValue));
+
+ /*!< Get the OPAMPx_CSR register value */
+ tmpreg = *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection);
+
+ /*!< Clear the trimming bits */
+ tmpreg &= ((uint32_t)~(OPAMP_CSR_TRIMMING_MASK<<OPAMP_Input));
+
+ /*!< Configure the new trimming value */
+ tmpreg |= (uint32_t)(OPAMP_TrimValue<<OPAMP_Input);
+
+ /*!< Write to OPAMPx_CSR register */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = tmpreg;
+}
+
+/**
+ * @brief Start or stop the calibration of selected OPAMP peripheral.
+ * @note If the selected OPAMP is locked, start/stop can't be performed.
+ * To unlock the configuration, perform a system reset.
+ * @param OPAMP_Selection: the selected OPAMP.
+ * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+ * to select the OPAMP peripheral.
+ * @param NewState: new state of the OPAMP peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void OPAMP_StartCalibration(uint32_t OPAMP_Selection, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Start the OPAMPx calibration */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_CALON);
+ }
+ else
+ {
+ /* Stop the OPAMPx calibration */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_CALON);
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_Group2 OPAMP configuration locking function
+ * @brief OPAMP1,...OPAMP4 configuration locking function
+ * OPAMP1,...OPAMP4 configuration can be locked each separately.
+ * Unlocking is performed by system reset.
+ *
+@verbatim
+ ===============================================================================
+ ##### Configuration Lock function #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Lock the selected OPAMP configuration.
+ * @note Locking the configuration means that all control bits are read-only.
+ * To unlock the OPAMP configuration, perform a system reset.
+ * @param OPAMP_Selection: the selected OPAMP.
+ * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+ * to select the OPAMP peripheral.
+ * @retval None
+ */
+void OPAMP_LockConfig(uint32_t OPAMP_Selection)
+{
+ /* Check the parameter */
+ assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+
+ /* Set the lock bit corresponding to selected OPAMP */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_LOCK);
+}
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_opamp.h Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,287 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_opamp.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the operational
+ * amplifiers (OPAMP) firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_OPAMP_H
+#define __STM32F30x_OPAMP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup OPAMP
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief OPAMP Init structure definition
+ */
+
+typedef struct
+{
+
+ uint32_t OPAMP_InvertingInput; /*!< Selects the inverting input of the operational amplifier.
+ This parameter can be a value of @ref OPAMP_InvertingInput */
+
+ uint32_t OPAMP_NonInvertingInput; /*!< Selects the non inverting input of the operational amplifier.
+ This parameter can be a value of @ref OPAMP_NonInvertingInput */
+
+}OPAMP_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup OPAMP_Exported_Constants
+ * @{
+ */
+
+/** @defgroup OPAMP_Selection
+ * @{
+ */
+
+#define OPAMP_Selection_OPAMP1 ((uint32_t)0x00000000) /*!< OPAMP1 Selection */
+#define OPAMP_Selection_OPAMP2 ((uint32_t)0x00000004) /*!< OPAMP2 Selection */
+#define OPAMP_Selection_OPAMP3 ((uint32_t)0x00000008) /*!< OPAMP3 Selection */
+#define OPAMP_Selection_OPAMP4 ((uint32_t)0x0000000C) /*!< OPAMP4 Selection */
+
+#define IS_OPAMP_ALL_PERIPH(PERIPH) (((PERIPH) == OPAMP_Selection_OPAMP1) || \
+ ((PERIPH) == OPAMP_Selection_OPAMP2) || \
+ ((PERIPH) == OPAMP_Selection_OPAMP3) || \
+ ((PERIPH) == OPAMP_Selection_OPAMP4))
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_InvertingInput
+ * @{
+ */
+
+#define OPAMP_InvertingInput_IO1 ((uint32_t)0x00000000) /*!< IO1 (PC5 for OPAMP1 and OPAMP2, PB10 for OPAMP3 and OPAMP4)
+ connected to OPAMPx inverting input */
+#define OPAMP_InvertingInput_IO2 OPAMP_CSR_VMSEL_0 /*!< IO2 (PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PD8 for OPAMP4)
+ connected to OPAMPx inverting input */
+#define OPAMP_InvertingInput_PGA OPAMP_CSR_VMSEL_1 /*!< Resistor feedback output connected to OPAMPx inverting input (PGA mode) */
+#define OPAMP_InvertingInput_Vout OPAMP_CSR_VMSEL /*!< Vout connected to OPAMPx inverting input (follower mode) */
+
+#define IS_OPAMP_INVERTING_INPUT(INPUT) (((INPUT) == OPAMP_InvertingInput_IO1) || \
+ ((INPUT) == OPAMP_InvertingInput_IO2) || \
+ ((INPUT) == OPAMP_InvertingInput_PGA) || \
+ ((INPUT) == OPAMP_InvertingInput_Vout))
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_NonInvertingInput
+ * @{
+ */
+
+#define OPAMP_NonInvertingInput_IO1 ((uint32_t)0x00000000) /*!< IO1 (PA7 for OPAMP1, PD14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4)
+ connected to OPAMPx non inverting input */
+#define OPAMP_NonInvertingInput_IO2 OPAMP_CSR_VPSEL_0 /*!< IO2 (PA5 for OPAMP1, PB14 for OPAMP2, PA5 for OPAMP3, PB11 for OPAMP4)
+ connected to OPAMPx non inverting input */
+#define OPAMP_NonInvertingInput_IO3 OPAMP_CSR_VPSEL_1 /*!< IO3 (PA3 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PA4 for OPAMP4)
+ connected to OPAMPx non inverting input */
+#define OPAMP_NonInvertingInput_IO4 OPAMP_CSR_VPSEL /*!< IO4 (PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4)
+ connected to OPAMPx non inverting input */
+
+#define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NonInvertingInput_IO1) || \
+ ((INPUT) == OPAMP_NonInvertingInput_IO2) || \
+ ((INPUT) == OPAMP_NonInvertingInput_IO3) || \
+ ((INPUT) == OPAMP_NonInvertingInput_IO4))
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_PGAGain_Config
+ * @{
+ */
+
+#define OPAMP_OPAMP_PGAGain_2 ((uint32_t)0x00000000)
+#define OPAMP_OPAMP_PGAGain_4 OPAMP_CSR_PGGAIN_0
+#define OPAMP_OPAMP_PGAGain_8 OPAMP_CSR_PGGAIN_1
+#define OPAMP_OPAMP_PGAGain_16 ((uint32_t)0x0000C000)
+
+#define IS_OPAMP_PGAGAIN(GAIN) (((GAIN) == OPAMP_OPAMP_PGAGain_2) || \
+ ((GAIN) == OPAMP_OPAMP_PGAGain_4) || \
+ ((GAIN) == OPAMP_OPAMP_PGAGain_8) || \
+ ((GAIN) == OPAMP_OPAMP_PGAGain_16))
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_PGAConnect_Config
+ * @{
+ */
+
+#define OPAMP_PGAConnect_No ((uint32_t)0x00000000)
+#define OPAMP_PGAConnect_IO1 OPAMP_CSR_PGGAIN_3
+#define OPAMP_PGAConnect_IO2 ((uint32_t)0x00030000)
+
+#define IS_OPAMP_PGACONNECT(CONNECT) (((CONNECT) == OPAMP_PGAConnect_No) || \
+ ((CONNECT) == OPAMP_PGAConnect_IO1) || \
+ ((CONNECT) == OPAMP_PGAConnect_IO2))
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_SecondaryInvertingInput
+ * @{
+ */
+
+#define IS_OPAMP_SECONDARY_INVINPUT(INVINPUT) (((INVINPUT) == OPAMP_InvertingInput_IO1) || \
+ ((INVINPUT) == OPAMP_InvertingInput_IO2))
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_Input
+ * @{
+ */
+
+#define OPAMP_Input_Inverting ((uint32_t)0x00000018) /*!< Inverting input */
+#define OPAMP_Input_NonInverting ((uint32_t)0x00000013) /*!< Non inverting input */
+
+#define IS_OPAMP_INPUT(INPUT) (((INPUT) == OPAMP_Input_Inverting) || \
+ ((INPUT) == OPAMP_Input_NonInverting))
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_Vref
+ * @{
+ */
+
+#define OPAMP_Vref_3VDDA ((uint32_t)0x00000000) /*!< OPMAP Vref = 3.3% VDDA */
+#define OPAMP_Vref_10VDDA OPAMP_CSR_CALSEL_0 /*!< OPMAP Vref = 10% VDDA */
+#define OPAMP_Vref_50VDDA OPAMP_CSR_CALSEL_1 /*!< OPMAP Vref = 50% VDDA */
+#define OPAMP_Vref_90VDDA OPAMP_CSR_CALSEL /*!< OPMAP Vref = 90% VDDA */
+
+#define IS_OPAMP_VREF(VREF) (((VREF) == OPAMP_Vref_3VDDA) || \
+ ((VREF) == OPAMP_Vref_10VDDA) || \
+ ((VREF) == OPAMP_Vref_50VDDA) || \
+ ((VREF) == OPAMP_Vref_90VDDA))
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_Trimming
+ */
+
+#define OPAMP_Trimming_Factory ((uint32_t)0x00000000) /*!< Factory trimming */
+#define OPAMP_Trimming_User OPAMP_CSR_USERTRIM /*!< User trimming */
+
+#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_Trimming_Factory) || \
+ ((TRIMMING) == OPAMP_Trimming_User))
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_TrimValue
+ * @{
+ */
+
+#define IS_OPAMP_TRIMMINGVALUE(VALUE) ((VALUE) <= 0x0000001F) /*!< Trimming value */
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_OutputLevel
+ * @{
+ */
+
+#define OPAMP_OutputLevel_High OPAMP_CSR_OUTCAL
+#define OPAMP_OutputLevel_Low ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the OPAMP configuration to the default reset state ***/
+void OPAMP_DeInit(uint32_t OPAMP_Selection);
+
+/* Initialization and Configuration functions *********************************/
+void OPAMP_Init(uint32_t OPAMP_Selection, OPAMP_InitTypeDef* OPAMP_InitStruct);
+void OPAMP_StructInit(OPAMP_InitTypeDef* OPAMP_InitStruct);
+void OPAMP_PGAConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_PGAGain, uint32_t OPAMP_PGAConnect);
+void OPAMP_VrefConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Vref);
+void OPAMP_VrefConnectADCCmd(uint32_t OPAMP_Selection, FunctionalState NewState);
+void OPAMP_TimerControlledMuxConfig(uint32_t OPAMP_Selection, OPAMP_InitTypeDef* OPAMP_InitStruct);
+void OPAMP_TimerControlledMuxCmd(uint32_t OPAMP_Selection, FunctionalState NewState);
+void OPAMP_Cmd(uint32_t OPAMP_Selection, FunctionalState NewState);
+uint32_t OPAMP_GetOutputLevel(uint32_t OPAMP_Selection);
+
+/* Calibration functions ******************************************************/
+void OPAMP_VrefConnectNonInvertingInput(uint32_t OPAMP_Selection, FunctionalState NewState);
+void OPAMP_OffsetTrimModeSelect(uint32_t OPAMP_Selection, uint32_t OPAMP_Trimming);
+void OPAMP_OffsetTrimConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue);
+void OPAMP_StartCalibration(uint32_t OPAMP_Selection, FunctionalState NewState);
+
+/* OPAMP configuration locking function ***************************************/
+void OPAMP_LockConfig(uint32_t OPAMP_Selection);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F30x_OPAMP_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_pwr.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,548 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_pwr.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Power Controller (PWR) peripheral:
+ * + Backup Domain Access
+ * + PVD configuration
+ * + WakeUp pins configuration
+ * + Low Power modes configuration
+ * + Flags management
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_pwr.h"
+#include "stm32f30x_rcc.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup PWR
+ * @brief PWR driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* --------- PWR registers bit address in the alias region ---------- */
+#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
+
+/* --- CR Register ---*/
+
+/* Alias word address of DBP bit */
+#define CR_OFFSET (PWR_OFFSET + 0x00)
+#define DBP_BitNumber 0x08
+#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
+
+/* Alias word address of PVDE bit */
+#define PVDE_BitNumber 0x04
+#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
+
+/* ------------------ PWR registers bit mask ------------------------ */
+
+/* CR register bit mask */
+#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
+#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup PWR_Private_Functions
+ * @{
+ */
+
+/** @defgroup PWR_Group1 Backup Domain Access function
+ * @brief Backup Domain Access function
+ *
+@verbatim
+ ==============================================================================
+ ##### Backup Domain Access function #####
+ ==============================================================================
+
+ [..] After reset, the Backup Domain Registers (RCC BDCR Register, RTC registers
+ and RTC backup registers) are protected against possible stray write accesses.
+ [..] To enable access to Backup domain use the PWR_BackupAccessCmd(ENABLE) function.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the PWR peripheral registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void PWR_DeInit(void)
+{
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
+}
+
+/**
+ * @brief Enables or disables access to the RTC and backup registers.
+ * @note If the HSE divided by 32 is used as the RTC clock, the
+ * Backup Domain Access should be kept enabled.
+ * @param NewState: new state of the access to the RTC and backup registers.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void PWR_BackupAccessCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Group2 PVD configuration functions
+ * @brief PVD configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### PVD configuration functions #####
+ ==============================================================================
+ [..]
+ (+) The PVD is used to monitor the VDD power supply by comparing it to a threshold
+ selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
+ (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the
+ PVD threshold. This event is internally connected to the EXTI line16
+ and can generate an interrupt if enabled through the EXTI registers.
+ (+) The PVD is stopped in Standby mode.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+ * @param PWR_PVDLevel: specifies the PVD detection level
+ * This parameter can be one of the following values:
+ * @arg PWR_PVDLevel_0: PVD detection level set to 2.18V
+ * @arg PWR_PVDLevel_1: PVD detection level set to 2.28V
+ * @arg PWR_PVDLevel_2: PVD detection level set to 2.38V
+ * @arg PWR_PVDLevel_3: PVD detection level set to 2.48V
+ * @arg PWR_PVDLevel_4: PVD detection level set to 2.58V
+ * @arg PWR_PVDLevel_5: PVD detection level set to 2.68V
+ * @arg PWR_PVDLevel_6: PVD detection level set to 2.78V
+ * @arg PWR_PVDLevel_7: PVD detection level set to 2.88V
+ * @retval None
+ */
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
+
+ tmpreg = PWR->CR;
+
+ /* Clear PLS[7:5] bits */
+ tmpreg &= CR_PLS_MASK;
+
+ /* Set PLS[7:5] bits according to PWR_PVDLevel value */
+ tmpreg |= PWR_PVDLevel;
+
+ /* Store the new value */
+ PWR->CR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the Power Voltage Detector(PVD).
+ * @param NewState: new state of the PVD.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void PWR_PVDCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Group3 WakeUp pins configuration functions
+ * @brief WakeUp pins configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### WakeUp pins configuration functions #####
+ ===============================================================================
+ [..]
+ (+) WakeUp pins are used to wakeup the system from Standby mode. These pins are
+ forced in input pull down configuration and are active on rising edges.
+ (+) There are three WakeUp pins: WakeUp Pin 1 on PA.00, WakeUp Pin 2 on PC.13 and
+ WakeUp Pin 3 on PE.06.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the WakeUp Pin functionality.
+ * @param PWR_WakeUpPin: specifies the WakeUpPin.
+ * This parameter can be: PWR_WakeUpPin_1, PWR_WakeUpPin_2 or PWR_WakeUpPin_3.
+ * @param NewState: new state of the WakeUp Pin functionality.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the EWUPx pin */
+ PWR->CSR |= PWR_WakeUpPin;
+ }
+ else
+ {
+ /* Disable the EWUPx pin */
+ PWR->CSR &= ~PWR_WakeUpPin;
+ }
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup PWR_Group4 Low Power modes configuration functions
+ * @brief Low Power modes configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Low Power modes configuration functions #####
+ ==============================================================================
+
+ [..] The devices feature three low-power modes:
+ (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
+ (+) Stop mode: all clocks are stopped, regulator running, regulator in low power mode
+ (+) Standby mode: VCORE domain powered off
+
+ *** Sleep mode ***
+ ==================
+ [..]
+ (+) Entry:
+ (++) The Sleep mode is entered by executing the WFE() or WFI() instructions.
+ (+) Exit:
+ (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
+ controller (NVIC) can wake up the device from Sleep mode.
+
+ *** Stop mode ***
+ =================
+ [..] In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the HSI,
+ and the HSE RC oscillators are disabled. Internal SRAM and register
+ contents are preserved.
+ The voltage regulator can be configured either in normal or low-power mode.
+
+ (+) Entry:
+ (++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,)
+ function with regulator in LowPower or with Regulator ON.
+ (+) Exit:
+ (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode
+ or any internal IPs (I2C or UASRT) wakeup event.
+
+ *** Standby mode ***
+ ====================
+ [..] The Standby mode allows to achieve the lowest power consumption. It is based
+ on the Cortex-M4 deepsleep mode, with the voltage regulator disabled.
+ The VCORE domain is consequently powered off. The PLL, the HSI, and the HSE
+ oscillator are also switched off. SRAM and register
+ contents are lost except for the Backup domain (RTC registers, RTC backup
+ registers and Standby circuitry).
+
+ [..] The voltage regulator is OFF.
+
+ (+) Entry:
+ (++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function.
+ (+) Exit:
+ (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
+ tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
+
+ *** Auto-wakeup (AWU) from low-power mode ***
+ =============================================
+ [..] The MCU can be woken up from low-power mode by an RTC Alarm event, a tamper
+ event, a time-stamp event, or a comparator event, without depending on an
+ external interrupt (Auto-wakeup mode).
+
+ (+) RTC auto-wakeup (AWU) from the Stop mode
+ (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
+ (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt
+ or Event modes) using the EXTI_Init() function.
+ (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
+ (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
+ and RTC_AlarmCmd() functions.
+ (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
+ is necessary to:
+ (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt
+ or Event modes) using the EXTI_Init() function.
+ (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
+ function.
+ (+++) Configure the RTC to detect the tamper or time stamp event using the
+ RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
+ functions.
+
+ (+) RTC auto-wakeup (AWU) from the Standby mode
+ (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
+ (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function.
+ (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
+ and RTC_AlarmCmd() functions.
+ (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it
+ is necessary to:
+ (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
+ function.
+ (+++) Configure the RTC to detect the tamper or time stamp event using the
+ RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
+ functions.
+
+ (+) Comparator auto-wakeup (AWU) from the Stop mode
+ (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to:
+ (+++) Configure the correspondant comparator EXTI Line to be sensitive to
+ the selected edges (falling, rising or falling and rising)
+ (Interrupt or Event modes) using the EXTI_Init() function.
+ (+++) Configure the comparator to generate the event.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enters Sleep mode.
+ * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
+ * @param PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.
+ * This parameter can be one of the following values:
+ * @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction
+ * @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction
+ * @retval None
+ */
+void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));
+
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+
+ /* Select SLEEP mode entry -------------------------------------------------*/
+ if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __WFE();
+ }
+}
+
+/**
+ * @brief Enters STOP mode.
+ * @note In Stop mode, all I/O pins keep the same state as in Run mode.
+ * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
+ * the HSI RC oscillator is selected as system clock.
+ * @note When the voltage regulator operates in low power mode, an additional
+ * startup delay is incurred when waking up from Stop mode.
+ * By keeping the internal regulator ON during Stop mode, the consumption
+ * is higher although the startup time is reduced.
+ * @param PWR_Regulator: specifies the regulator state in STOP mode.
+ * This parameter can be one of the following values:
+ * @arg PWR_Regulator_ON: STOP mode with regulator ON
+ * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
+ * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
+ * This parameter can be one of the following values:
+ * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
+ * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
+ * @retval None
+ */
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_PWR_REGULATOR(PWR_Regulator));
+ assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
+
+ /* Select the regulator state in STOP mode ---------------------------------*/
+ tmpreg = PWR->CR;
+ /* Clear PDDS and LPDSR bits */
+ tmpreg &= CR_DS_MASK;
+
+ /* Set LPDSR bit according to PWR_Regulator value */
+ tmpreg |= PWR_Regulator;
+
+ /* Store the new value */
+ PWR->CR = tmpreg;
+
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+ /* Select STOP mode entry --------------------------------------------------*/
+ if(PWR_STOPEntry == PWR_STOPEntry_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __WFE();
+ }
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+}
+
+/**
+ * @brief Enters STANDBY mode.
+ * @note In Standby mode, all I/O pins are high impedance except for:
+ * @note Reset pad (still available)
+ * @note RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper,
+ * time-stamp, RTC Alarm out, or RTC clock calibration out.
+ * @note WKUP pin 1 (PA0) and WKUP pin 3 (PE6), if enabled.
+ * @param None
+ * @retval None
+ */
+void PWR_EnterSTANDBYMode(void)
+{
+ /* Clear Wakeup flag */
+ PWR->CR |= PWR_CR_CWUF;
+
+ /* Select STANDBY mode */
+ PWR->CR |= PWR_CR_PDDS;
+
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+/* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM )
+ __force_stores();
+#endif
+ /* Request Wait For Interrupt */
+ __WFI();
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Group5 Flags management functions
+ * @brief Flags management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Flags management functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Checks whether the specified PWR flag is set or not.
+ * @param PWR_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
+ * was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B),
+ * RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
+ * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
+ * resumed from StandBy mode.
+ * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
+ * by the PWR_PVDCmd() function.
+ * @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag. This
+ * flag indicates the state of the internal voltage reference, VREFINT.
+ * @retval The new state of PWR_FLAG (SET or RESET).
+ */
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
+
+ if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the PWR's pending flags.
+ * @param PWR_FLAG: specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg PWR_FLAG_WU: Wake Up flag
+ * @arg PWR_FLAG_SB: StandBy flag
+ * @retval None
+ */
+void PWR_ClearFlag(uint32_t PWR_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
+
+ PWR->CR |= PWR_FLAG << 2;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_pwr.h Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,197 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_pwr.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the PWR firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_PWR_H
+#define __STM32F30x_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup PWR
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Constants
+ * @{
+ */
+
+/** @defgroup PWR_PVD_detection_level
+ * @{
+ */
+
+#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0
+#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1
+#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2
+#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3
+#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4
+#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5
+#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6
+#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7
+
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
+ ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
+ ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
+ ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
+/**
+ * @}
+ */
+
+/** @defgroup PWR_WakeUp_Pins
+ * @{
+ */
+
+#define PWR_WakeUpPin_1 PWR_CSR_EWUP1
+#define PWR_WakeUpPin_2 PWR_CSR_EWUP2
+#define PWR_WakeUpPin_3 PWR_CSR_EWUP3
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || \
+ ((PIN) == PWR_WakeUpPin_2) || \
+ ((PIN) == PWR_WakeUpPin_3))
+/**
+ * @}
+ */
+
+
+/** @defgroup PWR_Regulator_state_is_Sleep_STOP_mode
+ * @{
+ */
+
+#define PWR_Regulator_ON ((uint32_t)0x00000000)
+#define PWR_Regulator_LowPower PWR_CR_LPSDSR
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
+ ((REGULATOR) == PWR_Regulator_LowPower))
+/**
+ * @}
+ */
+
+/** @defgroup PWR_SLEEP_mode_entry
+ * @{
+ */
+
+#define PWR_SLEEPEntry_WFI ((uint8_t)0x01)
+#define PWR_SLEEPEntry_WFE ((uint8_t)0x02)
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_STOP_mode_entry
+ * @{
+ */
+
+#define PWR_STOPEntry_WFI ((uint8_t)0x01)
+#define PWR_STOPEntry_WFE ((uint8_t)0x02)
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Flag
+ * @{
+ */
+
+#define PWR_FLAG_WU PWR_CSR_WUF
+#define PWR_FLAG_SB PWR_CSR_SBF
+#define PWR_FLAG_PVDO PWR_CSR_PVDO
+#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
+
+#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
+ ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY))
+
+#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the PWR configuration to the default reset state ******/
+void PWR_DeInit(void);
+
+/* Backup Domain Access function **********************************************/
+void PWR_BackupAccessCmd(FunctionalState NewState);
+
+/* PVD configuration functions ************************************************/
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
+void PWR_PVDCmd(FunctionalState NewState);
+
+/* WakeUp pins configuration functions ****************************************/
+void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState);
+
+/* Low Power modes configuration functions ************************************/
+void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry);
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+void PWR_EnterSTANDBYMode(void);
+
+/* Flags management functions *************************************************/
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
+void PWR_ClearFlag(uint32_t PWR_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F30x_PWR_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_rcc.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,1961 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_rcc.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Reset and clock control (RCC) peripheral:
+ * + Internal/external clocks, PLL, CSS and MCO configuration
+ * + System, AHB and APB busses clocks configuration
+ * + Peripheral clocks configuration
+ * + Interrupts and flags management
+ *
+ @verbatim
+
+ ===============================================================================
+ ##### RCC specific features #####
+ ===============================================================================
+ [..] After reset the device is running from HSI (8 MHz) with Flash 0 WS,
+ all peripherals are off except internal SRAM, Flash and SWD.
+ (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
+ all peripherals mapped on these busses are running at HSI speed.
+ (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
+ (+) All GPIOs are in input floating state, except the SWD pins which
+ are assigned to be used for debug purpose.
+ [..] Once the device starts from reset, the user application has to:
+ (+) Configure the clock source to be used to drive the System clock
+ (if the application needs higher frequency/performance).
+ (+) Configure the System clock frequency and Flash settings.
+ (+) Configure the AHB and APB busses prescalers.
+ (+) Enable the clock for the peripheral(s) to be used.
+ (+) Configure the clock source(s) for peripherals which clocks are not
+ derived from the System clock (ADC, TIM, I2C, USART, RTC and IWDG).
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_rcc.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup RCC
+ * @brief RCC driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ------------ RCC registers bit address in the alias region ----------- */
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
+
+/* --- CR Register ---*/
+
+/* Alias word address of HSION bit */
+#define CR_OFFSET (RCC_OFFSET + 0x00)
+#define HSION_BitNumber 0x00
+#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
+
+/* Alias word address of PLLON bit */
+#define PLLON_BitNumber 0x18
+#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
+
+/* Alias word address of CSSON bit */
+#define CSSON_BitNumber 0x13
+#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
+
+/* --- CFGR Register ---*/
+/* Alias word address of USBPRE bit */
+#define CFGR_OFFSET (RCC_OFFSET + 0x04)
+#define USBPRE_BitNumber 0x16
+#define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
+/* Alias word address of I2SSRC bit */
+#define I2SSRC_BitNumber 0x17
+#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
+
+/* --- BDCR Register ---*/
+
+/* Alias word address of RTCEN bit */
+#define BDCR_OFFSET (RCC_OFFSET + 0x20)
+#define RTCEN_BitNumber 0x0F
+#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
+
+/* Alias word address of BDRST bit */
+#define BDRST_BitNumber 0x10
+#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
+
+/* --- CSR Register ---*/
+
+/* Alias word address of LSION bit */
+#define CSR_OFFSET (RCC_OFFSET + 0x24)
+#define LSION_BitNumber 0x00
+#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
+
+/* ---------------------- RCC registers bit mask ------------------------ */
+/* RCC Flag Mask */
+#define FLAG_MASK ((uint8_t)0x1F)
+
+/* CFGR register byte 3 (Bits[31:23]) base address */
+#define CFGR_BYTE3_ADDRESS ((uint32_t)0x40021007)
+
+/* CIR register byte 2 (Bits[15:8]) base address */
+#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009)
+
+/* CIR register byte 3 (Bits[23:16]) base address */
+#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A)
+
+/* CR register byte 2 (Bits[23:16]) base address */
+#define CR_BYTE2_ADDRESS ((uint32_t)0x40021002)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+static __I uint16_t ADCPrescTable[16] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256, 0, 0, 0, 0 };
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RCC_Private_Functions
+ * @{
+ */
+
+/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
+ * @brief Internal and external clocks, PLL, CSS and MCO configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Internal-external clocks, PLL, CSS and MCO configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to configure the internal/external
+ clocks, PLL, CSS and MCO.
+ (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly
+ or through the PLL as System clock source.
+ The HSI clock can be used also to clock the USART and I2C peripherals.
+ (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC
+ clock source.
+ (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or
+ through the PLL as System clock source. Can be used also as RTC clock source.
+ (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
+ LSE can be used also to clock the USART peripherals.
+ (#) PLL (clocked by HSI or HSE), for System clock.
+ (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs
+ (HSE used directly or through PLL as System clock source), the System clock
+ is automatically switched to HSI and an interrupt is generated if enabled.
+ The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
+ exception vector.
+ (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE,
+ PLL clock on PA8 pin.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Resets the RCC clock configuration to the default reset state.
+ * @note The default reset state of the clock configuration is given below:
+ * @note HSI ON and used as system clock source
+ * @note HSE and PLL OFF
+ * @note AHB, APB1 and APB2 prescalers set to 1.
+ * @note CSS and MCO OFF
+ * @note All interrupts disabled
+ * @note However, this function doesn't modify the configuration of the
+ * @note Peripheral clocks
+ * @note LSI, LSE and RTC clocks
+ * @param None
+ * @retval None
+ */
+void RCC_DeInit(void)
+{
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */
+ RCC->CFGR &= (uint32_t)0xF8FFC000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+ /* Reset PREDIV1[3:0] and ADCPRE[13:4] bits */
+ RCC->CFGR2 &= (uint32_t)0xFFFFC000;
+
+ /* Reset USARTSW[1:0], I2CSW and TIMSW bits */
+ RCC->CFGR3 &= (uint32_t)0xF00ECCC;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+}
+
+/**
+ * @brief Configures the External High Speed oscillator (HSE).
+ * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
+ * software should wait on HSERDY flag to be set indicating that HSE clock
+ * is stable and can be used to clock the PLL and/or system clock.
+ * @note HSE state can not be changed if it is used directly or through the
+ * PLL as system clock. In this case, you have to select another source
+ * of the system clock then change the HSE state (ex. disable it).
+ * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
+ * @note This function resets the CSSON bit, so if the Clock security system(CSS)
+ * was previously enabled you have to enable it again after calling this
+ * function.
+ * @param RCC_HSE: specifies the new state of the HSE.
+ * This parameter can be one of the following values:
+ * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
+ * 6 HSE oscillator clock cycles.
+ * @arg RCC_HSE_ON: turn ON the HSE oscillator
+ * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
+ * @retval None
+ */
+void RCC_HSEConfig(uint8_t RCC_HSE)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_HSE(RCC_HSE));
+
+ /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
+ *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE_OFF;
+
+ /* Set the new HSE configuration -------------------------------------------*/
+ *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE;
+
+}
+
+/**
+ * @brief Waits for HSE start-up.
+ * @note This function waits on HSERDY flag to be set and return SUCCESS if
+ * this flag is set, otherwise returns ERROR if the timeout is reached
+ * and this flag is not set. The timeout value is defined by the constant
+ * HSE_STARTUP_TIMEOUT in stm32f30x.h file. You can tailor it depending
+ * on the HSE crystal used in your application.
+ * @param None
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: HSE oscillator is stable and ready to use
+ * - ERROR: HSE oscillator not yet ready
+ */
+ErrorStatus RCC_WaitForHSEStartUp(void)
+{
+ __IO uint32_t StartUpCounter = 0;
+ ErrorStatus status = ERROR;
+ FlagStatus HSEStatus = RESET;
+
+ /* Wait till HSE is ready and if timeout is reached exit */
+ do
+ {
+ HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
+ StartUpCounter++;
+ } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
+
+ if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
+ {
+ status = SUCCESS;
+ }
+ else
+ {
+ status = ERROR;
+ }
+ return (status);
+}
+
+/**
+ * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
+ * @note The calibration is used to compensate for the variations in voltage
+ * and temperature that influence the frequency of the internal HSI RC.
+ * Refer to the Application Note AN3300 for more details on how to
+ * calibrate the HSI.
+ * @param HSICalibrationValue: specifies the HSI calibration trimming value.
+ * This parameter must be a number between 0 and 0x1F.
+ * @retval None
+ */
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue));
+
+ tmpreg = RCC->CR;
+
+ /* Clear HSITRIM[4:0] bits */
+ tmpreg &= ~RCC_CR_HSITRIM;
+
+ /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
+ tmpreg |= (uint32_t)HSICalibrationValue << 3;
+
+ /* Store the new value */
+ RCC->CR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the Internal High Speed oscillator (HSI).
+ * @note After enabling the HSI, the application software should wait on
+ * HSIRDY flag to be set indicating that HSI clock is stable and can
+ * be used to clock the PLL and/or system clock.
+ * @note HSI can not be stopped if it is used directly or through the PLL
+ * as system clock. In this case, you have to select another source
+ * of the system clock then stop the HSI.
+ * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
+ * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+ * clock cycles.
+ * @param NewState: new state of the HSI.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_HSICmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Configures the External Low Speed oscillator (LSE).
+ * @note As the LSE is in the Backup domain and write access is denied to this
+ * domain after reset, you have to enable write access using
+ * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE
+ * (to be done once after reset).
+ * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application
+ * software should wait on LSERDY flag to be set indicating that LSE clock
+ * is stable and can be used to clock the RTC.
+ * @param RCC_LSE: specifies the new state of the LSE.
+ * This parameter can be one of the following values:
+ * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
+ * 6 LSE oscillator clock cycles.
+ * @arg RCC_LSE_ON: turn ON the LSE oscillator
+ * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
+ * @retval None
+ */
+void RCC_LSEConfig(uint32_t RCC_LSE)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE(RCC_LSE));
+
+ /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
+ /* Reset LSEON bit */
+ RCC->BDCR &= ~(RCC_BDCR_LSEON);
+
+ /* Reset LSEBYP bit */
+ RCC->BDCR &= ~(RCC_BDCR_LSEBYP);
+
+ /* Configure LSE */
+ RCC->BDCR |= RCC_LSE;
+}
+
+/**
+ * @brief Configures the External Low Speed oscillator (LSE) drive capability.
+ * @param RCC_LSEDrive: specifies the new state of the LSE drive capability.
+ * This parameter can be one of the following values:
+ * @arg RCC_LSEDrive_Low: LSE oscillator low drive capability.
+ * @arg RCC_LSEDrive_MediumLow: LSE oscillator medium low drive capability.
+ * @arg RCC_LSEDrive_MediumHigh: LSE oscillator medium high drive capability.
+ * @arg RCC_LSEDrive_High: LSE oscillator high drive capability.
+ * @retval None
+ */
+void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE_DRIVE(RCC_LSEDrive));
+
+ /* Clear LSEDRV[1:0] bits */
+ RCC->BDCR &= ~(RCC_BDCR_LSEDRV);
+
+ /* Set the LSE Drive */
+ RCC->BDCR |= RCC_LSEDrive;
+}
+
+/**
+ * @brief Enables or disables the Internal Low Speed oscillator (LSI).
+ * @note After enabling the LSI, the application software should wait on
+ * LSIRDY flag to be set indicating that LSI clock is stable and can
+ * be used to clock the IWDG and/or the RTC.
+ * @note LSI can not be disabled if the IWDG is running.
+ * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
+ * clock cycles.
+ * @param NewState: new state of the LSI.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_LSICmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Configures the PLL clock source and multiplication factor.
+ * @note This function must be used only when the PLL is disabled.
+ * @note The minimum input clock frequency for PLL is 2 MHz (when using HSE as
+ * PLL source).
+ * @param RCC_PLLSource: specifies the PLL entry clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as
+ * PLL clock entry
+ * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock source
+ * @param RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock
+ * This parameter can be RCC_PLLMul_x where x:[2,16]
+ *
+ * @retval None
+ */
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
+ assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
+
+ /* Clear PLL Source [16] and Multiplier [21:18] bits */
+ RCC->CFGR &= ~(RCC_CFGR_PLLMULL | RCC_CFGR_PLLSRC);
+
+ /* Set the PLL Source and Multiplier */
+ RCC->CFGR |= (uint32_t)(RCC_PLLSource | RCC_PLLMul);
+}
+
+/**
+ * @brief Enables or disables the PLL.
+ * @note After enabling the PLL, the application software should wait on
+ * PLLRDY flag to be set indicating that PLL clock is stable and can
+ * be used as system clock source.
+ * @note The PLL can not be disabled if it is used as system clock source
+ * @note The PLL is disabled by hardware when entering STOP and STANDBY modes.
+ * @param NewState: new state of the PLL.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_PLLCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Configures the PREDIV1 division factor.
+ * @note This function must be used only when the PLL is disabled.
+ * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
+ * This parameter can be RCC_PREDIV1_Divx where x:[1,16]
+ * @retval None
+ */
+void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));
+
+ tmpreg = RCC->CFGR2;
+ /* Clear PREDIV1[3:0] bits */
+ tmpreg &= ~(RCC_CFGR2_PREDIV1);
+
+ /* Set the PREDIV1 division factor */
+ tmpreg |= RCC_PREDIV1_Div;
+
+ /* Store the new value */
+ RCC->CFGR2 = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the Clock Security System.
+ * @note If a failure is detected on the HSE oscillator clock, this oscillator
+ * is automatically disabled and an interrupt is generated to inform the
+ * software about the failure (Clock Security System Interrupt, CSSI),
+ * allowing the MCU to perform rescue operations. The CSSI is linked to
+ * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
+ * @param NewState: new state of the Clock Security System.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
+}
+
+#ifdef STM32F303xC
+/**
+ * @brief Selects the clock source to output on MCO pin (PA8).
+ * @note PA8 should be configured in alternate function mode.
+ * @param RCC_MCOSource: specifies the clock source to output.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCOSource_NoClock: No clock selected.
+ * @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected.
+ * @arg RCC_MCOSource_LSI: LSI oscillator clock selected.
+ * @arg RCC_MCOSource_LSE: LSE oscillator clock selected.
+ * @arg RCC_MCOSource_SYSCLK: System clock selected.
+ * @arg RCC_MCOSource_HSI: HSI oscillator clock selected.
+ * @arg RCC_MCOSource_HSE: HSE oscillator clock selected.
+ * @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected.
+ * @arg RCC_MCOSource_PLLCLK: PLL clock selected.
+ * @arg RCC_MCOSource_HSI48: HSI48 clock selected.
+ * @retval None
+ */
+void RCC_MCOConfig(uint8_t RCC_MCOSource)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
+
+ /* Get CFGR value */
+ tmpreg = RCC->CFGR;
+ /* Clear MCO[3:0] bits */
+ tmpreg &= ~(RCC_CFGR_MCO | RCC_CFGR_PLLNODIV);
+ /* Set the RCC_MCOSource */
+ tmpreg |= RCC_MCOSource<<24;
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+#else
+
+/**
+ * @brief Selects the clock source to output on MCO pin (PA8) and the corresponding
+ * prescsaler.
+ * @note PA8 should be configured in alternate function mode.
+ * @param RCC_MCOSource: specifies the clock source to output.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCOSource_NoClock: No clock selected.
+ * @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected.
+ * @arg RCC_MCOSource_LSI: LSI oscillator clock selected.
+ * @arg RCC_MCOSource_LSE: LSE oscillator clock selected.
+ * @arg RCC_MCOSource_SYSCLK: System clock selected.
+ * @arg RCC_MCOSource_HSI: HSI oscillator clock selected.
+ * @arg RCC_MCOSource_HSE: HSE oscillator clock selected.
+ * @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected.
+ * @arg RCC_MCOSource_PLLCLK: PLL clock selected.
+ * @arg RCC_MCOSource_HSI48: HSI48 clock selected.
+ * @param RCC_MCOPrescaler: specifies the prescaler on MCO pin.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCOPrescaler_1: MCO clock is divided by 1.
+ * @arg RCC_MCOPrescaler_2: MCO clock is divided by 2.
+ * @arg RCC_MCOPrescaler_4: MCO clock is divided by 4.
+ * @arg RCC_MCOPrescaler_8: MCO clock is divided by 8.
+ * @arg RCC_MCOPrescaler_16: MCO clock is divided by 16.
+ * @arg RCC_MCOPrescaler_32: MCO clock is divided by 32.
+ * @arg RCC_MCOPrescaler_64: MCO clock is divided by 64.
+ * @arg RCC_MCOPrescaler_128: MCO clock is divided by 128.
+ * @retval None
+ */
+void RCC_MCOConfig(uint8_t RCC_MCOSource, uint32_t RCC_MCOPrescaler)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
+ assert_param(IS_RCC_MCO_PRESCALER(RCC_MCOPrescaler));
+
+ /* Get CFGR value */
+ tmpreg = RCC->CFGR;
+ /* Clear MCOPRE[2:0] bits */
+ tmpreg &= ~(RCC_CFGR_MCO_PRE | RCC_CFGR_MCO | RCC_CFGR_PLLNODIV);
+ /* Set the RCC_MCOSource and RCC_MCOPrescaler */
+ tmpreg |= (RCC_MCOPrescaler | RCC_MCOSource<<24);
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+#endif /* STM32F303xC */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Group2 System AHB, APB1 and APB2 busses clocks configuration functions
+ * @brief System, AHB and APB busses clocks configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### System, AHB, APB1 and APB2 busses clocks configuration functions #####
+ ===============================================================================
+ [..] This section provide functions allowing to configure the System, AHB, APB1 and
+ APB2 busses clocks.
+ (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
+ HSE and PLL.
+ The AHB clock (HCLK) is derived from System clock through configurable prescaler
+ and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA and GPIO).
+ APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through
+ configurable prescalers and used to clock the peripherals mapped on these busses.
+ You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.
+
+ (#) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 72 MHz.
+ Depending on the maximum frequency, the FLASH wait states (WS) should be
+ adapted accordingly:
+ +---------------------------------+
+ | Wait states | HCLK clock |
+ | (Latency) | frequency (MHz) |
+ |-------------- |-----------------|
+ |0WS(1CPU cycle)| 0 < HCLK <= 24 |
+ |---------------|-----------------|
+ |1WS(2CPU cycle)|24 < HCLK <=48 |
+ |---------------|-----------------|
+ |2WS(3CPU cycle)|48 < HCLK <= 72 |
+ +---------------------------------+
+
+ (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
+ prefetch is disabled.
+ [..]
+ (@) All the peripheral clocks are derived from the System clock (SYSCLK)
+ except:
+ (+@) The FLASH program/erase clock which is always HSI 8MHz clock.
+ (+@) The USB 48 MHz clock which is derived from the PLL VCO clock.
+ (+@) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE.
+ (+@) The I2C clock which can be derived as well from HSI 8MHz clock.
+ (+@) The ADC clock which is derived from PLL output.
+ (+@) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC
+ (HSE divided by a programmable prescaler). The System clock (SYSCLK)
+ frequency must be higher or equal to the RTC clock frequency.
+ (+@) IWDG clock which is always the LSI clock.
+ [..] It is recommended to use the following software sequences to tune the number
+ of wait states needed to access the Flash memory with the CPU frequency (HCLK).
+ (+) Increasing the CPU frequency
+ (++) Program the Flash Prefetch buffer, using "FLASH_PrefetchBufferCmd(ENABLE)"
+ function
+ (++) Check that Flash Prefetch buffer activation is taken into account by
+ reading FLASH_ACR using the FLASH_GetPrefetchBufferStatus() function
+ (++) Program Flash WS to 1 or 2, using "FLASH_SetLatency()" function
+ (++) Check that the new number of WS is taken into account by reading FLASH_ACR
+ (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
+ (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
+ (++) Check that the new CPU clock source is taken into account by reading
+ the clock source status, using "RCC_GetSYSCLKSource()" function
+ (+) Decreasing the CPU frequency
+ (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
+ (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
+ (++) Check that the new CPU clock source is taken into account by reading
+ the clock source status, using "RCC_GetSYSCLKSource()" function
+ (++) Program the new number of WS, using "FLASH_SetLatency()" function
+ (++) Check that the new number of WS is taken into account by reading FLASH_ACR
+ (++) Disable the Flash Prefetch buffer using "FLASH_PrefetchBufferCmd(DISABLE)"
+ function
+ (++) Check that Flash Prefetch buffer deactivation is taken into account by reading FLASH_ACR
+ using the FLASH_GetPrefetchBufferStatus() function.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the system clock (SYSCLK).
+ * @note The HSI is used (enabled by hardware) as system clock source after
+ * startup from Reset, wake-up from STOP and STANDBY mode, or in case
+ * of failure of the HSE used directly or indirectly as system clock
+ * (if the Clock Security System CSS is enabled).
+ * @note A switch from one clock source to another occurs only if the target
+ * clock source is ready (clock stable after startup delay or PLL locked).
+ * If a clock source which is not yet ready is selected, the switch will
+ * occur when the clock source will be ready.
+ * You can use RCC_GetSYSCLKSource() function to know which clock is
+ * currently used as system clock source.
+ * @param RCC_SYSCLKSource: specifies the clock source used as system clock source
+ * This parameter can be one of the following values:
+ * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source
+ * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source
+ * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
+ * @retval None
+ */
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
+
+ tmpreg = RCC->CFGR;
+
+ /* Clear SW[1:0] bits */
+ tmpreg &= ~RCC_CFGR_SW;
+
+ /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
+ tmpreg |= RCC_SYSCLKSource;
+
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/**
+ * @brief Returns the clock source used as system clock.
+ * @param None
+ * @retval The clock source used as system clock. The returned value can be one
+ * of the following values:
+ * - 0x00: HSI used as system clock
+ * - 0x04: HSE used as system clock
+ * - 0x08: PLL used as system clock
+ */
+uint8_t RCC_GetSYSCLKSource(void)
+{
+ return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
+}
+
+/**
+ * @brief Configures the AHB clock (HCLK).
+ * @note Depending on the device voltage range, the software has to set correctly
+ * these bits to ensure that the system frequency does not exceed the
+ * maximum allowed frequency (for more details refer to section above
+ * "CPU, AHB and APB busses clocks configuration functions").
+ * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
+ * the system clock (SYSCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
+ * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
+ * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
+ * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
+ * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
+ * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
+ * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
+ * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
+ * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
+ * @retval None
+ */
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_HCLK(RCC_SYSCLK));
+
+ tmpreg = RCC->CFGR;
+
+ /* Clear HPRE[3:0] bits */
+ tmpreg &= ~RCC_CFGR_HPRE;
+
+ /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
+ tmpreg |= RCC_SYSCLK;
+
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/**
+ * @brief Configures the Low Speed APB clock (PCLK1).
+ * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
+ * the AHB clock (HCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_HCLK_Div1: APB1 clock = HCLK
+ * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
+ * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
+ * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
+ * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
+ * @retval None
+ */
+void RCC_PCLK1Config(uint32_t RCC_HCLK)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PCLK(RCC_HCLK));
+
+ tmpreg = RCC->CFGR;
+ /* Clear PPRE1[2:0] bits */
+ tmpreg &= ~RCC_CFGR_PPRE1;
+
+ /* Set PPRE1[2:0] bits according to RCC_HCLK value */
+ tmpreg |= RCC_HCLK;
+
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/**
+ * @brief Configures the High Speed APB clock (PCLK2).
+ * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
+ * the AHB clock (HCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_HCLK_Div1: APB2 clock = HCLK
+ * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
+ * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
+ * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
+ * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
+ * @retval None
+ */
+void RCC_PCLK2Config(uint32_t RCC_HCLK)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PCLK(RCC_HCLK));
+
+ tmpreg = RCC->CFGR;
+ /* Clear PPRE2[2:0] bits */
+ tmpreg &= ~RCC_CFGR_PPRE2;
+ /* Set PPRE2[2:0] bits according to RCC_HCLK value */
+ tmpreg |= RCC_HCLK << 3;
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/**
+ * @brief Returns the frequencies of the System, AHB, APB2 and APB1 busses clocks.
+ *
+ * @note This function returns the frequencies of :
+ * System, AHB, APB2 and APB1 busses clocks, ADC1/2/3/4 clocks,
+ * USART1/2/3/4/5 clocks, I2C1/2 clocks and TIM1/8 Clocks.
+ *
+ * @note The frequency returned by this function is not the real frequency
+ * in the chip. It is calculated based on the predefined constant and
+ * the source selected by RCC_SYSCLKConfig().
+ *
+ * @note If SYSCLK source is HSI, function returns constant HSI_VALUE(*)
+ *
+ * @note If SYSCLK source is HSE, function returns constant HSE_VALUE(**)
+ *
+ * @note If SYSCLK source is PLL, function returns constant HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied by the PLL factors.
+ *
+ * @note (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature, refer to RCC_AdjustHSICalibrationValue().
+ *
+ * @note (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * return wrong result.
+ *
+ * @note The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
+ * the clocks frequencies.
+ *
+ * @note This function can be used by the user application to compute the
+ * baudrate for the communication peripherals or configure other parameters.
+ * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
+ * must be called to update the structure's field. Otherwise, any
+ * configuration based on this function will be incorrect.
+ *
+ * @retval None
+ */
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0, presc = 0, pllclk = 0;
+ uint32_t apb2presc = 0, ahbpresc = 0;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock */
+ RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
+ break;
+ case 0x04: /* HSE used as system clock */
+ RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
+ break;
+ case 0x08: /* PLL used as system clock */
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+ pllmull = ( pllmull >> 18) + 2;
+
+ if (pllsource == 0x00)
+ {
+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ pllclk = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ pllclk = (HSE_VALUE / prediv1factor) * pllmull;
+ }
+ RCC_Clocks->SYSCLK_Frequency = pllclk;
+ break;
+ default: /* HSI used as system clock */
+ RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
+ break;
+ }
+ /* Compute HCLK, PCLK clocks frequencies -----------------------------------*/
+ /* Get HCLK prescaler */
+ tmp = RCC->CFGR & RCC_CFGR_HPRE;
+ tmp = tmp >> 4;
+ ahbpresc = APBAHBPrescTable[tmp];
+ /* HCLK clock frequency */
+ RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> ahbpresc;
+
+ /* Get PCLK1 prescaler */
+ tmp = RCC->CFGR & RCC_CFGR_PPRE1;
+ tmp = tmp >> 8;
+ presc = APBAHBPrescTable[tmp];
+ /* PCLK1 clock frequency */
+ RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+
+ /* Get PCLK2 prescaler */
+ tmp = RCC->CFGR & RCC_CFGR_PPRE2;
+ tmp = tmp >> 11;
+ apb2presc = APBAHBPrescTable[tmp];
+ /* PCLK2 clock frequency */
+ RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> apb2presc;
+
+ /* Get ADC12CLK prescaler */
+ tmp = RCC->CFGR2 & RCC_CFGR2_ADCPRE12;
+ tmp = tmp >> 4;
+ presc = ADCPrescTable[tmp & 0x0F];
+ if (((tmp & 0x10) != 0) && (presc != 0))
+ {
+ /* ADC12CLK clock frequency is derived from PLL clock */
+ RCC_Clocks->ADC12CLK_Frequency = pllclk / presc;
+ }
+ else
+ {
+ /* ADC12CLK clock frequency is AHB clock */
+ RCC_Clocks->ADC12CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
+ }
+
+ /* Get ADC34CLK prescaler */
+ tmp = RCC->CFGR2 & RCC_CFGR2_ADCPRE34;
+ tmp = tmp >> 9;
+ presc = ADCPrescTable[tmp & 0x0F];
+ if (((tmp & 0x10) != 0) && (presc != 0))
+ {
+ /* ADC34CLK clock frequency is derived from PLL clock */
+ RCC_Clocks->ADC34CLK_Frequency = pllclk / presc;
+ }
+ else
+ {
+ /* ADC34CLK clock frequency is AHB clock */
+ RCC_Clocks->ADC34CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
+ }
+
+ /* I2C1CLK clock frequency */
+ if((RCC->CFGR3 & RCC_CFGR3_I2C1SW) != RCC_CFGR3_I2C1SW)
+ {
+ /* I2C1 Clock is HSI Osc. */
+ RCC_Clocks->I2C1CLK_Frequency = HSI_VALUE;
+ }
+ else
+ {
+ /* I2C1 Clock is System Clock */
+ RCC_Clocks->I2C1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
+ }
+
+ /* I2C2CLK clock frequency */
+ if((RCC->CFGR3 & RCC_CFGR3_I2C2SW) != RCC_CFGR3_I2C2SW)
+ {
+ /* I2C2 Clock is HSI Osc. */
+ RCC_Clocks->I2C2CLK_Frequency = HSI_VALUE;
+ }
+ else
+ {
+ /* I2C2 Clock is System Clock */
+ RCC_Clocks->I2C2CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
+ }
+
+ /* I2C3CLK clock frequency */
+ if((RCC->CFGR3 & RCC_CFGR3_I2C3SW) != RCC_CFGR3_I2C3SW)
+ {
+ /* I2C3 Clock is HSI Osc. */
+ RCC_Clocks->I2C3CLK_Frequency = HSI_VALUE;
+ }
+ else
+ {
+ /* I2C3 Clock is System Clock */
+ RCC_Clocks->I2C3CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
+ }
+
+ /* TIM1CLK clock frequency */
+ if(((RCC->CFGR3 & RCC_CFGR3_TIM1SW) == RCC_CFGR3_TIM1SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
+ && (apb2presc == ahbpresc))
+ {
+ /* TIM1 Clock is 2 * pllclk */
+ RCC_Clocks->TIM1CLK_Frequency = pllclk * 2;
+ }
+ else
+ {
+ /* TIM1 Clock is APB2 clock. */
+ RCC_Clocks->TIM1CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
+ }
+
+ /* TIM1CLK clock frequency */
+ if(((RCC->CFGR3 & RCC_CFGR3_HRTIM1SW) == RCC_CFGR3_HRTIM1SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
+ && (apb2presc == ahbpresc))
+ {
+ /* HRTIM1 Clock is 2 * pllclk */
+ RCC_Clocks->HRTIM1CLK_Frequency = pllclk * 2;
+ }
+ else
+ {
+ /* HRTIM1 Clock is APB2 clock. */
+ RCC_Clocks->HRTIM1CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
+ }
+
+ /* TIM8CLK clock frequency */
+ if(((RCC->CFGR3 & RCC_CFGR3_TIM8SW) == RCC_CFGR3_TIM8SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
+ && (apb2presc == ahbpresc))
+ {
+ /* TIM8 Clock is 2 * pllclk */
+ RCC_Clocks->TIM8CLK_Frequency = pllclk * 2;
+ }
+ else
+ {
+ /* TIM8 Clock is APB2 clock. */
+ RCC_Clocks->TIM8CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
+ }
+
+ /* TIM15CLK clock frequency */
+ if(((RCC->CFGR3 & RCC_CFGR3_TIM15SW) == RCC_CFGR3_TIM15SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
+ && (apb2presc == ahbpresc))
+ {
+ /* TIM15 Clock is 2 * pllclk */
+ RCC_Clocks->TIM15CLK_Frequency = pllclk * 2;
+ }
+ else
+ {
+ /* TIM15 Clock is APB2 clock. */
+ RCC_Clocks->TIM15CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
+ }
+
+ /* TIM16CLK clock frequency */
+ if(((RCC->CFGR3 & RCC_CFGR3_TIM16SW) == RCC_CFGR3_TIM16SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
+ && (apb2presc == ahbpresc))
+ {
+ /* TIM16 Clock is 2 * pllclk */
+ RCC_Clocks->TIM16CLK_Frequency = pllclk * 2;
+ }
+ else
+ {
+ /* TIM16 Clock is APB2 clock. */
+ RCC_Clocks->TIM16CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
+ }
+
+ /* TIM17CLK clock frequency */
+ if(((RCC->CFGR3 & RCC_CFGR3_TIM17SW) == RCC_CFGR3_TIM17SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
+ && (apb2presc == ahbpresc))
+ {
+ /* TIM17 Clock is 2 * pllclk */
+ RCC_Clocks->TIM17CLK_Frequency = pllclk * 2;
+ }
+ else
+ {
+ /* TIM17 Clock is APB2 clock. */
+ RCC_Clocks->TIM16CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
+ }
+
+ /* USART1CLK clock frequency */
+ if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == 0x0)
+ {
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F301x8) || defined(STM32F302x8)
+ /* USART1 Clock is PCLK1 instead of PCLK2 (limitation described in the
+ STM32F302/01/34 x4/x6/x8 respective erratasheets) */
+ RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->PCLK1_Frequency;
+#else
+ /* USART Clock is PCLK2 */
+ RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
+#endif
+ }
+ else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_0)
+ {
+ /* USART Clock is System Clock */
+ RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
+ }
+ else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_1)
+ {
+ /* USART Clock is LSE Osc. */
+ RCC_Clocks->USART1CLK_Frequency = LSE_VALUE;
+ }
+ else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW)
+ {
+ /* USART Clock is HSI Osc. */
+ RCC_Clocks->USART1CLK_Frequency = HSI_VALUE;
+ }
+
+ /* USART2CLK clock frequency */
+ if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == 0x0)
+ {
+ /* USART Clock is PCLK */
+ RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->PCLK1_Frequency;
+ }
+ else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_0)
+ {
+ /* USART Clock is System Clock */
+ RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
+ }
+ else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_1)
+ {
+ /* USART Clock is LSE Osc. */
+ RCC_Clocks->USART2CLK_Frequency = LSE_VALUE;
+ }
+ else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW)
+ {
+ /* USART Clock is HSI Osc. */
+ RCC_Clocks->USART2CLK_Frequency = HSI_VALUE;
+ }
+
+ /* USART3CLK clock frequency */
+ if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == 0x0)
+ {
+ /* USART Clock is PCLK */
+ RCC_Clocks->USART3CLK_Frequency = RCC_Clocks->PCLK1_Frequency;
+ }
+ else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW_0)
+ {
+ /* USART Clock is System Clock */
+ RCC_Clocks->USART3CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
+ }
+ else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW_1)
+ {
+ /* USART Clock is LSE Osc. */
+ RCC_Clocks->USART3CLK_Frequency = LSE_VALUE;
+ }
+ else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW)
+ {
+ /* USART Clock is HSI Osc. */
+ RCC_Clocks->USART3CLK_Frequency = HSI_VALUE;
+ }
+
+ /* UART4CLK clock frequency */
+ if((RCC->CFGR3 & RCC_CFGR3_UART4SW) == 0x0)
+ {
+ /* USART Clock is PCLK */
+ RCC_Clocks->UART4CLK_Frequency = RCC_Clocks->PCLK1_Frequency;
+ }
+ else if((RCC->CFGR3 & RCC_CFGR3_UART4SW) == RCC_CFGR3_UART4SW_0)
+ {
+ /* USART Clock is System Clock */
+ RCC_Clocks->UART4CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
+ }
+ else if((RCC->CFGR3 & RCC_CFGR3_UART4SW) == RCC_CFGR3_UART4SW_1)
+ {
+ /* USART Clock is LSE Osc. */
+ RCC_Clocks->UART4CLK_Frequency = LSE_VALUE;
+ }
+ else if((RCC->CFGR3 & RCC_CFGR3_UART4SW) == RCC_CFGR3_UART4SW)
+ {
+ /* USART Clock is HSI Osc. */
+ RCC_Clocks->UART4CLK_Frequency = HSI_VALUE;
+ }
+
+ /* UART5CLK clock frequency */
+ if((RCC->CFGR3 & RCC_CFGR3_UART5SW) == 0x0)
+ {
+ /* USART Clock is PCLK */
+ RCC_Clocks->UART5CLK_Frequency = RCC_Clocks->PCLK1_Frequency;
+ }
+ else if((RCC->CFGR3 & RCC_CFGR3_UART5SW) == RCC_CFGR3_UART5SW_0)
+ {
+ /* USART Clock is System Clock */
+ RCC_Clocks->UART5CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
+ }
+ else if((RCC->CFGR3 & RCC_CFGR3_UART5SW) == RCC_CFGR3_UART5SW_1)
+ {
+ /* USART Clock is LSE Osc. */
+ RCC_Clocks->UART5CLK_Frequency = LSE_VALUE;
+ }
+ else if((RCC->CFGR3 & RCC_CFGR3_UART5SW) == RCC_CFGR3_UART5SW)
+ {
+ /* USART Clock is HSI Osc. */
+ RCC_Clocks->UART5CLK_Frequency = HSI_VALUE;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Group3 Peripheral clocks configuration functions
+ * @brief Peripheral clocks configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral clocks configuration functions #####
+ ===============================================================================
+ [..] This section provide functions allowing to configure the Peripheral clocks.
+ (#) The RTC clock which is derived from the LSE, LSI or HSE_Div32
+ (HSE divided by 32).
+ (#) After restart from Reset or wakeup from STANDBY, all peripherals are
+ off except internal SRAM, Flash and SWD. Before to start using
+ a peripheral you have to enable its interface clock. You can do this
+ using RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd()
+ and RCC_APB1PeriphClockCmd() functions.
+ (#) To reset the peripherals configuration (to the default state after
+ device reset) you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd()
+ and RCC_APB1PeriphResetCmd() functions.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the ADC clock (ADCCLK).
+ * @param RCC_PLLCLK: defines the ADC clock divider. This clock is derived from
+ * the PLL Clock.
+ * This parameter can be one of the following values:
+ * @arg RCC_ADC12PLLCLK_OFF: ADC12 clock disabled
+ * @arg RCC_ADC12PLLCLK_Div1: ADC12 clock = PLLCLK/1
+ * @arg RCC_ADC12PLLCLK_Div2: ADC12 clock = PLLCLK/2
+ * @arg RCC_ADC12PLLCLK_Div4: ADC12 clock = PLLCLK/4
+ * @arg RCC_ADC12PLLCLK_Div6: ADC12 clock = PLLCLK/6
+ * @arg RCC_ADC12PLLCLK_Div8: ADC12 clock = PLLCLK/8
+ * @arg RCC_ADC12PLLCLK_Div10: ADC12 clock = PLLCLK/10
+ * @arg RCC_ADC12PLLCLK_Div12: ADC12 clock = PLLCLK/12
+ * @arg RCC_ADC12PLLCLK_Div16: ADC12 clock = PLLCLK/16
+ * @arg RCC_ADC12PLLCLK_Div32: ADC12 clock = PLLCLK/32
+ * @arg RCC_ADC12PLLCLK_Div64: ADC12 clock = PLLCLK/64
+ * @arg RCC_ADC12PLLCLK_Div128: ADC12 clock = PLLCLK/128
+ * @arg RCC_ADC12PLLCLK_Div256: ADC12 clock = PLLCLK/256
+ * @arg RCC_ADC34PLLCLK_OFF: ADC34 clock disabled
+ * @arg RCC_ADC34PLLCLK_Div1: ADC34 clock = PLLCLK/1
+ * @arg RCC_ADC34PLLCLK_Div2: ADC34 clock = PLLCLK/2
+ * @arg RCC_ADC34PLLCLK_Div4: ADC34 clock = PLLCLK/4
+ * @arg RCC_ADC34PLLCLK_Div6: ADC34 clock = PLLCLK/6
+ * @arg RCC_ADC34PLLCLK_Div8: ADC34 clock = PLLCLK/8
+ * @arg RCC_ADC34PLLCLK_Div10: ADC34 clock = PLLCLK/10
+ * @arg RCC_ADC34PLLCLK_Div12: ADC34 clock = PLLCLK/12
+ * @arg RCC_ADC34PLLCLK_Div16: ADC34 clock = PLLCLK/16
+ * @arg RCC_ADC34PLLCLK_Div32: ADC34 clock = PLLCLK/32
+ * @arg RCC_ADC34PLLCLK_Div64: ADC34 clock = PLLCLK/64
+ * @arg RCC_ADC34PLLCLK_Div128: ADC34 clock = PLLCLK/128
+ * @arg RCC_ADC34PLLCLK_Div256: ADC34 clock = PLLCLK/256
+ * @retval None
+ */
+void RCC_ADCCLKConfig(uint32_t RCC_PLLCLK)
+{
+ uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_ADCCLK(RCC_PLLCLK));
+
+ tmp = (RCC_PLLCLK >> 28);
+
+ /* Clears ADCPRE34 bits */
+ if (tmp != 0)
+ {
+ RCC->CFGR2 &= ~RCC_CFGR2_ADCPRE34;
+ }
+ /* Clears ADCPRE12 bits */
+ else
+ {
+ RCC->CFGR2 &= ~RCC_CFGR2_ADCPRE12;
+ }
+ /* Set ADCPRE bits according to RCC_PLLCLK value */
+ RCC->CFGR2 |= RCC_PLLCLK;
+}
+
+/**
+ * @brief Configures the I2C clock (I2CCLK).
+ * @param RCC_I2CCLK: defines the I2C clock source. This clock is derived
+ * from the HSI or System clock.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2CxCLK_HSI: I2Cx clock = HSI
+ * @arg RCC_I2CxCLK_SYSCLK: I2Cx clock = System Clock
+ * (x can be 1 or 2 or 3).
+ * @retval None
+ */
+void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK)
+{
+ uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_I2CCLK(RCC_I2CCLK));
+
+ tmp = (RCC_I2CCLK >> 28);
+
+ /* Clear I2CSW bit */
+ switch (tmp)
+ {
+ case 0x00:
+ RCC->CFGR3 &= ~RCC_CFGR3_I2C1SW;
+ break;
+ case 0x01:
+ RCC->CFGR3 &= ~RCC_CFGR3_I2C2SW;
+ break;
+ case 0x02:
+ RCC->CFGR3 &= ~RCC_CFGR3_I2C3SW;
+ break;
+ default:
+ break;
+ }
+
+ /* Set I2CSW bits according to RCC_I2CCLK value */
+ RCC->CFGR3 |= RCC_I2CCLK;
+}
+
+/**
+ * @brief Configures the TIMx clock sources(TIMCLK).
+ * @note The configuration of the TIMx clock source is only possible when the
+ * SYSCLK = PLL and HCLK and PCLK2 clocks are not divided in respect to SYSCLK
+ * @note If one of the previous conditions is missed, the TIM clock source
+ * configuration is lost and calling again this function becomes mandatory.
+ * @param RCC_TIMCLK: defines the TIMx clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_TIMxCLK_HCLK: TIMx clock = APB high speed clock (doubled frequency
+ * when prescaled)
+ * @arg RCC_TIMxCLK_PLLCLK: TIMx clock = PLL output (running up to 144 MHz)
+ * (x can be 1, 8, 15, 16, 17).
+ * @retval None
+ */
+void RCC_TIMCLKConfig(uint32_t RCC_TIMCLK)
+{
+ uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_TIMCLK(RCC_TIMCLK));
+
+ tmp = (RCC_TIMCLK >> 28);
+
+ /* Clear TIMSW bit */
+
+ switch (tmp)
+ {
+ case 0x00:
+ RCC->CFGR3 &= ~RCC_CFGR3_TIM1SW;
+ break;
+ case 0x01:
+ RCC->CFGR3 &= ~RCC_CFGR3_TIM8SW;
+ break;
+ case 0x02:
+ RCC->CFGR3 &= ~RCC_CFGR3_TIM15SW;
+ break;
+ case 0x03:
+ RCC->CFGR3 &= ~RCC_CFGR3_TIM16SW;
+ break;
+ case 0x04:
+ RCC->CFGR3 &= ~RCC_CFGR3_TIM17SW;
+ break;
+ default:
+ break;
+ }
+
+ /* Set I2CSW bits according to RCC_TIMCLK value */
+ RCC->CFGR3 |= RCC_TIMCLK;
+}
+
+/**
+ * @brief Configures the HRTIM1 clock sources(HRTIM1CLK).
+ * @note The configuration of the HRTIM1 clock source is only possible when the
+ * SYSCLK = PLL and HCLK and PCLK2 clocks are not divided in respect to SYSCLK
+ * @note If one of the previous conditions is missed, the TIM clock source
+ * configuration is lost and calling again this function becomes mandatory.
+ * @param RCC_HRTIMCLK: defines the TIMx clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_HRTIM1CLK_HCLK: TIMx clock = APB high speed clock (doubled frequency
+ * when prescaled)
+ * @arg RCC_HRTIM1CLK_PLLCLK: TIMx clock = PLL output (running up to 144 MHz)
+ * (x can be 1 or 8).
+ * @retval None
+ */
+void RCC_HRTIM1CLKConfig(uint32_t RCC_HRTIMCLK)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_HRTIMCLK(RCC_HRTIMCLK));
+
+ /* Clear HRTIMSW bit */
+ RCC->CFGR3 &= ~RCC_CFGR3_HRTIM1SW;
+
+ /* Set HRTIMSW bits according to RCC_HRTIMCLK value */
+ RCC->CFGR3 |= RCC_HRTIMCLK;
+}
+
+/**
+ * @brief Configures the USART clock (USARTCLK).
+ * @param RCC_USARTCLK: defines the USART clock source. This clock is derived
+ * from the HSI or System clock.
+ * This parameter can be one of the following values:
+ * @arg RCC_USARTxCLK_PCLK: USART clock = APB Clock (PCLK)
+ * @arg RCC_USARTxCLK_SYSCLK: USART clock = System Clock
+ * @arg RCC_USARTxCLK_LSE: USART clock = LSE Clock
+ * @arg RCC_USARTxCLK_HSI: USART clock = HSI Clock
+ * (x can be 1, 2, 3, 4 or 5).
+ * @retval None
+ */
+void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK)
+{
+ uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_USARTCLK(RCC_USARTCLK));
+
+ tmp = (RCC_USARTCLK >> 28);
+
+ /* Clear USARTSW[1:0] bit */
+ switch (tmp)
+ {
+ case 0x01: /* clear USART1SW */
+ RCC->CFGR3 &= ~RCC_CFGR3_USART1SW;
+ break;
+ case 0x02: /* clear USART2SW */
+ RCC->CFGR3 &= ~RCC_CFGR3_USART2SW;
+ break;
+ case 0x03: /* clear USART3SW */
+ RCC->CFGR3 &= ~RCC_CFGR3_USART3SW;
+ break;
+ case 0x04: /* clear UART4SW */
+ RCC->CFGR3 &= ~RCC_CFGR3_UART4SW;
+ break;
+ case 0x05: /* clear UART5SW */
+ RCC->CFGR3 &= ~RCC_CFGR3_UART5SW;
+ break;
+ default:
+ break;
+ }
+
+ /* Set USARTSW bits according to RCC_USARTCLK value */
+ RCC->CFGR3 |= RCC_USARTCLK;
+}
+
+/**
+ * @brief Configures the USB clock (USBCLK).
+ * @param RCC_USBCLKSource: specifies the USB clock source. This clock is
+ * derived from the PLL output.
+ * This parameter can be one of the following values:
+ * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB
+ * clock source
+ * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
+ * @retval None
+ */
+void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
+
+ *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource;
+}
+
+/**
+ * @brief Configures the RTC clock (RTCCLK).
+ * @note As the RTC clock configuration bits are in the Backup domain and write
+ * access is denied to this domain after reset, you have to enable write
+ * access using PWR_BackupAccessCmd(ENABLE) function before to configure
+ * the RTC clock source (to be done once after reset).
+ * @note Once the RTC clock is configured it can't be changed unless the RTC
+ * is reset using RCC_BackupResetCmd function, or by a Power On Reset (POR)
+ *
+ * @param RCC_RTCCLKSource: specifies the RTC clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
+ * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
+ * @arg RCC_RTCCLKSource_HSE_Div32: HSE divided by 32 selected as RTC clock
+ *
+ * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
+ * work in STOP and STANDBY modes, and can be used as wakeup source.
+ * However, when the HSE clock is used as RTC clock source, the RTC
+ * cannot be used in STOP and STANDBY modes.
+ * @note The maximum input clock frequency for RTC is 2MHz (when using HSE as
+ * RTC clock source).
+ * @retval None
+ */
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
+
+ /* Select the RTC clock source */
+ RCC->BDCR |= RCC_RTCCLKSource;
+}
+
+/**
+ * @brief Configures the I2S clock source (I2SCLK).
+ * @note This function must be called before enabling the SPI2 and SPI3 clocks.
+ * @param RCC_I2SCLKSource: specifies the I2S clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2S2CLKSource_SYSCLK: SYSCLK clock used as I2S clock source
+ * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin
+ * used as I2S clock source
+ * @retval None
+ */
+void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
+
+ *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource;
+}
+
+/**
+ * @brief Enables or disables the RTC clock.
+ * @note This function must be used only after the RTC clock source was selected
+ * using the RCC_RTCCLKConfig function.
+ * @param NewState: new state of the RTC clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_RTCCLKCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Forces or releases the Backup domain reset.
+ * @note This function resets the RTC peripheral (including the backup registers)
+ * and the RTC clock source selection in RCC_BDCR register.
+ * @param NewState: new state of the Backup domain reset.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_BackupResetCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enables or disables the AHB peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_AHBPeriph_GPIOA
+ * @arg RCC_AHBPeriph_GPIOB
+ * @arg RCC_AHBPeriph_GPIOC
+ * @arg RCC_AHBPeriph_GPIOD
+ * @arg RCC_AHBPeriph_GPIOE
+ * @arg RCC_AHBPeriph_GPIOF
+ * @arg RCC_AHBPeriph_TS
+ * @arg RCC_AHBPeriph_CRC
+ * @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode)
+ * @arg RCC_AHBPeriph_SRAM
+ * @arg RCC_AHBPeriph_DMA2
+ * @arg RCC_AHBPeriph_DMA1
+ * @arg RCC_AHBPeriph_ADC34
+ * @arg RCC_AHBPeriph_ADC12
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RCC->AHBENR |= RCC_AHBPeriph;
+ }
+ else
+ {
+ RCC->AHBENR &= ~RCC_AHBPeriph;
+ }
+}
+
+/**
+ * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB2Periph_SYSCFG
+ * @arg RCC_APB2Periph_SPI1
+ * @arg RCC_APB2Periph_USART1
+ * @arg RCC_APB2Periph_TIM15
+ * @arg RCC_APB2Periph_TIM16
+ * @arg RCC_APB2Periph_TIM17
+ * @arg RCC_APB2Periph_TIM1
+ * @arg RCC_APB2Periph_TIM8
+ * @arg RCC_APB2Periph_HRTIM1
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RCC->APB2ENR |= RCC_APB2Periph;
+ }
+ else
+ {
+ RCC->APB2ENR &= ~RCC_APB2Periph;
+ }
+}
+
+/**
+ * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB1Periph_TIM2
+ * @arg RCC_APB1Periph_TIM3
+ * @arg RCC_APB1Periph_TIM4
+ * @arg RCC_APB1Periph_TIM6
+ * @arg RCC_APB1Periph_TIM7
+ * @arg RCC_APB1Periph_WWDG
+ * @arg RCC_APB1Periph_SPI2
+ * @arg RCC_APB1Periph_SPI3
+ * @arg RCC_APB1Periph_USART2
+ * @arg RCC_APB1Periph_USART3
+ * @arg RCC_APB1Periph_UART4
+ * @arg RCC_APB1Periph_UART5
+ * @arg RCC_APB1Periph_I2C1
+ * @arg RCC_APB1Periph_I2C2
+ * @arg RCC_APB1Periph_USB
+ * @arg RCC_APB1Periph_CAN1
+ * @arg RCC_APB1Periph_PWR
+ * @arg RCC_APB1Periph_DAC1
+ * @arg RCC_APB1Periph_DAC2
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RCC->APB1ENR |= RCC_APB1Periph;
+ }
+ else
+ {
+ RCC->APB1ENR &= ~RCC_APB1Periph;
+ }
+}
+
+/**
+ * @brief Forces or releases AHB peripheral reset.
+ * @param RCC_AHBPeriph: specifies the AHB peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_AHBPeriph_GPIOA
+ * @arg RCC_AHBPeriph_GPIOB
+ * @arg RCC_AHBPeriph_GPIOC
+ * @arg RCC_AHBPeriph_GPIOD
+ * @arg RCC_AHBPeriph_GPIOE
+ * @arg RCC_AHBPeriph_GPIOF
+ * @arg RCC_AHBPeriph_TS
+ * @arg RCC_AHBPeriph_ADC34
+ * @arg RCC_AHBPeriph_ADC12
+ * @param NewState: new state of the specified peripheral reset.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_AHB_RST_PERIPH(RCC_AHBPeriph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RCC->AHBRSTR |= RCC_AHBPeriph;
+ }
+ else
+ {
+ RCC->AHBRSTR &= ~RCC_AHBPeriph;
+ }
+}
+
+/**
+ * @brief Forces or releases High Speed APB (APB2) peripheral reset.
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB2Periph_SYSCFG
+ * @arg RCC_APB2Periph_SPI1
+ * @arg RCC_APB2Periph_USART1
+ * @arg RCC_APB2Periph_TIM15
+ * @arg RCC_APB2Periph_TIM16
+ * @arg RCC_APB2Periph_TIM17
+ * @arg RCC_APB2Periph_TIM1
+ * @arg RCC_APB2Periph_TIM8
+ * @arg RCC_APB2Periph_HRTIM1
+ * @param NewState: new state of the specified peripheral reset.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RCC->APB2RSTR |= RCC_APB2Periph;
+ }
+ else
+ {
+ RCC->APB2RSTR &= ~RCC_APB2Periph;
+ }
+}
+
+/**
+ * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB1Periph_TIM2
+ * @arg RCC_APB1Periph_TIM3
+ * @arg RCC_APB1Periph_TIM4
+ * @arg RCC_APB1Periph_TIM6
+ * @arg RCC_APB1Periph_TIM7
+ * @arg RCC_APB1Periph_WWDG
+ * @arg RCC_APB1Periph_SPI2
+ * @arg RCC_APB1Periph_SPI3
+ * @arg RCC_APB1Periph_USART2
+ * @arg RCC_APB1Periph_USART3
+ * @arg RCC_APB1Periph_UART4
+ * @arg RCC_APB1Periph_UART5
+ * @arg RCC_APB1Periph_I2C1
+ * @arg RCC_APB1Periph_I2C2
+ * @arg RCC_APB1Periph_I2C3
+ * @arg RCC_APB1Periph_USB
+ * @arg RCC_APB1Periph_CAN1
+ * @arg RCC_APB1Periph_PWR
+ * @arg RCC_APB1Periph_DAC
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RCC->APB1RSTR |= RCC_APB1Periph;
+ }
+ else
+ {
+ RCC->APB1RSTR &= ~RCC_APB1Periph;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Group4 Interrupts and flags management functions
+ * @brief Interrupts and flags management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupts and flags management functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the specified RCC interrupts.
+ * @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
+ * and if the HSE clock fails, the CSS interrupt occurs and an NMI is
+ * automatically generated. The NMI will be executed indefinitely, and
+ * since NMI has higher priority than any other IRQ (and main program)
+ * the application will be stacked in the NMI ISR unless the CSS interrupt
+ * pending bit is cleared.
+ * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt
+ * @param NewState: new state of the specified RCC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_IT(RCC_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Perform Byte access to RCC_CIR[13:8] bits to enable the selected interrupts */
+ *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
+ }
+ else
+ {
+ /* Perform Byte access to RCC_CIR[13:8] bits to disable the selected interrupts */
+ *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
+ }
+}
+
+/**
+ * @brief Checks whether the specified RCC flag is set or not.
+ * @param RCC_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
+ * @arg RCC_FLAG_PLLRDY: PLL clock ready
+ * @arg RCC_FLAG_MCOF: MCO Flag
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
+ * @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
+ * @arg RCC_FLAG_PINRST: Pin reset
+ * @arg RCC_FLAG_PORRST: POR/PDR reset
+ * @arg RCC_FLAG_SFTRST: Software reset
+ * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
+ * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
+ * @arg RCC_FLAG_LPWRRST: Low Power reset
+ * @retval The new state of RCC_FLAG (SET or RESET).
+ */
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
+{
+ uint32_t tmp = 0;
+ uint32_t statusreg = 0;
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_FLAG(RCC_FLAG));
+
+ /* Get the RCC register index */
+ tmp = RCC_FLAG >> 5;
+
+ if (tmp == 0) /* The flag to check is in CR register */
+ {
+ statusreg = RCC->CR;
+ }
+ else if (tmp == 1) /* The flag to check is in BDCR register */
+ {
+ statusreg = RCC->BDCR;
+ }
+ else if (tmp == 4) /* The flag to check is in CFGR register */
+ {
+ statusreg = RCC->CFGR;
+ }
+ else /* The flag to check is in CSR register */
+ {
+ statusreg = RCC->CSR;
+ }
+
+ /* Get the flag position */
+ tmp = RCC_FLAG & FLAG_MASK;
+
+ if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RCC reset flags.
+ * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST,
+ * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
+ * @param None
+ * @retval None
+ */
+void RCC_ClearFlag(void)
+{
+ /* Set RMVF bit to clear the reset flags */
+ RCC->CSR |= RCC_CSR_RMVF;
+}
+
+/**
+ * @brief Checks whether the specified RCC interrupt has occurred or not.
+ * @param RCC_IT: specifies the RCC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt
+ * @arg RCC_IT_CSS: Clock Security System interrupt
+ * @retval The new state of RCC_IT (SET or RESET).
+ */
+ITStatus RCC_GetITStatus(uint8_t RCC_IT)
+{
+ ITStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_GET_IT(RCC_IT));
+
+ /* Check the status of the specified RCC interrupt */
+ if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the RCC_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RCC's interrupt pending bits.
+ * @param RCC_IT: specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt
+ * @arg RCC_IT_CSS: Clock Security System interrupt
+ * @retval None
+ */
+void RCC_ClearITPendingBit(uint8_t RCC_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_CLEAR_IT(RCC_IT));
+
+ /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
+ pending bits */
+ *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_rcc.h Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,709 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_rcc.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the RCC
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_RCC_H
+#define __STM32F30x_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RCC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+typedef struct
+{
+ uint32_t SYSCLK_Frequency;
+ uint32_t HCLK_Frequency;
+ uint32_t PCLK1_Frequency;
+ uint32_t PCLK2_Frequency;
+ uint32_t ADC12CLK_Frequency;
+ uint32_t ADC34CLK_Frequency;
+ uint32_t I2C1CLK_Frequency;
+ uint32_t I2C2CLK_Frequency;
+ uint32_t I2C3CLK_Frequency;
+ uint32_t TIM1CLK_Frequency;
+ uint32_t HRTIM1CLK_Frequency;
+ uint32_t TIM8CLK_Frequency;
+ uint32_t USART1CLK_Frequency;
+ uint32_t USART2CLK_Frequency;
+ uint32_t USART3CLK_Frequency;
+ uint32_t UART4CLK_Frequency;
+ uint32_t UART5CLK_Frequency;
+ uint32_t TIM15CLK_Frequency;
+ uint32_t TIM16CLK_Frequency;
+ uint32_t TIM17CLK_Frequency;
+}RCC_ClocksTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup RCC_HSE_configuration
+ * @{
+ */
+
+#define RCC_HSE_OFF ((uint8_t)0x00)
+#define RCC_HSE_ON ((uint8_t)0x01)
+#define RCC_HSE_Bypass ((uint8_t)0x05)
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+ ((HSE) == RCC_HSE_Bypass))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Clock_Source
+ * @{
+ */
+
+#define RCC_PLLSource_HSI_Div2 RCC_CFGR_PLLSRC_HSI_Div2
+#define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_PREDIV1
+
+#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
+ ((SOURCE) == RCC_PLLSource_PREDIV1))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Multiplication_Factor
+ * @{
+ */
+
+#define RCC_PLLMul_2 RCC_CFGR_PLLMULL2
+#define RCC_PLLMul_3 RCC_CFGR_PLLMULL3
+#define RCC_PLLMul_4 RCC_CFGR_PLLMULL4
+#define RCC_PLLMul_5 RCC_CFGR_PLLMULL5
+#define RCC_PLLMul_6 RCC_CFGR_PLLMULL6
+#define RCC_PLLMul_7 RCC_CFGR_PLLMULL7
+#define RCC_PLLMul_8 RCC_CFGR_PLLMULL8
+#define RCC_PLLMul_9 RCC_CFGR_PLLMULL9
+#define RCC_PLLMul_10 RCC_CFGR_PLLMULL10
+#define RCC_PLLMul_11 RCC_CFGR_PLLMULL11
+#define RCC_PLLMul_12 RCC_CFGR_PLLMULL12
+#define RCC_PLLMul_13 RCC_CFGR_PLLMULL13
+#define RCC_PLLMul_14 RCC_CFGR_PLLMULL14
+#define RCC_PLLMul_15 RCC_CFGR_PLLMULL15
+#define RCC_PLLMul_16 RCC_CFGR_PLLMULL16
+#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
+ ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
+ ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
+ ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
+ ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
+ ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
+ ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
+ ((MUL) == RCC_PLLMul_16))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PREDIV1_division_factor
+ * @{
+ */
+#define RCC_PREDIV1_Div1 RCC_CFGR2_PREDIV1_DIV1
+#define RCC_PREDIV1_Div2 RCC_CFGR2_PREDIV1_DIV2
+#define RCC_PREDIV1_Div3 RCC_CFGR2_PREDIV1_DIV3
+#define RCC_PREDIV1_Div4 RCC_CFGR2_PREDIV1_DIV4
+#define RCC_PREDIV1_Div5 RCC_CFGR2_PREDIV1_DIV5
+#define RCC_PREDIV1_Div6 RCC_CFGR2_PREDIV1_DIV6
+#define RCC_PREDIV1_Div7 RCC_CFGR2_PREDIV1_DIV7
+#define RCC_PREDIV1_Div8 RCC_CFGR2_PREDIV1_DIV8
+#define RCC_PREDIV1_Div9 RCC_CFGR2_PREDIV1_DIV9
+#define RCC_PREDIV1_Div10 RCC_CFGR2_PREDIV1_DIV10
+#define RCC_PREDIV1_Div11 RCC_CFGR2_PREDIV1_DIV11
+#define RCC_PREDIV1_Div12 RCC_CFGR2_PREDIV1_DIV12
+#define RCC_PREDIV1_Div13 RCC_CFGR2_PREDIV1_DIV13
+#define RCC_PREDIV1_Div14 RCC_CFGR2_PREDIV1_DIV14
+#define RCC_PREDIV1_Div15 RCC_CFGR2_PREDIV1_DIV15
+#define RCC_PREDIV1_Div16 RCC_CFGR2_PREDIV1_DIV16
+
+#define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
+ ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
+ ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
+ ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
+ ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
+ ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
+ ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
+ ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Source
+ * @{
+ */
+
+#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI
+#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE
+#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
+ ((SOURCE) == RCC_SYSCLKSource_HSE) || \
+ ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB_Clock_Source
+ * @{
+ */
+
+#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1
+#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2
+#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4
+#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8
+#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16
+#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64
+#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128
+#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256
+#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
+ ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
+ ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
+ ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
+ ((HCLK) == RCC_SYSCLK_Div512))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_APB2_clock_source
+ * @{
+ */
+
+#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
+#define RCC_HCLK_Div2 ((uint32_t)0x00000400)
+#define RCC_HCLK_Div4 ((uint32_t)0x00000500)
+#define RCC_HCLK_Div8 ((uint32_t)0x00000600)
+#define RCC_HCLK_Div16 ((uint32_t)0x00000700)
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
+ ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
+ ((PCLK) == RCC_HCLK_Div16))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_ADC_clock_source
+ * @{
+ */
+
+/* ADC1 & ADC2 */
+#define RCC_ADC12PLLCLK_OFF ((uint32_t)0x00000000)
+#define RCC_ADC12PLLCLK_Div1 ((uint32_t)0x00000100)
+#define RCC_ADC12PLLCLK_Div2 ((uint32_t)0x00000110)
+#define RCC_ADC12PLLCLK_Div4 ((uint32_t)0x00000120)
+#define RCC_ADC12PLLCLK_Div6 ((uint32_t)0x00000130)
+#define RCC_ADC12PLLCLK_Div8 ((uint32_t)0x00000140)
+#define RCC_ADC12PLLCLK_Div10 ((uint32_t)0x00000150)
+#define RCC_ADC12PLLCLK_Div12 ((uint32_t)0x00000160)
+#define RCC_ADC12PLLCLK_Div16 ((uint32_t)0x00000170)
+#define RCC_ADC12PLLCLK_Div32 ((uint32_t)0x00000180)
+#define RCC_ADC12PLLCLK_Div64 ((uint32_t)0x00000190)
+#define RCC_ADC12PLLCLK_Div128 ((uint32_t)0x000001A0)
+#define RCC_ADC12PLLCLK_Div256 ((uint32_t)0x000001B0)
+
+/* ADC3 & ADC4 */
+#define RCC_ADC34PLLCLK_OFF ((uint32_t)0x10000000)
+#define RCC_ADC34PLLCLK_Div1 ((uint32_t)0x10002000)
+#define RCC_ADC34PLLCLK_Div2 ((uint32_t)0x10002200)
+#define RCC_ADC34PLLCLK_Div4 ((uint32_t)0x10002400)
+#define RCC_ADC34PLLCLK_Div6 ((uint32_t)0x10002600)
+#define RCC_ADC34PLLCLK_Div8 ((uint32_t)0x10002800)
+#define RCC_ADC34PLLCLK_Div10 ((uint32_t)0x10002A00)
+#define RCC_ADC34PLLCLK_Div12 ((uint32_t)0x10002C00)
+#define RCC_ADC34PLLCLK_Div16 ((uint32_t)0x10002E00)
+#define RCC_ADC34PLLCLK_Div32 ((uint32_t)0x10003000)
+#define RCC_ADC34PLLCLK_Div64 ((uint32_t)0x10003200)
+#define RCC_ADC34PLLCLK_Div128 ((uint32_t)0x10003400)
+#define RCC_ADC34PLLCLK_Div256 ((uint32_t)0x10003600)
+
+#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_Div1) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_Div2) || ((ADCCLK) == RCC_ADC12PLLCLK_Div4) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_Div6) || ((ADCCLK) == RCC_ADC12PLLCLK_Div8) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_Div10) || ((ADCCLK) == RCC_ADC12PLLCLK_Div12) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_Div16) || ((ADCCLK) == RCC_ADC12PLLCLK_Div32) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_Div64) || ((ADCCLK) == RCC_ADC12PLLCLK_Div128) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_Div256) || ((ADCCLK) == RCC_ADC34PLLCLK_OFF) || \
+ ((ADCCLK) == RCC_ADC34PLLCLK_Div1) || ((ADCCLK) == RCC_ADC34PLLCLK_Div2) || \
+ ((ADCCLK) == RCC_ADC34PLLCLK_Div4) || ((ADCCLK) == RCC_ADC34PLLCLK_Div6) || \
+ ((ADCCLK) == RCC_ADC34PLLCLK_Div8) || ((ADCCLK) == RCC_ADC34PLLCLK_Div10) || \
+ ((ADCCLK) == RCC_ADC34PLLCLK_Div12) || ((ADCCLK) == RCC_ADC34PLLCLK_Div16) || \
+ ((ADCCLK) == RCC_ADC34PLLCLK_Div32) || ((ADCCLK) == RCC_ADC34PLLCLK_Div64) || \
+ ((ADCCLK) == RCC_ADC34PLLCLK_Div128) || ((ADCCLK) == RCC_ADC34PLLCLK_Div256))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_TIM_clock_source
+ * @{
+ */
+
+#define RCC_TIM1CLK_HCLK ((uint32_t)0x00000000)
+#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW
+
+#define RCC_TIM8CLK_HCLK ((uint32_t)0x10000000)
+#define RCC_TIM8CLK_PLLCLK ((uint32_t)0x10000200)
+
+#define RCC_TIM15CLK_HCLK ((uint32_t)0x20000000)
+#define RCC_TIM15CLK_PLLCLK ((uint32_t)0x20000400)
+
+#define RCC_TIM16CLK_HCLK ((uint32_t)0x30000000)
+#define RCC_TIM16CLK_PLLCLK ((uint32_t)0x30000800)
+
+#define RCC_TIM17CLK_HCLK ((uint32_t)0x40000000)
+#define RCC_TIM17CLK_PLLCLK ((uint32_t)0x40002000)
+
+#define IS_RCC_TIMCLK(TIMCLK) (((TIMCLK) == RCC_TIM1CLK_HCLK) || ((TIMCLK) == RCC_TIM1CLK_PLLCLK) || \
+ ((TIMCLK) == RCC_TIM8CLK_HCLK) || ((TIMCLK) == RCC_TIM8CLK_PLLCLK) || \
+ ((TIMCLK) == RCC_TIM15CLK_HCLK) || ((TIMCLK) == RCC_TIM15CLK_PLLCLK) || \
+ ((TIMCLK) == RCC_TIM16CLK_HCLK) || ((TIMCLK) == RCC_TIM16CLK_PLLCLK) || \
+ ((TIMCLK) == RCC_TIM17CLK_HCLK) || ((TIMCLK) == RCC_TIM17CLK_PLLCLK))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HRTIM_clock_source
+ * @{
+ */
+
+#define RCC_HRTIM1CLK_HCLK ((uint32_t)0x00000000)
+#define RCC_HRTIM1CLK_PLLCLK RCC_CFGR3_HRTIM1SW
+
+#define IS_RCC_HRTIMCLK(HRTIMCLK) (((HRTIMCLK) == RCC_HRTIM1CLK_HCLK) || ((HRTIMCLK) == RCC_HRTIM1CLK_PLLCLK))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_I2C_clock_source
+ * @{
+ */
+
+#define RCC_I2C1CLK_HSI ((uint32_t)0x00000000)
+#define RCC_I2C1CLK_SYSCLK RCC_CFGR3_I2C1SW
+
+#define RCC_I2C2CLK_HSI ((uint32_t)0x10000000)
+#define RCC_I2C2CLK_SYSCLK ((uint32_t)0x10000020)
+
+#define RCC_I2C3CLK_HSI ((uint32_t)0x20000000)
+#define RCC_I2C3CLK_SYSCLK ((uint32_t)0x20000040)
+
+#define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK) || \
+ ((I2CCLK) == RCC_I2C2CLK_HSI) || ((I2CCLK) == RCC_I2C2CLK_SYSCLK) || \
+ ((I2CCLK) == RCC_I2C3CLK_HSI) || ((I2CCLK) == RCC_I2C3CLK_SYSCLK))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_USART_clock_source
+ * @{
+ */
+
+#define RCC_USART1CLK_PCLK ((uint32_t)0x10000000)
+#define RCC_USART1CLK_SYSCLK ((uint32_t)0x10000001)
+#define RCC_USART1CLK_LSE ((uint32_t)0x10000002)
+#define RCC_USART1CLK_HSI ((uint32_t)0x10000003)
+
+#define RCC_USART2CLK_PCLK ((uint32_t)0x20000000)
+#define RCC_USART2CLK_SYSCLK ((uint32_t)0x20010000)
+#define RCC_USART2CLK_LSE ((uint32_t)0x20020000)
+#define RCC_USART2CLK_HSI ((uint32_t)0x20030000)
+
+#define RCC_USART3CLK_PCLK ((uint32_t)0x30000000)
+#define RCC_USART3CLK_SYSCLK ((uint32_t)0x30040000)
+#define RCC_USART3CLK_LSE ((uint32_t)0x30080000)
+#define RCC_USART3CLK_HSI ((uint32_t)0x300C0000)
+
+#define RCC_UART4CLK_PCLK ((uint32_t)0x40000000)
+#define RCC_UART4CLK_SYSCLK ((uint32_t)0x40100000)
+#define RCC_UART4CLK_LSE ((uint32_t)0x40200000)
+#define RCC_UART4CLK_HSI ((uint32_t)0x40300000)
+
+#define RCC_UART5CLK_PCLK ((uint32_t)0x50000000)
+#define RCC_UART5CLK_SYSCLK ((uint32_t)0x50400000)
+#define RCC_UART5CLK_LSE ((uint32_t)0x50800000)
+#define RCC_UART5CLK_HSI ((uint32_t)0x50C00000)
+
+#define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \
+ ((USARTCLK) == RCC_USART1CLK_LSE) || ((USARTCLK) == RCC_USART1CLK_HSI) ||\
+ ((USARTCLK) == RCC_USART2CLK_PCLK) || ((USARTCLK) == RCC_USART2CLK_SYSCLK) || \
+ ((USARTCLK) == RCC_USART2CLK_LSE) || ((USARTCLK) == RCC_USART2CLK_HSI) || \
+ ((USARTCLK) == RCC_USART3CLK_PCLK) || ((USARTCLK) == RCC_USART3CLK_SYSCLK) || \
+ ((USARTCLK) == RCC_USART3CLK_LSE) || ((USARTCLK) == RCC_USART3CLK_HSI) || \
+ ((USARTCLK) == RCC_UART4CLK_PCLK) || ((USARTCLK) == RCC_UART4CLK_SYSCLK) || \
+ ((USARTCLK) == RCC_UART4CLK_LSE) || ((USARTCLK) == RCC_UART4CLK_HSI) || \
+ ((USARTCLK) == RCC_UART5CLK_PCLK) || ((USARTCLK) == RCC_UART5CLK_SYSCLK) || \
+ ((USARTCLK) == RCC_UART5CLK_LSE) || ((USARTCLK) == RCC_UART5CLK_HSI))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Interrupt_Source
+ * @{
+ */
+
+#define RCC_IT_LSIRDY ((uint8_t)0x01)
+#define RCC_IT_LSERDY ((uint8_t)0x02)
+#define RCC_IT_HSIRDY ((uint8_t)0x04)
+#define RCC_IT_HSERDY ((uint8_t)0x08)
+#define RCC_IT_PLLRDY ((uint8_t)0x10)
+#define RCC_IT_CSS ((uint8_t)0x80)
+
+#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
+
+#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
+ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
+ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
+
+
+#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSE_configuration
+ * @{
+ */
+
+#define RCC_LSE_OFF ((uint32_t)0x00000000)
+#define RCC_LSE_ON RCC_BDCR_LSEON
+#define RCC_LSE_Bypass ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP))
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+ ((LSE) == RCC_LSE_Bypass))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_RTC_Clock_Source
+ * @{
+ */
+
+#define RCC_RTCCLKSource_LSE RCC_BDCR_RTCSEL_LSE
+#define RCC_RTCCLKSource_LSI RCC_BDCR_RTCSEL_LSI
+#define RCC_RTCCLKSource_HSE_Div32 RCC_BDCR_RTCSEL_HSE
+
+#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
+ ((SOURCE) == RCC_RTCCLKSource_LSI) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div32))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_I2S_Clock_Source
+ * @{
+ */
+#define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00)
+#define RCC_I2S2CLKSource_Ext ((uint8_t)0x01)
+
+#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
+
+/** @defgroup RCC_LSE_Drive_Configuration
+ * @{
+ */
+
+#define RCC_LSEDrive_Low ((uint32_t)0x00000000)
+#define RCC_LSEDrive_MediumLow RCC_BDCR_LSEDRV_0
+#define RCC_LSEDrive_MediumHigh RCC_BDCR_LSEDRV_1
+#define RCC_LSEDrive_High RCC_BDCR_LSEDRV
+#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \
+ ((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB_Peripherals
+ * @{
+ */
+
+#define RCC_AHBPeriph_ADC34 RCC_AHBENR_ADC34EN
+#define RCC_AHBPeriph_ADC12 RCC_AHBENR_ADC12EN
+#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN
+#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN
+#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN
+#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN
+#define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN
+#define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN
+#define RCC_AHBPeriph_TS RCC_AHBENR_TSEN
+#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN
+#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN
+#define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAMEN
+#define RCC_AHBPeriph_DMA2 RCC_AHBENR_DMA2EN
+#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN
+
+#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xCE81FFA8) == 0x00) && ((PERIPH) != 0x00))
+#define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xCE81FFFF) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Peripherals
+ * @{
+ */
+
+#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN
+#define RCC_APB2Periph_TIM1 RCC_APB2ENR_TIM1EN
+#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN
+#define RCC_APB2Periph_TIM8 RCC_APB2ENR_TIM8EN
+#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN
+#define RCC_APB2Periph_TIM15 RCC_APB2ENR_TIM15EN
+#define RCC_APB2Periph_TIM16 RCC_APB2ENR_TIM16EN
+#define RCC_APB2Periph_TIM17 RCC_APB2ENR_TIM17EN
+#define RCC_APB2Periph_HRTIM1 RCC_APB2ENR_HRTIM1
+
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xDFF887FE) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Peripherals
+ * @{
+ */
+#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN
+#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN
+#define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN
+#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN
+#define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN
+#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN
+#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN
+#define RCC_APB1Periph_SPI3 RCC_APB1ENR_SPI3EN
+#define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN
+#define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN
+#define RCC_APB1Periph_UART4 RCC_APB1ENR_UART4EN
+#define RCC_APB1Periph_UART5 RCC_APB1ENR_UART5EN
+#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN
+#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN
+#define RCC_APB1Periph_USB RCC_APB1ENR_USBEN
+#define RCC_APB1Periph_CAN1 RCC_APB1ENR_CAN1EN
+#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN
+#define RCC_APB1Periph_DAC1 RCC_APB1ENR_DAC1EN
+#define RCC_APB1Periph_I2C3 RCC_APB1ENR_I2C3EN
+#define RCC_APB1Periph_DAC2 RCC_APB1ENR_DAC2EN
+#define RCC_APB1Periph_DAC RCC_APB1Periph_DAC1
+
+
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x890137C8) == 0x00) && ((PERIPH) != 0x00))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCO_Clock_Source
+ * @{
+ */
+
+#define RCC_MCOSource_NoClock ((uint8_t)0x00)
+#define RCC_MCOSource_LSI ((uint8_t)0x02)
+#define RCC_MCOSource_LSE ((uint8_t)0x03)
+#define RCC_MCOSource_SYSCLK ((uint8_t)0x04)
+#define RCC_MCOSource_HSI ((uint8_t)0x05)
+#define RCC_MCOSource_HSE ((uint8_t)0x06)
+#define RCC_MCOSource_PLLCLK_Div2 ((uint8_t)0x07)
+
+#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) ||((SOURCE) == RCC_MCOSource_SYSCLK) ||\
+ ((SOURCE) == RCC_MCOSource_HSI) || ((SOURCE) == RCC_MCOSource_HSE) || \
+ ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE) || \
+ ((SOURCE) == RCC_MCOSource_PLLCLK_Div2))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCOPrescaler
+ * @{
+ */
+
+#define RCC_MCOPrescaler_1 RCC_CFGR_MCO_PRE_1
+#define RCC_MCOPrescaler_2 RCC_CFGR_MCO_PRE_2
+#define RCC_MCOPrescaler_4 RCC_CFGR_MCO_PRE_4
+#define RCC_MCOPrescaler_8 RCC_CFGR_MCO_PRE_8
+#define RCC_MCOPrescaler_16 RCC_CFGR_MCO_PRE_16
+#define RCC_MCOPrescaler_32 RCC_CFGR_MCO_PRE_32
+#define RCC_MCOPrescaler_64 RCC_CFGR_MCO_PRE_64
+#define RCC_MCOPrescaler_128 RCC_CFGR_MCO_PRE_128
+
+#define IS_RCC_MCO_PRESCALER(PRESCALER) (((PRESCALER) == RCC_MCOPrescaler_1) || \
+ ((PRESCALER) == RCC_MCOPrescaler_2) || \
+ ((PRESCALER) == RCC_MCOPrescaler_4) || \
+ ((PRESCALER) == RCC_MCOPrescaler_8) || \
+ ((PRESCALER) == RCC_MCOPrescaler_16) || \
+ ((PRESCALER) == RCC_MCOPrescaler_32) || \
+ ((PRESCALER) == RCC_MCOPrescaler_64) || \
+ ((PRESCALER) == RCC_MCOPrescaler_128))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_USB_Device_clock_source
+ * @{
+ */
+
+#define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)
+#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)
+
+#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
+ ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Flag
+ * @{
+ */
+#define RCC_FLAG_HSIRDY ((uint8_t)0x01)
+#define RCC_FLAG_HSERDY ((uint8_t)0x11)
+#define RCC_FLAG_PLLRDY ((uint8_t)0x19)
+#define RCC_FLAG_MCOF ((uint8_t)0x9C)
+#define RCC_FLAG_LSERDY ((uint8_t)0x21)
+#define RCC_FLAG_LSIRDY ((uint8_t)0x41)
+#define RCC_FLAG_OBLRST ((uint8_t)0x59)
+#define RCC_FLAG_PINRST ((uint8_t)0x5A)
+#define RCC_FLAG_PORRST ((uint8_t)0x5B)
+#define RCC_FLAG_SFTRST ((uint8_t)0x5C)
+#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
+#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
+#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
+
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
+ ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
+ ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_OBLRST) || \
+ ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
+ ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
+ ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
+ ((FLAG) == RCC_FLAG_MCOF))
+
+#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the RCC clock configuration to the default reset state */
+void RCC_DeInit(void);
+
+/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
+void RCC_HSEConfig(uint8_t RCC_HSE);
+ErrorStatus RCC_WaitForHSEStartUp(void);
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
+void RCC_HSICmd(FunctionalState NewState);
+void RCC_LSEConfig(uint32_t RCC_LSE);
+void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive);
+void RCC_LSICmd(FunctionalState NewState);
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
+void RCC_PLLCmd(FunctionalState NewState);
+void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div);
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
+#ifdef STM32F303xC
+ void RCC_MCOConfig(uint8_t RCC_MCOSource);
+#else
+ void RCC_MCOConfig(uint8_t RCC_MCOSource,uint32_t RCC_MCOPrescaler);
+#endif /* STM32F303xC */
+
+/* System, AHB and APB busses clocks configuration functions ******************/
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
+uint8_t RCC_GetSYSCLKSource(void);
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
+void RCC_PCLK1Config(uint32_t RCC_HCLK);
+void RCC_PCLK2Config(uint32_t RCC_HCLK);
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
+
+/* Peripheral clocks configuration functions **********************************/
+void RCC_ADCCLKConfig(uint32_t RCC_PLLCLK);
+void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK);
+void RCC_TIMCLKConfig(uint32_t RCC_TIMCLK);
+void RCC_HRTIM1CLKConfig(uint32_t RCC_HRTIMCLK);
+void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
+void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK);
+void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
+
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
+void RCC_RTCCLKCmd(FunctionalState NewState);
+void RCC_BackupResetCmd(FunctionalState NewState);
+
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
+void RCC_ClearFlag(void);
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);
+void RCC_ClearITPendingBit(uint8_t RCC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F30x_RCC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_rtc.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,2608 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_rtc.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Real-Time Clock (RTC) peripheral:
+ * + Initialization
+ * + Calendar (Time and Date) configuration
+ * + Alarms (Alarm A and Alarm B) configuration
+ * + WakeUp Timer configuration
+ * + Daylight Saving configuration
+ * + Output pin Configuration
+ * + Smooth digital Calibration configuration
+ * + TimeStamp configuration
+ * + Tampers configuration
+ * + Backup Data Registers configuration
+ * + Output Type Config configuration
+ * + Shift control synchronisation
+ * + Interrupts and flags management
+ *
+ @verbatim
+
+ ===============================================================================
+ ##### RTC Operating Condition #####
+ ===============================================================================
+ [..] The real-time clock (RTC) and the RTC backup registers can be powered
+ from the VBAT voltage when the main VDD supply is powered off.
+ To retain the content of the RTC backup registers and supply the RTC
+ when VDD is turned off, VBAT pin can be connected to an optional
+ standby voltage supplied by a battery or by another source.
+
+ [..] To allow the RTC to operate even when the main digital supply (VDD)
+ is turned off, the VBAT pin powers the following blocks:
+ (#) The RTC
+ (#) The LSE oscillator
+ (#) PC13 to PC15 I/Os (when available)
+
+ [..] When the backup domain is supplied by VDD (analog switch connected
+ to VDD), the following functions are available:
+ (#) PC14 and PC15 can be used as either GPIO or LSE pins
+ (#) PC13 can be used as a GPIO or as the RTC_AF pin
+
+ [..] When the backup domain is supplied by VBAT (analog switch connected
+ to VBAT because VDD is not present), the following functions are available:
+ (#) PC14 and PC15 can be used as LSE pins only
+ (#) PC13 can be used as the RTC_AF pin
+
+ ##### Backup Domain Reset #####
+ ===============================================================================
+ [..] The backup domain reset sets all RTC registers and the RCC_BDCR
+ register to their reset values.
+ A backup domain reset is generated when one of the following events
+ occurs:
+ (#) Software reset, triggered by setting the BDRST bit in the
+ RCC Backup domain control register (RCC_BDCR). You can use the
+ RCC_BackupResetCmd().
+ (#) VDD or VBAT power on, if both supplies have previously been
+ powered off.
+
+ ##### Backup Domain Access #####
+ ===============================================================================
+ [..] After reset, the backup domain (RTC registers and RTC backup data
+ registers) is protected against possible unwanted write accesses.
+ [..] To enable access to the Backup Domain and RTC registers, proceed as follows:
+ (#) Enable the Power Controller (PWR) APB1 interface clock using the
+ RCC_APB1PeriphClockCmd() function.
+ (#) Enable access to Backup domain using the PWR_BackupAccessCmd() function.
+ (#) Select the RTC clock source using the RCC_RTCCLKConfig() function.
+ (#) Enable RTC Clock using the RCC_RTCCLKCmd() function.
+
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ (+) Enable the backup domain access (see description in the section above)
+ (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and
+ RTC hour format using the RTC_Init() function.
+
+ *** Time and Date configuration ***
+ ===================================
+ [..]
+ (+) To configure the RTC Calendar (Time and Date) use the RTC_SetTime()
+ and RTC_SetDate() functions.
+ (+) To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate()
+ functions.
+ (+) To read the RTC subsecond, use the RTC_GetSubSecond() function.
+ (+) Use the RTC_DayLightSavingConfig() function to add or sub one
+ hour to the RTC Calendar.
+
+ *** Alarm configuration ***
+ ===========================
+ [..]
+ (+) To configure the RTC Alarm use the RTC_SetAlarm() function.
+ (+) Enable the selected RTC Alarm using the RTC_AlarmCmd() function.
+ (+) To read the RTC Alarm, use the RTC_GetAlarm() function.
+ (+) To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function.
+
+ *** RTC Wakeup configuration ***
+ ================================
+ [..]
+ (+) Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig()
+ function.
+ (+) Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter()
+ function
+ (+) Enable the RTC WakeUp using the RTC_WakeUpCmd() function
+ (+) To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter()
+ function.
+
+ *** Outputs configuration ***
+ =============================
+ [..] The RTC has 2 different outputs:
+ (+) AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B
+ and WaKeUp signals.
+ To output the selected RTC signal on RTC_AF pin, use the
+ RTC_OutputConfig() function.
+ (+) AFO_CALIB: this output is 512Hz signal or 1Hz .
+ To output the RTC Clock on RTC_AF pin, use the RTC_CalibOutputCmd()
+ function.
+
+ *** Smooth digital Calibration configuration ***
+ ================================================
+ [..]
+ (+) Configure the RTC Original Digital Calibration Value and the corresponding
+ calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig()
+ function.
+
+ *** TimeStamp configuration ***
+ ===============================
+ [..]
+ (+) Configure the RTC_AF trigger and enables the RTC TimeStamp
+ using the RTC_TimeStampCmd() function.
+ (+) To read the RTC TimeStamp Time and Date register, use the
+ RTC_GetTimeStamp() function.
+ (+) To read the RTC TimeStamp SubSecond register, use the
+ RTC_GetTimeStampSubSecond() function.
+
+ *** Tamper configuration ***
+ ============================
+ [..]
+ (+) Configure the Tamper filter count using RTC_TamperFilterConfig()
+ function.
+ (+) Configure the RTC Tamper trigger Edge or Level according to the Tamper
+ filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig() function.
+ (+) Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig()
+ function.
+ (+) Configure the Tamper precharge or discharge duration using
+ RTC_TamperPinsPrechargeDuration() function.
+ (+) Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function.
+ (+) Enable the RTC Tamper using the RTC_TamperCmd() function.
+ (+) Enable the Time stamp on Tamper detection event using
+ RTC_TSOnTamperDetecCmd() function.
+
+ *** Backup Data Registers configuration ***
+ ===========================================
+ [..]
+ (+) To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister()
+ function.
+ (+) To read the RTC Backup Data registers, use the RTC_ReadBackupRegister()
+ function.
+
+ ##### RTC and low power modes #####
+ ===============================================================================
+ [..] The MCU can be woken up from a low power mode by an RTC alternate
+ function.
+ [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
+ RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
+ These RTC alternate functions can wake up the system from the Stop
+ and Standby lowpower modes.
+ The system can also wake up from low power modes without depending
+ on an external interrupt (Auto-wakeup mode), by using the RTC alarm
+ or the RTC wakeup events.
+ [..] The RTC provides a programmable time base for waking up from the
+ Stop or Standby mode at regular intervals.
+ Wakeup from STOP and Standby modes is possible only when the RTC
+ clock source is LSE or LSI.
+
+ ##### Selection of RTC_AF alternate functions #####
+ ===============================================================================
+ [..] The RTC_AF pin (PC13) can be used for the following purposes:
+ (+) Wakeup pin 2 (WKUP2) using the PWR_WakeUpPinCmd() function.
+ (+) AFO_ALARM output
+ (+) AFO_CALIB output
+ (+) AFI_TAMPER
+ (+) AFI_TIMESTAMP
+
+ +------------------------------------------------------------------------------------------+
+ | Pin |RTC ALARM |RTC CALIB |RTC TAMPER |RTC TIMESTAMP |PC13MODE| PC13VALUE |
+ | configuration | OUTPUT | OUTPUT | INPUT | INPUT | bit | bit |
+ | and function | ENABLED | ENABLED | ENABLED | ENABLED | | |
+ |-----------------|----------|----------|-----------|--------------|--------|--------------|
+ | Alarm out | | | | | Don't | |
+ | output OD | 1 |Don't care|Don't care | Don't care | care | 0 |
+ |-----------------|----------|----------|-----------|--------------|--------|--------------|
+ | Alarm out | | | | | Don't | |
+ | output PP | 1 |Don't care|Don't care | Don't care | care | 1 |
+ |-----------------|----------|----------|-----------|--------------|--------|--------------|
+ | Calibration out | | | | | Don't | |
+ | output PP | 0 | 1 |Don't care | Don't care | care | Don't care |
+ |-----------------|----------|----------|-----------|--------------|--------|--------------|
+ | TAMPER input | | | | | Don't | |
+ | floating | 0 | 0 | 1 | 0 | care | Don't care |
+ |-----------------|----------|----------|-----------|--------------|--------|--------------|
+ | TIMESTAMP and | | | | | Don't | |
+ | TAMPER input | 0 | 0 | 1 | 1 | care | Don't care |
+ | floating | | | | | | |
+ |-----------------|----------|----------|-----------|--------------|--------|--------------|
+ | TIMESTAMP input | | | | | Don't | |
+ | floating | 0 | 0 | 0 | 1 | care | Don't care |
+ |-----------------|----------|----------|-----------|--------------|--------|--------------|
+ | Output PP | 0 | 0 | 0 | 0 | 1 | PC13 output |
+ | Forced | | | | | | |
+ |-----------------|----------|----------|-----------|--------------|--------|--------------|
+ | Wakeup Pin or | 0 | 0 | 0 | 0 | 0 | Don't care |
+ | Standard GPIO | | | | | | |
+ +------------------------------------------------------------------------------------------+
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_rtc.h"
+#include "stm32f30x_rcc.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup RTC
+ * @brief RTC driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* Masks Definition */
+#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
+#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
+#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
+#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)
+#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
+ RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
+ RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
+ RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \
+ RTC_FLAG_TAMP2F | RTC_FLAG_TAMP3F | RTC_FLAG_RECALPF | \
+ RTC_FLAG_SHPF))
+
+#define INITMODE_TIMEOUT ((uint32_t) 0x00002000)
+#define SYNCHRO_TIMEOUT ((uint32_t) 0x00008000)
+#define RECALPF_TIMEOUT ((uint32_t) 0x00001000)
+#define SHPF_TIMEOUT ((uint32_t) 0x00002000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static uint8_t RTC_ByteToBcd2(uint8_t Value);
+static uint8_t RTC_Bcd2ToByte(uint8_t Value);
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RTC_Private_Functions
+ * @{
+ */
+
+/** @defgroup RTC_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..] This section provide functions allowing to initialize and configure the RTC
+ Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers
+ Write protection, enter and exit the RTC initialization mode, RTC registers
+ synchronization check and reference clock detection enable.
+ (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is
+ split into 2 programmable prescalers to minimize power consumption.
+ (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler.
+ (++) When both prescalers are used, it is recommended to configure the
+ asynchronous prescaler to a high value to minimize consumption.
+ (#) All RTC registers are Write protected. Writing to the RTC registers
+ is enabled by writing a key into the Write Protection register, RTC_WPR.
+ (#) To Configure the RTC Calendar, user application should enter initialization
+ mode. In this mode, the calendar counter is stopped and its value
+ can be updated. When the initialization sequence is complete, the
+ calendar restarts counting after 4 RTCCLK cycles.
+ (#) To read the calendar through the shadow registers after Calendar
+ initialization, calendar update or after wakeup from low power modes
+ the software must first clear the RSF flag. The software must then
+ wait until it is set again before reading the calendar, which means
+ that the calendar registers have been correctly copied into the RTC_TR
+ and RTC_DR shadow registers. The RTC_WaitForSynchro() function
+ implements the above software sequence (RSF clear and RSF check).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the RTC registers to their default reset values.
+ * @note This function doesn't reset the RTC Clock source and RTC Backup Data
+ * registers.
+ * @param None
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are deinitialized
+ * - ERROR: RTC registers are not deinitialized
+ */
+ErrorStatus RTC_DeInit(void)
+{
+ __IO uint32_t wutcounter = 0x00;
+ uint32_t wutwfstatus = 0x00;
+ ErrorStatus status = ERROR;
+
+ /* Disable the write protection for RTC registers */
+ RTC->WPR = 0xCA;
+ RTC->WPR = 0x53;
+
+ /* Set Initialization mode */
+ if (RTC_EnterInitMode() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ /* Reset TR, DR and CR registers */
+ RTC->TR = (uint32_t)0x00000000;
+ RTC->DR = (uint32_t)0x00002101;
+
+ /* Reset All CR bits except CR[2:0] */
+ RTC->CR &= (uint32_t)0x00000007;
+
+ /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+ do
+ {
+ wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;
+ wutcounter++;
+ } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
+
+ if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ /* Reset all RTC CR register bits */
+ RTC->CR &= (uint32_t)0x00000000;
+ RTC->WUTR = (uint32_t)0x0000FFFF;
+ RTC->PRER = (uint32_t)0x007F00FF;
+ RTC->ALRMAR = (uint32_t)0x00000000;
+ RTC->ALRMBR = (uint32_t)0x00000000;
+ RTC->SHIFTR = (uint32_t)0x00000000;
+ RTC->CALR = (uint32_t)0x00000000;
+ RTC->ALRMASSR = (uint32_t)0x00000000;
+ RTC->ALRMBSSR = (uint32_t)0x00000000;
+
+ /* Reset ISR register and exit initialization mode */
+ RTC->ISR = (uint32_t)0x00000000;
+
+ /* Reset Tamper and alternate functions configuration register */
+ RTC->TAFCR = 0x00000000;
+
+ /* Wait till the RTC RSF flag is set */
+ if (RTC_WaitForSynchro() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WPR = 0xFF;
+
+ return status;
+}
+
+/**
+ * @brief Initializes the RTC registers according to the specified parameters
+ * in RTC_InitStruct.
+ * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains
+ * the configuration information for the RTC peripheral.
+ * @note The RTC Prescaler register is write protected and can be written in
+ * initialization mode only.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are initialized
+ * - ERROR: RTC registers are not initialized
+ */
+ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat));
+ assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv));
+ assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WPR = 0xCA;
+ RTC->WPR = 0x53;
+
+ /* Set Initialization mode */
+ if (RTC_EnterInitMode() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ /* Clear RTC CR FMT Bit */
+ RTC->CR &= ((uint32_t)~(RTC_CR_FMT));
+ /* Set RTC_CR register */
+ RTC->CR |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat));
+
+ /* Configure the RTC PRER */
+ RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv);
+ RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16);
+
+ /* Exit Initialization mode */
+ RTC_ExitInitMode();
+
+ status = SUCCESS;
+ }
+ /* Enable the write protection for RTC registers */
+ RTC->WPR = 0xFF;
+
+ return status;
+}
+
+/**
+ * @brief Fills each RTC_InitStruct member with its default value.
+ * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be
+ * initialized.
+ * @retval None
+ */
+void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct)
+{
+ /* Initialize the RTC_HourFormat member */
+ RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24;
+
+ /* Initialize the RTC_AsynchPrediv member */
+ RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F;
+
+ /* Initialize the RTC_SynchPrediv member */
+ RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF;
+}
+
+/**
+ * @brief Enables or disables the RTC registers write protection.
+ * @note All the RTC registers are write protected except for RTC_ISR[13:8],
+ * RTC_TAFCR and RTC_BKPxR.
+ * @note Writing a wrong key reactivates the write protection.
+ * @note The protection mechanism is not affected by system reset.
+ * @param NewState: new state of the write protection.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RTC_WriteProtectionCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the write protection for RTC registers */
+ RTC->WPR = 0xFF;
+ }
+ else
+ {
+ /* Disable the write protection for RTC registers */
+ RTC->WPR = 0xCA;
+ RTC->WPR = 0x53;
+ }
+}
+
+/**
+ * @brief Enters the RTC Initialization mode.
+ * @note The RTC Initialization mode is write protected, use the
+ * RTC_WriteProtectionCmd(DISABLE) before calling this function.
+ * @param None
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC is in Init mode
+ * - ERROR: RTC is not in Init mode
+ */
+ErrorStatus RTC_EnterInitMode(void)
+{
+ __IO uint32_t initcounter = 0x00;
+ ErrorStatus status = ERROR;
+ uint32_t initstatus = 0x00;
+
+ /* Check if the Initialization mode is set */
+ if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+ {
+ /* Set the Initialization mode */
+ RTC->ISR = (uint32_t)RTC_INIT_MASK;
+
+ /* Wait till RTC is in INIT state and if Time out is reached exit */
+ do
+ {
+ initstatus = RTC->ISR & RTC_ISR_INITF;
+ initcounter++;
+ } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));
+
+ if ((RTC->ISR & RTC_ISR_INITF) != RESET)
+ {
+ status = SUCCESS;
+ }
+ else
+ {
+ status = ERROR;
+ }
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Exits the RTC Initialization mode.
+ * @note When the initialization sequence is complete, the calendar restarts
+ * counting after 4 RTCCLK cycles.
+ * @note The RTC Initialization mode is write protected, use the
+ * RTC_WriteProtectionCmd(DISABLE) before calling this function.
+ * @param None
+ * @retval None
+ */
+void RTC_ExitInitMode(void)
+{
+ /* Exit Initialization mode */
+ RTC->ISR &= (uint32_t)~RTC_ISR_INIT;
+}
+
+/**
+ * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are
+ * synchronized with RTC APB clock.
+ * @note The RTC Resynchronization mode is write protected, use the
+ * RTC_WriteProtectionCmd(DISABLE) before calling this function.
+ * @note To read the calendar through the shadow registers after Calendar
+ * initialization, calendar update or after wakeup from low power modes
+ * the software must first clear the RSF flag.
+ * The software must then wait until it is set again before reading
+ * the calendar, which means that the calendar registers have been
+ * correctly copied into the RTC_TR and RTC_DR shadow registers.
+ * @param None
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are synchronised
+ * - ERROR: RTC registers are not synchronised
+ */
+ErrorStatus RTC_WaitForSynchro(void)
+{
+ __IO uint32_t synchrocounter = 0;
+ ErrorStatus status = ERROR;
+ uint32_t synchrostatus = 0x00;
+
+ if ((RTC->CR & RTC_CR_BYPSHAD) != RESET)
+ {
+ /* Bypass shadow mode */
+ status = SUCCESS;
+ }
+ else
+ {
+ /* Disable the write protection for RTC registers */
+ RTC->WPR = 0xCA;
+ RTC->WPR = 0x53;
+
+ /* Clear RSF flag */
+ RTC->ISR &= (uint32_t)RTC_RSF_MASK;
+
+ /* Wait the registers to be synchronised */
+ do
+ {
+ synchrostatus = RTC->ISR & RTC_ISR_RSF;
+ synchrocounter++;
+ } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));
+
+ if ((RTC->ISR & RTC_ISR_RSF) != RESET)
+ {
+ status = SUCCESS;
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WPR = 0xFF;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Enables or disables the RTC reference clock detection.
+ * @param NewState: new state of the RTC reference clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC reference clock detection is enabled
+ * - ERROR: RTC reference clock detection is disabled
+ */
+ErrorStatus RTC_RefClockCmd(FunctionalState NewState)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WPR = 0xCA;
+ RTC->WPR = 0x53;
+
+ /* Set Initialization mode */
+ if (RTC_EnterInitMode() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ if (NewState != DISABLE)
+ {
+ /* Enable the RTC reference clock detection */
+ RTC->CR |= RTC_CR_REFCKON;
+ }
+ else
+ {
+ /* Disable the RTC reference clock detection */
+ RTC->CR &= ~RTC_CR_REFCKON;
+ }
+ /* Exit Initialization mode */
+ RTC_ExitInitMode();
+
+ status = SUCCESS;
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WPR = 0xFF;
+
+ return status;
+}
+
+/**
+ * @brief Enables or Disables the Bypass Shadow feature.
+ * @note When the Bypass Shadow is enabled the calendar value are taken
+ * directly from the Calendar counter.
+ * @param NewState: new state of the Bypass Shadow feature.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+*/
+void RTC_BypassShadowCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WPR = 0xCA;
+ RTC->WPR = 0x53;
+
+ if (NewState != DISABLE)
+ {
+ /* Set the BYPSHAD bit */
+ RTC->CR |= (uint8_t)RTC_CR_BYPSHAD;
+ }
+ else
+ {
+ /* Reset the BYPSHAD bit */
+ RTC->CR &= (uint8_t)~RTC_CR_BYPSHAD;
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WPR = 0xFF;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Group2 Time and Date configuration functions
+ * @brief Time and Date configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Time and Date configuration functions #####
+ ===============================================================================
+ [..] This section provide functions allowing to program and read the RTC Calendar
+ (Time and Date).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set the RTC current time.
+ * @param RTC_Format: specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_Format_BIN: Binary data format
+ * @arg RTC_Format_BCD: BCD data format
+ * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains
+ * the time configuration information for the RTC.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Time register is configured
+ * - ERROR: RTC Time register is not configured
+ */
+ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
+{
+ uint32_t tmpreg = 0;
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+
+ if (RTC_Format == RTC_Format_BIN)
+ {
+ if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ {
+ assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours));
+ assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12));
+ }
+ else
+ {
+ RTC_TimeStruct->RTC_H12 = 0x00;
+ assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours));
+ }
+ assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes));
+ assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds));
+ }
+ else
+ {
+ if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ {
+ tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
+ assert_param(IS_RTC_HOUR12(tmpreg));
+ assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12));
+ }
+ else
+ {
+ RTC_TimeStruct->RTC_H12 = 0x00;
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours)));
+ }
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds)));
+ }
+
+ /* Check the input parameters format */
+ if (RTC_Format != RTC_Format_BIN)
+ {
+ tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \
+ ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \
+ ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \
+ ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16));
+ }
+ else
+ {
+ tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \
+ ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \
+ ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \
+ (((uint32_t)RTC_TimeStruct->RTC_H12) << 16));
+ }
+
+ /* Disable the write protection for RTC registers */
+ RTC->WPR = 0xCA;
+ RTC->WPR = 0x53;
+
+ /* Set Initialization mode */
+ if (RTC_EnterInitMode() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ /* Set the RTC_TR register */
+ RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
+
+ /* Exit Initialization mode */
+ RTC_ExitInitMode();
+
+ /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)
+ {
+ if (RTC_WaitForSynchro() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+
+ }
+ /* Enable the write protection for RTC registers */
+ RTC->WPR = 0xFF;
+
+ return status;
+}
+
+/**
+ * @brief Fills each RTC_TimeStruct member with its default value
+ * (Time = 00h:00min:00sec).
+ * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be
+ * initialized.
+ * @retval None
+ */
+void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct)
+{
+ /* Time = 00h:00min:00sec */
+ RTC_TimeStruct->RTC_H12 = RTC_H12_AM;
+ RTC_TimeStruct->RTC_Hours = 0;
+ RTC_TimeStruct->RTC_Minutes = 0;
+ RTC_TimeStruct->RTC_Seconds = 0;
+}
+
+/**
+ * @brief Get the RTC current Time.
+ * @param RTC_Format: specifies the format of the returned parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_Format_BIN: Binary data format
+ * @arg RTC_Format_BCD: BCD data format
+ * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will
+ * contain the returned current time configuration.
+ * @retval None
+ */
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+
+ /* Get the RTC_TR register */
+ tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK);
+
+ /* Fill the structure fields with the read parameters */
+ RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);
+ RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);
+ RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
+ RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16);
+
+ /* Check the input parameters format */
+ if (RTC_Format == RTC_Format_BIN)
+ {
+ /* Convert the structure parameters to Binary format */
+ RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
+ RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes);
+ RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds);
+ }
+}
+
+/**
+ * @brief Gets the RTC current Calendar Subseconds value.
+ * @note This function freeze the Time and Date registers after reading the
+ * SSR register.
+ * @param None
+ * @retval RTC current Calendar Subseconds value.
+ */
+uint32_t RTC_GetSubSecond(void)
+{
+ uint32_t tmpreg = 0;
+
+ /* Get subseconds values from the correspondent registers*/
+ tmpreg = (uint32_t)(RTC->SSR);
+
+ /* Read DR register to unfroze calendar registers */
+ (void) (RTC->DR);
+
+ return (tmpreg);
+}
+
+/**
+ * @brief Set the RTC current date.
+ * @param RTC_Format: specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_Format_BIN: Binary data format
+ * @arg RTC_Format_BCD: BCD data format
+ * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains
+ * the date configuration information for the RTC.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Date register is configured
+ * - ERROR: RTC Date register is not configured
+ */
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
+{
+ uint32_t tmpreg = 0;
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+
+ if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10))
+ {
+ RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A;
+ }
+ if (RTC_Format == RTC_Format_BIN)
+ {
+ assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year));
+ assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month));
+ assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date));
+ }
+ else
+ {
+ assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year)));
+ tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);
+ assert_param(IS_RTC_MONTH(tmpreg));
+ tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);
+ assert_param(IS_RTC_DATE(tmpreg));
+ }
+ assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay));
+
+ /* Check the input parameters format */
+ if (RTC_Format != RTC_Format_BIN)
+ {
+ tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \
+ (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \
+ ((uint32_t)RTC_DateStruct->RTC_Date) | \
+ (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13));
+ }
+ else
+ {
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \
+ ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \
+ ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \
+ ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13));
+ }
+
+ /* Disable the write protection for RTC registers */
+ RTC->WPR = 0xCA;
+ RTC->WPR = 0x53;
+
+ /* Set Initialization mode */
+ if (RTC_EnterInitMode() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ /* Set the RTC_DR register */
+ RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK);
+
+ /* Exit Initialization mode */
+ RTC_ExitInitMode();
+
+ /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)
+ {
+ if (RTC_WaitForSynchro() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ /* Enable the write protection for RTC registers */
+ RTC->WPR = 0xFF;
+
+ return status;
+}
+
+/**
+ * @brief Fills each RTC_DateStruct member with its default value
+ * (Monday, January 01 xx00).
+ * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be
+ * initialized.
+ * @retval None
+ */
+void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct)
+{
+ /* Monday, January 01 xx00 */
+ RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday;
+ RTC_DateStruct->RTC_Date = 1;
+ RTC_DateStruct->RTC_Month = RTC_Month_January;
+ RTC_DateStruct->RTC_Year = 0;
+}
+
+/**
+ * @brief Get the RTC current date.
+ * @param RTC_Format: specifies the format of the returned parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_Format_BIN: Binary data format
+ * @arg RTC_Format_BCD: BCD data format
+ * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will
+ * contain the returned current date configuration.
+ * @retval None
+ */
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+
+ /* Get the RTC_TR register */
+ tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK);
+
+ /* Fill the structure fields with the read parameters */
+ RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);
+ RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);
+ RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU));
+ RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13);
+
+ /* Check the input parameters format */
+ if (RTC_Format == RTC_Format_BIN)
+ {
+ /* Convert the structure parameters to Binary format */
+ RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year);
+ RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);
+ RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);
+ RTC_DateStruct->RTC_WeekDay = (uint8_t)(RTC_DateStruct->RTC_WeekDay);
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Group3 Alarms configuration functions
+ * @brief Alarms (Alarm A and Alarm B) configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Alarms (Alarm A and Alarm B) configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to program and read the RTC Alarms.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set the specified RTC Alarm.
+ * @note The Alarm register can only be written when the corresponding Alarm
+ * is disabled (Use the RTC_AlarmCmd(DISABLE)).
+ * @param RTC_Format: specifies the format of the returned parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_Format_BIN: Binary data format
+ * @arg RTC_Format_BCD: BCD data format
+ * @param RTC_Alarm: specifies the alarm to be configured.
+ * This parameter can be one of the following values:
+ * @arg RTC_Alarm_A: to select Alarm A
+ * @arg RTC_Alarm_B: to select Alarm B
+ * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that
+ * contains the alarm configuration parameters.
+ * @retval None
+ */
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+ assert_param(IS_RTC_ALARM(RTC_Alarm));
+ assert_param(IS_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask));
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel));
+
+ if (RTC_Format == RTC_Format_BIN)
+ {
+ if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ {
+ assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
+ assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));
+ }
+ else
+ {
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;
+ assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
+ }
+ assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes));
+ assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds));
+
+ if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
+ }
+ else
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
+ }
+ }
+ else
+ {
+ if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ {
+ tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours);
+ assert_param(IS_RTC_HOUR12(tmpreg));
+ assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));
+ }
+ else
+ {
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)));
+ }
+
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)));
+
+ if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)
+ {
+ tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
+ }
+ else
+ {
+ tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
+ }
+ }
+
+ /* Check the input parameters format */
+ if (RTC_Format != RTC_Format_BIN)
+ {
+ tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \
+ ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \
+ ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \
+ ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \
+ ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \
+ ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \
+ ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask));
+ }
+ else
+ {
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \
+ ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \
+ ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \
+ ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \
+ ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \
+ ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \
+ ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask));
+ }
+
+ /* Disable the write protection for RTC registers */
+ RTC->WPR = 0xCA;
+ RTC->WPR = 0x53;
+
+ /* Configure the Alarm register */
+ if (RTC_Alarm == RTC_Alarm_A)
+ {
+ RTC->ALRMAR = (uint32_t)tmpreg;
+ }
+ else
+ {
+ RTC->ALRMBR = (uint32_t)tmpreg;
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WPR = 0xFF;
+}
+
+/**
+ * @brief Fills each RTC_AlarmStruct member with its default value
+ * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask =
+ * all fields are masked).
+ * @param RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which
+ * will be initialized.
+ * @retval None
+ */
+void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct)
+{
+ /* Alarm Time Settings : Time = 00h:00mn:00sec */
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM;
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0;
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0;
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0;
+
+ /* Alarm Date Settings : Date = 1st day of the month */
+ RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date;
+ RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1;
+
+ /* Alarm Masks Settings : Mask = all fields are not masked */
+ RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None;
+}
+
+/**
+ * @brief Get the RTC Alarm value and masks.
+ * @param RTC_Format: specifies the format of the output parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_Format_BIN: Binary data format
+ * @arg RTC_Format_BCD: BCD data format
+ * @param RTC_Alarm: specifies the alarm to be read.
+ * This parameter can be one of the following values:
+ * @arg RTC_Alarm_A: to select Alarm A
+ * @arg RTC_Alarm_B: to select Alarm B
+ * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will
+ * contains the output alarm configuration values.
+ * @retval None
+ */
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+ assert_param(IS_RTC_ALARM(RTC_Alarm));
+
+ /* Get the RTC_ALRMxR register */
+ if (RTC_Alarm == RTC_Alarm_A)
+ {
+ tmpreg = (uint32_t)(RTC->ALRMAR);
+ }
+ else
+ {
+ tmpreg = (uint32_t)(RTC->ALRMBR);
+ }
+
+ /* Fill the structure with the read parameters */
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \
+ RTC_ALRMAR_HU)) >> 16);
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \
+ RTC_ALRMAR_MNU)) >> 8);
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \
+ RTC_ALRMAR_SU));
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);
+ RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);
+ RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
+ RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All);
+
+ if (RTC_Format == RTC_Format_BIN)
+ {
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
+ RTC_AlarmTime.RTC_Hours);
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
+ RTC_AlarmTime.RTC_Minutes);
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
+ RTC_AlarmTime.RTC_Seconds);
+ RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
+ }
+}
+
+/**
+ * @brief Enables or disables the specified RTC Alarm.
+ * @param RTC_Alarm: specifies the alarm to be configured.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_Alarm_A: to select Alarm A
+ * @arg RTC_Alarm_B: to select Alarm B
+ * @param NewState: new state of the specified alarm.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Alarm is enabled/disabled
+ * - ERROR: RTC Alarm is not enabled/disabled
+ */
+ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState)
+{
+ __IO uint32_t alarmcounter = 0x00;
+ uint32_t alarmstatus = 0x00;
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_CMD_ALARM(RTC_Alarm));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WPR = 0xCA;
+ RTC->WPR = 0x53;
+
+ /* Configure the Alarm state */
+ if (NewState != DISABLE)
+ {
+ RTC->CR |= (uint32_t)RTC_Alarm;
+
+ status = SUCCESS;
+ }
+ else
+ {
+ /* Disable the Alarm in RTC_CR register */
+ RTC->CR &= (uint32_t)~RTC_Alarm;
+
+ /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
+ do
+ {
+ alarmstatus = RTC->ISR & (RTC_Alarm >> 8);
+ alarmcounter++;
+ } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00));
+
+ if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WPR = 0xFF;
+
+ return status;
+}
+
+/**
+ * @brief Configures the RTC AlarmA/B Subseconds value and mask.
+ * @note This function is performed only when the Alarm is disabled.
+ * @param RTC_Alarm: specifies the alarm to be configured.
+ * This parameter can be one of the following values:
+ * @arg RTC_Alarm_A: to select Alarm A
+ * @arg RTC_Alarm_B: to select Alarm B
+ * @param RTC_AlarmSubSecondValue: specifies the Subseconds value.
+ * This parameter can be a value from 0 to 0x00007FFF.
+ * @param RTC_AlarmSubSecondMask: specifies the Subseconds Mask.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_AlarmSubSecondMask_All : All Alarm SS fields are masked.
+ * There is no comparison on sub seconds for Alarm.
+ * @arg RTC_AlarmSubSecondMask_SS14_1 : SS[14:1] are don't care in Alarm comparison.
+ * Only SS[0] is compared
+ * @arg RTC_AlarmSubSecondMask_SS14_2 : SS[14:2] are don't care in Alarm comparison.
+ * Only SS[1:0] are compared
+ * @arg RTC_AlarmSubSecondMask_SS14_3 : SS[14:3] are don't care in Alarm comparison.
+ * Only SS[2:0] are compared
+ * @arg RTC_AlarmSubSecondMask_SS14_4 : SS[14:4] are don't care in Alarm comparison.
+ * Only SS[3:0] are compared
+ * @arg RTC_AlarmSubSecondMask_SS14_5 : SS[14:5] are don't care in Alarm comparison.
+ * Only SS[4:0] are compared
+ * @arg RTC_AlarmSubSecondMask_SS14_6 : SS[14:6] are don't care in Alarm comparison.
+ * Only SS[5:0] are compared
+ * @arg RTC_AlarmSubSecondMask_SS14_7 : SS[14:7] are don't care in Alarm comparison.
+ * Only SS[6:0] are compared
+ * @arg RTC_AlarmSubSecondMask_SS14_8 : SS[14:8] are don't care in Alarm comparison.
+ * Only SS[7:0] are compared
+ * @arg RTC_AlarmSubSecondMask_SS14_9 : SS[14:9] are don't care in Alarm comparison.
+ * Only SS[8:0] are compared
+ * @arg RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison.
+ * Only SS[9:0] are compared
+ * @arg RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison.
+ * Only SS[10:0] are compared
+ * @arg RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison.
+ * Only SS[11:0] are compared
+ * @arg RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison.
+ * Only SS[12:0] are compared
+ * @arg RTC_AlarmSubSecondMask_SS14 : SS[14] is don't care in Alarm comparison.
+ * Only SS[13:0] are compared
+ * @arg RTC_AlarmSubSecondMask_None : SS[14:0] are compared and must match
+ * to activate alarm
+ * @retval None
+ */
+void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALARM(RTC_Alarm));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(RTC_AlarmSubSecondMask));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WPR = 0xCA;
+ RTC->WPR = 0x53;
+
+ /* Configure the Alarm A or Alarm B SubSecond registers */
+ tmpreg = (uint32_t) (uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask);
+
+ if (RTC_Alarm == RTC_Alarm_A)
+ {
+ /* Configure the AlarmA SubSecond register */
+ RTC->ALRMASSR = tmpreg;
+ }
+ else
+ {
+ /* Configure the Alarm B SubSecond register */
+ RTC->ALRMBSSR = tmpreg;
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WPR = 0xFF;
+
+}
+
+/**
+ * @brief Gets the RTC Alarm Subseconds value.
+ * @param RTC_Alarm: specifies the alarm to be read.
+ * This parameter can be one of the following values:
+ * @arg RTC_Alarm_A: to select Alarm A
+ * @arg RTC_Alarm_B: to select Alarm B
+ * @param None
+ * @retval RTC Alarm Subseconds value.
+ */
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm)
+{
+ uint32_t tmpreg = 0;
+
+ /* Get the RTC_ALRMxR register */
+ if (RTC_Alarm == RTC_Alarm_A)
+ {
+ tmpreg = (uint32_t)((RTC->ALRMASSR) & RTC_ALRMASSR_SS);
+ }
+ else
+ {
+ tmpreg = (uint32_t)((RTC->ALRMBSSR) & RTC_ALRMBSSR_SS);
+ }
+
+ return (tmpreg);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Group4 WakeUp Timer configuration functions
+ * @brief WakeUp Timer configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### WakeUp Timer configuration functions #####
+ ===============================================================================
+ [..] This section provide functions allowing to program and read the RTC WakeUp.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the RTC Wakeup clock source.
+ * @note The WakeUp Clock source can only be changed when the RTC WakeUp
+ * is disabled (Use the RTC_WakeUpCmd(DISABLE)).
+ * @param RTC_WakeUpClock: Wakeup Clock source.
+ * This parameter can be one of the following values:
+ * @arg RTC_WakeUpClock_RTCCLK_Div16: RTC Wakeup Counter Clock = RTCCLK/16
+ * @arg RTC_WakeUpClock_RTCCLK_Div8: RTC Wakeup Counter Clock = RTCCLK/8
+ * @arg RTC_WakeUpClock_RTCCLK_Div4: RTC Wakeup Counter Clock = RTCCLK/4
+ * @arg RTC_WakeUpClock_RTCCLK_Div2: RTC Wakeup Counter Clock = RTCCLK/2
+ * @arg RTC_WakeUpClock_CK_SPRE_16bits: RTC Wakeup Counter Clock = CK_SPRE
+ * @arg RTC_WakeUpClock_CK_SPRE_17bits: RTC Wakeup Counter Clock = CK_SPRE
+ * @retval None
+ */
+void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WPR = 0xCA;
+ RTC->WPR = 0x53;
+
+ /* Clear the Wakeup Timer clock source bits in CR register */
+ RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL;
+
+ /* Configure the clock source */
+ RTC->CR |= (uint32_t)RTC_WakeUpClock;
+
+ /* Enable the write protection for RTC registers */
+ RTC->WPR = 0xFF;
+}
+
+/**
+ * @brief Configures the RTC Wakeup counter.
+ * @note The RTC WakeUp counter can only be written when the RTC WakeUp
+ * is disabled (Use the RTC_WakeUpCmd(DISABLE)).
+ * @param RTC_WakeUpCounter: specifies the WakeUp counter.
+ * This parameter can be a value from 0x0000 to 0xFFFF.
+ * @retval None
+ */
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WPR = 0xCA;
+ RTC->WPR = 0x53;
+
+ /* Configure the Wakeup Timer counter */
+ RTC->WUTR = (uint32_t)RTC_WakeUpCounter;
+
+ /* Enable the write protection for RTC registers */
+ RTC->WPR = 0xFF;
+}
+
+/**
+ * @brief Returns the RTC WakeUp timer counter value.
+ * @param None
+ * @retval The RTC WakeUp Counter value.
+ */
+uint32_t RTC_GetWakeUpCounter(void)
+{
+ /* Get the counter value */
+ return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT));
+}
+
+/**
+ * @brief Enables or Disables the RTC WakeUp timer.
+ * @param NewState: new state of the WakeUp timer.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+ErrorStatus RTC_WakeUpCmd(FunctionalState NewState)
+{
+ __IO uint32_t wutcounter = 0x00;
+ uint32_t wutwfstatus = 0x00;
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WPR = 0xCA;
+ RTC->WPR = 0x53;
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the Wakeup Timer */
+ RTC->CR |= (uint32_t)RTC_CR_WUTE;
+ status = SUCCESS;
+ }
+ else
+ {
+ /* Disable the Wakeup Timer */
+ RTC->CR &= (uint32_t)~RTC_CR_WUTE;
+ /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+ do
+ {
+ wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;
+ wutcounter++;
+ } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
+
+ if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WPR = 0xFF;
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Group5 Daylight Saving configuration functions
+ * @brief Daylight Saving configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Daylight Saving configuration functions #####
+ ===============================================================================
+ [..] This section provide functions allowing to configure the RTC DayLight Saving.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Adds or substract one hour from the current time.
+ * @param RTC_DayLightSaveOperation: the value of hour adjustment.
+ * This parameter can be one of the following values:
+ * @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time)
+ * @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time)
+ * @param RTC_StoreOperation: Specifies the value to be written in the BCK bit
+ * in CR register to store the operation.
+ * This parameter can be one of the following values:
+ * @arg RTC_StoreOperation_Reset: BCK Bit Reset
+ * @arg RTC_StoreOperation_Set: BCK Bit Set
+ * @retval None
+ */
+void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving));
+ assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WPR = 0xCA;
+ RTC->WPR = 0x53;
+
+ /* Clear the bits to be configured */
+ RTC->CR &= (uint32_t)~(RTC_CR_BCK);
+
+ /* Configure the RTC_CR register */
+ RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation);
+
+ /* Enable the write protection for RTC registers */
+ RTC->WPR = 0xFF;
+}
+
+/**
+ * @brief Returns the RTC Day Light Saving stored operation.
+ * @param None
+ * @retval RTC Day Light Saving stored operation.
+ * - RTC_StoreOperation_Reset
+ * - RTC_StoreOperation_Set
+ */
+uint32_t RTC_GetStoreOperation(void)
+{
+ return (RTC->CR & RTC_CR_BCK);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Group6 Output pin Configuration function
+ * @brief Output pin Configuration function
+ *
+@verbatim
+ ===============================================================================
+ ##### Output pin Configuration function #####
+ ===============================================================================
+ [..] This section provide functions allowing to configure the RTC Output source.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the RTC output source (AFO_ALARM).
+ * @param RTC_Output: Specifies which signal will be routed to the RTC output.
+ * This parameter can be one of the following values:
+ * @arg RTC_Output_Disable: No output selected
+ * @arg RTC_Output_AlarmA: signal of AlarmA mapped to output
+ * @arg RTC_Output_AlarmB: signal of AlarmB mapped to output
+ * @arg RTC_Output_WakeUp: signal of WakeUp mapped to output
+ * @param RTC_OutputPolarity: Specifies the polarity of the output signal.
+ * This parameter can be one of the following:
+ * @arg RTC_OutputPolarity_High: The output pin is high when the
+ * ALRAF/ALRBF/WUTF is high (depending on OSEL)
+ * @arg RTC_OutputPolarity_Low: The output pin is low when the
+ * ALRAF/ALRBF/WUTF is high (depending on OSEL)
+ * @retval None
+ */
+void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_OUTPUT(RTC_Output));
+ assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WPR = 0xCA;
+ RTC->WPR = 0x53;
+
+ /* Clear the bits to be configured */
+ RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL);
+
+ /* Configure the output selection and polarity */
+ RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity);
+
+ /* Enable the write protection for RTC registers */
+ RTC->WPR = 0xFF;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Group7 Digital Calibration configuration functions
+ * @brief Digital Calibration configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Digital Calibration configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the RTC clock to be output through the relative
+ * pin.
+ * @param NewState: new state of the digital calibration Output.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RTC_CalibOutputCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WPR = 0xCA;
+ RTC->WPR = 0x53;
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the RTC clock output */
+ RTC->CR |= (uint32_t)RTC_CR_COE;
+ }
+ else
+ {
+ /* Disable the RTC clock output */
+ RTC->CR &= (uint32_t)~RTC_CR_COE;
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WPR = 0xFF;
+}
+
+/**
+ * @brief Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ * @param RTC_CalibOutput : Select the Calibration output Selection .
+ * This parameter can be one of the following values:
+ * @arg RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz.
+ * @arg RTC_CalibOutput_1Hz : A signal has a regular waveform at 1Hz.
+ * @retval None
+*/
+void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WPR = 0xCA;
+ RTC->WPR = 0x53;
+
+ /*clear flags before config*/
+ RTC->CR &= (uint32_t)~(RTC_CR_COSEL);
+
+ /* Configure the RTC_CR register */
+ RTC->CR |= (uint32_t)RTC_CalibOutput;
+
+ /* Enable the write protection for RTC registers */
+ RTC->WPR = 0xFF;
+}
+
+/**
+ * @brief Configures the Smooth Calibration Settings.
+ * @param RTC_SmoothCalibPeriod : Select the Smooth Calibration Period.
+ * This parameter can be can be one of the following values:
+ * @arg RTC_SmoothCalibPeriod_32sec : The smooth calibration periode is 32s.
+ * @arg RTC_SmoothCalibPeriod_16sec : The smooth calibration periode is 16s.
+ * @arg RTC_SmoothCalibPeriod_8sec : The smooth calibartion periode is 8s.
+ * @param RTC_SmoothCalibPlusPulses : Select to Set or reset the CALP bit.
+ * This parameter can be one of the following values:
+ * @arg RTC_SmoothCalibPlusPulses_Set : Add one RTCCLK puls every 2**11 pulses.
+ * @arg RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added.
+ * @param RTC_SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
+ * This parameter can be one any value from 0 to 0x000001FF.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Calib registers are configured
+ * - ERROR: RTC Calib registers are not configured
+*/
+ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
+ uint32_t RTC_SmoothCalibPlusPulses,
+ uint32_t RTC_SmouthCalibMinusPulsesValue)
+{
+ ErrorStatus status = ERROR;
+ uint32_t recalpfcount = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(RTC_SmoothCalibPeriod));
+ assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses));
+ assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WPR = 0xCA;
+ RTC->WPR = 0x53;
+
+ /* check if a calibration is pending*/
+ if ((RTC->ISR & RTC_ISR_RECALPF) != RESET)
+ {
+ /* wait until the Calibration is completed*/
+ while (((RTC->ISR & RTC_ISR_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT))
+ {
+ recalpfcount++;
+ }
+ }
+
+ /* check if the calibration pending is completed or if there is no calibration operation at all*/
+ if ((RTC->ISR & RTC_ISR_RECALPF) == RESET)
+ {
+ /* Configure the Smooth calibration settings */
+ RTC->CALR = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses | (uint32_t)RTC_SmouthCalibMinusPulsesValue);
+
+ status = SUCCESS;
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WPR = 0xFF;
+
+ return (ErrorStatus)(status);
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup RTC_Group8 TimeStamp configuration functions
+ * @brief TimeStamp configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### TimeStamp configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or Disables the RTC TimeStamp functionality with the
+ * specified time stamp pin stimulating edge.
+ * @param RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is
+ * activated.
+ * This parameter can be one of the following:
+ * @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising
+ * edge of the related pin.
+ * @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the
+ * falling edge of the related pin.
+ * @param NewState: new state of the TimeStamp.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ /* Get the RTC_CR register and clear the bits to be configured */
+ tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
+
+ /* Get the new configuration */
+ if (NewState != DISABLE)
+ {
+ tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE);
+ }
+ else
+ {
+ tmpreg |= (uint32_t)(RTC_TimeStampEdge);
+ }
+
+ /* Disable the write protection for RTC registers */
+ RTC->WPR = 0xCA;
+ RTC->WPR = 0x53;
+
+ /* Configure the Time Stamp TSEDGE and Enable bits */
+ RTC->CR = (uint32_t)tmpreg;
+
+ /* Enable the write protection for RTC registers */
+ RTC->WPR = 0xFF;
+}
+
+/**
+ * @brief Gets the RTC TimeStamp value and masks.
+ * @param RTC_Format: specifies the format of the output parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_Format_BIN: Binary data format
+ * @arg RTC_Format_BCD: BCD data format
+ * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will
+ * contains the TimeStamp time values.
+ * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will
+ * contains the TimeStamp date values.
+ * @retval None
+ */
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct,
+ RTC_DateTypeDef* RTC_StampDateStruct)
+{
+ uint32_t tmptime = 0, tmpdate = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+
+ /* Get the TimeStamp time and date registers values */
+ tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK);
+ tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK);
+
+ /* Fill the Time structure fields with the read parameters */
+ RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);
+ RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);
+ RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
+ RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);
+
+ /* Fill the Date structure fields with the read parameters */
+ RTC_StampDateStruct->RTC_Year = 0;
+ RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);
+ RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
+ RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
+
+ /* Check the input parameters format */
+ if (RTC_Format == RTC_Format_BIN)
+ {
+ /* Convert the Time structure parameters to Binary format */
+ RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours);
+ RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes);
+ RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds);
+
+ /* Convert the Date structure parameters to Binary format */
+ RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month);
+ RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date);
+ RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay);
+ }
+}
+
+/**
+ * @brief Gets the RTC timestamp Subseconds value.
+ * @param None
+ * @retval RTC current timestamp Subseconds value.
+ */
+uint32_t RTC_GetTimeStampSubSecond(void)
+{
+ /* Get timestamp subseconds values from the correspondent registers */
+ return (uint32_t)(RTC->TSSSR);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Group9 Tampers configuration functions
+ * @brief Tampers configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Tampers configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the select Tamper pin edge.
+ * @param RTC_Tamper: Selected tamper pin.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_Tamper_1: Select Tamper 1.
+ * @arg RTC_Tamper_2: Select Tamper 2.
+ * @arg RTC_Tamper_3: Select Tamper 3.
+ * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that
+ * stimulates tamper event.
+ * This parameter can be one of the following values:
+ * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event.
+ * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event.
+ * @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event.
+ * @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event.
+ * @retval None
+ */
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER(RTC_Tamper));
+ assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger));
+
+ /* Check if the active level for Tamper is rising edge (Low level)*/
+ if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge)
+ {
+ /* Configure the RTC_TAFCR register */
+ RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1));
+ }
+ else
+ {
+ /* Configure the RTC_TAFCR register */
+ RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1);
+ }
+}
+
+/**
+ * @brief Enables or Disables the Tamper detection.
+ * @param RTC_Tamper: Selected tamper pin.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_Tamper_1: Select Tamper 1.
+ * @arg RTC_Tamper_2: Select Tamper 2.
+ * @arg RTC_Tamper_3: Select Tamper 3.
+ * @param NewState: new state of the tamper pin.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER(RTC_Tamper));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected Tamper pin */
+ RTC->TAFCR |= (uint32_t)RTC_Tamper;
+ }
+ else
+ {
+ /* Disable the selected Tamper pin */
+ RTC->TAFCR &= (uint32_t)~RTC_Tamper;
+ }
+}
+
+/**
+ * @brief Configures the Tampers Filter.
+ * @param RTC_TamperFilter: Specifies the tampers filter.
+ * This parameter can be one of the following values:
+ * @arg RTC_TamperFilter_Disable: Tamper filter is disabled.
+ * @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive
+ * samples at the active level
+ * @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive
+ * samples at the active level
+ * @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive
+ * samples at the active level
+ * @retval None
+ */
+void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter));
+
+ /* Clear TAMPFLT[1:0] bits in the RTC_TAFCR register */
+ RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFLT);
+
+ /* Configure the RTC_TAFCR register */
+ RTC->TAFCR |= (uint32_t)RTC_TamperFilter;
+}
+
+/**
+ * @brief Configures the Tampers Sampling Frequency.
+ * @param RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency.
+ * This parameter can be one of the following values:
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled
+ * with a frequency = RTCCLK / 32768
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled
+ * with a frequency = RTCCLK / 16384
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled
+ * with a frequency = RTCCLK / 8192
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled
+ * with a frequency = RTCCLK / 4096
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled
+ * with a frequency = RTCCLK / 2048
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled
+ * with a frequency = RTCCLK / 1024
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled
+ * with a frequency = RTCCLK / 512
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled
+ * with a frequency = RTCCLK / 256
+ * @retval None
+ */
+void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq));
+
+ /* Clear TAMPFREQ[2:0] bits in the RTC_TAFCR register */
+ RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFREQ);
+
+ /* Configure the RTC_TAFCR register */
+ RTC->TAFCR |= (uint32_t)RTC_TamperSamplingFreq;
+}
+
+/**
+ * @brief Configures the Tampers Pins input Precharge Duration.
+ * @param RTC_TamperPrechargeDuration: Specifies the Tampers Pins input
+ * Precharge Duration.
+ * This parameter can be one of the following values:
+ * @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle
+ * @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle
+ * @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle
+ * @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle
+ * @retval None
+ */
+void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration));
+
+ /* Clear TAMPPRCH[1:0] bits in the RTC_TAFCR register */
+ RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPPRCH);
+
+ /* Configure the RTC_TAFCR register */
+ RTC->TAFCR |= (uint32_t)RTC_TamperPrechargeDuration;
+}
+
+/**
+ * @brief Enables or Disables the TimeStamp on Tamper Detection Event.
+ * @note The timestamp is valid even the TSE bit in tamper control register
+ * is reset.
+ * @param NewState: new state of the timestamp on tamper event.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Save timestamp on tamper detection event */
+ RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPTS;
+ }
+ else
+ {
+ /* Tamper detection does not cause a timestamp to be saved */
+ RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPTS;
+ }
+}
+
+/**
+ * @brief Enables or Disables the Precharge of Tamper pin.
+ * @param NewState: new state of tamper pull up.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RTC_TamperPullUpCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable precharge of the selected Tamper pin */
+ RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPPUDIS;
+ }
+ else
+ {
+ /* Disable precharge of the selected Tamper pin */
+ RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPPUDIS;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Group10 Backup Data Registers configuration functions
+ * @brief Backup Data Registers configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Backup Data Registers configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Writes a data in a specified RTC Backup data register.
+ * @param RTC_BKP_DR: RTC Backup data Register number.
+ * This parameter can be: RTC_BKP_DRx where x can be from 0 to 15 to
+ * specify the register.
+ * @param Data: Data to be written in the specified RTC Backup data register.
+ * @retval None
+ */
+void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_BKP(RTC_BKP_DR));
+
+ tmp = RTC_BASE + 0x50;
+ tmp += (RTC_BKP_DR * 4);
+
+ /* Write the specified register */
+ *(__IO uint32_t *)tmp = (uint32_t)Data;
+}
+
+/**
+ * @brief Reads data from the specified RTC Backup data Register.
+ * @param RTC_BKP_DR: RTC Backup data Register number.
+ * This parameter can be: RTC_BKP_DRx where x can be from 0 to 15 to
+ * specify the register.
+ * @retval None
+ */
+uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_BKP(RTC_BKP_DR));
+
+ tmp = RTC_BASE + 0x50;
+ tmp += (RTC_BKP_DR * 4);
+
+ /* Read the specified register */
+ return (*(__IO uint32_t *)tmp);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Group11 Output Type Config configuration functions
+ * @brief Output Type Config configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Output Type Config configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the RTC Output Pin mode.
+ * @param RTC_OutputType: specifies the RTC Output (PC13) pin mode.
+ * This parameter can be one of the following values:
+ * @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in
+ * Open Drain mode.
+ * @arg RTC_OutputType_PushPull: RTC Output (PC13) is configured in
+ * Push Pull mode.
+ * @retval None
+ */
+void RTC_OutputTypeConfig(uint32_t RTC_OutputType)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType));
+
+ RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE);
+ RTC->TAFCR |= (uint32_t)(RTC_OutputType);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Group12 Shift control synchronisation functions
+ * @brief Shift control synchronisation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Shift control synchronisation functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the Synchronization Shift Control Settings.
+ * @note When REFCKON is set, firmware must not write to Shift control register
+ * @param RTC_ShiftAdd1S : Select to add or not 1 second to the time Calendar.
+ * This parameter can be one of the following values :
+ * @arg RTC_ShiftAdd1S_Set : Add one second to the clock calendar.
+ * @arg RTC_ShiftAdd1S_Reset: No effect.
+ * @param RTC_ShiftSubFS: Select the number of Second Fractions to Substitute.
+ * This parameter can be one any value from 0 to 0x7FFF.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Shift registers are configured
+ * - ERROR: RTC Shift registers are not configured
+*/
+ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS)
+{
+ ErrorStatus status = ERROR;
+ uint32_t shpfcount = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S));
+ assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WPR = 0xCA;
+ RTC->WPR = 0x53;
+
+ /* Check if a Shift is pending*/
+ if ((RTC->ISR & RTC_ISR_SHPF) != RESET)
+ {
+ /* Wait until the shift is completed*/
+ while (((RTC->ISR & RTC_ISR_SHPF) != RESET) && (shpfcount != SHPF_TIMEOUT))
+ {
+ shpfcount++;
+ }
+ }
+
+ /* Check if the Shift pending is completed or if there is no Shift operation at all*/
+ if ((RTC->ISR & RTC_ISR_SHPF) == RESET)
+ {
+ /* check if the reference clock detection is disabled */
+ if((RTC->CR & RTC_CR_REFCKON) == RESET)
+ {
+ /* Configure the Shift settings */
+ RTC->SHIFTR = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S);
+
+ if(RTC_WaitForSynchro() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ else
+ {
+ status = ERROR;
+ }
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WPR = 0xFF;
+
+ return (ErrorStatus)(status);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Group13 Interrupts and flags management functions
+ * @brief Interrupts and flags management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupts and flags management functions #####
+ ===============================================================================
+ [..] All RTC interrupts are connected to the EXTI controller.
+ (+) To enable the RTC Alarm interrupt, the following sequence is required:
+ (++) Configure and enable the EXTI Line 17 in interrupt mode and select
+ the rising edge sensitivity using the EXTI_Init() function.
+ (++) Configure and enable the RTC_Alarm IRQ channel in the NVIC using
+ the NVIC_Init() function.
+ (++) Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B)
+ using the RTC_SetAlarm() and RTC_AlarmCmd() functions.
+ (+) To enable the RTC Wakeup interrupt, the following sequence is required:
+ (++) Configure and enable the EXTI Line 20 in interrupt mode and select
+ the rising edge sensitivity using the EXTI_Init() function.
+ (++) Configure and enable the RTC_WKUP IRQ channel in the NVIC using
+ the NVIC_Init() function.
+ (++) Configure the RTC to generate the RTC wakeup timer event using the
+ RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd()
+ functions.
+ (+) To enable the RTC Tamper interrupt, the following sequence is required:
+ (++) Configure and enable the EXTI Line 19 in interrupt mode and select
+ the rising edge sensitivity using the EXTI_Init() function.
+ (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using
+ the NVIC_Init() function.
+ (++) Configure the RTC to detect the RTC tamper event using the
+ RTC_TamperTriggerConfig() and RTC_TamperCmd() functions.
+ (+) To enable the RTC TimeStamp interrupt, the following sequence is required:
+ (++) Configure and enable the EXTI Line 19 in interrupt mode and select
+ the rising edge sensitivity using the EXTI_Init() function.
+ (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using
+ the NVIC_Init() function.
+ (++) Configure the RTC to detect the RTC time-stamp event using the
+ RTC_TimeStampCmd() functions.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the specified RTC interrupts.
+ * @param RTC_IT: specifies the RTC interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_TS: Time Stamp interrupt mask
+ * @arg RTC_IT_WUT: WakeUp Timer interrupt mask
+ * @arg RTC_IT_ALRB: Alarm B interrupt mask
+ * @arg RTC_IT_ALRA: Alarm A interrupt mask
+ * @arg RTC_IT_TAMP: Tamper event interrupt mask
+ * @param NewState: new state of the specified RTC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_CONFIG_IT(RTC_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WPR = 0xCA;
+ RTC->WPR = 0x53;
+
+ if (NewState != DISABLE)
+ {
+ /* Configure the Interrupts in the RTC_CR register */
+ RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE);
+ /* Configure the Tamper Interrupt in the RTC_TAFCR */
+ RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE);
+ }
+ else
+ {
+ /* Configure the Interrupts in the RTC_CR register */
+ RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE);
+ /* Configure the Tamper Interrupt in the RTC_TAFCR */
+ RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE);
+ }
+ /* Enable the write protection for RTC registers */
+ RTC->WPR = 0xFF;
+}
+
+/**
+ * @brief Checks whether the specified RTC flag is set or not.
+ * @param RTC_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg RTC_FLAG_RECALPF: RECALPF event flag
+ * @arg RTC_FLAG_TAMP3F: Tamper 3 event flag
+ * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag
+ * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag
+ * @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag
+ * @arg RTC_FLAG_TSF: Time Stamp event flag
+ * @arg RTC_FLAG_WUTF: WakeUp Timer flag
+ * @arg RTC_FLAG_ALRBF: Alarm B flag
+ * @arg RTC_FLAG_ALRAF: Alarm A flag
+ * @arg RTC_FLAG_INITF: Initialization mode flag
+ * @arg RTC_FLAG_RSF: Registers Synchronized flag
+ * @arg RTC_FLAG_INITS: Registers Configured flag
+ * @argRTC_FLAG_SHPF : Shift operation pending flag.
+ * @arg RTC_FLAG_WUTWF: WakeUp Timer Write flag
+ * @arg RTC_FLAG_ALRBWF: Alarm B Write flag
+ * @arg RTC_FLAG_ALRAWF: Alarm A write flag
+ * @retval The new state of RTC_FLAG (SET or RESET).
+ */
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
+
+ /* Get all the flags */
+ tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK);
+
+ /* Return the status of the flag */
+ if ((tmpreg & RTC_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RTC's pending flags.
+ * @param RTC_FLAG: specifies the RTC flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_FLAG_TAMP3F: Tamper 3 event flag
+ * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag
+ * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag
+ * @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag
+ * @arg RTC_FLAG_TSF: Time Stamp event flag
+ * @arg RTC_FLAG_WUTF: WakeUp Timer flag
+ * @arg RTC_FLAG_ALRBF: Alarm B flag
+ * @arg RTC_FLAG_ALRAF: Alarm A flag
+ * @arg RTC_FLAG_RSF: Registers Synchronized flag
+ * @retval None
+ */
+void RTC_ClearFlag(uint32_t RTC_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
+
+ /* Clear the Flags in the RTC_ISR register */
+ RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0001FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT)));
+}
+
+/**
+ * @brief Checks whether the specified RTC interrupt has occurred or not.
+ * @param RTC_IT: specifies the RTC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg RTC_IT_TS: Time Stamp interrupt
+ * @arg RTC_IT_WUT: WakeUp Timer interrupt
+ * @arg RTC_IT_ALRB: Alarm B interrupt
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @arg RTC_IT_TAMP1: Tamper1 event interrupt
+ * @arg RTC_IT_TAMP2: Tamper2 event interrupt
+ * @arg RTC_IT_TAMP3: Tamper3 event interrupt
+ * @retval The new state of RTC_IT (SET or RESET).
+ */
+ITStatus RTC_GetITStatus(uint32_t RTC_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint32_t tmpreg = 0, enablestatus = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_GET_IT(RTC_IT));
+
+ /* Get the TAMPER Interrupt enable bit and pending bit */
+ tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE));
+
+ /* Get the Interrupt enable Status */
+ enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & ((RTC_IT >> (RTC_IT >> 18)) >> 15)));
+
+ /* Get the Interrupt pending bit */
+ tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4)));
+
+ /* Get the status of the Interrupt */
+ if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RTC's interrupt pending bits.
+ * @param RTC_IT: specifies the RTC interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_TS: Time Stamp interrupt
+ * @arg RTC_IT_WUT: WakeUp Timer interrupt
+ * @arg RTC_IT_ALRB: Alarm B interrupt
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @arg RTC_IT_TAMP1: Tamper1 event interrupt
+ * @arg RTC_IT_TAMP2: Tamper2 event interrupt
+ * @arg RTC_IT_TAMP3: Tamper3 event interrupt
+ * @retval None
+ */
+void RTC_ClearITPendingBit(uint32_t RTC_IT)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_CLEAR_IT(RTC_IT));
+
+ /* Get the RTC_ISR Interrupt pending bits mask */
+ tmpreg = (uint32_t)(RTC_IT >> 4);
+
+ /* Clear the interrupt pending bits in the RTC_ISR register */
+ RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT)));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @brief Converts a 2 digit decimal to BCD format.
+ * @param Value: Byte to be converted.
+ * @retval Converted byte
+ */
+static uint8_t RTC_ByteToBcd2(uint8_t Value)
+{
+ uint8_t bcdhigh = 0;
+
+ while (Value >= 10)
+ {
+ bcdhigh++;
+ Value -= 10;
+ }
+
+ return ((uint8_t)(bcdhigh << 4) | Value);
+}
+
+/**
+ * @brief Convert from 2 digit BCD to Binary.
+ * @param Value: BCD value to be converted.
+ * @retval Converted word
+ */
+static uint8_t RTC_Bcd2ToByte(uint8_t Value)
+{
+ uint8_t tmp = 0;
+ tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
+ return (tmp + (Value & (uint8_t)0x0F));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_rtc.h Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,862 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_rtc.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the RTC firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_RTC_H
+#define __STM32F30x_RTC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RTC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief RTC Init structures definition
+ */
+typedef struct
+{
+ uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format.
+ This parameter can be a value of @ref RTC_Hour_Formats */
+
+ uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
+ This parameter must be set to a value lower than 0x7F */
+
+ uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
+ This parameter must be set to a value lower than 0x1FFF */
+}RTC_InitTypeDef;
+
+/**
+ * @brief RTC Time structure definition
+ */
+typedef struct
+{
+ uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour.
+ This parameter must be set to a value in the 0-12 range
+ if the RTC_HourFormat_12 is selected or 0-23 range if
+ the RTC_HourFormat_24 is selected. */
+
+ uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes.
+ This parameter must be set to a value in the 0-59 range. */
+
+ uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds.
+ This parameter must be set to a value in the 0-59 range. */
+
+ uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time.
+ This parameter can be a value of @ref RTC_AM_PM_Definitions */
+}RTC_TimeTypeDef;
+
+/**
+ * @brief RTC Date structure definition
+ */
+typedef struct
+{
+ uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.
+ This parameter can be a value of @ref RTC_WeekDay_Definitions */
+
+ uint8_t RTC_Month; /*!< Specifies the RTC Date Month (in BCD format).
+ This parameter can be a value of @ref RTC_Month_Date_Definitions */
+
+ uint8_t RTC_Date; /*!< Specifies the RTC Date.
+ This parameter must be set to a value in the 1-31 range. */
+
+ uint8_t RTC_Year; /*!< Specifies the RTC Date Year.
+ This parameter must be set to a value in the 0-99 range. */
+}RTC_DateTypeDef;
+
+/**
+ * @brief RTC Alarm structure definition
+ */
+typedef struct
+{
+ RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */
+
+ uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks.
+ This parameter can be a value of @ref RTC_AlarmMask_Definitions */
+
+ uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
+ This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
+
+ uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
+ If the Alarm Date is selected, this parameter
+ must be set to a value in the 1-31 range.
+ If the Alarm WeekDay is selected, this
+ parameter can be a value of @ref RTC_WeekDay_Definitions */
+}RTC_AlarmTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RTC_Exported_Constants
+ * @{
+ */
+
+
+/** @defgroup RTC_Hour_Formats
+ * @{
+ */
+#define RTC_HourFormat_24 ((uint32_t)0x00000000)
+#define RTC_HourFormat_12 ((uint32_t)0x00000040)
+#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \
+ ((FORMAT) == RTC_HourFormat_24))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Asynchronous_Predivider
+ * @{
+ */
+#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F)
+
+/**
+ * @}
+ */
+
+
+/** @defgroup RTC_Synchronous_Predivider
+ * @{
+ */
+#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Time_Definitions
+ * @{
+ */
+#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))
+#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23)
+#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)
+#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_AM_PM_Definitions
+ * @{
+ */
+#define RTC_H12_AM ((uint8_t)0x00)
+#define RTC_H12_PM ((uint8_t)0x40)
+#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Year_Date_Definitions
+ * @{
+ */
+#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Month_Date_Definitions
+ * @{
+ */
+
+/* Coded in BCD format */
+#define RTC_Month_January ((uint8_t)0x01)
+#define RTC_Month_February ((uint8_t)0x02)
+#define RTC_Month_March ((uint8_t)0x03)
+#define RTC_Month_April ((uint8_t)0x04)
+#define RTC_Month_May ((uint8_t)0x05)
+#define RTC_Month_June ((uint8_t)0x06)
+#define RTC_Month_July ((uint8_t)0x07)
+#define RTC_Month_August ((uint8_t)0x08)
+#define RTC_Month_September ((uint8_t)0x09)
+#define RTC_Month_October ((uint8_t)0x10)
+#define RTC_Month_November ((uint8_t)0x11)
+#define RTC_Month_December ((uint8_t)0x12)
+#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12))
+#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_WeekDay_Definitions
+ * @{
+ */
+
+#define RTC_Weekday_Monday ((uint8_t)0x01)
+#define RTC_Weekday_Tuesday ((uint8_t)0x02)
+#define RTC_Weekday_Wednesday ((uint8_t)0x03)
+#define RTC_Weekday_Thursday ((uint8_t)0x04)
+#define RTC_Weekday_Friday ((uint8_t)0x05)
+#define RTC_Weekday_Saturday ((uint8_t)0x06)
+#define RTC_Weekday_Sunday ((uint8_t)0x07)
+#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
+ ((WEEKDAY) == RTC_Weekday_Tuesday) || \
+ ((WEEKDAY) == RTC_Weekday_Wednesday) || \
+ ((WEEKDAY) == RTC_Weekday_Thursday) || \
+ ((WEEKDAY) == RTC_Weekday_Friday) || \
+ ((WEEKDAY) == RTC_Weekday_Saturday) || \
+ ((WEEKDAY) == RTC_Weekday_Sunday))
+/**
+ * @}
+ */
+
+
+/** @defgroup RTC_Alarm_Definitions
+ * @{
+ */
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
+#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
+ ((WEEKDAY) == RTC_Weekday_Tuesday) || \
+ ((WEEKDAY) == RTC_Weekday_Wednesday) || \
+ ((WEEKDAY) == RTC_Weekday_Thursday) || \
+ ((WEEKDAY) == RTC_Weekday_Friday) || \
+ ((WEEKDAY) == RTC_Weekday_Saturday) || \
+ ((WEEKDAY) == RTC_Weekday_Sunday))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup RTC_AlarmDateWeekDay_Definitions
+ * @{
+ */
+#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000)
+#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000)
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \
+ ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup RTC_AlarmMask_Definitions
+ * @{
+ */
+#define RTC_AlarmMask_None ((uint32_t)0x00000000)
+#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000)
+#define RTC_AlarmMask_Hours ((uint32_t)0x00800000)
+#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000)
+#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080)
+#define RTC_AlarmMask_All ((uint32_t)0x80808080)
+#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Alarms_Definitions
+ * @{
+ */
+#define RTC_Alarm_A ((uint32_t)0x00000100)
+#define RTC_Alarm_B ((uint32_t)0x00000200)
+#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B))
+#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions
+ * @{
+ */
+#define RTC_AlarmSubSecondMask_All ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked.
+ There is no comparison on sub seconds
+ for Alarm */
+#define RTC_AlarmSubSecondMask_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm
+ comparison. Only SS[0] is compared. */
+#define RTC_AlarmSubSecondMask_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm
+ comparison. Only SS[1:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm
+ comparison. Only SS[2:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm
+ comparison. Only SS[3:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm
+ comparison. Only SS[4:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm
+ comparison. Only SS[5:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm
+ comparison. Only SS[6:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm
+ comparison. Only SS[7:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm
+ comparison. Only SS[8:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm
+ comparison. Only SS[9:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm
+ comparison. Only SS[10:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm
+ comparison.Only SS[11:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm
+ comparison. Only SS[12:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm
+ comparison.Only SS[13:0] are compared */
+#define RTC_AlarmSubSecondMask_None ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match
+ to activate alarm. */
+#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14) || \
+ ((MASK) == RTC_AlarmSubSecondMask_None))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Alarm_Sub_Seconds_Value
+ * @{
+ */
+
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Wakeup_Timer_Definitions
+ * @{
+ */
+#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000)
+#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001)
+#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002)
+#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003)
+#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004)
+#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006)
+#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \
+ ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \
+ ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \
+ ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \
+ ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \
+ ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))
+#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Time_Stamp_Edges_definitions
+ * @{
+ */
+#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000)
+#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008)
+#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \
+ ((EDGE) == RTC_TimeStampEdge_Falling))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Output_selection_Definitions
+ * @{
+ */
+#define RTC_Output_Disable ((uint32_t)0x00000000)
+#define RTC_Output_AlarmA ((uint32_t)0x00200000)
+#define RTC_Output_AlarmB ((uint32_t)0x00400000)
+#define RTC_Output_WakeUp ((uint32_t)0x00600000)
+
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \
+ ((OUTPUT) == RTC_Output_AlarmA) || \
+ ((OUTPUT) == RTC_Output_AlarmB) || \
+ ((OUTPUT) == RTC_Output_WakeUp))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Output_Polarity_Definitions
+ * @{
+ */
+#define RTC_OutputPolarity_High ((uint32_t)0x00000000)
+#define RTC_OutputPolarity_Low ((uint32_t)0x00100000)
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \
+ ((POL) == RTC_OutputPolarity_Low))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Digital_Calibration_Definitions
+ * @{
+ */
+#define RTC_CalibSign_Positive ((uint32_t)0x00000000)
+#define RTC_CalibSign_Negative ((uint32_t)0x00000080)
+#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \
+ ((SIGN) == RTC_CalibSign_Negative))
+#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
+
+/**
+ * @}
+ */
+
+ /** @defgroup RTC_Calib_Output_selection_Definitions
+ * @{
+ */
+#define RTC_CalibOutput_512Hz ((uint32_t)0x00000000)
+#define RTC_CalibOutput_1Hz ((uint32_t)0x00080000)
+#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \
+ ((OUTPUT) == RTC_CalibOutput_1Hz))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Smooth_calib_period_Definitions
+ * @{
+ */
+#define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
+ period is 32s, else 2exp20 RTCCLK seconds */
+#define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
+ period is 16s, else 2exp19 RTCCLK seconds */
+#define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
+ period is 8s, else 2exp18 RTCCLK seconds */
+#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \
+ ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \
+ ((PERIOD) == RTC_SmoothCalibPeriod_8sec))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions
+ * @{
+ */
+#define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added
+ during a X -second window = Y - CALM[8:0].
+ with Y = 512, 256, 128 when X = 32, 16, 8 */
+#define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited
+ during a 32-second window = CALM[8:0]. */
+#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \
+ ((PLUS) == RTC_SmoothCalibPlusPulses_Reset))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions
+ * @{
+ */
+#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_DayLightSaving_Definitions
+ * @{
+ */
+#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000)
+#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000)
+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \
+ ((SAVE) == RTC_DayLightSaving_ADD1H))
+
+#define RTC_StoreOperation_Reset ((uint32_t)0x00000000)
+#define RTC_StoreOperation_Set ((uint32_t)0x00040000)
+#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \
+ ((OPERATION) == RTC_StoreOperation_Set))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Tamper_Trigger_Definitions
+ * @{
+ */
+#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000)
+#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001)
+#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000)
+#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001)
+#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
+ ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \
+ ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \
+ ((TRIGGER) == RTC_TamperTrigger_HighLevel))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Tamper_Filter_Definitions
+ * @{
+ */
+#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
+
+#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2
+ consecutive samples at the active level */
+#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4
+ consecutive samples at the active level */
+#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8
+ consecutive samples at the active leve. */
+#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \
+ ((FILTER) == RTC_TamperFilter_2Sample) || \
+ ((FILTER) == RTC_TamperFilter_4Sample) || \
+ ((FILTER) == RTC_TamperFilter_8Sample))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions
+ * @{
+ */
+#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 32768 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 16384 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 8192 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 4096 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 2048 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 1024 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 512 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 256 */
+#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))
+
+/**
+ * @}
+ */
+
+ /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions
+ * @{
+ */
+#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before
+ sampling during 1 RTCCLK cycle */
+#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before
+ sampling during 2 RTCCLK cycles */
+#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before
+ sampling during 4 RTCCLK cycles */
+#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before
+ sampling during 8 RTCCLK cycles */
+
+#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \
+ ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \
+ ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \
+ ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Tamper_Pins_Definitions
+ * @{
+ */
+#define RTC_Tamper_1 RTC_TAFCR_TAMP1E /*!< Tamper detection enable for
+ input tamper 1 */
+#define RTC_Tamper_2 RTC_TAFCR_TAMP2E /*!< Tamper detection enable for
+ input tamper 2 */
+#define RTC_Tamper_3 RTC_TAFCR_TAMP3E /*!< Tamper detection enable for
+ input tamper 3 */
+
+#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
+
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Output_Type_ALARM_OUT
+ * @{
+ */
+#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000)
+#define RTC_OutputType_PushPull ((uint32_t)0x00040000)
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \
+ ((TYPE) == RTC_OutputType_PushPull))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Add_1_Second_Parameter_Definitions
+ * @{
+ */
+#define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000)
+#define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000)
+#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \
+ ((SEL) == RTC_ShiftAdd1S_Set))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Substract_Fraction_Of_Second_Value
+ * @{
+ */
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Backup_Registers_Definitions
+ * @{
+ */
+
+#define RTC_BKP_DR0 ((uint32_t)0x00000000)
+#define RTC_BKP_DR1 ((uint32_t)0x00000001)
+#define RTC_BKP_DR2 ((uint32_t)0x00000002)
+#define RTC_BKP_DR3 ((uint32_t)0x00000003)
+#define RTC_BKP_DR4 ((uint32_t)0x00000004)
+#define RTC_BKP_DR5 ((uint32_t)0x00000005)
+#define RTC_BKP_DR6 ((uint32_t)0x00000006)
+#define RTC_BKP_DR7 ((uint32_t)0x00000007)
+#define RTC_BKP_DR8 ((uint32_t)0x00000008)
+#define RTC_BKP_DR9 ((uint32_t)0x00000009)
+#define RTC_BKP_DR10 ((uint32_t)0x0000000A)
+#define RTC_BKP_DR11 ((uint32_t)0x0000000B)
+#define RTC_BKP_DR12 ((uint32_t)0x0000000C)
+#define RTC_BKP_DR13 ((uint32_t)0x0000000D)
+#define RTC_BKP_DR14 ((uint32_t)0x0000000E)
+#define RTC_BKP_DR15 ((uint32_t)0x0000000F)
+#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \
+ ((BKP) == RTC_BKP_DR1) || \
+ ((BKP) == RTC_BKP_DR2) || \
+ ((BKP) == RTC_BKP_DR3) || \
+ ((BKP) == RTC_BKP_DR4) || \
+ ((BKP) == RTC_BKP_DR5) || \
+ ((BKP) == RTC_BKP_DR6) || \
+ ((BKP) == RTC_BKP_DR7) || \
+ ((BKP) == RTC_BKP_DR8) || \
+ ((BKP) == RTC_BKP_DR9) || \
+ ((BKP) == RTC_BKP_DR10) || \
+ ((BKP) == RTC_BKP_DR11) || \
+ ((BKP) == RTC_BKP_DR12) || \
+ ((BKP) == RTC_BKP_DR13) || \
+ ((BKP) == RTC_BKP_DR14) || \
+ ((BKP) == RTC_BKP_DR15))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Input_parameter_format_definitions
+ * @{
+ */
+#define RTC_Format_BIN ((uint32_t)0x000000000)
+#define RTC_Format_BCD ((uint32_t)0x000000001)
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Flags_Definitions
+ * @{
+ */
+#define RTC_FLAG_RECALPF ((uint32_t)0x00010000)
+#define RTC_FLAG_TAMP3F ((uint32_t)0x00008000)
+#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000)
+#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)
+#define RTC_FLAG_TSOVF ((uint32_t)0x00001000)
+#define RTC_FLAG_TSF ((uint32_t)0x00000800)
+#define RTC_FLAG_WUTF ((uint32_t)0x00000400)
+#define RTC_FLAG_ALRBF ((uint32_t)0x00000200)
+#define RTC_FLAG_ALRAF ((uint32_t)0x00000100)
+#define RTC_FLAG_INITF ((uint32_t)0x00000040)
+#define RTC_FLAG_RSF ((uint32_t)0x00000020)
+#define RTC_FLAG_INITS ((uint32_t)0x00000010)
+#define RTC_FLAG_SHPF ((uint32_t)0x00000008)
+#define RTC_FLAG_WUTWF ((uint32_t)0x00000004)
+#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002)
+#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001)
+#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \
+ ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \
+ ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \
+ ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \
+ ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \
+ ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_TAMP2F) || \
+ ((FLAG) == RTC_FLAG_TAMP3F) || ((FLAG) == RTC_FLAG_RECALPF) || \
+ ((FLAG) == RTC_FLAG_SHPF))
+#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Interrupts_Definitions
+ * @{
+ */
+#define RTC_IT_TS ((uint32_t)0x00008000)
+#define RTC_IT_WUT ((uint32_t)0x00004000)
+#define RTC_IT_ALRB ((uint32_t)0x00002000)
+#define RTC_IT_ALRA ((uint32_t)0x00001000)
+#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
+#define RTC_IT_TAMP1 ((uint32_t)0x00020000)
+#define RTC_IT_TAMP2 ((uint32_t)0x00040000)
+#define RTC_IT_TAMP3 ((uint32_t)0x00080000)
+
+
+#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))
+#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \
+ ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \
+ ((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_TAMP2) || \
+ ((IT) == RTC_IT_TAMP3))
+#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF10FFF) == (uint32_t)RESET))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the RTC configuration to the default reset state *****/
+ErrorStatus RTC_DeInit(void);
+
+
+/* Initialization and Configuration functions *********************************/
+ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);
+void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);
+void RTC_WriteProtectionCmd(FunctionalState NewState);
+ErrorStatus RTC_EnterInitMode(void);
+void RTC_ExitInitMode(void);
+ErrorStatus RTC_WaitForSynchro(void);
+ErrorStatus RTC_RefClockCmd(FunctionalState NewState);
+void RTC_BypassShadowCmd(FunctionalState NewState);
+
+/* Time and Date configuration functions **************************************/
+ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
+void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
+uint32_t RTC_GetSubSecond(void);
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
+void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
+
+/* Alarms (Alarm A and Alarm B) configuration functions **********************/
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
+void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
+ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);
+void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask);
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);
+
+/* WakeUp Timer configuration functions ***************************************/
+void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock);
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter);
+uint32_t RTC_GetWakeUpCounter(void);
+ErrorStatus RTC_WakeUpCmd(FunctionalState NewState);
+
+/* Daylight Saving configuration functions ************************************/
+void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
+uint32_t RTC_GetStoreOperation(void);
+
+/* Output pin Configuration function ******************************************/
+void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
+
+/* Digital Calibration configuration functions ********************************/
+void RTC_CalibOutputCmd(FunctionalState NewState);
+void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput);
+ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
+ uint32_t RTC_SmoothCalibPlusPulses,
+ uint32_t RTC_SmouthCalibMinusPulsesValue);
+
+/* TimeStamp configuration functions ******************************************/
+void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct,
+ RTC_DateTypeDef* RTC_StampDateStruct);
+uint32_t RTC_GetTimeStampSubSecond(void);
+
+/* Tampers configuration functions ********************************************/
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);
+void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);
+void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);
+void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);
+void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);
+void RTC_TamperPullUpCmd(FunctionalState NewState);
+
+/* Backup Data Registers configuration functions ******************************/
+void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);
+uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);
+
+/* Output Type Config configuration functions *********************************/
+void RTC_OutputTypeConfig(uint32_t RTC_OutputType);
+
+/* RTC_Shift_control_synchonisation_functions *********************************/
+ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);
+
+/* Interrupts and flags management functions **********************************/
+void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
+void RTC_ClearFlag(uint32_t RTC_FLAG);
+ITStatus RTC_GetITStatus(uint32_t RTC_IT);
+void RTC_ClearITPendingBit(uint32_t RTC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F30x_RTC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_spi.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,1420 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_spi.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Serial peripheral interface (SPI):
+ * + Initialization and Configuration
+ * + Data transfers functions
+ * + Hardware CRC Calculation
+ * + DMA transfers management
+ * + Interrupts and flags management
+ *
+ * @verbatim
+
+
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ (#) Enable peripheral clock using RCC_APBPeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE)
+ function for SPI1 or using RCC_APBPeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE)
+ function for SPI2.
+ (#) Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHBPeriphClockCmd()
+ function.
+ (#) Peripherals alternate function:
+ (++) Connect the pin to the desired peripherals' Alternate
+ Function (AF) using GPIO_PinAFConfig() function.
+ (++) Configure the desired pin in alternate function by:
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
+ (++) Select the type, pull-up/pull-down and output speed via
+ GPIO_PuPd, GPIO_OType and GPIO_Speed members.
+ (++) Call GPIO_Init() function.
+ (#) Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave
+ Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
+ function in SPI mode. In I2S mode, program the Mode, Standard, Data Format,
+ MCLK Output, Audio frequency and Polarity using I2S_Init() function.
+ (#) Configure the FIFO threshold using SPI_RxFIFOThresholdConfig() to select
+ at which threshold the RXNE event is generated.
+ (#) Enable the NVIC and the corresponding interrupt using the function
+ SPI_I2S_ITConfig() if you need to use interrupt mode.
+ (#) When using the DMA mode
+ (++) Configure the DMA using DMA_Init() function.
+ (++) Active the needed channel Request using SPI_I2S_DMACmd() function.
+ (#) Enable the SPI using the SPI_Cmd() function or enable the I2S using
+ I2S_Cmd().
+ (#) Enable the DMA using the DMA_Cmd() function when using DMA mode.
+ (#) Optionally you can enable/configure the following parameters without
+ re-initialization (i.e there is no need to call again SPI_Init() function):
+ (++) When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)
+ is programmed as Data direction parameter using the SPI_Init() function
+ it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx
+ using the SPI_BiDirectionalLineConfig() function.
+ (++) When SPI_NSS_Soft is selected as Slave Select Management parameter
+ using the SPI_Init() function it can be possible to manage the
+ NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.
+ (++) Reconfigure the data size using the SPI_DataSizeConfig() function.
+ (++) Enable or disable the SS output using the SPI_SSOutputCmd() function.
+ (#) To use the CRC Hardware calculation feature refer to the Peripheral
+ CRC hardware Calculation subsection.
+ [..] It is possible to use SPI in I2S full duplex mode, in this case, each SPI
+ peripheral is able to manage sending and receiving data simultaneously
+ using two data lines. Each SPI peripheral has an extended block called I2Sxext
+ (ie. I2S2ext for SPI2 and I2S3ext for SPI3).
+ The extension block is not a full SPI IP, it is used only as I2S slave to
+ implement full duplex mode. The extension block uses the same clock sources
+ as its master.
+ To configure I2S full duplex you have to:
+ (#) Configure SPIx in I2S mode (I2S_Init() function) as described above.
+ (#) Call the I2S_FullDuplexConfig() function using the same strucutre passed to
+ I2S_Init() function.
+ (#) Call I2S_Cmd() for SPIx then for its extended block.
+ (#) Configure interrupts or DMA requests and to get/clear flag status,
+ use I2Sxext instance for the extension block.
+ [..] Functions that can be called with I2Sxext instances are:
+ I2S_Cmd(), I2S_FullDuplexConfig(), SPI_I2S_ReceiveData16(), SPI_I2S_SendData16(),
+ SPI_I2S_DMACmd(), SPI_I2S_ITConfig(), SPI_I2S_GetFlagStatus(), SPI_I2S_ClearFlag(),
+ SPI_I2S_GetITStatus() and SPI_I2S_ClearITPendingBit().
+ [..] Example: To use SPI3 in Full duplex mode (SPI3 is Master Tx, I2S3ext is Slave Rx):
+ [..] RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);
+ I2S_StructInit(&I2SInitStruct);
+ I2SInitStruct.Mode = I2S_Mode_MasterTx;
+ I2S_Init(SPI3, &I2SInitStruct);
+ I2S_FullDuplexConfig(SPI3ext, &I2SInitStruct)
+ I2S_Cmd(SPI3, ENABLE);
+ I2S_Cmd(SPI3ext, ENABLE);
+ ...
+ while (SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
+ {}
+ SPI_I2S_SendData16(SPI3, txdata[i]);
+ ...
+ while (SPI_I2S_GetFlagStatus(I2S3ext, SPI_FLAG_RXNE) == RESET)
+ {}
+ rxdata[i] = SPI_I2S_ReceiveData16(I2S3ext);
+ ...
+ [..]
+ (@) In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd()
+ just after calling the function SPI_Init().
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_spi.h"
+#include "stm32f30x_rcc.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup SPI
+ * @brief SPI driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* SPI registers Masks */
+#define CR1_CLEAR_MASK ((uint16_t)0x3040)
+#define CR2_LDMA_MASK ((uint16_t)0x9FFF)
+
+#define I2SCFGR_CLEAR_MASK ((uint16_t)0xF040)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SPI_Private_Functions
+ * @{
+ */
+
+/** @defgroup SPI_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..] This section provides a set of functions allowing to initialize the SPI Direction,
+ SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud
+ Rate Prescaler, SPI First Bit and SPI CRC Polynomial.
+ [..] The SPI_Init() function follows the SPI configuration procedures for Master mode
+ and Slave mode (details for these procedures are available in reference manual).
+ [..] When the Software NSS management (SPI_InitStruct->SPI_NSS = SPI_NSS_Soft) is selected,
+ use the following function to manage the NSS bit:
+ void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
+ [..] In Master mode, when the Hardware NSS management (SPI_InitStruct->SPI_NSS = SPI_NSS_Hard)
+ is selected, use the follwoing function to enable the NSS output feature.
+ void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+ [..] The NSS pulse mode can be managed by the SPI TI mode when enabling it using the
+ following function: void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+ And it can be managed by software in the SPI Motorola mode using this function:
+ void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+ [..] This section provides also functions to initialize the I2S Mode, Standard,
+ Data Format, MCLK Output, Audio frequency and Polarity.
+ [..] The I2S_Init() function follows the I2S configuration procedures for Master mode
+ and Slave mode.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the SPIx peripheral registers to their default
+ * reset values.
+ * @param SPIx: To select the SPIx peripheral, where x can be: 1, 2 or 3
+ * in SPI mode.
+ * @retval None
+ */
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+ if (SPIx == SPI1)
+ {
+ /* Enable SPI1 reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
+ /* Release SPI1 from reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
+ }
+ else if (SPIx == SPI2)
+ {
+ /* Enable SPI2 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
+ /* Release SPI2 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
+ }
+ else
+ {
+ if (SPIx == SPI3)
+ {
+ /* Enable SPI3 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
+ /* Release SPI3 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
+ }
+ }
+}
+
+/**
+ * @brief Fills each SPI_InitStruct member with its default value.
+ * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized.
+ * @retval None
+ */
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
+{
+/*--------------- Reset SPI init structure parameters values -----------------*/
+ /* Initialize the SPI_Direction member */
+ SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+ /* Initialize the SPI_Mode member */
+ SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
+ /* Initialize the SPI_DataSize member */
+ SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
+ /* Initialize the SPI_CPOL member */
+ SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
+ /* Initialize the SPI_CPHA member */
+ SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
+ /* Initialize the SPI_NSS member */
+ SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
+ /* Initialize the SPI_BaudRatePrescaler member */
+ SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+ /* Initialize the SPI_FirstBit member */
+ SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
+ /* Initialize the SPI_CRCPolynomial member */
+ SPI_InitStruct->SPI_CRCPolynomial = 7;
+}
+
+/**
+ * @brief Initializes the SPIx peripheral according to the specified
+ * parameters in the SPI_InitStruct.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
+ * contains the configuration information for the specified SPI peripheral.
+ * @retval None
+ */
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
+{
+ uint16_t tmpreg = 0;
+
+ /* check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+ /* Check the SPI parameters */
+ assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
+ assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
+ assert_param(IS_SPI_DATA_SIZE(SPI_InitStruct->SPI_DataSize));
+ assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
+ assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
+ assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
+ assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
+ assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
+ assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
+
+ /* Configuring the SPI in master mode */
+ if(SPI_InitStruct->SPI_Mode == SPI_Mode_Master)
+ {
+/*---------------------------- SPIx CR1 Configuration ------------------------*/
+ /* Get the SPIx CR1 value */
+ tmpreg = SPIx->CR1;
+ /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
+ tmpreg &= CR1_CLEAR_MASK;
+ /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
+ master/slave mode, CPOL and CPHA */
+ /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
+ /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
+ /* Set LSBFirst bit according to SPI_FirstBit value */
+ /* Set BR bits according to SPI_BaudRatePrescaler value */
+ /* Set CPOL bit according to SPI_CPOL value */
+ /* Set CPHA bit according to SPI_CPHA value */
+ tmpreg |= (uint16_t)((uint16_t)(SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode) |
+ (uint16_t)((uint16_t)(SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA) |
+ (uint16_t)((uint16_t)(SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler) |
+ SPI_InitStruct->SPI_FirstBit)));
+ /* Write to SPIx CR1 */
+ SPIx->CR1 = tmpreg;
+ /*-------------------------Data Size Configuration -----------------------*/
+ /* Get the SPIx CR2 value */
+ tmpreg = SPIx->CR2;
+ /* Clear DS[3:0] bits */
+ tmpreg &= (uint16_t)~SPI_CR2_DS;
+ /* Configure SPIx: Data Size */
+ tmpreg |= (uint16_t)(SPI_InitStruct->SPI_DataSize);
+ /* Write to SPIx CR2 */
+ SPIx->CR2 = tmpreg;
+ }
+ /* Configuring the SPI in slave mode */
+ else
+ {
+/*---------------------------- Data size Configuration -----------------------*/
+ /* Get the SPIx CR2 value */
+ tmpreg = SPIx->CR2;
+ /* Clear DS[3:0] bits */
+ tmpreg &= (uint16_t)~SPI_CR2_DS;
+ /* Configure SPIx: Data Size */
+ tmpreg |= (uint16_t)(SPI_InitStruct->SPI_DataSize);
+ /* Write to SPIx CR2 */
+ SPIx->CR2 = tmpreg;
+/*---------------------------- SPIx CR1 Configuration ------------------------*/
+ /* Get the SPIx CR1 value */
+ tmpreg = SPIx->CR1;
+ /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
+ tmpreg &= CR1_CLEAR_MASK;
+ /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
+ master/salve mode, CPOL and CPHA */
+ /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
+ /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
+ /* Set LSBFirst bit according to SPI_FirstBit value */
+ /* Set BR bits according to SPI_BaudRatePrescaler value */
+ /* Set CPOL bit according to SPI_CPOL value */
+ /* Set CPHA bit according to SPI_CPHA value */
+ tmpreg |= (uint16_t)((uint16_t)(SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode) |
+ (uint16_t)((uint16_t)(SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA) |
+ (uint16_t)((uint16_t)(SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler) |
+ SPI_InitStruct->SPI_FirstBit)));
+
+ /* Write to SPIx CR1 */
+ SPIx->CR1 = tmpreg;
+ }
+
+ /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
+ SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD);
+
+/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
+ /* Write to SPIx CRCPOLY */
+ SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
+}
+
+/**
+ * @brief Fills each I2S_InitStruct member with its default value.
+ * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized.
+ * @retval None
+ */
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
+{
+/*--------------- Reset I2S init structure parameters values -----------------*/
+ /* Initialize the I2S_Mode member */
+ I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
+
+ /* Initialize the I2S_Standard member */
+ I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
+
+ /* Initialize the I2S_DataFormat member */
+ I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
+
+ /* Initialize the I2S_MCLKOutput member */
+ I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
+
+ /* Initialize the I2S_AudioFreq member */
+ I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
+
+ /* Initialize the I2S_CPOL member */
+ I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
+}
+
+/**
+ * @brief Initializes the SPIx peripheral according to the specified
+ * parameters in the I2S_InitStruct.
+ * @param SPIx:To select the SPIx peripheral, where x can be: 2 or 3
+ * in I2S mode.
+ * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
+ * contains the configuration information for the specified SPI peripheral
+ * configured in I2S mode.
+ * @note
+ * The function calculates the optimal prescaler needed to obtain the most
+ * accurate audio frequency (depending on the I2S clock source, the PLL values
+ * and the product configuration). But in case the prescaler value is greater
+ * than 511, the default value (0x02) will be configured instead.
+ * @retval None
+ */
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
+{
+ uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
+ uint32_t tmp = 0;
+ RCC_ClocksTypeDef RCC_Clocks;
+ uint32_t sourceclock = 0;
+
+ /* Check the I2S parameters */
+ assert_param(IS_SPI_23_PERIPH(SPIx));
+ assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
+ assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
+ assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
+ assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
+ assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
+ assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
+
+/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+ SPIx->I2SCFGR &= I2SCFGR_CLEAR_MASK;
+ SPIx->I2SPR = 0x0002;
+
+ /* Get the I2SCFGR register value */
+ tmpreg = SPIx->I2SCFGR;
+
+ /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
+ if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
+ {
+ i2sodd = (uint16_t)0;
+ i2sdiv = (uint16_t)2;
+ }
+ /* If the requested audio frequency is not the default, compute the prescaler */
+ else
+ {
+ /* Check the frame length (For the Prescaler computing) */
+ if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
+ {
+ /* Packet length is 16 bits */
+ packetlength = 1;
+ }
+ else
+ {
+ /* Packet length is 32 bits */
+ packetlength = 2;
+ }
+
+ /* I2S Clock source is System clock: Get System Clock frequency */
+ RCC_GetClocksFreq(&RCC_Clocks);
+
+ /* Get the source clock value: based on System Clock value */
+ sourceclock = RCC_Clocks.SYSCLK_Frequency;
+
+ /* Compute the Real divider depending on the MCLK output state with a floating point */
+ if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
+ {
+ /* MCLK output is enabled */
+ tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
+ }
+ else
+ {
+ /* MCLK output is disabled */
+ tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
+ }
+
+ /* Remove the floating point */
+ tmp = tmp / 10;
+
+ /* Check the parity of the divider */
+ i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
+
+ /* Compute the i2sdiv prescaler */
+ i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
+
+ /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+ i2sodd = (uint16_t) (i2sodd << 8);
+ }
+
+ /* Test if the divider is 1 or 0 or greater than 0xFF */
+ if ((i2sdiv < 2) || (i2sdiv > 0xFF))
+ {
+ /* Set the default values */
+ i2sdiv = 2;
+ i2sodd = 0;
+ }
+
+ /* Write to SPIx I2SPR register the computed value */
+ SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
+
+ /* Configure the I2S with the SPI_InitStruct values */
+ tmpreg |= (uint16_t)((uint16_t)(SPI_I2SCFGR_I2SMOD | I2S_InitStruct->I2S_Mode) | \
+ (uint16_t)((uint16_t)((uint16_t)(I2S_InitStruct->I2S_Standard |I2S_InitStruct->I2S_DataFormat) |\
+ I2S_InitStruct->I2S_CPOL)));
+
+ /* Write to SPIx I2SCFGR */
+ SPIx->I2SCFGR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the specified SPI peripheral.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param NewState: new state of the SPIx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI peripheral */
+ SPIx->CR1 |= SPI_CR1_SPE;
+ }
+ else
+ {
+ /* Disable the selected SPI peripheral */
+ SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);
+ }
+}
+
+/**
+ * @brief Enables or disables the TI Mode.
+ * @note This function can be called only after the SPI_Init() function has
+ * been called.
+ * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA
+ * are not taken into consideration and are configured by hardware
+ * respectively to the TI mode requirements.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param NewState: new state of the selected SPI TI communication mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the TI mode for the selected SPI peripheral */
+ SPIx->CR2 |= SPI_CR2_FRF;
+ }
+ else
+ {
+ /* Disable the TI mode for the selected SPI peripheral */
+ SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRF);
+ }
+}
+
+/**
+ * @brief Enables or disables the specified SPI peripheral (in I2S mode).
+ * @param SPIx:To select the SPIx peripheral, where x can be: 2 or 3 in
+ * I2S mode or I2Sxext for I2S full duplex mode.
+ * @param NewState: new state of the SPIx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_23_PERIPH_EXT(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI peripheral in I2S mode */
+ SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE;
+ }
+ else
+ {
+ /* Disable the selected SPI peripheral in I2S mode */
+ SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE);
+ }
+}
+
+/**
+ * @brief Configures the data size for the selected SPI.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param SPI_DataSize: specifies the SPI data size.
+ * For the SPIx peripheral this parameter can be one of the following values:
+ * @arg SPI_DataSize_4b: Set data size to 4 bits
+ * @arg SPI_DataSize_5b: Set data size to 5 bits
+ * @arg SPI_DataSize_6b: Set data size to 6 bits
+ * @arg SPI_DataSize_7b: Set data size to 7 bits
+ * @arg SPI_DataSize_8b: Set data size to 8 bits
+ * @arg SPI_DataSize_9b: Set data size to 9 bits
+ * @arg SPI_DataSize_10b: Set data size to 10 bits
+ * @arg SPI_DataSize_11b: Set data size to 11 bits
+ * @arg SPI_DataSize_12b: Set data size to 12 bits
+ * @arg SPI_DataSize_13b: Set data size to 13 bits
+ * @arg SPI_DataSize_14b: Set data size to 14 bits
+ * @arg SPI_DataSize_15b: Set data size to 15 bits
+ * @arg SPI_DataSize_16b: Set data size to 16 bits
+ * @retval None
+ */
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
+{
+ uint16_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_DATA_SIZE(SPI_DataSize));
+ /* Read the CR2 register */
+ tmpreg = SPIx->CR2;
+ /* Clear DS[3:0] bits */
+ tmpreg &= (uint16_t)~SPI_CR2_DS;
+ /* Set new DS[3:0] bits value */
+ tmpreg |= SPI_DataSize;
+ SPIx->CR2 = tmpreg;
+}
+
+/**
+ * @brief Configures the FIFO reception threshold for the selected SPI.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param SPI_RxFIFOThreshold: specifies the FIFO reception threshold.
+ * This parameter can be one of the following values:
+ * @arg SPI_RxFIFOThreshold_HF: RXNE event is generated if the FIFO
+ * level is greater or equal to 1/2.
+ * @arg SPI_RxFIFOThreshold_QF: RXNE event is generated if the FIFO
+ * level is greater or equal to 1/4.
+ * @retval None
+ */
+void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_RX_FIFO_THRESHOLD(SPI_RxFIFOThreshold));
+
+ /* Clear FRXTH bit */
+ SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRXTH);
+
+ /* Set new FRXTH bit value */
+ SPIx->CR2 |= SPI_RxFIFOThreshold;
+}
+
+/**
+ * @brief Selects the data transfer direction in bidirectional mode for the specified SPI.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param SPI_Direction: specifies the data transfer direction in bidirectional mode.
+ * This parameter can be one of the following values:
+ * @arg SPI_Direction_Tx: Selects Tx transmission direction
+ * @arg SPI_Direction_Rx: Selects Rx receive direction
+ * @retval None
+ */
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_DIRECTION(SPI_Direction));
+ if (SPI_Direction == SPI_Direction_Tx)
+ {
+ /* Set the Tx only mode */
+ SPIx->CR1 |= SPI_Direction_Tx;
+ }
+ else
+ {
+ /* Set the Rx only mode */
+ SPIx->CR1 &= SPI_Direction_Rx;
+ }
+}
+
+/**
+ * @brief Configures internally by software the NSS pin for the selected SPI.
+ * @note This function can be called only after the SPI_Init() function has
+ * been called.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.
+ * This parameter can be one of the following values:
+ * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
+ * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
+ * @retval None
+ */
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
+
+ if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
+ {
+ /* Set NSS pin internally by software */
+ SPIx->CR1 |= SPI_NSSInternalSoft_Set;
+ }
+ else
+ {
+ /* Reset NSS pin internally by software */
+ SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
+ }
+}
+
+/**
+ * @brief Configures the full duplex mode for the I2Sx peripheral using its
+ * extension I2Sxext according to the specified parameters in the
+ * I2S_InitStruct.
+ * @param I2Sxext: where x can be 2 or 3 to select the I2S peripheral extension block.
+ * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
+ * contains the configuration information for the specified I2S peripheral
+ * extension.
+ *
+ * @note The structure pointed by I2S_InitStruct parameter should be the same
+ * used for the master I2S peripheral. In this case, if the master is
+ * configured as transmitter, the slave will be receiver and vice versa.
+ * Or you can force a different mode by modifying the field I2S_Mode to the
+ * value I2S_SlaveRx or I2S_SlaveTx indepedently of the master configuration.
+ *
+ * @note The I2S full duplex extension can be configured in slave mode only.
+ *
+ * @retval None
+ */
+void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct)
+{
+ uint16_t tmpreg = 0, tmp = 0;
+
+ /* Check the I2S parameters */
+ assert_param(IS_I2S_EXT_PERIPH(I2Sxext));
+ assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
+ assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
+ assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
+ assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
+
+/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+ I2Sxext->I2SCFGR &= I2SCFGR_CLEAR_MASK;
+ I2Sxext->I2SPR = 0x0002;
+
+ /* Get the I2SCFGR register value */
+ tmpreg = I2Sxext->I2SCFGR;
+
+ /* Get the mode to be configured for the extended I2S */
+ if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveTx))
+ {
+ tmp = I2S_Mode_SlaveRx;
+ }
+ else
+ {
+ if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterRx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveRx))
+ {
+ tmp = I2S_Mode_SlaveTx;
+ }
+ }
+
+
+ /* Configure the I2S with the SPI_InitStruct values */
+ tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \
+ (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
+ (uint16_t)I2S_InitStruct->I2S_CPOL))));
+
+ /* Write to SPIx I2SCFGR */
+ I2Sxext->I2SCFGR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the SS output for the selected SPI.
+ * @note This function can be called only after the SPI_Init() function has
+ * been called and the NSS hardware management mode is selected.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param NewState: new state of the SPIx SS output.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI SS output */
+ SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE;
+ }
+ else
+ {
+ /* Disable the selected SPI SS output */
+ SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);
+ }
+}
+
+/**
+ * @brief Enables or disables the NSS pulse management mode.
+ * @note This function can be called only after the SPI_Init() function has
+ * been called.
+ * @note When TI mode is selected, the control bits NSSP is not taken into
+ * consideration and are configured by hardware respectively to the
+ * TI mode requirements.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param NewState: new state of the NSS pulse management mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the NSS pulse management mode */
+ SPIx->CR2 |= SPI_CR2_NSSP;
+ }
+ else
+ {
+ /* Disable the NSS pulse management mode */
+ SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_NSSP);
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Group2 Data transfers functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Data transfers functions #####
+ ===============================================================================
+ [..] This section provides a set of functions allowing to manage the SPI or I2S
+ data transfers.
+ [..] In reception, data are received and then stored into an internal Rx buffer while
+ In transmission, data are first stored into an internal Tx buffer before being
+ transmitted.
+ [..] The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData()
+ function and returns the Rx buffered value. Whereas a write access to the SPI_DR
+ can be done using SPI_I2S_SendData() function and stores the written data into
+ Tx buffer.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmits a Data through the SPIx peripheral.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param Data: Data to be transmitted.
+ * @retval None
+ */
+void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data)
+{
+ uint32_t spixbase = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+ spixbase = (uint32_t)SPIx;
+ spixbase += 0x0C;
+
+ *(__IO uint8_t *) spixbase = Data;
+}
+
+/**
+ * @brief Transmits a Data through the SPIx/I2Sx peripheral.
+ * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
+ * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
+ * @param Data: Data to be transmitted.
+ * @retval None
+ */
+void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
+
+ SPIx->DR = (uint16_t)Data;
+}
+
+/**
+ * @brief Returns the most recent received data by the SPIx peripheral.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @retval The value of the received data.
+ */
+uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx)
+{
+ uint32_t spixbase = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
+
+ spixbase = (uint32_t)SPIx;
+ spixbase += 0x0C;
+
+ return *(__IO uint8_t *) spixbase;
+}
+
+/**
+ * @brief Returns the most recent received data by the SPIx peripheral.
+ * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
+ * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
+ * @retval The value of the received data.
+ */
+uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
+
+ return SPIx->DR;
+}
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Group3 Hardware CRC Calculation functions
+ * @brief Hardware CRC Calculation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Hardware CRC Calculation functions #####
+ ===============================================================================
+ [..] This section provides a set of functions allowing to manage the SPI CRC hardware
+ calculation.
+ [..] SPI communication using CRC is possible through the following procedure:
+ (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler,
+ Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
+ function.
+ (#) Enable the CRC calculation using the SPI_CalculateCRC() function.
+ (#) Enable the SPI using the SPI_Cmd() function
+ (#) Before writing the last data to the TX buffer, set the CRCNext bit using the
+ SPI_TransmitCRC() function to indicate that after transmission of the last
+ data, the CRC should be transmitted.
+ (#) After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT
+ bit is reset. The CRC is also received and compared against the SPI_RXCRCR
+ value.
+ If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt
+ can be generated when the SPI_I2S_IT_ERR interrupt is enabled.
+ [..]
+ (@)
+ (+@) It is advised to don't read the calculate CRC values during the communication.
+ (+@) When the SPI is in slave mode, be careful to enable CRC calculation only
+ when the clock is stable, that is, when the clock is in the steady state.
+ If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive
+ to the SCK slave input clock as soon as CRCEN is set, and this, whatever
+ the value of the SPE bit.
+ (+@) With high bitrate frequencies, be careful when transmitting the CRC.
+ As the number of used CPU cycles has to be as low as possible in the CRC
+ transfer phase, it is forbidden to call software functions in the CRC
+ transmission sequence to avoid errors in the last data and CRC reception.
+ In fact, CRCNEXT bit has to be written before the end of the transmission/reception
+ of the last data.
+ (+@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the
+ degradation of the SPI speed performance due to CPU accesses impacting the
+ SPI bandwidth.
+ (+@) When the STM32F30x are configured as slaves and the NSS hardware mode is
+ used, the NSS pin needs to be kept low between the data phase and the CRC
+ phase.
+ (+@) When the SPI is configured in slave mode with the CRC feature enabled, CRC
+ calculation takes place even if a high level is applied on the NSS pin.
+ This may happen for example in case of a multislave environment where the
+ communication master addresses slaves alternately.
+ (+@) Between a slave deselection (high level on NSS) and a new slave selection
+ (low level on NSS), the CRC value should be cleared on both master and slave
+ sides in order to resynchronize the master and slave for their respective
+ CRC calculation.
+ [..]
+ (@) To clear the CRC, follow the procedure below:
+ (#@) Disable SPI using the SPI_Cmd() function.
+ (#@) Disable the CRC calculation using the SPI_CalculateCRC() function.
+ (#@) Enable the CRC calculation using the SPI_CalculateCRC() function.
+ (#@) Enable SPI using the SPI_Cmd() function.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the CRC calculation length for the selected SPI.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param SPI_CRCLength: specifies the SPI CRC calculation length.
+ * This parameter can be one of the following values:
+ * @arg SPI_CRCLength_8b: Set CRC Calculation to 8 bits
+ * @arg SPI_CRCLength_16b: Set CRC Calculation to 16 bits
+ * @retval None
+ */
+void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_CRC_LENGTH(SPI_CRCLength));
+
+ /* Clear CRCL bit */
+ SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCL);
+
+ /* Set new CRCL bit value */
+ SPIx->CR1 |= SPI_CRCLength;
+}
+
+/**
+ * @brief Enables or disables the CRC value calculation of the transferred bytes.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param NewState: new state of the SPIx CRC value calculation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI CRC calculation */
+ SPIx->CR1 |= SPI_CR1_CRCEN;
+ }
+ else
+ {
+ /* Disable the selected SPI CRC calculation */
+ SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);
+ }
+}
+
+/**
+ * @brief Transmits the SPIx CRC value.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @retval None
+ */
+void SPI_TransmitCRC(SPI_TypeDef* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+ /* Enable the selected SPI CRC transmission */
+ SPIx->CR1 |= SPI_CR1_CRCNEXT;
+}
+
+/**
+ * @brief Returns the transmit or the receive CRC register value for the specified SPI.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param SPI_CRC: specifies the CRC register to be read.
+ * This parameter can be one of the following values:
+ * @arg SPI_CRC_Tx: Selects Tx CRC register
+ * @arg SPI_CRC_Rx: Selects Rx CRC register
+ * @retval The selected CRC register value..
+ */
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
+{
+ uint16_t crcreg = 0;
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_CRC(SPI_CRC));
+
+ if (SPI_CRC != SPI_CRC_Rx)
+ {
+ /* Get the Tx CRC register */
+ crcreg = SPIx->TXCRCR;
+ }
+ else
+ {
+ /* Get the Rx CRC register */
+ crcreg = SPIx->RXCRCR;
+ }
+ /* Return the selected CRC register */
+ return crcreg;
+}
+
+/**
+ * @brief Returns the CRC Polynomial register value for the specified SPI.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @retval The CRC Polynomial register value.
+ */
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+ /* Return the CRC polynomial register */
+ return SPIx->CRCPR;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Group4 DMA transfers management functions
+ * @brief DMA transfers management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### DMA transfers management functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the SPIx/I2Sx DMA interface.
+ * @param SPIx:To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
+ * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
+ * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
+ * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
+ * @param NewState: new state of the selected SPI DMA transfer request.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_SPI_I2S_DMA_REQ(SPI_I2S_DMAReq));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI DMA requests */
+ SPIx->CR2 |= SPI_I2S_DMAReq;
+ }
+ else
+ {
+ /* Disable the selected SPI DMA requests */
+ SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
+ }
+}
+
+/**
+ * @brief Configures the number of data to transfer type(Even/Odd) for the DMA
+ * last transfers and for the selected SPI.
+ * @note This function have a meaning only if DMA mode is selected and if
+ * the packing mode is used (data length <= 8 and DMA transfer size halfword)
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param SPI_LastDMATransfer: specifies the SPI last DMA transfers state.
+ * This parameter can be one of the following values:
+ * @arg SPI_LastDMATransfer_TxEvenRxEven: Number of data for transmission Even
+ * and number of data for reception Even.
+ * @arg SPI_LastDMATransfer_TxOddRxEven: Number of data for transmission Odd
+ * and number of data for reception Even.
+ * @arg SPI_LastDMATransfer_TxEvenRxOdd: Number of data for transmission Even
+ * and number of data for reception Odd.
+ * @arg SPI_LastDMATransfer_TxOddRxOdd: RNumber of data for transmission Odd
+ * and number of data for reception Odd.
+ * @retval None
+ */
+void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_LAST_DMA_TRANSFER(SPI_LastDMATransfer));
+
+ /* Clear LDMA_TX and LDMA_RX bits */
+ SPIx->CR2 &= CR2_LDMA_MASK;
+
+ /* Set new LDMA_TX and LDMA_RX bits value */
+ SPIx->CR2 |= SPI_LastDMATransfer;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Group5 Interrupts and flags management functions
+ * @brief Interrupts and flags management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupts and flags management functions #####
+ ===============================================================================
+ [..] This section provides a set of functions allowing to configure the SPI/I2S
+ Interrupts sources and check or clear the flags or pending bits status.
+ The user should identify which mode will be used in his application to manage
+ the communication: Polling mode, Interrupt mode or DMA mode.
+
+ *** Polling Mode ***
+ ====================
+ [..] In Polling Mode, the SPI/I2S communication can be managed by 9 flags:
+ (#) SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register.
+ (#) SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register.
+ (#) SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI.
+ (#) SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur.
+ (#) SPI_FLAG_MODF : to indicate if a Mode Fault error occur.
+ (#) SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur.
+ (#) SPI_I2S_FLAG_FRE: to indicate a Frame Format error occurs.
+ (#) I2S_FLAG_UDR: to indicate an Underrun error occurs.
+ (#) I2S_FLAG_CHSIDE: to indicate Channel Side.
+ [..]
+ (@) Do not use the BSY flag to handle each data transmission or reception.
+ It is better to use the TXE and RXNE flags instead.
+ [..] In this Mode it is advised to use the following functions:
+ (+) FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+ (+) void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+
+ *** Interrupt Mode ***
+ ======================
+ [..] In Interrupt Mode, the SPI/I2S communication can be managed by 3 interrupt sources
+ and 5 pending bits:
+ [..] Pending Bits:
+ (#) SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register.
+ (#) SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register.
+ (#) SPI_I2S_IT_OVR : to indicate if an Overrun error occur.
+ (#) I2S_IT_UDR : to indicate an Underrun Error occurs.
+ (#) SPI_I2S_FLAG_FRE : to indicate a Frame Format error occurs.
+ [..] Interrupt Source:
+ (#) SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty
+ interrupt.
+ (#) SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not
+ empty interrupt.
+ (#) SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt.
+ [..] In this Mode it is advised to use the following functions:
+ (+) void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
+ (+) ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+
+ *** FIFO Status ***
+ ===================
+ [..] It is possible to monitor the FIFO status when a transfer is ongoing using the
+ following function:
+ (+) uint32_t SPI_GetFIFOStatus(uint8_t SPI_FIFO_Direction);
+
+ *** DMA Mode ***
+ ================
+ [..] In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests:
+ (#) SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
+ (#) SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
+ [..] In this Mode it is advised to use the following function:
+ (+) void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the specified SPI/I2S interrupts.
+ * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
+ * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
+ * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
+ * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
+ * @arg SPI_I2S_IT_ERR: Error interrupt mask
+ * @param NewState: new state of the specified SPI interrupt.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
+{
+ uint16_t itpos = 0, itmask = 0 ;
+
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
+
+ /* Get the SPI IT index */
+ itpos = SPI_I2S_IT >> 4;
+
+ /* Set the IT mask */
+ itmask = (uint16_t)1 << (uint16_t)itpos;
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI interrupt */
+ SPIx->CR2 |= itmask;
+ }
+ else
+ {
+ /* Disable the selected SPI interrupt */
+ SPIx->CR2 &= (uint16_t)~itmask;
+ }
+}
+
+/**
+ * @brief Returns the current SPIx Transmission FIFO filled level.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @retval The Transmission FIFO filling state.
+ * - SPI_TransmissionFIFOStatus_Empty: when FIFO is empty
+ * - SPI_TransmissionFIFOStatus_1QuarterFull: if more than 1 quarter-full.
+ * - SPI_TransmissionFIFOStatus_HalfFull: if more than 1 half-full.
+ * - SPI_TransmissionFIFOStatus_Full: when FIFO is full.
+ */
+uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx)
+{
+ /* Get the SPIx Transmission FIFO level bits */
+ return (uint16_t)((SPIx->SR & SPI_SR_FTLVL));
+}
+
+/**
+ * @brief Returns the current SPIx Reception FIFO filled level.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @retval The Reception FIFO filling state.
+ * - SPI_ReceptionFIFOStatus_Empty: when FIFO is empty
+ * - SPI_ReceptionFIFOStatus_1QuarterFull: if more than 1 quarter-full.
+ * - SPI_ReceptionFIFOStatus_HalfFull: if more than 1 half-full.
+ * - SPI_ReceptionFIFOStatus_Full: when FIFO is full.
+ */
+uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx)
+{
+ /* Get the SPIx Reception FIFO level bits */
+ return (uint16_t)((SPIx->SR & SPI_SR_FRLVL));
+}
+
+/**
+ * @brief Checks whether the specified SPI flag is set or not.
+ * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
+ * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
+ * @param SPI_I2S_FLAG: specifies the SPI flag to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
+ * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
+ * @arg SPI_I2S_FLAG_BSY: Busy flag.
+ * @arg SPI_I2S_FLAG_OVR: Overrun flag.
+ * @arg SPI_I2S_FLAG_MODF: Mode Fault flag.
+ * @arg SPI_I2S_FLAG_CRCERR: CRC Error flag.
+ * @arg SPI_I2S_FLAG_FRE: TI frame format error flag.
+ * @arg I2S_FLAG_UDR: Underrun Error flag.
+ * @arg I2S_FLAG_CHSIDE: Channel Side flag.
+ * @retval The new state of SPI_I2S_FLAG (SET or RESET).
+ */
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
+ assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
+
+ /* Check the status of the specified SPI flag */
+ if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
+ {
+ /* SPI_I2S_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* SPI_I2S_FLAG is reset */
+ bitstatus = RESET;
+ }
+ /* Return the SPI_I2S_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the SPIx CRC Error (CRCERR) flag.
+ * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
+ * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
+ * @param SPI_I2S_FLAG: specifies the SPI flag to clear.
+ * This function clears only CRCERR flag.
+ * @note OVR (OverRun error) flag is cleared by software sequence: a read
+ * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read
+ * operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
+ * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write
+ * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a
+ * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
+ * @retval None
+ */
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
+ assert_param(IS_SPI_CLEAR_FLAG(SPI_I2S_FLAG));
+
+ /* Clear the selected SPI CRC Error (CRCERR) flag */
+ SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified SPI/I2S interrupt has occurred or not.
+ * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
+ * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
+ * @param SPI_I2S_IT: specifies the SPI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
+ * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
+ * @arg SPI_IT_MODF: Mode Fault interrupt.
+ * @arg SPI_I2S_IT_OVR: Overrun interrupt.
+ * @arg I2S_IT_UDR: Underrun interrupt.
+ * @arg SPI_I2S_IT_FRE: Format Error interrupt.
+ * @retval The new state of SPI_I2S_IT (SET or RESET).
+ */
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint16_t itpos = 0, itmask = 0, enablestatus = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
+ assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
+
+ /* Get the SPI_I2S_IT index */
+ itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+
+ /* Get the SPI_I2S_IT IT mask */
+ itmask = SPI_I2S_IT >> 4;
+
+ /* Set the IT mask */
+ itmask = 0x01 << itmask;
+
+ /* Get the SPI_I2S_IT enable bit status */
+ enablestatus = (SPIx->CR2 & itmask) ;
+
+ /* Check the status of the specified SPI interrupt */
+ if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
+ {
+ /* SPI_I2S_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* SPI_I2S_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the SPI_I2S_IT status */
+ return bitstatus;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_spi.h Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,616 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_spi.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the SPI
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_SPI_H
+#define __STM32F30x_SPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief SPI Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
+ This parameter can be a value of @ref SPI_data_direction */
+
+ uint16_t SPI_Mode; /*!< Specifies the SPI mode (Master/Slave).
+ This parameter can be a value of @ref SPI_mode */
+
+ uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
+ This parameter can be a value of @ref SPI_data_size */
+
+ uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
+ This parameter can be a value of @ref SPI_Clock_Polarity */
+
+ uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
+ This parameter can be a value of @ref SPI_Clock_Phase */
+
+ uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
+ hardware (NSS pin) or by software using the SSI bit.
+ This parameter can be a value of @ref SPI_Slave_Select_management */
+
+ uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
+ used to configure the transmit and receive SCK clock.
+ This parameter can be a value of @ref SPI_BaudRate_Prescaler.
+ @note The communication clock is derived from the master
+ clock. The slave clock does not need to be set. */
+
+ uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+ uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
+}SPI_InitTypeDef;
+
+
+/**
+ * @brief I2S Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
+ This parameter can be a value of @ref I2S_Mode */
+
+ uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
+ This parameter can be a value of @ref I2S_Standard */
+
+ uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
+ This parameter can be a value of @ref I2S_Data_Format */
+
+ uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
+ This parameter can be a value of @ref I2S_MCLK_Output */
+
+ uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
+ This parameter can be a value of @ref I2S_Audio_Frequency */
+
+ uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
+ This parameter can be a value of @ref I2S_Clock_Polarity */
+}I2S_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SPI_Exported_Constants
+ * @{
+ */
+
+#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
+ ((PERIPH) == SPI2) || \
+ ((PERIPH) == SPI3))
+
+#define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \
+ ((PERIPH) == SPI2) || \
+ ((PERIPH) == SPI3) || \
+ ((PERIPH) == I2S2ext) || \
+ ((PERIPH) == I2S3ext))
+
+#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
+ ((PERIPH) == SPI3))
+
+#define IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || \
+ ((PERIPH) == SPI3) || \
+ ((PERIPH) == I2S2ext) || \
+ ((PERIPH) == I2S3ext))
+
+#define IS_I2S_EXT_PERIPH(PERIPH) (((PERIPH) == I2S2ext) || \
+ ((PERIPH) == I2S3ext))
+
+/** @defgroup SPI_data_direction
+ * @{
+ */
+
+#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
+#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
+#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
+#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
+ ((MODE) == SPI_Direction_2Lines_RxOnly) || \
+ ((MODE) == SPI_Direction_1Line_Rx) || \
+ ((MODE) == SPI_Direction_1Line_Tx))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_mode
+ * @{
+ */
+
+#define SPI_Mode_Master ((uint16_t)0x0104)
+#define SPI_Mode_Slave ((uint16_t)0x0000)
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
+ ((MODE) == SPI_Mode_Slave))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_data_size
+ * @{
+ */
+
+#define SPI_DataSize_4b ((uint16_t)0x0300)
+#define SPI_DataSize_5b ((uint16_t)0x0400)
+#define SPI_DataSize_6b ((uint16_t)0x0500)
+#define SPI_DataSize_7b ((uint16_t)0x0600)
+#define SPI_DataSize_8b ((uint16_t)0x0700)
+#define SPI_DataSize_9b ((uint16_t)0x0800)
+#define SPI_DataSize_10b ((uint16_t)0x0900)
+#define SPI_DataSize_11b ((uint16_t)0x0A00)
+#define SPI_DataSize_12b ((uint16_t)0x0B00)
+#define SPI_DataSize_13b ((uint16_t)0x0C00)
+#define SPI_DataSize_14b ((uint16_t)0x0D00)
+#define SPI_DataSize_15b ((uint16_t)0x0E00)
+#define SPI_DataSize_16b ((uint16_t)0x0F00)
+#define IS_SPI_DATA_SIZE(SIZE) (((SIZE) == SPI_DataSize_4b) || \
+ ((SIZE) == SPI_DataSize_5b) || \
+ ((SIZE) == SPI_DataSize_6b) || \
+ ((SIZE) == SPI_DataSize_7b) || \
+ ((SIZE) == SPI_DataSize_8b) || \
+ ((SIZE) == SPI_DataSize_9b) || \
+ ((SIZE) == SPI_DataSize_10b) || \
+ ((SIZE) == SPI_DataSize_11b) || \
+ ((SIZE) == SPI_DataSize_12b) || \
+ ((SIZE) == SPI_DataSize_13b) || \
+ ((SIZE) == SPI_DataSize_14b) || \
+ ((SIZE) == SPI_DataSize_15b) || \
+ ((SIZE) == SPI_DataSize_16b))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_length
+ * @{
+ */
+
+#define SPI_CRCLength_8b ((uint16_t)0x0000)
+#define SPI_CRCLength_16b ((uint16_t)0x0800)
+#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRCLength_8b) || \
+ ((LENGTH) == SPI_CRCLength_16b))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Clock_Polarity
+ * @{
+ */
+
+#define SPI_CPOL_Low ((uint16_t)0x0000)
+#define SPI_CPOL_High ((uint16_t)0x0002)
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
+ ((CPOL) == SPI_CPOL_High))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Clock_Phase
+ * @{
+ */
+
+#define SPI_CPHA_1Edge ((uint16_t)0x0000)
+#define SPI_CPHA_2Edge ((uint16_t)0x0001)
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
+ ((CPHA) == SPI_CPHA_2Edge))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Slave_Select_management
+ * @{
+ */
+
+#define SPI_NSS_Soft ((uint16_t)0x0200)
+#define SPI_NSS_Hard ((uint16_t)0x0000)
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
+ ((NSS) == SPI_NSS_Hard))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_BaudRate_Prescaler
+ * @{
+ */
+
+#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
+#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
+#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
+#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
+#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
+#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
+#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
+#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_256))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_MSB_LSB_transmission
+ * @{
+ */
+
+#define SPI_FirstBit_MSB ((uint16_t)0x0000)
+#define SPI_FirstBit_LSB ((uint16_t)0x0080)
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
+ ((BIT) == SPI_FirstBit_LSB))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Mode
+ * @{
+ */
+
+#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
+#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
+#define I2S_Mode_MasterTx ((uint16_t)0x0200)
+#define I2S_Mode_MasterRx ((uint16_t)0x0300)
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
+ ((MODE) == I2S_Mode_SlaveRx) || \
+ ((MODE) == I2S_Mode_MasterTx)|| \
+ ((MODE) == I2S_Mode_MasterRx))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Standard
+ * @{
+ */
+
+#define I2S_Standard_Phillips ((uint16_t)0x0000)
+#define I2S_Standard_MSB ((uint16_t)0x0010)
+#define I2S_Standard_LSB ((uint16_t)0x0020)
+#define I2S_Standard_PCMShort ((uint16_t)0x0030)
+#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
+ ((STANDARD) == I2S_Standard_MSB) || \
+ ((STANDARD) == I2S_Standard_LSB) || \
+ ((STANDARD) == I2S_Standard_PCMShort) || \
+ ((STANDARD) == I2S_Standard_PCMLong))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Data_Format
+ * @{
+ */
+
+#define I2S_DataFormat_16b ((uint16_t)0x0000)
+#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
+#define I2S_DataFormat_24b ((uint16_t)0x0003)
+#define I2S_DataFormat_32b ((uint16_t)0x0005)
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
+ ((FORMAT) == I2S_DataFormat_16bextended) || \
+ ((FORMAT) == I2S_DataFormat_24b) || \
+ ((FORMAT) == I2S_DataFormat_32b))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_MCLK_Output
+ * @{
+ */
+
+#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
+#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
+ ((OUTPUT) == I2S_MCLKOutput_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Audio_Frequency
+ * @{
+ */
+
+#define I2S_AudioFreq_192k ((uint32_t)192000)
+#define I2S_AudioFreq_96k ((uint32_t)96000)
+#define I2S_AudioFreq_48k ((uint32_t)48000)
+#define I2S_AudioFreq_44k ((uint32_t)44100)
+#define I2S_AudioFreq_32k ((uint32_t)32000)
+#define I2S_AudioFreq_22k ((uint32_t)22050)
+#define I2S_AudioFreq_16k ((uint32_t)16000)
+#define I2S_AudioFreq_11k ((uint32_t)11025)
+#define I2S_AudioFreq_8k ((uint32_t)8000)
+#define I2S_AudioFreq_Default ((uint32_t)2)
+
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
+ ((FREQ) <= I2S_AudioFreq_192k)) || \
+ ((FREQ) == I2S_AudioFreq_Default))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Clock_Polarity
+ * @{
+ */
+
+#define I2S_CPOL_Low ((uint16_t)0x0000)
+#define I2S_CPOL_High ((uint16_t)0x0008)
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
+ ((CPOL) == I2S_CPOL_High))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_FIFO_reception_threshold
+ * @{
+ */
+
+#define SPI_RxFIFOThreshold_HF ((uint16_t)0x0000)
+#define SPI_RxFIFOThreshold_QF ((uint16_t)0x1000)
+#define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RxFIFOThreshold_HF) || \
+ ((THRESHOLD) == SPI_RxFIFOThreshold_QF))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_I2S_DMA_transfer_requests
+ * @{
+ */
+
+#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
+#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
+#define IS_SPI_I2S_DMA_REQ(REQ) ((((REQ) & (uint16_t)0xFFFC) == 0x00) && ((REQ) != 0x00))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_last_DMA_transfers
+ * @{
+ */
+
+#define SPI_LastDMATransfer_TxEvenRxEven ((uint16_t)0x0000)
+#define SPI_LastDMATransfer_TxOddRxEven ((uint16_t)0x4000)
+#define SPI_LastDMATransfer_TxEvenRxOdd ((uint16_t)0x2000)
+#define SPI_LastDMATransfer_TxOddRxOdd ((uint16_t)0x6000)
+#define IS_SPI_LAST_DMA_TRANSFER(TRANSFER) (((TRANSFER) == SPI_LastDMATransfer_TxEvenRxEven) || \
+ ((TRANSFER) == SPI_LastDMATransfer_TxOddRxEven) || \
+ ((TRANSFER) == SPI_LastDMATransfer_TxEvenRxOdd) || \
+ ((TRANSFER) == SPI_LastDMATransfer_TxOddRxOdd))
+/**
+ * @}
+ */
+/** @defgroup SPI_NSS_internal_software_management
+ * @{
+ */
+
+#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
+#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
+#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
+ ((INTERNAL) == SPI_NSSInternalSoft_Reset))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_Transmit_Receive
+ * @{
+ */
+
+#define SPI_CRC_Tx ((uint8_t)0x00)
+#define SPI_CRC_Rx ((uint8_t)0x01)
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_direction_transmit_receive
+ * @{
+ */
+
+#define SPI_Direction_Rx ((uint16_t)0xBFFF)
+#define SPI_Direction_Tx ((uint16_t)0x4000)
+#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
+ ((DIRECTION) == SPI_Direction_Tx))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_I2S_interrupts_definition
+ * @{
+ */
+
+#define SPI_I2S_IT_TXE ((uint8_t)0x71)
+#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
+#define SPI_I2S_IT_ERR ((uint8_t)0x50)
+
+#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
+ ((IT) == SPI_I2S_IT_RXNE) || \
+ ((IT) == SPI_I2S_IT_ERR))
+
+#define I2S_IT_UDR ((uint8_t)0x53)
+#define SPI_IT_MODF ((uint8_t)0x55)
+#define SPI_I2S_IT_OVR ((uint8_t)0x56)
+#define SPI_I2S_IT_FRE ((uint8_t)0x58)
+
+#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
+ ((IT) == SPI_I2S_IT_OVR) || ((IT) == SPI_IT_MODF) || \
+ ((IT) == SPI_I2S_IT_FRE)|| ((IT) == I2S_IT_UDR))
+/**
+ * @}
+ */
+
+
+/** @defgroup SPI_transmission_fifo_status_level
+ * @{
+ */
+
+#define SPI_TransmissionFIFOStatus_Empty ((uint16_t)0x0000)
+#define SPI_TransmissionFIFOStatus_1QuarterFull ((uint16_t)0x0800)
+#define SPI_TransmissionFIFOStatus_HalfFull ((uint16_t)0x1000)
+#define SPI_TransmissionFIFOStatus_Full ((uint16_t)0x1800)
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_reception_fifo_status_level
+ * @{
+ */
+#define SPI_ReceptionFIFOStatus_Empty ((uint16_t)0x0000)
+#define SPI_ReceptionFIFOStatus_1QuarterFull ((uint16_t)0x0200)
+#define SPI_ReceptionFIFOStatus_HalfFull ((uint16_t)0x0400)
+#define SPI_ReceptionFIFOStatus_Full ((uint16_t)0x0600)
+
+/**
+ * @}
+ */
+
+
+/** @defgroup SPI_I2S_flags_definition
+ * @{
+ */
+
+#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
+#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
+#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
+#define I2S_FLAG_UDR ((uint16_t)0x0008)
+#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
+#define SPI_FLAG_MODF ((uint16_t)0x0020)
+#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
+#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
+#define SPI_I2S_FLAG_FRE ((uint16_t)0x0100)
+
+
+
+#define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
+#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
+ ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
+ ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
+ ((FLAG) == SPI_I2S_FLAG_FRE)|| ((FLAG) == I2S_FLAG_CHSIDE)|| \
+ ((FLAG) == I2S_FLAG_UDR))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_polynomial
+ * @{
+ */
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the SPI configuration to the default reset state*******/
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
+
+/* Initialization and Configuration functions *********************************/
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
+void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
+void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold);
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct);
+
+/* Data transfers functions ***************************************************/
+void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data);
+void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data);
+uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx);
+uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx);
+
+/* Hardware CRC Calculation functions *****************************************/
+void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength);
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
+
+/* DMA transfers management functions *****************************************/
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
+void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer);
+
+/* Interrupts and flags management functions **********************************/
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
+uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx);
+uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx);
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F30x_SPI_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_syscfg.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,533 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_syscfg.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the SYSCFG peripheral:
+ * + Remapping the memory mapped at 0x00000000
+ * + Remapping the DMA channels
+ * + Enabling I2C fast mode plus driving capability for I2C plus
+ * + Remapping USB interrupt line
+ * + Configuring the EXTI lines connection to the GPIO port
+ * + Configuring the CLASSB requirements
+ *
+ @verbatim
+
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..] The SYSCFG registers can be accessed only when the SYSCFG
+ interface APB clock is enabled.
+ [..] To enable SYSCFG APB clock use:
+ RCC_APBPeriphClockCmd(RCC_APBPeriph_SYSCFG, ENABLE);
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_syscfg.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup SYSCFG
+ * @brief SYSCFG driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Reset value od SYSCFG_CFGR1 register */
+#define CFGR1_CLEAR_MASK ((uint32_t)0x7C000000)
+
+/* ------------ SYSCFG registers bit address in the alias region -------------*/
+#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
+
+/* --- CFGR1 Register ---*/
+/* Alias word address of USB_IT_RMP bit */
+#define CFGR1_OFFSET (SYSCFG_OFFSET + 0x00)
+#define USBITRMP_BitNumber 0x05
+#define CFGR1_USBITRMP_BB (PERIPH_BB_BASE + (CFGR1_OFFSET * 32) + (USBITRMP_BitNumber * 4))
+
+/* --- CFGR2 Register ---*/
+/* Alias word address of BYP_ADDR_PAR bit */
+#define CFGR2_OFFSET (SYSCFG_OFFSET + 0x18)
+#define BYPADDRPAR_BitNumber 0x04
+#define CFGR1_BYPADDRPAR_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (BYPADDRPAR_BitNumber * 4))
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SYSCFG_Private_Functions
+ * @{
+ */
+
+/** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions
+ * @brief SYSCFG Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### SYSCFG Initialization and Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the SYSCFG registers to their default reset values.
+ * @param None
+ * @retval None
+ * @note MEM_MODE bits are not affected by APB reset.
+ * MEM_MODE bits took the value from the user option bytes.
+ */
+void SYSCFG_DeInit(void)
+{
+ /* Reset SYSCFG_CFGR1 register to reset value without affecting MEM_MODE bits */
+ SYSCFG->CFGR1 &= SYSCFG_CFGR1_MEM_MODE;
+ /* Set FPU Interrupt Enable bits to default value */
+ SYSCFG->CFGR1 |= 0x7C000000;
+ /* Reset RAM Write protection bits to default value */
+ SYSCFG->RCR = 0x00000000;
+ /* Set EXTICRx registers to reset value */
+ SYSCFG->EXTICR[0] = 0;
+ SYSCFG->EXTICR[1] = 0;
+ SYSCFG->EXTICR[2] = 0;
+ SYSCFG->EXTICR[3] = 0;
+ /* Set CFGR2 register to reset value */
+ SYSCFG->CFGR2 = 0;
+ /* Set CFGR3 register to reset value */
+ SYSCFG->CFGR3 = 0;
+}
+
+/**
+ * @brief Configures the memory mapping at address 0x00000000.
+ * @param SYSCFG_MemoryRemap: selects the memory remapping.
+ * This parameter can be one of the following values:
+ * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
+ * @arg SYSCFG_MemoryRemap_SystemMemory: System Flash memory mapped at 0x00000000
+ * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000
+ * @retval None
+ */
+void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap)
+{
+ uint32_t tmpcfgr1 = 0;
+
+ /* Check the parameter */
+ assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap));
+
+ /* Get CFGR1 register value */
+ tmpcfgr1 = SYSCFG->CFGR1;
+
+ /* Clear MEM_MODE bits */
+ tmpcfgr1 &= (uint32_t) (~SYSCFG_CFGR1_MEM_MODE);
+
+ /* Set the new MEM_MODE bits value */
+ tmpcfgr1 |= (uint32_t) SYSCFG_MemoryRemap;
+
+ /* Set CFGR1 register with the new memory remap configuration */
+ SYSCFG->CFGR1 = tmpcfgr1;
+}
+
+/**
+ * @brief Configures the DMA channels remapping.
+ * @param SYSCFG_DMARemap: selects the DMA channels remap.
+ * This parameter can be one of the following values:
+ * @arg SYSCFG_DMARemap_TIM17: Remap TIM17 DMA requests from DMA1 channel1 to channel2
+ * @arg SYSCFG_DMARemap_TIM16: Remap TIM16 DMA requests from DMA1 channel3 to channel4
+ * @arg SYSCFG_DMARemap_TIM6DAC1Ch1: Remap TIM6/DAC1 DMA requests from DMA2 channel 3 to DMA1 channel 3
+ * @arg SYSCFG_DMARemap_TIM7DAC1Ch2: Remap TIM7/DAC2 DMA requests from DMA2 channel 4 to DMA1 channel 4
+ * @arg SYSCFG_DMARemap_ADC2ADC4: Remap ADC2 and ADC4 DMA requests from DMA2 channel1/channel3 to channel3/channel4
+ * @arg SYSCFG_DMARemap_DAC2Ch1: Remap DAC2 DMA requests to DMA1 channel5
+ * @arg SYSCFG_DMARemapCh2_SPI1_RX: Remap SPI1 RX DMA1 CH2 requests
+ * @arg SYSCFG_DMARemapCh4_SPI1_RX: Remap SPI1 RX DMA CH4 requests
+ * @arg SYSCFG_DMARemapCh6_SPI1_RX: Remap SPI1 RX DMA CH6 requests
+ * @arg SYSCFG_DMARemapCh3_SPI1_TX: Remap SPI1 TX DMA CH2 requests
+ * @arg SYSCFG_DMARemapCh5_SPI1_TX: Remap SPI1 TX DMA CH5 requests
+ * @arg SYSCFG_DMARemapCh7_SPI1_TX: Remap SPI1 TX DMA CH7 requests
+ * @arg SYSCFG_DMARemapCh7_I2C1_RX: Remap I2C1 RX DMA CH7 requests
+ * @arg SYSCFG_DMARemapCh3_I2C1_RX: Remap I2C1 RX DMA CH3 requests
+ * @arg SYSCFG_DMARemapCh5_I2C1_RX: Remap I2C1 RX DMA CH5 requests
+ * @arg SYSCFG_DMARemapCh6_I2C1_TX: Remap I2C1 TX DMA CH6 requests
+ * @arg SYSCFG_DMARemapCh2_I2C1_TX: Remap I2C1 TX DMA CH2 requests
+ * @arg SYSCFG_DMARemapCh4_I2C1_TX: Remap I2C1 TX DMA CH4 requests
+ * @arg SYSCFG_DMARemapCh4_ADC2: Remap ADC2 DMA1 Ch4 requests
+ * @arg SYSCFG_DMARemapCh2_ADC2: Remap ADC2 DMA1 Ch2 requests
+ * @param NewState: new state of the DMA channel remapping.
+ * This parameter can be: Enable or Disable.
+ * @note When enabled, DMA channel of the selected peripheral is remapped
+ * @note When disabled, Default DMA channel is mapped to the selected peripheral
+ * @note
+ * By default TIM17 DMA requests is mapped to channel 1
+ * use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Enable)
+ * to remap TIM17 DMA requests to DMA1 channel 2
+ * use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Disable)
+ * to map TIM17 DMA requests to DMA1 channel 1 (default mapping)
+ * @retval None
+ */
+void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSCFG_DMA_REMAP(SYSCFG_DMARemap));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if ((SYSCFG_DMARemap & 0x80000000)!= 0x80000000)
+ {
+ if (NewState != DISABLE)
+ {
+ /* Remap the DMA channel */
+ SYSCFG->CFGR1 |= (uint32_t)SYSCFG_DMARemap;
+ }
+ else
+ {
+ /* use the default DMA channel mapping */
+ SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_DMARemap);
+ }
+ }
+ else
+ {
+ if (NewState != DISABLE)
+ {
+ /* Remap the DMA channel */
+ SYSCFG->CFGR3 |= (uint32_t)SYSCFG_DMARemap;
+ }
+ else
+ {
+ /* use the default DMA channel mapping */
+ SYSCFG->CFGR3 &= (uint32_t)(~SYSCFG_DMARemap);
+ }
+ }
+}
+
+/**
+ * @brief Configures the remapping capabilities of DAC/TIM triggers.
+ * @param SYSCFG_TriggerRemap: selects the trigger to be remapped.
+ * This parameter can be one of the following values:
+ * @arg SYSCFG_TriggerRemap_DACTIM3: Remap DAC trigger from TIM8 to TIM3
+ * @arg SYSCFG_TriggerRemap_TIM1TIM17: Remap TIM1 ITR3 from TIM4 TRGO to TIM17 OC
+ * @arg SYSCFG_TriggerRemap_DACHRTIM1_TRIG1: Remap DAC trigger to HRTIM1 TRIG1
+ * @arg SYSCFG_TriggerRemap_DACHRTIM1_TRIG2: Remap DAC trigger to HRTIM1 TRIG2
+ * @param NewState: new state of the trigger mapping.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note ENABLE: Enable fast mode plus driving capability for selected pin
+ * @note DISABLE: Disable fast mode plus driving capability for selected pin
+ * @retval None
+ */
+void SYSCFG_TriggerRemapConfig(uint32_t SYSCFG_TriggerRemap, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSCFG_TRIGGER_REMAP(SYSCFG_TriggerRemap));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if ((SYSCFG_TriggerRemap & 0x80000000)!= 0x80000000)
+ {
+ if (NewState != DISABLE)
+ {
+ /* Remap the trigger */
+ SYSCFG->CFGR1 |= (uint32_t)SYSCFG_TriggerRemap;
+ }
+ else
+ {
+ /* Use the default trigger mapping */
+ SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_TriggerRemap);
+ }
+ }
+ else
+ {
+ if (NewState != DISABLE)
+ {
+ /* Remap the trigger */
+ SYSCFG->CFGR3 |= (uint32_t)SYSCFG_TriggerRemap;
+ }
+ else
+ {
+ /* Use the default trigger mapping */
+ SYSCFG->CFGR3 &= (uint32_t)(~SYSCFG_TriggerRemap);
+ }
+ }
+}
+
+/**
+ * @brief Configures the remapping capabilities of encoder mode.
+ * @ note This feature implement the so-called M/T method for measuring speed
+ * and position using quadrature encoders.
+ * @param SYSCFG_EncoderRemap: selects the remap option for encoder mode.
+ * This parameter can be one of the following values:
+ * @arg SYSCFG_EncoderRemap_No: No remap
+ * @arg SYSCFG_EncoderRemap_TIM2: Timer 2 IC1 and IC2 connected to TIM15 IC1 and IC2
+ * @arg SYSCFG_EncoderRemap_TIM3: Timer 3 IC1 and IC2 connected to TIM15 IC1 and IC2
+ * @arg SYSCFG_EncoderRemap_TIM4: Timer 4 IC1 and IC2 connected to TIM15 IC1 and IC2
+ * @retval None
+ */
+void SYSCFG_EncoderRemapConfig(uint32_t SYSCFG_EncoderRemap)
+{
+ /* Check the parameter */
+ assert_param(IS_SYSCFG_ENCODER_REMAP(SYSCFG_EncoderRemap));
+
+ /* Reset the encoder mode remapping bits */
+ SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_CFGR1_ENCODER_MODE);
+
+ /* Set the selected configuration */
+ SYSCFG->CFGR1 |= (uint32_t)(SYSCFG_EncoderRemap);
+}
+
+/**
+ * @brief Remaps the USB interrupt lines.
+ * @param NewState: new state of the mapping of USB interrupt lines.
+ * This parameter can be:
+ * @param ENABLE: Remap the USB interrupt line as following:
+ * @arg USB Device High Priority (USB_HP) interrupt mapped to line 74.
+ * @arg USB Device Low Priority (USB_LP) interrupt mapped to line 75.
+ * @arg USB Wakeup Interrupt (USB_WKUP) interrupt mapped to line 76.
+ * @param DISABLE: Use the default USB interrupt line:
+ * @arg USB Device High Priority (USB_HP) interrupt mapped to line 19.
+ * @arg USB Device Low Priority (USB_LP) interrupt mapped to line 20.
+ * @arg USB Wakeup Interrupt (USB_WKUP) interrupt mapped to line 42.
+ * @retval None
+ */
+void SYSCFG_USBInterruptLineRemapCmd(FunctionalState NewState)
+{
+ /* Check the parameter */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ /* Remap the USB interupt lines */
+ *(__IO uint32_t *) CFGR1_USBITRMP_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Configures the I2C fast mode plus driving capability.
+ * @param SYSCFG_I2CFastModePlus: selects the pin.
+ * This parameter can be one of the following values:
+ * @arg SYSCFG_I2CFastModePlus_PB6: Configure fast mode plus driving capability for PB6
+ * @arg SYSCFG_I2CFastModePlus_PB7: Configure fast mode plus driving capability for PB7
+ * @arg SYSCFG_I2CFastModePlus_PB8: Configure fast mode plus driving capability for PB8
+ * @arg SYSCFG_I2CFastModePlus_PB9: Configure fast mode plus driving capability for PB9
+ * @arg SYSCFG_I2CFastModePlus_I2C1: Configure fast mode plus driving capability for I2C1 pins
+ * @arg SYSCFG_I2CFastModePlus_I2C2: Configure fast mode plus driving capability for I2C2 pins
+ * @param NewState: new state of the DMA channel remapping.
+ * This parameter can be:
+ * @arg ENABLE: Enable fast mode plus driving capability for selected I2C pin
+ * @arg DISABLE: Disable fast mode plus driving capability for selected I2C pin
+ * @note For I2C1, fast mode plus driving capability can be enabled on all selected
+ * I2C1 pins using SYSCFG_I2CFastModePlus_I2C1 parameter or independently
+ * on each one of the following pins PB6, PB7, PB8 and PB9.
+ * @note For remaing I2C1 pins (PA14, PA15...) fast mode plus driving capability
+ * can be enabled only by using SYSCFG_I2CFastModePlus_I2C1 parameter.
+ * @note For all I2C2 pins fast mode plus driving capability can be enabled
+ * only by using SYSCFG_I2CFastModePlus_I2C2 parameter.
+ * @retval None
+ */
+void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSCFG_I2C_FMP(SYSCFG_I2CFastModePlus));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable fast mode plus driving capability for selected I2C pin */
+ SYSCFG->CFGR1 |= (uint32_t)SYSCFG_I2CFastModePlus;
+ }
+ else
+ {
+ /* Disable fast mode plus driving capability for selected I2C pin */
+ SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_I2CFastModePlus);
+ }
+}
+
+/**
+ * @brief Enables or disables the selected SYSCFG interrupts.
+ * @param SYSCFG_IT: specifies the SYSCFG interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg SYSCFG_IT_IXC: Inexact Interrupt
+ * @arg SYSCFG_IT_IDC: Input denormal Interrupt
+ * @arg SYSCFG_IT_OFC: Overflow Interrupt
+ * @arg SYSCFG_IT_UFC: Underflow Interrupt
+ * @arg SYSCFG_IT_DZC: Divide-by-zero Interrupt
+ * @arg SYSCFG_IT_IOC: Invalid operation Interrupt
+ * @param NewState: new state of the specified SYSCFG interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SYSCFG_ITConfig(uint32_t SYSCFG_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_SYSCFG_IT(SYSCFG_IT));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SYSCFG interrupts */
+ SYSCFG->CFGR1 |= SYSCFG_IT;
+ }
+ else
+ {
+ /* Disable the selected SYSCFG interrupts */
+ SYSCFG->CFGR1 &= ((uint32_t)~SYSCFG_IT);
+ }
+}
+
+/**
+ * @brief Selects the GPIO pin used as EXTI Line.
+ * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source
+ * for EXTI lines where x can be (A, B, C, D, E or F).
+ * @param EXTI_PinSourcex: specifies the EXTI line to be configured.
+ * This parameter can be EXTI_PinSourcex where x can be (0..15)
+ * @retval None
+ */
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
+{
+ uint32_t tmp = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
+ assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
+
+ tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
+ SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
+ SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
+}
+
+/**
+ * @brief Connects the selected parameter to the break input of TIM1.
+ * @note The selected configuration is locked and can be unlocked by system reset
+ * @param SYSCFG_Break: selects the configuration to be connected to break
+ * input of TIM1
+ * This parameter can be any combination of the following values:
+ * @arg SYSCFG_Break_PVD: PVD interrupt is connected to the break input of TIM1.
+ * @arg SYSCFG_Break_SRAMParity: SRAM Parity error is connected to the break input of TIM1.
+ * @arg SYSCFG_Break_HardFault: Lockup output of CortexM4 is connected to the break input of TIM1.
+ * @retval None
+ */
+void SYSCFG_BreakConfig(uint32_t SYSCFG_Break)
+{
+ /* Check the parameter */
+ assert_param(IS_SYSCFG_LOCK_CONFIG(SYSCFG_Break));
+
+ SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break;
+}
+
+/**
+ * @brief Disables the parity check on RAM.
+ * @note Disabling the parity check on RAM locks the configuration bit.
+ * To re-enable the parity check on RAM perform a system reset.
+ * @param None
+ * @retval None
+ */
+void SYSCFG_BypassParityCheckDisable(void)
+{
+ /* Disable the adddress parity check on RAM */
+ *(__IO uint32_t *) CFGR1_BYPADDRPAR_BB = (uint32_t)0x00000001;
+}
+
+/**
+ * @brief Enables the ICODE SRAM write protection.
+ * @note Enabling the ICODE SRAM write protection locks the configuration bit.
+ * To disable the ICODE SRAM write protection perform a system reset.
+ * @param None
+ * @retval None
+ */
+void SYSCFG_SRAMWRPEnable(uint32_t SYSCFG_SRAMWRP)
+{
+ /* Check the parameter */
+ assert_param(IS_SYSCFG_PAGE(SYSCFG_SRAMWRP));
+
+ /* Enable the write-protection on the selected ICODE SRAM page */
+ SYSCFG->RCR |= (uint32_t)SYSCFG_SRAMWRP;
+}
+
+/**
+ * @brief Checks whether the specified SYSCFG flag is set or not.
+ * @param SYSCFG_Flag: specifies the SYSCFG flag to check.
+ * This parameter can be one of the following values:
+ * @arg SYSCFG_FLAG_PE: SRAM parity error flag.
+ * @retval The new state of SYSCFG_Flag (SET or RESET).
+ */
+FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameter */
+ assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));
+
+ /* Check the status of the specified SPI flag */
+ if ((SYSCFG->CFGR2 & SYSCFG_CFGR2_SRAM_PE) != (uint32_t)RESET)
+ {
+ /* SYSCFG_Flag is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* SYSCFG_Flag is reset */
+ bitstatus = RESET;
+ }
+ /* Return the SYSCFG_Flag status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the selected SYSCFG flag.
+ * @param SYSCFG_Flag: selects the flag to be cleared.
+ * This parameter can be any combination of the following values:
+ * @arg SYSCFG_FLAG_PE: SRAM parity error flag.
+ * @retval None
+ */
+void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag)
+{
+ /* Check the parameter */
+ assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));
+
+ SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Flag;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_syscfg.h Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,355 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_syscfg.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the SYSCFG firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*!< Define to prevent recursive inclusion -----------------------------------*/
+#ifndef __STM32F30x_SYSCFG_H
+#define __STM32F30x_SYSCFG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*!< Includes ----------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup SYSCFG
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SYSCFG_Exported_Constants
+ * @{
+ */
+
+/** @defgroup SYSCFG_EXTI_Port_Sources
+ * @{
+ */
+#define EXTI_PortSourceGPIOA ((uint8_t)0x00)
+#define EXTI_PortSourceGPIOB ((uint8_t)0x01)
+#define EXTI_PortSourceGPIOC ((uint8_t)0x02)
+#define EXTI_PortSourceGPIOD ((uint8_t)0x03)
+#define EXTI_PortSourceGPIOE ((uint8_t)0x04)
+#define EXTI_PortSourceGPIOF ((uint8_t)0x05)
+
+#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
+ ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
+ ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
+ ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
+ ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
+ ((PORTSOURCE) == EXTI_PortSourceGPIOF))
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_EXTI_Pin_sources
+ * @{
+ */
+#define EXTI_PinSource0 ((uint8_t)0x00)
+#define EXTI_PinSource1 ((uint8_t)0x01)
+#define EXTI_PinSource2 ((uint8_t)0x02)
+#define EXTI_PinSource3 ((uint8_t)0x03)
+#define EXTI_PinSource4 ((uint8_t)0x04)
+#define EXTI_PinSource5 ((uint8_t)0x05)
+#define EXTI_PinSource6 ((uint8_t)0x06)
+#define EXTI_PinSource7 ((uint8_t)0x07)
+#define EXTI_PinSource8 ((uint8_t)0x08)
+#define EXTI_PinSource9 ((uint8_t)0x09)
+#define EXTI_PinSource10 ((uint8_t)0x0A)
+#define EXTI_PinSource11 ((uint8_t)0x0B)
+#define EXTI_PinSource12 ((uint8_t)0x0C)
+#define EXTI_PinSource13 ((uint8_t)0x0D)
+#define EXTI_PinSource14 ((uint8_t)0x0E)
+#define EXTI_PinSource15 ((uint8_t)0x0F)
+
+#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
+ ((PINSOURCE) == EXTI_PinSource1) || \
+ ((PINSOURCE) == EXTI_PinSource2) || \
+ ((PINSOURCE) == EXTI_PinSource3) || \
+ ((PINSOURCE) == EXTI_PinSource4) || \
+ ((PINSOURCE) == EXTI_PinSource5) || \
+ ((PINSOURCE) == EXTI_PinSource6) || \
+ ((PINSOURCE) == EXTI_PinSource7) || \
+ ((PINSOURCE) == EXTI_PinSource8) || \
+ ((PINSOURCE) == EXTI_PinSource9) || \
+ ((PINSOURCE) == EXTI_PinSource10) || \
+ ((PINSOURCE) == EXTI_PinSource11) || \
+ ((PINSOURCE) == EXTI_PinSource12) || \
+ ((PINSOURCE) == EXTI_PinSource13) || \
+ ((PINSOURCE) == EXTI_PinSource14) || \
+ ((PINSOURCE) == EXTI_PinSource15))
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_Memory_Remap_Config
+ * @{
+ */
+#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)
+#define SYSCFG_MemoryRemap_SystemMemory ((uint8_t)0x01)
+#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)
+
+
+#define IS_SYSCFG_MEMORY_REMAP(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
+ ((REMAP) == SYSCFG_MemoryRemap_SystemMemory) || \
+ ((REMAP) == SYSCFG_MemoryRemap_SRAM))
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_DMA_Remap_Config
+ * @{
+ */
+#define SYSCFG_DMARemap_TIM17 SYSCFG_CFGR1_TIM17_DMA_RMP /*!< Remap TIM17 DMA requests from channel1 to channel2 */
+#define SYSCFG_DMARemap_TIM16 SYSCFG_CFGR1_TIM16_DMA_RMP /*!< Remap TIM16 DMA requests from channel3 to channel4 */
+#define SYSCFG_DMARemap_ADC2ADC4 SYSCFG_CFGR1_ADC24_DMA_RMP /*!< Remap ADC2 and ADC4 DMA requests */
+
+#define SYSCFG_DMARemap_TIM6DAC1Ch1 SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP /* Remap TIM6/DAC1 Ch1 DMA requests */
+#define SYSCFG_DMARemap_TIM7DAC1Ch2 SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP /* Remap TIM7/DAC1 Ch2 DMA requests */
+#define SYSCFG_DMARemap_DAC2Ch1 SYSCFG_CFGR1_DAC2Ch1_DMA_RMP /* Remap DAC2 Ch1 DMA requests */
+
+#define SYSCFG_DMARemapCh2_SPI1_RX ((uint32_t)0x80000003) /* Remap SPI1 RX DMA CH2 requests */
+#define SYSCFG_DMARemapCh4_SPI1_RX ((uint32_t)0x80000001) /* Remap SPI1 RX DMA CH4 requests */
+#define SYSCFG_DMARemapCh6_SPI1_RX ((uint32_t)0x80000002) /* Remap SPI1 RX DMA CH6 requests */
+
+#define SYSCFG_DMARemapCh3_SPI1_TX ((uint32_t)0x8000000C) /* Remap SPI1 TX DMA CH2 requests */
+#define SYSCFG_DMARemapCh5_SPI1_TX ((uint32_t)0x80000004) /* Remap SPI1 TX DMA CH5 requests */
+#define SYSCFG_DMARemapCh7_SPI1_TX ((uint32_t)0x80000008) /* Remap SPI1 TX DMA CH7 requests */
+
+#define SYSCFG_DMARemapCh7_I2C1_RX ((uint32_t)0x80000030) /* Remap I2C1 RX DMA CH7 requests */
+#define SYSCFG_DMARemapCh3_I2C1_RX ((uint32_t)0x80000010) /* Remap I2C1 RX DMA CH3 requests */
+#define SYSCFG_DMARemapCh5_I2C1_RX ((uint32_t)0x80000020) /* Remap I2C1 RX DMA CH5 requests */
+
+#define SYSCFG_DMARemapCh6_I2C1_TX ((uint32_t)0x800000C0) /* Remap I2C1 TX DMA CH6 requests */
+#define SYSCFG_DMARemapCh2_I2C1_TX ((uint32_t)0x80000040) /* Remap I2C1 TX DMA CH2 requests */
+#define SYSCFG_DMARemapCh4_I2C1_TX ((uint32_t)0x80000080) /* Remap I2C1 TX DMA CH4 requests */
+
+#define SYSCFG_DMARemapCh4_ADC2 ((uint32_t)0x80000300) /* Remap ADC2 DMA1 Ch4 requests */
+#define SYSCFG_DMARemapCh2_ADC2 ((uint32_t)0x80000200) /* Remap ADC2 DMA1 Ch2 requests */
+
+/* SYSCFG_DMA_Remap_Legacy */
+#define SYSCFG_DMARemap_TIM6DAC1 SYSCFG_DMARemap_TIM6DAC1Ch1 /*!< Remap TIM6/DAC1 DMA requests */
+#define SYSCFG_DMARemap_TIM7DAC2 SYSCFG_DMARemap_TIM7DAC1Ch2 /*!< Remap TIM7/DAC2 DMA requests */
+
+#define IS_SYSCFG_DMA_REMAP(REMAP) (((REMAP) == SYSCFG_DMARemap_TIM17) || \
+ ((REMAP) == SYSCFG_DMARemap_TIM16) || \
+ ((REMAP) == SYSCFG_DMARemap_ADC2ADC4) || \
+ ((REMAP) == SYSCFG_DMARemap_TIM6DAC1Ch1) || \
+ ((REMAP) == SYSCFG_DMARemap_TIM7DAC1Ch2) || \
+ ((REMAP) == SYSCFG_DMARemap_DAC2Ch1) || \
+ ((REMAP) == SYSCFG_DMARemapCh2_SPI1_RX) || \
+ ((REMAP) == SYSCFG_DMARemapCh4_SPI1_RX) || \
+ ((REMAP) == SYSCFG_DMARemapCh6_SPI1_RX) || \
+ ((REMAP) == SYSCFG_DMARemapCh5_SPI1_TX) || \
+ ((REMAP) == SYSCFG_DMARemapCh5_SPI1_TX) || \
+ ((REMAP) == SYSCFG_DMARemapCh7_SPI1_TX) || \
+ ((REMAP) == SYSCFG_DMARemapCh7_I2C1_RX) || \
+ ((REMAP) == SYSCFG_DMARemapCh3_I2C1_RX) || \
+ ((REMAP) == SYSCFG_DMARemapCh5_I2C1_RX) || \
+ ((REMAP) == SYSCFG_DMARemapCh6_I2C1_TX) || \
+ ((REMAP) == SYSCFG_DMARemapCh2_I2C1_TX) || \
+ ((REMAP) == SYSCFG_DMARemapCh4_I2C1_TX) || \
+ ((REMAP) == SYSCFG_DMARemapCh4_ADC2) || \
+ ((REMAP) == SYSCFG_DMARemapCh2_ADC2))
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_Trigger_Remap_Config
+ * @{
+ */
+#define SYSCFG_TriggerRemap_DACTIM3 SYSCFG_CFGR1_DAC1_TRIG1_RMP /*!< Remap DAC trigger to TIM3 */
+#define SYSCFG_TriggerRemap_TIM1TIM17 SYSCFG_CFGR1_TIM1_ITR3_RMP /*!< Remap TIM1 ITR3 to TIM17 OC */
+#define SYSCFG_TriggerRemap_DACHRTIM1_TRIG1 ((uint32_t)0x80010000) /*!< Remap DAC trigger to HRTIM1 TRIG1 */
+#define SYSCFG_TriggerRemap_DACHRTIM1_TRIG2 ((uint32_t)0x80020000) /*!< Remap DAC trigger to HRTIM1 TRIG2 */
+
+#define IS_SYSCFG_TRIGGER_REMAP(REMAP) (((REMAP) == SYSCFG_TriggerRemap_DACTIM3) || \
+ ((REMAP) == SYSCFG_TriggerRemap_DACHRTIM1_TRIG1) || \
+ ((REMAP) == SYSCFG_TriggerRemap_DACHRTIM1_TRIG2) || \
+ ((REMAP) == SYSCFG_TriggerRemap_TIM1TIM17))
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_EncoderRemap_Config
+ * @{
+ */
+#define SYSCFG_EncoderRemap_No ((uint32_t)0x00000000) /*!< No redirection */
+#define SYSCFG_EncoderRemap_TIM2 SYSCFG_CFGR1_ENCODER_MODE_0 /*!< Timer 2 IC1 and IC2 connected to TIM15 IC1 and IC2 */
+#define SYSCFG_EncoderRemap_TIM3 SYSCFG_CFGR1_ENCODER_MODE_1 /*!< Timer 3 IC1 and IC2 connected to TIM15 IC1 and IC2 */
+#define SYSCFG_EncoderRemap_TIM4 SYSCFG_CFGR1_ENCODER_MODE /*!< Timer 4 IC1 and IC2 connected to TIM15 IC1 and IC2 */
+
+#define IS_SYSCFG_ENCODER_REMAP(REMAP) (((REMAP) == SYSCFG_EncoderRemap_No) || \
+ ((REMAP) == SYSCFG_EncoderRemap_TIM2) || \
+ ((REMAP) == SYSCFG_EncoderRemap_TIM3) || \
+ ((REMAP) == SYSCFG_EncoderRemap_TIM4))
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_I2C_FastModePlus_Config
+ * @{
+ */
+#define SYSCFG_I2CFastModePlus_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
+#define SYSCFG_I2CFastModePlus_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
+#define SYSCFG_I2CFastModePlus_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
+#define SYSCFG_I2CFastModePlus_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
+#define SYSCFG_I2CFastModePlus_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
+#define SYSCFG_I2CFastModePlus_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
+
+#define IS_SYSCFG_I2C_FMP(PIN) (((PIN) == SYSCFG_I2CFastModePlus_PB6) || \
+ ((PIN) == SYSCFG_I2CFastModePlus_PB7) || \
+ ((PIN) == SYSCFG_I2CFastModePlus_PB8) || \
+ ((PIN) == SYSCFG_I2CFastModePlus_PB9) || \
+ ((PIN) == SYSCFG_I2CFastModePlus_I2C1) || \
+ ((PIN) == SYSCFG_I2CFastModePlus_I2C2))
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_FPU_Interrupt_Config
+ * @{
+ */
+#define SYSCFG_IT_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Inexact Interrupt enable (interrupt disabled by default) */
+#define SYSCFG_IT_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Input denormal Interrupt enable */
+#define SYSCFG_IT_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Overflow Interrupt enable */
+#define SYSCFG_IT_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Underflow Interrupt enable */
+#define SYSCFG_IT_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Divide-by-zero Interrupt enable */
+#define SYSCFG_IT_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Invalid operation Interrupt enable */
+
+#define IS_SYSCFG_IT(IT) ((((IT) & (uint32_t)0x03FFFFFF) == 0) && ((IT) != 0))
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_Lock_Config
+ * @{
+ */
+#define SYSCFG_Break_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
+#define SYSCFG_Break_SRAMParity SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */
+#define SYSCFG_Break_Lockup SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */
+
+#define IS_SYSCFG_LOCK_CONFIG(CONFIG) (((CONFIG) == SYSCFG_Break_PVD) || \
+ ((CONFIG) == SYSCFG_Break_SRAMParity) || \
+ ((CONFIG) == SYSCFG_Break_Lockup))
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_SRAMWRP_Config
+ * @{
+ */
+#define SYSCFG_SRAMWRP_Page0 SYSCFG_RCR_PAGE0 /*!< ICODE SRAM Write protection page 0 */
+#define SYSCFG_SRAMWRP_Page1 SYSCFG_RCR_PAGE1 /*!< ICODE SRAM Write protection page 1 */
+#define SYSCFG_SRAMWRP_Page2 SYSCFG_RCR_PAGE2 /*!< ICODE SRAM Write protection page 2 */
+#define SYSCFG_SRAMWRP_Page3 SYSCFG_RCR_PAGE3 /*!< ICODE SRAM Write protection page 3 */
+#define SYSCFG_SRAMWRP_Page4 SYSCFG_RCR_PAGE4 /*!< ICODE SRAM Write protection page 4 */
+#define SYSCFG_SRAMWRP_Page5 SYSCFG_RCR_PAGE5 /*!< ICODE SRAM Write protection page 5 */
+#define SYSCFG_SRAMWRP_Page6 SYSCFG_RCR_PAGE6 /*!< ICODE SRAM Write protection page 6 */
+#define SYSCFG_SRAMWRP_Page7 SYSCFG_RCR_PAGE7 /*!< ICODE SRAM Write protection page 7 */
+
+#define IS_SYSCFG_PAGE(PAGE)((((PAGE) & (uint32_t)0xFFFFFF00) == 0x00000000) && ((PAGE) != 0x00000000))
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_flags_definition
+ * @{
+ */
+
+#define SYSCFG_FLAG_PE SYSCFG_CFGR2_SRAM_PE
+
+#define IS_SYSCFG_FLAG(FLAG) (((FLAG) == SYSCFG_FLAG_PE))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the SYSCFG configuration to the default reset state **/
+void SYSCFG_DeInit(void);
+
+/* SYSCFG configuration functions *********************************************/
+void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap);
+void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState);
+void SYSCFG_TriggerRemapConfig(uint32_t SYSCFG_TriggerRemap, FunctionalState NewState);
+void SYSCFG_EncoderRemapConfig(uint32_t SYSCFG_EncoderRemap);
+void SYSCFG_USBInterruptLineRemapCmd(FunctionalState NewState);
+void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState);
+void SYSCFG_ITConfig(uint32_t SYSCFG_IT, FunctionalState NewState);
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
+void SYSCFG_BreakConfig(uint32_t SYSCFG_Break);
+void SYSCFG_BypassParityCheckDisable(void);
+void SYSCFG_SRAMWRPEnable(uint32_t SYSCFG_SRAMWRP);
+FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag);
+void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F30x_SYSCFG_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_tim.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,4005 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_tim.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the TIM peripheral:
+ * + TimeBase management
+ * + Output Compare management
+ * + Input Capture management
+ * + Advanced-control timers (TIM1 and TIM8) specific features
+ * + Interrupts, DMA and flags management
+ * + Clocks management
+ * + Synchronization management
+ * + Specific interface management
+ * + Specific remapping management
+ *
+ @verbatim
+
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..] This driver provides functions to configure and program the TIM
+ of all stm32f30x devices.
+ These functions are split in 9 groups:
+
+ (#) TIM TimeBase management: this group includes all needed functions
+ to configure the TM Timebase unit:
+ (++) Set/Get Prescaler
+ (++) Set/Get Autoreload
+ (++) Counter modes configuration
+ (++) Set Clock division
+ (++) Select the One Pulse mode
+ (++) Update Request Configuration
+ (++) Update Disable Configuration
+ (++) Auto-Preload Configuration
+ (++) Enable/Disable the counter
+
+ (#) TIM Output Compare management: this group includes all needed
+ functions to configure the Capture/Compare unit used in Output
+ compare mode:
+ (++) Configure each channel, independently, in Output Compare mode
+ (++) Select the output compare modes
+ (++) Select the Polarities of each channel
+ (++) Set/Get the Capture/Compare register values
+ (++) Select the Output Compare Fast mode
+ (++) Select the Output Compare Forced mode
+ (++) Output Compare-Preload Configuration
+ (++) Clear Output Compare Reference
+ (++) Select the OCREF Clear signal
+ (++) Enable/Disable the Capture/Compare Channels
+
+ (#) TIM Input Capture management: this group includes all needed
+ functions to configure the Capture/Compare unit used in
+ Input Capture mode:
+ (++) Configure each channel in input capture mode
+ (++) Configure Channel1/2 in PWM Input mode
+ (++) Set the Input Capture Prescaler
+ (++) Get the Capture/Compare values
+
+ (#) Advanced-control timers (TIM1 and TIM8) specific features
+ (++) Configures the Break input, dead time, Lock level, the OSSI,
+ the OSSR State and the AOE(automatic output enable)
+ (++) Enable/Disable the TIM peripheral Main Outputs
+ (++) Select the Commutation event
+ (++) Set/Reset the Capture Compare Preload Control bit
+
+ (#) TIM interrupts, DMA and flags management
+ (++) Enable/Disable interrupt sources
+ (++) Get flags status
+ (++) Clear flags/ Pending bits
+ (++) Enable/Disable DMA requests
+ (++) Configure DMA burst mode
+ (++) Select CaptureCompare DMA request
+
+ (#) TIM clocks management: this group includes all needed functions
+ to configure the clock controller unit:
+ (++) Select internal/External clock
+ (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx
+
+ (#) TIM synchronization management: this group includes all needed
+ functions to configure the Synchronization unit:
+ (++) Select Input Trigger
+ (++) Select Output Trigger
+ (++) Select Master Slave Mode
+ (++) ETR Configuration when used as external trigger
+
+ (#) TIM specific interface management, this group includes all
+ needed functions to use the specific TIM interface:
+ (++) Encoder Interface Configuration
+ (++) Select Hall Sensor
+
+ (#) TIM specific remapping management includes the Remapping
+ configuration of specific timers
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_tim.h"
+#include "stm32f30x_rcc.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup TIM
+ * @brief TIM driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* ---------------------- TIM registers bit mask ------------------------ */
+#define SMCR_ETR_MASK ((uint16_t)0x00FF)
+#define CCMR_OFFSET ((uint16_t)0x0018)
+#define CCER_CCE_SET ((uint16_t)0x0001)
+#define CCER_CCNE_SET ((uint16_t)0x0004)
+#define CCMR_OC13M_MASK ((uint32_t)0xFFFEFF8F)
+#define CCMR_OC24M_MASK ((uint32_t)0xFEFF8FFF)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter);
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter);
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter);
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter);
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup TIM_Private_Functions
+ * @{
+ */
+
+/** @defgroup TIM_Group1 TimeBase management functions
+ * @brief TimeBase management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### TimeBase management functions #####
+ ===============================================================================
+
+
+ *** TIM Driver: how to use it in Timing(Time base) Mode ***
+ ============================================================
+ [..]
+ To use the Timer in Timing(Time base) mode, the following steps are mandatory:
+
+ (#) Enable TIM clock using
+ RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
+ (#) Fill the TIM_TimeBaseInitStruct with the desired parameters.
+ (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure
+ the Time Base unit
+ with the corresponding configuration
+ (#) Enable the NVIC if you need to generate the update interrupt.
+ (#) Enable the corresponding interrupt using the function
+ TIM_ITConfig(TIMx, TIM_IT_Update)
+ (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
+ [..]
+ (@) All other functions can be used separately to modify, if needed,
+ a specific feature of the Timer.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the TIMx peripheral registers to their default reset values.
+ * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
+ * @retval None
+
+ */
+void TIM_DeInit(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+ if (TIMx == TIM1)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
+ }
+ else if (TIMx == TIM2)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
+ }
+ else if (TIMx == TIM3)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
+ }
+ else if (TIMx == TIM4)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
+ }
+ else if (TIMx == TIM6)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
+ }
+ else if (TIMx == TIM7)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
+ }
+ else if (TIMx == TIM8)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
+ }
+ else if (TIMx == TIM15)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE);
+ }
+ else if (TIMx == TIM16)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE);
+ }
+ else
+ {
+ if (TIMx == TIM17)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE);
+ }
+ }
+}
+
+/**
+ * @brief Initializes the TIMx Time Base Unit peripheral according to
+ * the specified parameters in the TIM_TimeBaseInitStruct.
+ * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
+ * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure
+ * that contains the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
+{
+ uint16_t tmpcr1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
+ assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
+
+ tmpcr1 = TIMx->CR1;
+
+ if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) ||
+ (TIMx == TIM3)|| (TIMx == TIM4))
+ {
+ /* Select the Counter Mode */
+ tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS));
+ tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
+ }
+
+ if((TIMx != TIM6) && (TIMx != TIM7))
+ {
+ /* Set the clock division */
+ tmpcr1 &= (uint16_t)(~TIM_CR1_CKD);
+ tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
+ }
+
+ TIMx->CR1 = tmpcr1;
+
+ /* Set the Autoreload value */
+ TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
+
+ /* Set the Prescaler value */
+ TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
+
+ if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15) ||
+ (TIMx == TIM16) || (TIMx == TIM17))
+ {
+ /* Set the Repetition Counter value */
+ TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
+ }
+
+ /* Generate an update event to reload the Prescaler
+ and the repetition counter(only for TIM1 and TIM8) value immediatly */
+ TIMx->EGR = TIM_PSCReloadMode_Immediate;
+}
+
+/**
+ * @brief Fills each TIM_TimeBaseInitStruct member with its default value.
+ * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
+ * structure which will be initialized.
+ * @retval None
+ */
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
+{
+ /* Set the default configuration */
+ TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF;
+ TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
+ TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
+ TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
+ TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
+}
+
+/**
+ * @brief Configures the TIMx Prescaler.
+ * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
+ * @param Prescaler: specifies the Prescaler Register value
+ * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
+ * This parameter can be one of the following values:
+ * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
+ * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
+ * @retval None
+ */
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
+ /* Set the Prescaler value */
+ TIMx->PSC = Prescaler;
+ /* Set or reset the UG Bit */
+ TIMx->EGR = TIM_PSCReloadMode;
+}
+
+/**
+ * @brief Specifies the TIMx Counter Mode to be used.
+ * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
+ * @param TIM_CounterMode: specifies the Counter Mode to be used
+ * This parameter can be one of the following values:
+ * @arg TIM_CounterMode_Up: TIM Up Counting Mode
+ * @arg TIM_CounterMode_Down: TIM Down Counting Mode
+ * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
+ * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
+ * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
+ * @retval None
+ */
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
+{
+ uint16_t tmpcr1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
+
+ tmpcr1 = TIMx->CR1;
+
+ /* Reset the CMS and DIR Bits */
+ tmpcr1 &= (uint16_t)~(TIM_CR1_DIR | TIM_CR1_CMS);
+
+ /* Set the Counter Mode */
+ tmpcr1 |= TIM_CounterMode;
+
+ /* Write to TIMx CR1 register */
+ TIMx->CR1 = tmpcr1;
+}
+
+/**
+ * @brief Sets the TIMx Counter Register value
+ * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
+ * @param Counter: specifies the Counter register new value.
+ * @retval None
+ */
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+ /* Set the Counter Register value */
+ TIMx->CNT = Counter;
+}
+
+/**
+ * @brief Sets the TIMx Autoreload Register value
+ * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
+ * @param Autoreload: specifies the Autoreload register new value.
+ * @retval None
+ */
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+ /* Set the Autoreload Register value */
+ TIMx->ARR = Autoreload;
+}
+
+/**
+ * @brief Gets the TIMx Counter value.
+ * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
+ * @retval Counter Register value
+ */
+uint32_t TIM_GetCounter(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+ /* Get the Counter Register value */
+ return TIMx->CNT;
+}
+
+/**
+ * @brief Gets the TIMx Prescaler value.
+ * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
+ * @retval Prescaler Register value.
+ */
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+ /* Get the Prescaler Register value */
+ return TIMx->PSC;
+}
+
+/**
+ * @brief Enables or Disables the TIMx Update event.
+ * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
+ * @param NewState: new state of the TIMx UDIS bit
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Set the Update Disable Bit */
+ TIMx->CR1 |= TIM_CR1_UDIS;
+ }
+ else
+ {
+ /* Reset the Update Disable Bit */
+ TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS;
+ }
+}
+
+/**
+ * @brief Configures the TIMx Update Request Interrupt source.
+ * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
+ * @param TIM_UpdateSource: specifies the Update source.
+ * This parameter can be one of the following values:
+ * @arg TIM_UpdateSource_Regular: Source of update is the counter
+ * overflow/underflow or the setting of UG bit, or an update
+ * generation through the slave mode controller.
+ * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
+ * @retval None
+ */
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
+
+ if (TIM_UpdateSource != TIM_UpdateSource_Global)
+ {
+ /* Set the URS Bit */
+ TIMx->CR1 |= TIM_CR1_URS;
+ }
+ else
+ {
+ /* Reset the URS Bit */
+ TIMx->CR1 &= (uint16_t)~TIM_CR1_URS;
+ }
+}
+
+/**
+ * @brief Sets or resets the update interrupt flag (UIF)status bit Remapping.
+ * when sets, reading TIMx_CNT register returns UIF bit instead of CNT[31]
+ * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
+ * @param NewState: new state of the UIFREMAP bit.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_UIFRemap(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the TIM Counter */
+ TIMx->CR1 |= TIM_CR1_UIFREMAP;
+ }
+ else
+ {
+ /* Disable the TIM Counter */
+ TIMx->CR1 &= (uint16_t)~TIM_CR1_UIFREMAP;
+ }
+}
+
+/**
+ * @brief Enables or disables TIMx peripheral Preload register on ARR.
+ * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
+ * @param NewState: new state of the TIMx peripheral Preload register
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Set the ARR Preload Bit */
+ TIMx->CR1 |= TIM_CR1_ARPE;
+ }
+ else
+ {
+ /* Reset the ARR Preload Bit */
+ TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE;
+ }
+}
+
+/**
+ * @brief Selects the TIMx's One Pulse Mode.
+ * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
+ * @param TIM_OPMode: specifies the OPM Mode to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_OPMode_Single
+ * @arg TIM_OPMode_Repetitive
+ * @retval None
+ */
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
+
+ /* Reset the OPM Bit */
+ TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM;
+
+ /* Configure the OPM Mode */
+ TIMx->CR1 |= TIM_OPMode;
+}
+
+/**
+ * @brief Sets the TIMx Clock Division value.
+ * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17, to select the TIM peripheral.
+ * @param TIM_CKD: specifies the clock division value.
+ * This parameter can be one of the following value:
+ * @arg TIM_CKD_DIV1: TDTS = Tck_tim
+ * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
+ * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
+ * @retval None
+ */
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+ assert_param(IS_TIM_CKD_DIV(TIM_CKD));
+
+ /* Reset the CKD Bits */
+ TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD);
+
+ /* Set the CKD value */
+ TIMx->CR1 |= TIM_CKD;
+}
+
+/**
+ * @brief Enables or disables the specified TIM peripheral.
+ * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select
+ * the TIMx peripheral.
+ * @param NewState: new state of the TIMx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the TIM Counter */
+ TIMx->CR1 |= TIM_CR1_CEN;
+ }
+ else
+ {
+ /* Disable the TIM Counter */
+ TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN;
+ }
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Group2 Output Compare management functions
+ * @brief Output Compare management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Output Compare management functions #####
+ ===============================================================================
+
+ *** TIM Driver: how to use it in Output Compare Mode ***
+ ========================================================
+ [..]
+ To use the Timer in Output Compare mode, the following steps are mandatory:
+
+ (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
+
+ (#) Configure the TIM pins by configuring the corresponding GPIO pins
+
+ (#) Configure the Time base unit as described in the first part of this driver,
+ if needed, else the Timer will run with the default configuration:
+ (++) Autoreload value = 0xFFFF
+ (++) Prescaler value = 0x0000
+ (++) Counter mode = Up counting
+ (++) Clock Division = TIM_CKD_DIV1
+ (#) Fill the TIM_OCInitStruct with the desired parameters including:
+ (++) The TIM Output Compare mode: TIM_OCMode
+ (++) TIM Output State: TIM_OutputState
+ (++) TIM Pulse value: TIM_Pulse
+ (++) TIM Output Compare Polarity : TIM_OCPolarity
+
+ (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired channel with the
+ corresponding configuration
+
+ (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
+ [..]
+ (@) All other functions can be used separately to modify, if needed,
+ a specific feature of the Timer.
+
+ (@) In case of PWM mode, this function is mandatory:
+ TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE);
+
+ (@) If the corresponding interrupt or DMA request are needed, the user should:
+ (#@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests).
+ (#@) Enable the corresponding interrupt (or DMA request) using the function
+ TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the TIMx Channel1 according to the specified parameters in
+ * the TIM_OCInitStruct.
+ * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17, to select the TIM peripheral.
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
+ * the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+ uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= (uint32_t)~TIM_CCMR1_OC1M;
+ tmpccmrx &= (uint32_t)~TIM_CCMR1_CC1S;
+ /* Select the Output Compare Mode */
+ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)~TIM_CCER_CC1P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
+
+ /* Set the Output State */
+ tmpccer |= TIM_OCInitStruct->TIM_OutputState;
+
+ if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM15) || (TIMx == TIM16) || (TIMx == TIM17))
+ {
+ assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+ assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= (uint32_t)~TIM_CCER_CC1NP;
+ /* Set the Output N Polarity */
+ tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
+ /* Reset the Output N State */
+ tmpccer &= (uint32_t)~TIM_CCER_CC1NE;
+
+ /* Set the Output N State */
+ tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= (uint32_t)~TIM_CR2_OIS1;
+ tmpcr2 &= (uint32_t)~TIM_CR2_OIS1N;
+ /* Set the Output Idle state */
+ tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
+ /* Set the Output N Idle state */
+ tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel2 according to the specified parameters
+ * in the TIM_OCInitStruct.
+ * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM peripheral.
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
+ * the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+ uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint32_t)~TIM_CCMR1_OC2M;
+ tmpccmrx &= (uint32_t)~TIM_CCMR1_CC2S;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)~TIM_CCER_CC2P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 4);
+
+ /* Set the Output State */
+ tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 4);
+
+ if((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+ assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= (uint32_t)~TIM_CCER_CC2NP;
+ /* Set the Output N Polarity */
+ tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNPolarity << 4);
+ /* Reset the Output N State */
+ tmpccer &= (uint32_t)~TIM_CCER_CC2NE;
+
+ /* Set the Output N State */
+ tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputNState << 4);
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= (uint32_t)~TIM_CR2_OIS2;
+ tmpcr2 &= (uint32_t)~TIM_CR2_OIS2N;
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 2);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNIdleState << 2);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel3 according to the specified parameters
+ * in the TIM_OCInitStruct.
+ * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
+ * the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+ uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
+
+ /* Disable the Channel 3: Reset the CC2E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint32_t)~TIM_CCMR2_OC3M;
+ tmpccmrx &= (uint32_t)~TIM_CCMR2_CC3S;
+ /* Select the Output Compare Mode */
+ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)~TIM_CCER_CC3P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 8);
+
+ /* Set the Output State */
+ tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 8);
+
+ if((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+ assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= (uint32_t)~TIM_CCER_CC3NP;
+ /* Set the Output N Polarity */
+ tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNPolarity << 8);
+ /* Reset the Output N State */
+ tmpccer &= (uint32_t)~TIM_CCER_CC3NE;
+
+ /* Set the Output N State */
+ tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputNState << 8);
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= (uint32_t)~TIM_CR2_OIS3;
+ tmpcr2 &= (uint32_t)~TIM_CR2_OIS3N;
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 4);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNIdleState << 4);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel4 according to the specified parameters
+ * in the TIM_OCInitStruct.
+ * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
+ * the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+ uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint32_t)~TIM_CCMR2_OC4M;
+ tmpccmrx &= (uint32_t)~TIM_CCMR2_CC4S;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)~TIM_CCER_CC4P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 12);
+
+ /* Set the Output State */
+ tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 12);
+
+ if((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &=(uint32_t) ~TIM_CR2_OIS4;
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 6);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel5 according to the specified parameters
+ * in the TIM_OCInitStruct.
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
+ * the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_OC5Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+ uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
+
+ /* Disable the Channel 5: Reset the CC5E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC5E; /* to be verified*/
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR3 register value */
+ tmpccmrx = TIMx->CCMR3;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint32_t)~TIM_CCMR3_OC5M;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)~TIM_CCER_CC5P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 16);
+
+ /* Set the Output State */
+ tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 16);
+
+ if((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &=(uint32_t) ~TIM_CR2_OIS5;
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 16);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR3 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR5 = TIM_OCInitStruct->TIM_Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel6 according to the specified parameters
+ * in the TIM_OCInitStruct.
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
+ * the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_OC6Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+ uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
+
+ /* Disable the Channel 5: Reset the CC5E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC6E; /* to be verified*/
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR3 register value */
+ tmpccmrx = TIMx->CCMR3;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint32_t)~TIM_CCMR3_OC6M;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)~TIM_CCER_CC6P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 20);
+
+ /* Set the Output State */
+ tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 20);
+
+ if((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &=(uint32_t) ~TIM_CR2_OIS6;
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 18);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR3 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR6 = TIM_OCInitStruct->TIM_Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Selects the TIM Group Channel 5 and Channel 1,
+ OC1REFC is the logical AND of OC1REFC and OC5REF.
+ * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
+ * @param NewState: new state of the Commutation event.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_SelectGC5C1(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Set the GC5C1 Bit */
+ TIMx->CCR5 |= TIM_CCR5_GC5C1;
+ }
+ else
+ {
+ /* Reset the GC5C1 Bit */
+ TIMx->CCR5 &= (uint32_t)~TIM_CCR5_GC5C1;
+ }
+}
+
+/**
+ * @brief Selects the TIM Group Channel 5 and Channel 2,
+ OC2REFC is the logical AND of OC2REFC and OC5REF.
+ * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
+ * @param NewState: new state of the Commutation event.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_SelectGC5C2(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Set the GC5C2 Bit */
+ TIMx->CCR5 |= TIM_CCR5_GC5C2;
+ }
+ else
+ {
+ /* Reset the GC5C2 Bit */
+ TIMx->CCR5 &= (uint32_t)~TIM_CCR5_GC5C2;
+ }
+}
+
+
+/**
+ * @brief Selects the TIM Group Channel 5 and Channel 3,
+ OC3REFC is the logical AND of OC3REFC and OC5REF.
+ * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
+ * @param NewState: new state of the Commutation event.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_SelectGC5C3(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Set the GC5C3 Bit */
+ TIMx->CCR5 |= TIM_CCR5_GC5C3;
+ }
+ else
+ {
+ /* Reset the GC5C3 Bit */
+ TIMx->CCR5 &= (uint32_t)~TIM_CCR5_GC5C3;
+ }
+}
+
+/**
+ * @brief Fills each TIM_OCInitStruct member with its default value.
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+ /* Set the default configuration */
+ TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
+ TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
+ TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
+ TIM_OCInitStruct->TIM_Pulse = 0x00000000;
+ TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
+ TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
+ TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
+ TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
+}
+
+/**
+ * @brief Selects the TIM Output Compare Mode.
+ * @note This function disables the selected channel before changing the Output
+ * Compare Mode. If needed, user has to enable this channel using
+ * TIM_CCxCmd() and TIM_CCxNCmd() functions.
+ * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
+ * @param TIM_Channel: specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_Channel_1: TIM Channel 1
+ * @arg TIM_Channel_2: TIM Channel 2
+ * @arg TIM_Channel_3: TIM Channel 3
+ * @arg TIM_Channel_4: TIM Channel 4
+ * @param TIM_OCMode: specifies the TIM Output Compare Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCMode_Timing
+ * @arg TIM_OCMode_Active
+ * @arg TIM_OCMode_Toggle
+ * @arg TIM_OCMode_PWM1
+ * @arg TIM_OCMode_PWM2
+ * @arg TIM_ForcedAction_Active
+ * @arg TIM_ForcedAction_InActive
+ * @arg TIM_OCMode_Retrigerrable_OPM1
+ * @arg TIM_OCMode_Retrigerrable_OPM2
+ * @arg TIM_OCMode_Combined_PWM1
+ * @arg TIM_OCMode_Combined_PWM2
+ * @arg TIM_OCMode_Asymmetric_PWM1
+ * @arg TIM_OCMode_Asymmetric_PWM2
+ * @retval None
+ */
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint32_t TIM_OCMode)
+{
+ uint32_t tmp = 0;
+ uint16_t tmp1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+ assert_param(IS_TIM_CHANNEL(TIM_Channel));
+ assert_param(IS_TIM_OCM(TIM_OCMode));
+
+ tmp = (uint32_t) TIMx;
+ tmp += CCMR_OFFSET;
+
+ tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;
+
+ /* Disable the Channel: Reset the CCxE Bit */
+ TIMx->CCER &= (uint16_t) ~tmp1;
+
+ if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
+ {
+ tmp += (TIM_Channel>>1);
+
+ /* Reset the OCxM bits in the CCMRx register */
+ *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK;
+
+ /* Configure the OCxM bits in the CCMRx register */
+ *(__IO uint32_t *) tmp |= TIM_OCMode;
+ }
+ else
+ {
+ tmp += (uint32_t)(TIM_Channel - (uint32_t)4)>> (uint32_t)1;
+
+ /* Reset the OCxM bits in the CCMRx register */
+ *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK;
+
+ /* Configure the OCxM bits in the CCMRx register */
+ *(__IO uint32_t *) tmp |= (uint32_t)(TIM_OCMode << 8);
+ }
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare1 Register value
+ * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
+ * @param Compare1: specifies the Capture Compare1 register new value.
+ * @retval None
+ */
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+
+ /* Set the Capture Compare1 Register value */
+ TIMx->CCR1 = Compare1;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare2 Register value
+ * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
+ * peripheral.
+ * @param Compare2: specifies the Capture Compare2 register new value.
+ * @retval None
+ */
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+
+ /* Set the Capture Compare2 Register value */
+ TIMx->CCR2 = Compare2;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare3 Register value
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param Compare3: specifies the Capture Compare3 register new value.
+ * @retval None
+ */
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+
+ /* Set the Capture Compare3 Register value */
+ TIMx->CCR3 = Compare3;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare4 Register value
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param Compare4: specifies the Capture Compare4 register new value.
+ * @retval None
+ */
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+
+ /* Set the Capture Compare4 Register value */
+ TIMx->CCR4 = Compare4;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare5 Register value
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
+ * @param Compare5: specifies the Capture Compare5 register new value.
+ * @retval None
+ */
+void TIM_SetCompare5(TIM_TypeDef* TIMx, uint32_t Compare5)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+
+ /* Set the Capture Compare5 Register value */
+ TIMx->CCR5 = Compare5;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare6 Register value
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
+ * @param Compare6: specifies the Capture Compare5 register new value.
+ * @retval None
+ */
+void TIM_SetCompare6(TIM_TypeDef* TIMx, uint32_t Compare6)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+
+ /* Set the Capture Compare6 Register value */
+ TIMx->CCR6 = Compare6;
+}
+
+/**
+ * @brief Forces the TIMx output 1 waveform to active or inactive level.
+ * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_ForcedAction_Active: Force active level on OC1REF
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
+ * @retval None
+ */
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint32_t tmpccmr1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Reset the OC1M Bits */
+ tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC1M;
+
+ /* Configure The Forced output Mode */
+ tmpccmr1 |= TIM_ForcedAction;
+
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Forces the TIMx output 2 waveform to active or inactive level.
+ * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
+ * peripheral.
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_ForcedAction_Active: Force active level on OC2REF
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
+ * @retval None
+ */
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint32_t tmpccmr1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Reset the OC2M Bits */
+ tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC2M;
+
+ /* Configure The Forced output Mode */
+ tmpccmr1 |= ((uint32_t)TIM_ForcedAction << 8);
+
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Forces the TIMx output 3 waveform to active or inactive level.
+ * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_ForcedAction_Active: Force active level on OC3REF
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
+ * @retval None
+ */
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint32_t tmpccmr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+
+ tmpccmr2 = TIMx->CCMR2;
+
+ /* Reset the OC1M Bits */
+ tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC3M;
+
+ /* Configure The Forced output Mode */
+ tmpccmr2 |= TIM_ForcedAction;
+
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Forces the TIMx output 4 waveform to active or inactive level.
+ * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_ForcedAction_Active: Force active level on OC4REF
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
+ * @retval None
+ */
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint32_t tmpccmr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+ tmpccmr2 = TIMx->CCMR2;
+
+ /* Reset the OC2M Bits */
+ tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC4M;
+
+ /* Configure The Forced output Mode */
+ tmpccmr2 |= ((uint32_t)TIM_ForcedAction << 8);
+
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Forces the TIMx output 5 waveform to active or inactive level.
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_ForcedAction_Active: Force active level on OC5REF
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC5REF.
+ * @retval None
+ */
+void TIM_ForcedOC5Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint32_t tmpccmr3 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+ tmpccmr3 = TIMx->CCMR3;
+
+ /* Reset the OC5M Bits */
+ tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC5M;
+
+ /* Configure The Forced output Mode */
+ tmpccmr3 |= (uint32_t)(TIM_ForcedAction);
+
+ /* Write to TIMx CCMR3 register */
+ TIMx->CCMR3 = tmpccmr3;
+}
+
+/**
+ * @brief Forces the TIMx output 6 waveform to active or inactive level.
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_ForcedAction_Active: Force active level on OC5REF
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC5REF.
+ * @retval None
+ */
+void TIM_ForcedOC6Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint32_t tmpccmr3 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+ tmpccmr3 = TIMx->CCMR3;
+
+ /* Reset the OC6M Bits */
+ tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC6M;
+
+ /* Configure The Forced output Mode */
+ tmpccmr3 |= ((uint32_t)TIM_ForcedAction << 8);
+
+ /* Write to TIMx CCMR3 register */
+ TIMx->CCMR3 = tmpccmr3;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR1.
+ * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPreload_Enable
+ * @arg TIM_OCPreload_Disable
+ * @retval None
+ */
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+ uint32_t tmpccmr1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Reset the OC1PE Bit */
+ tmpccmr1 &= (uint32_t)(~TIM_CCMR1_OC1PE);
+
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr1 |= TIM_OCPreload;
+
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR2.
+ * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
+ * peripheral.
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPreload_Enable
+ * @arg TIM_OCPreload_Disable
+ * @retval None
+ */
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+ uint32_t tmpccmr1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Reset the OC2PE Bit */
+ tmpccmr1 &= (uint32_t)(~TIM_CCMR1_OC2PE);
+
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr1 |= ((uint32_t)TIM_OCPreload << 8);
+
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR3.
+ * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPreload_Enable
+ * @arg TIM_OCPreload_Disable
+ * @retval None
+ */
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+ uint32_t tmpccmr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+
+ tmpccmr2 = TIMx->CCMR2;
+
+ /* Reset the OC3PE Bit */
+ tmpccmr2 &= (uint32_t)(~TIM_CCMR2_OC3PE);
+
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr2 |= TIM_OCPreload;
+
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR4.
+ * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPreload_Enable
+ * @arg TIM_OCPreload_Disable
+ * @retval None
+ */
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+ uint32_t tmpccmr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+
+ tmpccmr2 = TIMx->CCMR2;
+
+ /* Reset the OC4PE Bit */
+ tmpccmr2 &= (uint32_t)(~TIM_CCMR2_OC4PE);
+
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr2 |= ((uint32_t)TIM_OCPreload << 8);
+
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR5.
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPreload_Enable
+ * @arg TIM_OCPreload_Disable
+ * @retval None
+ */
+void TIM_OC5PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+ uint32_t tmpccmr3 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+
+ tmpccmr3 = TIMx->CCMR3;
+
+ /* Reset the OC5PE Bit */
+ tmpccmr3 &= (uint32_t)(~TIM_CCMR3_OC5PE);
+
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr3 |= (uint32_t)(TIM_OCPreload);
+
+ /* Write to TIMx CCMR3 register */
+ TIMx->CCMR3 = tmpccmr3;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR6.
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPreload_Enable
+ * @arg TIM_OCPreload_Disable
+ * @retval None
+ */
+void TIM_OC6PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+ uint32_t tmpccmr3 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+
+ tmpccmr3 = TIMx->CCMR3;
+
+ /* Reset the OC5PE Bit */
+ tmpccmr3 &= (uint32_t)(~TIM_CCMR3_OC6PE);
+
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr3 |= ((uint32_t)TIM_OCPreload << 8);
+
+ /* Write to TIMx CCMR3 register */
+ TIMx->CCMR3 = tmpccmr3;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 1 Fast feature.
+ * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable
+ * @retval None
+ */
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+ uint32_t tmpccmr1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Reset the OC1FE Bit */
+ tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC1FE;
+
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr1 |= TIM_OCFast;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 2 Fast feature.
+ * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
+ * peripheral.
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable
+ * @retval None
+ */
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+ uint32_t tmpccmr1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Reset the OC2FE Bit */
+ tmpccmr1 &= (uint32_t)(~TIM_CCMR1_OC2FE);
+
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr1 |= ((uint32_t)TIM_OCFast << 8);
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 3 Fast feature.
+ * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable
+ * @retval None
+ */
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+ uint32_t tmpccmr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmr2 = TIMx->CCMR2;
+
+ /* Reset the OC3FE Bit */
+ tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC3FE;
+
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr2 |= TIM_OCFast;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 4 Fast feature.
+ * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable
+ * @retval None
+ */
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+ uint32_t tmpccmr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmr2 = TIMx->CCMR2;
+
+ /* Reset the OC4FE Bit */
+ tmpccmr2 &= (uint32_t)(~TIM_CCMR2_OC4FE);
+
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr2 |= ((uint32_t)TIM_OCFast << 8);
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF1 signal on an external event
+ * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCClear_Enable: TIM Output clear enable
+ * @arg TIM_OCClear_Disable: TIM Output clear disable
+ * @retval None
+ */
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+ uint32_t tmpccmr1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Reset the OC1CE Bit */
+ tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC1CE;
+
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr1 |= TIM_OCClear;
+
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF2 signal on an external event
+ * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
+ * peripheral.
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCClear_Enable: TIM Output clear enable
+ * @arg TIM_OCClear_Disable: TIM Output clear disable
+ * @retval None
+ */
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+ uint32_t tmpccmr1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Reset the OC2CE Bit */
+ tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC2CE;
+
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr1 |= ((uint32_t)TIM_OCClear << 8);
+
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF3 signal on an external event
+ * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCClear_Enable: TIM Output clear enable
+ * @arg TIM_OCClear_Disable: TIM Output clear disable
+ * @retval None
+ */
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+ uint32_t tmpccmr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+
+ tmpccmr2 = TIMx->CCMR2;
+
+ /* Reset the OC3CE Bit */
+ tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC3CE;
+
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr2 |= TIM_OCClear;
+
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF4 signal on an external event
+ * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCClear_Enable: TIM Output clear enable
+ * @arg TIM_OCClear_Disable: TIM Output clear disable
+ * @retval None
+ */
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+ uint32_t tmpccmr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+
+ tmpccmr2 = TIMx->CCMR2;
+
+ /* Reset the OC4CE Bit */
+ tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC4CE;
+
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr2 |= ((uint32_t)TIM_OCClear << 8);
+
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF5 signal on an external event
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCClear_Enable: TIM Output clear enable
+ * @arg TIM_OCClear_Disable: TIM Output clear disable
+ * @retval None
+ */
+void TIM_ClearOC5Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+ uint32_t tmpccmr3 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+
+ tmpccmr3 = TIMx->CCMR3;
+
+ /* Reset the OC5CE Bit */
+ tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC5CE;
+
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr3 |= (uint32_t)(TIM_OCClear);
+
+ /* Write to TIMx CCMR3 register */
+ TIMx->CCMR3 = tmpccmr3;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF6 signal on an external event
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCClear_Enable: TIM Output clear enable
+ * @arg TIM_OCClear_Disable: TIM Output clear disable
+ * @retval None
+ */
+void TIM_ClearOC6Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+ uint32_t tmpccmr3 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+
+ tmpccmr3 = TIMx->CCMR3;
+
+ /* Reset the OC5CE Bit */
+ tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC6CE;
+
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr3 |= ((uint32_t)TIM_OCClear << 8);
+
+ /* Write to TIMx CCMR3 register */
+ TIMx->CCMR3 = tmpccmr3;
+}
+
+/**
+ * @brief Selects the OCReference Clear source.
+ * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
+ * @param TIM_OCReferenceClear: specifies the OCReference Clear source.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF.
+ * @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input.
+ * @retval None
+ */
+void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+ assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear));
+
+ /* Set the TIM_OCReferenceClear source */
+ TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_OCCS);
+ TIMx->SMCR |= TIM_OCReferenceClear;
+}
+
+/**
+ * @brief Configures the TIMx channel 1 polarity.
+ * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
+ * @param TIM_OCPolarity: specifies the OC1 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPolarity_High: Output Compare active high
+ * @arg TIM_OCPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+ uint32_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+
+ tmpccer = TIMx->CCER;
+
+ /* Set or Reset the CC1P Bit */
+ tmpccer &= (uint32_t)(~TIM_CCER_CC1P);
+ tmpccer |= TIM_OCPolarity;
+
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx Channel 1N polarity.
+ * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
+ * @param TIM_OCNPolarity: specifies the OC1N Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCNPolarity_High: Output Compare active high
+ * @arg TIM_OCNPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+
+ tmpccer = TIMx->CCER;
+
+ /* Set or Reset the CC1NP Bit */
+ tmpccer &= (uint32_t)~TIM_CCER_CC1NP;
+ tmpccer |= TIM_OCNPolarity;
+
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 2 polarity.
+ * @param TIMx: where x can be 1, 2, 3, 4 8 or 15 to select the TIM
+ * peripheral.
+ * @param TIM_OCPolarity: specifies the OC2 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPolarity_High: Output Compare active high
+ * @arg TIM_OCPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+ uint32_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+
+ tmpccer = TIMx->CCER;
+
+ /* Set or Reset the CC2P Bit */
+ tmpccer &= (uint32_t)(~TIM_CCER_CC2P);
+ tmpccer |= ((uint32_t)TIM_OCPolarity << 4);
+
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx Channel 2N polarity.
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCNPolarity: specifies the OC2N Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCNPolarity_High: Output Compare active high
+ * @arg TIM_OCNPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+ uint32_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+
+ tmpccer = TIMx->CCER;
+
+ /* Set or Reset the CC2NP Bit */
+ tmpccer &= (uint32_t)~TIM_CCER_CC2NP;
+ tmpccer |= ((uint32_t)TIM_OCNPolarity << 4);
+
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 3 polarity.
+ * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
+ * @param TIM_OCPolarity: specifies the OC3 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPolarity_High: Output Compare active high
+ * @arg TIM_OCPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+ uint32_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+
+ tmpccer = TIMx->CCER;
+
+ /* Set or Reset the CC3P Bit */
+ tmpccer &= (uint32_t)~TIM_CCER_CC3P;
+ tmpccer |= ((uint32_t)TIM_OCPolarity << 8);
+
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx Channel 3N polarity.
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCNPolarity: specifies the OC3N Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCNPolarity_High: Output Compare active high
+ * @arg TIM_OCNPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+ uint32_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+
+ tmpccer = TIMx->CCER;
+
+ /* Set or Reset the CC3NP Bit */
+ tmpccer &= (uint32_t)~TIM_CCER_CC3NP;
+ tmpccer |= ((uint32_t)TIM_OCNPolarity << 8);
+
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 4 polarity.
+ * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
+ * @param TIM_OCPolarity: specifies the OC4 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPolarity_High: Output Compare active high
+ * @arg TIM_OCPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+ uint32_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+
+ tmpccer = TIMx->CCER;
+
+ /* Set or Reset the CC4P Bit */
+ tmpccer &= (uint32_t)~TIM_CCER_CC4P;
+ tmpccer |= ((uint32_t)TIM_OCPolarity << 12);
+
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 5 polarity.
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCPolarity: specifies the OC5 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPolarity_High: Output Compare active high
+ * @arg TIM_OCPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC5PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+ uint32_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+
+ tmpccer = TIMx->CCER;
+
+ /* Set or Reset the CC5P Bit */
+ tmpccer &= (uint32_t)~TIM_CCER_CC5P;
+ tmpccer |= ((uint32_t)TIM_OCPolarity << 16);
+
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 6 polarity.
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCPolarity: specifies the OC6 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPolarity_High: Output Compare active high
+ * @arg TIM_OCPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC6PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+ uint32_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+
+ tmpccer = TIMx->CCER;
+
+ /* Set or Reset the CC6P Bit */
+ tmpccer &= (uint32_t)~TIM_CCER_CC6P;
+ tmpccer |= ((uint32_t)TIM_OCPolarity << 20);
+
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel x.
+ * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
+ * @param TIM_Channel: specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_Channel_1: TIM Channel 1
+ * @arg TIM_Channel_2: TIM Channel 2
+ * @arg TIM_Channel_3: TIM Channel 3
+ * @arg TIM_Channel_4: TIM Channel 4
+ * @arg TIM_Channel_5: TIM Channel 5
+ * @arg TIM_Channel_6: TIM Channel 6
+ * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
+ * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
+ * @retval None
+ */
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
+{
+ uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+ assert_param(IS_TIM_CHANNEL(TIM_Channel));
+ assert_param(IS_TIM_CCX(TIM_CCx));
+
+ tmp = (uint32_t)CCER_CCE_SET << (uint32_t)TIM_Channel;
+
+ /* Reset the CCxE Bit */
+ TIMx->CCER &= (uint32_t)(~tmp);
+
+ /* Set or reset the CCxE Bit */
+ TIMx->CCER |= ((uint32_t)TIM_CCx << (uint32_t)TIM_Channel);
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel xN.
+ * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
+ * @param TIM_Channel: specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_Channel_1: TIM Channel 1
+ * @arg TIM_Channel_2: TIM Channel 2
+ * @arg TIM_Channel_3: TIM Channel 3
+ * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
+ * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
+ * @retval None
+ */
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
+{
+ uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
+ assert_param(IS_TIM_CCXN(TIM_CCxN));
+
+ tmp = (uint32_t)CCER_CCNE_SET << (uint32_t)TIM_Channel;
+
+ /* Reset the CCxNE Bit */
+ TIMx->CCER &= (uint32_t) ~tmp;
+
+ /* Set or reset the CCxNE Bit */
+ TIMx->CCER |= ((uint32_t)TIM_CCxN << (uint32_t)TIM_Channel);
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Group3 Input Capture management functions
+ * @brief Input Capture management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Input Capture management functions #####
+ ===============================================================================
+
+ *** TIM Driver: how to use it in Input Capture Mode ***
+ =======================================================
+ [..]
+ To use the Timer in Input Capture mode, the following steps are mandatory:
+
+ (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
+
+ (#) Configure the TIM pins by configuring the corresponding GPIO pins
+
+ (#) Configure the Time base unit as described in the first part of this driver,
+ if needed, else the Timer will run with the default configuration:
+ (++) Autoreload value = 0xFFFF
+ (++) Prescaler value = 0x0000
+ (++) Counter mode = Up counting
+ (++) Clock Division = TIM_CKD_DIV1
+
+ (#) Fill the TIM_ICInitStruct with the desired parameters including:
+ (++) TIM Channel: TIM_Channel
+ (++) TIM Input Capture polarity: TIM_ICPolarity
+ (++) TIM Input Capture selection: TIM_ICSelection
+ (++) TIM Input Capture Prescaler: TIM_ICPrescaler
+ (++) TIM Input CApture filter value: TIM_ICFilter
+
+ (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel with the
+ corresponding configuration and to measure only frequency or duty cycle of the input signal,
+ or,
+ Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired channels with the
+ corresponding configuration and to measure the frequency and the duty cycle of the input signal
+
+ (#) Enable the NVIC or the DMA to read the measured frequency.
+
+ (#) Enable the corresponding interrupt (or DMA request) to read the Captured value,
+ using the function TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))
+
+ (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
+
+ (#) Use TIM_GetCapturex(TIMx); to read the captured value.
+ [..]
+ (@) All other functions can be used separately to modify, if needed,
+ a specific feature of the Timer.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the TIM peripheral according to the specified parameters
+ * in the TIM_ICInitStruct.
+ * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
+ * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains
+ * the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+ assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
+ assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
+ assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
+
+ if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
+ {
+ /* TI1 Configuration */
+ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+ TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+ else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
+ {
+ /* TI2 Configuration */
+ TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+ TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+ else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
+ {
+ /* TI3 Configuration */
+ TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+ TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+ else
+ {
+ /* TI4 Configuration */
+ TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+ TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+}
+
+/**
+ * @brief Fills each TIM_ICInitStruct member with its default value.
+ * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+ /* Set the default configuration */
+ TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
+ TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
+ TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
+ TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
+ TIM_ICInitStruct->TIM_ICFilter = 0x00;
+}
+
+/**
+ * @brief Configures the TIM peripheral according to the specified parameters
+ * in the TIM_ICInitStruct to measure an external PWM signal.
+ * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
+ * peripheral.
+ * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains
+ * the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+ uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
+ uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+
+ /* Select the Opposite Input Polarity */
+ if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
+ {
+ icoppositepolarity = TIM_ICPolarity_Falling;
+ }
+ else
+ {
+ icoppositepolarity = TIM_ICPolarity_Rising;
+ }
+ /* Select the Opposite Input */
+ if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
+ {
+ icoppositeselection = TIM_ICSelection_IndirectTI;
+ }
+ else
+ {
+ icoppositeselection = TIM_ICSelection_DirectTI;
+ }
+ if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
+ {
+ /* TI1 Configuration */
+ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ /* TI2 Configuration */
+ TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+ else
+ {
+ /* TI2 Configuration */
+ TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ /* TI1 Configuration */
+ TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 1 value.
+ * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
+ * @retval Capture Compare 1 Register value.
+ */
+uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+
+ /* Get the Capture 1 Register value */
+ return TIMx->CCR1;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 2 value.
+ * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
+ * peripheral.
+ * @retval Capture Compare 2 Register value.
+ */
+uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+
+ /* Get the Capture 2 Register value */
+ return TIMx->CCR2;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 3 value.
+ * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
+ * @retval Capture Compare 3 Register value.
+ */
+uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+
+ /* Get the Capture 3 Register value */
+ return TIMx->CCR3;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 4 value.
+ * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
+ * @retval Capture Compare 4 Register value.
+ */
+uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+
+ /* Get the Capture 4 Register value */
+ return TIMx->CCR4;
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 1 prescaler.
+ * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
+ * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ * @retval None
+ */
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+
+ /* Reset the IC1PSC Bits */
+ TIMx->CCMR1 &= (uint32_t)~TIM_CCMR1_IC1PSC;
+
+ /* Set the IC1PSC value */
+ TIMx->CCMR1 |= TIM_ICPSC;
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 2 prescaler.
+ * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
+ * peripheral.
+ * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ * @retval None
+ */
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+
+ /* Reset the IC2PSC Bits */
+ TIMx->CCMR1 &= (uint32_t)~TIM_CCMR1_IC2PSC;
+
+ /* Set the IC2PSC value */
+ TIMx->CCMR1 |= (uint32_t)((uint32_t)TIM_ICPSC << 8);
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 3 prescaler.
+ * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
+ * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ * @retval None
+ */
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+
+ /* Reset the IC3PSC Bits */
+ TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC;
+
+ /* Set the IC3PSC value */
+ TIMx->CCMR2 |= TIM_ICPSC;
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 4 prescaler.
+ * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
+ * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ * @retval None
+ */
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+
+ /* Reset the IC4PSC Bits */
+ TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC;
+
+ /* Set the IC4PSC value */
+ TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Group4 Advanced-control timers (TIM1 and TIM8) specific features
+ * @brief Advanced-control timers (TIM1 and TIM8) specific features
+ *
+@verbatim
+ ===============================================================================
+ ##### Advanced-control timers (TIM1 and TIM8) specific features #####
+ ===============================================================================
+
+ *** TIM Driver: how to use the Break feature ***
+ ================================================
+ [..]
+ After configuring the Timer channel(s) in the appropriate Output Compare mode:
+
+ (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer
+ Break Polarity, dead time, Lock level, the OSSI/OSSR State and the
+ AOE(automatic output enable).
+
+ (#) Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer
+
+ (#) Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE)
+
+ (#) Once the break even occurs, the Timer's output signals are put in reset
+ state or in a known state (according to the configuration made in
+ TIM_BDTRConfig() function).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
+ * and the AOE(automatic output enable).
+ * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM
+ * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
+ * contains the BDTR Register configuration information for the TIM peripheral.
+ * @retval None
+ */
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
+ assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
+ assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
+ assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
+ assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
+ assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
+
+ /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */
+ TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
+ TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
+ TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
+ TIM_BDTRInitStruct->TIM_AutomaticOutput;
+}
+
+/**
+ * @brief Configures the Break1 feature.
+ * @param TIMx: where x can be 1 or 8 to select the TIM
+ * @param TIM_Break1Polarity: specifies the Break1 polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_Break1Polarity_Low: Break1 input is active low
+ * @arg TIM_Break1Polarity_High: Break1 input is active high
+ * @param TIM_Break1Filter: specifies the Break1 filter value.
+ * This parameter must be a value between 0x00 and 0x0F
+ * @retval None
+ */
+void TIM_Break1Config(TIM_TypeDef* TIMx, uint32_t TIM_Break1Polarity, uint8_t TIM_Break1Filter)
+{ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+ assert_param(IS_TIM_BREAK1_FILTER(TIM_Break1Filter));
+
+ /* Reset the BKP and BKF Bits */
+ TIMx->BDTR &= (uint32_t)~ (TIM_BDTR_BKP | TIM_BDTR_BKF);
+ /* Configure the Break1 polarity and filter */
+ TIMx->BDTR |= TIM_Break1Polarity |((uint32_t)TIM_Break1Filter << 16);
+}
+
+/**
+ * @brief Configures the Break2 feature.
+ * @param TIMx: where x can be 1 or 8 to select the TIM
+ * @param TIM_Break2Polarity: specifies the Break2 polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_Break2Polarity_Low: Break2 input is active low
+ * @arg TIM_Break2Polarity_High: Break2 input is active high
+ * @param TIM_Break2Filter: specifies the Break2 filter value.
+ * This parameter must be a value between 0x00 and 0x0F
+ * @retval None
+ */
+void TIM_Break2Config(TIM_TypeDef* TIMx, uint32_t TIM_Break2Polarity, uint8_t TIM_Break2Filter)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+ assert_param(IS_TIM_BREAK2_FILTER(TIM_Break2Filter));
+
+ /* Reset the BKP and BKF Bits */
+ TIMx->BDTR &= (uint32_t)~ (TIM_BDTR_BK2P | TIM_BDTR_BK2F);
+
+ /* Configure the Break1 polarity and filter */
+ TIMx->BDTR |= TIM_Break2Polarity |((uint32_t)TIM_Break2Filter << 20);
+}
+
+/**
+ * @brief Enables or disables the TIM Break1 input.
+ * @param TIMx: where x can be 1, 8, 1, 16 or 17 to select the TIMx peripheral.
+ * @param NewState: new state of the TIM Break1 input.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_Break1Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the Break1 */
+ TIMx->BDTR |= TIM_BDTR_BKE;
+ }
+ else
+ {
+ /* Disable the Break1 */
+ TIMx->BDTR &= (uint32_t)~TIM_BDTR_BKE;
+ }
+}
+
+/**
+ * @brief Enables or disables the TIM Break2 input.
+ * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral.
+ * @param NewState: new state of the TIM Break2 input.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_Break2Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the Break1 */
+ TIMx->BDTR |= TIM_BDTR_BK2E;
+ }
+ else
+ {
+ /* Disable the Break1 */
+ TIMx->BDTR &= (uint32_t)~TIM_BDTR_BK2E;
+ }
+}
+
+/**
+ * @brief Fills each TIM_BDTRInitStruct member with its default value.
+ * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
+ * will be initialized.
+ * @retval None
+ */
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
+{
+ /* Set the default configuration */
+ TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
+ TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
+ TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
+ TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
+ TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
+ TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
+ TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
+}
+
+/**
+ * @brief Enables or disables the TIM peripheral Main Outputs.
+ * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral.
+ * @param NewState: new state of the TIM peripheral Main Outputs.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the TIM Main Output */
+ TIMx->BDTR |= TIM_BDTR_MOE;
+ }
+ else
+ {
+ /* Disable the TIM Main Output */
+ TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE;
+ }
+}
+
+/**
+ * @brief Selects the TIM peripheral Commutation event.
+ * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral
+ * @param NewState: new state of the Commutation event.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Set the COM Bit */
+ TIMx->CR2 |= TIM_CR2_CCUS;
+ }
+ else
+ {
+ /* Reset the COM Bit */
+ TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS;
+ }
+}
+
+/**
+ * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
+ * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
+ * @param NewState: new state of the Capture Compare Preload Control bit
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Set the CCPC Bit */
+ TIMx->CR2 |= TIM_CR2_CCPC;
+ }
+ else
+ {
+ /* Reset the CCPC Bit */
+ TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC;
+ }
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Group5 Interrupts DMA and flags management functions
+ * @brief Interrupts, DMA and flags management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupts, DMA and flags management functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the specified TIM interrupts.
+ * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIMx peripheral.
+ * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_IT_Update: TIM update Interrupt source
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+ * @arg TIM_IT_COM: TIM Commutation Interrupt source
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+ * @arg TIM_IT_Break: TIM Break Interrupt source
+ *
+ * @note For TIM6 and TIM7 only the parameter TIM_IT_Update can be used
+ * @note For TIM9 and TIM12 only one of the following parameters can be used: TIM_IT_Update,
+ * TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger.
+ * @note For TIM10, TIM11, TIM13 and TIM14 only one of the following parameters can
+ * be used: TIM_IT_Update or TIM_IT_CC1
+ * @note TIM_IT_COM and TIM_IT_Break can be used only with TIM1 and TIM8
+ *
+ * @param NewState: new state of the TIM interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_IT(TIM_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the Interrupt sources */
+ TIMx->DIER |= TIM_IT;
+ }
+ else
+ {
+ /* Disable the Interrupt sources */
+ TIMx->DIER &= (uint16_t)~TIM_IT;
+ }
+}
+
+/**
+ * @brief Configures the TIMx event to be generate by software.
+ * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral.
+ * @param TIM_EventSource: specifies the event source.
+ * This parameter can be one or more of the following values:
+ * @arg TIM_EventSource_Update: Timer update Event source
+ * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
+ * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
+ * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
+ * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
+ * @arg TIM_EventSource_COM: Timer COM event source
+ * @arg TIM_EventSource_Trigger: Timer Trigger Event source
+ * @arg TIM_EventSource_Break: Timer Break event source
+ *
+ * @note TIM6 and TIM7 can only generate an update event.
+ * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
+ *
+ * @retval None
+ */
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
+
+ /* Set the event sources */
+ TIMx->EGR = TIM_EventSource;
+}
+
+/**
+ * @brief Checks whether the specified TIM flag is set or not.
+ * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral.
+ * @param TIM_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_FLAG_Update: TIM update Flag
+ * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
+ * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
+ * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
+ * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
+ * @arg TIM_FLAG_CC5: TIM Capture Compare 5 Flag
+ * @arg TIM_FLAG_CC6: TIM Capture Compare 6 Flag
+ * @arg TIM_FLAG_COM: TIM Commutation Flag
+ * @arg TIM_FLAG_Trigger: TIM Trigger Flag
+ * @arg TIM_FLAG_Break: TIM Break Flag
+ * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag
+ * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag
+ * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag
+ * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag
+ *
+ * @note TIM6 and TIM7 can have only one update flag.
+ * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
+ *
+ * @retval The new state of TIM_FLAG (SET or RESET).
+ */
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint32_t TIM_FLAG)
+{
+ ITStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
+
+
+ if ((TIMx->SR & TIM_FLAG) != RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the TIMx's pending flags.
+ * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral.
+ * @param TIM_FLAG: specifies the flag bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_FLAG_Update: TIM update Flag
+ * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
+ * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
+ * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
+ * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
+ * @arg TIM_FLAG_CC5: TIM Capture Compare 5 Flag
+ * @arg TIM_FLAG_CC6: TIM Capture Compare 6 Flag
+ * @arg TIM_FLAG_COM: TIM Commutation Flag
+ * @arg TIM_FLAG_Trigger: TIM Trigger Flag
+ * @arg TIM_FLAG_Break: TIM Break Flag
+ * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag
+ * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag
+ * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag
+ * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag
+ *
+ * @note TIM6 and TIM7 can have only one update flag.
+ * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
+ *
+ * @retval None
+ */
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+ /* Clear the flags */
+ TIMx->SR = (uint16_t)~TIM_FLAG;
+}
+
+/**
+ * @brief Checks whether the TIM interrupt has occurred or not.
+ * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral.
+ * @param TIM_IT: specifies the TIM interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_Update: TIM update Interrupt source
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+ * @arg TIM_IT_COM: TIM Commutation Interrupt source
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+ * @arg TIM_IT_Break: TIM Break Interrupt source
+ *
+ * @note TIM6 and TIM7 can generate only an update interrupt.
+ * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
+ *
+ * @retval The new state of the TIM_IT(SET or RESET).
+ */
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint16_t itstatus = 0x0, itenable = 0x0;
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_GET_IT(TIM_IT));
+
+ itstatus = TIMx->SR & TIM_IT;
+
+ itenable = TIMx->DIER & TIM_IT;
+ if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the TIMx's interrupt pending bits.
+ * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral.
+ * @param TIM_IT: specifies the pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_IT_Update: TIM1 update Interrupt source
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+ * @arg TIM_IT_COM: TIM Commutation Interrupt source
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+ * @arg TIM_IT_Break: TIM Break Interrupt source
+ *
+ * @note TIM6 and TIM7 can generate only an update interrupt.
+ * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
+ *
+ * @retval None
+ */
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+ /* Clear the IT pending Bit */
+ TIMx->SR = (uint16_t)~TIM_IT;
+}
+
+/**
+ * @brief Configures the TIMx's DMA interface.
+ * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
+ * @param TIM_DMABase: DMA Base address.
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABase_CR1
+ * @arg TIM_DMABase_CR2
+ * @arg TIM_DMABase_SMCR
+ * @arg TIM_DMABase_DIER
+ * @arg TIM1_DMABase_SR
+ * @arg TIM_DMABase_EGR
+ * @arg TIM_DMABase_CCMR1
+ * @arg TIM_DMABase_CCMR2
+ * @arg TIM_DMABase_CCER
+ * @arg TIM_DMABase_CNT
+ * @arg TIM_DMABase_PSC
+ * @arg TIM_DMABase_ARR
+ * @arg TIM_DMABase_RCR
+ * @arg TIM_DMABase_CCR1
+ * @arg TIM_DMABase_CCR2
+ * @arg TIM_DMABase_CCR3
+ * @arg TIM_DMABase_CCR4
+ * @arg TIM_DMABase_BDTR
+ * @arg TIM_DMABase_DCR
+ * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value
+ * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
+ * @retval None
+ */
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+ assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
+ assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
+
+ /* Set the DMA Base and the DMA Burst Length */
+ TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
+}
+
+/**
+ * @brief Enables or disables the TIMx's DMA Requests.
+ * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral.
+ * @param TIM_DMASource: specifies the DMA Request sources.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_DMA_Update: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_Trigger: TIM Trigger DMA source
+ * @param NewState: new state of the DMA Request sources.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the DMA sources */
+ TIMx->DIER |= TIM_DMASource;
+ }
+ else
+ {
+ /* Disable the DMA sources */
+ TIMx->DIER &= (uint16_t)~TIM_DMASource;
+ }
+}
+
+/**
+ * @brief Selects the TIMx peripheral Capture Compare DMA source.
+ * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
+ * @param NewState: new state of the Capture Compare DMA source
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Set the CCDS Bit */
+ TIMx->CR2 |= TIM_CR2_CCDS;
+ }
+ else
+ {
+ /* Reset the CCDS Bit */
+ TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS;
+ }
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Group6 Clocks management functions
+ * @brief Clocks management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Clocks management functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the TIMx internal Clock
+ * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
+ * peripheral.
+ * @retval None
+ */
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+
+ /* Disable slave mode to clock the prescaler directly with the internal clock */
+ TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS;
+}
+
+/**
+ * @brief Configures the TIMx Internal Trigger as External Clock
+ * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
+ * peripheral.
+ * @param TIM_InputTriggerSource: Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal Trigger 0
+ * @arg TIM_TS_ITR1: Internal Trigger 1
+ * @arg TIM_TS_ITR2: Internal Trigger 2
+ * @arg TIM_TS_ITR3: Internal Trigger 3
+ * @retval None
+ */
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+ assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
+
+ /* Select the Internal Trigger */
+ TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
+
+ /* Select the External clock mode1 */
+ TIMx->SMCR |= TIM_SlaveMode_External1;
+}
+
+/**
+ * @brief Configures the TIMx Trigger as External Clock
+ * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15
+ * to select the TIM peripheral.
+ * @param TIM_TIxExternalCLKSource: Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
+ * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
+ * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
+ * @param TIM_ICPolarity: specifies the TIx Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @param ICFilter: specifies the filter value.
+ * This parameter must be a value between 0x0 and 0xF.
+ * @retval None
+ */
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
+ uint16_t TIM_ICPolarity, uint16_t ICFilter)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+ assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
+ assert_param(IS_TIM_IC_FILTER(ICFilter));
+
+ /* Configure the Timer Input Clock Source */
+ if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
+ {
+ TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
+ }
+ else
+ {
+ TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
+ }
+ /* Select the Trigger source */
+ TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
+ /* Select the External clock mode1 */
+ TIMx->SMCR |= TIM_SlaveMode_External1;
+}
+
+/**
+ * @brief Configures the External clock Mode1
+ * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+ * @param ExtTRGFilter: External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ * @retval None
+ */
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
+{
+ uint16_t tmpsmcr = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+ /* Configure the ETR Clock source */
+ TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = TIMx->SMCR;
+
+ /* Reset the SMS Bits */
+ tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
+
+ /* Select the External clock mode1 */
+ tmpsmcr |= TIM_SlaveMode_External1;
+
+ /* Select the Trigger selection : ETRF */
+ tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
+ tmpsmcr |= TIM_TS_ETRF;
+
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+
+/**
+ * @brief Configures the External clock Mode2
+ * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+ * @param ExtTRGFilter: External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ * @retval None
+ */
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+
+ /* Configure the ETR Clock source */
+ TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+
+ /* Enable the External clock mode2 */
+ TIMx->SMCR |= TIM_SMCR_ECE;
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Group7 Synchronization management functions
+ * @brief Synchronization management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Synchronization management functions #####
+ ===============================================================================
+
+ *** TIM Driver: how to use it in synchronization Mode ***
+ =========================================================
+ [..] Case of two/several Timers
+
+ (#) Configure the Master Timers using the following functions:
+ (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
+ (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
+ (#) Configure the Slave Timers using the following functions:
+ (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+ (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
+
+ [..] Case of Timers and external trigger(ETR pin)
+
+ (#) Configure the External trigger using this function:
+ (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter);
+ (#) Configure the Slave Timers using the following functions:
+ (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+ (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Selects the Input Trigger source
+ * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15
+ * to select the TIM peripheral.
+ * @param TIM_InputTriggerSource: The Input Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal Trigger 0
+ * @arg TIM_TS_ITR1: Internal Trigger 1
+ * @arg TIM_TS_ITR2: Internal Trigger 2
+ * @arg TIM_TS_ITR3: Internal Trigger 3
+ * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+ * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+ * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+ * @arg TIM_TS_ETRF: External Trigger input
+ * @retval None
+ */
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
+{
+ uint16_t tmpsmcr = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+ assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = TIMx->SMCR;
+
+ /* Reset the TS Bits */
+ tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
+
+ /* Set the Input Trigger source */
+ tmpsmcr |= TIM_InputTriggerSource;
+
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+
+/**
+ * @brief Selects the TIMx Trigger Output Mode.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8 or 15 to select the TIM peripheral.
+ *
+ * @param TIM_TRGOSource: specifies the Trigger Output source.
+ * This parameter can be one of the following values:
+ *
+ * - For all TIMx
+ * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO)
+ * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO)
+ * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO)
+ *
+ * - For all TIMx except TIM6 and TIM7
+ * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
+ * is to be set, as soon as a capture or compare match occurs(TRGO)
+ * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO)
+ * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO)
+ * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO)
+ * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO)
+ *
+ * @retval None
+ */
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST7_PERIPH(TIMx));
+ assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
+
+ /* Reset the MMS Bits */
+ TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS;
+ /* Select the TRGO source */
+ TIMx->CR2 |= TIM_TRGOSource;
+}
+
+/**
+ * @brief Selects the TIMx Trigger Output Mode2 (TRGO2).
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
+ *
+ * @param TIM_TRGO2Source: specifies the Trigger Output source.
+ * This parameter can be one of the following values:
+ *
+ * - For all TIMx
+ * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO2)
+ * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO2)
+ * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO2)
+ * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
+ * is to be set, as soon as a capture or compare match occurs(TRGO2)
+ * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO2)
+ * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO2)
+ * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO2)
+ * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO2)
+ * @arg TIM_TRGO2Source_OC4Ref_RisingFalling: OC4Ref Rising and Falling are used as the trigger output(TRGO2)
+ * @arg TIM_TRGO2Source_OC6Ref_RisingFalling: OC6Ref Rising and Falling are used as the trigger output(TRGO2)
+ * @arg TIM_TRGO2Source_OC4RefRising_OC6RefRising: OC4Ref Rising and OC6Ref Rising are used as the trigger output(TRGO2)
+ * @arg TIM_TRGO2Source_OC4RefRising_OC6RefFalling: OC4Ref Rising and OC6Ref Falling are used as the trigger output(TRGO2)
+ * @arg TIM_TRGO2Source_OC5RefRising_OC6RefRising: OC5Ref Rising and OC6Ref Rising are used as the trigger output(TRGO2)
+ * @arg TIM_TRGO2Source_OC5RefRising_OC6RefFalling: OC5Ref Rising and OC6Ref Falling are used as the trigger output(TRGO2)
+ *
+ * @retval None
+ */
+void TIM_SelectOutputTrigger2(TIM_TypeDef* TIMx, uint32_t TIM_TRGO2Source)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+ assert_param(IS_TIM_TRGO2_SOURCE(TIM_TRGO2Source));
+
+ /* Reset the MMS Bits */
+ TIMx->CR2 &= (uint32_t)~TIM_CR2_MMS2;
+ /* Select the TRGO source */
+ TIMx->CR2 |= TIM_TRGO2Source;
+}
+
+/**
+ * @brief Selects the TIMx Slave Mode.
+ * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM peripheral.
+ * @param TIM_SlaveMode: specifies the Timer Slave Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal(TRGI) reinitialize
+ * the counter and triggers an update of the registers
+ * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high
+ * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI
+ * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter
+ * @arg TIM_SlaveMode_Combined_ResetTrigger: Rising edge of the selected trigger input (TRGI)
+ * reinitializes the counter, generates an update
+ * of the registers and starts the counter.
+ * @retval None
+ */
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint32_t TIM_SlaveMode)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+ assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
+
+ /* Reset the SMS Bits */
+ TIMx->SMCR &= (uint32_t)~TIM_SMCR_SMS;
+
+ /* Select the Slave Mode */
+ TIMx->SMCR |= (uint32_t)TIM_SlaveMode;
+}
+
+/**
+ * @brief Sets or Resets the TIMx Master/Slave Mode.
+ * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM peripheral.
+ * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
+ * and its slaves (through TRGO)
+ * @arg TIM_MasterSlaveMode_Disable: No action
+ * @retval None
+ */
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+ assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
+
+ /* Reset the MSM Bit */
+ TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM;
+
+ /* Set or Reset the MSM Bit */
+ TIMx->SMCR |= TIM_MasterSlaveMode;
+}
+
+/**
+ * @brief Configures the TIMx External Trigger (ETR).
+ * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+ * @param ExtTRGFilter: External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ * @retval None
+ */
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
+{
+ uint16_t tmpsmcr = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+
+ tmpsmcr = TIMx->SMCR;
+
+ /* Reset the ETR Bits */
+ tmpsmcr &= SMCR_ETR_MASK;
+
+ /* Set the Prescaler, the Filter value and the Polarity */
+ tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
+
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Group8 Specific interface management functions
+ * @brief Specific interface management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Specific interface management functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the TIMx Encoder Interface.
+ * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM
+ * peripheral.
+ * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
+ * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
+ * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
+ * on the level of the other input.
+ * @param TIM_IC1Polarity: specifies the IC1 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Falling: IC Falling edge.
+ * @arg TIM_ICPolarity_Rising: IC Rising edge.
+ * @param TIM_IC2Polarity: specifies the IC2 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Falling: IC Falling edge.
+ * @arg TIM_ICPolarity_Rising: IC Rising edge.
+ * @retval None
+ */
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
+ uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
+{
+ uint16_t tmpsmcr = 0;
+ uint16_t tmpccmr1 = 0;
+ uint16_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
+ assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
+ assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = TIMx->SMCR;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
+ /* Set the encoder Mode */
+ tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
+ tmpsmcr |= TIM_EncoderMode;
+
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+ tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S);
+ tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
+
+ /* Set the TI1 and the TI2 Polarities */
+ tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P);
+ tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
+
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmr1;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Enables or disables the TIMx's Hall sensor interface.
+ * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
+ * peripheral.
+ * @param NewState: new state of the TIMx Hall sensor interface.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Set the TI1S Bit */
+ TIMx->CR2 |= TIM_CR2_TI1S;
+ }
+ else
+ {
+ /* Reset the TI1S Bit */
+ TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S;
+ }
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Group9 Specific remapping management function
+ * @brief Specific remapping management function
+ *
+@verbatim
+ ===============================================================================
+ ##### Specific remapping management function #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the TIM16 Remapping input Capabilities.
+ * @param TIMx: where x can be 1, 8 or 16 to select the TIM peripheral.
+ * @param TIM_Remap: specifies the TIM input reampping source.
+ * This parameter can be one of the following values:
+ * @arg TIM16_GPIO: TIM16 Channel 1 is connected to GPIO.
+ * @arg TIM16_RTC_CLK: TIM16 Channel 1 is connected to RTC input clock.
+ * @arg TIM16_HSE_DIV32: TIM16 Channel 1 is connected to HSE/32 clock.
+ * @arg TIM16_MCO: TIM16 Channel 1 is connected to MCO clock.
+ * @arg TIM1_ADC1_AWDG1: TIM1 ETR is connected to ADC1 AWDG1.
+ * @arg TIM1_ADC1_AWDG2: TIM1 ETR is connected to ADC1 AWDG2.
+ * @arg TIM1_ADC1_AWDG3: TIM1 ETR is connected to ADC1 AWDG3.
+ * @arg TIM1_ADC4_AWDG1: TIM1 ETR is connected to ADC4 AWDG1.
+ * @arg TIM1_ADC4_AWDG2: TIM1 ETR is connected to ADC4 AWDG2.
+ * @arg TIM1_ADC4_AWDG3: TIM1 ETR is connected to ADC4 AWDG3.
+ * @arg TIM8_ADC2_AWDG1: TIM8 ETR is connected to ADC2 AWDG1.
+ * @arg TIM8_ADC2_AWDG2: TIM8 ETR is connected to ADC2 AWDG2.
+ * @arg TIM8_ADC2_AWDG3: TIM8 ETR is connected to ADC2 AWDG3.
+ * @arg TIM8_ADC4_AWDG1: TIM8 ETR is connected to ADC4 AWDG1.
+ * @arg TIM8_ADC4_AWDG2: TIM8 ETR is connected to ADC4 AWDG2.
+ * @arg TIM8_ADC4_AWDG3: TIM8 ETR is connected to ADC4 AWDG3.
+ * @retval : None
+ */
+void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+ assert_param(IS_TIM_REMAP(TIM_Remap));
+
+ /* Set the Timer remapping configuration */
+ TIMx->OR = TIM_Remap;
+}
+/**
+ * @}
+ */
+
+/**
+ * @brief Configure the TI1 as Input.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14
+ * to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @arg TIM_ICPolarity_BothEdge
+ * @param TIM_ICSelection: specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
+ * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1 = 0, tmpccer = 0;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input and set the filter */
+ tmpccmr1 &= ((uint32_t)~TIM_CCMR1_CC1S) & ((uint32_t)~TIM_CCMR1_IC1F);
+ tmpccmr1 |= (uint32_t)(TIM_ICSelection | (uint32_t)((uint32_t)TIM_ICFilter << 4));
+
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+ tmpccer |= (uint32_t)(TIM_ICPolarity | (uint32_t)TIM_CCER_CC1E);
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI2 as Input.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
+ * peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @arg TIM_ICPolarity_BothEdge
+ * @param TIM_ICSelection: specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
+ * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+ tmp = (uint16_t)(TIM_ICPolarity << 4);
+
+ /* Select the Input and set the filter */
+ tmpccmr1 &= ((uint32_t)~TIM_CCMR1_CC2S) & ((uint32_t)~TIM_CCMR1_IC2F);
+ tmpccmr1 |= (uint32_t)((uint32_t)TIM_ICFilter << 12);
+ tmpccmr1 |= (uint32_t)((uint32_t)TIM_ICSelection << 8);
+
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1 ;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI3 as Input.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @arg TIM_ICPolarity_BothEdge
+ * @param TIM_ICSelection: specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
+ * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter)
+{
+ uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E;
+ tmpccmr2 = TIMx->CCMR2;
+ tmpccer = TIMx->CCER;
+ tmp = (uint16_t)(TIM_ICPolarity << 8);
+
+ /* Select the Input and set the filter */
+ tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F);
+ tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
+
+ /* Select the Polarity and set the CC3E Bit */
+ tmpccer &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
+ tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
+
+ /* Write to TIMx CCMR2 and CCER registers */
+ TIMx->CCMR2 = tmpccmr2;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI4 as Input.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @arg TIM_ICPolarity_BothEdge
+ * @param TIM_ICSelection: specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
+ * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter)
+{
+ uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E;
+ tmpccmr2 = TIMx->CCMR2;
+ tmpccer = TIMx->CCER;
+ tmp = (uint16_t)(TIM_ICPolarity << 12);
+
+ /* Select the Input and set the filter */
+ tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F);
+ tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
+ tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
+
+ /* Select the Polarity and set the CC4E Bit */
+ tmpccer &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
+ tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
+
+ /* Write to TIMx CCMR2 and CCER registers */
+ TIMx->CCMR2 = tmpccmr2;
+ TIMx->CCER = tmpccer ;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_tim.h Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,1344 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_tim.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the TIM firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_TIM_H
+#define __STM32F30x_TIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup stm32f30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup TIM
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief TIM Time Base Init structure definition
+ * @note This structure is used with all TIMx except for TIM6 and TIM7.
+ */
+
+typedef struct
+{
+ uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
+ This parameter can be a number between 0x0000 and 0xFFFF */
+
+ uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
+ This parameter can be a value of @ref TIM_Counter_Mode */
+
+ uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active
+ Auto-Reload Register at the next update event.
+ This parameter must be a number between 0x0000 and 0xFFFF. */
+
+ uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
+ This parameter can be a value of @ref TIM_Clock_Division_CKD */
+
+ uint16_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
+ reaches zero, an update event is generated and counting restarts
+ from the RCR value (N).
+ This means in PWM mode that (N+1) corresponds to:
+ - the number of PWM periods in edge-aligned mode
+ - the number of half PWM period in center-aligned mode
+ This parameter must be a number between 0x00 and 0xFF.
+ @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_TimeBaseInitTypeDef;
+
+/**
+ * @brief TIM Output Compare Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t TIM_OCMode; /*!< Specifies the TIM mode.
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+ uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
+ This parameter can be a value of @ref TIM_Output_Compare_State */
+
+ uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between 0x0000 and 0xFFFF */
+
+ uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+ uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_OCInitTypeDef;
+
+/**
+ * @brief TIM Input Capture Init structure definition
+ */
+
+typedef struct
+{
+
+ uint16_t TIM_Channel; /*!< Specifies the TIM channel.
+ This parameter can be a value of @ref TIM_Channel */
+
+ uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint16_t TIM_ICSelection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between 0x0 and 0xF */
+} TIM_ICInitTypeDef;
+
+/**
+ * @brief BDTR structure definition
+ * @note This structure is used only with TIM1 and TIM8.
+ */
+
+typedef struct
+{
+
+ uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.
+ This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+
+ uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.
+ This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+
+ uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.
+ This parameter can be a value of @ref TIM_Lock_level */
+
+ uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the
+ switching-on of the outputs.
+ This parameter can be a number between 0x00 and 0xFF */
+
+ uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not.
+ This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+
+ uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
+ This parameter can be a value of @ref TIM_Break_Polarity */
+
+ uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
+ This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+} TIM_BDTRInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup TIM_Exported_constants
+ * @{
+ */
+
+#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM6) || \
+ ((PERIPH) == TIM7) || \
+ ((PERIPH) == TIM8) || \
+ ((PERIPH) == TIM15) || \
+ ((PERIPH) == TIM16) || \
+ ((PERIPH) == TIM17))
+/* LIST1: TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16 and TIM17 */
+#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM8) || \
+ ((PERIPH) == TIM15) || \
+ ((PERIPH) == TIM16) || \
+ ((PERIPH) == TIM17))
+
+/* LIST2: TIM1, TIM2, TIM3, TIM4, TIM8 and TIM15 */
+#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM8) || \
+ ((PERIPH) == TIM15))
+/* LIST3: TIM1, TIM2, TIM3, TIM4 and TIM8 */
+#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM8))
+/* LIST4: TIM1 and TIM8 */
+#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) ||\
+ ((PERIPH) == TIM8))
+/* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */
+#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM6) || \
+ ((PERIPH) == TIM7) || \
+ ((PERIPH) == TIM8))
+/* LIST6: TIM1, TIM8, TIM15, TIM16 and TIM17 */
+#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM8) || \
+ ((PERIPH) == TIM15) || \
+ ((PERIPH) == TIM16) || \
+ ((PERIPH) == TIM17))
+
+/* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */
+#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM6) || \
+ ((PERIPH) == TIM7) || \
+ ((PERIPH) == TIM8) || \
+ ((PERIPH) == TIM15))
+/* LIST8: TIM16 (option register) */
+#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM16)|| \
+ ((PERIPH) == TIM1)||\
+ ((PERIPH) == TIM8))
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes
+ * @{
+ */
+
+#define TIM_OCMode_Timing ((uint32_t)0x00000)
+#define TIM_OCMode_Active ((uint32_t)0x00010)
+#define TIM_OCMode_Inactive ((uint32_t)0x00020)
+#define TIM_OCMode_Toggle ((uint32_t)0x00030)
+#define TIM_OCMode_PWM1 ((uint32_t)0x00060)
+#define TIM_OCMode_PWM2 ((uint32_t)0x00070)
+
+#define TIM_OCMode_Retrigerrable_OPM1 ((uint32_t)0x10000)
+#define TIM_OCMode_Retrigerrable_OPM2 ((uint32_t)0x10010)
+#define TIM_OCMode_Combined_PWM1 ((uint32_t)0x10040)
+#define TIM_OCMode_Combined_PWM2 ((uint32_t)0x10050)
+#define TIM_OCMode_Asymmetric_PWM1 ((uint32_t)0x10060)
+#define TIM_OCMode_Asymmetric_PWM2 ((uint32_t)0x10070)
+
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
+ ((MODE) == TIM_OCMode_Active) || \
+ ((MODE) == TIM_OCMode_Inactive) || \
+ ((MODE) == TIM_OCMode_Toggle)|| \
+ ((MODE) == TIM_OCMode_PWM1) || \
+ ((MODE) == TIM_OCMode_PWM2) || \
+ ((MODE) == TIM_OCMode_Retrigerrable_OPM1) || \
+ ((MODE) == TIM_OCMode_Retrigerrable_OPM2) || \
+ ((MODE) == TIM_OCMode_Combined_PWM1) || \
+ ((MODE) == TIM_OCMode_Combined_PWM2) || \
+ ((MODE) == TIM_OCMode_Asymmetric_PWM1) || \
+ ((MODE) == TIM_OCMode_Asymmetric_PWM2))
+
+#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
+ ((MODE) == TIM_OCMode_Active) || \
+ ((MODE) == TIM_OCMode_Inactive) || \
+ ((MODE) == TIM_OCMode_Toggle)|| \
+ ((MODE) == TIM_OCMode_PWM1) || \
+ ((MODE) == TIM_OCMode_PWM2) || \
+ ((MODE) == TIM_ForcedAction_Active) || \
+ ((MODE) == TIM_ForcedAction_InActive) || \
+ ((MODE) == TIM_OCMode_Retrigerrable_OPM1) || \
+ ((MODE) == TIM_OCMode_Retrigerrable_OPM2) || \
+ ((MODE) == TIM_OCMode_Combined_PWM1) || \
+ ((MODE) == TIM_OCMode_Combined_PWM2) || \
+ ((MODE) == TIM_OCMode_Asymmetric_PWM1) || \
+ ((MODE) == TIM_OCMode_Asymmetric_PWM2))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_One_Pulse_Mode
+ * @{
+ */
+
+#define TIM_OPMode_Single ((uint16_t)0x0008)
+#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
+ ((MODE) == TIM_OPMode_Repetitive))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Channel
+ * @{
+ */
+
+#define TIM_Channel_1 ((uint16_t)0x0000)
+#define TIM_Channel_2 ((uint16_t)0x0004)
+#define TIM_Channel_3 ((uint16_t)0x0008)
+#define TIM_Channel_4 ((uint16_t)0x000C)
+#define TIM_Channel_5 ((uint16_t)0x0010)
+#define TIM_Channel_6 ((uint16_t)0x0014)
+
+#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+ ((CHANNEL) == TIM_Channel_2) || \
+ ((CHANNEL) == TIM_Channel_3) || \
+ ((CHANNEL) == TIM_Channel_4))
+
+#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+ ((CHANNEL) == TIM_Channel_2))
+#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+ ((CHANNEL) == TIM_Channel_2) || \
+ ((CHANNEL) == TIM_Channel_3))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Division_CKD
+ * @{
+ */
+
+#define TIM_CKD_DIV1 ((uint16_t)0x0000)
+#define TIM_CKD_DIV2 ((uint16_t)0x0100)
+#define TIM_CKD_DIV4 ((uint16_t)0x0200)
+#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
+ ((DIV) == TIM_CKD_DIV2) || \
+ ((DIV) == TIM_CKD_DIV4))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Counter_Mode
+ * @{
+ */
+
+#define TIM_CounterMode_Up ((uint16_t)0x0000)
+#define TIM_CounterMode_Down ((uint16_t)0x0010)
+#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
+#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
+#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
+ ((MODE) == TIM_CounterMode_Down) || \
+ ((MODE) == TIM_CounterMode_CenterAligned1) || \
+ ((MODE) == TIM_CounterMode_CenterAligned2) || \
+ ((MODE) == TIM_CounterMode_CenterAligned3))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Polarity
+ * @{
+ */
+
+#define TIM_OCPolarity_High ((uint16_t)0x0000)
+#define TIM_OCPolarity_Low ((uint16_t)0x0002)
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
+ ((POLARITY) == TIM_OCPolarity_Low))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_Polarity
+ * @{
+ */
+
+#define TIM_OCNPolarity_High ((uint16_t)0x0000)
+#define TIM_OCNPolarity_Low ((uint16_t)0x0008)
+#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
+ ((POLARITY) == TIM_OCNPolarity_Low))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_State
+ * @{
+ */
+
+#define TIM_OutputState_Disable ((uint16_t)0x0000)
+#define TIM_OutputState_Enable ((uint16_t)0x0001)
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
+ ((STATE) == TIM_OutputState_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_State
+ * @{
+ */
+
+#define TIM_OutputNState_Disable ((uint16_t)0x0000)
+#define TIM_OutputNState_Enable ((uint16_t)0x0004)
+#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
+ ((STATE) == TIM_OutputNState_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Capture_Compare_State
+ * @{
+ */
+
+#define TIM_CCx_Enable ((uint16_t)0x0001)
+#define TIM_CCx_Disable ((uint16_t)0x0000)
+#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
+ ((CCX) == TIM_CCx_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Capture_Compare_N_State
+ * @{
+ */
+
+#define TIM_CCxN_Enable ((uint16_t)0x0004)
+#define TIM_CCxN_Disable ((uint16_t)0x0000)
+#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
+ ((CCXN) == TIM_CCxN_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break_Input_enable_disable
+ * @{
+ */
+
+#define TIM_Break_Enable ((uint16_t)0x1000)
+#define TIM_Break_Disable ((uint16_t)0x0000)
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
+ ((STATE) == TIM_Break_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break1_Input_enable_disable
+ * @{
+ */
+
+#define TIM_Break1_Enable ((uint32_t)0x00001000)
+#define TIM_Break1_Disable ((uint32_t)0x00000000)
+#define IS_TIM_BREAK1_STATE(STATE) (((STATE) == TIM_Break1_Enable) || \
+ ((STATE) == TIM_Break1_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break2_Input_enable_disable
+ * @{
+ */
+
+#define TIM_Break2_Enable ((uint32_t)0x01000000)
+#define TIM_Break2_Disable ((uint32_t)0x00000000)
+#define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_Break2_Enable) || \
+ ((STATE) == TIM_Break2_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break_Polarity
+ * @{
+ */
+
+#define TIM_BreakPolarity_Low ((uint16_t)0x0000)
+#define TIM_BreakPolarity_High ((uint16_t)0x2000)
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
+ ((POLARITY) == TIM_BreakPolarity_High))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break1_Polarity
+ * @{
+ */
+
+#define TIM_Break1Polarity_Low ((uint32_t)0x00000000)
+#define TIM_Break1Polarity_High ((uint32_t)0x00002000)
+#define IS_TIM_BREAK1_POLARITY(POLARITY) (((POLARITY) == TIM_Break1Polarity_Low) || \
+ ((POLARITY) == TIM_Break1Polarity_High))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break2_Polarity
+ * @{
+ */
+
+#define TIM_Break2Polarity_Low ((uint32_t)0x00000000)
+#define TIM_Break2Polarity_High ((uint32_t)0x02000000)
+#define IS_TIM_BREAK2_POLARITY(POLARITY) (((POLARITY) == TIM_Break2Polarity_Low) || \
+ ((POLARITY) == TIM_Break2Polarity_High))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break1_Filter
+ * @{
+ */
+
+#define IS_TIM_BREAK1_FILTER(FILTER) ((FILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break2_Filter
+ * @{
+ */
+
+#define IS_TIM_BREAK2_FILTER(FILTER) ((FILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_AOE_Bit_Set_Reset
+ * @{
+ */
+
+#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
+#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
+ ((STATE) == TIM_AutomaticOutput_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Lock_level
+ * @{
+ */
+
+#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
+#define TIM_LOCKLevel_1 ((uint16_t)0x0100)
+#define TIM_LOCKLevel_2 ((uint16_t)0x0200)
+#define TIM_LOCKLevel_3 ((uint16_t)0x0300)
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
+ ((LEVEL) == TIM_LOCKLevel_1) || \
+ ((LEVEL) == TIM_LOCKLevel_2) || \
+ ((LEVEL) == TIM_LOCKLevel_3))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state
+ * @{
+ */
+
+#define TIM_OSSIState_Enable ((uint16_t)0x0400)
+#define TIM_OSSIState_Disable ((uint16_t)0x0000)
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
+ ((STATE) == TIM_OSSIState_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
+ * @{
+ */
+
+#define TIM_OSSRState_Enable ((uint16_t)0x0800)
+#define TIM_OSSRState_Disable ((uint16_t)0x0000)
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
+ ((STATE) == TIM_OSSRState_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Idle_State
+ * @{
+ */
+
+#define TIM_OCIdleState_Set ((uint16_t)0x0100)
+#define TIM_OCIdleState_Reset ((uint16_t)0x0000)
+#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
+ ((STATE) == TIM_OCIdleState_Reset))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_Idle_State
+ * @{
+ */
+
+#define TIM_OCNIdleState_Set ((uint16_t)0x0200)
+#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
+#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
+ ((STATE) == TIM_OCNIdleState_Reset))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Polarity
+ * @{
+ */
+
+#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
+#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
+#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
+ ((POLARITY) == TIM_ICPolarity_Falling)|| \
+ ((POLARITY) == TIM_ICPolarity_BothEdge))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Selection
+ * @{
+ */
+
+#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC2, IC1, IC4 or IC3, respectively. */
+#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
+ ((SELECTION) == TIM_ICSelection_IndirectTI) || \
+ ((SELECTION) == TIM_ICSelection_TRC))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Prescaler
+ * @{
+ */
+
+#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
+#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
+#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
+#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
+ ((PRESCALER) == TIM_ICPSC_DIV2) || \
+ ((PRESCALER) == TIM_ICPSC_DIV4) || \
+ ((PRESCALER) == TIM_ICPSC_DIV8))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_interrupt_sources
+ * @{
+ */
+
+#define TIM_IT_Update ((uint16_t)0x0001)
+#define TIM_IT_CC1 ((uint16_t)0x0002)
+#define TIM_IT_CC2 ((uint16_t)0x0004)
+#define TIM_IT_CC3 ((uint16_t)0x0008)
+#define TIM_IT_CC4 ((uint16_t)0x0010)
+#define TIM_IT_COM ((uint16_t)0x0020)
+#define TIM_IT_Trigger ((uint16_t)0x0040)
+#define TIM_IT_Break ((uint16_t)0x0080)
+#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
+
+#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
+ ((IT) == TIM_IT_CC1) || \
+ ((IT) == TIM_IT_CC2) || \
+ ((IT) == TIM_IT_CC3) || \
+ ((IT) == TIM_IT_CC4) || \
+ ((IT) == TIM_IT_COM) || \
+ ((IT) == TIM_IT_Trigger) || \
+ ((IT) == TIM_IT_Break))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Base_address
+ * @{
+ */
+
+#define TIM_DMABase_CR1 ((uint16_t)0x0000)
+#define TIM_DMABase_CR2 ((uint16_t)0x0001)
+#define TIM_DMABase_SMCR ((uint16_t)0x0002)
+#define TIM_DMABase_DIER ((uint16_t)0x0003)
+#define TIM_DMABase_SR ((uint16_t)0x0004)
+#define TIM_DMABase_EGR ((uint16_t)0x0005)
+#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
+#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
+#define TIM_DMABase_CCER ((uint16_t)0x0008)
+#define TIM_DMABase_CNT ((uint16_t)0x0009)
+#define TIM_DMABase_PSC ((uint16_t)0x000A)
+#define TIM_DMABase_ARR ((uint16_t)0x000B)
+#define TIM_DMABase_RCR ((uint16_t)0x000C)
+#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
+#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
+#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
+#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
+#define TIM_DMABase_BDTR ((uint16_t)0x0011)
+#define TIM_DMABase_DCR ((uint16_t)0x0012)
+#define TIM_DMABase_OR ((uint16_t)0x0013)
+#define TIM_DMABase_CCMR3 ((uint16_t)0x0014)
+#define TIM_DMABase_CCR5 ((uint16_t)0x0015)
+#define TIM_DMABase_CCR6 ((uint16_t)0x0016)
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
+ ((BASE) == TIM_DMABase_CR2) || \
+ ((BASE) == TIM_DMABase_SMCR) || \
+ ((BASE) == TIM_DMABase_DIER) || \
+ ((BASE) == TIM_DMABase_SR) || \
+ ((BASE) == TIM_DMABase_EGR) || \
+ ((BASE) == TIM_DMABase_CCMR1) || \
+ ((BASE) == TIM_DMABase_CCMR2) || \
+ ((BASE) == TIM_DMABase_CCER) || \
+ ((BASE) == TIM_DMABase_CNT) || \
+ ((BASE) == TIM_DMABase_PSC) || \
+ ((BASE) == TIM_DMABase_ARR) || \
+ ((BASE) == TIM_DMABase_RCR) || \
+ ((BASE) == TIM_DMABase_CCR1) || \
+ ((BASE) == TIM_DMABase_CCR2) || \
+ ((BASE) == TIM_DMABase_CCR3) || \
+ ((BASE) == TIM_DMABase_CCR4) || \
+ ((BASE) == TIM_DMABase_BDTR) || \
+ ((BASE) == TIM_DMABase_DCR) || \
+ ((BASE) == TIM_DMABase_OR) || \
+ ((BASE) == TIM_DMABase_CCMR3) || \
+ ((BASE) == TIM_DMABase_CCR5) || \
+ ((BASE) == TIM_DMABase_CCR6))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Burst_Length
+ * @{
+ */
+
+#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
+#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
+#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
+#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
+#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
+#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
+#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
+#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
+#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
+#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
+#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
+#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
+#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
+#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
+#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
+#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
+#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
+#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
+ ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_18Transfers))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_sources
+ * @{
+ */
+
+#define TIM_DMA_Update ((uint16_t)0x0100)
+#define TIM_DMA_CC1 ((uint16_t)0x0200)
+#define TIM_DMA_CC2 ((uint16_t)0x0400)
+#define TIM_DMA_CC3 ((uint16_t)0x0800)
+#define TIM_DMA_CC4 ((uint16_t)0x1000)
+#define TIM_DMA_COM ((uint16_t)0x2000)
+#define TIM_DMA_Trigger ((uint16_t)0x4000)
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_External_Trigger_Prescaler
+ * @{
+ */
+
+#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
+#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
+#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
+#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
+#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Internal_Trigger_Selection
+ * @{
+ */
+
+#define TIM_TS_ITR0 ((uint16_t)0x0000)
+#define TIM_TS_ITR1 ((uint16_t)0x0010)
+#define TIM_TS_ITR2 ((uint16_t)0x0020)
+#define TIM_TS_ITR3 ((uint16_t)0x0030)
+#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
+#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
+#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
+#define TIM_TS_ETRF ((uint16_t)0x0070)
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3) || \
+ ((SELECTION) == TIM_TS_TI1F_ED) || \
+ ((SELECTION) == TIM_TS_TI1FP1) || \
+ ((SELECTION) == TIM_TS_TI2FP2) || \
+ ((SELECTION) == TIM_TS_ETRF))
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_TIx_External_Clock_Source
+ * @{
+ */
+
+#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
+#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
+#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_External_Trigger_Polarity
+ * @{
+ */
+#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
+#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
+#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
+ ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Prescaler_Reload_Mode
+ * @{
+ */
+
+#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
+#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
+#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
+ ((RELOAD) == TIM_PSCReloadMode_Immediate))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Forced_Action
+ * @{
+ */
+
+#define TIM_ForcedAction_Active ((uint16_t)0x0050)
+#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
+#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
+ ((ACTION) == TIM_ForcedAction_InActive))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Encoder_Mode
+ * @{
+ */
+
+#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
+#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
+#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
+ ((MODE) == TIM_EncoderMode_TI2) || \
+ ((MODE) == TIM_EncoderMode_TI12))
+/**
+ * @}
+ */
+
+
+/** @defgroup TIM_Event_Source
+ * @{
+ */
+
+#define TIM_EventSource_Update ((uint16_t)0x0001)
+#define TIM_EventSource_CC1 ((uint16_t)0x0002)
+#define TIM_EventSource_CC2 ((uint16_t)0x0004)
+#define TIM_EventSource_CC3 ((uint16_t)0x0008)
+#define TIM_EventSource_CC4 ((uint16_t)0x0010)
+#define TIM_EventSource_COM ((uint16_t)0x0020)
+#define TIM_EventSource_Trigger ((uint16_t)0x0040)
+#define TIM_EventSource_Break ((uint16_t)0x0080)
+#define TIM_EventSource_Break2 ((uint16_t)0x0100)
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFE00) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Update_Source
+ * @{
+ */
+
+#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
+ or the setting of UG bit, or an update generation
+ through the slave mode controller. */
+#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
+#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
+ ((SOURCE) == TIM_UpdateSource_Regular))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Preload_State
+ * @{
+ */
+
+#define TIM_OCPreload_Enable ((uint16_t)0x0008)
+#define TIM_OCPreload_Disable ((uint16_t)0x0000)
+#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
+ ((STATE) == TIM_OCPreload_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Fast_State
+ * @{
+ */
+
+#define TIM_OCFast_Enable ((uint16_t)0x0004)
+#define TIM_OCFast_Disable ((uint16_t)0x0000)
+#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
+ ((STATE) == TIM_OCFast_Disable))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Clear_State
+ * @{
+ */
+
+#define TIM_OCClear_Enable ((uint16_t)0x0080)
+#define TIM_OCClear_Disable ((uint16_t)0x0000)
+#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
+ ((STATE) == TIM_OCClear_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Output_Source
+ * @{
+ */
+
+#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
+#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
+#define TIM_TRGOSource_Update ((uint16_t)0x0020)
+#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
+#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
+#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
+#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
+#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
+ ((SOURCE) == TIM_TRGOSource_Enable) || \
+ ((SOURCE) == TIM_TRGOSource_Update) || \
+ ((SOURCE) == TIM_TRGOSource_OC1) || \
+ ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
+ ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
+ ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
+ ((SOURCE) == TIM_TRGOSource_OC4Ref))
+
+
+#define TIM_TRGO2Source_Reset ((uint32_t)0x00000000)
+#define TIM_TRGO2Source_Enable ((uint32_t)0x00100000)
+#define TIM_TRGO2Source_Update ((uint32_t)0x00200000)
+#define TIM_TRGO2Source_OC1 ((uint32_t)0x00300000)
+#define TIM_TRGO2Source_OC1Ref ((uint32_t)0x00400000)
+#define TIM_TRGO2Source_OC2Ref ((uint32_t)0x00500000)
+#define TIM_TRGO2Source_OC3Ref ((uint32_t)0x00600000)
+#define TIM_TRGO2Source_OC4Ref ((uint32_t)0x00700000)
+#define TIM_TRGO2Source_OC5Ref ((uint32_t)0x00800000)
+#define TIM_TRGO2Source_OC6Ref ((uint32_t)0x00900000)
+#define TIM_TRGO2Source_OC4Ref_RisingFalling ((uint32_t)0x00A00000)
+#define TIM_TRGO2Source_OC6Ref_RisingFalling ((uint32_t)0x00B00000)
+#define TIM_TRGO2Source_OC4RefRising_OC6RefRising ((uint32_t)0x00C00000)
+#define TIM_TRGO2Source_OC4RefRising_OC6RefFalling ((uint32_t)0x00D00000)
+#define TIM_TRGO2Source_OC5RefRising_OC6RefRising ((uint32_t)0x00E00000)
+#define TIM_TRGO2Source_OC5RefRising_OC6RefFalling ((uint32_t)0x00F00000)
+#define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2Source_Reset) || \
+ ((SOURCE) == TIM_TRGO2Source_Enable) || \
+ ((SOURCE) == TIM_TRGO2Source_Update) || \
+ ((SOURCE) == TIM_TRGO2Source_OC1) || \
+ ((SOURCE) == TIM_TRGO2Source_OC1Ref) || \
+ ((SOURCE) == TIM_TRGO2Source_OC2Ref) || \
+ ((SOURCE) == TIM_TRGO2Source_OC3Ref) || \
+ ((SOURCE) == TIM_TRGO2Source_OC4Ref) || \
+ ((SOURCE) == TIM_TRGO2Source_OC5Ref) || \
+ ((SOURCE) == TIM_TRGO2Source_OC6Ref) || \
+ ((SOURCE) == TIM_TRGO2Source_OC4Ref_RisingFalling) || \
+ ((SOURCE) == TIM_TRGO2Source_OC6Ref_RisingFalling) || \
+ ((SOURCE) == TIM_TRGO2Source_OC4RefRising_OC6RefRising) || \
+ ((SOURCE) == TIM_TRGO2Source_OC4RefRising_OC6RefFalling) || \
+ ((SOURCE) == TIM_TRGO2Source_OC5RefRising_OC6RefRising) || \
+ ((SOURCE) == TIM_TRGO2Source_OC5RefRising_OC6RefFalling))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Slave_Mode
+ * @{
+ */
+
+#define TIM_SlaveMode_Reset ((uint32_t)0x00004)
+#define TIM_SlaveMode_Gated ((uint32_t)0x00005)
+#define TIM_SlaveMode_Trigger ((uint32_t)0x00006)
+#define TIM_SlaveMode_External1 ((uint32_t)0x00007)
+#define TIM_SlaveMode_Combined_ResetTrigger ((uint32_t)0x10000)
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
+ ((MODE) == TIM_SlaveMode_Gated) || \
+ ((MODE) == TIM_SlaveMode_Trigger) || \
+ ((MODE) == TIM_SlaveMode_External1) || \
+ ((MODE) == TIM_SlaveMode_Combined_ResetTrigger))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Master_Slave_Mode
+ * @{
+ */
+
+#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
+#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
+ ((STATE) == TIM_MasterSlaveMode_Disable))
+/**
+ * @}
+ */
+/** @defgroup TIM_Remap
+ * @{
+ */
+#define TIM16_GPIO ((uint16_t)0x0000)
+#define TIM16_RTC_CLK ((uint16_t)0x0001)
+#define TIM16_HSEDiv32 ((uint16_t)0x0002)
+#define TIM16_MCO ((uint16_t)0x0003)
+
+#define TIM1_ADC1_AWDG1 ((uint16_t)0x0001)
+#define TIM1_ADC1_AWDG2 ((uint16_t)0x0002)
+#define TIM1_ADC1_AWDG3 ((uint16_t)0x0003)
+#define TIM1_ADC4_AWDG1 ((uint16_t)0x0004)
+#define TIM1_ADC4_AWDG2 ((uint16_t)0x0008)
+#define TIM1_ADC4_AWDG3 ((uint16_t)0x000C)
+
+#define TIM8_ADC2_AWDG1 ((uint16_t)0x0001)
+#define TIM8_ADC2_AWDG2 ((uint16_t)0x0002)
+#define TIM8_ADC2_AWDG3 ((uint16_t)0x0003)
+#define TIM8_ADC3_AWDG1 ((uint16_t)0x0004)
+#define TIM8_ADC3_AWDG2 ((uint16_t)0x0008)
+#define TIM8_ADC3_AWDG3 ((uint16_t)0x000C)
+
+#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM16_GPIO)|| \
+ ((TIM_REMAP) == TIM16_RTC_CLK) || \
+ ((TIM_REMAP) == TIM16_HSEDiv32) || \
+ ((TIM_REMAP) == TIM16_MCO) ||\
+ ((TIM_REMAP) == TIM1_ADC1_AWDG1) ||\
+ ((TIM_REMAP) == TIM1_ADC1_AWDG2) ||\
+ ((TIM_REMAP) == TIM1_ADC1_AWDG3) ||\
+ ((TIM_REMAP) == TIM1_ADC4_AWDG1) ||\
+ ((TIM_REMAP) == TIM1_ADC4_AWDG2) ||\
+ ((TIM_REMAP) == TIM1_ADC4_AWDG3) ||\
+ ((TIM_REMAP) == TIM8_ADC2_AWDG1) ||\
+ ((TIM_REMAP) == TIM8_ADC2_AWDG2) ||\
+ ((TIM_REMAP) == TIM8_ADC2_AWDG3) ||\
+ ((TIM_REMAP) == TIM8_ADC3_AWDG1) ||\
+ ((TIM_REMAP) == TIM8_ADC3_AWDG2) ||\
+ ((TIM_REMAP) == TIM8_ADC3_AWDG3))
+
+/**
+ * @}
+ */
+/** @defgroup TIM_Flags
+ * @{
+ */
+
+#define TIM_FLAG_Update ((uint32_t)0x00001)
+#define TIM_FLAG_CC1 ((uint32_t)0x00002)
+#define TIM_FLAG_CC2 ((uint32_t)0x00004)
+#define TIM_FLAG_CC3 ((uint32_t)0x00008)
+#define TIM_FLAG_CC4 ((uint32_t)0x00010)
+#define TIM_FLAG_COM ((uint32_t)0x00020)
+#define TIM_FLAG_Trigger ((uint32_t)0x00040)
+#define TIM_FLAG_Break ((uint32_t)0x00080)
+#define TIM_FLAG_Break2 ((uint32_t)0x00100)
+#define TIM_FLAG_CC1OF ((uint32_t)0x00200)
+#define TIM_FLAG_CC2OF ((uint32_t)0x00400)
+#define TIM_FLAG_CC3OF ((uint32_t)0x00800)
+#define TIM_FLAG_CC4OF ((uint32_t)0x01000)
+#define TIM_FLAG_CC5 ((uint32_t)0x10000)
+#define TIM_FLAG_CC6 ((uint32_t)0x20000)
+#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
+ ((FLAG) == TIM_FLAG_CC1) || \
+ ((FLAG) == TIM_FLAG_CC2) || \
+ ((FLAG) == TIM_FLAG_CC3) || \
+ ((FLAG) == TIM_FLAG_CC4) || \
+ ((FLAG) == TIM_FLAG_COM) || \
+ ((FLAG) == TIM_FLAG_Trigger) || \
+ ((FLAG) == TIM_FLAG_Break) || \
+ ((FLAG) == TIM_FLAG_Break2) || \
+ ((FLAG) == TIM_FLAG_CC1OF) || \
+ ((FLAG) == TIM_FLAG_CC2OF) || \
+ ((FLAG) == TIM_FLAG_CC3OF) || \
+ ((FLAG) == TIM_FLAG_CC4OF) ||\
+ ((FLAG) == TIM_FLAG_CC5) ||\
+ ((FLAG) == TIM_FLAG_CC6))
+
+#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint32_t)0xE000) == 0x0000) && ((TIM_FLAG) != 0x0000))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_OCReferenceClear
+ * @{
+ */
+#define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008)
+#define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000)
+#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \
+ ((SOURCE) == TIM_OCReferenceClear_OCREFCLR))
+
+/** @defgroup TIM_Input_Capture_Filer_Value
+ * @{
+ */
+
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_External_Trigger_Filter
+ * @{
+ */
+
+#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Legacy
+ * @{
+ */
+
+#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
+#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
+#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
+#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
+#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
+#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
+#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
+#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
+#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
+#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
+#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
+#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
+#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
+#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
+#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
+#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
+#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
+#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* TimeBase management ********************************************************/
+void TIM_DeInit(TIM_TypeDef* TIMx);
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
+uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
+void TIM_UIFRemap(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Output Compare management **************************************************/
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC5Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC6Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_SelectGC5C1(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectGC5C2(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectGC5C3(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint32_t TIM_OCMode);
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
+void TIM_SetCompare5(TIM_TypeDef* TIMx, uint32_t Compare5);
+void TIM_SetCompare6(TIM_TypeDef* TIMx, uint32_t Compare6);
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC5Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC6Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC5PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC6PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC5Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC6Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear);
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC5PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC6PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
+
+/* Input Capture management ***************************************************/
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
+uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
+uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
+uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+
+/* Advanced-control timers (TIM1 and TIM8) specific features ******************/
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
+void TIM_Break1Config(TIM_TypeDef* TIMx, uint32_t TIM_Break1Polarity, uint8_t TIM_Break1Filter);
+void TIM_Break2Config(TIM_TypeDef* TIMx, uint32_t TIM_Break2Polarity, uint8_t TIM_Break2Filter);
+void TIM_Break1Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_Break2Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Interrupts, DMA and flags management ***************************************/
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint32_t TIM_FLAG);
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Clocks management **********************************************************/
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
+ uint16_t TIM_ICPolarity, uint16_t ICFilter);
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter);
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
+
+/* Synchronization management *************************************************/
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
+void TIM_SelectOutputTrigger2(TIM_TypeDef* TIMx, uint32_t TIM_TRGO2Source);
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint32_t TIM_SlaveMode);
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter);
+
+/* Specific interface management **********************************************/
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
+ uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Specific remapping management **********************************************/
+void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F30x_TIM_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_usart.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,2094 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_usart.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Universal synchronous asynchronous receiver
+ * transmitter (USART):
+ * + Initialization and Configuration
+ * + STOP Mode
+ * + AutoBaudRate
+ * + Data transfers
+ * + Multi-Processor Communication
+ * + LIN mode
+ * + Half-duplex mode
+ * + Smartcard mode
+ * + IrDA mode
+ * + RS485 mode
+ * + DMA transfers management
+ * + Interrupts and flags management
+ *
+ * @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE)
+ function for USART1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE)
+ function for USART2, USART3, UART4 and UART5.
+ (#) According to the USART mode, enable the GPIO clocks using
+ RCC_AHBPeriphClockCmd() function. (The I/O can be TX, RX, CTS,
+ or and SCLK).
+ (#) Peripheral's alternate function:
+ (++) Connect the pin to the desired peripherals' Alternate
+ Function (AF) using GPIO_PinAFConfig() function.
+ (++) Configure the desired pin in alternate function by:
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
+ (++) Select the type, pull-up/pull-down and output speed via
+ GPIO_PuPd, GPIO_OType and GPIO_Speed members.
+ (++) Call GPIO_Init() function.
+ (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware
+ flow control and Mode(Receiver/Transmitter) using the SPI_Init()
+ function.
+ (#) For synchronous mode, enable the clock and program the polarity,
+ phase and last bit using the USART_ClockInit() function.
+ (#) Enable the USART using the USART_Cmd() function.
+ (#) Enable the NVIC and the corresponding interrupt using the function
+ USART_ITConfig() if you need to use interrupt mode.
+ (#) When using the DMA mode:
+ (++) Configure the DMA using DMA_Init() function.
+ (++) Activate the needed channel Request using USART_DMACmd() function.
+ (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode.
+ [..]
+ Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections
+ for more details.
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_usart.h"
+#include "stm32f30x_rcc.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup USART
+ * @brief USART driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/*!< USART CR1 register clear Mask ((~(uint32_t)0xFFFFE6F3)) */
+#define CR1_CLEAR_MASK ((uint32_t)(USART_CR1_M | USART_CR1_PCE | \
+ USART_CR1_PS | USART_CR1_TE | \
+ USART_CR1_RE))
+
+/*!< USART CR2 register clock bits clear Mask ((~(uint32_t)0xFFFFF0FF)) */
+#define CR2_CLOCK_CLEAR_MASK ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
+ USART_CR2_CPHA | USART_CR2_LBCL))
+
+/*!< USART CR3 register clear Mask ((~(uint32_t)0xFFFFFCFF)) */
+#define CR3_CLEAR_MASK ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
+
+/*!< USART Interrupts mask */
+#define IT_MASK ((uint32_t)0x000000FF)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup USART_Private_Functions
+ * @{
+ */
+
+/** @defgroup USART_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USART
+ in asynchronous and in synchronous modes.
+ (+) For the asynchronous mode only these parameters can be configured:
+ (++) Baud Rate.
+ (++) Word Length.
+ (++) Stop Bit.
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ Depending on the frame length defined by the M bit (8-bits or 9-bits),
+ the possible USART frame formats are as listed in the following table:
+ [..]
+ +-------------------------------------------------------------+
+ | M bit | PCE bit | USART frame |
+ |---------------------|---------------------------------------|
+ | 0 | 0 | | SB | 8 bit data | STB | |
+ |---------|-----------|---------------------------------------|
+ | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ |---------|-----------|---------------------------------------|
+ | 1 | 0 | | SB | 9 bit data | STB | |
+ |---------|-----------|---------------------------------------|
+ | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ +-------------------------------------------------------------+
+ [..]
+ (++) Hardware flow control.
+ (++) Receiver/transmitter modes.
+ [..] The USART_Init() function follows the USART asynchronous configuration
+ procedure(details for the procedure are available in reference manual.
+ (+) For the synchronous mode in addition to the asynchronous mode parameters
+ these parameters should be also configured:
+ (++) USART Clock Enabled.
+ (++) USART polarity.
+ (++) USART phase.
+ (++) USART LastBit.
+ [..] These parameters can be configured using the USART_ClockInit() function.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the USARTx peripheral registers to their default reset values.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @retval None
+ */
+void USART_DeInit(USART_TypeDef* USARTx)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ if (USARTx == USART1)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
+ }
+ else if (USARTx == USART2)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
+ }
+ else if (USARTx == USART3)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
+ }
+ else if (USARTx == UART4)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
+ }
+ else
+ {
+ if (USARTx == UART5)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
+ }
+ }
+}
+
+/**
+ * @brief Initializes the USARTx peripheral according to the specified
+ * parameters in the USART_InitStruct .
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param USART_InitStruct: pointer to a USART_InitTypeDef structure
+ * that contains the configuration information for the specified USART peripheral.
+ * @retval None
+ */
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
+{
+ uint32_t divider = 0, apbclock = 0, tmpreg = 0;
+ RCC_ClocksTypeDef RCC_ClocksStatus;
+
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));
+ assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
+ assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
+ assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
+ assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
+ assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
+
+ /* Disable USART */
+ USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UE);
+
+ /*---------------------------- USART CR2 Configuration -----------------------*/
+ tmpreg = USARTx->CR2;
+ /* Clear STOP[13:12] bits */
+ tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
+
+ /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
+ /* Set STOP[13:12] bits according to USART_StopBits value */
+ tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
+
+ /* Write to USART CR2 */
+ USARTx->CR2 = tmpreg;
+
+ /*---------------------------- USART CR1 Configuration -----------------------*/
+ tmpreg = USARTx->CR1;
+ /* Clear M, PCE, PS, TE and RE bits */
+ tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK);
+
+ /* Configure the USART Word Length, Parity and mode ----------------------- */
+ /* Set the M bits according to USART_WordLength value */
+ /* Set PCE and PS bits according to USART_Parity value */
+ /* Set TE and RE bits according to USART_Mode value */
+ tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
+ USART_InitStruct->USART_Mode;
+
+ /* Write to USART CR1 */
+ USARTx->CR1 = tmpreg;
+
+ /*---------------------------- USART CR3 Configuration -----------------------*/
+ tmpreg = USARTx->CR3;
+ /* Clear CTSE and RTSE bits */
+ tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK);
+
+ /* Configure the USART HFC -------------------------------------------------*/
+ /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
+ tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
+
+ /* Write to USART CR3 */
+ USARTx->CR3 = tmpreg;
+
+ /*---------------------------- USART BRR Configuration -----------------------*/
+ /* Configure the USART Baud Rate -------------------------------------------*/
+ RCC_GetClocksFreq(&RCC_ClocksStatus);
+
+ if (USARTx == USART1)
+ {
+ apbclock = RCC_ClocksStatus.USART1CLK_Frequency;
+ }
+ else if (USARTx == USART2)
+ {
+ apbclock = RCC_ClocksStatus.USART2CLK_Frequency;
+ }
+ else if (USARTx == USART3)
+ {
+ apbclock = RCC_ClocksStatus.USART3CLK_Frequency;
+ }
+ else if (USARTx == UART4)
+ {
+ apbclock = RCC_ClocksStatus.UART4CLK_Frequency;
+ }
+ else
+ {
+ apbclock = RCC_ClocksStatus.UART5CLK_Frequency;
+ }
+
+ /* Determine the integer part */
+ if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
+ {
+ /* (divider * 10) computing in case Oversampling mode is 8 Samples */
+ divider = (uint32_t)((2 * apbclock) / (USART_InitStruct->USART_BaudRate));
+ tmpreg = (uint32_t)((2 * apbclock) % (USART_InitStruct->USART_BaudRate));
+ }
+ else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
+ {
+ /* (divider * 10) computing in case Oversampling mode is 16 Samples */
+ divider = (uint32_t)((apbclock) / (USART_InitStruct->USART_BaudRate));
+ tmpreg = (uint32_t)((apbclock) % (USART_InitStruct->USART_BaudRate));
+ }
+
+ /* round the divider : if fractional part i greater than 0.5 increment divider */
+ if (tmpreg >= (USART_InitStruct->USART_BaudRate) / 2)
+ {
+ divider++;
+ }
+
+ /* Implement the divider in case Oversampling mode is 8 Samples */
+ if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
+ {
+ /* get the LSB of divider and shift it to the right by 1 bit */
+ tmpreg = (divider & (uint16_t)0x000F) >> 1;
+
+ /* update the divider value */
+ divider = (divider & (uint16_t)0xFFF0) | tmpreg;
+ }
+
+ /* Write to USART BRR */
+ USARTx->BRR = (uint16_t)divider;
+}
+
+/**
+ * @brief Fills each USART_InitStruct member with its default value.
+ * @param USART_InitStruct: pointer to a USART_InitTypeDef structure
+ * which will be initialized.
+ * @retval None
+ */
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
+{
+ /* USART_InitStruct members default value */
+ USART_InitStruct->USART_BaudRate = 9600;
+ USART_InitStruct->USART_WordLength = USART_WordLength_8b;
+ USART_InitStruct->USART_StopBits = USART_StopBits_1;
+ USART_InitStruct->USART_Parity = USART_Parity_No ;
+ USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+ USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+}
+
+/**
+ * @brief Initializes the USARTx peripheral Clock according to the
+ * specified parameters in the USART_ClockInitStruct.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3.
+ * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
+ * structure that contains the configuration information for the specified
+ * USART peripheral.
+ * @retval None
+ */
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
+ assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
+ assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
+ assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));
+/*---------------------------- USART CR2 Configuration -----------------------*/
+ tmpreg = USARTx->CR2;
+ /* Clear CLKEN, CPOL, CPHA, LBCL and SSM bits */
+ tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK);
+ /* Configure the USART Clock, CPOL, CPHA, LastBit and SSM ------------*/
+ /* Set CLKEN bit according to USART_Clock value */
+ /* Set CPOL bit according to USART_CPOL value */
+ /* Set CPHA bit according to USART_CPHA value */
+ /* Set LBCL bit according to USART_LastBit value */
+ tmpreg |= (uint32_t)(USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL |
+ USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit);
+ /* Write to USART CR2 */
+ USARTx->CR2 = tmpreg;
+}
+
+/**
+ * @brief Fills each USART_ClockInitStruct member with its default value.
+ * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
+ * structure which will be initialized.
+ * @retval None
+ */
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
+{
+ /* USART_ClockInitStruct members default value */
+ USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
+ USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
+ USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
+ USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
+}
+
+/**
+ * @brief Enables or disables the specified USART peripheral.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param NewState: new state of the USARTx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected USART by setting the UE bit in the CR1 register */
+ USARTx->CR1 |= USART_CR1_UE;
+ }
+ else
+ {
+ /* Disable the selected USART by clearing the UE bit in the CR1 register */
+ USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UE);
+ }
+}
+
+/**
+ * @brief Enables or disables the USART's transmitter or receiver.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param USART_Direction: specifies the USART direction.
+ * This parameter can be any combination of the following values:
+ * @arg USART_Mode_Tx: USART Transmitter
+ * @arg USART_Mode_Rx: USART Receiver
+ * @param NewState: new state of the USART transfer direction.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_MODE(USART_DirectionMode));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the USART's transfer interface by setting the TE and/or RE bits
+ in the USART CR1 register */
+ USARTx->CR1 |= USART_DirectionMode;
+ }
+ else
+ {
+ /* Disable the USART's transfer interface by clearing the TE and/or RE bits
+ in the USART CR3 register */
+ USARTx->CR1 &= (uint32_t)~USART_DirectionMode;
+ }
+}
+
+/**
+ * @brief Enables or disables the USART's 8x oversampling mode.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param NewState: new state of the USART 8x oversampling mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note
+ * This function has to be called before calling USART_Init()
+ * function in order to have correct baudrate Divider value.
+ * @retval None
+ */
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */
+ USARTx->CR1 |= USART_CR1_OVER8;
+ }
+ else
+ {
+ /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */
+ USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_OVER8);
+ }
+}
+
+/**
+ * @brief Enables or disables the USART's one bit sampling method.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param NewState: new state of the USART one bit sampling method.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note
+ * This function has to be called before calling USART_Cmd() function.
+ * @retval None
+ */
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the one bit method by setting the ONEBIT bit in the CR3 register */
+ USARTx->CR3 |= USART_CR3_ONEBIT;
+ }
+ else
+ {
+ /* Disable the one bit method by clearing the ONEBIT bit in the CR3 register */
+ USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT);
+ }
+}
+
+/**
+ * @brief Enables or disables the USART's most significant bit first
+ * transmitted/received following the start bit.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param NewState: new state of the USART most significant bit first
+ * transmitted/received following the start bit.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note
+ * This function has to be called before calling USART_Cmd() function.
+ * @retval None
+ */
+void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the most significant bit first transmitted/received following the
+ start bit by setting the MSBFIRST bit in the CR2 register */
+ USARTx->CR2 |= USART_CR2_MSBFIRST;
+ }
+ else
+ {
+ /* Disable the most significant bit first transmitted/received following the
+ start bit by clearing the MSBFIRST bit in the CR2 register */
+ USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_MSBFIRST);
+ }
+}
+
+/**
+ * @brief Enables or disables the binary data inversion.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param NewState: new defined levels for the USART data.
+ * This parameter can be: ENABLE or DISABLE.
+ * @arg ENABLE: Logical data from the data register are send/received in negative
+ * logic. (1=L, 0=H). The parity bit is also inverted.
+ * @arg DISABLE: Logical data from the data register are send/received in positive
+ * logic. (1=H, 0=L)
+ * @note
+ * This function has to be called before calling USART_Cmd() function.
+ * @retval None
+ */
+void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the binary data inversion feature by setting the DATAINV bit in
+ the CR2 register */
+ USARTx->CR2 |= USART_CR2_DATAINV;
+ }
+ else
+ {
+ /* Disable the binary data inversion feature by clearing the DATAINV bit in
+ the CR2 register */
+ USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_DATAINV);
+ }
+}
+
+/**
+ * @brief Enables or disables the Pin(s) active level inversion.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param USART_InvPin: specifies the USART pin(s) to invert.
+ * This parameter can be any combination of the following values:
+ * @arg USART_InvPin_Tx: USART Tx pin active level inversion.
+ * @arg USART_InvPin_Rx: USART Rx pin active level inversion.
+ * @param NewState: new active level status for the USART pin(s).
+ * This parameter can be: ENABLE or DISABLE.
+ * - ENABLE: pin(s) signal values are inverted (Vdd =0, Gnd =1).
+ * - DISABLE: pin(s) signal works using the standard logic levels (Vdd =1, Gnd =0).
+ * @note
+ * This function has to be called before calling USART_Cmd() function.
+ * @retval None
+ */
+void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_INVERSTION_PIN(USART_InvPin));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the active level inversion for selected pins by setting the TXINV
+ and/or RXINV bits in the USART CR2 register */
+ USARTx->CR2 |= USART_InvPin;
+ }
+ else
+ {
+ /* Disable the active level inversion for selected requests by clearing the
+ TXINV and/or RXINV bits in the USART CR2 register */
+ USARTx->CR2 &= (uint32_t)~USART_InvPin;
+ }
+}
+
+/**
+ * @brief Enables or disables the swap Tx/Rx pins.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param NewState: new state of the USARTx TX/RX pins pinout.
+ * This parameter can be: ENABLE or DISABLE.
+ * @arg ENABLE: The TX and RX pins functions are swapped.
+ * @arg DISABLE: TX/RX pins are used as defined in standard pinout
+ * @note
+ * This function has to be called before calling USART_Cmd() function.
+ * @retval None
+ */
+void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the SWAP feature by setting the SWAP bit in the CR2 register */
+ USARTx->CR2 |= USART_CR2_SWAP;
+ }
+ else
+ {
+ /* Disable the SWAP feature by clearing the SWAP bit in the CR2 register */
+ USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_SWAP);
+ }
+}
+
+/**
+ * @brief Enables or disables the receiver Time Out feature.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param NewState: new state of the USARTx receiver Time Out.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the receiver time out feature by setting the RTOEN bit in the CR2
+ register */
+ USARTx->CR2 |= USART_CR2_RTOEN;
+ }
+ else
+ {
+ /* Disable the receiver time out feature by clearing the RTOEN bit in the CR2
+ register */
+ USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_RTOEN);
+ }
+}
+
+/**
+ * @brief Sets the receiver Time Out value.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param USART_ReceiverTimeOut: specifies the Receiver Time Out value.
+ * @retval None
+ */
+void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_TIMEOUT(USART_ReceiverTimeOut));
+
+ /* Clear the receiver Time Out value by clearing the RTO[23:0] bits in the RTOR
+ register */
+ USARTx->RTOR &= (uint32_t)~((uint32_t)USART_RTOR_RTO);
+ /* Set the receiver Time Out value by setting the RTO[23:0] bits in the RTOR
+ register */
+ USARTx->RTOR |= USART_ReceiverTimeOut;
+}
+
+/**
+ * @brief Sets the system clock prescaler.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param USART_Prescaler: specifies the prescaler clock.
+ * @note
+ * This function has to be called before calling USART_Cmd() function.
+ * @retval None
+ */
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ /* Clear the USART prescaler */
+ USARTx->GTPR &= USART_GTPR_GT;
+ /* Set the USART prescaler */
+ USARTx->GTPR |= USART_Prescaler;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup USART_Group2 STOP Mode functions
+ * @brief STOP Mode functions
+ *
+@verbatim
+ ===============================================================================
+ ##### STOP Mode functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to manage
+ WakeUp from STOP mode.
+
+ [..] The USART is able to WakeUp from Stop Mode if USART clock is set to HSI
+ or LSI.
+
+ [..] The WakeUp source is configured by calling USART_StopModeWakeUpSourceConfig()
+ function.
+
+ [..] After configuring the source of WakeUp and before entering in Stop Mode
+ USART_STOPModeCmd() function should be called to allow USART WakeUp.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the specified USART peripheral in STOP Mode.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param NewState: new state of the USARTx peripheral state in stop mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note
+ * This function has to be called when USART clock is set to HSI or LSE.
+ * @retval None
+ */
+void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected USART in STOP mode by setting the UESM bit in the CR1
+ register */
+ USARTx->CR1 |= USART_CR1_UESM;
+ }
+ else
+ {
+ /* Disable the selected USART in STOP mode by clearing the UE bit in the CR1
+ register */
+ USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UESM);
+ }
+}
+
+/**
+ * @brief Selects the USART WakeUp method form stop mode.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param USART_WakeUp: specifies the selected USART wakeup method.
+ * This parameter can be one of the following values:
+ * @arg USART_WakeUpSource_AddressMatch: WUF active on address match.
+ * @arg USART_WakeUpSource_StartBit: WUF active on Start bit detection.
+ * @arg USART_WakeUpSource_RXNE: WUF active on RXNE.
+ * @note
+ * This function has to be called before calling USART_Cmd() function.
+ * @retval None
+ */
+void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_STOPMODE_WAKEUPSOURCE(USART_WakeUpSource));
+
+ USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_WUS);
+ USARTx->CR3 |= USART_WakeUpSource;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup USART_Group3 AutoBaudRate functions
+ * @brief AutoBaudRate functions
+ *
+@verbatim
+ ===============================================================================
+ ##### AutoBaudRate functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to manage
+ the AutoBaudRate detections.
+
+ [..] Before Enabling AutoBaudRate detection using USART_AutoBaudRateCmd ()
+ The character patterns used to calculate baudrate must be chosen by calling
+ USART_AutoBaudRateConfig() function. These function take as parameter :
+ (#)USART_AutoBaudRate_StartBit : any character starting with a bit 1.
+ (#)USART_AutoBaudRate_FallingEdge : any character starting with a 10xx bit pattern.
+
+ [..] At any later time, another request for AutoBaudRate detection can be performed
+ using USART_RequestCmd() function.
+
+ [..] The AutoBaudRate detection is monitored by the status of ABRF flag which indicate
+ that the AutoBaudRate detection is completed. In addition to ABRF flag, the ABRE flag
+ indicate that this procedure is completed without success. USART_GetFlagStatus ()
+ function should be used to monitor the status of these flags.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the Auto Baud Rate.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param NewState: new state of the USARTx auto baud rate.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the auto baud rate feature by setting the ABREN bit in the CR2
+ register */
+ USARTx->CR2 |= USART_CR2_ABREN;
+ }
+ else
+ {
+ /* Disable the auto baud rate feature by clearing the ABREN bit in the CR2
+ register */
+ USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ABREN);
+ }
+}
+
+/**
+ * @brief Selects the USART auto baud rate method.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param USART_AutoBaudRate: specifies the selected USART auto baud rate method.
+ * This parameter can be one of the following values:
+ * @arg USART_AutoBaudRate_StartBit: Start Bit duration measurement.
+ * @arg USART_AutoBaudRate_FallingEdge: Falling edge to falling edge measurement.
+ * @arg USART_AutoBaudRate_0x7FFrame: 0x7F frame.
+ * @arg USART_AutoBaudRate_0x55Frame: 0x55 frame.
+ * @note
+ * This function has to be called before calling USART_Cmd() function.
+ * @retval None
+ */
+void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_AUTOBAUDRATE_MODE(USART_AutoBaudRate));
+
+ USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ABRMODE);
+ USARTx->CR2 |= USART_AutoBaudRate;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup USART_Group4 Data transfers functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Data transfers functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to manage
+ the USART data transfers.
+ [..] During an USART reception, data shifts in least significant bit first
+ through the RX pin. When a transmission is taking place, a write instruction to
+ the USART_TDR register stores the data in the shift register.
+ [..] The read access of the USART_RDR register can be done using
+ the USART_ReceiveData() function and returns the RDR value.
+ Whereas a write access to the USART_TDR can be done using USART_SendData()
+ function and stores the written data into TDR.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmits single data through the USARTx peripheral.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param Data: the data to transmit.
+ * @retval None
+ */
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_DATA(Data));
+
+ /* Transmit Data */
+ USARTx->TDR = (Data & (uint16_t)0x01FF);
+}
+
+/**
+ * @brief Returns the most recent received data by the USARTx peripheral.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @retval The received data.
+ */
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ /* Receive Data */
+ return (uint16_t)(USARTx->RDR & (uint16_t)0x01FF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Group5 MultiProcessor Communication functions
+ * @brief Multi-Processor Communication functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Multi-Processor Communication functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to manage the USART
+ multiprocessor communication.
+ [..] For instance one of the USARTs can be the master, its TX output is
+ connected to the RX input of the other USART. The others are slaves,
+ their respective TX outputs are logically ANDed together and connected
+ to the RX input of the master. USART multiprocessor communication is
+ possible through the following procedure:
+ (#) Program the Baud rate, Word length = 9 bits, Stop bits, Parity,
+ Mode transmitter or Mode receiver and hardware flow control values
+ using the USART_Init() function.
+ (#) Configures the USART address using the USART_SetAddress() function.
+ (#) Configures the wake up methode (USART_WakeUp_IdleLine or
+ USART_WakeUp_AddressMark) using USART_WakeUpConfig() function only
+ for the slaves.
+ (#) Enable the USART using the USART_Cmd() function.
+ (#) Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd()
+ function.
+ [..] The USART Slave exit from mute mode when receive the wake up condition.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Sets the address of the USART node.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param USART_Address: Indicates the address of the USART node.
+ * @retval None
+ */
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ /* Clear the USART address */
+ USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ADD);
+ /* Set the USART address node */
+ USARTx->CR2 |=((uint32_t)USART_Address << (uint32_t)0x18);
+}
+
+/**
+ * @brief Enables or disables the USART's mute mode.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param NewState: new state of the USART mute mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the USART mute mode by setting the MME bit in the CR1 register */
+ USARTx->CR1 |= USART_CR1_MME;
+ }
+ else
+ {
+ /* Disable the USART mute mode by clearing the MME bit in the CR1 register */
+ USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_MME);
+ }
+}
+
+/**
+ * @brief Selects the USART WakeUp method from mute mode.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param USART_WakeUp: specifies the USART wakeup method.
+ * This parameter can be one of the following values:
+ * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection
+ * @arg USART_WakeUp_AddressMark: WakeUp by an address mark
+ * @retval None
+ */
+void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_MUTEMODE_WAKEUP(USART_WakeUp));
+
+ USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_WAKE);
+ USARTx->CR1 |= USART_WakeUp;
+}
+
+/**
+ * @brief Configure the the USART Address detection length.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param USART_AddressLength: specifies the USART address length detection.
+ * This parameter can be one of the following values:
+ * @arg USART_AddressLength_4b: 4-bit address length detection
+ * @arg USART_AddressLength_7b: 7-bit address length detection
+ * @retval None
+ */
+void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_ADDRESS_DETECTION(USART_AddressLength));
+
+ USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ADDM7);
+ USARTx->CR2 |= USART_AddressLength;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Group6 LIN mode functions
+ * @brief LIN mode functions
+ *
+@verbatim
+ ===============================================================================
+ ##### LIN mode functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to manage the USART
+ LIN Mode communication.
+ [..] In LIN mode, 8-bit data format with 1 stop bit is required in accordance
+ with the LIN standard.
+ [..] Only this LIN Feature is supported by the USART IP:
+ (+) LIN Master Synchronous Break send capability and LIN slave break
+ detection capability : 13-bit break generation and 10/11 bit break
+ detection.
+ [..] USART LIN Master transmitter communication is possible through the
+ following procedure:
+ (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity,
+ Mode transmitter or Mode receiver and hardware flow control values
+ using the USART_Init() function.
+ (#) Enable the LIN mode using the USART_LINCmd() function.
+ (#) Enable the USART using the USART_Cmd() function.
+ (#) Send the break character using USART_SendBreak() function.
+ [..] USART LIN Master receiver communication is possible through the
+ following procedure:
+ (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity,
+ Mode transmitter or Mode receiver and hardware flow control values
+ using the USART_Init() function.
+ (#) Configures the break detection length
+ using the USART_LINBreakDetectLengthConfig() function.
+ (#) Enable the LIN mode using the USART_LINCmd() function.
+ (#) Enable the USART using the USART_Cmd() function.
+ [..]
+ (@) In LIN mode, the following bits must be kept cleared:
+ (+@) CLKEN in the USART_CR2 register.
+ (+@) STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Sets the USART LIN Break detection length.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param USART_LINBreakDetectLength: specifies the LIN break detection length.
+ * This parameter can be one of the following values:
+ * @arg USART_LINBreakDetectLength_10b: 10-bit break detection
+ * @arg USART_LINBreakDetectLength_11b: 11-bit break detection
+ * @retval None
+ */
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
+
+ USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_LBDL);
+ USARTx->CR2 |= USART_LINBreakDetectLength;
+}
+
+/**
+ * @brief Enables or disables the USART's LIN mode.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param NewState: new state of the USART LIN mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+ USARTx->CR2 |= USART_CR2_LINEN;
+ }
+ else
+ {
+ /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
+ USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_LINEN);
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Group7 Halfduplex mode function
+ * @brief Half-duplex mode function
+ *
+@verbatim
+ ===============================================================================
+ ##### Half-duplex mode function #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to manage the USART
+ Half-duplex communication.
+ [..] The USART can be configured to follow a single-wire half-duplex protocol
+ where the TX and RX lines are internally connected.
+ [..] USART Half duplex communication is possible through the following procedure:
+ (#) Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter
+ or Mode receiver and hardware flow control values using the USART_Init()
+ function.
+ (#) Configures the USART address using the USART_SetAddress() function.
+ (#) Enable the half duplex mode using USART_HalfDuplexCmd() function.
+ (#) Enable the USART using the USART_Cmd() function.
+ [..]
+ (@) The RX pin is no longer used.
+ (@) In Half-duplex mode the following bits must be kept cleared:
+ (+@) LINEN and CLKEN bits in the USART_CR2 register.
+ (+@) SCEN and IREN bits in the USART_CR3 register.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the USART's Half Duplex communication.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param NewState: new state of the USART Communication.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+ USARTx->CR3 |= USART_CR3_HDSEL;
+ }
+ else
+ {
+ /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
+ USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_HDSEL);
+ }
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup USART_Group8 Smartcard mode functions
+ * @brief Smartcard mode functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Smartcard mode functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to manage the USART
+ Smartcard communication.
+ [..] The Smartcard interface is designed to support asynchronous protocol
+ Smartcards as defined in the ISO 7816-3 standard. The USART can provide
+ a clock to the smartcard through the SCLK output. In smartcard mode,
+ SCLK is not associated to the communication but is simply derived from
+ the internal peripheral input clock through a 5-bit prescaler.
+ [..] Smartcard communication is possible through the following procedure:
+ (#) Configures the Smartcard Prsecaler using the USART_SetPrescaler()
+ function.
+ (#) Configures the Smartcard Guard Time using the USART_SetGuardTime()
+ function.
+ (#) Program the USART clock using the USART_ClockInit() function as following:
+ (++) USART Clock enabled.
+ (++) USART CPOL Low.
+ (++) USART CPHA on first edge.
+ (++) USART Last Bit Clock Enabled.
+ (#) Program the Smartcard interface using the USART_Init() function as
+ following:
+ (++) Word Length = 9 Bits.
+ (++) 1.5 Stop Bit.
+ (++) Even parity.
+ (++) BaudRate = 12096 baud.
+ (++) Hardware flow control disabled (RTS and CTS signals).
+ (++) Tx and Rx enabled
+ (#) Optionally you can enable the parity error interrupt using
+ the USART_ITConfig() function.
+ (#) Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function.
+ (#) Enable the Smartcard interface using the USART_SmartCardCmd() function.
+ (#) Enable the USART using the USART_Cmd() function.
+ [..]
+ Please refer to the ISO 7816-3 specification for more details.
+ [..]
+ (@) It is also possible to choose 0.5 stop bit for receiving but it is
+ recommended to use 1.5 stop bits for both transmitting and receiving
+ to avoid switching between the two configurations.
+ (@) In smartcard mode, the following bits must be kept cleared:
+ (+@) LINEN bit in the USART_CR2 register.
+ (+@) HDSEL and IREN bits in the USART_CR3 register.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Sets the specified USART guard time.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3.
+ * @param USART_GuardTime: specifies the guard time.
+ * @retval None
+ */
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+
+ /* Clear the USART Guard time */
+ USARTx->GTPR &= USART_GTPR_PSC;
+ /* Set the USART guard time */
+ USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
+}
+
+/**
+ * @brief Enables or disables the USART's Smart Card mode.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3.
+ * @param NewState: new state of the Smart Card mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the SC mode by setting the SCEN bit in the CR3 register */
+ USARTx->CR3 |= USART_CR3_SCEN;
+ }
+ else
+ {
+ /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
+ USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_SCEN);
+ }
+}
+
+/**
+ * @brief Enables or disables NACK transmission.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3.
+ * @param NewState: new state of the NACK transmission.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
+ USARTx->CR3 |= USART_CR3_NACK;
+ }
+ else
+ {
+ /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
+ USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_NACK);
+ }
+}
+
+/**
+ * @brief Sets the Smart Card number of retries in transmit and receive.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3.
+ * @param USART_AutoCount: specifies the Smart Card auto retry count.
+ * @retval None
+ */
+void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ assert_param(IS_USART_AUTO_RETRY_COUNTER(USART_AutoCount));
+ /* Clear the USART auto retry count */
+ USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_SCARCNT);
+ /* Set the USART auto retry count*/
+ USARTx->CR3 |= (uint32_t)((uint32_t)USART_AutoCount << 0x11);
+}
+
+/**
+ * @brief Sets the Smart Card Block length.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3.
+ * @param USART_BlockLength: specifies the Smart Card block length.
+ * @retval None
+ */
+void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+
+ /* Clear the Smart card block length */
+ USARTx->RTOR &= (uint32_t)~((uint32_t)USART_RTOR_BLEN);
+ /* Set the Smart Card block length */
+ USARTx->RTOR |= (uint32_t)((uint32_t)USART_BlockLength << 0x18);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Group9 IrDA mode functions
+ * @brief IrDA mode functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IrDA mode functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to manage the USART
+ IrDA communication.
+ [..] IrDA is a half duplex communication protocol. If the Transmitter is busy,
+ any data on the IrDA receive line will be ignored by the IrDA decoder
+ and if the Receiver is busy, data on the TX from the USART to IrDA will
+ not be encoded by IrDA. While receiving data, transmission should be
+ avoided as the data to be transmitted could be corrupted.
+ [..] IrDA communication is possible through the following procedure:
+ (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity,
+ Transmitter/Receiver modes and hardware flow control values using
+ the USART_Init() function.
+ (#) Configures the IrDA pulse width by configuring the prescaler using
+ the USART_SetPrescaler() function.
+ (#) Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal
+ mode using the USART_IrDAConfig() function.
+ (#) Enable the IrDA using the USART_IrDACmd() function.
+ (#) Enable the USART using the USART_Cmd() function.
+ [..]
+ (@) A pulse of width less than two and greater than one PSC period(s) may or
+ may not be rejected.
+ (@) The receiver set up time should be managed by software. The IrDA physical
+ layer specification specifies a minimum of 10 ms delay between
+ transmission and reception (IrDA is a half duplex protocol).
+ (@) In IrDA mode, the following bits must be kept cleared:
+ (+@) LINEN, STOP and CLKEN bits in the USART_CR2 register.
+ (+@) SCEN and HDSEL bits in the USART_CR3 register.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the USART's IrDA interface.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param USART_IrDAMode: specifies the IrDA mode.
+ * This parameter can be one of the following values:
+ * @arg USART_IrDAMode_LowPower
+ * @arg USART_IrDAMode_Normal
+ * @retval None
+ */
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
+
+ USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_IRLP);
+ USARTx->CR3 |= USART_IrDAMode;
+}
+
+/**
+ * @brief Enables or disables the USART's IrDA interface.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param NewState: new state of the IrDA mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
+ USARTx->CR3 |= USART_CR3_IREN;
+ }
+ else
+ {
+ /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
+ USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_IREN);
+ }
+}
+/**
+ * @}
+ */
+
+/** @defgroup USART_Group10 RS485 mode function
+ * @brief RS485 mode function
+ *
+@verbatim
+ ===============================================================================
+ ##### RS485 mode functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to manage the USART
+ RS485 flow control.
+ [..] RS485 flow control (Driver enable feature) handling is possible through
+ the following procedure:
+ (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity,
+ Transmitter/Receiver modes and hardware flow control values using
+ the USART_Init() function.
+ (#) Enable the Driver Enable using the USART_DECmd() function.
+ (#) Configures the Driver Enable polarity using the USART_DEPolarityConfig()
+ function.
+ (#) Configures the Driver Enable assertion time using USART_SetDEAssertionTime()
+ function and deassertion time using the USART_SetDEDeassertionTime()
+ function.
+ (#) Enable the USART using the USART_Cmd() function.
+ [..]
+ (@) The assertion and dessertion times are expressed in sample time units (1/8 or
+ 1/16 bit time, depending on the oversampling rate).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the USART's DE functionality.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param NewState: new state of the driver enable mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the DE functionality by setting the DEM bit in the CR3 register */
+ USARTx->CR3 |= USART_CR3_DEM;
+ }
+ else
+ {
+ /* Disable the DE functionality by clearing the DEM bit in the CR3 register */
+ USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DEM);
+ }
+}
+
+/**
+ * @brief Configures the USART's DE polarity
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param USART_DEPolarity: specifies the DE polarity.
+ * This parameter can be one of the following values:
+ * @arg USART_DEPolarity_Low
+ * @arg USART_DEPolarity_High
+ * @retval None
+ */
+void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_DE_POLARITY(USART_DEPolarity));
+
+ USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DEP);
+ USARTx->CR3 |= USART_DEPolarity;
+}
+
+/**
+ * @brief Sets the specified RS485 DE assertion time
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param USART_AssertionTime: specifies the time between the activation of the DE
+ * signal and the beginning of the start bit
+ * @retval None
+ */
+void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_DE_ASSERTION_DEASSERTION_TIME(USART_DEAssertionTime));
+
+ /* Clear the DE assertion time */
+ USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_DEAT);
+ /* Set the new value for the DE assertion time */
+ USARTx->CR1 |=((uint32_t)USART_DEAssertionTime << (uint32_t)0x15);
+}
+
+/**
+ * @brief Sets the specified RS485 DE deassertion time
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param USART_DeassertionTime: specifies the time between the middle of the last
+ * stop bit in a transmitted message and the de-activation of the DE signal
+ * @retval None
+ */
+void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_DE_ASSERTION_DEASSERTION_TIME(USART_DEDeassertionTime));
+
+ /* Clear the DE deassertion time */
+ USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_DEDT);
+ /* Set the new value for the DE deassertion time */
+ USARTx->CR1 |=((uint32_t)USART_DEDeassertionTime << (uint32_t)0x10);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Group11 DMA transfers management functions
+ * @brief DMA transfers management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### DMA transfers management functions #####
+ ===============================================================================
+ [..] This section provides two functions that can be used only in DMA mode.
+ [..] In DMA Mode, the USART communication can be managed by 2 DMA Channel
+ requests:
+ (#) USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
+ (#) USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
+ [..] In this Mode it is advised to use the following function:
+ (+) void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq,
+ FunctionalState NewState).
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the USART's DMA interface.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4.
+ * @param USART_DMAReq: specifies the DMA request.
+ * This parameter can be any combination of the following values:
+ * @arg USART_DMAReq_Tx: USART DMA transmit request
+ * @arg USART_DMAReq_Rx: USART DMA receive request
+ * @param NewState: new state of the DMA Request sources.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_1234_PERIPH(USARTx));
+ assert_param(IS_USART_DMAREQ(USART_DMAReq));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the DMA transfer for selected requests by setting the DMAT and/or
+ DMAR bits in the USART CR3 register */
+ USARTx->CR3 |= USART_DMAReq;
+ }
+ else
+ {
+ /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
+ DMAR bits in the USART CR3 register */
+ USARTx->CR3 &= (uint32_t)~USART_DMAReq;
+ }
+}
+
+/**
+ * @brief Enables or disables the USART's DMA interface when reception error occurs.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4.
+ * @param USART_DMAOnError: specifies the DMA status in case of reception error.
+ * This parameter can be any combination of the following values:
+ * @arg USART_DMAOnError_Enable: DMA receive request enabled when the USART DMA
+ * reception error is asserted.
+ * @arg USART_DMAOnError_Disable: DMA receive request disabled when the USART DMA
+ * reception error is asserted.
+ * @retval None
+ */
+void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_1234_PERIPH(USARTx));
+ assert_param(IS_USART_DMAONERROR(USART_DMAOnError));
+
+ /* Clear the DMA Reception error detection bit */
+ USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DDRE);
+ /* Set the new value for the DMA Reception error detection bit */
+ USARTx->CR3 |= USART_DMAOnError;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Group12 Interrupts and flags management functions
+ * @brief Interrupts and flags management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupts and flags management functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to configure the
+ USART Interrupts sources, Requests and check or clear the flags or pending bits status.
+ The user should identify which mode will be used in his application to
+ manage the communication: Polling mode, Interrupt mode.
+
+ *** Polling Mode ***
+ ====================
+ [..] In Polling Mode, the SPI communication can be managed by these flags:
+ (#) USART_FLAG_REACK: to indicate the status of the Receive Enable
+ acknowledge flag
+ (#) USART_FLAG_TEACK: to indicate the status of the Transmit Enable
+ acknowledge flag.
+ (#) USART_FLAG_WUF: to indicate the status of the Wake up flag.
+ (#) USART_FLAG_RWU: to indicate the status of the Receive Wake up flag.
+ (#) USART_FLAG_SBK: to indicate the status of the Send Break flag.
+ (#) USART_FLAG_CMF: to indicate the status of the Character match flag.
+ (#) USART_FLAG_BUSY: to indicate the status of the Busy flag.
+ (#) USART_FLAG_ABRF: to indicate the status of the Auto baud rate flag.
+ (#) USART_FLAG_ABRE: to indicate the status of the Auto baud rate error flag.
+ (#) USART_FLAG_EOBF: to indicate the status of the End of block flag.
+ (#) USART_FLAG_RTOF: to indicate the status of the Receive time out flag.
+ (#) USART_FLAG_nCTSS: to indicate the status of the Inverted nCTS input
+ bit status.
+ (#) USART_FLAG_TXE: to indicate the status of the transmit buffer register.
+ (#) USART_FLAG_RXNE: to indicate the status of the receive buffer register.
+ (#) USART_FLAG_TC: to indicate the status of the transmit operation.
+ (#) USART_FLAG_IDLE: to indicate the status of the Idle Line.
+ (#) USART_FLAG_CTS: to indicate the status of the nCTS input.
+ (#) USART_FLAG_LBD: to indicate the status of the LIN break detection.
+ (#) USART_FLAG_NE: to indicate if a noise error occur.
+ (#) USART_FLAG_FE: to indicate if a frame error occur.
+ (#) USART_FLAG_PE: to indicate if a parity error occur.
+ (#) USART_FLAG_ORE: to indicate if an Overrun error occur.
+ [..] In this Mode it is advised to use the following functions:
+ (+) FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG).
+ (+) void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG).
+
+ *** Interrupt Mode ***
+ ======================
+ [..] In Interrupt Mode, the USART communication can be managed by 8 interrupt
+ sources and 10 pending bits:
+ (+) Pending Bits:
+ (##) USART_IT_WU: to indicate the status of the Wake up interrupt.
+ (##) USART_IT_CM: to indicate the status of Character match interrupt.
+ (##) USART_IT_EOB: to indicate the status of End of block interrupt.
+ (##) USART_IT_RTO: to indicate the status of Receive time out interrupt.
+ (##) USART_IT_CTS: to indicate the status of CTS change interrupt.
+ (##) USART_IT_LBD: to indicate the status of LIN Break detection interrupt.
+ (##) USART_IT_TC: to indicate the status of Transmission complete interrupt.
+ (##) USART_IT_IDLE: to indicate the status of IDLE line detected interrupt.
+ (##) USART_IT_ORE: to indicate the status of OverRun Error interrupt.
+ (##) USART_IT_NE: to indicate the status of Noise Error interrupt.
+ (##) USART_IT_FE: to indicate the status of Framing Error interrupt.
+ (##) USART_IT_PE: to indicate the status of Parity Error interrupt.
+
+ (+) Interrupt Source:
+ (##) USART_IT_WU: specifies the interrupt source for Wake up interrupt.
+ (##) USART_IT_CM: specifies the interrupt source for Character match
+ interrupt.
+ (##) USART_IT_EOB: specifies the interrupt source for End of block
+ interrupt.
+ (##) USART_IT_RTO: specifies the interrupt source for Receive time-out
+ interrupt.
+ (##) USART_IT_CTS: specifies the interrupt source for CTS change interrupt.
+ (##) USART_IT_LBD: specifies the interrupt source for LIN Break
+ detection interrupt.
+ (##) USART_IT_TXE: specifies the interrupt source for Tansmit Data
+ Register empty interrupt.
+ (##) USART_IT_TC: specifies the interrupt source for Transmission
+ complete interrupt.
+ (##) USART_IT_RXNE: specifies the interrupt source for Receive Data
+ register not empty interrupt.
+ (##) USART_IT_IDLE: specifies the interrupt source for Idle line
+ detection interrupt.
+ (##) USART_IT_PE: specifies the interrupt source for Parity Error interrupt.
+ (##) USART_IT_ERR: specifies the interrupt source for Error interrupt
+ (Frame error, noise error, overrun error)
+ -@@- Some parameters are coded in order to use them as interrupt
+ source or as pending bits.
+ [..] In this Mode it is advised to use the following functions:
+ (+) void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState).
+ (+) ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT).
+ (+) void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the specified USART interrupts.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg USART_IT_WU: Wake up interrupt.
+ * @arg USART_IT_CM: Character match interrupt.
+ * @arg USART_IT_EOB: End of block interrupt.
+ * @arg USART_IT_RTO: Receive time out interrupt.
+ * @arg USART_IT_CTS: CTS change interrupt.
+ * @arg USART_IT_LBD: LIN Break detection interrupt.
+ * @arg USART_IT_TXE: Tansmit Data Register empty interrupt.
+ * @arg USART_IT_TC: Transmission complete interrupt.
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt.
+ * @arg USART_IT_IDLE: Idle line detection interrupt.
+ * @arg USART_IT_PE: Parity Error interrupt.
+ * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @param NewState: new state of the specified USARTx interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState)
+{
+ uint32_t usartreg = 0, itpos = 0, itmask = 0;
+ uint32_t usartxbase = 0;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_CONFIG_IT(USART_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ usartxbase = (uint32_t)USARTx;
+
+ /* Get the USART register index */
+ usartreg = (((uint16_t)USART_IT) >> 0x08);
+
+ /* Get the interrupt position */
+ itpos = USART_IT & IT_MASK;
+ itmask = (((uint32_t)0x01) << itpos);
+
+ if (usartreg == 0x02) /* The IT is in CR2 register */
+ {
+ usartxbase += 0x04;
+ }
+ else if (usartreg == 0x03) /* The IT is in CR3 register */
+ {
+ usartxbase += 0x08;
+ }
+ else /* The IT is in CR1 register */
+ {
+ }
+ if (NewState != DISABLE)
+ {
+ *(__IO uint32_t*)usartxbase |= itmask;
+ }
+ else
+ {
+ *(__IO uint32_t*)usartxbase &= ~itmask;
+ }
+}
+
+/**
+ * @brief Enables the specified USART's Request.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param USART_Request: specifies the USART request.
+ * This parameter can be any combination of the following values:
+ * @arg USART_Request_TXFRQ: Transmit data flush ReQuest
+ * @arg USART_Request_RXFRQ: Receive data flush ReQuest
+ * @arg USART_Request_MMRQ: Mute Mode ReQuest
+ * @arg USART_Request_SBKRQ: Send Break ReQuest
+ * @arg USART_Request_ABRRQ: Auto Baud Rate ReQuest
+ * @param NewState: new state of the DMA interface when reception error occurs.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_REQUEST(USART_Request));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the USART ReQuest by setting the dedicated request bit in the RQR
+ register.*/
+ USARTx->RQR |= USART_Request;
+ }
+ else
+ {
+ /* Disable the USART ReQuest by clearing the dedicated request bit in the RQR
+ register.*/
+ USARTx->RQR &= (uint32_t)~USART_Request;
+ }
+}
+
+/**
+ * @brief Enables or disables the USART's Overrun detection.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param USART_OVRDetection: specifies the OVR detection status in case of OVR error.
+ * This parameter can be any combination of the following values:
+ * @arg USART_OVRDetection_Enable: OVR error detection enabled when the USART OVR error
+ * is asserted.
+ * @arg USART_OVRDetection_Disable: OVR error detection disabled when the USART OVR error
+ * is asserted.
+ * @retval None
+ */
+void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_OVRDETECTION(USART_OVRDetection));
+
+ /* Clear the OVR detection bit */
+ USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_OVRDIS);
+ /* Set the new value for the OVR detection bit */
+ USARTx->CR3 |= USART_OVRDetection;
+}
+
+/**
+ * @brief Checks whether the specified USART flag is set or not.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param USART_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg USART_FLAG_REACK: Receive Enable acknowledge flag.
+ * @arg USART_FLAG_TEACK: Transmit Enable acknowledge flag.
+ * @arg USART_FLAG_WUF: Wake up flag.
+ * @arg USART_FLAG_RWU: Receive Wake up flag.
+ * @arg USART_FLAG_SBK: Send Break flag.
+ * @arg USART_FLAG_CMF: Character match flag.
+ * @arg USART_FLAG_BUSY: Busy flag.
+ * @arg USART_FLAG_ABRF: Auto baud rate flag.
+ * @arg USART_FLAG_ABRE: Auto baud rate error flag.
+ * @arg USART_FLAG_EOBF: End of block flag.
+ * @arg USART_FLAG_RTOF: Receive time out flag.
+ * @arg USART_FLAG_nCTSS: Inverted nCTS input bit status.
+ * @arg USART_FLAG_CTS: CTS Change flag.
+ * @arg USART_FLAG_LBD: LIN Break detection flag.
+ * @arg USART_FLAG_TXE: Transmit data register empty flag.
+ * @arg USART_FLAG_TC: Transmission Complete flag.
+ * @arg USART_FLAG_RXNE: Receive data register not empty flag.
+ * @arg USART_FLAG_IDLE: Idle Line detection flag.
+ * @arg USART_FLAG_ORE: OverRun Error flag.
+ * @arg USART_FLAG_NE: Noise Error flag.
+ * @arg USART_FLAG_FE: Framing Error flag.
+ * @arg USART_FLAG_PE: Parity Error flag.
+ * @retval The new state of USART_FLAG (SET or RESET).
+ */
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_FLAG(USART_FLAG));
+
+ if ((USARTx->ISR & USART_FLAG) != (uint16_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the USARTx's pending flags.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param USART_FLAG: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg USART_FLAG_WUF: Wake up flag.
+ * @arg USART_FLAG_CMF: Character match flag.
+ * @arg USART_FLAG_EOBF: End of block flag.
+ * @arg USART_FLAG_RTOF: Receive time out flag.
+ * @arg USART_FLAG_CTS: CTS Change flag.
+ * @arg USART_FLAG_LBD: LIN Break detection flag.
+ * @arg USART_FLAG_TC: Transmission Complete flag.
+ * @arg USART_FLAG_IDLE: IDLE line detected flag.
+ * @arg USART_FLAG_ORE: OverRun Error flag.
+ * @arg USART_FLAG_NE: Noise Error flag.
+ * @arg USART_FLAG_FE: Framing Error flag.
+ * @arg USART_FLAG_PE: Parity Errorflag.
+ *
+ * @note
+ * - RXNE pending bit is cleared by a read to the USART_RDR register
+ * (USART_ReceiveData()) or by writing 1 to the RXFRQ in the register USART_RQR
+ * (USART_RequestCmd()).
+ * - TC flag can be also cleared by software sequence: a read operation to
+ * USART_SR register (USART_GetFlagStatus()) followed by a write operation
+ * to USART_TDR register (USART_SendData()).
+ * - TXE flag is cleared by a write to the USART_TDR register
+ * (USART_SendData()) or by writing 1 to the TXFRQ in the register USART_RQR
+ * (USART_RequestCmd()).
+ * - SBKF flag is cleared by 1 to the SBKRQ in the register USART_RQR
+ * (USART_RequestCmd()).
+ * @retval None
+ */
+void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
+
+ USARTx->ICR = USART_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified USART interrupt has occurred or not.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param USART_IT: specifies the USART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg USART_IT_WU: Wake up interrupt.
+ * @arg USART_IT_CM: Character match interrupt.
+ * @arg USART_IT_EOB: End of block interrupt.
+ * @arg USART_IT_RTO: Receive time out interrupt.
+ * @arg USART_IT_CTS: CTS change interrupt.
+ * @arg USART_IT_LBD: LIN Break detection interrupt.
+ * @arg USART_IT_TXE: Tansmit Data Register empty interrupt.
+ * @arg USART_IT_TC: Transmission complete interrupt.
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt.
+ * @arg USART_IT_IDLE: Idle line detection interrupt.
+ * @arg USART_IT_ORE: OverRun Error interrupt.
+ * @arg USART_IT_NE: Noise Error interrupt.
+ * @arg USART_IT_FE: Framing Error interrupt.
+ * @arg USART_IT_PE: Parity Error interrupt.
+ * @retval The new state of USART_IT (SET or RESET).
+ */
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT)
+{
+ uint32_t bitpos = 0, itmask = 0, usartreg = 0;
+ ITStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_GET_IT(USART_IT));
+
+ /* Get the USART register index */
+ usartreg = (((uint16_t)USART_IT) >> 0x08);
+ /* Get the interrupt position */
+ itmask = USART_IT & IT_MASK;
+ itmask = (uint32_t)0x01 << itmask;
+
+ if (usartreg == 0x01) /* The IT is in CR1 register */
+ {
+ itmask &= USARTx->CR1;
+ }
+ else if (usartreg == 0x02) /* The IT is in CR2 register */
+ {
+ itmask &= USARTx->CR2;
+ }
+ else /* The IT is in CR3 register */
+ {
+ itmask &= USARTx->CR3;
+ }
+
+ bitpos = USART_IT >> 0x10;
+ bitpos = (uint32_t)0x01 << bitpos;
+ bitpos &= USARTx->ISR;
+ if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the USARTx's interrupt pending bits.
+ * @param USARTx: Select the USART peripheral. This parameter can be one of the
+ * following values: USART1 or USART2 or USART3 or UART4 or UART5.
+ * @param USART_IT: specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg USART_IT_WU: Wake up interrupt.
+ * @arg USART_IT_CM: Character match interrupt.
+ * @arg USART_IT_EOB: End of block interrupt.
+ * @arg USART_IT_RTO: Receive time out interrupt.
+ * @arg USART_IT_CTS: CTS change interrupt.
+ * @arg USART_IT_LBD: LIN Break detection interrupt.
+ * @arg USART_IT_TC: Transmission complete interrupt.
+ * @arg USART_IT_IDLE: IDLE line detected interrupt.
+ * @arg USART_IT_ORE: OverRun Error interrupt.
+ * @arg USART_IT_NE: Noise Error interrupt.
+ * @arg USART_IT_FE: Framing Error interrupt.
+ * @arg USART_IT_PE: Parity Error interrupt.
+ * @note
+ * - RXNE pending bit is cleared by a read to the USART_RDR register
+ * (USART_ReceiveData()) or by writing 1 to the RXFRQ in the register USART_RQR
+ * (USART_RequestCmd()).
+ * - TC pending bit can be also cleared by software sequence: a read
+ * operation to USART_SR register (USART_GetITStatus()) followed by a write
+ * operation to USART_TDR register (USART_SendData()).
+ * - TXE pending bit is cleared by a write to the USART_TDR register
+ * (USART_SendData()) or by writing 1 to the TXFRQ in the register USART_RQR
+ * (USART_RequestCmd()).
+ * @retval None
+ */
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT)
+{
+ uint32_t bitpos = 0, itmask = 0;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_CLEAR_IT(USART_IT));
+
+ bitpos = USART_IT >> 0x10;
+ itmask = ((uint32_t)0x01 << (uint32_t)bitpos);
+ USARTx->ICR = (uint32_t)itmask;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_usart.h Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,617 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_usart.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the USART
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_USART_H
+#define __STM32F30x_USART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup USART
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+
+
+/**
+ * @brief USART Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
+ The baud rate is computed using the following formula:
+ - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
+ - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
+
+ uint32_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref USART_Word_Length */
+
+ uint32_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref USART_Stop_Bits */
+
+ uint32_t USART_Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref USART_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint32_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref USART_Mode */
+
+ uint32_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
+ or disabled.
+ This parameter can be a value of @ref USART_Hardware_Flow_Control*/
+} USART_InitTypeDef;
+
+/**
+ * @brief USART Clock Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
+ This parameter can be a value of @ref USART_Clock */
+
+ uint32_t USART_CPOL; /*!< Specifies the steady state of the serial clock.
+ This parameter can be a value of @ref USART_Clock_Polarity */
+
+ uint32_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref USART_Clock_Phase */
+
+ uint32_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref USART_Last_Bit */
+} USART_ClockInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup USART_Exported_Constants
+ * @{
+ */
+
+#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+ ((PERIPH) == USART2) || \
+ ((PERIPH) == USART3) || \
+ ((PERIPH) == UART4) || \
+ ((PERIPH) == UART5))
+
+#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+ ((PERIPH) == USART2) || \
+ ((PERIPH) == USART3))
+
+#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+ ((PERIPH) == USART2) || \
+ ((PERIPH) == USART3) || \
+ ((PERIPH) == UART4))
+
+
+/** @defgroup USART_Word_Length
+ * @{
+ */
+
+#define USART_WordLength_8b ((uint32_t)0x00000000)
+#define USART_WordLength_9b USART_CR1_M
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
+ ((LENGTH) == USART_WordLength_9b))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Stop_Bits
+ * @{
+ */
+
+#define USART_StopBits_1 ((uint32_t)0x00000000)
+#define USART_StopBits_2 USART_CR2_STOP_1
+#define USART_StopBits_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
+ ((STOPBITS) == USART_StopBits_2) || \
+ ((STOPBITS) == USART_StopBits_1_5))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Parity
+ * @{
+ */
+
+#define USART_Parity_No ((uint32_t)0x00000000)
+#define USART_Parity_Even USART_CR1_PCE
+#define USART_Parity_Odd (USART_CR1_PCE | USART_CR1_PS)
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
+ ((PARITY) == USART_Parity_Even) || \
+ ((PARITY) == USART_Parity_Odd))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Mode
+ * @{
+ */
+
+#define USART_Mode_Rx USART_CR1_RE
+#define USART_Mode_Tx USART_CR1_TE
+#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFFFFFF3) == 0x00) && \
+ ((MODE) != (uint32_t)0x00))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Hardware_Flow_Control
+ * @{
+ */
+
+#define USART_HardwareFlowControl_None ((uint32_t)0x00000000)
+#define USART_HardwareFlowControl_RTS USART_CR3_RTSE
+#define USART_HardwareFlowControl_CTS USART_CR3_CTSE
+#define USART_HardwareFlowControl_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
+ (((CONTROL) == USART_HardwareFlowControl_None) || \
+ ((CONTROL) == USART_HardwareFlowControl_RTS) || \
+ ((CONTROL) == USART_HardwareFlowControl_CTS) || \
+ ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock
+ * @{
+ */
+
+#define USART_Clock_Disable ((uint32_t)0x00000000)
+#define USART_Clock_Enable USART_CR2_CLKEN
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
+ ((CLOCK) == USART_Clock_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock_Polarity
+ * @{
+ */
+
+#define USART_CPOL_Low ((uint32_t)0x00000000)
+#define USART_CPOL_High USART_CR2_CPOL
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock_Phase
+ * @{
+ */
+
+#define USART_CPHA_1Edge ((uint32_t)0x00000000)
+#define USART_CPHA_2Edge USART_CR2_CPHA
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Last_Bit
+ * @{
+ */
+
+#define USART_LastBit_Disable ((uint32_t)0x00000000)
+#define USART_LastBit_Enable USART_CR2_LBCL
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
+ ((LASTBIT) == USART_LastBit_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup USART_DMA_Requests
+ * @{
+ */
+
+#define USART_DMAReq_Tx USART_CR3_DMAT
+#define USART_DMAReq_Rx USART_CR3_DMAR
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint32_t)0xFFFFFF3F) == 0x00) && \
+ ((DMAREQ) != (uint32_t)0x00))
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_DMA_Recception_Error
+ * @{
+ */
+
+#define USART_DMAOnError_Enable ((uint32_t)0x00000000)
+#define USART_DMAOnError_Disable USART_CR3_DDRE
+#define IS_USART_DMAONERROR(DMAERROR) (((DMAERROR) == USART_DMAOnError_Disable)|| \
+ ((DMAERROR) == USART_DMAOnError_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup USART_MuteMode_WakeUp_methods
+ * @{
+ */
+
+#define USART_WakeUp_IdleLine ((uint32_t)0x00000000)
+#define USART_WakeUp_AddressMark USART_CR1_WAKE
+#define IS_USART_MUTEMODE_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
+ ((WAKEUP) == USART_WakeUp_AddressMark))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Address_Detection
+ * @{
+ */
+
+#define USART_AddressLength_4b ((uint32_t)0x00000000)
+#define USART_AddressLength_7b USART_CR2_ADDM7
+#define IS_USART_ADDRESS_DETECTION(ADDRESS) (((ADDRESS) == USART_AddressLength_4b) || \
+ ((ADDRESS) == USART_AddressLength_7b))
+/**
+ * @}
+ */
+
+/** @defgroup USART_StopMode_WakeUp_methods
+ * @{
+ */
+
+#define USART_WakeUpSource_AddressMatch ((uint32_t)0x00000000)
+#define USART_WakeUpSource_StartBit USART_CR3_WUS_1
+#define USART_WakeUpSource_RXNE (uint32_t)(USART_CR3_WUS_0 | USART_CR3_WUS_1)
+#define IS_USART_STOPMODE_WAKEUPSOURCE(SOURCE) (((SOURCE) == USART_WakeUpSource_AddressMatch) || \
+ ((SOURCE) == USART_WakeUpSource_StartBit) || \
+ ((SOURCE) == USART_WakeUpSource_RXNE))
+/**
+ * @}
+ */
+
+/** @defgroup USART_LIN_Break_Detection_Length
+ * @{
+ */
+
+#define USART_LINBreakDetectLength_10b ((uint32_t)0x00000000)
+#define USART_LINBreakDetectLength_11b USART_CR2_LBDL
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
+ (((LENGTH) == USART_LINBreakDetectLength_10b) || \
+ ((LENGTH) == USART_LINBreakDetectLength_11b))
+/**
+ * @}
+ */
+
+/** @defgroup USART_IrDA_Low_Power
+ * @{
+ */
+
+#define USART_IrDAMode_LowPower USART_CR3_IRLP
+#define USART_IrDAMode_Normal ((uint32_t)0x00000000)
+#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
+ ((MODE) == USART_IrDAMode_Normal))
+/**
+ * @}
+ */
+
+/** @defgroup USART_DE_Polarity
+ * @{
+ */
+
+#define USART_DEPolarity_High ((uint32_t)0x00000000)
+#define USART_DEPolarity_Low USART_CR3_DEP
+#define IS_USART_DE_POLARITY(POLARITY) (((POLARITY) == USART_DEPolarity_Low) || \
+ ((POLARITY) == USART_DEPolarity_High))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Inversion_Pins
+ * @{
+ */
+
+#define USART_InvPin_Tx USART_CR2_TXINV
+#define USART_InvPin_Rx USART_CR2_RXINV
+#define IS_USART_INVERSTION_PIN(PIN) ((((PIN) & (uint32_t)0xFFFCFFFF) == 0x00) && \
+ ((PIN) != (uint32_t)0x00))
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_AutoBaudRate_Mode
+ * @{
+ */
+
+#define USART_AutoBaudRate_StartBit ((uint32_t)0x00000000)
+#define USART_AutoBaudRate_FallingEdge USART_CR2_ABRMODE_0
+#define USART_AutoBaudRate_0x7FFrame USART_CR2_ABRMODE_1
+#define USART_AutoBaudRate_0x55Frame (USART_CR2_ABRMODE_0 | USART_CR2_ABRMODE_1)
+#define IS_USART_AUTOBAUDRATE_MODE(MODE) (((MODE) == USART_AutoBaudRate_StartBit) || \
+ ((MODE) == USART_AutoBaudRate_FallingEdge) || \
+ ((MODE) == USART_AutoBaudRate_0x7FFrame) || \
+ ((MODE) == USART_AutoBaudRate_0x55Frame))
+/**
+ * @}
+ */
+
+/** @defgroup USART_OVR_DETECTION
+ * @{
+ */
+
+#define USART_OVRDetection_Enable ((uint32_t)0x00000000)
+#define USART_OVRDetection_Disable USART_CR3_OVRDIS
+#define IS_USART_OVRDETECTION(OVR) (((OVR) == USART_OVRDetection_Enable)|| \
+ ((OVR) == USART_OVRDetection_Disable))
+/**
+ * @}
+ */
+/** @defgroup USART_Request
+ * @{
+ */
+
+#define USART_Request_ABRRQ USART_RQR_ABRRQ
+#define USART_Request_SBKRQ USART_RQR_SBKRQ
+#define USART_Request_MMRQ USART_RQR_MMRQ
+#define USART_Request_RXFRQ USART_RQR_RXFRQ
+#define USART_Request_TXFRQ USART_RQR_TXFRQ
+
+#define IS_USART_REQUEST(REQUEST) (((REQUEST) == USART_Request_TXFRQ) || \
+ ((REQUEST) == USART_Request_RXFRQ) || \
+ ((REQUEST) == USART_Request_MMRQ) || \
+ ((REQUEST) == USART_Request_SBKRQ) || \
+ ((REQUEST) == USART_Request_ABRRQ))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Flags
+ * @{
+ */
+#define USART_FLAG_REACK USART_ISR_REACK
+#define USART_FLAG_TEACK USART_ISR_TEACK
+#define USART_FLAG_WU USART_ISR_WUF
+#define USART_FLAG_RWU USART_ISR_RWU
+#define USART_FLAG_SBK USART_ISR_SBKF
+#define USART_FLAG_CM USART_ISR_CMF
+#define USART_FLAG_BUSY USART_ISR_BUSY
+#define USART_FLAG_ABRF USART_ISR_ABRF
+#define USART_FLAG_ABRE USART_ISR_ABRE
+#define USART_FLAG_EOB USART_ISR_EOBF
+#define USART_FLAG_RTO USART_ISR_RTOF
+#define USART_FLAG_nCTSS USART_ISR_CTS
+#define USART_FLAG_CTS USART_ISR_CTSIF
+#define USART_FLAG_LBD USART_ISR_LBD
+#define USART_FLAG_TXE USART_ISR_TXE
+#define USART_FLAG_TC USART_ISR_TC
+#define USART_FLAG_RXNE USART_ISR_RXNE
+#define USART_FLAG_IDLE USART_ISR_IDLE
+#define USART_FLAG_ORE USART_ISR_ORE
+#define USART_FLAG_NE USART_ISR_NE
+#define USART_FLAG_FE USART_ISR_FE
+#define USART_FLAG_PE USART_ISR_PE
+#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
+ ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
+ ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
+ ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
+ ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
+ ((FLAG) == USART_FLAG_nCTSS) || ((FLAG) == USART_FLAG_RTO) || \
+ ((FLAG) == USART_FLAG_EOB) || ((FLAG) == USART_FLAG_ABRE) || \
+ ((FLAG) == USART_FLAG_ABRF) || ((FLAG) == USART_FLAG_BUSY) || \
+ ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_SBK) || \
+ ((FLAG) == USART_FLAG_RWU) || ((FLAG) == USART_FLAG_WU) || \
+ ((FLAG) == USART_FLAG_TEACK)|| ((FLAG) == USART_FLAG_REACK))
+
+#define IS_USART_CLEAR_FLAG(FLAG) (((FLAG) == USART_FLAG_WU) || ((FLAG) == USART_FLAG_TC) || \
+ ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_ORE) || \
+ ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
+ ((FLAG) == USART_FLAG_LBD) || ((FLAG) == USART_FLAG_CTS) || \
+ ((FLAG) == USART_FLAG_RTO) || ((FLAG) == USART_FLAG_EOB) || \
+ ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_PE))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Interrupt_definition
+ * @brief USART Interrupt definition
+ * USART_IT possible values
+ * Elements values convention: 0xZZZZYYXX
+ * XX: Position of the corresponding Interrupt
+ * YY: Register index
+ * ZZZZ: Flag position
+ * @{
+ */
+
+#define USART_IT_WU ((uint32_t)0x00140316)
+#define USART_IT_CM ((uint32_t)0x0011010E)
+#define USART_IT_EOB ((uint32_t)0x000C011B)
+#define USART_IT_RTO ((uint32_t)0x000B011A)
+#define USART_IT_PE ((uint32_t)0x00000108)
+#define USART_IT_TXE ((uint32_t)0x00070107)
+#define USART_IT_TC ((uint32_t)0x00060106)
+#define USART_IT_RXNE ((uint32_t)0x00050105)
+#define USART_IT_IDLE ((uint32_t)0x00040104)
+#define USART_IT_LBD ((uint32_t)0x00080206)
+#define USART_IT_CTS ((uint32_t)0x0009030A)
+#define USART_IT_ERR ((uint32_t)0x00000300)
+#define USART_IT_ORE ((uint32_t)0x00030300)
+#define USART_IT_NE ((uint32_t)0x00020300)
+#define USART_IT_FE ((uint32_t)0x00010300)
+
+#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR) || \
+ ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
+ ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
+
+#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
+ ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE) || \
+ ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
+ ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
+
+#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_PE) || \
+ ((IT) == USART_IT_FE) || ((IT) == USART_IT_NE) || \
+ ((IT) == USART_IT_ORE) || ((IT) == USART_IT_IDLE) || \
+ ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS) || \
+ ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
+ ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Global_definition
+ * @{
+ */
+
+#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x005B8D81))
+#define IS_USART_DE_ASSERTION_DEASSERTION_TIME(TIME) ((TIME) <= 0x1F)
+#define IS_USART_AUTO_RETRY_COUNTER(COUNTER) ((COUNTER) <= 0x7)
+#define IS_USART_TIMEOUT(TIMEOUT) ((TIMEOUT) <= 0x00FFFFFF)
+#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Initialization and Configuration functions *********************************/
+void USART_DeInit(USART_TypeDef* USARTx);
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState);
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState);
+void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut);
+
+/* STOP Mode functions ********************************************************/
+void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource);
+
+/* AutoBaudRate functions *****************************************************/
+void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate);
+
+/* Data transfers functions ***************************************************/
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
+
+/* Multi-Processor Communication functions ************************************/
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
+void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp);
+void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength);
+/* LIN mode functions *********************************************************/
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength);
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
+/* Half-duplex mode function **************************************************/
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
+/* Smartcard mode functions ***************************************************/
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
+void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount);
+void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength);
+
+/* IrDA mode functions ********************************************************/
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode);
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
+/* RS485 mode functions *******************************************************/
+void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity);
+void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime);
+void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime);
+
+/* DMA transfers management functions *****************************************/
+void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState);
+void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError);
+
+/* Interrupts and flags management functions **********************************/
+void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState);
+void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState);
+void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection);
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG);
+void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG);
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT);
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F30x_USART_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_wwdg.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,314 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_wwdg.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Window watchdog (WWDG) peripheral:
+ * + Prescaler, Refresh window and Counter configuration
+ * + WWDG activation
+ * + Interrupts and flags management
+ *
+ * @verbatim
+ *
+ ==============================================================================
+ ##### WWDG features #####
+ ==============================================================================
+
+ [..] Once enabled the WWDG generates a system reset on expiry of a programmed
+ time period, unless the program refreshes the counter (downcounter)
+ before to reach 0x3F value (i.e. a reset is generated when the counter
+ value rolls over from 0x40 to 0x3F).
+ [..] An MCU reset is also generated if the counter value is refreshed
+ before the counter has reached the refresh window value. This
+ implies that the counter must be refreshed in a limited window.
+
+ [..] Once enabled the WWDG cannot be disabled except by a system reset.
+
+ [..] WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
+ reset occurs.
+
+ [..] The WWDG counter input clock is derived from the APB clock divided
+ by a programmable prescaler.
+
+ [..] WWDG counter clock = PCLK1 / Prescaler.
+ [..] WWDG timeout = (WWDG counter clock) * (counter value).
+
+ [..] Min-max timeout value @36MHz (PCLK1): ~114us / ~58.3ms.
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE)
+ function.
+
+ (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function.
+
+ (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function.
+
+ (#) Set the WWDG counter value and start it using WWDG_Enable() function.
+ When the WWDG is enabled the counter value should be configured to
+ a value greater than 0x40 to prevent generating an immediate reset.
+
+ (#) Optionally you can enable the Early wakeup interrupt which is
+ generated when the counter reach 0x40.
+ Once enabled this interrupt cannot be disabled except by a system reset.
+
+ (#) Then the application program must refresh the WWDG counter at regular
+ intervals during normal operation to prevent an MCU reset, using
+ WWDG_SetCounter() function. This operation must occur only when
+ the counter value is lower than the refresh window value,
+ programmed using WWDG_SetWindowValue().
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_wwdg.h"
+#include "stm32f30x_rcc.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup WWDG
+ * @brief WWDG driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* --------------------- WWDG registers bit mask ---------------------------- */
+/* CFR register bit mask */
+#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F)
+#define CFR_W_MASK ((uint32_t)0xFFFFFF80)
+#define BIT_MASK ((uint8_t)0x7F)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup WWDG_Private_Functions
+ * @{
+ */
+
+/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions
+ * @brief Prescaler, Refresh window and Counter configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Prescaler, Refresh window and Counter configuration functions #####
+ ==============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the WWDG peripheral registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void WWDG_DeInit(void)
+{
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
+}
+
+/**
+ * @brief Sets the WWDG Prescaler.
+ * @param WWDG_Prescaler: specifies the WWDG Prescaler.
+ * This parameter can be one of the following values:
+ * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
+ * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
+ * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
+ * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
+ * @retval None
+ */
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
+ /* Clear WDGTB[1:0] bits */
+ tmpreg = WWDG->CFR & CFR_WDGTB_MASK;
+ /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
+ tmpreg |= WWDG_Prescaler;
+ /* Store the new value */
+ WWDG->CFR = tmpreg;
+}
+
+/**
+ * @brief Sets the WWDG window value.
+ * @param WindowValue: specifies the window value to be compared to the downcounter.
+ * This parameter value must be lower than 0x80.
+ * @retval None
+ */
+void WWDG_SetWindowValue(uint8_t WindowValue)
+{
+ __IO uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
+ /* Clear W[6:0] bits */
+
+ tmpreg = WWDG->CFR & CFR_W_MASK;
+
+ /* Set W[6:0] bits according to WindowValue value */
+ tmpreg |= WindowValue & (uint32_t) BIT_MASK;
+
+ /* Store the new value */
+ WWDG->CFR = tmpreg;
+}
+
+/**
+ * @brief Enables the WWDG Early Wakeup interrupt(EWI).
+ * @note Once enabled this interrupt cannot be disabled except by a system reset.
+ * @param None
+ * @retval None
+ */
+void WWDG_EnableIT(void)
+{
+ WWDG->CFR |= WWDG_CFR_EWI;
+}
+
+/**
+ * @brief Sets the WWDG counter value.
+ * @param Counter: specifies the watchdog counter value.
+ * This parameter must be a number between 0x40 and 0x7F (to prevent generating
+ * an immediate reset).
+ * @retval None
+ */
+void WWDG_SetCounter(uint8_t Counter)
+{
+ /* Check the parameters */
+ assert_param(IS_WWDG_COUNTER(Counter));
+ /* Write to T[6:0] bits to configure the counter value, no need to do
+ a read-modify-write; writing a 0 to WDGA bit does nothing */
+ WWDG->CR = Counter & BIT_MASK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Group2 WWDG activation functions
+ * @brief WWDG activation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### WWDG activation function #####
+ ==============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables WWDG and load the counter value.
+ * @param Counter: specifies the watchdog counter value.
+ * This parameter must be a number between 0x40 and 0x7F (to prevent generating
+ * an immediate reset).
+ * @retval None
+ */
+void WWDG_Enable(uint8_t Counter)
+{
+ /* Check the parameters */
+ assert_param(IS_WWDG_COUNTER(Counter));
+ WWDG->CR = WWDG_CR_WDGA | Counter;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Group3 Interrupts and flags management functions
+ * @brief Interrupts and flags management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Interrupts and flags management functions #####
+ ==============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Checks whether the Early Wakeup interrupt flag is set or not.
+ * @param None
+ * @retval The new state of the Early Wakeup interrupt flag (SET or RESET).
+ */
+FlagStatus WWDG_GetFlagStatus(void)
+{
+ FlagStatus bitstatus = RESET;
+
+ if ((WWDG->SR) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears Early Wakeup interrupt flag.
+ * @param None
+ * @retval None
+ */
+void WWDG_ClearFlag(void)
+{
+ WWDG->SR = (uint32_t)RESET;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_wwdg.h Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,119 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_wwdg.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the WWDG
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_WWDG_H
+#define __STM32F30x_WWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup WWDG
+ * @{
+ */
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Constants
+ * @{
+ */
+
+/** @defgroup WWDG_Prescaler
+ * @{
+ */
+
+#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
+#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
+#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
+#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
+#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
+ ((PRESCALER) == WWDG_Prescaler_2) || \
+ ((PRESCALER) == WWDG_Prescaler_4) || \
+ ((PRESCALER) == WWDG_Prescaler_8))
+#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
+#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* Function used to set the WWDG configuration to the default reset state ****/
+void WWDG_DeInit(void);
+
+/* Prescaler, Refresh window and Counter configuration functions **************/
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
+void WWDG_SetWindowValue(uint8_t WindowValue);
+void WWDG_EnableIT(void);
+void WWDG_SetCounter(uint8_t Counter);
+
+/* WWDG activation functions **************************************************/
+void WWDG_Enable(uint8_t Counter);
+
+/* Interrupts and flags management functions **********************************/
+FlagStatus WWDG_GetFlagStatus(void);
+void WWDG_ClearFlag(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F30x_WWDG_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/system_stm32f30x.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,478 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f30x.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 05-March-2014
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+ * This file contains the system clock configuration for STM32F30x devices,
+ * and is generated by the clock configuration tool
+ * stm32f30x_Clock_Configuration_V1.0.0.xls
+ *
+ * 1. This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+ * and Divider factors, AHB/APBx prescalers and Flash settings),
+ * depending on the configuration made in the clock xls tool.
+ * This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f30x.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32f30x.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * 3. If the system clock source selected by user fails to startup, the SystemInit()
+ * function will do nothing and HSI still used as system clock source. User can
+ * add some code to deal with this issue inside the SetSysClock() function.
+ *
+ * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
+ * in "stm32f30x.h" file. When HSE is used as system clock source, directly or
+ * through PLL, and you are using different crystal you have to adapt the HSE
+ * value to your own configuration.
+ *
+ * 5. This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------
+ * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
+ * | (external 8 MHz clock) | (internal 8 MHz)
+ * | 2- PLL_HSE_XTAL |
+ * | (external 8 MHz xtal) |
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 72 | 64
+ *-----------------------------------------------------------------------------
+ * AHBCLK (MHz) | 72 | 64
+ *-----------------------------------------------------------------------------
+ * APB1CLK (MHz) | 36 | 32
+ *-----------------------------------------------------------------------------
+ * APB2CLK (MHz) | 72 | 64
+ *-----------------------------------------------------------------------------
+ * USB capable (48 MHz precise clock) | YES | NO
+ *-----------------------------------------------------------------------------
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f30x_system
+ * @{
+ */
+
+/** @addtogroup STM32F30x_System_Private_Includes
+ * @{
+ */
+
+#include "stm32f30x.h"
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F30x_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F30x_System_Private_Defines
+ * @{
+ */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F30x_System_Private_Macros
+ * @{
+ */
+
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (1) /* Use external clock */
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F30x_System_Private_Variables
+ * @{
+ */
+
+uint32_t SystemCoreClock = 64000000; /* Default with HSI. Will be updated if HSE is used */
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F30x_System_Private_FunctionPrototypes
+ * @{
+ */
+
+void SetSysClock(void);
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F30x_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the Embedded Flash Interface, the PLL and update the
+ * SystemFrequency variable.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+ #endif
+
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR &= 0xF87FC00C;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+ /* Reset PREDIV1[3:0] bits */
+ RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+ /* Reset USARTSW[1:0], I2CSW and TIMs bits */
+ RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+ /* Configure the System clock source, PLL Multiplier and Divider factors,
+ AHB/APBx prescalers and Flash settings */
+ SetSysClock();
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x04: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x08: /* PLL used as system clock */
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+ pllmull = ( pllmull >> 18) + 2;
+
+ if (pllsource == 0x00)
+ {
+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
+ }
+ break;
+ default: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+ /* Compute HCLK clock frequency ----------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+void SetSysClock(void)
+{
+ /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+ /* 2- If fail try to start with HSE and external xtal */
+ #if USE_PLL_HSE_XTAL != 0
+ if (SetSysClock_PLL_HSE(0) == 0)
+ #endif
+ {
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+ {
+ while(1)
+ {
+ // [TODO] Put something here to tell the user that a problem occured...
+ }
+ }
+ }
+ }
+
+ /* Output SYSCLK on MCO pin(PA8) for debugging purpose */
+ /*
+ // Enable GPIOA clock
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
+ // Configure MCO pin (PA8)
+ GPIO_InitTypeDef GPIO_InitStructure;
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+ GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+ GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+ GPIO_Init(GPIOA, &GPIO_InitStructure);
+ // Select the clock to output
+ RCC_MCOConfig(RCC_MCOSource_SYSCLK, RCC_MCOPrescaler_1);
+ */
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ __IO uint32_t StartUpCounter = 0;
+ __IO uint32_t HSEStatus = 0;
+
+ /* Bypass HSE: can be done only if HSE is OFF */
+ RCC->CR &= ((uint32_t)~RCC_CR_HSEON); /* To be sure HSE is OFF */
+ if (bypass != 0)
+ {
+ RCC->CR |= ((uint32_t)RCC_CR_HSEBYP);
+ }
+ else
+ {
+ RCC->CR &= ((uint32_t)~RCC_CR_HSEBYP);
+ }
+
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ /* Check if HSE has started correctly */
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ /* Enable prefetch buffer and set flash latency
+ 0WS for 0 < SYSCLK <= 24 MHz
+ 1WS for 24 < SYSCLK <= 48 MHz
+ 2WS for 48 < SYSCLK <= 72 MHz */
+ FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1; /* 2 WS */
+
+ /* Warning: values are obtained with external xtal or clock = 8 MHz */
+ /* SYSCLK = 72 MHz (8 MHz * 9) */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9
+ | RCC_CFGR_HPRE_DIV1 /* HCLK = 72 MHz */
+ | RCC_CFGR_PPRE2_DIV1 /* PCLK2 = 72 MHz */
+ | RCC_CFGR_PPRE1_DIV2); /* PCLK1 = 36 MHz */
+ /* USBCLK = 48 MHz (72 MHz / 1.5) --> USB OK */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+ {
+ }
+
+ return 1; // OK
+ }
+ else
+ {
+ return 0; // FAIL
+ }
+}
+#endif
+
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ /* At this stage the HSI is already enabled and used as System clock source */
+
+ /* Enable prefetch buffer and set flash latency
+ 0WS for 0 < SYSCLK <= 24 MHz
+ 1WS for 24 < SYSCLK <= 48 MHz
+ 2WS for 48 < SYSCLK <= 72 MHz */
+ FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1; /* 2 WS */
+
+ /* SYSCLK = 64 MHz (8 MHz / 2 * 16) */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL16
+ | RCC_CFGR_HPRE_DIV1 /* HCLK = 64 MHz */
+ | RCC_CFGR_PPRE2_DIV1 /* PCLK2 = 64 MHz */
+ | RCC_CFGR_PPRE1_DIV2); /* PCLK1 = 32 MHz */
+ /* USBCLK = 42.667 MHz (64 MHz / 1.5) --> USB NOT POSSIBLE */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+ {
+ }
+
+ return 1; // OK
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/system_stm32f30x.h Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,86 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f30x.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief CMSIS Cortex-M4 Device System Source File for STM32F30x devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f30x_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F30X_H
+#define __SYSTEM_STM32F30X_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/** @addtogroup STM32F30x_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F30X_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F3XX/PeripheralNames.h Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,79 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE
+} ADCName;
+
+typedef enum {
+ DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_3 = (int)USART3_BASE
+} UARTName;
+
+#define STDIO_UART_TX PA_2
+#define STDIO_UART_RX PA_3
+#define STDIO_UART UART_2
+
+typedef enum {
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_15 = (int)TIM15_BASE,
+ PWM_16 = (int)TIM16_BASE,
+ PWM_17 = (int)TIM17_BASE
+} PWMName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F3XX/PinNames.h Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,180 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// MODE (see GPIOMode_TypeDef structure)
+// OTYPE (see GPIOOType_TypeDef structure)
+// PUPD (see GPIOPuPd_TypeDef structure)
+// AFNUM (see AF_mapping constant table, 0xFF is not used)
+#define STM_PIN_DATA(MODE, OTYPE, PUPD, AFNUM) (((AFNUM)<<8)|((PUPD)<<4)|((OTYPE)<<2)|((MODE)<<0))
+#define STM_PIN_MODE(X) (((X)>>0) & 0x3)
+#define STM_PIN_OTYPE(X) (((X)>>2) & 0x1)
+#define STM_PIN_PUPD(X) (((X)>>4) & 0x3)
+#define STM_PIN_AFNUM(X) (((X)>>8) & 0xF)
+
+// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
+// Low nibble = pin number
+#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
+#define STM_PIN(X) ((uint32_t)(X) & 0xF)
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_1 = 0x01,
+ PA_2 = 0x02,
+ PA_3 = 0x03,
+ PA_4 = 0x04,
+ PA_5 = 0x05,
+ PA_6 = 0x06,
+ PA_7 = 0x07,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+
+ PB_0 = 0x10,
+ PB_1 = 0x11,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_4 = 0x14,
+ PB_5 = 0x15,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_9 = 0x19,
+ PB_10 = 0x1A,
+ PB_11 = 0x1B,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_15 = 0x1F,
+
+ PC_0 = 0x20,
+ PC_1 = 0x21,
+ PC_2 = 0x22,
+ PC_3 = 0x23,
+ PC_4 = 0x24,
+ PC_5 = 0x25,
+ PC_6 = 0x26,
+ PC_7 = 0x27,
+ PC_8 = 0x28,
+ PC_9 = 0x29,
+ PC_10 = 0x2A,
+ PC_11 = 0x2B,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_0 = 0x30,
+ PD_1 = 0x31,
+ PD_2 = 0x32,
+ PD_3 = 0x33,
+ PD_4 = 0x34,
+ PD_5 = 0x35,
+ PD_6 = 0x36,
+ PD_7 = 0x37,
+ PD_8 = 0x38,
+ PD_9 = 0x39,
+ PD_10 = 0x3A,
+ PD_11 = 0x3B,
+ PD_12 = 0x3C,
+ PD_13 = 0x3D,
+ PD_14 = 0x3E,
+ PD_15 = 0x3F,
+
+ PE_0 = 0x40,
+ PE_1 = 0x41,
+ PE_2 = 0x42,
+ PE_3 = 0x43,
+ PE_4 = 0x44,
+ PE_5 = 0x45,
+ PE_6 = 0x46,
+ PE_7 = 0x47,
+ PE_8 = 0x48,
+ PE_9 = 0x49,
+ PE_10 = 0x4A,
+ PE_11 = 0x4B,
+ PE_12 = 0x4C,
+ PE_13 = 0x4D,
+ PE_14 = 0x4E,
+ PE_15 = 0x4F,
+
+ PF_0 = 0x50,
+ PF_1 = 0x51,
+ PF_2 = 0x52,
+ PF_3 = 0x53,
+ PF_4 = 0x54,
+ PF_5 = 0x55,
+ PF_6 = 0x56,
+ PF_7 = 0x57,
+ PF_8 = 0x58,
+ PF_9 = 0x59,
+ PF_10 = 0x5A,
+ PF_11 = 0x5B,
+ PF_12 = 0x5C,
+ PF_13 = 0x5D,
+ PF_14 = 0x5E,
+ PF_15 = 0x5F,
+
+ LED1 = PE_9,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+ PullNone = 0,
+ PullUp = 1,
+ PullDown = 2,
+ OpenDrain = 3,
+ PullDefault = PullNone
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F3XX/PortNames.h Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,49 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PortA = 0,
+ PortB = 1,
+ PortC = 2,
+ PortD = 3,
+ PortE = 4,
+ PortF = 5
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F3XX/analogin_api.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,194 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "analogin_api.h"
+#include "wait_api.h"
+
+#if DEVICE_ANALOGIN
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+static const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN1
+ {PA_1, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN2
+ {PA_2, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN3
+ {PA_3, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN4
+ {PA_4, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN5
+ {PC_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN6
+ {PC_1, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN7
+ {PC_2, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN8
+ {PC_3, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN9
+ {PA_6, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN10
+ {PB_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN11
+ {PB_1, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN12
+ {PB_13, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN13
+ {PB_11, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN14
+ {PA_7, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN15
+ {NC, NC, 0}
+};
+
+int adc_inited = 0;
+
+void analogin_init(analogin_t *obj, PinName pin) {
+
+ ADC_TypeDef *adc;
+ ADC_InitTypeDef ADC_InitStructure;
+ ADC_CommonInitTypeDef ADC_CommonInitStructure;
+
+ // Get the peripheral name from the pin and assign it to the object
+ obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+
+ if (obj->adc == (ADCName)NC) {
+ error("ADC pin mapping failed");
+ }
+
+ // Configure GPIO
+ pinmap_pinout(pin, PinMap_ADC);
+
+ // Save pin number for the read function
+ obj->pin = pin;
+
+ // The ADC initialization is done once
+ if (adc_inited == 0) {
+ adc_inited = 1;
+
+ // Get ADC registers structure address
+ adc = (ADC_TypeDef *)(obj->adc);
+
+ // Enable ADC clock
+ RCC_ADCCLKConfig(RCC_ADC12PLLCLK_Div1);
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_ADC12, ENABLE);
+
+ // Calibration
+ ADC_VoltageRegulatorCmd(adc, ENABLE);
+ wait_us(10);
+ ADC_SelectCalibrationMode(adc, ADC_CalibrationMode_Single);
+ ADC_StartCalibration(adc);
+ while (ADC_GetCalibrationStatus(adc) != RESET) {}
+
+ // Configure ADC
+ ADC_CommonInitStructure.ADC_Mode = ADC_Mode_Independent;
+ ADC_CommonInitStructure.ADC_Clock = ADC_Clock_AsynClkMode;
+ ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;
+ ADC_CommonInitStructure.ADC_DMAMode = ADC_DMAMode_OneShot;
+ ADC_CommonInitStructure.ADC_TwoSamplingDelay = 0;
+ ADC_CommonInit(adc, &ADC_CommonInitStructure);
+
+ ADC_InitStructure.ADC_ContinuousConvMode = ADC_ContinuousConvMode_Disable;
+ ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b;
+ ADC_InitStructure.ADC_ExternalTrigConvEvent = ADC_ExternalTrigConvEvent_0;
+ ADC_InitStructure.ADC_ExternalTrigEventEdge = ADC_ExternalTrigEventEdge_None;
+ ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
+ ADC_InitStructure.ADC_OverrunMode = ADC_OverrunMode_Disable;
+ ADC_InitStructure.ADC_AutoInjMode = ADC_AutoInjec_Disable;
+ ADC_InitStructure.ADC_NbrOfRegChannel = 1;
+ ADC_Init(adc, &ADC_InitStructure);
+
+ // Enable ADC
+ ADC_Cmd(adc, ENABLE);
+
+ while (!ADC_GetFlagStatus(adc, ADC_FLAG_RDY)) {}
+ }
+}
+
+static inline uint16_t adc_read(analogin_t *obj) {
+ // Get ADC registers structure address
+ ADC_TypeDef *adc = (ADC_TypeDef *)(obj->adc);
+ uint8_t channel = 0;
+
+ // Configure ADC channel
+ switch (obj->pin) {
+ case PA_0:
+ channel = ADC_Channel_1;
+ break;
+ case PA_1:
+ channel = ADC_Channel_2;
+ break;
+ case PA_2:
+ channel = ADC_Channel_3;
+ break;
+ case PA_3:
+ channel = ADC_Channel_4;
+ break;
+ case PA_4:
+ channel = ADC_Channel_5;
+ break;
+ case PC_0:
+ channel = ADC_Channel_6;
+ break;
+ case PC_1:
+ channel = ADC_Channel_7;
+ break;
+ case PC_2:
+ channel = ADC_Channel_8;
+ break;
+ case PC_3:
+ channel = ADC_Channel_9;
+ break;
+ case PA_6:
+ channel = ADC_Channel_10;
+ break;
+ case PB_0:
+ channel = ADC_Channel_11;
+ break;
+ case PB_1:
+ channel = ADC_Channel_12;
+ break;
+ case PB_13:
+ channel = ADC_Channel_13;
+ break;
+ case PB_11:
+ channel = ADC_Channel_14;
+ break;
+ case PA_7:
+ channel = ADC_Channel_15;
+ break;
+ default:
+ return 0;
+ }
+
+ ADC_RegularChannelConfig(adc, channel, 1, ADC_SampleTime_7Cycles5);
+
+ ADC_StartConversion(adc); // Start conversion
+
+ while (ADC_GetFlagStatus(adc, ADC_FLAG_EOC) == RESET); // Wait end of conversion
+
+ return (ADC_GetConversionValue(adc)); // Get conversion value
+}
+
+uint16_t analogin_read_u16(analogin_t *obj) {
+ return (adc_read(obj));
+}
+
+float analogin_read(analogin_t *obj) {
+ uint16_t value = adc_read(obj);
+ return (float)value * (1.0f / (float)0xFFF); // 12 bits range
+}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F3XX/analogout_api.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,113 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "analogout_api.h"
+
+#if DEVICE_ANALOGOUT
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+#define RANGE_12BIT (0xFFF)
+
+static const PinMap PinMap_DAC[] = {
+ {PA_4, DAC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // DAC_OUT1
+ {NC, NC, 0}
+};
+
+void analogout_init(dac_t *obj, PinName pin) {
+ DAC_TypeDef *dac;
+ DAC_InitTypeDef DAC_InitStructure;
+
+ // Get the peripheral name (DAC_1, ...) from the pin and assign it to the object
+ obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC);
+
+ if (obj->dac == (DACName)NC) {
+ error("DAC pin mapping failed");
+ }
+
+ dac = (DAC_TypeDef *)(obj->dac);
+
+ // Configure GPIO
+ pinmap_pinout(pin, PinMap_DAC);
+
+ // Save the channel for the write and read functions
+ obj->channel = pin;
+
+ // Enable DAC clock
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE);
+
+ // Configure and enable DAC channel
+ DAC_StructInit(&DAC_InitStructure);
+ DAC_Init(dac, DAC_Channel_1, &DAC_InitStructure);
+ DAC_Cmd(dac, DAC_Channel_1, ENABLE);
+
+ analogout_write_u16(obj, 0);
+}
+
+void analogout_free(dac_t *obj) {
+}
+
+static inline void dac_write(dac_t *obj, uint16_t value) {
+ DAC_TypeDef *dac = (DAC_TypeDef *)(obj->dac);
+ DAC_SetChannel1Data(dac, DAC_Align_12b_R, value);
+}
+
+static inline int dac_read(dac_t *obj) {
+ DAC_TypeDef *dac = (DAC_TypeDef *)(obj->dac);
+ return (int)DAC_GetDataOutputValue(dac, DAC_Channel_1);
+}
+
+void analogout_write(dac_t *obj, float value) {
+ if (value < 0.0f) {
+ dac_write(obj, 0); // Min value
+ } else if (value > 1.0f) {
+ dac_write(obj, (uint16_t)RANGE_12BIT); // Max value
+ } else {
+ dac_write(obj, (uint16_t)(value * (float)RANGE_12BIT));
+ }
+}
+
+void analogout_write_u16(dac_t *obj, uint16_t value) {
+ if (value > (uint16_t)RANGE_12BIT) {
+ dac_write(obj, (uint16_t)RANGE_12BIT); // Max value
+ } else {
+ dac_write(obj, value);
+ }
+}
+
+float analogout_read(dac_t *obj) {
+ uint32_t value = dac_read(obj);
+ return (float)value * (1.0f / (float)RANGE_12BIT);
+}
+
+uint16_t analogout_read_u16(dac_t *obj) {
+ return (uint16_t)dac_read(obj);
+}
+
+#endif // DEVICE_ANALOGOUT
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_STM/TARGET_STM32F3XX/device.h Tue Apr 08 09:15:06 2014 +0100 @@ -0,0 +1,71 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 1 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 0 // Not yet supported + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 0 // Not yet supported + +#define DEVICE_RTC 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SLEEP 1 + +//======================================= + +#define DEVICE_SEMIHOST 0 + +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_RED 0 + +#include "objects.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F3XX/gpio_api.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,71 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "gpio_api.h"
+#include "pinmap.h"
+#include "error.h"
+
+extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
+
+uint32_t gpio_set(PinName pin) {
+ if (pin == NC) return 0;
+
+ pin_function(pin, STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0xFF));
+
+ return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask
+}
+
+void gpio_init(gpio_t *obj, PinName pin) {
+ if (pin == NC) return;
+
+ uint32_t port_index = STM_PORT(pin);
+
+ // Enable GPIO clock
+ uint32_t gpio_add = Set_GPIO_Clock(port_index);
+ GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
+
+ // Fill GPIO object structure for future use
+ obj->pin = pin;
+ obj->mask = gpio_set(pin);
+ obj->reg_in = &gpio->IDR;
+ obj->reg_set = &gpio->BSRR;
+ obj->reg_clr = &gpio->BRR;
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode) {
+ pin_mode(obj->pin, mode);
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction) {
+ if (direction == PIN_OUTPUT) {
+ pin_function(obj->pin, STM_PIN_DATA(GPIO_Mode_OUT, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF));
+ } else { // PIN_INPUT
+ pin_function(obj->pin, STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0xFF));
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F3XX/gpio_irq_api.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,255 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include <stddef.h>
+#include "cmsis.h"
+
+#include "gpio_irq_api.h"
+#include "pinmap.h"
+#include "error.h"
+
+#define EDGE_NONE (0)
+#define EDGE_RISE (1)
+#define EDGE_FALL (2)
+#define EDGE_BOTH (3)
+
+#define CHANNEL_NUM (7)
+
+static uint32_t channel_ids[CHANNEL_NUM] = {0, 0, 0, 0, 0, 0, 0};
+static uint32_t channel_gpio[CHANNEL_NUM] = {0, 0, 0, 0, 0, 0, 0};
+static uint32_t channel_pin[CHANNEL_NUM] = {0, 0, 0, 0, 0, 0, 0};
+
+static gpio_irq_handler irq_handler;
+
+static void handle_interrupt_in(uint32_t irq_index) {
+ // Retrieve the gpio and pin that generate the irq
+ GPIO_TypeDef *gpio = (GPIO_TypeDef *)(channel_gpio[irq_index]);
+ uint32_t pin = (uint32_t)(1 << channel_pin[irq_index]);
+
+ // Clear interrupt flag
+ if (EXTI_GetITStatus(channel_pin[irq_index]) != RESET) {
+ EXTI_ClearITPendingBit(channel_pin[irq_index]);
+ }
+
+ if (channel_ids[irq_index] == 0) return;
+
+ // Check which edge has generated the irq
+ if ((gpio->IDR & pin) == 0) {
+ irq_handler(channel_ids[irq_index], IRQ_FALL);
+ } else {
+ irq_handler(channel_ids[irq_index], IRQ_RISE);
+ }
+}
+
+static void gpio_irq0(void) {
+ handle_interrupt_in(0); // EXTI line 0
+}
+
+static void gpio_irq1(void) {
+ handle_interrupt_in(1); // EXTI line 1
+}
+
+static void gpio_irq2(void) {
+ handle_interrupt_in(2); // EXTI line 2
+}
+
+static void gpio_irq3(void) {
+ handle_interrupt_in(3); // EXTI line 3
+}
+
+static void gpio_irq4(void) {
+ handle_interrupt_in(4); // EXTI line 4
+}
+
+static void gpio_irq5(void) {
+ handle_interrupt_in(5); // EXTI lines 5 to 9
+}
+
+static void gpio_irq6(void) {
+ handle_interrupt_in(6); // EXTI lines 10 to 15
+}
+
+extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
+ IRQn_Type irq_n = (IRQn_Type)0;
+ uint32_t vector = 0;
+ uint32_t irq_index;
+
+ if (pin == NC) return -1;
+
+ uint32_t port_index = STM_PORT(pin);
+ uint32_t pin_index = STM_PIN(pin);
+
+ // Select irq number and interrupt routine
+ switch (pin_index) {
+ case 0:
+ irq_n = EXTI0_IRQn;
+ vector = (uint32_t)&gpio_irq0;
+ irq_index = 0;
+ break;
+ case 1:
+ irq_n = EXTI1_IRQn;
+ vector = (uint32_t)&gpio_irq1;
+ irq_index = 1;
+ break;
+ case 2:
+ irq_n = EXTI2_TS_IRQn;
+ vector = (uint32_t)&gpio_irq2;
+ irq_index = 2;
+ break;
+ case 3:
+ irq_n = EXTI3_IRQn;
+ vector = (uint32_t)&gpio_irq3;
+ irq_index = 3;
+ break;
+ case 4:
+ irq_n = EXTI4_IRQn;
+ vector = (uint32_t)&gpio_irq4;
+ irq_index = 4;
+ break;
+ case 5:
+ case 6:
+ case 7:
+ case 8:
+ case 9:
+ irq_n = EXTI9_5_IRQn;
+ vector = (uint32_t)&gpio_irq5;
+ irq_index = 5;
+ break;
+ case 10:
+ case 11:
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ irq_n = EXTI15_10_IRQn;
+ vector = (uint32_t)&gpio_irq6;
+ irq_index = 6;
+ break;
+ default:
+ error("This pin is not supported with InterruptIn.\n");
+ return -1;
+ }
+
+ // Enable GPIO clock
+ uint32_t gpio_add = Set_GPIO_Clock(port_index);
+
+ // Enable SYSCFG clock
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+
+ // Connect EXTI line to pin
+ SYSCFG_EXTILineConfig(port_index, pin_index);
+
+ // Configure EXTI line
+ EXTI_InitTypeDef EXTI_InitStructure;
+ EXTI_InitStructure.EXTI_Line = pin_index;
+ EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+ EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
+ EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+ EXTI_Init(&EXTI_InitStructure);
+
+ // Enable and set EXTI interrupt to the lowest priority
+ NVIC_InitTypeDef NVIC_InitStructure;
+ NVIC_InitStructure.NVIC_IRQChannel = irq_n;
+ NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
+ NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
+ NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+ NVIC_Init(&NVIC_InitStructure);
+
+ NVIC_SetVector(irq_n, vector);
+ NVIC_EnableIRQ(irq_n);
+
+ // Save informations for future use
+ obj->irq_n = irq_n;
+ obj->irq_index = irq_index;
+ obj->event = EDGE_NONE;
+ channel_ids[irq_index] = id;
+ channel_gpio[irq_index] = gpio_add;
+ channel_pin[irq_index] = pin_index;
+
+ irq_handler = handler;
+
+ return 0;
+}
+
+void gpio_irq_free(gpio_irq_t *obj) {
+ channel_ids[obj->irq_index] = 0;
+ channel_gpio[obj->irq_index] = 0;
+ channel_pin[obj->irq_index] = 0;
+ // Disable EXTI line
+ EXTI_InitTypeDef EXTI_InitStructure;
+ EXTI_StructInit(&EXTI_InitStructure);
+ EXTI_Init(&EXTI_InitStructure);
+ obj->event = EDGE_NONE;
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
+ EXTI_InitTypeDef EXTI_InitStructure;
+
+ EXTI_InitStructure.EXTI_Line = channel_pin[obj->irq_index];
+ EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+
+ if (event == IRQ_RISE) {
+ if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) {
+ EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
+ obj->event = EDGE_BOTH;
+ } else { // NONE or RISE
+ EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
+ obj->event = EDGE_RISE;
+ }
+ }
+
+ if (event == IRQ_FALL) {
+ if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) {
+ EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
+ obj->event = EDGE_BOTH;
+ } else { // NONE or FALL
+ EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
+ obj->event = EDGE_FALL;
+ }
+ }
+
+ if (enable) {
+ EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+ } else {
+ EXTI_InitStructure.EXTI_LineCmd = DISABLE;
+ }
+
+ EXTI_Init(&EXTI_InitStructure);
+}
+
+void gpio_irq_enable(gpio_irq_t *obj) {
+ NVIC_EnableIRQ(obj->irq_n);
+}
+
+void gpio_irq_disable(gpio_irq_t *obj) {
+ NVIC_DisableIRQ(obj->irq_n);
+ obj->event = EDGE_NONE;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F3XX/gpio_object.h Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,66 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+ uint32_t mask;
+ __IO uint16_t *reg_in;
+ __IO uint32_t *reg_set;
+ __IO uint16_t *reg_clr;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+ if (value) {
+ *obj->reg_set = obj->mask;
+ } else {
+ *obj->reg_clr = obj->mask;
+ }
+}
+
+static inline int gpio_read(gpio_t *obj) {
+ return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F3XX/i2c_api.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,357 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "i2c_api.h"
+
+#if DEVICE_I2C
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+/* Timeout values for flags and events waiting loops. These timeouts are
+ not based on accurate values, they just guarantee that the application will
+ not remain stuck if the I2C communication is corrupted. */
+#define FLAG_TIMEOUT ((int)0x1000)
+#define LONG_TIMEOUT ((int)0x8000)
+
+static const PinMap PinMap_I2C_SDA[] = {
+ {PA_10, I2C_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_4)},
+ {PA_14, I2C_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_4)},
+ {PB_5, I2C_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_8)},
+ {PB_7, I2C_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_4)},
+ {PB_9, I2C_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_4)},
+ {PC_9, I2C_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_3)},
+ {PF_0, I2C_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_4)},
+ {NC, NC, 0}
+};
+
+static const PinMap PinMap_I2C_SCL[] = {
+ {PA_8, I2C_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_3)},
+ {PA_9, I2C_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_4)},
+ {PA_15, I2C_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_4)},
+ {PB_6, I2C_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_4)},
+ {PB_8, I2C_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_4)},
+ {PF_1, I2C_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_4)},
+ {NC, NC, 0}
+};
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
+ // Determine the I2C to use
+ I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
+ I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
+
+ obj->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl);
+
+ if (obj->i2c == (I2CName)NC) {
+ error("I2C pin mapping failed");
+ }
+
+ // Enable I2C clock
+ if (obj->i2c == I2C_1) {
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C1, ENABLE);
+ }
+ if (obj->i2c == I2C_2) {
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C2, ENABLE);
+ }
+ if (obj->i2c == I2C_3) {
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C3, ENABLE);
+ }
+
+ // Configure I2C pins
+ pinmap_pinout(scl, PinMap_I2C_SCL);
+ pin_mode(scl, OpenDrain);
+ pinmap_pinout(sda, PinMap_I2C_SDA);
+ pin_mode(sda, OpenDrain);
+
+ // Reset to clear pending flags if any
+ i2c_reset(obj);
+
+ // I2C configuration
+ i2c_frequency(obj, 100000); // 100 kHz per default
+}
+
+void i2c_frequency(i2c_t *obj, int hz) {
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ I2C_InitTypeDef I2C_InitStructure;
+ uint32_t tim;
+
+ // Disable the Fast Mode Plus capability
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); // Enable SYSCFG clock
+ SYSCFG_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus_I2C1, DISABLE);
+ SYSCFG_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus_I2C2, DISABLE);
+
+ /*
+ Values calculated with I2C_Timing_Configuration_V1.0.1.xls file (see AN4235)
+ * Standard mode (up to 100 kHz)
+ * Fast Mode (up to 400 kHz)
+ * Fast Mode Plus (up to 1 MHz)
+ Below values obtained with:
+ - I2C clock source = 8 MHz (HSI clock per default)
+ - Analog filter delay = ON
+ - Digital filter coefficient = 0
+ - Rise time = 100 ns
+ - Fall time = 10ns
+ */
+ switch (hz) {
+ case 100000:
+ tim = 0x00201D2B; // Standard mode
+ break;
+ case 200000:
+ tim = 0x0010021E; // Fast Mode
+ break;
+ case 400000:
+ tim = 0x0010020A; // Fast Mode
+ break;
+ case 1000000:
+ tim = 0x00100001; // Fast Mode Plus
+ // Enable the Fast Mode Plus capability
+ if (obj->i2c == I2C_1) {
+ SYSCFG_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus_I2C1, ENABLE);
+ }
+ if (obj->i2c == I2C_2) {
+ SYSCFG_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus_I2C2, ENABLE);
+ }
+ break;
+ default:
+ error("Only 100kHz, 200kHz, 400kHz and 1MHz I2C frequencies are supported.");
+ break;
+ }
+
+ // I2C configuration
+ I2C_DeInit(i2c);
+ I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
+ I2C_InitStructure.I2C_AnalogFilter = I2C_AnalogFilter_Enable;
+ I2C_InitStructure.I2C_DigitalFilter = 0x00;
+ I2C_InitStructure.I2C_OwnAddress1 = 0x00;
+ I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
+ I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+ I2C_InitStructure.I2C_Timing = tim;
+ I2C_Init(i2c, &I2C_InitStructure);
+
+ I2C_Cmd(i2c, ENABLE);
+}
+
+inline int i2c_start(i2c_t *obj) {
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ int timeout;
+
+ // Test BUSY Flag
+ timeout = LONG_TIMEOUT;
+ while (I2C_GetFlagStatus(i2c, I2C_ISR_BUSY) != RESET) {
+ timeout--;
+ if (timeout == 0) {
+ return 0;
+ }
+ }
+
+ I2C_GenerateSTART(i2c, ENABLE);
+
+ return 0;
+}
+
+inline int i2c_stop(i2c_t *obj) {
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+
+ I2C_GenerateSTOP(i2c, ENABLE);
+
+ return 0;
+}
+
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ int count;
+ int value;
+
+ if (length == 0) return 0;
+
+ // Configure slave address, nbytes, reload, end mode and start or stop generation
+ I2C_TransferHandling(i2c, address, length, I2C_AutoEnd_Mode, I2C_Generate_Start_Read);
+
+ // Read all bytes
+ for (count = 0; count < length; count++) {
+ value = i2c_byte_read(obj, 0);
+ data[count] = (char)value;
+ }
+
+ return length;
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ //int timeout;
+ int count;
+
+ if (length == 0) return 0;
+
+ // [TODO] The stop is always sent even with I2C_SoftEnd_Mode. To be corrected.
+
+ // Configure slave address, nbytes, reload, end mode and start or stop generation
+ //if (stop) {
+ I2C_TransferHandling(i2c, address, length, I2C_AutoEnd_Mode, I2C_Generate_Start_Write);
+ //}
+ //else {
+ // I2C_TransferHandling(i2c, address, length, I2C_SoftEnd_Mode, I2C_Generate_Start_Write);
+ //}
+
+ // Write all bytes
+ for (count = 0; count < length; count++) {
+ if (i2c_byte_write(obj, data[count]) != 1) {
+ i2c_stop(obj);
+ return 0;
+ }
+ }
+
+ /*
+ if (stop) {
+ // Wait until STOPF flag is set
+ timeout = LONG_TIMEOUT;
+ while (I2C_GetFlagStatus(i2c, I2C_ISR_STOPF) == RESET) {
+ timeout--;
+ if (timeout == 0) {
+ return 0;
+ }
+ }
+ // Clear STOPF flag
+ I2C_ClearFlag(i2c, I2C_ICR_STOPCF);
+ }
+ */
+
+ return count;
+}
+
+int i2c_byte_read(i2c_t *obj, int last) {
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ uint8_t data;
+ int timeout;
+
+ // Wait until the byte is received
+ timeout = FLAG_TIMEOUT;
+ while (I2C_GetFlagStatus(i2c, I2C_ISR_RXNE) == RESET) {
+ timeout--;
+ if (timeout == 0) {
+ return 0;
+ }
+ }
+
+ data = I2C_ReceiveData(i2c);
+
+ return (int)data;
+}
+
+int i2c_byte_write(i2c_t *obj, int data) {
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ int timeout;
+
+ // Wait until the previous byte is transmitted
+ timeout = FLAG_TIMEOUT;
+ while (I2C_GetFlagStatus(i2c, I2C_ISR_TXIS) == RESET) {
+ timeout--;
+ if (timeout == 0) {
+ return 0;
+ }
+ }
+
+ I2C_SendData(i2c, (uint8_t)data);
+
+ return 1;
+}
+
+void i2c_reset(i2c_t *obj) {
+ if (obj->i2c == I2C_1) {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
+ }
+ if (obj->i2c == I2C_2) {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
+ }
+ if (obj->i2c == I2C_3) {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C3, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C3, DISABLE);
+ }
+}
+
+#if DEVICE_I2CSLAVE
+
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ uint16_t tmpreg;
+
+ // Get the old register value
+ tmpreg = i2c->OAR1;
+ // Reset address bits
+ tmpreg &= 0xFC00;
+ // Set new address
+ tmpreg |= (uint16_t)((uint16_t)address & (uint16_t)0x00FE); // 7-bits
+ // Store the new register value
+ i2c->OAR1 = tmpreg;
+}
+
+void i2c_slave_mode(i2c_t *obj, int enable_slave) {
+ // Nothing to do
+}
+
+// See I2CSlave.h
+#define NoData 0 // the slave has not been addressed
+#define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter)
+#define WriteGeneral 2 // the master is writing to all slave
+#define WriteAddressed 3 // the master is writing to this slave (slave = receiver)
+
+int i2c_slave_receive(i2c_t *obj) {
+ // TO BE DONE
+ return (0);
+}
+
+int i2c_slave_read(i2c_t *obj, char *data, int length) {
+ int count = 0;
+
+ // Read all bytes
+ for (count = 0; count < length; count++) {
+ data[count] = i2c_byte_read(obj, 0);
+ }
+
+ return count;
+}
+
+int i2c_slave_write(i2c_t *obj, const char *data, int length) {
+ int count = 0;
+
+ // Write all bytes
+ for (count = 0; count < length; count++) {
+ i2c_byte_write(obj, data[count]);
+ }
+
+ return count;
+}
+
+
+#endif // DEVICE_I2CSLAVE
+
+#endif // DEVICE_I2C
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F3XX/mbed_overrides.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,35 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+extern void SystemCoreClockUpdate(void);
+
+// This function is called after RAM initialization and before main.
+void mbed_sdk_init() {
+ // Update the SystemCoreClock variable.
+ SystemCoreClockUpdate();
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F3XX/objects.h Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,102 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ IRQn_Type irq_n;
+ uint32_t irq_index;
+ uint32_t event;
+};
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+ PinDirection direction;
+ __IO uint16_t *reg_in;
+ __IO uint16_t *reg_out;
+};
+
+struct analogin_s {
+ ADCName adc;
+ PinName pin;
+};
+
+struct dac_s {
+ DACName dac;
+ PinName channel;
+};
+
+struct serial_s {
+ UARTName uart;
+ int index; // Used by irq
+ uint32_t baudrate;
+ uint32_t databits;
+ uint32_t stopbits;
+ uint32_t parity;
+};
+
+struct spi_s {
+ SPIName spi;
+ uint32_t bits;
+ uint32_t cpol;
+ uint32_t cpha;
+ uint32_t mode;
+ uint32_t nss;
+ uint32_t br_presc;
+};
+
+struct i2c_s {
+ I2CName i2c;
+};
+
+struct pwmout_s {
+ PWMName pwm;
+ PinName pin;
+ uint32_t period;
+ uint32_t pulse;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F3XX/pinmap.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,133 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "pinmap.h"
+#include "PortNames.h"
+#include "error.h"
+
+// Enable GPIO clock and return GPIO base address
+uint32_t Set_GPIO_Clock(uint32_t port_idx) {
+ uint32_t gpio_add;
+ switch (port_idx) {
+ case PortA:
+ gpio_add = GPIOA_BASE;
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
+ break;
+ case PortB:
+ gpio_add = GPIOB_BASE;
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOB, ENABLE);
+ break;
+ case PortC:
+ gpio_add = GPIOC_BASE;
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOC, ENABLE);
+ break;
+ case PortD:
+ gpio_add = GPIOD_BASE;
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOD, ENABLE);
+ break;
+ case PortE:
+ gpio_add = GPIOE_BASE;
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOE, ENABLE);
+ break;
+ case PortF:
+ gpio_add = GPIOF_BASE;
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOF, ENABLE);
+ break;
+ default:
+ gpio_add = 0;
+ error("Port number is not correct.");
+ break;
+ }
+ return gpio_add;
+}
+
+/**
+ * Configure pin (mode, speed, output type and pull-up/pull-down)
+ */
+void pin_function(PinName pin, int data) {
+ if (pin == NC) return;
+
+ // Get the pin informations
+ uint32_t mode = STM_PIN_MODE(data);
+ uint32_t otype = STM_PIN_OTYPE(data);
+ uint32_t pupd = STM_PIN_PUPD(data);
+ uint32_t afnum = STM_PIN_AFNUM(data);
+
+ uint32_t port_index = STM_PORT(pin);
+ uint32_t pin_index = STM_PIN(pin);
+
+ // Enable GPIO clock
+ uint32_t gpio_add = Set_GPIO_Clock(port_index);
+ GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
+
+ // Configure Alternate Function
+ // Warning: Must be done before the GPIO is initialized
+ if (afnum != 0xFF) {
+ GPIO_PinAFConfig(gpio, (uint16_t)pin_index, afnum);
+ }
+
+ // Configure GPIO
+ GPIO_InitTypeDef GPIO_InitStructure;
+ GPIO_InitStructure.GPIO_Pin = (uint16_t)(1 << pin_index);
+ GPIO_InitStructure.GPIO_Mode = (GPIOMode_TypeDef)mode;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_Level_3;
+ GPIO_InitStructure.GPIO_OType = (GPIOOType_TypeDef)otype;
+ GPIO_InitStructure.GPIO_PuPd = (GPIOPuPd_TypeDef)pupd;
+ GPIO_Init(gpio, &GPIO_InitStructure);
+
+ // [TODO] Disconnect JTAG-DP + SW-DP signals.
+ // Warning: Need to reconnect under reset
+ //if ((pin == PA_13) || (pin == PA_14)) {
+ //
+ //}
+ //if ((pin == PA_15) || (pin == PB_3) || (pin == PB_4)) {
+ //
+ //}
+}
+
+/**
+ * Configure pin pull-up/pull-down
+ */
+void pin_mode(PinName pin, PinMode mode) {
+ if (pin == NC) return;
+
+ uint32_t port_index = STM_PORT(pin);
+ uint32_t pin_index = STM_PIN(pin);
+
+ // Enable GPIO clock
+ uint32_t gpio_add = Set_GPIO_Clock(port_index);
+ GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
+
+ // Configure pull-up/pull-down resistors
+ uint32_t pupd = (uint32_t)mode;
+ if (pupd > 2) pupd = 0; // Open-drain = No pull-up/No pull-down
+ gpio->PUPDR &= (uint32_t)(~(GPIO_PUPDR_PUPDR0 << (pin_index * 2)));
+ gpio->PUPDR |= (uint32_t)(pupd << (pin_index * 2));
+
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F3XX/port_api.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,97 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "port_api.h"
+#include "pinmap.h"
+#include "gpio_api.h"
+#include "error.h"
+
+#if DEVICE_PORTIN || DEVICE_PORTOUT
+
+extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
+
+// high nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...)
+// low nibble = pin number
+PinName port_pin(PortName port, int pin_n) {
+ return (PinName)(pin_n + (port << 4));
+}
+
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
+ uint32_t port_index = (uint32_t)port;
+
+ // Enable GPIO clock
+ uint32_t gpio_add = Set_GPIO_Clock(port_index);
+ GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
+
+ // Fill PORT object structure for future use
+ obj->port = port;
+ obj->mask = mask;
+ obj->direction = dir;
+ obj->reg_in = &gpio->IDR;
+ obj->reg_out = &gpio->ODR;
+
+ port_dir(obj, dir);
+}
+
+void port_dir(port_t *obj, PinDirection dir) {
+ uint32_t i;
+ obj->direction = dir;
+ for (i = 0; i < 16; i++) { // Process all pins
+ if (obj->mask & (1 << i)) { // If the pin is used
+ if (dir == PIN_OUTPUT) {
+ pin_function(port_pin(obj->port, i), STM_PIN_DATA(GPIO_Mode_OUT, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF));
+ } else { // PIN_INPUT
+ pin_function(port_pin(obj->port, i), STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0xFF));
+ }
+ }
+ }
+}
+
+void port_mode(port_t *obj, PinMode mode) {
+ uint32_t i;
+ for (i = 0; i < 16; i++) { // Process all pins
+ if (obj->mask & (1 << i)) { // If the pin is used
+ pin_mode(port_pin(obj->port, i), mode);
+ }
+ }
+}
+
+void port_write(port_t *obj, int value) {
+ *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask);
+}
+
+int port_read(port_t *obj) {
+ if (obj->direction == PIN_OUTPUT) {
+ return (*obj->reg_out & obj->mask);
+ } else { // PIN_INPUT
+ return (*obj->reg_in & obj->mask);
+ }
+}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F3XX/pwmout_api.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,277 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "pwmout_api.h"
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+// TIM2 cannot be used because already used by the us_ticker
+static const PinMap PinMap_PWM[] = {
+// {PA_0, PWM_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM2_CH1
+// {PA_1, PWM_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM2_CH2
+ {PA_1, PWM_15, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_9)}, // TIM15_CH1N
+ {PA_2, PWM_15, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_9)}, // TIM15_CH1
+ {PA_3, PWM_15, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_9)}, // TIM15_CH2
+// {PA_5, PWM_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM2_CH1
+ {PA_6, PWM_16, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM16_CH1
+ {PA_7, PWM_17, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM17_CH1
+// {PA_7, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_6)}, // TIM1_CH1N
+ {PA_8, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_6)}, // TIM1_CH1
+ {PA_9, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_6)}, // TIM1_CH2
+// {PA_9, PWM_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_10)}, // TIM2_CH3
+ {PA_10, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_6)}, // TIM1_CH3
+// {PA_10, PWM_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_10)}, // TIM2_CH4
+ {PA_11, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_11)}, // TIM1_CH4
+// {PA_11, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_6)}, // TIM1_CH1N
+ {PA_12, PWM_16, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM16_CH1
+// {PA_12, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_6)}, // TIM1_CH2N
+ {PA_13, PWM_16, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM16_CH1N
+// {PA_15, PWM_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM2_CH1
+
+ {PB_0, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_6)}, // TIM1_CH2N
+ {PB_1, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_6)}, // TIM1_CH3N
+// {PB_3, PWM_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM2_CH2
+ {PB_4, PWM_16, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM16_CH1
+ {PB_5, PWM_17, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_10)}, // TIM17_CH1
+ {PB_6, PWM_16, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM16_CH1N
+ {PB_7, PWM_17, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM17_CH1N
+ {PB_8, PWM_16, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM16_CH1
+ {PB_9, PWM_17, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM17_CH1
+// {PB_10, PWM_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM2_CH3
+// {PB_11, PWM_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM2_CH4
+ {PB_13, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_6)}, // TIM1_CH1N
+ {PB_14, PWM_15, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM15_CH1
+// {PB_14, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_6)}, // TIM1_CH2N
+ {PB_15, PWM_15, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM15_CH2
+// {PB_15, PWM_15, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_2)}, // TIM15_CH1N
+// {PB_15, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_4)}, // TIM1_CH3N
+
+ {PC_0, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_2)}, // TIM1_CH1
+ {PC_1, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_2)}, // TIM1_CH2
+ {PC_2, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_2)}, // TIM1_CH3
+ {PC_3, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_2)}, // TIM1_CH4
+ {PC_13, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_4)}, // TIM1_CH1N
+
+ {PF_0, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_6)}, // TIM1_CH3N
+
+ {NC, NC, 0}
+};
+
+void pwmout_init(pwmout_t* obj, PinName pin) {
+ // Get the peripheral name from the pin and assign it to the object
+ obj->pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
+
+ if (obj->pwm == (PWMName)NC) {
+ error("PWM pinout mapping failed");
+ }
+
+ // Enable TIM clock
+ if (obj->pwm == PWM_1) RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE);
+ if (obj->pwm == PWM_15) RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM15, ENABLE);
+ if (obj->pwm == PWM_16) RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM16, ENABLE);
+ if (obj->pwm == PWM_17) RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM17, ENABLE);
+
+ // Configure GPIO
+ pinmap_pinout(pin, PinMap_PWM);
+
+ obj->pin = pin;
+ obj->period = 0;
+ obj->pulse = 0;
+
+ pwmout_period_us(obj, 20000); // 20 ms per default
+}
+
+void pwmout_free(pwmout_t* obj) {
+ TIM_TypeDef *tim = (TIM_TypeDef *)(obj->pwm);
+ TIM_DeInit(tim);
+}
+
+void pwmout_write(pwmout_t* obj, float value) {
+ TIM_TypeDef *tim = (TIM_TypeDef *)(obj->pwm);
+ TIM_OCInitTypeDef TIM_OCInitStructure;
+
+ if (value < (float)0.0) {
+ value = (float)0.0;
+ } else if (value > (float)1.0) {
+ value = (float)1.0;
+ }
+
+ obj->pulse = (uint32_t)((float)obj->period * value);
+
+ // Configure channels
+ TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
+ TIM_OCInitStructure.TIM_Pulse = obj->pulse;
+ TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
+ TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCPolarity_High;
+ TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Reset;
+ TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCNIdleState_Reset;
+
+ switch (obj->pin) {
+ // Channels 1
+// case PA_0:
+ case PA_2:
+// case PA_5:
+ case PA_6:
+ case PA_7:
+ case PA_8:
+ case PA_12:
+// case PA_15:
+ case PB_4:
+ case PB_5:
+ case PB_8:
+ case PB_9:
+ case PB_14:
+ case PC_0:
+ TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
+ TIM_OC1PreloadConfig(tim, TIM_OCPreload_Enable);
+ TIM_OC1Init(tim, &TIM_OCInitStructure);
+ break;
+ // Channels 1N
+ case PA_1:
+// case PA_7:
+// case PA_11:
+ case PA_13:
+ case PB_6:
+ case PB_7:
+ case PB_13:
+// case PB_15:
+ case PC_13:
+ TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
+ TIM_OC1PreloadConfig(tim, TIM_OCPreload_Enable);
+ TIM_OC1Init(tim, &TIM_OCInitStructure);
+ break;
+ // Channels 2
+// case PA_1:
+ case PA_3:
+ case PA_9:
+// case PB_3:
+ case PB_15:
+ case PC_1:
+ TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
+ TIM_OC2PreloadConfig(tim, TIM_OCPreload_Enable);
+ TIM_OC2Init(tim, &TIM_OCInitStructure);
+ break;
+ // Channels 2N
+// case PA_12:
+ case PB_0:
+// case PB_14:
+ TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
+ TIM_OC2PreloadConfig(tim, TIM_OCPreload_Enable);
+ TIM_OC2Init(tim, &TIM_OCInitStructure);
+ break;
+ // Channels 3
+// case PA_9:
+ case PA_10:
+// case PB_10:
+ case PC_2:
+ TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
+ TIM_OC3PreloadConfig(tim, TIM_OCPreload_Enable);
+ TIM_OC3Init(tim, &TIM_OCInitStructure);
+ break;
+ // Channels 3N
+ case PB_1:
+ case PF_0:
+// case PB_15:
+ TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
+ TIM_OC3PreloadConfig(tim, TIM_OCPreload_Enable);
+ TIM_OC3Init(tim, &TIM_OCInitStructure);
+ break;
+ // Channels 4
+// case PA_10:
+ case PA_11:
+// case PB_11:
+ case PC_3:
+ TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
+ TIM_OC4PreloadConfig(tim, TIM_OCPreload_Enable);
+ TIM_OC4Init(tim, &TIM_OCInitStructure);
+ break;
+ default:
+ return;
+ }
+}
+
+float pwmout_read(pwmout_t* obj) {
+ float value = 0;
+ if (obj->period > 0) {
+ value = (float)(obj->pulse) / (float)(obj->period);
+ }
+ return ((value > (float)1.0) ? ((float)1.0) : (value));
+}
+
+void pwmout_period(pwmout_t* obj, float seconds) {
+ pwmout_period_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_period_ms(pwmout_t* obj, int ms) {
+ pwmout_period_us(obj, ms * 1000);
+}
+
+void pwmout_period_us(pwmout_t* obj, int us) {
+ TIM_TypeDef *tim = (TIM_TypeDef *)(obj->pwm);
+ TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
+ float dc = pwmout_read(obj);
+
+ TIM_Cmd(tim, DISABLE);
+
+ obj->period = us;
+
+ TIM_TimeBaseStructInit(&TIM_TimeBaseStructure);
+ TIM_TimeBaseStructure.TIM_Period = obj->period - 1;
+ TIM_TimeBaseStructure.TIM_Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick
+ TIM_TimeBaseStructure.TIM_ClockDivision = 0;
+ TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
+ TIM_TimeBaseInit(tim, &TIM_TimeBaseStructure);
+
+ // Set duty cycle again
+ pwmout_write(obj, dc);
+
+ TIM_ARRPreloadConfig(tim, ENABLE);
+
+ // Warning: Main Output must be enabled on TIM1, TIM8, TIM5, TIM6 and TIM17
+ if ((obj->pwm == PWM_1) || (obj->pwm == PWM_15) || (obj->pwm == PWM_16) || (obj->pwm == PWM_17)) {
+ TIM_CtrlPWMOutputs(tim, ENABLE);
+ }
+
+ TIM_Cmd(tim, ENABLE);
+}
+
+void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
+ pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
+ pwmout_pulsewidth_us(obj, ms * 1000);
+}
+
+void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
+ float value = (float)us / (float)obj->period;
+ pwmout_write(obj, value);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F3XX/rtc_api.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,138 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "rtc_api.h"
+
+static int rtc_inited = 0;
+
+void rtc_init(void) {
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); // Enable PWR clock
+
+ PWR_BackupAccessCmd(ENABLE); // Enable access to RTC
+
+ // Be sure to start correctly
+ RCC_BackupResetCmd(ENABLE);
+ RCC_BackupResetCmd(DISABLE);
+
+ // Note: the LSI is used as RTC source clock
+ // The RTC Clock may vary due to LSI frequency dispersion.
+ RCC_LSICmd(ENABLE); // Enable LSI
+
+ while (RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET) {} // Wait until ready
+
+ RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI); // Select LSI as RTC Clock Source
+
+ RCC_RTCCLKCmd(ENABLE); // Enable RTC Clock
+
+ RTC_WaitForSynchro(); // Wait for RTC registers synchronization
+
+ uint32_t lsi_freq = 40000; // [TODO] To be measured precisely using a timer input capture
+
+ RTC_InitTypeDef RTC_InitStructure;
+ RTC_InitStructure.RTC_AsynchPrediv = 127;
+ RTC_InitStructure.RTC_SynchPrediv = (lsi_freq / 128) - 1;
+ RTC_InitStructure.RTC_HourFormat = RTC_HourFormat_24;
+ RTC_Init(&RTC_InitStructure);
+
+ rtc_inited = 1;
+}
+
+void rtc_free(void) {
+ RCC_DeInit(); // Resets the RCC clock configuration to the default reset state
+ rtc_inited = 0;
+}
+
+int rtc_isenabled(void) {
+ return rtc_inited;
+}
+
+/*
+ RTC Registers
+ RTC_WeekDay 1=monday, 2=tuesday, ..., 7=sunday
+ RTC_Month 1=january, 2=february, ..., 12=december
+ RTC_Date day of the month 1-31
+ RTC_Year year 0-99
+ struct tm
+ tm_sec seconds after the minute 0-61
+ tm_min minutes after the hour 0-59
+ tm_hour hours since midnight 0-23
+ tm_mday day of the month 1-31
+ tm_mon months since January 0-11
+ tm_year years since 1900
+ tm_wday days since Sunday 0-6
+ tm_yday days since January 1 0-365
+ tm_isdst Daylight Saving Time flag
+*/
+time_t rtc_read(void) {
+ RTC_DateTypeDef dateStruct;
+ RTC_TimeTypeDef timeStruct;
+ struct tm timeinfo;
+
+ // Read actual date and time
+ RTC_GetTime(RTC_Format_BIN, &timeStruct);
+ RTC_GetDate(RTC_Format_BIN, &dateStruct);
+
+ // Setup a tm structure based on the RTC
+ timeinfo.tm_wday = dateStruct.RTC_WeekDay;
+ timeinfo.tm_mon = dateStruct.RTC_Month - 1;
+ timeinfo.tm_mday = dateStruct.RTC_Date;
+ timeinfo.tm_year = dateStruct.RTC_Year + 100;
+ timeinfo.tm_hour = timeStruct.RTC_Hours;
+ timeinfo.tm_min = timeStruct.RTC_Minutes;
+ timeinfo.tm_sec = timeStruct.RTC_Seconds;
+
+ // Convert to timestamp
+ time_t t = mktime(&timeinfo);
+
+ return t;
+}
+
+void rtc_write(time_t t) {
+ RTC_DateTypeDef dateStruct;
+ RTC_TimeTypeDef timeStruct;
+
+ // Convert the time into a tm
+ struct tm *timeinfo = localtime(&t);
+
+ // Fill RTC structures
+ dateStruct.RTC_WeekDay = timeinfo->tm_wday;
+ dateStruct.RTC_Month = timeinfo->tm_mon + 1;
+ dateStruct.RTC_Date = timeinfo->tm_mday;
+ dateStruct.RTC_Year = timeinfo->tm_year - 100;
+ timeStruct.RTC_Hours = timeinfo->tm_hour;
+ timeStruct.RTC_Minutes = timeinfo->tm_min;
+ timeStruct.RTC_Seconds = timeinfo->tm_sec;
+ timeStruct.RTC_H12 = RTC_HourFormat_24;
+
+ // Change the RTC current date/time
+ PWR_BackupAccessCmd(ENABLE); // Enable access to RTC
+ RTC_SetDate(RTC_Format_BIN, &dateStruct);
+ RTC_SetTime(RTC_Format_BIN, &timeStruct);
+ PWR_BackupAccessCmd(DISABLE); // Disable access to RTC
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F3XX/serial_api.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,311 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "serial_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+#include <string.h>
+
+static const PinMap PinMap_UART_TX[] = {
+ {PA_2, UART_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)},
+ {PA_9, UART_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)},
+ {PA_14, UART_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)},
+ {PB_3, UART_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)},
+ {PB_6, UART_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)},
+ {PB_9, UART_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)},
+ {PB_10, UART_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)},
+ {PC_4, UART_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)},
+ {PC_10, UART_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)},
+ {NC, NC, 0}
+};
+
+static const PinMap PinMap_UART_RX[] = {
+ {PA_3, UART_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)},
+ {PA_10, UART_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)},
+ {PA_15, UART_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)},
+ {PB_4, UART_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)},
+ {PB_7, UART_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)},
+ {PB_8, UART_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)},
+ {PB_11, UART_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)},
+ {PC_5, UART_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)},
+ {PC_11, UART_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)},
+ {NC, NC, 0}
+};
+
+#define UART_NUM (2)
+
+static uint32_t serial_irq_ids[UART_NUM] = {0};
+
+static uart_irq_handler irq_handler;
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+static void init_usart(serial_t *obj) {
+ USART_TypeDef *usart = (USART_TypeDef *)(obj->uart);
+ USART_InitTypeDef USART_InitStructure;
+
+ USART_Cmd(usart, DISABLE);
+
+ USART_InitStructure.USART_BaudRate = obj->baudrate;
+ USART_InitStructure.USART_WordLength = obj->databits;
+ USART_InitStructure.USART_StopBits = obj->stopbits;
+ USART_InitStructure.USART_Parity = obj->parity;
+ USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+ USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+ USART_Init(usart, &USART_InitStructure);
+
+ USART_Cmd(usart, ENABLE);
+}
+
+void serial_init(serial_t *obj, PinName tx, PinName rx) {
+ // Determine the UART to use
+ UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
+ UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
+
+ // Get the peripheral name from the pin and assign it to the object
+ obj->uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
+
+ if (obj->uart == (UARTName)NC) {
+ error("Serial pinout mapping failed");
+ }
+
+ // Enable USART clock
+ if (obj->uart == UART_1) {
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
+ }
+ if (obj->uart == UART_2) {
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
+ }
+ if (obj->uart == UART_3) {
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
+ }
+
+ // Configure the UART pins
+ pinmap_pinout(tx, PinMap_UART_TX);
+ pinmap_pinout(rx, PinMap_UART_RX);
+ pin_mode(tx, PullUp);
+ pin_mode(rx, PullUp);
+
+ // Configure UART
+ obj->baudrate = 9600;
+ obj->databits = USART_WordLength_8b;
+ obj->stopbits = USART_StopBits_1;
+ obj->parity = USART_Parity_No;
+
+ init_usart(obj);
+
+ // The index is used by irq
+ if (obj->uart == UART_1) obj->index = 0;
+ if (obj->uart == UART_2) obj->index = 1;
+ if (obj->uart == UART_3) obj->index = 2;
+
+ // For stdio management
+ if (obj->uart == STDIO_UART) {
+ stdio_uart_inited = 1;
+ memcpy(&stdio_uart, obj, sizeof(serial_t));
+ }
+
+}
+
+void serial_free(serial_t *obj) {
+ serial_irq_ids[obj->index] = 0;
+}
+
+void serial_baud(serial_t *obj, int baudrate) {
+ obj->baudrate = baudrate;
+ init_usart(obj);
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
+ if (data_bits == 8) {
+ obj->databits = USART_WordLength_8b;
+ } else {
+ obj->databits = USART_WordLength_9b;
+ }
+
+ switch (parity) {
+ case ParityOdd:
+ case ParityForced0:
+ obj->parity = USART_Parity_Odd;
+ break;
+ case ParityEven:
+ case ParityForced1:
+ obj->parity = USART_Parity_Even;
+ break;
+ default: // ParityNone
+ obj->parity = USART_Parity_No;
+ break;
+ }
+
+ if (stop_bits == 2) {
+ obj->stopbits = USART_StopBits_2;
+ } else {
+ obj->stopbits = USART_StopBits_1;
+ }
+
+ init_usart(obj);
+}
+
+/******************************************************************************
+ * INTERRUPTS HANDLING
+ ******************************************************************************/
+
+// not api
+static void uart_irq(USART_TypeDef* usart, int id) {
+ if (serial_irq_ids[id] != 0) {
+ if (USART_GetITStatus(usart, USART_IT_TC) != RESET) {
+ irq_handler(serial_irq_ids[id], TxIrq);
+ USART_ClearITPendingBit(usart, USART_IT_TC);
+ }
+ if (USART_GetITStatus(usart, USART_IT_RXNE) != RESET) {
+ irq_handler(serial_irq_ids[id], RxIrq);
+ USART_ClearITPendingBit(usart, USART_IT_RXNE);
+ }
+ }
+}
+
+static void uart1_irq(void) {
+ uart_irq((USART_TypeDef*)UART_1, 0);
+}
+static void uart2_irq(void) {
+ uart_irq((USART_TypeDef*)UART_2, 1);
+}
+static void uart3_irq(void) {
+ uart_irq((USART_TypeDef*)UART_3, 2);
+}
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
+ irq_handler = handler;
+ serial_irq_ids[obj->index] = id;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
+ IRQn_Type irq_n = (IRQn_Type)0;
+ uint32_t vector = 0;
+ USART_TypeDef *usart = (USART_TypeDef *)(obj->uart);
+
+ if (obj->uart == UART_1) {
+ irq_n = USART1_IRQn;
+ vector = (uint32_t)&uart1_irq;
+ }
+
+ if (obj->uart == UART_2) {
+ irq_n = USART2_IRQn;
+ vector = (uint32_t)&uart2_irq;
+ }
+
+ if (obj->uart == UART_3) {
+ irq_n = USART3_IRQn;
+ vector = (uint32_t)&uart3_irq;
+ }
+
+ if (enable) {
+
+ if (irq == RxIrq) {
+ USART_ITConfig(usart, USART_IT_RXNE, ENABLE);
+ } else { // TxIrq
+ USART_ITConfig(usart, USART_IT_TC, ENABLE);
+ }
+
+ NVIC_SetVector(irq_n, vector);
+ NVIC_EnableIRQ(irq_n);
+
+ } else { // disable
+
+ int all_disabled = 0;
+
+ if (irq == RxIrq) {
+ USART_ITConfig(usart, USART_IT_RXNE, DISABLE);
+ // Check if TxIrq is disabled too
+ if ((usart->CR1 & USART_CR1_TXEIE) == 0) all_disabled = 1;
+ } else { // TxIrq
+ USART_ITConfig(usart, USART_IT_TXE, DISABLE);
+ // Check if RxIrq is disabled too
+ if ((usart->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1;
+ }
+
+ if (all_disabled) NVIC_DisableIRQ(irq_n);
+
+ }
+}
+
+/******************************************************************************
+ * READ/WRITE
+ ******************************************************************************/
+
+int serial_getc(serial_t *obj) {
+ USART_TypeDef *usart = (USART_TypeDef *)(obj->uart);
+ while (!serial_readable(obj));
+ return (int)(USART_ReceiveData(usart));
+}
+
+void serial_putc(serial_t *obj, int c) {
+ USART_TypeDef *usart = (USART_TypeDef *)(obj->uart);
+ while (!serial_writable(obj));
+ USART_SendData(usart, (uint16_t)c);
+}
+
+int serial_readable(serial_t *obj) {
+ int status;
+ USART_TypeDef *usart = (USART_TypeDef *)(obj->uart);
+ // Check if data is received
+ status = ((USART_GetFlagStatus(usart, USART_FLAG_RXNE) != RESET) ? 1 : 0);
+ return status;
+}
+
+int serial_writable(serial_t *obj) {
+ int status;
+ USART_TypeDef *usart = (USART_TypeDef *)(obj->uart);
+ // Check if data is transmitted
+ status = ((USART_GetFlagStatus(usart, USART_FLAG_TXE) != RESET) ? 1 : 0);
+ return status;
+}
+
+void serial_clear(serial_t *obj) {
+ USART_TypeDef *usart = (USART_TypeDef *)(obj->uart);
+ USART_ClearFlag(usart, USART_FLAG_TXE);
+ USART_ClearFlag(usart, USART_FLAG_RXNE);
+}
+
+void serial_pinout_tx(PinName tx) {
+ pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+void serial_break_set(serial_t *obj) {
+ USART_TypeDef *usart = (USART_TypeDef *)(obj->uart);
+ USART_RequestCmd(usart, USART_Request_SBKRQ, ENABLE);
+}
+
+void serial_break_clear(serial_t *obj) {
+ USART_TypeDef *usart = (USART_TypeDef *)(obj->uart);
+ USART_RequestCmd(usart, USART_Request_SBKRQ, DISABLE);
+ USART_ClearFlag(usart, USART_FLAG_SBK);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F3XX/sleep.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "sleep_api.h"
+#include "cmsis.h"
+
+// This function is in the system_stm32f30x.c file
+extern void SetSysClock(void);
+
+// MCU SLEEP mode
+void sleep(void) {
+ // Enable PWR clock
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
+
+ // Request to enter SLEEP mode
+ PWR_EnterSleepMode(PWR_SLEEPEntry_WFI);
+}
+
+// MCU STOP mode
+void deepsleep(void) {
+ // Enable PWR clock
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
+
+ // Enter Stop Mode
+ PWR_EnterSTOPMode(PWR_Regulator_LowPower, PWR_STOPEntry_WFI);
+
+ // After wake-up from STOP reconfigure the PLL
+ SetSysClock();
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F3XX/spi_api.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,280 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "spi_api.h"
+
+#if DEVICE_SPI
+
+#include <math.h>
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+static const PinMap PinMap_SPI_MOSI[] = {
+ {PA_11, SPI_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_DOWN, GPIO_AF_5)},
+ {PB_5, SPI_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_DOWN, GPIO_AF_6)},
+ {PB_15, SPI_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_DOWN, GPIO_AF_5)},
+ {PC_12, SPI_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_DOWN, GPIO_AF_6)},
+ {NC, NC, 0}
+};
+
+static const PinMap PinMap_SPI_MISO[] = {
+ {PA_10, SPI_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_DOWN, GPIO_AF_5)},
+ {PB_4, SPI_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_DOWN, GPIO_AF_6)},
+ {PB_14, SPI_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_DOWN, GPIO_AF_5)},
+ {PC_11, SPI_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_DOWN, GPIO_AF_6)},
+ {NC, NC, 0}
+};
+
+static const PinMap PinMap_SPI_SCLK[] = {
+ {PB_3, SPI_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_DOWN, GPIO_AF_6)},
+ {PB_13, SPI_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_DOWN, GPIO_AF_5)},
+ {PC_10, SPI_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_DOWN, GPIO_AF_6)},
+ {PF_1, SPI_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_DOWN, GPIO_AF_5)},
+ {NC, NC, 0}
+};
+
+static const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_DOWN, GPIO_AF_6)},
+ {PA_15, SPI_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_DOWN, GPIO_AF_6)},
+ {PB_12, SPI_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_DOWN, GPIO_AF_5)},
+ {PF_0, SPI_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_DOWN, GPIO_AF_5)},
+ {NC, NC, 0}
+};
+
+static void init_spi(spi_t *obj) {
+ SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+ SPI_InitTypeDef SPI_InitStructure;
+
+ SPI_Cmd(spi, DISABLE);
+
+ SPI_InitStructure.SPI_Mode = obj->mode;
+ SPI_InitStructure.SPI_NSS = obj->nss;
+ SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+ SPI_InitStructure.SPI_DataSize = obj->bits;
+ SPI_InitStructure.SPI_CPOL = obj->cpol;
+ SPI_InitStructure.SPI_CPHA = obj->cpha;
+ SPI_InitStructure.SPI_BaudRatePrescaler = obj->br_presc;
+ SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
+ SPI_InitStructure.SPI_CRCPolynomial = 7;
+ SPI_Init(spi, &SPI_InitStructure);
+
+ SPI_RxFIFOThresholdConfig(spi, SPI_RxFIFOThreshold_QF);
+
+ SPI_Cmd(spi, ENABLE);
+}
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+ // Determine the SPI to use
+ SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+ SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
+ SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+ SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+
+ SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
+ SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
+
+ obj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
+
+ if (obj->spi == (SPIName)NC) {
+ error("SPI pinout mapping failed");
+ }
+
+ // Enable SPI clock
+ if (obj->spi == SPI_2) {
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
+ }
+ if (obj->spi == SPI_3) {
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);
+ }
+
+ // Configure the SPI pins
+ pinmap_pinout(mosi, PinMap_SPI_MOSI);
+ pinmap_pinout(miso, PinMap_SPI_MISO);
+ pinmap_pinout(sclk, PinMap_SPI_SCLK);
+
+ // Save new values
+ obj->bits = SPI_DataSize_8b;
+ obj->cpol = SPI_CPOL_Low;
+ obj->cpha = SPI_CPHA_1Edge;
+ obj->br_presc = SPI_BaudRatePrescaler_256;
+
+ if (ssel == NC) { // Master
+ obj->mode = SPI_Mode_Master;
+ obj->nss = SPI_NSS_Soft;
+ } else { // Slave
+ pinmap_pinout(ssel, PinMap_SPI_SSEL);
+ obj->mode = SPI_Mode_Slave;
+ obj->nss = SPI_NSS_Soft;
+ }
+
+ init_spi(obj);
+}
+
+void spi_free(spi_t *obj) {
+ SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+ SPI_I2S_DeInit(spi);
+}
+
+void spi_format(spi_t *obj, int bits, int mode, int slave) {
+ // Save new values
+ if (bits == 8) {
+ obj->bits = SPI_DataSize_8b;
+ } else {
+ obj->bits = SPI_DataSize_16b;
+ }
+
+ switch (mode) {
+ case 0:
+ obj->cpol = SPI_CPOL_Low;
+ obj->cpha = SPI_CPHA_1Edge;
+ break;
+ case 1:
+ obj->cpol = SPI_CPOL_Low;
+ obj->cpha = SPI_CPHA_2Edge;
+ break;
+ case 2:
+ obj->cpol = SPI_CPOL_High;
+ obj->cpha = SPI_CPHA_1Edge;
+ break;
+ default:
+ obj->cpol = SPI_CPOL_High;
+ obj->cpha = SPI_CPHA_2Edge;
+ break;
+ }
+
+ if (slave == 0) {
+ obj->mode = SPI_Mode_Master;
+ obj->nss = SPI_NSS_Soft;
+ } else {
+ obj->mode = SPI_Mode_Slave;
+ obj->nss = SPI_NSS_Hard;
+ }
+
+ init_spi(obj);
+}
+
+void spi_frequency(spi_t *obj, int hz) {
+ // Values depend of PCLK1: 32 MHz if HSI is used, 36 MHz if HSE is used
+ if (hz < 250000) {
+ obj->br_presc = SPI_BaudRatePrescaler_256; // 125 kHz - 141 kHz
+ } else if ((hz >= 250000) && (hz < 500000)) {
+ obj->br_presc = SPI_BaudRatePrescaler_128; // 250 kHz - 280 kHz
+ } else if ((hz >= 500000) && (hz < 1000000)) {
+ obj->br_presc = SPI_BaudRatePrescaler_64; // 500 kHz - 560 kHz
+ } else if ((hz >= 1000000) && (hz < 2000000)) {
+ obj->br_presc = SPI_BaudRatePrescaler_32; // 1 MHz - 1.13 MHz
+ } else if ((hz >= 2000000) && (hz < 4000000)) {
+ obj->br_presc = SPI_BaudRatePrescaler_16; // 2 MHz - 2.25 MHz
+ } else if ((hz >= 4000000) && (hz < 8000000)) {
+ obj->br_presc = SPI_BaudRatePrescaler_8; // 4 MHz - 4.5 MHz
+ } else if ((hz >= 8000000) && (hz < 16000000)) {
+ obj->br_presc = SPI_BaudRatePrescaler_4; // 8 MHz - 9 MHz
+ } else { // >= 16000000
+ obj->br_presc = SPI_BaudRatePrescaler_2; // 16 MHz - 18 MHz
+ }
+ init_spi(obj);
+}
+
+static inline int ssp_readable(spi_t *obj) {
+ int status;
+ SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+ // Check if data is received
+ status = ((SPI_I2S_GetFlagStatus(spi, SPI_I2S_FLAG_RXNE) != RESET) ? 1 : 0);
+ return status;
+}
+
+static inline int ssp_writeable(spi_t *obj) {
+ int status;
+ SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+ // Check if data is transmitted
+ status = ((SPI_I2S_GetFlagStatus(spi, SPI_I2S_FLAG_TXE) != RESET) ? 1 : 0);
+ return status;
+}
+
+static inline void ssp_write(spi_t *obj, int value) {
+ SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+ while (!ssp_writeable(obj));
+ if (obj->bits == SPI_DataSize_8b) {
+ SPI_SendData8(spi, (uint8_t)value);
+ } else {
+ SPI_I2S_SendData16(spi, (uint16_t)value);
+ }
+}
+
+static inline int ssp_read(spi_t *obj) {
+ SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+ while (!ssp_readable(obj));
+ if (obj->bits == SPI_DataSize_8b) {
+ return (int)SPI_ReceiveData8(spi);
+ } else {
+ return (int)SPI_I2S_ReceiveData16(spi);
+ }
+}
+
+static inline int ssp_busy(spi_t *obj) {
+ int status;
+ SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+ status = ((SPI_I2S_GetFlagStatus(spi, SPI_I2S_FLAG_BSY) != RESET) ? 1 : 0);
+ return status;
+}
+
+int spi_master_write(spi_t *obj, int value) {
+ ssp_write(obj, value);
+ return ssp_read(obj);
+}
+
+int spi_slave_receive(spi_t *obj) {
+ return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
+};
+
+int spi_slave_read(spi_t *obj) {
+ SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+ if (obj->bits == SPI_DataSize_8b) {
+ return (int)SPI_ReceiveData8(spi);
+ } else {
+ return (int)SPI_I2S_ReceiveData16(spi);
+ }
+}
+
+void spi_slave_write(spi_t *obj, int value) {
+ SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+ while (!ssp_writeable(obj));
+ if (obj->bits == SPI_DataSize_8b) {
+ SPI_SendData8(spi, (uint8_t)value);
+ } else {
+ SPI_I2S_SendData16(spi, (uint16_t)value);
+ }
+}
+
+int spi_busy(spi_t *obj) {
+ return ssp_busy(obj);
+}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F3XX/us_ticker.c Tue Apr 08 09:15:06 2014 +0100
@@ -0,0 +1,81 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <stddef.h>
+#include "us_ticker_api.h"
+#include "PeripheralNames.h"
+
+// 32-bit timer selection
+#define TIM_MST TIM2
+#define TIM_MST_IRQ TIM2_IRQn
+#define TIM_MST_RCC RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE)
+
+static int us_ticker_inited = 0;
+
+void us_ticker_init(void) {
+ TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
+
+ if (us_ticker_inited) return;
+ us_ticker_inited = 1;
+
+ // Enable timer clock
+ TIM_MST_RCC;
+
+ // Configure time base
+ TIM_TimeBaseStructInit(&TIM_TimeBaseStructure);
+ TIM_TimeBaseStructure.TIM_Period = 0xFFFFFFFF;
+ TIM_TimeBaseStructure.TIM_Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick
+ TIM_TimeBaseStructure.TIM_ClockDivision = 0;
+ TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
+ TIM_TimeBaseInit(TIM_MST, &TIM_TimeBaseStructure);
+
+ NVIC_SetVector(TIM_MST_IRQ, (uint32_t)us_ticker_irq_handler);
+ NVIC_EnableIRQ(TIM_MST_IRQ);
+
+ // Enable timer
+ TIM_Cmd(TIM_MST, ENABLE);
+}
+
+uint32_t us_ticker_read() {
+ if (!us_ticker_inited) us_ticker_init();
+ return TIM_MST->CNT;
+}
+
+void us_ticker_set_interrupt(unsigned int timestamp) {
+ // Set new output compare value
+ TIM_SetCompare1(TIM_MST, timestamp);
+ // Enable IT
+ TIM_ITConfig(TIM_MST, TIM_IT_CC1, ENABLE);
+}
+
+void us_ticker_disable_interrupt(void) {
+ TIM_ITConfig(TIM_MST, TIM_IT_CC1, DISABLE);
+}
+
+void us_ticker_clear_interrupt(void) {
+ TIM_ClearITPendingBit(TIM_MST, TIM_IT_CC1);
+}