FXOS8700CQ.h

00001 #ifndef FXOS8700CQ_H
00002 #define FXOS8700CQ_H
00003 
00004 #include "mbed.h" // Building this for the mbed platform
00005 
00006 #define I2C_400K 400000
00007 
00008 // FXOS8700CQ I2C address
00009 #define FXOS8700CQ_SLAVE_ADDR0 (0x1E<<1) // with pins SA0=0, SA1=0
00010 #define FXOS8700CQ_SLAVE_ADDR1 (0x1D<<1) // with pins SA0=1, SA1=0
00011 #define FXOS8700CQ_SLAVE_ADDR2 (0x1C<<1) // with pins SA0=0, SA1=1
00012 #define FXOS8700CQ_SLAVE_ADDR3 (0x1F<<1) // with pins SA0=1, SA1=1
00013 
00014 // FXOS8700CQ internal register addresses
00015 #define FXOS8700CQ_STATUS 0x00
00016 #define FXOS8700CQ_OUT_X_MSB 0x01
00017 #define FXOS8700CQ_WHOAMI 0x0D
00018 #define FXOS8700CQ_M_OUT_X_MSB 0x33
00019 
00020 #define FXOS8700CQ_XYZ_DATA_CFG 0x0E
00021 
00022 #define FXOS8700CQ_CTRL_REG1 0x2A
00023 #define FXOS8700CQ_CTRL_REG2 0x2B
00024 #define FXOS8700CQ_CTRL_REG3 0x2C
00025 #define FXOS8700CQ_CTRL_REG4 0x2D
00026 #define FXOS8700CQ_CTRL_REG5 0x2E
00027 
00028 #define FXOS8700CQ_M_CTRL_REG1 0x5B
00029 #define FXOS8700CQ_M_CTRL_REG2 0x5C
00030 #define FXOS8700CQ_M_CTRL_REG3 0x5D
00031 
00032 /* start MPL additions */
00033 //MPL interrupts
00034 #define FXOS8700CQ_INT_SOURCE 0x0C
00035 //#define FXOS8700CQ_CTRL_REG2 0x2B   //bit 2 turns on auto-sleep
00036 //#define FXOS8700CQ_CTRL_REG3 0x2C  //interrupt control register
00037 //#define FXOS8700CQ_CTRL_REG4 0x2D  //interrupt enable register
00038 //#define FXOS8700CQ_CTRL_REG5 0x2E //interrupt routing config register, by default all routed to INT2
00039 
00040 //MPL motion detection
00041 #define FXOS8700CQ_A_FFMT_CFG 0x15
00042 #define FXOS8700CQ_A_FFMT_SRC 0x16
00043 #define FXOS8700CQ_A_FFMT_THS 0x17
00044 #define FXOS8700CQ_A_FFMT_COUNT 0x18
00045 #define FXOS8700CQ_A_FFMT_THS_X_MSB 0x73
00046 #define FXOS8700CQ_A_FFMT_THS_X_LSB 0x74
00047 #define FXOS8700CQ_A_FFMT_THS_Y_MSB 0x75
00048 #define FXOS8700CQ_A_FFMT_THS_Y_LSB 0x76
00049 #define FXOS8700CQ_A_FFMT_THS_Z_MSB 0x77
00050 #define FXOS8700CQ_A_FFMT_THS_Z_LSB 0x78 
00051 /* end MPL additions */
00052 
00053 // FXOS8700CQ configuration macros, per register
00054 
00055 #define FXOS8700CQ_CTRL_REG1_ASLP_RATE2(x) (x << 6) // x is 2-bit
00056 #define FXOS8700CQ_CTRL_REG1_DR3(x) (x << 3) // x is 3-bit
00057 #define FXOS8700CQ_CTRL_REG1_LNOISE (1 << 2)
00058 #define FXOS8700CQ_CTRL_REG1_F_READ (1 << 1)
00059 #define FXOS8700CQ_CTRL_REG1_ACTIVE (1 << 0)
00060 
00061 #define FXOS8700CQ_CTRL_REG2_ST (1 << 7)
00062 #define FXOS8700CQ_CTRL_REG2_RST (1 << 6)
00063 #define FXOS8700CQ_CTRL_REG2_SMODS2(x) (x << 3) // x is 2-bit
00064 #define FXOS8700CQ_CTRL_REG2_SLPE (1 << 2)
00065 #define FXOS8700CQ_CTRL_REG2_MODS2(x) (x << 0) // x is 2-bit
00066 
00067 #define FXOS8700CQ_CTRL_REG3_FIFO_GATE (1 << 7)
00068 #define FXOS8700CQ_CTRL_REG3_WAKE_TRANS (1 << 6)
00069 #define FXOS8700CQ_CTRL_REG3_WAKE_LNDPRT (1 << 5)
00070 #define FXOS8700CQ_CTRL_REG3_WAKE_PULSE (1 << 4)
00071 #define FXOS8700CQ_CTRL_REG3_WAKE_FFMT (1 << 3)
00072 #define FXOS8700CQ_CTRL_REG3_WAKE_A_VECM (1 << 2)
00073 #define FXOS8700CQ_CTRL_REG3_IPOL (1 << 1)
00074 #define FXOS8700CQ_CTRL_REG3_PP_OD (1 << 0)
00075 
00076 #define FXOS8700CQ_CTRL_REG4_INT_EN_ASLP (1 << 7)
00077 #define FXOS8700CQ_CTRL_REG4_INT_EN_FIFO (1 << 6)
00078 #define FXOS8700CQ_CTRL_REG4_INT_EN_TRANS (1 << 5)
00079 #define FXOS8700CQ_CTRL_REG4_INT_EN_LNDPRT (1 << 4)
00080 #define FXOS8700CQ_CTRL_REG4_INT_EN_PULSE (1 << 3)
00081 #define FXOS8700CQ_CTRL_REG4_INT_EN_FFMT (1 << 2)
00082 #define FXOS8700CQ_CTRL_REG4_INT_EN_A_VECM (1 << 1)
00083 #define FXOS8700CQ_CTRL_REG4_INT_EN_DRDY (1 << 0)
00084 
00085 #define FXOS8700CQ_CTRL_REG5_INT_CFG_ASLP (1 << 7)
00086 #define FXOS8700CQ_CTRL_REG5_INT_CFG_FIFO (1 << 6)
00087 #define FXOS8700CQ_CTRL_REG5_INT_CFG_TRANS (1 << 5)
00088 #define FXOS8700CQ_CTRL_REG5_INT_CFG_LNDPRT (1 << 4)
00089 #define FXOS8700CQ_CTRL_REG5_INT_CFG_PULSE (1 << 3)
00090 #define FXOS8700CQ_CTRL_REG5_INT_CFG_FFMT (1 << 2)
00091 #define FXOS8700CQ_CTRL_REG5_INT_CFG_A_VECM (1 << 1)
00092 #define FXOS8700CQ_CTRL_REG5_INT_CFG_DRDY (1 << 0)
00093 
00094 #define FXOS8700CQ_XYZ_DATA_CFG_HPF_OUT (1 << 4)
00095 #define FXOS8700CQ_XYZ_DATA_CFG_FS2(x) (x << 0) // x is 2-bit
00096 
00097 #define FXOS8700CQ_M_CTRL_REG1_M_ACAL (1 << 7)
00098 #define FXOS8700CQ_M_CTRL_REG1_M_RST (1 << 6)
00099 #define FXOS8700CQ_M_CTRL_REG1_M_OST (1 << 5)
00100 #define FXOS8700CQ_M_CTRL_REG1_MO_OS3(x) (x << 2) // x is 3-bit
00101 #define FXOS8700CQ_M_CTRL_REG1_M_HMS2(x) (x << 0) // x is 2-bit
00102 
00103 #define FXOS8700CQ_M_CTRL_REG2_HYB_AUTOINC_MODE (1 << 5)
00104 #define FXOS8700CQ_M_CTRL_REG2_M_MAXMIN_DIS (1 << 4)
00105 #define FXOS8700CQ_M_CTRL_REG2_M_MAXMIN_DIS_THS (1 << 3)
00106 #define FXOS8700CQ_M_CTRL_REG2_M_MAXMIN_RST (1 << 2)
00107 #define FXOS8700CQ_M_CTRL_REG2_M_RST_CNT2(x) (x << 0) // x is 2-bit
00108 
00109 #define FXOS8700CQ_M_CTRL_REG3_M_RAW (1 << 7)
00110 #define FXOS8700CQ_M_CTRL_REG3_M_ASLP_OS3(x) (x << 4) // x is 3-bit
00111 #define FXOS8700CQ_M_CTRL_REG3_M_THS_XYZ_UPDATE (1 << 3)
00112 #define FXOS8700CQ_M_CTRL_REG3_M_ST_Z (1 << 2)
00113 #define FXOS8700CQ_M_CTRL_REG3_M_ST_XY2(x) (x << 0) // x is 2-bit
00114 
00115 // FXOS8700CQ WHOAMI production register value
00116 #define FXOS8700CQ_WHOAMI_VAL 0xC7
00117 
00118 // 6 channels of two bytes = 12 bytes; read from FXOS8700CQ_OUT_X_MSB
00119 #define FXOS8700CQ_READ_LEN 12
00120 
00121 // For processing the accelerometer data to right-justified 2's complement
00122 #define UINT14_MAX 16383
00123 
00124 // TODO: struct to hold the data out of the sensor
00125 typedef struct {
00126     int16_t x;
00127     int16_t y;
00128     int16_t z;
00129 } SRAWDATA;
00130 
00131 
00132 /**
00133 * A driver on top of mbed-I2C to operate the FXOS8700CQ accelerometer/magnetometer
00134 * on the FRDM-K64F.
00135 *
00136 * Code has been completed, but likely not optimized and potentially buggy.
00137 */
00138 class FXOS8700CQ
00139 {
00140 public:
00141     /**
00142     * FXOS8700CQ constructor
00143     *
00144     * @param sda SDA pin
00145     * @param sdl SCL pin
00146     * @param addr address of the I2C peripheral in (7-bit << 1) form
00147     */
00148     FXOS8700CQ(PinName sda, PinName scl, int addr);
00149 
00150     /**
00151     * FXOS8700CQ destructor
00152     */
00153     ~FXOS8700CQ(void);
00154 
00155     void enable(void);
00156     void disable(void);
00157 
00158     /**
00159     * @return the contents of device register FXOS8700CQ_WHOAMI 0x0D,
00160     * should be FXOS8700CQ_WHOAMI_VAL 0xC7
00161     */
00162     uint8_t get_whoami (void);
00163     
00164     /**
00165     * @return the contents of device register FXOS8700CQ_STATUS 0x00
00166     */
00167     uint8_t status (void);
00168 
00169     /**
00170     * Data retrieval from the FXOS8700CQ
00171     *
00172     * @param accel_data destination XYZ accelerometer data struct
00173     * @param magn_data destination XYZ magnetometer data struct
00174     * @return 0 on success, non-zero on failure
00175     */
00176     uint8_t get_data(SRAWDATA *accel_data, SRAWDATA *magn_data);
00177 
00178     /**
00179     * Retrieve the full-range scale value of the accelerometer
00180     *
00181     * @return 2, 4, or 8, depending on part configuration; 0 on error
00182     */
00183     uint8_t get_accel_scale(void);
00184 
00185     /**
00186     * configure external interrupts
00187     *
00188     * @return 2, 4, or 8, depending on part configuration; 0 on error
00189     */
00190     uint8_t config_int(void);
00191     
00192     /**
00193     * configure feature (tap detection, motion detection, etc)
00194     *
00195     * @return 2, 4, or 8, depending on part configuration; 0 on error
00196     */
00197     uint8_t config_feature(void);
00198 
00199     /**
00200     * clear interrupt
00201     *
00202     * @return 2, 4, or 8, depending on part configuration; 0 on error
00203     */    
00204     void clear_int(void);
00205 
00206 private:
00207     I2C dev_i2c; // instance of the mbed I2C class
00208     uint8_t dev_addr; // Device I2C address, in (7-bit << 1) form
00209     bool enabled; // keep track of enable bit of device
00210 
00211     // I2C helper methods
00212     void read_regs(int reg_addr, uint8_t* data, int len);
00213     void write_regs(uint8_t* data, int len);
00214 
00215 };
00216 
00217 #endif