Aleksandrs Gumenuks / MaximInterface_Extended

Extended MaximInterface

Dependents:   mbed_DS28EC20_GPIO

Devices/DS2480B.cpp@0:f77ad7f72d04, 2017-11-06 (annotated)

Committer:
IanBenzMaxim
Date:
Mon Nov 06 14:39:18 2017 -0600
Revision:
0:f77ad7f72d04
Child:
3:f818ea5172ed
Initial commit.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
IanBenzMaxim 0:f77ad7f72d04 1 /*******************************************************************************
IanBenzMaxim 0:f77ad7f72d04 2 * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
IanBenzMaxim 0:f77ad7f72d04 3 *
IanBenzMaxim 0:f77ad7f72d04 4 * Permission is hereby granted, free of charge, to any person obtaining a
IanBenzMaxim 0:f77ad7f72d04 5 * copy of this software and associated documentation files (the "Software"),
IanBenzMaxim 0:f77ad7f72d04 6 * to deal in the Software without restriction, including without limitation
IanBenzMaxim 0:f77ad7f72d04 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
IanBenzMaxim 0:f77ad7f72d04 8 * and/or sell copies of the Software, and to permit persons to whom the
IanBenzMaxim 0:f77ad7f72d04 9 * Software is furnished to do so, subject to the following conditions:
IanBenzMaxim 0:f77ad7f72d04 10 *
IanBenzMaxim 0:f77ad7f72d04 11 * The above copyright notice and this permission notice shall be included
IanBenzMaxim 0:f77ad7f72d04 12 * in all copies or substantial portions of the Software.
IanBenzMaxim 0:f77ad7f72d04 13 *
IanBenzMaxim 0:f77ad7f72d04 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
IanBenzMaxim 0:f77ad7f72d04 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
IanBenzMaxim 0:f77ad7f72d04 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IanBenzMaxim 0:f77ad7f72d04 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
IanBenzMaxim 0:f77ad7f72d04 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
IanBenzMaxim 0:f77ad7f72d04 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
IanBenzMaxim 0:f77ad7f72d04 20 * OTHER DEALINGS IN THE SOFTWARE.
IanBenzMaxim 0:f77ad7f72d04 21 *
IanBenzMaxim 0:f77ad7f72d04 22 * Except as contained in this notice, the name of Maxim Integrated
IanBenzMaxim 0:f77ad7f72d04 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
IanBenzMaxim 0:f77ad7f72d04 24 * Products, Inc. Branding Policy.
IanBenzMaxim 0:f77ad7f72d04 25 *
IanBenzMaxim 0:f77ad7f72d04 26 * The mere transfer of this software does not imply any licenses
IanBenzMaxim 0:f77ad7f72d04 27 * of trade secrets, proprietary technology, copyrights, patents,
IanBenzMaxim 0:f77ad7f72d04 28 * trademarks, maskwork rights, or any other form of intellectual
IanBenzMaxim 0:f77ad7f72d04 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
IanBenzMaxim 0:f77ad7f72d04 30 * ownership rights.
IanBenzMaxim 0:f77ad7f72d04 31 *******************************************************************************/
IanBenzMaxim 0:f77ad7f72d04 32
IanBenzMaxim 0:f77ad7f72d04 33 #include <MaximInterface/Utilities/Error.hpp>
IanBenzMaxim 0:f77ad7f72d04 34 #include "DS2480B.hpp"
IanBenzMaxim 0:f77ad7f72d04 35
IanBenzMaxim 0:f77ad7f72d04 36 // Mode Commands
IanBenzMaxim 0:f77ad7f72d04 37 #define MODE_DATA 0xE1
IanBenzMaxim 0:f77ad7f72d04 38 #define MODE_COMMAND 0xE3
IanBenzMaxim 0:f77ad7f72d04 39 #define MODE_STOP_PULSE 0xF1
IanBenzMaxim 0:f77ad7f72d04 40
IanBenzMaxim 0:f77ad7f72d04 41 // Return byte value
IanBenzMaxim 0:f77ad7f72d04 42 #define RB_CHIPID_MASK 0x1C
IanBenzMaxim 0:f77ad7f72d04 43 #define RB_RESET_MASK 0x03
IanBenzMaxim 0:f77ad7f72d04 44 #define RB_1WIRESHORT 0x00
IanBenzMaxim 0:f77ad7f72d04 45 #define RB_PRESENCE 0x01
IanBenzMaxim 0:f77ad7f72d04 46 #define RB_ALARMPRESENCE 0x02
IanBenzMaxim 0:f77ad7f72d04 47 #define RB_NOPRESENCE 0x03
IanBenzMaxim 0:f77ad7f72d04 48
IanBenzMaxim 0:f77ad7f72d04 49 #define RB_BIT_MASK 0x03
IanBenzMaxim 0:f77ad7f72d04 50 #define RB_BIT_ONE 0x03
IanBenzMaxim 0:f77ad7f72d04 51 #define RB_BIT_ZERO 0x00
IanBenzMaxim 0:f77ad7f72d04 52
IanBenzMaxim 0:f77ad7f72d04 53 // Masks for all bit ranges
IanBenzMaxim 0:f77ad7f72d04 54 #define CMD_MASK 0x80
IanBenzMaxim 0:f77ad7f72d04 55 #define FUNCTSEL_MASK 0x60
IanBenzMaxim 0:f77ad7f72d04 56 #define BITPOL_MASK 0x10
IanBenzMaxim 0:f77ad7f72d04 57 #define SPEEDSEL_MASK 0x0C
IanBenzMaxim 0:f77ad7f72d04 58 #define MODSEL_MASK 0x02
IanBenzMaxim 0:f77ad7f72d04 59 #define PARMSEL_MASK 0x70
IanBenzMaxim 0:f77ad7f72d04 60 #define PARMSET_MASK 0x0E
IanBenzMaxim 0:f77ad7f72d04 61
IanBenzMaxim 0:f77ad7f72d04 62 // Command or config bit
IanBenzMaxim 0:f77ad7f72d04 63 #define CMD_COMM 0x81
IanBenzMaxim 0:f77ad7f72d04 64 #define CMD_CONFIG 0x01
IanBenzMaxim 0:f77ad7f72d04 65
IanBenzMaxim 0:f77ad7f72d04 66 // Function select bits
IanBenzMaxim 0:f77ad7f72d04 67 #define FUNCTSEL_BIT 0x00
IanBenzMaxim 0:f77ad7f72d04 68 #define FUNCTSEL_SEARCHON 0x30
IanBenzMaxim 0:f77ad7f72d04 69 #define FUNCTSEL_SEARCHOFF 0x20
IanBenzMaxim 0:f77ad7f72d04 70 #define FUNCTSEL_RESET 0x40
IanBenzMaxim 0:f77ad7f72d04 71 #define FUNCTSEL_CHMOD 0x60
IanBenzMaxim 0:f77ad7f72d04 72
IanBenzMaxim 0:f77ad7f72d04 73 // Bit polarity/Pulse voltage bits
IanBenzMaxim 0:f77ad7f72d04 74 #define BITPOL_ONE 0x10
IanBenzMaxim 0:f77ad7f72d04 75 #define BITPOL_ZERO 0x00
IanBenzMaxim 0:f77ad7f72d04 76 #define BITPOL_5V 0x00
IanBenzMaxim 0:f77ad7f72d04 77 #define BITPOL_12V 0x10
IanBenzMaxim 0:f77ad7f72d04 78
IanBenzMaxim 0:f77ad7f72d04 79 // One Wire speed bits
IanBenzMaxim 0:f77ad7f72d04 80 #define SPEEDSEL_STD 0x00
IanBenzMaxim 0:f77ad7f72d04 81 #define SPEEDSEL_FLEX 0x04
IanBenzMaxim 0:f77ad7f72d04 82 #define SPEEDSEL_OD 0x08
IanBenzMaxim 0:f77ad7f72d04 83 #define SPEEDSEL_PULSE 0x0C
IanBenzMaxim 0:f77ad7f72d04 84
IanBenzMaxim 0:f77ad7f72d04 85 // Data/Command mode select bits
IanBenzMaxim 0:f77ad7f72d04 86 #define MODSEL_DATA 0x00
IanBenzMaxim 0:f77ad7f72d04 87 #define MODSEL_COMMAND 0x02
IanBenzMaxim 0:f77ad7f72d04 88
IanBenzMaxim 0:f77ad7f72d04 89 // 5V Follow Pulse select bits
IanBenzMaxim 0:f77ad7f72d04 90 #define PRIME5V_TRUE 0x02
IanBenzMaxim 0:f77ad7f72d04 91 #define PRIME5V_FALSE 0x00
IanBenzMaxim 0:f77ad7f72d04 92
IanBenzMaxim 0:f77ad7f72d04 93 // Parameter select bits
IanBenzMaxim 0:f77ad7f72d04 94 #define PARMSEL_PARMREAD 0x00
IanBenzMaxim 0:f77ad7f72d04 95 #define PARMSEL_SLEW 0x10
IanBenzMaxim 0:f77ad7f72d04 96 #define PARMSEL_12VPULSE 0x20
IanBenzMaxim 0:f77ad7f72d04 97 #define PARMSEL_5VPULSE 0x30
IanBenzMaxim 0:f77ad7f72d04 98 #define PARMSEL_WRITE1LOW 0x40
IanBenzMaxim 0:f77ad7f72d04 99 #define PARMSEL_SAMPLEOFFSET 0x50
IanBenzMaxim 0:f77ad7f72d04 100 #define PARMSEL_ACTIVEPULLUPTIME 0x60
IanBenzMaxim 0:f77ad7f72d04 101 #define PARMSEL_BAUDRATE 0x70
IanBenzMaxim 0:f77ad7f72d04 102
IanBenzMaxim 0:f77ad7f72d04 103 // Pull down slew rate.
IanBenzMaxim 0:f77ad7f72d04 104 #define PARMSET_Slew15Vus 0x00
IanBenzMaxim 0:f77ad7f72d04 105 #define PARMSET_Slew2p2Vus 0x02
IanBenzMaxim 0:f77ad7f72d04 106 #define PARMSET_Slew1p65Vus 0x04
IanBenzMaxim 0:f77ad7f72d04 107 #define PARMSET_Slew1p37Vus 0x06
IanBenzMaxim 0:f77ad7f72d04 108 #define PARMSET_Slew1p1Vus 0x08
IanBenzMaxim 0:f77ad7f72d04 109 #define PARMSET_Slew0p83Vus 0x0A
IanBenzMaxim 0:f77ad7f72d04 110 #define PARMSET_Slew0p7Vus 0x0C
IanBenzMaxim 0:f77ad7f72d04 111 #define PARMSET_Slew0p55Vus 0x0E
IanBenzMaxim 0:f77ad7f72d04 112
IanBenzMaxim 0:f77ad7f72d04 113 // 12V programming pulse time table
IanBenzMaxim 0:f77ad7f72d04 114 #define PARMSET_32us 0x00
IanBenzMaxim 0:f77ad7f72d04 115 #define PARMSET_64us 0x02
IanBenzMaxim 0:f77ad7f72d04 116 #define PARMSET_128us 0x04
IanBenzMaxim 0:f77ad7f72d04 117 #define PARMSET_256us 0x06
IanBenzMaxim 0:f77ad7f72d04 118 #define PARMSET_512us 0x08
IanBenzMaxim 0:f77ad7f72d04 119 #define PARMSET_1024us 0x0A
IanBenzMaxim 0:f77ad7f72d04 120 #define PARMSET_2048us 0x0C
IanBenzMaxim 0:f77ad7f72d04 121 #define PARMSET_infinite 0x0E
IanBenzMaxim 0:f77ad7f72d04 122
IanBenzMaxim 0:f77ad7f72d04 123 // 5V strong pull up pulse time table
IanBenzMaxim 0:f77ad7f72d04 124 #define PARMSET_16p4ms 0x00
IanBenzMaxim 0:f77ad7f72d04 125 #define PARMSET_65p5ms 0x02
IanBenzMaxim 0:f77ad7f72d04 126 #define PARMSET_131ms 0x04
IanBenzMaxim 0:f77ad7f72d04 127 #define PARMSET_262ms 0x06
IanBenzMaxim 0:f77ad7f72d04 128 #define PARMSET_524ms 0x08
IanBenzMaxim 0:f77ad7f72d04 129 #define PARMSET_1p05s 0x0A
IanBenzMaxim 0:f77ad7f72d04 130 #define PARMSET_dynamic 0x0C
IanBenzMaxim 0:f77ad7f72d04 131 #define PARMSET_infinite 0x0E
IanBenzMaxim 0:f77ad7f72d04 132
IanBenzMaxim 0:f77ad7f72d04 133 // Write 1 low time
IanBenzMaxim 0:f77ad7f72d04 134 #define PARMSET_Write8us 0x00
IanBenzMaxim 0:f77ad7f72d04 135 #define PARMSET_Write9us 0x02
IanBenzMaxim 0:f77ad7f72d04 136 #define PARMSET_Write10us 0x04
IanBenzMaxim 0:f77ad7f72d04 137 #define PARMSET_Write11us 0x06
IanBenzMaxim 0:f77ad7f72d04 138 #define PARMSET_Write12us 0x08
IanBenzMaxim 0:f77ad7f72d04 139 #define PARMSET_Write13us 0x0A
IanBenzMaxim 0:f77ad7f72d04 140 #define PARMSET_Write14us 0x0C
IanBenzMaxim 0:f77ad7f72d04 141 #define PARMSET_Write15us 0x0E
IanBenzMaxim 0:f77ad7f72d04 142
IanBenzMaxim 0:f77ad7f72d04 143 // Data sample offset and Write 0 recovery time
IanBenzMaxim 0:f77ad7f72d04 144 #define PARMSET_SampOff3us 0x00
IanBenzMaxim 0:f77ad7f72d04 145 #define PARMSET_SampOff4us 0x02
IanBenzMaxim 0:f77ad7f72d04 146 #define PARMSET_SampOff5us 0x04
IanBenzMaxim 0:f77ad7f72d04 147 #define PARMSET_SampOff6us 0x06
IanBenzMaxim 0:f77ad7f72d04 148 #define PARMSET_SampOff7us 0x08
IanBenzMaxim 0:f77ad7f72d04 149 #define PARMSET_SampOff8us 0x0A
IanBenzMaxim 0:f77ad7f72d04 150 #define PARMSET_SampOff9us 0x0C
IanBenzMaxim 0:f77ad7f72d04 151 #define PARMSET_SampOff10us 0x0E
IanBenzMaxim 0:f77ad7f72d04 152
IanBenzMaxim 0:f77ad7f72d04 153 // Active pull up on time
IanBenzMaxim 0:f77ad7f72d04 154 #define PARMSET_PullUp0p0us 0x00
IanBenzMaxim 0:f77ad7f72d04 155 #define PARMSET_PullUp0p5us 0x02
IanBenzMaxim 0:f77ad7f72d04 156 #define PARMSET_PullUp1p0us 0x04
IanBenzMaxim 0:f77ad7f72d04 157 #define PARMSET_PullUp1p5us 0x06
IanBenzMaxim 0:f77ad7f72d04 158 #define PARMSET_PullUp2p0us 0x08
IanBenzMaxim 0:f77ad7f72d04 159 #define PARMSET_PullUp2p5us 0x0A
IanBenzMaxim 0:f77ad7f72d04 160 #define PARMSET_PullUp3p0us 0x0C
IanBenzMaxim 0:f77ad7f72d04 161 #define PARMSET_PullUp3p5us 0x0E
IanBenzMaxim 0:f77ad7f72d04 162
IanBenzMaxim 0:f77ad7f72d04 163 // DS2480B program voltage available
IanBenzMaxim 0:f77ad7f72d04 164 #define DS2480BPROG_MASK 0x20
IanBenzMaxim 0:f77ad7f72d04 165
IanBenzMaxim 0:f77ad7f72d04 166 namespace MaximInterface {
IanBenzMaxim 0:f77ad7f72d04 167
IanBenzMaxim 0:f77ad7f72d04 168 error_code DS2480B::initialize() {
IanBenzMaxim 0:f77ad7f72d04 169 // reset modes
IanBenzMaxim 0:f77ad7f72d04 170 level = NormalLevel;
IanBenzMaxim 0:f77ad7f72d04 171 baud = Baud9600bps;
IanBenzMaxim 0:f77ad7f72d04 172 mode = MODSEL_COMMAND;
IanBenzMaxim 0:f77ad7f72d04 173 speed = SPEEDSEL_FLEX;
IanBenzMaxim 0:f77ad7f72d04 174
IanBenzMaxim 0:f77ad7f72d04 175 // set the baud rate to 9600
IanBenzMaxim 0:f77ad7f72d04 176 error_code result = setComBaud(baud);
IanBenzMaxim 0:f77ad7f72d04 177 if (result) {
IanBenzMaxim 0:f77ad7f72d04 178 return result;
IanBenzMaxim 0:f77ad7f72d04 179 }
IanBenzMaxim 0:f77ad7f72d04 180
IanBenzMaxim 0:f77ad7f72d04 181 // send a break to reset the DS2480B
IanBenzMaxim 0:f77ad7f72d04 182 result = breakCom();
IanBenzMaxim 0:f77ad7f72d04 183 if (result) {
IanBenzMaxim 0:f77ad7f72d04 184 return result;
IanBenzMaxim 0:f77ad7f72d04 185 }
IanBenzMaxim 0:f77ad7f72d04 186
IanBenzMaxim 0:f77ad7f72d04 187 // delay to let line settle
IanBenzMaxim 0:f77ad7f72d04 188 (*sleep)(2);
IanBenzMaxim 0:f77ad7f72d04 189
IanBenzMaxim 0:f77ad7f72d04 190 // flush the buffers
IanBenzMaxim 0:f77ad7f72d04 191 result = uart->clearReadBuffer();
IanBenzMaxim 0:f77ad7f72d04 192 if (result) {
IanBenzMaxim 0:f77ad7f72d04 193 return result;
IanBenzMaxim 0:f77ad7f72d04 194 }
IanBenzMaxim 0:f77ad7f72d04 195
IanBenzMaxim 0:f77ad7f72d04 196 // send the timing byte
IanBenzMaxim 0:f77ad7f72d04 197 uint_least8_t packet[5];
IanBenzMaxim 0:f77ad7f72d04 198 packet[0] = 0xC1;
IanBenzMaxim 0:f77ad7f72d04 199 result = uart->writeBlock(packet, 1);
IanBenzMaxim 0:f77ad7f72d04 200 if (result) {
IanBenzMaxim 0:f77ad7f72d04 201 return result;
IanBenzMaxim 0:f77ad7f72d04 202 }
IanBenzMaxim 0:f77ad7f72d04 203
IanBenzMaxim 0:f77ad7f72d04 204 // delay to let line settle
IanBenzMaxim 0:f77ad7f72d04 205 (*sleep)(2);
IanBenzMaxim 0:f77ad7f72d04 206
IanBenzMaxim 0:f77ad7f72d04 207 // set the FLEX configuration parameters
IanBenzMaxim 0:f77ad7f72d04 208 // default PDSRC = 1.37Vus
IanBenzMaxim 0:f77ad7f72d04 209 int packetLen = 0;
IanBenzMaxim 0:f77ad7f72d04 210 packet[packetLen++] = CMD_CONFIG | PARMSEL_SLEW | PARMSET_Slew1p37Vus;
IanBenzMaxim 0:f77ad7f72d04 211 // default W1LT = 10us
IanBenzMaxim 0:f77ad7f72d04 212 packet[packetLen++] = CMD_CONFIG | PARMSEL_WRITE1LOW | PARMSET_Write10us;
IanBenzMaxim 0:f77ad7f72d04 213 // default DSO/WORT = 8us
IanBenzMaxim 0:f77ad7f72d04 214 packet[packetLen++] = CMD_CONFIG | PARMSEL_SAMPLEOFFSET | PARMSET_SampOff8us;
IanBenzMaxim 0:f77ad7f72d04 215
IanBenzMaxim 0:f77ad7f72d04 216 // construct the command to read the baud rate (to test command block)
IanBenzMaxim 0:f77ad7f72d04 217 packet[packetLen++] = CMD_CONFIG | PARMSEL_PARMREAD | (PARMSEL_BAUDRATE >> 3);
IanBenzMaxim 0:f77ad7f72d04 218
IanBenzMaxim 0:f77ad7f72d04 219 // also do 1 bit operation (to test 1-Wire block)
IanBenzMaxim 0:f77ad7f72d04 220 packet[packetLen++] = CMD_COMM | FUNCTSEL_BIT | baud | BITPOL_ONE;
IanBenzMaxim 0:f77ad7f72d04 221
IanBenzMaxim 0:f77ad7f72d04 222 // flush the buffers
IanBenzMaxim 0:f77ad7f72d04 223 result = uart->clearReadBuffer();
IanBenzMaxim 0:f77ad7f72d04 224 if (result) {
IanBenzMaxim 0:f77ad7f72d04 225 return result;
IanBenzMaxim 0:f77ad7f72d04 226 }
IanBenzMaxim 0:f77ad7f72d04 227
IanBenzMaxim 0:f77ad7f72d04 228 // send the packet
IanBenzMaxim 0:f77ad7f72d04 229 result = uart->writeBlock(packet, packetLen);
IanBenzMaxim 0:f77ad7f72d04 230 if (result) {
IanBenzMaxim 0:f77ad7f72d04 231 return result;
IanBenzMaxim 0:f77ad7f72d04 232 }
IanBenzMaxim 0:f77ad7f72d04 233
IanBenzMaxim 0:f77ad7f72d04 234 // read back the response
IanBenzMaxim 0:f77ad7f72d04 235 result = uart->readBlock(packet, sizeof(packet) / sizeof(packet[0]));
IanBenzMaxim 0:f77ad7f72d04 236 if (result) {
IanBenzMaxim 0:f77ad7f72d04 237 return result;
IanBenzMaxim 0:f77ad7f72d04 238 }
IanBenzMaxim 0:f77ad7f72d04 239
IanBenzMaxim 0:f77ad7f72d04 240 // look at the baud rate and bit operation
IanBenzMaxim 0:f77ad7f72d04 241 // to see if the response makes sense
IanBenzMaxim 0:f77ad7f72d04 242 if (!(((packet[3] & 0xF1) == 0x00) && ((packet[3] & 0x0E) == baud) &&
IanBenzMaxim 0:f77ad7f72d04 243 ((packet[4] & 0xF0) == 0x90) && ((packet[4] & 0x0C) == baud))) {
IanBenzMaxim 0:f77ad7f72d04 244 result = make_error_code(HardwareError);
IanBenzMaxim 0:f77ad7f72d04 245 }
IanBenzMaxim 0:f77ad7f72d04 246
IanBenzMaxim 0:f77ad7f72d04 247 return result;
IanBenzMaxim 0:f77ad7f72d04 248 }
IanBenzMaxim 0:f77ad7f72d04 249
IanBenzMaxim 0:f77ad7f72d04 250 error_code DS2480B::reset() {
IanBenzMaxim 0:f77ad7f72d04 251 uint_least8_t packet[2];
IanBenzMaxim 0:f77ad7f72d04 252 int packetLen = 0;
IanBenzMaxim 0:f77ad7f72d04 253
IanBenzMaxim 0:f77ad7f72d04 254 // check for correct mode
IanBenzMaxim 0:f77ad7f72d04 255 if (mode != MODSEL_COMMAND) {
IanBenzMaxim 0:f77ad7f72d04 256 mode = MODSEL_COMMAND;
IanBenzMaxim 0:f77ad7f72d04 257 packet[packetLen++] = MODE_COMMAND;
IanBenzMaxim 0:f77ad7f72d04 258 }
IanBenzMaxim 0:f77ad7f72d04 259
IanBenzMaxim 0:f77ad7f72d04 260 // construct the command
IanBenzMaxim 0:f77ad7f72d04 261 packet[packetLen++] = (CMD_COMM | FUNCTSEL_RESET | speed);
IanBenzMaxim 0:f77ad7f72d04 262
IanBenzMaxim 0:f77ad7f72d04 263 // flush the buffers
IanBenzMaxim 0:f77ad7f72d04 264 error_code result = uart->clearReadBuffer();
IanBenzMaxim 0:f77ad7f72d04 265 if (result) {
IanBenzMaxim 0:f77ad7f72d04 266 return result;
IanBenzMaxim 0:f77ad7f72d04 267 }
IanBenzMaxim 0:f77ad7f72d04 268
IanBenzMaxim 0:f77ad7f72d04 269 // send the packet
IanBenzMaxim 0:f77ad7f72d04 270 result = uart->writeBlock(packet, packetLen);
IanBenzMaxim 0:f77ad7f72d04 271 if (result) {
IanBenzMaxim 0:f77ad7f72d04 272 return result;
IanBenzMaxim 0:f77ad7f72d04 273 }
IanBenzMaxim 0:f77ad7f72d04 274
IanBenzMaxim 0:f77ad7f72d04 275 // read back the 1 byte response
IanBenzMaxim 0:f77ad7f72d04 276 result = uart->readBlock(packet, 1);
IanBenzMaxim 0:f77ad7f72d04 277 if (result) {
IanBenzMaxim 0:f77ad7f72d04 278 return result;
IanBenzMaxim 0:f77ad7f72d04 279 }
IanBenzMaxim 0:f77ad7f72d04 280
IanBenzMaxim 0:f77ad7f72d04 281 // make sure this byte looks like a reset byte
IanBenzMaxim 0:f77ad7f72d04 282 if ((packet[0] & RB_RESET_MASK) == RB_1WIRESHORT) {
IanBenzMaxim 0:f77ad7f72d04 283 result = make_error_code(ShortDetectedError);
IanBenzMaxim 0:f77ad7f72d04 284 }
IanBenzMaxim 0:f77ad7f72d04 285 else if ((packet[0] & RB_RESET_MASK) == RB_NOPRESENCE) {
IanBenzMaxim 0:f77ad7f72d04 286 result = make_error_code(NoSlaveError);
IanBenzMaxim 0:f77ad7f72d04 287 }
IanBenzMaxim 0:f77ad7f72d04 288
IanBenzMaxim 0:f77ad7f72d04 289 return result;
IanBenzMaxim 0:f77ad7f72d04 290 }
IanBenzMaxim 0:f77ad7f72d04 291
IanBenzMaxim 0:f77ad7f72d04 292 error_code DS2480B::touchBitSetLevel(bool & sendRecvBit, Level afterLevel) {
IanBenzMaxim 0:f77ad7f72d04 293 uint_least8_t packet[2];
IanBenzMaxim 0:f77ad7f72d04 294 int packetLen = 0;
IanBenzMaxim 0:f77ad7f72d04 295
IanBenzMaxim 0:f77ad7f72d04 296 // check for correct mode
IanBenzMaxim 0:f77ad7f72d04 297 if (mode != MODSEL_COMMAND) {
IanBenzMaxim 0:f77ad7f72d04 298 mode = MODSEL_COMMAND;
IanBenzMaxim 0:f77ad7f72d04 299 packet[packetLen++] = MODE_COMMAND;
IanBenzMaxim 0:f77ad7f72d04 300 }
IanBenzMaxim 0:f77ad7f72d04 301
IanBenzMaxim 0:f77ad7f72d04 302 // construct the command
IanBenzMaxim 0:f77ad7f72d04 303 packet[packetLen++] = (sendRecvBit ? BITPOL_ONE : BITPOL_ZERO) | CMD_COMM |
IanBenzMaxim 0:f77ad7f72d04 304 FUNCTSEL_BIT | speed;
IanBenzMaxim 0:f77ad7f72d04 305
IanBenzMaxim 0:f77ad7f72d04 306 // flush the buffers
IanBenzMaxim 0:f77ad7f72d04 307 error_code result = uart->clearReadBuffer();
IanBenzMaxim 0:f77ad7f72d04 308 if (result) {
IanBenzMaxim 0:f77ad7f72d04 309 return result;
IanBenzMaxim 0:f77ad7f72d04 310 }
IanBenzMaxim 0:f77ad7f72d04 311
IanBenzMaxim 0:f77ad7f72d04 312 // send the packet
IanBenzMaxim 0:f77ad7f72d04 313 result = uart->writeBlock(packet, packetLen);
IanBenzMaxim 0:f77ad7f72d04 314 if (result) {
IanBenzMaxim 0:f77ad7f72d04 315 return result;
IanBenzMaxim 0:f77ad7f72d04 316 }
IanBenzMaxim 0:f77ad7f72d04 317
IanBenzMaxim 0:f77ad7f72d04 318 // read back the response
IanBenzMaxim 0:f77ad7f72d04 319 result = uart->readBlock(packet, 1);
IanBenzMaxim 0:f77ad7f72d04 320 if (result) {
IanBenzMaxim 0:f77ad7f72d04 321 return result;
IanBenzMaxim 0:f77ad7f72d04 322 }
IanBenzMaxim 0:f77ad7f72d04 323
IanBenzMaxim 0:f77ad7f72d04 324 // interpret the response
IanBenzMaxim 0:f77ad7f72d04 325 if ((packet[0] & 0xE0) == 0x80) {
IanBenzMaxim 0:f77ad7f72d04 326 sendRecvBit = ((packet[0] & RB_BIT_MASK) == RB_BIT_ONE);
IanBenzMaxim 0:f77ad7f72d04 327 result = setLevel(afterLevel);
IanBenzMaxim 0:f77ad7f72d04 328 } else {
IanBenzMaxim 0:f77ad7f72d04 329 result = make_error_code(HardwareError);
IanBenzMaxim 0:f77ad7f72d04 330 }
IanBenzMaxim 0:f77ad7f72d04 331
IanBenzMaxim 0:f77ad7f72d04 332 return result;
IanBenzMaxim 0:f77ad7f72d04 333 }
IanBenzMaxim 0:f77ad7f72d04 334
IanBenzMaxim 0:f77ad7f72d04 335 error_code DS2480B::writeByteSetLevel(uint_least8_t sendByte,
IanBenzMaxim 0:f77ad7f72d04 336 Level afterLevel) {
IanBenzMaxim 0:f77ad7f72d04 337 uint_least8_t packet[3];
IanBenzMaxim 0:f77ad7f72d04 338 int packetLen = 0;
IanBenzMaxim 0:f77ad7f72d04 339
IanBenzMaxim 0:f77ad7f72d04 340 // check for correct mode
IanBenzMaxim 0:f77ad7f72d04 341 if (mode != MODSEL_DATA) {
IanBenzMaxim 0:f77ad7f72d04 342 mode = MODSEL_DATA;
IanBenzMaxim 0:f77ad7f72d04 343 packet[packetLen++] = MODE_DATA;
IanBenzMaxim 0:f77ad7f72d04 344 }
IanBenzMaxim 0:f77ad7f72d04 345
IanBenzMaxim 0:f77ad7f72d04 346 // add the byte to send
IanBenzMaxim 0:f77ad7f72d04 347 packet[packetLen++] = sendByte;
IanBenzMaxim 0:f77ad7f72d04 348
IanBenzMaxim 0:f77ad7f72d04 349 // check for duplication of data that looks like COMMAND mode
IanBenzMaxim 0:f77ad7f72d04 350 if (sendByte == MODE_COMMAND) {
IanBenzMaxim 0:f77ad7f72d04 351 packet[packetLen++] = sendByte;
IanBenzMaxim 0:f77ad7f72d04 352 }
IanBenzMaxim 0:f77ad7f72d04 353
IanBenzMaxim 0:f77ad7f72d04 354 // flush the buffers
IanBenzMaxim 0:f77ad7f72d04 355 error_code result = uart->clearReadBuffer();
IanBenzMaxim 0:f77ad7f72d04 356 if (result) {
IanBenzMaxim 0:f77ad7f72d04 357 return result;
IanBenzMaxim 0:f77ad7f72d04 358 }
IanBenzMaxim 0:f77ad7f72d04 359
IanBenzMaxim 0:f77ad7f72d04 360 // send the packet
IanBenzMaxim 0:f77ad7f72d04 361 result = uart->writeBlock(packet, packetLen);
IanBenzMaxim 0:f77ad7f72d04 362 if (result) {
IanBenzMaxim 0:f77ad7f72d04 363 return result;
IanBenzMaxim 0:f77ad7f72d04 364 }
IanBenzMaxim 0:f77ad7f72d04 365
IanBenzMaxim 0:f77ad7f72d04 366 // read back the 1 byte response
IanBenzMaxim 0:f77ad7f72d04 367 result = uart->readBlock(packet, 1);
IanBenzMaxim 0:f77ad7f72d04 368 if (result) {
IanBenzMaxim 0:f77ad7f72d04 369 return result;
IanBenzMaxim 0:f77ad7f72d04 370 }
IanBenzMaxim 0:f77ad7f72d04 371
IanBenzMaxim 0:f77ad7f72d04 372 if (packet[0] == sendByte) {
IanBenzMaxim 0:f77ad7f72d04 373 result = setLevel(afterLevel);
IanBenzMaxim 0:f77ad7f72d04 374 } else {
IanBenzMaxim 0:f77ad7f72d04 375 result = make_error_code(HardwareError);
IanBenzMaxim 0:f77ad7f72d04 376 }
IanBenzMaxim 0:f77ad7f72d04 377
IanBenzMaxim 0:f77ad7f72d04 378 return result;
IanBenzMaxim 0:f77ad7f72d04 379 }
IanBenzMaxim 0:f77ad7f72d04 380
IanBenzMaxim 0:f77ad7f72d04 381 error_code DS2480B::readByteSetLevel(uint_least8_t & recvByte,
IanBenzMaxim 0:f77ad7f72d04 382 Level afterLevel) {
IanBenzMaxim 0:f77ad7f72d04 383 uint_least8_t packet[2];
IanBenzMaxim 0:f77ad7f72d04 384 int packetLen = 0;
IanBenzMaxim 0:f77ad7f72d04 385
IanBenzMaxim 0:f77ad7f72d04 386 // check for correct mode
IanBenzMaxim 0:f77ad7f72d04 387 if (mode != MODSEL_DATA) {
IanBenzMaxim 0:f77ad7f72d04 388 mode = MODSEL_DATA;
IanBenzMaxim 0:f77ad7f72d04 389 packet[packetLen++] = MODE_DATA;
IanBenzMaxim 0:f77ad7f72d04 390 }
IanBenzMaxim 0:f77ad7f72d04 391
IanBenzMaxim 0:f77ad7f72d04 392 // add the byte to send
IanBenzMaxim 0:f77ad7f72d04 393 packet[packetLen++] = 0xFF;
IanBenzMaxim 0:f77ad7f72d04 394
IanBenzMaxim 0:f77ad7f72d04 395 // flush the buffers
IanBenzMaxim 0:f77ad7f72d04 396 error_code result = uart->clearReadBuffer();
IanBenzMaxim 0:f77ad7f72d04 397 if (result) {
IanBenzMaxim 0:f77ad7f72d04 398 return result;
IanBenzMaxim 0:f77ad7f72d04 399 }
IanBenzMaxim 0:f77ad7f72d04 400
IanBenzMaxim 0:f77ad7f72d04 401 // send the packet
IanBenzMaxim 0:f77ad7f72d04 402 result = uart->writeBlock(packet, packetLen);
IanBenzMaxim 0:f77ad7f72d04 403 if (result) {
IanBenzMaxim 0:f77ad7f72d04 404 return result;
IanBenzMaxim 0:f77ad7f72d04 405 }
IanBenzMaxim 0:f77ad7f72d04 406
IanBenzMaxim 0:f77ad7f72d04 407 // read back the 1 byte response
IanBenzMaxim 0:f77ad7f72d04 408 result = uart->readBlock(packet, 1);
IanBenzMaxim 0:f77ad7f72d04 409 if (result) {
IanBenzMaxim 0:f77ad7f72d04 410 return result;
IanBenzMaxim 0:f77ad7f72d04 411 }
IanBenzMaxim 0:f77ad7f72d04 412
IanBenzMaxim 0:f77ad7f72d04 413 recvByte = packet[0];
IanBenzMaxim 0:f77ad7f72d04 414 result = setLevel(afterLevel);
IanBenzMaxim 0:f77ad7f72d04 415
IanBenzMaxim 0:f77ad7f72d04 416 return result;
IanBenzMaxim 0:f77ad7f72d04 417 }
IanBenzMaxim 0:f77ad7f72d04 418
IanBenzMaxim 0:f77ad7f72d04 419 error_code DS2480B::setSpeed(Speed newSpeed) {
IanBenzMaxim 0:f77ad7f72d04 420 error_code result;
IanBenzMaxim 0:f77ad7f72d04 421 bool setSpeed = false;
IanBenzMaxim 0:f77ad7f72d04 422
IanBenzMaxim 0:f77ad7f72d04 423 // check if supported speed
IanBenzMaxim 0:f77ad7f72d04 424 switch (newSpeed) {
IanBenzMaxim 0:f77ad7f72d04 425 case OverdriveSpeed:
IanBenzMaxim 0:f77ad7f72d04 426 // check if change from current mode
IanBenzMaxim 0:f77ad7f72d04 427 if (speed != SPEEDSEL_OD) {
IanBenzMaxim 0:f77ad7f72d04 428 result = changeBaud(Baud115200bps);
IanBenzMaxim 0:f77ad7f72d04 429 if (!result) {
IanBenzMaxim 0:f77ad7f72d04 430 speed = SPEEDSEL_OD;
IanBenzMaxim 0:f77ad7f72d04 431 setSpeed = true;
IanBenzMaxim 0:f77ad7f72d04 432 }
IanBenzMaxim 0:f77ad7f72d04 433 }
IanBenzMaxim 0:f77ad7f72d04 434 break;
IanBenzMaxim 0:f77ad7f72d04 435
IanBenzMaxim 0:f77ad7f72d04 436 case StandardSpeed:
IanBenzMaxim 0:f77ad7f72d04 437 // check if change from current mode
IanBenzMaxim 0:f77ad7f72d04 438 if (speed != SPEEDSEL_STD) {
IanBenzMaxim 0:f77ad7f72d04 439 result = changeBaud(Baud9600bps);
IanBenzMaxim 0:f77ad7f72d04 440 if (!result) {
IanBenzMaxim 0:f77ad7f72d04 441 speed = SPEEDSEL_STD;
IanBenzMaxim 0:f77ad7f72d04 442 setSpeed = true;
IanBenzMaxim 0:f77ad7f72d04 443 }
IanBenzMaxim 0:f77ad7f72d04 444 }
IanBenzMaxim 0:f77ad7f72d04 445 break;
IanBenzMaxim 0:f77ad7f72d04 446
IanBenzMaxim 0:f77ad7f72d04 447 default:
IanBenzMaxim 0:f77ad7f72d04 448 result = make_error_code(InvalidSpeedError);
IanBenzMaxim 0:f77ad7f72d04 449 break;
IanBenzMaxim 0:f77ad7f72d04 450 }
IanBenzMaxim 0:f77ad7f72d04 451
IanBenzMaxim 0:f77ad7f72d04 452 // if baud rate is set correctly then change DS2480 speed
IanBenzMaxim 0:f77ad7f72d04 453 if (setSpeed) {
IanBenzMaxim 0:f77ad7f72d04 454 uint_least8_t packet[2];
IanBenzMaxim 0:f77ad7f72d04 455 int packetLen = 0;
IanBenzMaxim 0:f77ad7f72d04 456
IanBenzMaxim 0:f77ad7f72d04 457 // check if correct mode
IanBenzMaxim 0:f77ad7f72d04 458 if (mode != MODSEL_COMMAND) {
IanBenzMaxim 0:f77ad7f72d04 459 mode = MODSEL_COMMAND;
IanBenzMaxim 0:f77ad7f72d04 460 packet[packetLen++] = MODE_COMMAND;
IanBenzMaxim 0:f77ad7f72d04 461 }
IanBenzMaxim 0:f77ad7f72d04 462
IanBenzMaxim 0:f77ad7f72d04 463 // proceed to set the DS2480 communication speed
IanBenzMaxim 0:f77ad7f72d04 464 packet[packetLen++] = CMD_COMM | FUNCTSEL_SEARCHOFF | speed;
IanBenzMaxim 0:f77ad7f72d04 465
IanBenzMaxim 0:f77ad7f72d04 466 // send the packet
IanBenzMaxim 0:f77ad7f72d04 467 result = uart->writeBlock(packet, packetLen);
IanBenzMaxim 0:f77ad7f72d04 468 }
IanBenzMaxim 0:f77ad7f72d04 469
IanBenzMaxim 0:f77ad7f72d04 470 return result;
IanBenzMaxim 0:f77ad7f72d04 471 }
IanBenzMaxim 0:f77ad7f72d04 472
IanBenzMaxim 0:f77ad7f72d04 473 error_code DS2480B::setLevel(Level newLevel) {
IanBenzMaxim 0:f77ad7f72d04 474 error_code result;
IanBenzMaxim 0:f77ad7f72d04 475 // check if need to change level
IanBenzMaxim 0:f77ad7f72d04 476 if (newLevel != level) {
IanBenzMaxim 0:f77ad7f72d04 477 uint_least8_t packet[4];
IanBenzMaxim 0:f77ad7f72d04 478 int packetLen = 0;
IanBenzMaxim 0:f77ad7f72d04 479
IanBenzMaxim 0:f77ad7f72d04 480 // check for correct mode
IanBenzMaxim 0:f77ad7f72d04 481 if (mode != MODSEL_COMMAND) {
IanBenzMaxim 0:f77ad7f72d04 482 mode = MODSEL_COMMAND;
IanBenzMaxim 0:f77ad7f72d04 483 packet[packetLen++] = MODE_COMMAND;
IanBenzMaxim 0:f77ad7f72d04 484 }
IanBenzMaxim 0:f77ad7f72d04 485
IanBenzMaxim 0:f77ad7f72d04 486 switch (newLevel) {
IanBenzMaxim 0:f77ad7f72d04 487 case NormalLevel:
IanBenzMaxim 0:f77ad7f72d04 488 // stop pulse command
IanBenzMaxim 0:f77ad7f72d04 489 packet[packetLen++] = MODE_STOP_PULSE;
IanBenzMaxim 0:f77ad7f72d04 490
IanBenzMaxim 0:f77ad7f72d04 491 // add the command to begin the pulse WITHOUT prime
IanBenzMaxim 0:f77ad7f72d04 492 packet[packetLen++] = CMD_COMM | FUNCTSEL_CHMOD | SPEEDSEL_PULSE |
IanBenzMaxim 0:f77ad7f72d04 493 BITPOL_5V | PRIME5V_FALSE;
IanBenzMaxim 0:f77ad7f72d04 494
IanBenzMaxim 0:f77ad7f72d04 495 // stop pulse command
IanBenzMaxim 0:f77ad7f72d04 496 packet[packetLen++] = MODE_STOP_PULSE;
IanBenzMaxim 0:f77ad7f72d04 497
IanBenzMaxim 0:f77ad7f72d04 498 // flush the buffers
IanBenzMaxim 0:f77ad7f72d04 499 result = uart->clearReadBuffer();
IanBenzMaxim 0:f77ad7f72d04 500 if (result) {
IanBenzMaxim 0:f77ad7f72d04 501 return result;
IanBenzMaxim 0:f77ad7f72d04 502 }
IanBenzMaxim 0:f77ad7f72d04 503
IanBenzMaxim 0:f77ad7f72d04 504 // send the packet
IanBenzMaxim 0:f77ad7f72d04 505 result = uart->writeBlock(packet, packetLen);
IanBenzMaxim 0:f77ad7f72d04 506 if (result) {
IanBenzMaxim 0:f77ad7f72d04 507 return result;
IanBenzMaxim 0:f77ad7f72d04 508 }
IanBenzMaxim 0:f77ad7f72d04 509
IanBenzMaxim 0:f77ad7f72d04 510 // read back the 1 byte response
IanBenzMaxim 0:f77ad7f72d04 511 result = uart->readBlock(packet, 2);
IanBenzMaxim 0:f77ad7f72d04 512 if (result) {
IanBenzMaxim 0:f77ad7f72d04 513 return result;
IanBenzMaxim 0:f77ad7f72d04 514 }
IanBenzMaxim 0:f77ad7f72d04 515
IanBenzMaxim 0:f77ad7f72d04 516 // check response byte
IanBenzMaxim 0:f77ad7f72d04 517 if (((packet[0] & 0xE0) == 0xE0) && ((packet[1] & 0xE0) == 0xE0)) {
IanBenzMaxim 0:f77ad7f72d04 518 level = NormalLevel;
IanBenzMaxim 0:f77ad7f72d04 519 } else {
IanBenzMaxim 0:f77ad7f72d04 520 result = make_error_code(HardwareError);
IanBenzMaxim 0:f77ad7f72d04 521 }
IanBenzMaxim 0:f77ad7f72d04 522 break;
IanBenzMaxim 0:f77ad7f72d04 523
IanBenzMaxim 0:f77ad7f72d04 524 case StrongLevel:
IanBenzMaxim 0:f77ad7f72d04 525 // set the SPUD time value
IanBenzMaxim 0:f77ad7f72d04 526 packet[packetLen++] = CMD_CONFIG | PARMSEL_5VPULSE | PARMSET_infinite;
IanBenzMaxim 0:f77ad7f72d04 527 // add the command to begin the pulse
IanBenzMaxim 0:f77ad7f72d04 528 packet[packetLen++] =
IanBenzMaxim 0:f77ad7f72d04 529 CMD_COMM | FUNCTSEL_CHMOD | SPEEDSEL_PULSE | BITPOL_5V;
IanBenzMaxim 0:f77ad7f72d04 530
IanBenzMaxim 0:f77ad7f72d04 531 // flush the buffers
IanBenzMaxim 0:f77ad7f72d04 532 result = uart->clearReadBuffer();
IanBenzMaxim 0:f77ad7f72d04 533 if (result) {
IanBenzMaxim 0:f77ad7f72d04 534 return result;
IanBenzMaxim 0:f77ad7f72d04 535 }
IanBenzMaxim 0:f77ad7f72d04 536
IanBenzMaxim 0:f77ad7f72d04 537 // send the packet
IanBenzMaxim 0:f77ad7f72d04 538 result = uart->writeBlock(packet, packetLen);
IanBenzMaxim 0:f77ad7f72d04 539 if (result) {
IanBenzMaxim 0:f77ad7f72d04 540 return result;
IanBenzMaxim 0:f77ad7f72d04 541 }
IanBenzMaxim 0:f77ad7f72d04 542
IanBenzMaxim 0:f77ad7f72d04 543 // read back the 1 byte response from setting time limit
IanBenzMaxim 0:f77ad7f72d04 544 result = uart->readBlock(packet, 1);
IanBenzMaxim 0:f77ad7f72d04 545 if (result) {
IanBenzMaxim 0:f77ad7f72d04 546 return result;
IanBenzMaxim 0:f77ad7f72d04 547 }
IanBenzMaxim 0:f77ad7f72d04 548
IanBenzMaxim 0:f77ad7f72d04 549 // check response byte
IanBenzMaxim 0:f77ad7f72d04 550 if ((packet[0] & 0x81) == 0) {
IanBenzMaxim 0:f77ad7f72d04 551 level = newLevel;
IanBenzMaxim 0:f77ad7f72d04 552 } else {
IanBenzMaxim 0:f77ad7f72d04 553 result = make_error_code(HardwareError);
IanBenzMaxim 0:f77ad7f72d04 554 }
IanBenzMaxim 0:f77ad7f72d04 555 break;
IanBenzMaxim 0:f77ad7f72d04 556
IanBenzMaxim 0:f77ad7f72d04 557 default:
IanBenzMaxim 0:f77ad7f72d04 558 result = make_error_code(InvalidLevelError);
IanBenzMaxim 0:f77ad7f72d04 559 break;
IanBenzMaxim 0:f77ad7f72d04 560 }
IanBenzMaxim 0:f77ad7f72d04 561 }
IanBenzMaxim 0:f77ad7f72d04 562 return result;
IanBenzMaxim 0:f77ad7f72d04 563 }
IanBenzMaxim 0:f77ad7f72d04 564
IanBenzMaxim 0:f77ad7f72d04 565 error_code DS2480B::changeBaud(BaudRate newBaud) {
IanBenzMaxim 0:f77ad7f72d04 566 error_code result;
IanBenzMaxim 0:f77ad7f72d04 567
IanBenzMaxim 0:f77ad7f72d04 568 //see if different then current baud rate
IanBenzMaxim 0:f77ad7f72d04 569 if (baud != newBaud) {
IanBenzMaxim 0:f77ad7f72d04 570 uint_least8_t packet[2];
IanBenzMaxim 0:f77ad7f72d04 571 int packetLen = 0;
IanBenzMaxim 0:f77ad7f72d04 572
IanBenzMaxim 0:f77ad7f72d04 573 // build the command packet
IanBenzMaxim 0:f77ad7f72d04 574 // check for correct mode
IanBenzMaxim 0:f77ad7f72d04 575 if (mode != MODSEL_COMMAND) {
IanBenzMaxim 0:f77ad7f72d04 576 mode = MODSEL_COMMAND;
IanBenzMaxim 0:f77ad7f72d04 577 packet[packetLen++] = MODE_COMMAND;
IanBenzMaxim 0:f77ad7f72d04 578 }
IanBenzMaxim 0:f77ad7f72d04 579 // build the command
IanBenzMaxim 0:f77ad7f72d04 580 const uint_least8_t baudByte = CMD_CONFIG | PARMSEL_BAUDRATE | newBaud;
IanBenzMaxim 0:f77ad7f72d04 581 packet[packetLen++] = baudByte;
IanBenzMaxim 0:f77ad7f72d04 582
IanBenzMaxim 0:f77ad7f72d04 583 // flush the buffers
IanBenzMaxim 0:f77ad7f72d04 584 result = uart->clearReadBuffer();
IanBenzMaxim 0:f77ad7f72d04 585 if (result) {
IanBenzMaxim 0:f77ad7f72d04 586 return result;
IanBenzMaxim 0:f77ad7f72d04 587 }
IanBenzMaxim 0:f77ad7f72d04 588
IanBenzMaxim 0:f77ad7f72d04 589 // send the packet
IanBenzMaxim 0:f77ad7f72d04 590 result = uart->writeBlock(packet, packetLen);
IanBenzMaxim 0:f77ad7f72d04 591 if (result) {
IanBenzMaxim 0:f77ad7f72d04 592 return result;
IanBenzMaxim 0:f77ad7f72d04 593 }
IanBenzMaxim 0:f77ad7f72d04 594
IanBenzMaxim 0:f77ad7f72d04 595 // make sure buffer is flushed
IanBenzMaxim 0:f77ad7f72d04 596 (*sleep)(5);
IanBenzMaxim 0:f77ad7f72d04 597
IanBenzMaxim 0:f77ad7f72d04 598 // change our baud rate
IanBenzMaxim 0:f77ad7f72d04 599 result = setComBaud(newBaud);
IanBenzMaxim 0:f77ad7f72d04 600 if (result) {
IanBenzMaxim 0:f77ad7f72d04 601 return result;
IanBenzMaxim 0:f77ad7f72d04 602 }
IanBenzMaxim 0:f77ad7f72d04 603 baud = newBaud;
IanBenzMaxim 0:f77ad7f72d04 604
IanBenzMaxim 0:f77ad7f72d04 605 // wait for things to settle
IanBenzMaxim 0:f77ad7f72d04 606 (*sleep)(5);
IanBenzMaxim 0:f77ad7f72d04 607
IanBenzMaxim 0:f77ad7f72d04 608 // build a command packet to read back baud rate
IanBenzMaxim 0:f77ad7f72d04 609 packet[0] = CMD_CONFIG | PARMSEL_PARMREAD | (PARMSEL_BAUDRATE >> 3);
IanBenzMaxim 0:f77ad7f72d04 610
IanBenzMaxim 0:f77ad7f72d04 611 // flush the buffers
IanBenzMaxim 0:f77ad7f72d04 612 result = uart->clearReadBuffer();
IanBenzMaxim 0:f77ad7f72d04 613 if (result) {
IanBenzMaxim 0:f77ad7f72d04 614 return result;
IanBenzMaxim 0:f77ad7f72d04 615 }
IanBenzMaxim 0:f77ad7f72d04 616
IanBenzMaxim 0:f77ad7f72d04 617 // send the packet
IanBenzMaxim 0:f77ad7f72d04 618 result = uart->writeBlock(packet, 1);
IanBenzMaxim 0:f77ad7f72d04 619 if (result) {
IanBenzMaxim 0:f77ad7f72d04 620 return result;
IanBenzMaxim 0:f77ad7f72d04 621 }
IanBenzMaxim 0:f77ad7f72d04 622
IanBenzMaxim 0:f77ad7f72d04 623 // read back the 1 byte response
IanBenzMaxim 0:f77ad7f72d04 624 result = uart->readBlock(packet, 1);
IanBenzMaxim 0:f77ad7f72d04 625 if (result) {
IanBenzMaxim 0:f77ad7f72d04 626 return result;
IanBenzMaxim 0:f77ad7f72d04 627 }
IanBenzMaxim 0:f77ad7f72d04 628
IanBenzMaxim 0:f77ad7f72d04 629 // verify correct baud
IanBenzMaxim 0:f77ad7f72d04 630 if (!((packet[0] & 0x0E) == (baudByte & 0x0E))) {
IanBenzMaxim 0:f77ad7f72d04 631 result = make_error_code(HardwareError);
IanBenzMaxim 0:f77ad7f72d04 632 }
IanBenzMaxim 0:f77ad7f72d04 633 }
IanBenzMaxim 0:f77ad7f72d04 634
IanBenzMaxim 0:f77ad7f72d04 635 return result;
IanBenzMaxim 0:f77ad7f72d04 636 }
IanBenzMaxim 0:f77ad7f72d04 637
IanBenzMaxim 0:f77ad7f72d04 638 error_code DS2480B::setComBaud(BaudRate newBaud) {
IanBenzMaxim 0:f77ad7f72d04 639 switch (newBaud) {
IanBenzMaxim 0:f77ad7f72d04 640 case Baud115200bps:
IanBenzMaxim 0:f77ad7f72d04 641 return uart->setBaud(115200);
IanBenzMaxim 0:f77ad7f72d04 642
IanBenzMaxim 0:f77ad7f72d04 643 case Baud57600bps:
IanBenzMaxim 0:f77ad7f72d04 644 return uart->setBaud(57600);
IanBenzMaxim 0:f77ad7f72d04 645
IanBenzMaxim 0:f77ad7f72d04 646 case Baud19200bps:
IanBenzMaxim 0:f77ad7f72d04 647 return uart->setBaud(19200);
IanBenzMaxim 0:f77ad7f72d04 648
IanBenzMaxim 0:f77ad7f72d04 649 case Baud9600bps:
IanBenzMaxim 0:f77ad7f72d04 650 default:
IanBenzMaxim 0:f77ad7f72d04 651 return uart->setBaud(9600);
IanBenzMaxim 0:f77ad7f72d04 652 }
IanBenzMaxim 0:f77ad7f72d04 653 }
IanBenzMaxim 0:f77ad7f72d04 654
IanBenzMaxim 0:f77ad7f72d04 655 error_code DS2480B::breakCom() {
IanBenzMaxim 0:f77ad7f72d04 656 // Switch to lower baud rate to ensure break is longer than 2 ms.
IanBenzMaxim 0:f77ad7f72d04 657 error_code result = uart->setBaud(4800);
IanBenzMaxim 0:f77ad7f72d04 658 if (result) {
IanBenzMaxim 0:f77ad7f72d04 659 return result;
IanBenzMaxim 0:f77ad7f72d04 660 }
IanBenzMaxim 0:f77ad7f72d04 661 result = uart->sendBreak();
IanBenzMaxim 0:f77ad7f72d04 662 if (result) {
IanBenzMaxim 0:f77ad7f72d04 663 return result;
IanBenzMaxim 0:f77ad7f72d04 664 }
IanBenzMaxim 0:f77ad7f72d04 665 result = setComBaud(baud);
IanBenzMaxim 0:f77ad7f72d04 666 return result;
IanBenzMaxim 0:f77ad7f72d04 667 }
IanBenzMaxim 0:f77ad7f72d04 668
IanBenzMaxim 0:f77ad7f72d04 669 const error_category & DS2480B::errorCategory() {
IanBenzMaxim 0:f77ad7f72d04 670 static class : public error_category {
IanBenzMaxim 0:f77ad7f72d04 671 public:
IanBenzMaxim 0:f77ad7f72d04 672 virtual const char * name() const { return "DS2480B"; }
IanBenzMaxim 0:f77ad7f72d04 673
IanBenzMaxim 0:f77ad7f72d04 674 virtual std::string message(int condition) const {
IanBenzMaxim 0:f77ad7f72d04 675 switch (condition) {
IanBenzMaxim 0:f77ad7f72d04 676 case HardwareError:
IanBenzMaxim 0:f77ad7f72d04 677 return "Hardware Error";
IanBenzMaxim 0:f77ad7f72d04 678
IanBenzMaxim 0:f77ad7f72d04 679 default:
IanBenzMaxim 0:f77ad7f72d04 680 return defaultErrorMessage(condition);
IanBenzMaxim 0:f77ad7f72d04 681 }
IanBenzMaxim 0:f77ad7f72d04 682 }
IanBenzMaxim 0:f77ad7f72d04 683 } instance;
IanBenzMaxim 0:f77ad7f72d04 684 return instance;
IanBenzMaxim 0:f77ad7f72d04 685 }
IanBenzMaxim 0:f77ad7f72d04 686
IanBenzMaxim 0:f77ad7f72d04 687 } // namespace MaximInterface