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Fork of mbed-dev by Umar Naeem

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_dma.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_hal_dma.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.5.1
<> 144:ef7eb2e8f9f7 6 * @date 31-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief DMA HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Direct Memory Access (DMA) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + IO operation functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral State and errors functions
<> 144:ef7eb2e8f9f7 13 @verbatim
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 [..]
<> 144:ef7eb2e8f9f7 18 (#) Enable and configure the peripheral to be connected to the DMA Channel
<> 144:ef7eb2e8f9f7 19 (except for internal SRAM / FLASH memories: no initialization is
<> 144:ef7eb2e8f9f7 20 necessary). Please refer to the Reference manual for connection between peripherals
<> 144:ef7eb2e8f9f7 21 and DMA requests.
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 (#) For a given Channel, program the required configuration through the following parameters:
<> 144:ef7eb2e8f9f7 24 Channel request, Transfer Direction, Source and Destination data formats,
<> 144:ef7eb2e8f9f7 25 Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
<> 144:ef7eb2e8f9f7 26 using HAL_DMA_Init() function.
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
<> 144:ef7eb2e8f9f7 29 detection.
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 (#) Use HAL_DMA_Abort() function to abort the current transfer
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
<> 144:ef7eb2e8f9f7 34 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 35 =================================
<> 144:ef7eb2e8f9f7 36 [..]
<> 144:ef7eb2e8f9f7 37 (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
<> 144:ef7eb2e8f9f7 38 address and destination address and the Length of data to be transferred
<> 144:ef7eb2e8f9f7 39 (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
<> 144:ef7eb2e8f9f7 40 case a fixed Timeout can be configured by User depending from his application.
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 43 ===================================
<> 144:ef7eb2e8f9f7 44 [..]
<> 144:ef7eb2e8f9f7 45 (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
<> 144:ef7eb2e8f9f7 46 (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
<> 144:ef7eb2e8f9f7 47 (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
<> 144:ef7eb2e8f9f7 48 Source address and destination address and the Length of data to be transferred.
<> 144:ef7eb2e8f9f7 49 In this case the DMA interrupt is configured
<> 144:ef7eb2e8f9f7 50 (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
<> 144:ef7eb2e8f9f7 51 (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
<> 144:ef7eb2e8f9f7 52 add his own function by customization of function pointer XferCpltCallback and
<> 144:ef7eb2e8f9f7 53 XferErrorCallback (i.e. a member of DMA handle structure).
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 *** DMA HAL driver macros list ***
<> 144:ef7eb2e8f9f7 56 =============================================
<> 144:ef7eb2e8f9f7 57 [..]
<> 144:ef7eb2e8f9f7 58 Below the list of most used macros in DMA HAL driver.
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
<> 144:ef7eb2e8f9f7 61 (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
<> 144:ef7eb2e8f9f7 62 (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
<> 144:ef7eb2e8f9f7 63 (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
<> 144:ef7eb2e8f9f7 64 (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
<> 144:ef7eb2e8f9f7 65 (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
<> 144:ef7eb2e8f9f7 66 (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 [..]
<> 144:ef7eb2e8f9f7 69 (@) You can refer to the DMA HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 @endverbatim
<> 144:ef7eb2e8f9f7 72 ******************************************************************************
<> 144:ef7eb2e8f9f7 73 * @attention
<> 144:ef7eb2e8f9f7 74 *
<> 144:ef7eb2e8f9f7 75 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 76 *
<> 144:ef7eb2e8f9f7 77 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 78 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 79 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 80 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 81 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 82 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 83 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 84 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 85 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 86 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 87 *
<> 144:ef7eb2e8f9f7 88 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 89 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 90 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 91 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 92 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 93 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 94 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 95 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 96 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 97 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 98 *
<> 144:ef7eb2e8f9f7 99 ******************************************************************************
<> 144:ef7eb2e8f9f7 100 */
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 103 #include "stm32l4xx_hal.h"
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /** @addtogroup STM32L4xx_HAL_Driver
<> 144:ef7eb2e8f9f7 106 * @{
<> 144:ef7eb2e8f9f7 107 */
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 /** @defgroup DMA DMA
<> 144:ef7eb2e8f9f7 110 * @brief DMA HAL module driver
<> 144:ef7eb2e8f9f7 111 * @{
<> 144:ef7eb2e8f9f7 112 */
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 #ifdef HAL_DMA_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 117 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 118 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 119 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 120 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 121 /** @defgroup DMA_Private_Functions DMA Private Functions
<> 144:ef7eb2e8f9f7 122 * @{
<> 144:ef7eb2e8f9f7 123 */
<> 144:ef7eb2e8f9f7 124 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
<> 144:ef7eb2e8f9f7 125 /**
<> 144:ef7eb2e8f9f7 126 * @}
<> 144:ef7eb2e8f9f7 127 */
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /** @defgroup DMA_Exported_Functions DMA Exported Functions
<> 144:ef7eb2e8f9f7 132 * @{
<> 144:ef7eb2e8f9f7 133 */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 136 * @brief Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 137 *
<> 144:ef7eb2e8f9f7 138 @verbatim
<> 144:ef7eb2e8f9f7 139 ===============================================================================
<> 144:ef7eb2e8f9f7 140 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 141 ===============================================================================
<> 144:ef7eb2e8f9f7 142 [..]
<> 144:ef7eb2e8f9f7 143 This section provides functions allowing to initialize the DMA Channel source
<> 144:ef7eb2e8f9f7 144 and destination addresses, incrementation and data sizes, transfer direction,
<> 144:ef7eb2e8f9f7 145 circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
<> 144:ef7eb2e8f9f7 146 [..]
<> 144:ef7eb2e8f9f7 147 The HAL_DMA_Init() function follows the DMA configuration procedures as described in
<> 144:ef7eb2e8f9f7 148 reference manual.
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 @endverbatim
<> 144:ef7eb2e8f9f7 151 * @{
<> 144:ef7eb2e8f9f7 152 */
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 /**
<> 144:ef7eb2e8f9f7 155 * @brief Initialize the DMA according to the specified
<> 144:ef7eb2e8f9f7 156 * parameters in the DMA_InitTypeDef and initialize the associated handle.
<> 144:ef7eb2e8f9f7 157 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 158 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 159 * @retval HAL status
<> 144:ef7eb2e8f9f7 160 */
<> 144:ef7eb2e8f9f7 161 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 162 {
<> 144:ef7eb2e8f9f7 163 uint32_t tmp = 0;
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 /* Check the DMA handle allocation */
<> 144:ef7eb2e8f9f7 166 if(hdma == NULL)
<> 144:ef7eb2e8f9f7 167 {
<> 144:ef7eb2e8f9f7 168 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 169 }
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /* Check the parameters */
<> 144:ef7eb2e8f9f7 172 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
<> 144:ef7eb2e8f9f7 173 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
<> 144:ef7eb2e8f9f7 174 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
<> 144:ef7eb2e8f9f7 175 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
<> 144:ef7eb2e8f9f7 176 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
<> 144:ef7eb2e8f9f7 177 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
<> 144:ef7eb2e8f9f7 178 assert_param(IS_DMA_MODE(hdma->Init.Mode));
<> 144:ef7eb2e8f9f7 179 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
<> 144:ef7eb2e8f9f7 180 if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
<> 144:ef7eb2e8f9f7 181 {
<> 144:ef7eb2e8f9f7 182 assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
<> 144:ef7eb2e8f9f7 183 }
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /* calculation of the channel index */
<> 144:ef7eb2e8f9f7 186 if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
<> 144:ef7eb2e8f9f7 187 {
<> 144:ef7eb2e8f9f7 188 /* DMA1 */
<> 144:ef7eb2e8f9f7 189 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
<> 144:ef7eb2e8f9f7 190 hdma->DmaBaseAddress = DMA1;
<> 144:ef7eb2e8f9f7 191 }
<> 144:ef7eb2e8f9f7 192 else
<> 144:ef7eb2e8f9f7 193 {
<> 144:ef7eb2e8f9f7 194 /* DMA2 */
<> 144:ef7eb2e8f9f7 195 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
<> 144:ef7eb2e8f9f7 196 hdma->DmaBaseAddress = DMA2;
<> 144:ef7eb2e8f9f7 197 }
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /* Change DMA peripheral state */
<> 144:ef7eb2e8f9f7 200 hdma->State = HAL_DMA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 /* Get the CR register value */
<> 144:ef7eb2e8f9f7 203 tmp = hdma->Instance->CCR;
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
<> 144:ef7eb2e8f9f7 206 tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
<> 144:ef7eb2e8f9f7 207 DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
<> 144:ef7eb2e8f9f7 208 DMA_CCR_DIR));
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 /* Prepare the DMA Channel configuration */
<> 144:ef7eb2e8f9f7 211 tmp |= hdma->Init.Direction |
<> 144:ef7eb2e8f9f7 212 hdma->Init.PeriphInc | hdma->Init.MemInc |
<> 144:ef7eb2e8f9f7 213 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
<> 144:ef7eb2e8f9f7 214 hdma->Init.Mode | hdma->Init.Priority;
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /* Write to DMA Channel CR register */
<> 144:ef7eb2e8f9f7 217 hdma->Instance->CCR = tmp;
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 /* Set request selection */
<> 144:ef7eb2e8f9f7 220 if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
<> 144:ef7eb2e8f9f7 221 {
<> 144:ef7eb2e8f9f7 222 /* Write to DMA channel selection register */
<> 144:ef7eb2e8f9f7 223 if (DMA1 == hdma->DmaBaseAddress)
<> 144:ef7eb2e8f9f7 224 {
<> 144:ef7eb2e8f9f7 225 /* Reset request selection for DMA1 Channelx */
<> 144:ef7eb2e8f9f7 226 DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << hdma->ChannelIndex);
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /* Configure request selection for DMA1 Channelx */
<> 144:ef7eb2e8f9f7 229 DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex));
<> 144:ef7eb2e8f9f7 230 }
<> 144:ef7eb2e8f9f7 231 else /* DMA2 */
<> 144:ef7eb2e8f9f7 232 {
<> 144:ef7eb2e8f9f7 233 /* Reset request selection for DMA2 Channelx */
<> 144:ef7eb2e8f9f7 234 DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << hdma->ChannelIndex);
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 /* Configure request selection for DMA2 Channelx */
<> 144:ef7eb2e8f9f7 237 DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex));
<> 144:ef7eb2e8f9f7 238 }
<> 144:ef7eb2e8f9f7 239 }
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 /* Clean callbacks */
<> 144:ef7eb2e8f9f7 242 hdma->XferCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 243 hdma->XferHalfCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 244 hdma->XferErrorCallback = NULL;
<> 144:ef7eb2e8f9f7 245 hdma->XferAbortCallback = NULL;
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 /* Initialise the error code */
<> 144:ef7eb2e8f9f7 248 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 /* Initialize the DMA state*/
<> 144:ef7eb2e8f9f7 251 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 254 hdma->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 return HAL_OK;
<> 144:ef7eb2e8f9f7 257 }
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /**
<> 144:ef7eb2e8f9f7 260 * @brief DeInitialize the DMA peripheral.
<> 144:ef7eb2e8f9f7 261 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 262 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 263 * @retval HAL status
<> 144:ef7eb2e8f9f7 264 */
<> 144:ef7eb2e8f9f7 265 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 266 {
<> 144:ef7eb2e8f9f7 267 /* Check the DMA handle allocation */
<> 144:ef7eb2e8f9f7 268 if(hdma == NULL)
<> 144:ef7eb2e8f9f7 269 {
<> 144:ef7eb2e8f9f7 270 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 271 }
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /* Check the parameters */
<> 144:ef7eb2e8f9f7 274 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /* Disable the selected DMA Channelx */
<> 144:ef7eb2e8f9f7 277 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 /* Reset DMA Channel control register */
<> 144:ef7eb2e8f9f7 280 hdma->Instance->CCR = 0;
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /* Calculation of the channel index */
<> 144:ef7eb2e8f9f7 283 if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
<> 144:ef7eb2e8f9f7 284 {
<> 144:ef7eb2e8f9f7 285 /* DMA1 */
<> 144:ef7eb2e8f9f7 286 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
<> 144:ef7eb2e8f9f7 287 hdma->DmaBaseAddress = DMA1;
<> 144:ef7eb2e8f9f7 288 }
<> 144:ef7eb2e8f9f7 289 else
<> 144:ef7eb2e8f9f7 290 {
<> 144:ef7eb2e8f9f7 291 /* DMA2 */
<> 144:ef7eb2e8f9f7 292 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
<> 144:ef7eb2e8f9f7 293 hdma->DmaBaseAddress = DMA2;
<> 144:ef7eb2e8f9f7 294 }
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /* Clear all flags */
<> 144:ef7eb2e8f9f7 298 hdma->DmaBaseAddress->IFCR |= ((DMA_ISR_GIF1) << (hdma->ChannelIndex));
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /* Reset DMA channel selection register */
<> 144:ef7eb2e8f9f7 301 if (DMA1 == hdma->DmaBaseAddress)
<> 144:ef7eb2e8f9f7 302 {
<> 144:ef7eb2e8f9f7 303 /* DMA1 */
<> 144:ef7eb2e8f9f7 304 DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex));
<> 144:ef7eb2e8f9f7 305 }
<> 144:ef7eb2e8f9f7 306 else
<> 144:ef7eb2e8f9f7 307 {
<> 144:ef7eb2e8f9f7 308 /* DMA2 */
<> 144:ef7eb2e8f9f7 309 DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex));
<> 144:ef7eb2e8f9f7 310 }
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 /* Initialize the error code */
<> 144:ef7eb2e8f9f7 313 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 /* Initialize the DMA state */
<> 144:ef7eb2e8f9f7 316 hdma->State = HAL_DMA_STATE_RESET;
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 /* Release Lock */
<> 144:ef7eb2e8f9f7 319 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 return HAL_OK;
<> 144:ef7eb2e8f9f7 322 }
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 /**
<> 144:ef7eb2e8f9f7 325 * @}
<> 144:ef7eb2e8f9f7 326 */
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
<> 144:ef7eb2e8f9f7 329 * @brief Input and Output operation functions
<> 144:ef7eb2e8f9f7 330 *
<> 144:ef7eb2e8f9f7 331 @verbatim
<> 144:ef7eb2e8f9f7 332 ===============================================================================
<> 144:ef7eb2e8f9f7 333 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 334 ===============================================================================
<> 144:ef7eb2e8f9f7 335 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 336 (+) Configure the source, destination address and data length and Start DMA transfer
<> 144:ef7eb2e8f9f7 337 (+) Configure the source, destination address and data length and
<> 144:ef7eb2e8f9f7 338 Start DMA transfer with interrupt
<> 144:ef7eb2e8f9f7 339 (+) Abort DMA transfer
<> 144:ef7eb2e8f9f7 340 (+) Poll for transfer complete
<> 144:ef7eb2e8f9f7 341 (+) Handle DMA interrupt request
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 @endverbatim
<> 144:ef7eb2e8f9f7 344 * @{
<> 144:ef7eb2e8f9f7 345 */
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 /**
<> 144:ef7eb2e8f9f7 348 * @brief Start the DMA Transfer.
<> 144:ef7eb2e8f9f7 349 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 350 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 351 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 352 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 353 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 354 * @retval HAL status
<> 144:ef7eb2e8f9f7 355 */
<> 144:ef7eb2e8f9f7 356 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 357 {
<> 144:ef7eb2e8f9f7 358 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 /* Check the parameters */
<> 144:ef7eb2e8f9f7 361 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /* Process locked */
<> 144:ef7eb2e8f9f7 364 __HAL_LOCK(hdma);
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 if(HAL_DMA_STATE_READY == hdma->State)
<> 144:ef7eb2e8f9f7 367 {
<> 144:ef7eb2e8f9f7 368 /* Change DMA peripheral state */
<> 144:ef7eb2e8f9f7 369 hdma->State = HAL_DMA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 370 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 /* Disable the peripheral */
<> 144:ef7eb2e8f9f7 373 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /* Configure the source, destination address and the data length & clear flags*/
<> 144:ef7eb2e8f9f7 376 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 379 __HAL_DMA_ENABLE(hdma);
<> 144:ef7eb2e8f9f7 380 }
<> 144:ef7eb2e8f9f7 381 else
<> 144:ef7eb2e8f9f7 382 {
<> 144:ef7eb2e8f9f7 383 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 384 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 385 status = HAL_BUSY;
<> 144:ef7eb2e8f9f7 386 }
<> 144:ef7eb2e8f9f7 387 return status;
<> 144:ef7eb2e8f9f7 388 }
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 /**
<> 144:ef7eb2e8f9f7 391 * @brief Start the DMA Transfer with interrupt enabled.
<> 144:ef7eb2e8f9f7 392 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 393 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 394 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 395 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 396 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 397 * @retval HAL status
<> 144:ef7eb2e8f9f7 398 */
<> 144:ef7eb2e8f9f7 399 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 400 {
<> 144:ef7eb2e8f9f7 401 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 /* Check the parameters */
<> 144:ef7eb2e8f9f7 404 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 /* Process locked */
<> 144:ef7eb2e8f9f7 407 __HAL_LOCK(hdma);
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 if(HAL_DMA_STATE_READY == hdma->State)
<> 144:ef7eb2e8f9f7 410 {
<> 144:ef7eb2e8f9f7 411 /* Change DMA peripheral state */
<> 144:ef7eb2e8f9f7 412 hdma->State = HAL_DMA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 413 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 /* Disable the peripheral */
<> 144:ef7eb2e8f9f7 416 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 /* Configure the source, destination address and the data length & clear flags*/
<> 144:ef7eb2e8f9f7 419 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 /* Enable the transfer complete interrupt */
<> 144:ef7eb2e8f9f7 422 /* Enable the transfer Error interrupt */
<> 144:ef7eb2e8f9f7 423 if(NULL != hdma->XferHalfCpltCallback )
<> 144:ef7eb2e8f9f7 424 {
<> 144:ef7eb2e8f9f7 425 /* Enable the Half transfer complete interrupt as well */
<> 144:ef7eb2e8f9f7 426 __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
<> 144:ef7eb2e8f9f7 427 }
<> 144:ef7eb2e8f9f7 428 else
<> 144:ef7eb2e8f9f7 429 {
<> 144:ef7eb2e8f9f7 430 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
<> 144:ef7eb2e8f9f7 431 __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
<> 144:ef7eb2e8f9f7 432 }
<> 144:ef7eb2e8f9f7 433 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 434 __HAL_DMA_ENABLE(hdma);
<> 144:ef7eb2e8f9f7 435 }
<> 144:ef7eb2e8f9f7 436 else
<> 144:ef7eb2e8f9f7 437 {
<> 144:ef7eb2e8f9f7 438 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 439 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 /* Remain BUSY */
<> 144:ef7eb2e8f9f7 442 status = HAL_BUSY;
<> 144:ef7eb2e8f9f7 443 }
<> 144:ef7eb2e8f9f7 444 return status;
<> 144:ef7eb2e8f9f7 445 }
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 /**
<> 144:ef7eb2e8f9f7 448 * @brief Abort the DMA Transfer.
<> 144:ef7eb2e8f9f7 449 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 450 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 451 * @retval HAL status
<> 144:ef7eb2e8f9f7 452 */
<> 144:ef7eb2e8f9f7 453 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 454 {
<> 144:ef7eb2e8f9f7 455 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 if(HAL_DMA_STATE_BUSY != hdma->State)
<> 144:ef7eb2e8f9f7 458 {
<> 144:ef7eb2e8f9f7 459 /* no transfer ongoing */
<> 144:ef7eb2e8f9f7 460 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 463 }
<> 144:ef7eb2e8f9f7 464 else
<> 144:ef7eb2e8f9f7 465 {
<> 144:ef7eb2e8f9f7 466 /* Disable DMA IT */
<> 144:ef7eb2e8f9f7 467 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /* Disable the channel */
<> 144:ef7eb2e8f9f7 470 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 /* Clear all flags */
<> 144:ef7eb2e8f9f7 473 hdma->DmaBaseAddress->IFCR = ((DMA_ISR_GIF1) << (hdma->ChannelIndex));
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 476 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 479 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 480 }
<> 144:ef7eb2e8f9f7 481 return status;
<> 144:ef7eb2e8f9f7 482 }
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 /**
<> 144:ef7eb2e8f9f7 485 * @brief Aborts the DMA Transfer in Interrupt mode.
<> 144:ef7eb2e8f9f7 486 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 487 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 488 * @retval HAL status
<> 144:ef7eb2e8f9f7 489 */
<> 144:ef7eb2e8f9f7 490 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 491 {
<> 144:ef7eb2e8f9f7 492 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 if(HAL_DMA_STATE_BUSY != hdma->State)
<> 144:ef7eb2e8f9f7 495 {
<> 144:ef7eb2e8f9f7 496 /* no transfer ongoing */
<> 144:ef7eb2e8f9f7 497 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 500 }
<> 144:ef7eb2e8f9f7 501 else
<> 144:ef7eb2e8f9f7 502 {
<> 144:ef7eb2e8f9f7 503 /* Disable DMA IT */
<> 144:ef7eb2e8f9f7 504 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 /* Disable the channel */
<> 144:ef7eb2e8f9f7 507 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 /* Clear all flags */
<> 144:ef7eb2e8f9f7 510 hdma->DmaBaseAddress->IFCR |= ((DMA_ISR_GIF1) << (hdma->ChannelIndex));
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 513 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 516 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 /* Call User Abort callback */
<> 144:ef7eb2e8f9f7 519 if(hdma->XferAbortCallback != NULL)
<> 144:ef7eb2e8f9f7 520 {
<> 144:ef7eb2e8f9f7 521 hdma->XferAbortCallback(hdma);
<> 144:ef7eb2e8f9f7 522 }
<> 144:ef7eb2e8f9f7 523 }
<> 144:ef7eb2e8f9f7 524 return status;
<> 144:ef7eb2e8f9f7 525 }
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 /**
<> 144:ef7eb2e8f9f7 528 * @brief Polling for transfer complete.
<> 144:ef7eb2e8f9f7 529 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 530 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 531 * @param CompleteLevel: Specifies the DMA level complete.
<> 144:ef7eb2e8f9f7 532 * @param Timeout: Timeout duration.
<> 144:ef7eb2e8f9f7 533 * @retval HAL status
<> 144:ef7eb2e8f9f7 534 */
<> 144:ef7eb2e8f9f7 535 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 536 {
<> 144:ef7eb2e8f9f7 537 uint32_t temp;
<> 144:ef7eb2e8f9f7 538 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 if(HAL_DMA_STATE_BUSY != hdma->State)
<> 144:ef7eb2e8f9f7 541 {
<> 144:ef7eb2e8f9f7 542 /* no transfer ongoing */
<> 144:ef7eb2e8f9f7 543 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 546 }
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548 /* Polling mode not supported in circular mode */
<> 144:ef7eb2e8f9f7 549 if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC))
<> 144:ef7eb2e8f9f7 550 {
<> 144:ef7eb2e8f9f7 551 hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
<> 144:ef7eb2e8f9f7 552 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 553 }
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 /* Get the level transfer complete flag */
<> 144:ef7eb2e8f9f7 556 if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
<> 144:ef7eb2e8f9f7 557 {
<> 144:ef7eb2e8f9f7 558 /* Transfer Complete flag */
<> 144:ef7eb2e8f9f7 559 temp = DMA_FLAG_TC1 << hdma->ChannelIndex;
<> 144:ef7eb2e8f9f7 560 }
<> 144:ef7eb2e8f9f7 561 else
<> 144:ef7eb2e8f9f7 562 {
<> 144:ef7eb2e8f9f7 563 /* Half Transfer Complete flag */
<> 144:ef7eb2e8f9f7 564 temp = DMA_FLAG_HT1 << hdma->ChannelIndex;
<> 144:ef7eb2e8f9f7 565 }
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 /* Get tick */
<> 144:ef7eb2e8f9f7 568 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 while(RESET == (hdma->DmaBaseAddress->ISR & temp))
<> 144:ef7eb2e8f9f7 571 {
<> 144:ef7eb2e8f9f7 572 if((RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex))))
<> 144:ef7eb2e8f9f7 573 {
<> 144:ef7eb2e8f9f7 574 /* When a DMA transfer error occurs */
<> 144:ef7eb2e8f9f7 575 /* A hardware clear of its EN bits is performed */
<> 144:ef7eb2e8f9f7 576 /* Clear all flags */
<> 144:ef7eb2e8f9f7 577 hdma->DmaBaseAddress->IFCR |= ((DMA_ISR_GIF1) << (hdma->ChannelIndex));
<> 144:ef7eb2e8f9f7 578
<> 144:ef7eb2e8f9f7 579 /* Update error code */
<> 144:ef7eb2e8f9f7 580 hdma->ErrorCode = HAL_DMA_ERROR_TE;
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 583 hdma->State= HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 586 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 589 }
<> 144:ef7eb2e8f9f7 590 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 591 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 592 {
<> 144:ef7eb2e8f9f7 593 if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 594 {
<> 144:ef7eb2e8f9f7 595 /* Update error code */
<> 144:ef7eb2e8f9f7 596 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 599 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 602 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 605 }
<> 144:ef7eb2e8f9f7 606 }
<> 144:ef7eb2e8f9f7 607 }
<> 144:ef7eb2e8f9f7 608
<> 144:ef7eb2e8f9f7 609 if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
<> 144:ef7eb2e8f9f7 610 {
<> 144:ef7eb2e8f9f7 611 /* Clear the transfer complete flag */
<> 144:ef7eb2e8f9f7 612 hdma->DmaBaseAddress->IFCR |= (DMA_FLAG_TC1 << hdma->ChannelIndex);
<> 144:ef7eb2e8f9f7 613
<> 144:ef7eb2e8f9f7 614 /* The selected Channelx EN bit is cleared (DMA is disabled and
<> 144:ef7eb2e8f9f7 615 all transfers are complete) */
<> 144:ef7eb2e8f9f7 616 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 617 }
<> 144:ef7eb2e8f9f7 618 else
<> 144:ef7eb2e8f9f7 619 {
<> 144:ef7eb2e8f9f7 620 /* Clear the half transfer complete flag */
<> 144:ef7eb2e8f9f7 621 hdma->DmaBaseAddress->IFCR |= (DMA_FLAG_HT1 << hdma->ChannelIndex);
<> 144:ef7eb2e8f9f7 622 }
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 /* Process unlocked */
<> 144:ef7eb2e8f9f7 625 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 626
<> 144:ef7eb2e8f9f7 627 return HAL_OK;
<> 144:ef7eb2e8f9f7 628 }
<> 144:ef7eb2e8f9f7 629
<> 144:ef7eb2e8f9f7 630 /**
<> 144:ef7eb2e8f9f7 631 * @brief Handle DMA interrupt request.
<> 144:ef7eb2e8f9f7 632 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 633 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 634 * @retval None
<> 144:ef7eb2e8f9f7 635 */
<> 144:ef7eb2e8f9f7 636 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 637 {
<> 144:ef7eb2e8f9f7 638 uint32_t flag_it = hdma->DmaBaseAddress->ISR;
<> 144:ef7eb2e8f9f7 639 uint32_t source_it = hdma->Instance->CCR;
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 /* Half Transfer Complete Interrupt management ******************************/
<> 144:ef7eb2e8f9f7 642 if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT)))
<> 144:ef7eb2e8f9f7 643 {
<> 144:ef7eb2e8f9f7 644 /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
<> 144:ef7eb2e8f9f7 645 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
<> 144:ef7eb2e8f9f7 646 {
<> 144:ef7eb2e8f9f7 647 /* Disable the half transfer interrupt */
<> 144:ef7eb2e8f9f7 648 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
<> 144:ef7eb2e8f9f7 649 }
<> 144:ef7eb2e8f9f7 650 /* Clear the half transfer complete flag */
<> 144:ef7eb2e8f9f7 651 hdma->DmaBaseAddress->IFCR |= (DMA_ISR_HTIF1 << hdma->ChannelIndex);
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 /* DMA peripheral state is not updated in Half Transfer */
<> 144:ef7eb2e8f9f7 654 /* but in Transfer Complete case */
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 if(hdma->XferHalfCpltCallback != NULL)
<> 144:ef7eb2e8f9f7 657 {
<> 144:ef7eb2e8f9f7 658 /* Half transfer callback */
<> 144:ef7eb2e8f9f7 659 hdma->XferHalfCpltCallback(hdma);
<> 144:ef7eb2e8f9f7 660 }
<> 144:ef7eb2e8f9f7 661 }
<> 144:ef7eb2e8f9f7 662
<> 144:ef7eb2e8f9f7 663 /* Transfer Complete Interrupt management ***********************************/
<> 144:ef7eb2e8f9f7 664 else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC)))
<> 144:ef7eb2e8f9f7 665 {
<> 144:ef7eb2e8f9f7 666 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
<> 144:ef7eb2e8f9f7 667 {
<> 144:ef7eb2e8f9f7 668 /* Disable the transfer complete and error interrupt */
<> 144:ef7eb2e8f9f7 669 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
<> 144:ef7eb2e8f9f7 670
<> 144:ef7eb2e8f9f7 671 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 672 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 673 }
<> 144:ef7eb2e8f9f7 674 /* Clear the transfer complete flag */
<> 144:ef7eb2e8f9f7 675 hdma->DmaBaseAddress->IFCR |= (DMA_ISR_TCIF1 << hdma->ChannelIndex);
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 678 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680 if(hdma->XferCpltCallback != NULL)
<> 144:ef7eb2e8f9f7 681 {
<> 144:ef7eb2e8f9f7 682 /* Transfer complete callback */
<> 144:ef7eb2e8f9f7 683 hdma->XferCpltCallback(hdma);
<> 144:ef7eb2e8f9f7 684 }
<> 144:ef7eb2e8f9f7 685 }
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 /* Transfer Error Interrupt management **************************************/
<> 144:ef7eb2e8f9f7 688 else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
<> 144:ef7eb2e8f9f7 689 {
<> 144:ef7eb2e8f9f7 690 /* When a DMA transfer error occurs */
<> 144:ef7eb2e8f9f7 691 /* A hardware clear of its EN bits is performed */
<> 144:ef7eb2e8f9f7 692 /* Disable ALL DMA IT */
<> 144:ef7eb2e8f9f7 693 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
<> 144:ef7eb2e8f9f7 694
<> 144:ef7eb2e8f9f7 695 /* Clear all flags */
<> 144:ef7eb2e8f9f7 696 hdma->DmaBaseAddress->IFCR |= (DMA_ISR_GIF1 << hdma->ChannelIndex);
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 /* Update error code */
<> 144:ef7eb2e8f9f7 699 hdma->ErrorCode = HAL_DMA_ERROR_TE;
<> 144:ef7eb2e8f9f7 700
<> 144:ef7eb2e8f9f7 701 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 702 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 703
<> 144:ef7eb2e8f9f7 704 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 705 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 706
<> 144:ef7eb2e8f9f7 707 if (hdma->XferErrorCallback != NULL)
<> 144:ef7eb2e8f9f7 708 {
<> 144:ef7eb2e8f9f7 709 /* Transfer error callback */
<> 144:ef7eb2e8f9f7 710 hdma->XferErrorCallback(hdma);
<> 144:ef7eb2e8f9f7 711 }
<> 144:ef7eb2e8f9f7 712 }
<> 144:ef7eb2e8f9f7 713 return;
<> 144:ef7eb2e8f9f7 714 }
<> 144:ef7eb2e8f9f7 715
<> 144:ef7eb2e8f9f7 716 /**
<> 144:ef7eb2e8f9f7 717 * @brief Register callbacks
<> 144:ef7eb2e8f9f7 718 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 719 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 720 * @param CallbackID: User Callback identifer
<> 144:ef7eb2e8f9f7 721 * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
<> 144:ef7eb2e8f9f7 722 * @param pCallback: pointer to private callbacsk function which has pointer to
<> 144:ef7eb2e8f9f7 723 * a DMA_HandleTypeDef structure as parameter.
<> 144:ef7eb2e8f9f7 724 * @retval HAL status
<> 144:ef7eb2e8f9f7 725 */
<> 144:ef7eb2e8f9f7 726 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
<> 144:ef7eb2e8f9f7 727 {
<> 144:ef7eb2e8f9f7 728 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 729
<> 144:ef7eb2e8f9f7 730 /* Process locked */
<> 144:ef7eb2e8f9f7 731 __HAL_LOCK(hdma);
<> 144:ef7eb2e8f9f7 732
<> 144:ef7eb2e8f9f7 733 if(HAL_DMA_STATE_READY == hdma->State)
<> 144:ef7eb2e8f9f7 734 {
<> 144:ef7eb2e8f9f7 735 switch (CallbackID)
<> 144:ef7eb2e8f9f7 736 {
<> 144:ef7eb2e8f9f7 737 case HAL_DMA_XFER_CPLT_CB_ID:
<> 144:ef7eb2e8f9f7 738 hdma->XferCpltCallback = pCallback;
<> 144:ef7eb2e8f9f7 739 break;
<> 144:ef7eb2e8f9f7 740
<> 144:ef7eb2e8f9f7 741 case HAL_DMA_XFER_HALFCPLT_CB_ID:
<> 144:ef7eb2e8f9f7 742 hdma->XferHalfCpltCallback = pCallback;
<> 144:ef7eb2e8f9f7 743 break;
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 case HAL_DMA_XFER_ERROR_CB_ID:
<> 144:ef7eb2e8f9f7 746 hdma->XferErrorCallback = pCallback;
<> 144:ef7eb2e8f9f7 747 break;
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749 case HAL_DMA_XFER_ABORT_CB_ID:
<> 144:ef7eb2e8f9f7 750 hdma->XferAbortCallback = pCallback;
<> 144:ef7eb2e8f9f7 751 break;
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753 default:
<> 144:ef7eb2e8f9f7 754 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 755 break;
<> 144:ef7eb2e8f9f7 756 }
<> 144:ef7eb2e8f9f7 757 }
<> 144:ef7eb2e8f9f7 758 else
<> 144:ef7eb2e8f9f7 759 {
<> 144:ef7eb2e8f9f7 760 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 761 }
<> 144:ef7eb2e8f9f7 762
<> 144:ef7eb2e8f9f7 763 /* Release Lock */
<> 144:ef7eb2e8f9f7 764 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 765
<> 144:ef7eb2e8f9f7 766 return status;
<> 144:ef7eb2e8f9f7 767 }
<> 144:ef7eb2e8f9f7 768
<> 144:ef7eb2e8f9f7 769 /**
<> 144:ef7eb2e8f9f7 770 * @brief UnRegister callbacks
<> 144:ef7eb2e8f9f7 771 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 772 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 773 * @param CallbackID: User Callback identifer
<> 144:ef7eb2e8f9f7 774 * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
<> 144:ef7eb2e8f9f7 775 * @retval HAL status
<> 144:ef7eb2e8f9f7 776 */
<> 144:ef7eb2e8f9f7 777 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
<> 144:ef7eb2e8f9f7 778 {
<> 144:ef7eb2e8f9f7 779 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 780
<> 144:ef7eb2e8f9f7 781 /* Process locked */
<> 144:ef7eb2e8f9f7 782 __HAL_LOCK(hdma);
<> 144:ef7eb2e8f9f7 783
<> 144:ef7eb2e8f9f7 784 if(HAL_DMA_STATE_READY == hdma->State)
<> 144:ef7eb2e8f9f7 785 {
<> 144:ef7eb2e8f9f7 786 switch (CallbackID)
<> 144:ef7eb2e8f9f7 787 {
<> 144:ef7eb2e8f9f7 788 case HAL_DMA_XFER_CPLT_CB_ID:
<> 144:ef7eb2e8f9f7 789 hdma->XferCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 790 break;
<> 144:ef7eb2e8f9f7 791
<> 144:ef7eb2e8f9f7 792 case HAL_DMA_XFER_HALFCPLT_CB_ID:
<> 144:ef7eb2e8f9f7 793 hdma->XferHalfCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 794 break;
<> 144:ef7eb2e8f9f7 795
<> 144:ef7eb2e8f9f7 796 case HAL_DMA_XFER_ERROR_CB_ID:
<> 144:ef7eb2e8f9f7 797 hdma->XferErrorCallback = NULL;
<> 144:ef7eb2e8f9f7 798 break;
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800 case HAL_DMA_XFER_ABORT_CB_ID:
<> 144:ef7eb2e8f9f7 801 hdma->XferAbortCallback = NULL;
<> 144:ef7eb2e8f9f7 802 break;
<> 144:ef7eb2e8f9f7 803
<> 144:ef7eb2e8f9f7 804 case HAL_DMA_XFER_ALL_CB_ID:
<> 144:ef7eb2e8f9f7 805 hdma->XferCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 806 hdma->XferHalfCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 807 hdma->XferErrorCallback = NULL;
<> 144:ef7eb2e8f9f7 808 hdma->XferAbortCallback = NULL;
<> 144:ef7eb2e8f9f7 809 break;
<> 144:ef7eb2e8f9f7 810
<> 144:ef7eb2e8f9f7 811 default:
<> 144:ef7eb2e8f9f7 812 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 813 break;
<> 144:ef7eb2e8f9f7 814 }
<> 144:ef7eb2e8f9f7 815 }
<> 144:ef7eb2e8f9f7 816 else
<> 144:ef7eb2e8f9f7 817 {
<> 144:ef7eb2e8f9f7 818 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 819 }
<> 144:ef7eb2e8f9f7 820
<> 144:ef7eb2e8f9f7 821 /* Release Lock */
<> 144:ef7eb2e8f9f7 822 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 823
<> 144:ef7eb2e8f9f7 824 return status;
<> 144:ef7eb2e8f9f7 825 }
<> 144:ef7eb2e8f9f7 826
<> 144:ef7eb2e8f9f7 827 /**
<> 144:ef7eb2e8f9f7 828 * @}
<> 144:ef7eb2e8f9f7 829 */
<> 144:ef7eb2e8f9f7 830
<> 144:ef7eb2e8f9f7 831
<> 144:ef7eb2e8f9f7 832
<> 144:ef7eb2e8f9f7 833 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 834 * @brief Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 835 *
<> 144:ef7eb2e8f9f7 836 @verbatim
<> 144:ef7eb2e8f9f7 837 ===============================================================================
<> 144:ef7eb2e8f9f7 838 ##### Peripheral State and Errors functions #####
<> 144:ef7eb2e8f9f7 839 ===============================================================================
<> 144:ef7eb2e8f9f7 840 [..]
<> 144:ef7eb2e8f9f7 841 This subsection provides functions allowing to
<> 144:ef7eb2e8f9f7 842 (+) Check the DMA state
<> 144:ef7eb2e8f9f7 843 (+) Get error code
<> 144:ef7eb2e8f9f7 844
<> 144:ef7eb2e8f9f7 845 @endverbatim
<> 144:ef7eb2e8f9f7 846 * @{
<> 144:ef7eb2e8f9f7 847 */
<> 144:ef7eb2e8f9f7 848
<> 144:ef7eb2e8f9f7 849 /**
<> 144:ef7eb2e8f9f7 850 * @brief Return the DMA hande state.
<> 144:ef7eb2e8f9f7 851 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 852 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 853 * @retval HAL state
<> 144:ef7eb2e8f9f7 854 */
<> 144:ef7eb2e8f9f7 855 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 856 {
<> 144:ef7eb2e8f9f7 857 /* Return DMA handle state */
<> 144:ef7eb2e8f9f7 858 return hdma->State;
<> 144:ef7eb2e8f9f7 859 }
<> 144:ef7eb2e8f9f7 860
<> 144:ef7eb2e8f9f7 861 /**
<> 144:ef7eb2e8f9f7 862 * @brief Return the DMA error code.
<> 144:ef7eb2e8f9f7 863 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 864 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 865 * @retval DMA Error Code
<> 144:ef7eb2e8f9f7 866 */
<> 144:ef7eb2e8f9f7 867 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 868 {
<> 144:ef7eb2e8f9f7 869 return hdma->ErrorCode;
<> 144:ef7eb2e8f9f7 870 }
<> 144:ef7eb2e8f9f7 871
<> 144:ef7eb2e8f9f7 872 /**
<> 144:ef7eb2e8f9f7 873 * @}
<> 144:ef7eb2e8f9f7 874 */
<> 144:ef7eb2e8f9f7 875
<> 144:ef7eb2e8f9f7 876 /**
<> 144:ef7eb2e8f9f7 877 * @}
<> 144:ef7eb2e8f9f7 878 */
<> 144:ef7eb2e8f9f7 879
<> 144:ef7eb2e8f9f7 880 /** @addtogroup DMA_Private_Functions
<> 144:ef7eb2e8f9f7 881 * @{
<> 144:ef7eb2e8f9f7 882 */
<> 144:ef7eb2e8f9f7 883
<> 144:ef7eb2e8f9f7 884 /**
<> 144:ef7eb2e8f9f7 885 * @brief Sets the DMA Transfer parameter.
<> 144:ef7eb2e8f9f7 886 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 887 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 888 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 889 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 890 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 891 * @retval HAL status
<> 144:ef7eb2e8f9f7 892 */
<> 144:ef7eb2e8f9f7 893 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 894 {
<> 144:ef7eb2e8f9f7 895 /* Clear all flags */
<> 144:ef7eb2e8f9f7 896 hdma->DmaBaseAddress->IFCR |= (DMA_ISR_GIF1 << hdma->ChannelIndex);
<> 144:ef7eb2e8f9f7 897
<> 144:ef7eb2e8f9f7 898 /* Configure DMA Channel data length */
<> 144:ef7eb2e8f9f7 899 hdma->Instance->CNDTR = DataLength;
<> 144:ef7eb2e8f9f7 900
<> 144:ef7eb2e8f9f7 901 /* Peripheral to Memory */
<> 144:ef7eb2e8f9f7 902 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
<> 144:ef7eb2e8f9f7 903 {
<> 144:ef7eb2e8f9f7 904 /* Configure DMA Channel destination address */
<> 144:ef7eb2e8f9f7 905 hdma->Instance->CPAR = DstAddress;
<> 144:ef7eb2e8f9f7 906
<> 144:ef7eb2e8f9f7 907 /* Configure DMA Channel source address */
<> 144:ef7eb2e8f9f7 908 hdma->Instance->CMAR = SrcAddress;
<> 144:ef7eb2e8f9f7 909 }
<> 144:ef7eb2e8f9f7 910 /* Memory to Peripheral */
<> 144:ef7eb2e8f9f7 911 else
<> 144:ef7eb2e8f9f7 912 {
<> 144:ef7eb2e8f9f7 913 /* Configure DMA Channel source address */
<> 144:ef7eb2e8f9f7 914 hdma->Instance->CPAR = SrcAddress;
<> 144:ef7eb2e8f9f7 915
<> 144:ef7eb2e8f9f7 916 /* Configure DMA Channel destination address */
<> 144:ef7eb2e8f9f7 917 hdma->Instance->CMAR = DstAddress;
<> 144:ef7eb2e8f9f7 918 }
<> 144:ef7eb2e8f9f7 919 }
<> 144:ef7eb2e8f9f7 920
<> 144:ef7eb2e8f9f7 921 /**
<> 144:ef7eb2e8f9f7 922 * @}
<> 144:ef7eb2e8f9f7 923 */
<> 144:ef7eb2e8f9f7 924
<> 144:ef7eb2e8f9f7 925 /**
<> 144:ef7eb2e8f9f7 926 * @}
<> 144:ef7eb2e8f9f7 927 */
<> 144:ef7eb2e8f9f7 928
<> 144:ef7eb2e8f9f7 929 #endif /* HAL_DMA_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 930 /**
<> 144:ef7eb2e8f9f7 931 * @}
<> 144:ef7eb2e8f9f7 932 */
<> 144:ef7eb2e8f9f7 933
<> 144:ef7eb2e8f9f7 934 /**
<> 144:ef7eb2e8f9f7 935 * @}
<> 144:ef7eb2e8f9f7 936 */
<> 144:ef7eb2e8f9f7 937
<> 144:ef7eb2e8f9f7 938 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/