Umar Naeem / mbed-dev

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targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_nor.c@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_hal_nor.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.5.1
<> 144:ef7eb2e8f9f7 6 * @date 31-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief NOR HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides a generic firmware to drive NOR memories mounted
<> 144:ef7eb2e8f9f7 9 * as external device.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 @verbatim
<> 144:ef7eb2e8f9f7 12 ==============================================================================
<> 144:ef7eb2e8f9f7 13 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 [..]
<> 144:ef7eb2e8f9f7 16 This driver is a generic layered driver which contains a set of APIs used to
<> 144:ef7eb2e8f9f7 17 control NOR flash memories. It uses the FMC layer functions to interface
<> 144:ef7eb2e8f9f7 18 with NOR devices. This driver is used as follows:
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
<> 144:ef7eb2e8f9f7 21 with control and timing parameters for both normal and extended mode.
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 (+) Read NOR flash memory manufacturer code and device IDs using the function
<> 144:ef7eb2e8f9f7 24 HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
<> 144:ef7eb2e8f9f7 25 structure declared by the function caller.
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 (+) Access NOR flash memory by read/write data unit operations using the functions
<> 144:ef7eb2e8f9f7 28 HAL_NOR_Read(), HAL_NOR_Program().
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 (+) Perform NOR flash erase block/chip operations using the functions
<> 144:ef7eb2e8f9f7 31 HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 (+) Read the NOR flash CFI (common flash interface) IDs using the function
<> 144:ef7eb2e8f9f7 34 HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
<> 144:ef7eb2e8f9f7 35 structure declared by the function caller.
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
<> 144:ef7eb2e8f9f7 38 HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 (+) You can monitor the NOR device HAL state by calling the function
<> 144:ef7eb2e8f9f7 41 HAL_NOR_GetState()
<> 144:ef7eb2e8f9f7 42 [..]
<> 144:ef7eb2e8f9f7 43 (@) This driver is a set of generic APIs which handle standard NOR flash operations.
<> 144:ef7eb2e8f9f7 44 If a NOR flash device contains different operations and/or implementations,
<> 144:ef7eb2e8f9f7 45 it should be implemented separately.
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 *** NOR HAL driver macros list ***
<> 144:ef7eb2e8f9f7 48 =============================================
<> 144:ef7eb2e8f9f7 49 [..]
<> 144:ef7eb2e8f9f7 50 Below the list of most used macros in NOR HAL driver.
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 (+) NOR_WRITE : NOR memory write data to specified address
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 @endverbatim
<> 144:ef7eb2e8f9f7 55 ******************************************************************************
<> 144:ef7eb2e8f9f7 56 * @attention
<> 144:ef7eb2e8f9f7 57 *
<> 144:ef7eb2e8f9f7 58 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 59 *
<> 144:ef7eb2e8f9f7 60 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 61 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 62 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 63 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 64 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 65 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 66 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 68 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 69 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 70 *
<> 144:ef7eb2e8f9f7 71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 81 *
<> 144:ef7eb2e8f9f7 82 ******************************************************************************
<> 144:ef7eb2e8f9f7 83 */
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 86 #include "stm32l4xx_hal.h"
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 /** @addtogroup STM32L4xx_HAL_Driver
<> 144:ef7eb2e8f9f7 91 * @{
<> 144:ef7eb2e8f9f7 92 */
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 #ifdef HAL_NOR_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 /** @defgroup NOR NOR
<> 144:ef7eb2e8f9f7 97 * @brief NOR HAL module driver
<> 144:ef7eb2e8f9f7 98 * @{
<> 144:ef7eb2e8f9f7 99 */
<> 144:ef7eb2e8f9f7 100 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 101 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 102 /** @defgroup NOR_Private_Constants NOR Private Constants
<> 144:ef7eb2e8f9f7 103 * @{
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /* Constants to define address to set to write a command */
<> 144:ef7eb2e8f9f7 107 #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
<> 144:ef7eb2e8f9f7 108 #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
<> 144:ef7eb2e8f9f7 109 #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
<> 144:ef7eb2e8f9f7 110 #define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
<> 144:ef7eb2e8f9f7 111 #define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
<> 144:ef7eb2e8f9f7 112 #define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
<> 144:ef7eb2e8f9f7 113 #define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 /* Constants to define data to program a command */
<> 144:ef7eb2e8f9f7 116 #define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
<> 144:ef7eb2e8f9f7 117 #define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
<> 144:ef7eb2e8f9f7 118 #define NOR_CMD_DATA_SECOND (uint16_t)0x0055
<> 144:ef7eb2e8f9f7 119 #define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
<> 144:ef7eb2e8f9f7 120 #define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
<> 144:ef7eb2e8f9f7 121 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
<> 144:ef7eb2e8f9f7 122 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
<> 144:ef7eb2e8f9f7 123 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
<> 144:ef7eb2e8f9f7 124 #define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
<> 144:ef7eb2e8f9f7 125 #define NOR_CMD_DATA_CFI (uint16_t)0x0098
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 #define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
<> 144:ef7eb2e8f9f7 128 #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
<> 144:ef7eb2e8f9f7 129 #define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /* Mask on NOR STATUS REGISTER */
<> 144:ef7eb2e8f9f7 132 #define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
<> 144:ef7eb2e8f9f7 133 #define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /**
<> 144:ef7eb2e8f9f7 136 * @}
<> 144:ef7eb2e8f9f7 137 */
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 140 /** @defgroup NOR_Private_Macros NOR Private Macros
<> 144:ef7eb2e8f9f7 141 * @{
<> 144:ef7eb2e8f9f7 142 */
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 /**
<> 144:ef7eb2e8f9f7 145 * @}
<> 144:ef7eb2e8f9f7 146 */
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 /** @defgroup NOR_Private_Variables NOR Private Variables
<> 144:ef7eb2e8f9f7 151 * @{
<> 144:ef7eb2e8f9f7 152 */
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 /**
<> 144:ef7eb2e8f9f7 157 * @}
<> 144:ef7eb2e8f9f7 158 */
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 /** @defgroup NOR_Exported_Functions NOR Exported Functions
<> 144:ef7eb2e8f9f7 163 * @{
<> 144:ef7eb2e8f9f7 164 */
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 167 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 168 *
<> 144:ef7eb2e8f9f7 169 @verbatim
<> 144:ef7eb2e8f9f7 170 ==============================================================================
<> 144:ef7eb2e8f9f7 171 ##### NOR Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 172 ==============================================================================
<> 144:ef7eb2e8f9f7 173 [..]
<> 144:ef7eb2e8f9f7 174 This section provides functions allowing to initialize/de-initialize
<> 144:ef7eb2e8f9f7 175 the NOR memory
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 @endverbatim
<> 144:ef7eb2e8f9f7 178 * @{
<> 144:ef7eb2e8f9f7 179 */
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 /**
<> 144:ef7eb2e8f9f7 182 * @brief Perform the NOR memory Initialization sequence.
<> 144:ef7eb2e8f9f7 183 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 184 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 185 * @param Timing: pointer to NOR control timing structure
<> 144:ef7eb2e8f9f7 186 * @param ExtTiming: pointer to NOR extended mode timing structure
<> 144:ef7eb2e8f9f7 187 * @retval HAL status
<> 144:ef7eb2e8f9f7 188 */
<> 144:ef7eb2e8f9f7 189 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
<> 144:ef7eb2e8f9f7 190 {
<> 144:ef7eb2e8f9f7 191 /* Check the NOR handle parameter */
<> 144:ef7eb2e8f9f7 192 if(hnor == NULL)
<> 144:ef7eb2e8f9f7 193 {
<> 144:ef7eb2e8f9f7 194 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 195 }
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 if(hnor->State == HAL_NOR_STATE_RESET)
<> 144:ef7eb2e8f9f7 198 {
<> 144:ef7eb2e8f9f7 199 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 200 hnor->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 /* Initialize the low level hardware (MSP) */
<> 144:ef7eb2e8f9f7 203 HAL_NOR_MspInit(hnor);
<> 144:ef7eb2e8f9f7 204 }
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /* Initialize NOR control Interface */
<> 144:ef7eb2e8f9f7 207 FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 /* Initialize NOR timing Interface */
<> 144:ef7eb2e8f9f7 210 FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /* Initialize NOR extended mode timing Interface */
<> 144:ef7eb2e8f9f7 213 FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 /* Enable the NORSRAM device */
<> 144:ef7eb2e8f9f7 216 __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 /* Initialize NOR Memory Data Width*/
<> 144:ef7eb2e8f9f7 219 if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8)
<> 144:ef7eb2e8f9f7 220 {
<> 144:ef7eb2e8f9f7 221 uwNORMemoryDataWidth = NOR_MEMORY_8B;
<> 144:ef7eb2e8f9f7 222 }
<> 144:ef7eb2e8f9f7 223 else
<> 144:ef7eb2e8f9f7 224 {
<> 144:ef7eb2e8f9f7 225 uwNORMemoryDataWidth = NOR_MEMORY_16B;
<> 144:ef7eb2e8f9f7 226 }
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 229 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 return HAL_OK;
<> 144:ef7eb2e8f9f7 232 }
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 /**
<> 144:ef7eb2e8f9f7 235 * @brief Perform NOR memory De-Initialization sequence.
<> 144:ef7eb2e8f9f7 236 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 237 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 238 * @retval HAL status
<> 144:ef7eb2e8f9f7 239 */
<> 144:ef7eb2e8f9f7 240 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
<> 144:ef7eb2e8f9f7 241 {
<> 144:ef7eb2e8f9f7 242 /* De-Initialize the low level hardware (MSP) */
<> 144:ef7eb2e8f9f7 243 HAL_NOR_MspDeInit(hnor);
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /* Configure the NOR registers with their reset values */
<> 144:ef7eb2e8f9f7 246 FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 249 hnor->State = HAL_NOR_STATE_RESET;
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /* Release Lock */
<> 144:ef7eb2e8f9f7 252 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 return HAL_OK;
<> 144:ef7eb2e8f9f7 255 }
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /**
<> 144:ef7eb2e8f9f7 258 * @brief Initialize the NOR MSP.
<> 144:ef7eb2e8f9f7 259 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 260 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 261 * @retval None
<> 144:ef7eb2e8f9f7 262 */
<> 144:ef7eb2e8f9f7 263 __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
<> 144:ef7eb2e8f9f7 264 {
<> 144:ef7eb2e8f9f7 265 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 266 UNUSED(hnor);
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 269 the HAL_NOR_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 270 */
<> 144:ef7eb2e8f9f7 271 }
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /**
<> 144:ef7eb2e8f9f7 274 * @brief DeInitialize the NOR MSP.
<> 144:ef7eb2e8f9f7 275 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 276 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 277 * @retval None
<> 144:ef7eb2e8f9f7 278 */
<> 144:ef7eb2e8f9f7 279 __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
<> 144:ef7eb2e8f9f7 280 {
<> 144:ef7eb2e8f9f7 281 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 282 UNUSED(hnor);
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 285 the HAL_NOR_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 286 */
<> 144:ef7eb2e8f9f7 287 }
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /**
<> 144:ef7eb2e8f9f7 290 * @brief NOR MSP Wait for Ready/Busy signal.
<> 144:ef7eb2e8f9f7 291 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 292 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 293 * @param Timeout: Maximum timeout value
<> 144:ef7eb2e8f9f7 294 * @retval None
<> 144:ef7eb2e8f9f7 295 */
<> 144:ef7eb2e8f9f7 296 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 297 {
<> 144:ef7eb2e8f9f7 298 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 299 UNUSED(hnor);
<> 144:ef7eb2e8f9f7 300 UNUSED(Timeout);
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 303 the HAL_NOR_MspWait could be implemented in the user file
<> 144:ef7eb2e8f9f7 304 */
<> 144:ef7eb2e8f9f7 305 }
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /**
<> 144:ef7eb2e8f9f7 308 * @}
<> 144:ef7eb2e8f9f7 309 */
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
<> 144:ef7eb2e8f9f7 312 * @brief Input Output and memory control functions
<> 144:ef7eb2e8f9f7 313 *
<> 144:ef7eb2e8f9f7 314 @verbatim
<> 144:ef7eb2e8f9f7 315 ==============================================================================
<> 144:ef7eb2e8f9f7 316 ##### NOR Input and Output functions #####
<> 144:ef7eb2e8f9f7 317 ==============================================================================
<> 144:ef7eb2e8f9f7 318 [..]
<> 144:ef7eb2e8f9f7 319 This section provides functions allowing to use and control the NOR memory
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 @endverbatim
<> 144:ef7eb2e8f9f7 322 * @{
<> 144:ef7eb2e8f9f7 323 */
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 /**
<> 144:ef7eb2e8f9f7 326 * @brief Read NOR flash IDs.
<> 144:ef7eb2e8f9f7 327 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 328 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 329 * @param pNOR_ID : pointer to NOR ID structure
<> 144:ef7eb2e8f9f7 330 * @retval HAL status
<> 144:ef7eb2e8f9f7 331 */
<> 144:ef7eb2e8f9f7 332 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
<> 144:ef7eb2e8f9f7 333 {
<> 144:ef7eb2e8f9f7 334 uint32_t deviceaddress = 0;
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /* Process Locked */
<> 144:ef7eb2e8f9f7 337 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 340 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 341 {
<> 144:ef7eb2e8f9f7 342 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 343 }
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 346 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 347 {
<> 144:ef7eb2e8f9f7 348 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 349 }
<> 144:ef7eb2e8f9f7 350 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 351 {
<> 144:ef7eb2e8f9f7 352 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 353 }
<> 144:ef7eb2e8f9f7 354 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 355 {
<> 144:ef7eb2e8f9f7 356 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 357 }
<> 144:ef7eb2e8f9f7 358 else /* FMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 359 {
<> 144:ef7eb2e8f9f7 360 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 361 }
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 364 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 /* Send read ID command */
<> 144:ef7eb2e8f9f7 367 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 144:ef7eb2e8f9f7 368 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 144:ef7eb2e8f9f7 369 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /* Read the NOR IDs */
<> 144:ef7eb2e8f9f7 372 pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
<> 144:ef7eb2e8f9f7 373 pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
<> 144:ef7eb2e8f9f7 374 pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
<> 144:ef7eb2e8f9f7 375 pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 378 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 /* Process unlocked */
<> 144:ef7eb2e8f9f7 381 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 return HAL_OK;
<> 144:ef7eb2e8f9f7 384 }
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 /**
<> 144:ef7eb2e8f9f7 387 * @brief Return the NOR memory to Read mode.
<> 144:ef7eb2e8f9f7 388 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 389 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 390 * @retval HAL status
<> 144:ef7eb2e8f9f7 391 */
<> 144:ef7eb2e8f9f7 392 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
<> 144:ef7eb2e8f9f7 393 {
<> 144:ef7eb2e8f9f7 394 uint32_t deviceaddress = 0;
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /* Process Locked */
<> 144:ef7eb2e8f9f7 397 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 400 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 401 {
<> 144:ef7eb2e8f9f7 402 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 403 }
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 406 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 407 {
<> 144:ef7eb2e8f9f7 408 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 409 }
<> 144:ef7eb2e8f9f7 410 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 411 {
<> 144:ef7eb2e8f9f7 412 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 413 }
<> 144:ef7eb2e8f9f7 414 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 415 {
<> 144:ef7eb2e8f9f7 416 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 417 }
<> 144:ef7eb2e8f9f7 418 else /* FMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 419 {
<> 144:ef7eb2e8f9f7 420 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 421 }
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 426 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 /* Process unlocked */
<> 144:ef7eb2e8f9f7 429 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 return HAL_OK;
<> 144:ef7eb2e8f9f7 432 }
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 /**
<> 144:ef7eb2e8f9f7 435 * @brief Read data from NOR memory.
<> 144:ef7eb2e8f9f7 436 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 437 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 438 * @param pAddress: pointer to Device address
<> 144:ef7eb2e8f9f7 439 * @param pData : pointer to read data
<> 144:ef7eb2e8f9f7 440 * @retval HAL status
<> 144:ef7eb2e8f9f7 441 */
<> 144:ef7eb2e8f9f7 442 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
<> 144:ef7eb2e8f9f7 443 {
<> 144:ef7eb2e8f9f7 444 uint32_t deviceaddress = 0;
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 /* Process Locked */
<> 144:ef7eb2e8f9f7 447 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 450 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 451 {
<> 144:ef7eb2e8f9f7 452 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 453 }
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 456 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 457 {
<> 144:ef7eb2e8f9f7 458 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 459 }
<> 144:ef7eb2e8f9f7 460 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 461 {
<> 144:ef7eb2e8f9f7 462 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 463 }
<> 144:ef7eb2e8f9f7 464 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 465 {
<> 144:ef7eb2e8f9f7 466 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 467 }
<> 144:ef7eb2e8f9f7 468 else /* FMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 469 {
<> 144:ef7eb2e8f9f7 470 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 471 }
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 474 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 /* Send read data command */
<> 144:ef7eb2e8f9f7 477 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 144:ef7eb2e8f9f7 478 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 144:ef7eb2e8f9f7 479 NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET);
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 /* Read the data */
<> 144:ef7eb2e8f9f7 482 *pData = *(__IO uint32_t *)(uint32_t)pAddress;
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 485 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 /* Process unlocked */
<> 144:ef7eb2e8f9f7 488 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 return HAL_OK;
<> 144:ef7eb2e8f9f7 491 }
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 /**
<> 144:ef7eb2e8f9f7 494 * @brief Program data to NOR memory.
<> 144:ef7eb2e8f9f7 495 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 496 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 497 * @param pAddress: Device address
<> 144:ef7eb2e8f9f7 498 * @param pData : pointer to the data to write
<> 144:ef7eb2e8f9f7 499 * @retval HAL status
<> 144:ef7eb2e8f9f7 500 */
<> 144:ef7eb2e8f9f7 501 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
<> 144:ef7eb2e8f9f7 502 {
<> 144:ef7eb2e8f9f7 503 uint32_t deviceaddress = 0;
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 /* Process Locked */
<> 144:ef7eb2e8f9f7 506 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 509 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 510 {
<> 144:ef7eb2e8f9f7 511 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 512 }
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 515 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 516 {
<> 144:ef7eb2e8f9f7 517 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 518 }
<> 144:ef7eb2e8f9f7 519 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 520 {
<> 144:ef7eb2e8f9f7 521 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 522 }
<> 144:ef7eb2e8f9f7 523 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 524 {
<> 144:ef7eb2e8f9f7 525 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 526 }
<> 144:ef7eb2e8f9f7 527 else /* FMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 528 {
<> 144:ef7eb2e8f9f7 529 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 530 }
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 533 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 /* Send program data command */
<> 144:ef7eb2e8f9f7 536 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 144:ef7eb2e8f9f7 537 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 144:ef7eb2e8f9f7 538 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 /* Write the data */
<> 144:ef7eb2e8f9f7 541 NOR_WRITE(pAddress, *pData);
<> 144:ef7eb2e8f9f7 542
<> 144:ef7eb2e8f9f7 543 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 544 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 545
<> 144:ef7eb2e8f9f7 546 /* Process unlocked */
<> 144:ef7eb2e8f9f7 547 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 return HAL_OK;
<> 144:ef7eb2e8f9f7 550 }
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552 /**
<> 144:ef7eb2e8f9f7 553 * @brief Read a block of data from the FMC NOR memory.
<> 144:ef7eb2e8f9f7 554 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 555 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 556 * @param uwAddress: NOR memory internal address to read from.
<> 144:ef7eb2e8f9f7 557 * @param pData: pointer to the buffer that receives the data read from the
<> 144:ef7eb2e8f9f7 558 * NOR memory.
<> 144:ef7eb2e8f9f7 559 * @param uwBufferSize : number of Half word to read.
<> 144:ef7eb2e8f9f7 560 * @retval HAL status
<> 144:ef7eb2e8f9f7 561 */
<> 144:ef7eb2e8f9f7 562 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
<> 144:ef7eb2e8f9f7 563 {
<> 144:ef7eb2e8f9f7 564 uint32_t deviceaddress = 0;
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 /* Process Locked */
<> 144:ef7eb2e8f9f7 567 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 570 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 571 {
<> 144:ef7eb2e8f9f7 572 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 573 }
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 576 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 577 {
<> 144:ef7eb2e8f9f7 578 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 579 }
<> 144:ef7eb2e8f9f7 580 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 581 {
<> 144:ef7eb2e8f9f7 582 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 583 }
<> 144:ef7eb2e8f9f7 584 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 585 {
<> 144:ef7eb2e8f9f7 586 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 587 }
<> 144:ef7eb2e8f9f7 588 else /* FMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 589 {
<> 144:ef7eb2e8f9f7 590 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 591 }
<> 144:ef7eb2e8f9f7 592
<> 144:ef7eb2e8f9f7 593 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 594 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 595
<> 144:ef7eb2e8f9f7 596 /* Send read data command */
<> 144:ef7eb2e8f9f7 597 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 144:ef7eb2e8f9f7 598 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 144:ef7eb2e8f9f7 599 NOR_WRITE(uwAddress, NOR_CMD_DATA_READ_RESET);
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 /* Read buffer */
<> 144:ef7eb2e8f9f7 602 while( uwBufferSize > 0)
<> 144:ef7eb2e8f9f7 603 {
<> 144:ef7eb2e8f9f7 604 *pData++ = *(__IO uint16_t *)uwAddress;
<> 144:ef7eb2e8f9f7 605 uwAddress += 2;
<> 144:ef7eb2e8f9f7 606 uwBufferSize--;
<> 144:ef7eb2e8f9f7 607 }
<> 144:ef7eb2e8f9f7 608
<> 144:ef7eb2e8f9f7 609 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 610 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 /* Process unlocked */
<> 144:ef7eb2e8f9f7 613 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615 return HAL_OK;
<> 144:ef7eb2e8f9f7 616 }
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 /**
<> 144:ef7eb2e8f9f7 619 * @brief Write a half-word buffer to the FMC NOR memory. This function
<> 144:ef7eb2e8f9f7 620 * must be used only with S29GL128P NOR memory.
<> 144:ef7eb2e8f9f7 621 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 622 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 623 * @param uwAddress: NOR memory internal address from which the data
<> 144:ef7eb2e8f9f7 624 * @note Some NOR memory need Address aligned to xx bytes (can be aligned to
<> 144:ef7eb2e8f9f7 625 * 64 bytes boundary for example).
<> 144:ef7eb2e8f9f7 626 * @param pData: pointer to source data buffer.
<> 144:ef7eb2e8f9f7 627 * @param uwBufferSize: number of Half words to write.
<> 144:ef7eb2e8f9f7 628 * @note The maximum buffer size allowed is NOR memory dependent
<> 144:ef7eb2e8f9f7 629 * (can be 64 Bytes max for example).
<> 144:ef7eb2e8f9f7 630 * @retval HAL status
<> 144:ef7eb2e8f9f7 631 */
<> 144:ef7eb2e8f9f7 632 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
<> 144:ef7eb2e8f9f7 633 {
<> 144:ef7eb2e8f9f7 634 uint16_t * p_currentaddress = (uint16_t *)NULL;
<> 144:ef7eb2e8f9f7 635 uint16_t * p_endaddress = (uint16_t *)NULL;
<> 144:ef7eb2e8f9f7 636 uint32_t lastloadedaddress = 0, deviceaddress = 0;
<> 144:ef7eb2e8f9f7 637
<> 144:ef7eb2e8f9f7 638 /* Process Locked */
<> 144:ef7eb2e8f9f7 639 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 642 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 643 {
<> 144:ef7eb2e8f9f7 644 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 645 }
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 648 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 649 {
<> 144:ef7eb2e8f9f7 650 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 651 }
<> 144:ef7eb2e8f9f7 652 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 653 {
<> 144:ef7eb2e8f9f7 654 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 655 }
<> 144:ef7eb2e8f9f7 656 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 657 {
<> 144:ef7eb2e8f9f7 658 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 659 }
<> 144:ef7eb2e8f9f7 660 else /* FMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 661 {
<> 144:ef7eb2e8f9f7 662 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 663 }
<> 144:ef7eb2e8f9f7 664
<> 144:ef7eb2e8f9f7 665 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 666 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668 /* Initialize variables */
<> 144:ef7eb2e8f9f7 669 p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));
<> 144:ef7eb2e8f9f7 670 p_endaddress = p_currentaddress + (uwBufferSize-1);
<> 144:ef7eb2e8f9f7 671 lastloadedaddress = (uint32_t)(uwAddress);
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673 /* Issue unlock command sequence */
<> 144:ef7eb2e8f9f7 674 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 144:ef7eb2e8f9f7 675 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 /* Write Buffer Load Command */
<> 144:ef7eb2e8f9f7 678 NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG);
<> 144:ef7eb2e8f9f7 679 NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1));
<> 144:ef7eb2e8f9f7 680
<> 144:ef7eb2e8f9f7 681 /* Load Data into NOR Buffer */
<> 144:ef7eb2e8f9f7 682 while(p_currentaddress <= p_endaddress)
<> 144:ef7eb2e8f9f7 683 {
<> 144:ef7eb2e8f9f7 684 /* Store last loaded address & data value (for polling) */
<> 144:ef7eb2e8f9f7 685 lastloadedaddress = (uint32_t)p_currentaddress;
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 NOR_WRITE(p_currentaddress, *pData++);
<> 144:ef7eb2e8f9f7 688
<> 144:ef7eb2e8f9f7 689 p_currentaddress++;
<> 144:ef7eb2e8f9f7 690 }
<> 144:ef7eb2e8f9f7 691
<> 144:ef7eb2e8f9f7 692 NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 695 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697 /* Process unlocked */
<> 144:ef7eb2e8f9f7 698 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 return HAL_OK;
<> 144:ef7eb2e8f9f7 701
<> 144:ef7eb2e8f9f7 702 }
<> 144:ef7eb2e8f9f7 703
<> 144:ef7eb2e8f9f7 704 /**
<> 144:ef7eb2e8f9f7 705 * @brief Erase the specified block of the NOR memory.
<> 144:ef7eb2e8f9f7 706 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 707 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 708 * @param BlockAddress : Block to erase address
<> 144:ef7eb2e8f9f7 709 * @param Address: Device address
<> 144:ef7eb2e8f9f7 710 * @retval HAL status
<> 144:ef7eb2e8f9f7 711 */
<> 144:ef7eb2e8f9f7 712 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
<> 144:ef7eb2e8f9f7 713 {
<> 144:ef7eb2e8f9f7 714 uint32_t deviceaddress = 0;
<> 144:ef7eb2e8f9f7 715
<> 144:ef7eb2e8f9f7 716 /* Process Locked */
<> 144:ef7eb2e8f9f7 717 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 718
<> 144:ef7eb2e8f9f7 719 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 720 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 721 {
<> 144:ef7eb2e8f9f7 722 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 723 }
<> 144:ef7eb2e8f9f7 724
<> 144:ef7eb2e8f9f7 725 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 726 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 727 {
<> 144:ef7eb2e8f9f7 728 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 729 }
<> 144:ef7eb2e8f9f7 730 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 731 {
<> 144:ef7eb2e8f9f7 732 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 733 }
<> 144:ef7eb2e8f9f7 734 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 735 {
<> 144:ef7eb2e8f9f7 736 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 737 }
<> 144:ef7eb2e8f9f7 738 else /* FMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 739 {
<> 144:ef7eb2e8f9f7 740 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 741 }
<> 144:ef7eb2e8f9f7 742
<> 144:ef7eb2e8f9f7 743 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 744 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 745
<> 144:ef7eb2e8f9f7 746 /* Send block erase command sequence */
<> 144:ef7eb2e8f9f7 747 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 144:ef7eb2e8f9f7 748 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 144:ef7eb2e8f9f7 749 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
<> 144:ef7eb2e8f9f7 750 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
<> 144:ef7eb2e8f9f7 751 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
<> 144:ef7eb2e8f9f7 752 NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 /* Check the NOR memory status and update the controller state */
<> 144:ef7eb2e8f9f7 755 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 756
<> 144:ef7eb2e8f9f7 757 /* Process unlocked */
<> 144:ef7eb2e8f9f7 758 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 759
<> 144:ef7eb2e8f9f7 760 return HAL_OK;
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 }
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764 /**
<> 144:ef7eb2e8f9f7 765 * @brief Erase the entire NOR chip.
<> 144:ef7eb2e8f9f7 766 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 767 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 768 * @param Address : Device address
<> 144:ef7eb2e8f9f7 769 * @retval HAL status
<> 144:ef7eb2e8f9f7 770 */
<> 144:ef7eb2e8f9f7 771 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
<> 144:ef7eb2e8f9f7 772 {
<> 144:ef7eb2e8f9f7 773 uint32_t deviceaddress = 0;
<> 144:ef7eb2e8f9f7 774
<> 144:ef7eb2e8f9f7 775 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 776 UNUSED(Address);
<> 144:ef7eb2e8f9f7 777
<> 144:ef7eb2e8f9f7 778 /* Process Locked */
<> 144:ef7eb2e8f9f7 779 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 780
<> 144:ef7eb2e8f9f7 781 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 782 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 783 {
<> 144:ef7eb2e8f9f7 784 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 785 }
<> 144:ef7eb2e8f9f7 786
<> 144:ef7eb2e8f9f7 787 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 788 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 789 {
<> 144:ef7eb2e8f9f7 790 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 791 }
<> 144:ef7eb2e8f9f7 792 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 793 {
<> 144:ef7eb2e8f9f7 794 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 795 }
<> 144:ef7eb2e8f9f7 796 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 797 {
<> 144:ef7eb2e8f9f7 798 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 799 }
<> 144:ef7eb2e8f9f7 800 else /* FMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 801 {
<> 144:ef7eb2e8f9f7 802 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 803 }
<> 144:ef7eb2e8f9f7 804
<> 144:ef7eb2e8f9f7 805 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 806 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 807
<> 144:ef7eb2e8f9f7 808 /* Send NOR chip erase command sequence */
<> 144:ef7eb2e8f9f7 809 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 144:ef7eb2e8f9f7 810 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 144:ef7eb2e8f9f7 811 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
<> 144:ef7eb2e8f9f7 812 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
<> 144:ef7eb2e8f9f7 813 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
<> 144:ef7eb2e8f9f7 814 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
<> 144:ef7eb2e8f9f7 815
<> 144:ef7eb2e8f9f7 816 /* Check the NOR memory status and update the controller state */
<> 144:ef7eb2e8f9f7 817 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 818
<> 144:ef7eb2e8f9f7 819 /* Process unlocked */
<> 144:ef7eb2e8f9f7 820 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 821
<> 144:ef7eb2e8f9f7 822 return HAL_OK;
<> 144:ef7eb2e8f9f7 823 }
<> 144:ef7eb2e8f9f7 824
<> 144:ef7eb2e8f9f7 825 /**
<> 144:ef7eb2e8f9f7 826 * @brief Read NOR flash CFI IDs.
<> 144:ef7eb2e8f9f7 827 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 828 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 829 * @param pNOR_CFI : pointer to NOR CFI IDs structure
<> 144:ef7eb2e8f9f7 830 * @retval HAL status
<> 144:ef7eb2e8f9f7 831 */
<> 144:ef7eb2e8f9f7 832 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
<> 144:ef7eb2e8f9f7 833 {
<> 144:ef7eb2e8f9f7 834 uint32_t deviceaddress = 0;
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 /* Process Locked */
<> 144:ef7eb2e8f9f7 837 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 838
<> 144:ef7eb2e8f9f7 839 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 840 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 841 {
<> 144:ef7eb2e8f9f7 842 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 843 }
<> 144:ef7eb2e8f9f7 844
<> 144:ef7eb2e8f9f7 845 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 846 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 847 {
<> 144:ef7eb2e8f9f7 848 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 849 }
<> 144:ef7eb2e8f9f7 850 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 851 {
<> 144:ef7eb2e8f9f7 852 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 853 }
<> 144:ef7eb2e8f9f7 854 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 855 {
<> 144:ef7eb2e8f9f7 856 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 857 }
<> 144:ef7eb2e8f9f7 858 else /* FMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 859 {
<> 144:ef7eb2e8f9f7 860 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 861 }
<> 144:ef7eb2e8f9f7 862
<> 144:ef7eb2e8f9f7 863 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 864 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 865
<> 144:ef7eb2e8f9f7 866 /* Send read CFI query command */
<> 144:ef7eb2e8f9f7 867 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
<> 144:ef7eb2e8f9f7 868
<> 144:ef7eb2e8f9f7 869 /* read the NOR CFI information */
<> 144:ef7eb2e8f9f7 870 pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
<> 144:ef7eb2e8f9f7 871 pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
<> 144:ef7eb2e8f9f7 872 pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
<> 144:ef7eb2e8f9f7 873 pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
<> 144:ef7eb2e8f9f7 874
<> 144:ef7eb2e8f9f7 875 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 876 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 877
<> 144:ef7eb2e8f9f7 878 /* Process unlocked */
<> 144:ef7eb2e8f9f7 879 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 880
<> 144:ef7eb2e8f9f7 881 return HAL_OK;
<> 144:ef7eb2e8f9f7 882 }
<> 144:ef7eb2e8f9f7 883
<> 144:ef7eb2e8f9f7 884 /**
<> 144:ef7eb2e8f9f7 885 * @}
<> 144:ef7eb2e8f9f7 886 */
<> 144:ef7eb2e8f9f7 887
<> 144:ef7eb2e8f9f7 888 /** @defgroup NOR_Exported_Functions_Group3 Peripheral Control functions
<> 144:ef7eb2e8f9f7 889 * @brief management functions
<> 144:ef7eb2e8f9f7 890 *
<> 144:ef7eb2e8f9f7 891 @verbatim
<> 144:ef7eb2e8f9f7 892 ==============================================================================
<> 144:ef7eb2e8f9f7 893 ##### NOR Control functions #####
<> 144:ef7eb2e8f9f7 894 ==============================================================================
<> 144:ef7eb2e8f9f7 895 [..]
<> 144:ef7eb2e8f9f7 896 This subsection provides a set of functions allowing to control dynamically
<> 144:ef7eb2e8f9f7 897 the NOR interface.
<> 144:ef7eb2e8f9f7 898
<> 144:ef7eb2e8f9f7 899 @endverbatim
<> 144:ef7eb2e8f9f7 900 * @{
<> 144:ef7eb2e8f9f7 901 */
<> 144:ef7eb2e8f9f7 902
<> 144:ef7eb2e8f9f7 903 /**
<> 144:ef7eb2e8f9f7 904 * @brief Enable dynamically NOR write operation.
<> 144:ef7eb2e8f9f7 905 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 906 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 907 * @retval HAL status
<> 144:ef7eb2e8f9f7 908 */
<> 144:ef7eb2e8f9f7 909 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
<> 144:ef7eb2e8f9f7 910 {
<> 144:ef7eb2e8f9f7 911 /* Process Locked */
<> 144:ef7eb2e8f9f7 912 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 913
<> 144:ef7eb2e8f9f7 914 /* Enable write operation */
<> 144:ef7eb2e8f9f7 915 FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
<> 144:ef7eb2e8f9f7 916
<> 144:ef7eb2e8f9f7 917 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 918 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 919
<> 144:ef7eb2e8f9f7 920 /* Process unlocked */
<> 144:ef7eb2e8f9f7 921 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 922
<> 144:ef7eb2e8f9f7 923 return HAL_OK;
<> 144:ef7eb2e8f9f7 924 }
<> 144:ef7eb2e8f9f7 925
<> 144:ef7eb2e8f9f7 926 /**
<> 144:ef7eb2e8f9f7 927 * @brief Disable dynamically NOR write operation.
<> 144:ef7eb2e8f9f7 928 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 929 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 930 * @retval HAL status
<> 144:ef7eb2e8f9f7 931 */
<> 144:ef7eb2e8f9f7 932 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
<> 144:ef7eb2e8f9f7 933 {
<> 144:ef7eb2e8f9f7 934 /* Process Locked */
<> 144:ef7eb2e8f9f7 935 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 936
<> 144:ef7eb2e8f9f7 937 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 938 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 939
<> 144:ef7eb2e8f9f7 940 /* Disable write operation */
<> 144:ef7eb2e8f9f7 941 FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
<> 144:ef7eb2e8f9f7 942
<> 144:ef7eb2e8f9f7 943 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 944 hnor->State = HAL_NOR_STATE_PROTECTED;
<> 144:ef7eb2e8f9f7 945
<> 144:ef7eb2e8f9f7 946 /* Process unlocked */
<> 144:ef7eb2e8f9f7 947 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 948
<> 144:ef7eb2e8f9f7 949 return HAL_OK;
<> 144:ef7eb2e8f9f7 950 }
<> 144:ef7eb2e8f9f7 951
<> 144:ef7eb2e8f9f7 952 /**
<> 144:ef7eb2e8f9f7 953 * @}
<> 144:ef7eb2e8f9f7 954 */
<> 144:ef7eb2e8f9f7 955
<> 144:ef7eb2e8f9f7 956 /** @defgroup NOR_Exported_Functions_Group4 Peripheral State functions
<> 144:ef7eb2e8f9f7 957 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 958 *
<> 144:ef7eb2e8f9f7 959 @verbatim
<> 144:ef7eb2e8f9f7 960 ==============================================================================
<> 144:ef7eb2e8f9f7 961 ##### NOR State functions #####
<> 144:ef7eb2e8f9f7 962 ==============================================================================
<> 144:ef7eb2e8f9f7 963 [..]
<> 144:ef7eb2e8f9f7 964 This subsection permits to get in run-time the status of the NOR controller
<> 144:ef7eb2e8f9f7 965 and the data flow.
<> 144:ef7eb2e8f9f7 966
<> 144:ef7eb2e8f9f7 967 @endverbatim
<> 144:ef7eb2e8f9f7 968 * @{
<> 144:ef7eb2e8f9f7 969 */
<> 144:ef7eb2e8f9f7 970
<> 144:ef7eb2e8f9f7 971 /**
<> 144:ef7eb2e8f9f7 972 * @brief Return the NOR controller handle state.
<> 144:ef7eb2e8f9f7 973 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 974 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 975 * @retval NOR controller state
<> 144:ef7eb2e8f9f7 976 */
<> 144:ef7eb2e8f9f7 977 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
<> 144:ef7eb2e8f9f7 978 {
<> 144:ef7eb2e8f9f7 979 /* Return NOR handle state */
<> 144:ef7eb2e8f9f7 980 return hnor->State;
<> 144:ef7eb2e8f9f7 981 }
<> 144:ef7eb2e8f9f7 982
<> 144:ef7eb2e8f9f7 983 /**
<> 144:ef7eb2e8f9f7 984 * @brief Return the NOR operation status.
<> 144:ef7eb2e8f9f7 985 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 986 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 987 * @param Address: Device address
<> 144:ef7eb2e8f9f7 988 * @param Timeout: NOR programming Timeout
<> 144:ef7eb2e8f9f7 989 * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
<> 144:ef7eb2e8f9f7 990 * or HAL_NOR_STATUS_TIMEOUT
<> 144:ef7eb2e8f9f7 991 */
<> 144:ef7eb2e8f9f7 992 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 993 {
<> 144:ef7eb2e8f9f7 994 HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
<> 144:ef7eb2e8f9f7 995 uint16_t tmp_sr1 = 0, tmp_sr2 = 0;
<> 144:ef7eb2e8f9f7 996 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 997
<> 144:ef7eb2e8f9f7 998 /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
<> 144:ef7eb2e8f9f7 999 HAL_NOR_MspWait(hnor, Timeout);
<> 144:ef7eb2e8f9f7 1000
<> 144:ef7eb2e8f9f7 1001 /* Get tick */
<> 144:ef7eb2e8f9f7 1002 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1003 while((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
<> 144:ef7eb2e8f9f7 1004 {
<> 144:ef7eb2e8f9f7 1005 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1006 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1007 {
<> 144:ef7eb2e8f9f7 1008 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1009 {
<> 144:ef7eb2e8f9f7 1010 status = HAL_NOR_STATUS_TIMEOUT;
<> 144:ef7eb2e8f9f7 1011 }
<> 144:ef7eb2e8f9f7 1012 }
<> 144:ef7eb2e8f9f7 1013
<> 144:ef7eb2e8f9f7 1014 /* Read NOR status register (DQ6 and DQ5) */
<> 144:ef7eb2e8f9f7 1015 tmp_sr1 = *(__IO uint16_t *)Address;
<> 144:ef7eb2e8f9f7 1016 tmp_sr2 = *(__IO uint16_t *)Address;
<> 144:ef7eb2e8f9f7 1017
<> 144:ef7eb2e8f9f7 1018 /* If DQ6 did not toggle between the two reads then return NOR_Success */
<> 144:ef7eb2e8f9f7 1019 if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
<> 144:ef7eb2e8f9f7 1020 {
<> 144:ef7eb2e8f9f7 1021 return HAL_NOR_STATUS_SUCCESS;
<> 144:ef7eb2e8f9f7 1022 }
<> 144:ef7eb2e8f9f7 1023
<> 144:ef7eb2e8f9f7 1024 if((tmp_sr1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5)
<> 144:ef7eb2e8f9f7 1025 {
<> 144:ef7eb2e8f9f7 1026 status = HAL_NOR_STATUS_ONGOING;
<> 144:ef7eb2e8f9f7 1027 }
<> 144:ef7eb2e8f9f7 1028
<> 144:ef7eb2e8f9f7 1029 tmp_sr1 = *(__IO uint16_t *)Address;
<> 144:ef7eb2e8f9f7 1030 tmp_sr2 = *(__IO uint16_t *)Address;
<> 144:ef7eb2e8f9f7 1031
<> 144:ef7eb2e8f9f7 1032 /* If DQ6 did not toggle between the two reads then return NOR_Success */
<> 144:ef7eb2e8f9f7 1033 if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
<> 144:ef7eb2e8f9f7 1034 {
<> 144:ef7eb2e8f9f7 1035 return HAL_NOR_STATUS_SUCCESS;
<> 144:ef7eb2e8f9f7 1036 }
<> 144:ef7eb2e8f9f7 1037 else if((tmp_sr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
<> 144:ef7eb2e8f9f7 1038 {
<> 144:ef7eb2e8f9f7 1039 return HAL_NOR_STATUS_ERROR;
<> 144:ef7eb2e8f9f7 1040 }
<> 144:ef7eb2e8f9f7 1041 }
<> 144:ef7eb2e8f9f7 1042
<> 144:ef7eb2e8f9f7 1043 /* Return the operation status */
<> 144:ef7eb2e8f9f7 1044 return status;
<> 144:ef7eb2e8f9f7 1045 }
<> 144:ef7eb2e8f9f7 1046
<> 144:ef7eb2e8f9f7 1047 /**
<> 144:ef7eb2e8f9f7 1048 * @}
<> 144:ef7eb2e8f9f7 1049 */
<> 144:ef7eb2e8f9f7 1050
<> 144:ef7eb2e8f9f7 1051 /**
<> 144:ef7eb2e8f9f7 1052 * @}
<> 144:ef7eb2e8f9f7 1053 */
<> 144:ef7eb2e8f9f7 1054 /**
<> 144:ef7eb2e8f9f7 1055 * @}
<> 144:ef7eb2e8f9f7 1056 */
<> 144:ef7eb2e8f9f7 1057 #endif /* HAL_NOR_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1058
<> 144:ef7eb2e8f9f7 1059 /**
<> 144:ef7eb2e8f9f7 1060 * @}
<> 144:ef7eb2e8f9f7 1061 */
<> 144:ef7eb2e8f9f7 1062
<> 144:ef7eb2e8f9f7 1063 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
<> 144:ef7eb2e8f9f7 1064
<> 144:ef7eb2e8f9f7 1065 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/