Umar Naeem / mbed-dev

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targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L432KC/device/system_stm32l4xx.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/system_stm32l4xx.c@144:ef7eb2e8f9f7
Child:
153:fa9ff456f731
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file system_stm32l4xx.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.1
<> 144:ef7eb2e8f9f7 6 * @date 29-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * This file provides two functions and one global variable to be called from
<> 144:ef7eb2e8f9f7 10 * user application:
<> 144:ef7eb2e8f9f7 11 * - SystemInit(): This function is called at startup just after reset and
<> 144:ef7eb2e8f9f7 12 * before branch to main program. This call is made inside
<> 144:ef7eb2e8f9f7 13 * the "startup_stm32l4xx.s" file.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
<> 144:ef7eb2e8f9f7 16 * by the user application to setup the SysTick
<> 144:ef7eb2e8f9f7 17 * timer or configure other parameters.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
<> 144:ef7eb2e8f9f7 20 * be called whenever the core clock is changed
<> 144:ef7eb2e8f9f7 21 * during program execution.
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * After each device reset the MSI (4 MHz) is used as system clock source.
<> 144:ef7eb2e8f9f7 24 * Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
<> 144:ef7eb2e8f9f7 25 * configure the system clock before to branch to main program.
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * This file configures the system clock as follows:
<> 144:ef7eb2e8f9f7 28 *=============================================================================
<> 144:ef7eb2e8f9f7 29 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
<> 144:ef7eb2e8f9f7 30 * | (external 8 MHz clock) | (internal 16 MHz)
<> 144:ef7eb2e8f9f7 31 * | 2- PLL_HSE_XTAL | or PLL_MSI
<> 144:ef7eb2e8f9f7 32 * | (external 8 MHz xtal) | (internal 4 MHz)
<> 144:ef7eb2e8f9f7 33 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 34 * SYSCLK(MHz) | 48 | 80
<> 144:ef7eb2e8f9f7 35 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 36 * AHBCLK (MHz) | 48 | 80
<> 144:ef7eb2e8f9f7 37 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 38 * APB1CLK (MHz) | 48 | 80
<> 144:ef7eb2e8f9f7 39 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 40 * APB2CLK (MHz) | 48 | 80
<> 144:ef7eb2e8f9f7 41 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 42 * USB capable (48 MHz precise clock) | YES | NO
<> 144:ef7eb2e8f9f7 43 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 44 *=============================================================================
<> 144:ef7eb2e8f9f7 45 ******************************************************************************
<> 144:ef7eb2e8f9f7 46 * @attention
<> 144:ef7eb2e8f9f7 47 *
<> 144:ef7eb2e8f9f7 48 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 49 *
<> 144:ef7eb2e8f9f7 50 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 51 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 52 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 53 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 54 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 55 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 56 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 57 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 58 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 59 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 60 *
<> 144:ef7eb2e8f9f7 61 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 62 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 64 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 67 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 68 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 69 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 70 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 71 *
<> 144:ef7eb2e8f9f7 72 ******************************************************************************
<> 144:ef7eb2e8f9f7 73 */
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 /** @addtogroup CMSIS
<> 144:ef7eb2e8f9f7 76 * @{
<> 144:ef7eb2e8f9f7 77 */
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 /** @addtogroup stm32l4xx_system
<> 144:ef7eb2e8f9f7 80 * @{
<> 144:ef7eb2e8f9f7 81 */
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 /** @addtogroup STM32L4xx_System_Private_Includes
<> 144:ef7eb2e8f9f7 84 * @{
<> 144:ef7eb2e8f9f7 85 */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 #include "stm32l4xx.h"
<> 144:ef7eb2e8f9f7 88 #include "hal_tick.h"
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 #if !defined (HSE_VALUE)
<> 144:ef7eb2e8f9f7 91 #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
<> 144:ef7eb2e8f9f7 92 #endif /* HSE_VALUE */
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 #if !defined (MSI_VALUE)
<> 144:ef7eb2e8f9f7 95 #define MSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
<> 144:ef7eb2e8f9f7 96 #endif /* MSI_VALUE */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 #if !defined (HSI_VALUE)
<> 144:ef7eb2e8f9f7 99 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
<> 144:ef7eb2e8f9f7 100 #endif /* HSI_VALUE */
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /**
<> 144:ef7eb2e8f9f7 103 * @}
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /** @addtogroup STM32L4xx_System_Private_TypesDefinitions
<> 144:ef7eb2e8f9f7 107 * @{
<> 144:ef7eb2e8f9f7 108 */
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /**
<> 144:ef7eb2e8f9f7 111 * @}
<> 144:ef7eb2e8f9f7 112 */
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /** @addtogroup STM32L4xx_System_Private_Defines
<> 144:ef7eb2e8f9f7 115 * @{
<> 144:ef7eb2e8f9f7 116 */
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 /************************* Miscellaneous Configuration ************************/
<> 144:ef7eb2e8f9f7 119 /*!< Uncomment the following line if you need to relocate your vector Table in
<> 144:ef7eb2e8f9f7 120 Internal SRAM. */
<> 144:ef7eb2e8f9f7 121 /* #define VECT_TAB_SRAM */
<> 144:ef7eb2e8f9f7 122 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
<> 144:ef7eb2e8f9f7 123 This value must be a multiple of 0x200. */
<> 144:ef7eb2e8f9f7 124 /******************************************************************************/
<> 144:ef7eb2e8f9f7 125 /**
<> 144:ef7eb2e8f9f7 126 * @}
<> 144:ef7eb2e8f9f7 127 */
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /** @addtogroup STM32L4xx_System_Private_Macros
<> 144:ef7eb2e8f9f7 130 * @{
<> 144:ef7eb2e8f9f7 131 */
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 // Select the clock sources (default is PLL_MSI) to start with (0=OFF, 1=ON)
<> 144:ef7eb2e8f9f7 134 #define USE_PLL_HSE_EXTC (1) // Use external clock
<> 144:ef7eb2e8f9f7 135 #define USE_PLL_HSE_XTAL (0) // Use external xtal
<> 144:ef7eb2e8f9f7 136 #define USE_PLL_HSI (0) // Use HSI/MSI internal clock (0=MSI, 1=HSI)
<> 144:ef7eb2e8f9f7 137 #define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
<> 144:ef7eb2e8f9f7 138 /**
<> 144:ef7eb2e8f9f7 139 * @}
<> 144:ef7eb2e8f9f7 140 */
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /** @addtogroup STM32L4xx_System_Private_Variables
<> 144:ef7eb2e8f9f7 143 * @{
<> 144:ef7eb2e8f9f7 144 */
<> 144:ef7eb2e8f9f7 145 /* The SystemCoreClock variable is updated in three ways:
<> 144:ef7eb2e8f9f7 146 1) by calling CMSIS function SystemCoreClockUpdate()
<> 144:ef7eb2e8f9f7 147 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
<> 144:ef7eb2e8f9f7 148 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
<> 144:ef7eb2e8f9f7 149 Note: If you use this function to configure the system clock; then there
<> 144:ef7eb2e8f9f7 150 is no need to call the 2 first functions listed above, since SystemCoreClock
<> 144:ef7eb2e8f9f7 151 variable is updated automatically.
<> 144:ef7eb2e8f9f7 152 */
<> 144:ef7eb2e8f9f7 153 uint32_t SystemCoreClock = 4000000;
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
<> 144:ef7eb2e8f9f7 156 const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
<> 144:ef7eb2e8f9f7 157 const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, \
<> 144:ef7eb2e8f9f7 158 4000000, 8000000, 16000000, 24000000, 32000000, 48000000};
<> 144:ef7eb2e8f9f7 159 /**
<> 144:ef7eb2e8f9f7 160 * @}
<> 144:ef7eb2e8f9f7 161 */
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /** @addtogroup STM32L4xx_System_Private_FunctionPrototypes
<> 144:ef7eb2e8f9f7 164 * @{
<> 144:ef7eb2e8f9f7 165 */
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
<> 144:ef7eb2e8f9f7 168 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
<> 144:ef7eb2e8f9f7 169 #endif
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 #if (USE_PLL_HSI != 0)
<> 144:ef7eb2e8f9f7 172 uint8_t SetSysClock_PLL_HSI(void);
<> 144:ef7eb2e8f9f7 173 #endif
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 uint8_t SetSysClock_PLL_MSI(void);
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 /**
<> 144:ef7eb2e8f9f7 178 * @}
<> 144:ef7eb2e8f9f7 179 */
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 /** @addtogroup STM32L4xx_System_Private_Functions
<> 144:ef7eb2e8f9f7 182 * @{
<> 144:ef7eb2e8f9f7 183 */
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /**
<> 144:ef7eb2e8f9f7 186 * @brief Setup the microcontroller system.
<> 144:ef7eb2e8f9f7 187 * @param None
<> 144:ef7eb2e8f9f7 188 * @retval None
<> 144:ef7eb2e8f9f7 189 */
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 void SystemInit(void)
<> 144:ef7eb2e8f9f7 192 {
<> 144:ef7eb2e8f9f7 193 /* FPU settings ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 194 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 144:ef7eb2e8f9f7 195 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
<> 144:ef7eb2e8f9f7 196 #endif
<> 144:ef7eb2e8f9f7 197 /* Reset the RCC clock configuration to the default reset state ------------*/
<> 144:ef7eb2e8f9f7 198 /* Set MSION bit */
<> 144:ef7eb2e8f9f7 199 RCC->CR |= RCC_CR_MSION;
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /* Reset CFGR register */
<> 144:ef7eb2e8f9f7 202 RCC->CFGR = 0x00000000;
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 /* Reset HSEON, CSSON , HSION, and PLLON bits */
<> 144:ef7eb2e8f9f7 205 RCC->CR &= (uint32_t)0xEAF6FFFF;
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /* Reset PLLCFGR register */
<> 144:ef7eb2e8f9f7 208 RCC->PLLCFGR = 0x00001000;
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 /* Reset HSEBYP bit */
<> 144:ef7eb2e8f9f7 211 RCC->CR &= (uint32_t)0xFFFBFFFF;
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /* Disable all interrupts */
<> 144:ef7eb2e8f9f7 214 RCC->CIER = 0x00000000;
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /* Configure the Vector Table location add offset address ------------------*/
<> 144:ef7eb2e8f9f7 217 #ifdef VECT_TAB_SRAM
<> 144:ef7eb2e8f9f7 218 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
<> 144:ef7eb2e8f9f7 219 #else
<> 144:ef7eb2e8f9f7 220 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
<> 144:ef7eb2e8f9f7 221 #endif
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /* Configure the Cube driver */
<> 144:ef7eb2e8f9f7 224 SystemCoreClock = MSI_VALUE; // At this stage the MSI is used as system clock
<> 144:ef7eb2e8f9f7 225 HAL_Init();
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /* Configure the System clock source, PLL Multiplier and Divider factors,
<> 144:ef7eb2e8f9f7 228 AHB/APBx prescalers and Flash settings */
<> 144:ef7eb2e8f9f7 229 SetSysClock();
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 /* Reset the timer to avoid issues after the RAM initialization */
<> 144:ef7eb2e8f9f7 232 TIM_MST_RESET_ON;
<> 144:ef7eb2e8f9f7 233 TIM_MST_RESET_OFF;
<> 144:ef7eb2e8f9f7 234 }
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 /**
<> 144:ef7eb2e8f9f7 237 * @brief Update SystemCoreClock variable according to Clock Register Values.
<> 144:ef7eb2e8f9f7 238 * The SystemCoreClock variable contains the core clock (HCLK), it can
<> 144:ef7eb2e8f9f7 239 * be used by the user application to setup the SysTick timer or configure
<> 144:ef7eb2e8f9f7 240 * other parameters.
<> 144:ef7eb2e8f9f7 241 *
<> 144:ef7eb2e8f9f7 242 * @note Each time the core clock (HCLK) changes, this function must be called
<> 144:ef7eb2e8f9f7 243 * to update SystemCoreClock variable value. Otherwise, any configuration
<> 144:ef7eb2e8f9f7 244 * based on this variable will be incorrect.
<> 144:ef7eb2e8f9f7 245 *
<> 144:ef7eb2e8f9f7 246 * @note - The system frequency computed by this function is not the real
<> 144:ef7eb2e8f9f7 247 * frequency in the chip. It is calculated based on the predefined
<> 144:ef7eb2e8f9f7 248 * constant and the selected clock source:
<> 144:ef7eb2e8f9f7 249 *
<> 144:ef7eb2e8f9f7 250 * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
<> 144:ef7eb2e8f9f7 251 *
<> 144:ef7eb2e8f9f7 252 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
<> 144:ef7eb2e8f9f7 253 *
<> 144:ef7eb2e8f9f7 254 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
<> 144:ef7eb2e8f9f7 255 *
<> 144:ef7eb2e8f9f7 256 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
<> 144:ef7eb2e8f9f7 257 * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
<> 144:ef7eb2e8f9f7 258 *
<> 144:ef7eb2e8f9f7 259 * (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
<> 144:ef7eb2e8f9f7 260 * 4 MHz) but the real value may vary depending on the variations
<> 144:ef7eb2e8f9f7 261 * in voltage and temperature.
<> 144:ef7eb2e8f9f7 262 *
<> 144:ef7eb2e8f9f7 263 * (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
<> 144:ef7eb2e8f9f7 264 * 16 MHz) but the real value may vary depending on the variations
<> 144:ef7eb2e8f9f7 265 * in voltage and temperature.
<> 144:ef7eb2e8f9f7 266 *
<> 144:ef7eb2e8f9f7 267 * (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value
<> 144:ef7eb2e8f9f7 268 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
<> 144:ef7eb2e8f9f7 269 * frequency of the crystal used. Otherwise, this function may
<> 144:ef7eb2e8f9f7 270 * have wrong result.
<> 144:ef7eb2e8f9f7 271 *
<> 144:ef7eb2e8f9f7 272 * - The result of this function could be not correct when using fractional
<> 144:ef7eb2e8f9f7 273 * value for HSE crystal.
<> 144:ef7eb2e8f9f7 274 *
<> 144:ef7eb2e8f9f7 275 * @param None
<> 144:ef7eb2e8f9f7 276 * @retval None
<> 144:ef7eb2e8f9f7 277 */
<> 144:ef7eb2e8f9f7 278 void SystemCoreClockUpdate(void)
<> 144:ef7eb2e8f9f7 279 {
<> 144:ef7eb2e8f9f7 280 uint32_t tmp = 0, msirange = 0, pllvco = 0, pllr = 2, pllsource = 0, pllm = 2;
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /* Get MSI Range frequency--------------------------------------------------*/
<> 144:ef7eb2e8f9f7 283 if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)
<> 144:ef7eb2e8f9f7 284 { /* MSISRANGE from RCC_CSR applies */
<> 144:ef7eb2e8f9f7 285 msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8;
<> 144:ef7eb2e8f9f7 286 }
<> 144:ef7eb2e8f9f7 287 else
<> 144:ef7eb2e8f9f7 288 { /* MSIRANGE from RCC_CR applies */
<> 144:ef7eb2e8f9f7 289 msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4;
<> 144:ef7eb2e8f9f7 290 }
<> 144:ef7eb2e8f9f7 291 /*MSI frequency range in HZ*/
<> 144:ef7eb2e8f9f7 292 msirange = MSIRangeTable[msirange];
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 /* Get SYSCLK source -------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 295 switch (RCC->CFGR & RCC_CFGR_SWS)
<> 144:ef7eb2e8f9f7 296 {
<> 144:ef7eb2e8f9f7 297 case 0x00: /* MSI used as system clock source */
<> 144:ef7eb2e8f9f7 298 SystemCoreClock = msirange;
<> 144:ef7eb2e8f9f7 299 break;
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 case 0x04: /* HSI used as system clock source */
<> 144:ef7eb2e8f9f7 302 SystemCoreClock = HSI_VALUE;
<> 144:ef7eb2e8f9f7 303 break;
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 case 0x08: /* HSE used as system clock source */
<> 144:ef7eb2e8f9f7 306 SystemCoreClock = HSE_VALUE;
<> 144:ef7eb2e8f9f7 307 break;
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 case 0x0C: /* PLL used as system clock source */
<> 144:ef7eb2e8f9f7 310 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
<> 144:ef7eb2e8f9f7 311 SYSCLK = PLL_VCO / PLLR
<> 144:ef7eb2e8f9f7 312 */
<> 144:ef7eb2e8f9f7 313 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
<> 144:ef7eb2e8f9f7 314 pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1 ;
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 switch (pllsource)
<> 144:ef7eb2e8f9f7 317 {
<> 144:ef7eb2e8f9f7 318 case 0x02: /* HSI used as PLL clock source */
<> 144:ef7eb2e8f9f7 319 pllvco = (HSI_VALUE / pllm);
<> 144:ef7eb2e8f9f7 320 break;
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 case 0x03: /* HSE used as PLL clock source */
<> 144:ef7eb2e8f9f7 323 pllvco = (HSE_VALUE / pllm);
<> 144:ef7eb2e8f9f7 324 break;
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 default: /* MSI used as PLL clock source */
<> 144:ef7eb2e8f9f7 327 pllvco = (msirange / pllm);
<> 144:ef7eb2e8f9f7 328 break;
<> 144:ef7eb2e8f9f7 329 }
<> 144:ef7eb2e8f9f7 330 pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
<> 144:ef7eb2e8f9f7 331 pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1) * 2;
<> 144:ef7eb2e8f9f7 332 SystemCoreClock = pllvco/pllr;
<> 144:ef7eb2e8f9f7 333 break;
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 default:
<> 144:ef7eb2e8f9f7 336 SystemCoreClock = msirange;
<> 144:ef7eb2e8f9f7 337 break;
<> 144:ef7eb2e8f9f7 338 }
<> 144:ef7eb2e8f9f7 339 /* Compute HCLK clock frequency --------------------------------------------*/
<> 144:ef7eb2e8f9f7 340 /* Get HCLK prescaler */
<> 144:ef7eb2e8f9f7 341 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
<> 144:ef7eb2e8f9f7 342 /* HCLK clock frequency */
<> 144:ef7eb2e8f9f7 343 SystemCoreClock >>= tmp;
<> 144:ef7eb2e8f9f7 344 }
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 /**
<> 144:ef7eb2e8f9f7 347 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
<> 144:ef7eb2e8f9f7 348 * AHB/APBx prescalers and Flash settings
<> 144:ef7eb2e8f9f7 349 * @note This function should be called only once the RCC clock configuration
<> 144:ef7eb2e8f9f7 350 * is reset to the default reset state (done in SystemInit() function).
<> 144:ef7eb2e8f9f7 351 * @param None
<> 144:ef7eb2e8f9f7 352 * @retval None
<> 144:ef7eb2e8f9f7 353 */
<> 144:ef7eb2e8f9f7 354 void SetSysClock(void)
<> 144:ef7eb2e8f9f7 355 {
<> 144:ef7eb2e8f9f7 356 /* 1- Try to start with HSE and external clock */
<> 144:ef7eb2e8f9f7 357 #if USE_PLL_HSE_EXTC != 0
<> 144:ef7eb2e8f9f7 358 if (SetSysClock_PLL_HSE(1) == 0)
<> 144:ef7eb2e8f9f7 359 #endif
<> 144:ef7eb2e8f9f7 360 {
<> 144:ef7eb2e8f9f7 361 /* 2- If fail try to start with HSE and external xtal */
<> 144:ef7eb2e8f9f7 362 #if USE_PLL_HSE_XTAL != 0
<> 144:ef7eb2e8f9f7 363 if (SetSysClock_PLL_HSE(0) == 0)
<> 144:ef7eb2e8f9f7 364 #endif
<> 144:ef7eb2e8f9f7 365 {
<> 144:ef7eb2e8f9f7 366 /* 3- If fail start with HSI or MSI clock */
<> 144:ef7eb2e8f9f7 367 #if (USE_PLL_HSI != 0)
<> 144:ef7eb2e8f9f7 368 if (SetSysClock_PLL_HSI() == 0)
<> 144:ef7eb2e8f9f7 369 #else
<> 144:ef7eb2e8f9f7 370 if (SetSysClock_PLL_MSI() == 0)
<> 144:ef7eb2e8f9f7 371 #endif
<> 144:ef7eb2e8f9f7 372 {
<> 144:ef7eb2e8f9f7 373 while(1)
<> 144:ef7eb2e8f9f7 374 {
<> 144:ef7eb2e8f9f7 375 // [TODO] Put something here to tell the user that a problem occured...
<> 144:ef7eb2e8f9f7 376 }
<> 144:ef7eb2e8f9f7 377 }
<> 144:ef7eb2e8f9f7 378 }
<> 144:ef7eb2e8f9f7 379 }
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 // Output clock on MCO1 pin(PA8) for debugging purpose
<> 144:ef7eb2e8f9f7 382 #if DEBUG_MCO == 1
<> 144:ef7eb2e8f9f7 383 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
<> 144:ef7eb2e8f9f7 384 #endif
<> 144:ef7eb2e8f9f7 385 }
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
<> 144:ef7eb2e8f9f7 388 /******************************************************************************/
<> 144:ef7eb2e8f9f7 389 /* PLL (clocked by HSE) used as System clock source */
<> 144:ef7eb2e8f9f7 390 /******************************************************************************/
<> 144:ef7eb2e8f9f7 391 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
<> 144:ef7eb2e8f9f7 392 {
<> 144:ef7eb2e8f9f7 393 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
<> 144:ef7eb2e8f9f7 394 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 // Used to gain time after DeepSleep in case HSI is used
<> 144:ef7eb2e8f9f7 397 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
<> 144:ef7eb2e8f9f7 398 {
<> 144:ef7eb2e8f9f7 399 return 0;
<> 144:ef7eb2e8f9f7 400 }
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 // Select MSI as system clock source to allow modification of the PLL configuration
<> 144:ef7eb2e8f9f7 403 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
<> 144:ef7eb2e8f9f7 404 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
<> 144:ef7eb2e8f9f7 405 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 // Enable HSE oscillator and activate PLL with HSE as source
<> 144:ef7eb2e8f9f7 408 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
<> 144:ef7eb2e8f9f7 409 if (bypass == 0)
<> 144:ef7eb2e8f9f7 410 {
<> 144:ef7eb2e8f9f7 411 RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
<> 144:ef7eb2e8f9f7 412 }
<> 144:ef7eb2e8f9f7 413 else
<> 144:ef7eb2e8f9f7 414 {
<> 144:ef7eb2e8f9f7 415 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
<> 144:ef7eb2e8f9f7 416 }
<> 144:ef7eb2e8f9f7 417 RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
<> 144:ef7eb2e8f9f7 418 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz
<> 144:ef7eb2e8f9f7 419 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 // Non-USB configuration : sysclock = 80MHz
<> 144:ef7eb2e8f9f7 422 //RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
<> 144:ef7eb2e8f9f7 423 //RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
<> 144:ef7eb2e8f9f7 424 //RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
<> 144:ef7eb2e8f9f7 425 //RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
<> 144:ef7eb2e8f9f7 426 //RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 // USB configuration : sysclock = 48 MHz
<> 144:ef7eb2e8f9f7 429 RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
<> 144:ef7eb2e8f9f7 430 RCC_OscInitStruct.PLL.PLLN = 24; // VCO output clock = 192 MHz (8 MHz * 24)
<> 144:ef7eb2e8f9f7 431 RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 27.4 MHz (192 MHz / 7)
<> 144:ef7eb2e8f9f7 432 RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 48 MHz (192 MHz / 4) --> OK for USB
<> 144:ef7eb2e8f9f7 433 RCC_OscInitStruct.PLL.PLLR = 4; // PLL clock = 48 MHz (192 MHz / 4)
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
<> 144:ef7eb2e8f9f7 436 {
<> 144:ef7eb2e8f9f7 437 return 0; // FAIL
<> 144:ef7eb2e8f9f7 438 }
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440 // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
<> 144:ef7eb2e8f9f7 441 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
<> 144:ef7eb2e8f9f7 442 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
<> 144:ef7eb2e8f9f7 443 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz
<> 144:ef7eb2e8f9f7 444 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
<> 144:ef7eb2e8f9f7 445 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
<> 144:ef7eb2e8f9f7 446 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
<> 144:ef7eb2e8f9f7 447 {
<> 144:ef7eb2e8f9f7 448 return 0; // FAIL
<> 144:ef7eb2e8f9f7 449 }
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 // Disable MSI Oscillator
<> 144:ef7eb2e8f9f7 452 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
<> 144:ef7eb2e8f9f7 453 RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
<> 144:ef7eb2e8f9f7 454 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
<> 144:ef7eb2e8f9f7 455 HAL_RCC_OscConfig(&RCC_OscInitStruct);
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 // Output clock on MCO1 pin(PA8) for debugging purpose
<> 144:ef7eb2e8f9f7 458 #if DEBUG_MCO == 2
<> 144:ef7eb2e8f9f7 459 if (bypass == 0)
<> 144:ef7eb2e8f9f7 460 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
<> 144:ef7eb2e8f9f7 461 else
<> 144:ef7eb2e8f9f7 462 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
<> 144:ef7eb2e8f9f7 463 #endif
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 return 1; // OK
<> 144:ef7eb2e8f9f7 466 }
<> 144:ef7eb2e8f9f7 467 #endif
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 #if (USE_PLL_HSI != 0)
<> 144:ef7eb2e8f9f7 470 /******************************************************************************/
<> 144:ef7eb2e8f9f7 471 /* PLL (clocked by HSI) used as System clock source */
<> 144:ef7eb2e8f9f7 472 /******************************************************************************/
<> 144:ef7eb2e8f9f7 473 uint8_t SetSysClock_PLL_HSI(void)
<> 144:ef7eb2e8f9f7 474 {
<> 144:ef7eb2e8f9f7 475 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
<> 144:ef7eb2e8f9f7 476 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 // Select MSI as system clock source to allow modification of the PLL configuration
<> 144:ef7eb2e8f9f7 479 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
<> 144:ef7eb2e8f9f7 480 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
<> 144:ef7eb2e8f9f7 481 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483 // Enable HSI oscillator and activate PLL with HSI as source
<> 144:ef7eb2e8f9f7 484 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
<> 144:ef7eb2e8f9f7 485 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
<> 144:ef7eb2e8f9f7 486 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
<> 144:ef7eb2e8f9f7 487 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
<> 144:ef7eb2e8f9f7 488 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
<> 144:ef7eb2e8f9f7 489 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz
<> 144:ef7eb2e8f9f7 490 RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2)
<> 144:ef7eb2e8f9f7 491 RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
<> 144:ef7eb2e8f9f7 492 RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
<> 144:ef7eb2e8f9f7 493 RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
<> 144:ef7eb2e8f9f7 494 RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
<> 144:ef7eb2e8f9f7 495 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
<> 144:ef7eb2e8f9f7 496 {
<> 144:ef7eb2e8f9f7 497 return 0; // FAIL
<> 144:ef7eb2e8f9f7 498 }
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
<> 144:ef7eb2e8f9f7 501 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
<> 144:ef7eb2e8f9f7 502 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
<> 144:ef7eb2e8f9f7 503 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
<> 144:ef7eb2e8f9f7 504 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
<> 144:ef7eb2e8f9f7 505 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
<> 144:ef7eb2e8f9f7 506 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
<> 144:ef7eb2e8f9f7 507 {
<> 144:ef7eb2e8f9f7 508 return 0; // FAIL
<> 144:ef7eb2e8f9f7 509 }
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 // Disable MSI Oscillator
<> 144:ef7eb2e8f9f7 512 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
<> 144:ef7eb2e8f9f7 513 RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
<> 144:ef7eb2e8f9f7 514 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
<> 144:ef7eb2e8f9f7 515 HAL_RCC_OscConfig(&RCC_OscInitStruct);
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 // Output clock on MCO1 pin(PA8) for debugging purpose
<> 144:ef7eb2e8f9f7 518 #if DEBUG_MCO == 3
<> 144:ef7eb2e8f9f7 519 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
<> 144:ef7eb2e8f9f7 520 #endif
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 return 1; // OK
<> 144:ef7eb2e8f9f7 523 }
<> 144:ef7eb2e8f9f7 524 #endif
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 /******************************************************************************/
<> 144:ef7eb2e8f9f7 527 /* PLL (clocked by MSI) used as System clock source */
<> 144:ef7eb2e8f9f7 528 /******************************************************************************/
<> 144:ef7eb2e8f9f7 529 uint8_t SetSysClock_PLL_MSI(void)
<> 144:ef7eb2e8f9f7 530 {
<> 144:ef7eb2e8f9f7 531 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
<> 144:ef7eb2e8f9f7 532 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
<> 144:ef7eb2e8f9f7 533
<> 144:ef7eb2e8f9f7 534 // Enable LSE Oscillator to automatically calibrate the MSI clock
<> 144:ef7eb2e8f9f7 535 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
<> 144:ef7eb2e8f9f7 536 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
<> 144:ef7eb2e8f9f7 537 RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
<> 144:ef7eb2e8f9f7 538 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
<> 144:ef7eb2e8f9f7 539 RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
<> 144:ef7eb2e8f9f7 540 }
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 // Enable MSI oscillator and activate PLL with MSI as source
<> 144:ef7eb2e8f9f7 543 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
<> 144:ef7eb2e8f9f7 544 RCC_OscInitStruct.MSIState = RCC_MSI_ON;
<> 144:ef7eb2e8f9f7 545 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
<> 144:ef7eb2e8f9f7 546 RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
<> 144:ef7eb2e8f9f7 547 RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
<> 144:ef7eb2e8f9f7 548 RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
<> 144:ef7eb2e8f9f7 549 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
<> 144:ef7eb2e8f9f7 550 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; // 4 MHz
<> 144:ef7eb2e8f9f7 551 RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 4 MHz (4 MHz / 1)
<> 144:ef7eb2e8f9f7 552 RCC_OscInitStruct.PLL.PLLN = 40; // VCO output clock = 160 MHz (4 MHz * 40)
<> 144:ef7eb2e8f9f7 553 RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22.86 MHz (160 MHz / 7)
<> 144:ef7eb2e8f9f7 554 RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
<> 144:ef7eb2e8f9f7 555 RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
<> 144:ef7eb2e8f9f7 556 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
<> 144:ef7eb2e8f9f7 557 {
<> 144:ef7eb2e8f9f7 558 return 0; // FAIL
<> 144:ef7eb2e8f9f7 559 }
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
<> 144:ef7eb2e8f9f7 562 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
<> 144:ef7eb2e8f9f7 563 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
<> 144:ef7eb2e8f9f7 564 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
<> 144:ef7eb2e8f9f7 565 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
<> 144:ef7eb2e8f9f7 566 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
<> 144:ef7eb2e8f9f7 567 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
<> 144:ef7eb2e8f9f7 568 {
<> 144:ef7eb2e8f9f7 569 return 0; // FAIL
<> 144:ef7eb2e8f9f7 570 }
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 // Output clock on MCO1 pin(PA8) for debugging purpose
<> 144:ef7eb2e8f9f7 573 #if DEBUG_MCO == 4
<> 144:ef7eb2e8f9f7 574 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
<> 144:ef7eb2e8f9f7 575 #endif
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 return 1; // OK
<> 144:ef7eb2e8f9f7 578 }
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 /**
<> 144:ef7eb2e8f9f7 581 * @}
<> 144:ef7eb2e8f9f7 582 */
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 /**
<> 144:ef7eb2e8f9f7 585 * @}
<> 144:ef7eb2e8f9f7 586 */
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 /**
<> 144:ef7eb2e8f9f7 589 * @}
<> 144:ef7eb2e8f9f7 590 */
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/