Umar Naeem / mbed-dev

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Fork of mbed-dev by Umar Naeem

targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_i2c.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 *******************************************************************************
<> 144:ef7eb2e8f9f7 3 * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
<> 144:ef7eb2e8f9f7 4 * All rights reserved.
<> 144:ef7eb2e8f9f7 5 *
<> 144:ef7eb2e8f9f7 6 * Redistribution and use in source and binary forms, with or without
<> 144:ef7eb2e8f9f7 7 * modification, are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 10 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 12 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 13 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 * 3. Neither the name of ARM Limited nor the names of its contributors
<> 144:ef7eb2e8f9f7 15 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 16 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 17 *
<> 144:ef7eb2e8f9f7 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 28 *******************************************************************************
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30 /*include -------------------------------------*/
<> 144:ef7eb2e8f9f7 31 #include "W7500x.h"
<> 144:ef7eb2e8f9f7 32 #include "W7500x_i2c.h"
<> 144:ef7eb2e8f9f7 33 #include "W7500x_gpio.h"
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 GPIO_InitTypeDef GPIO_InitDef;
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 uint32_t I2C_Init(I2C_ConfigStruct* conf)
<> 144:ef7eb2e8f9f7 38 {
<> 144:ef7eb2e8f9f7 39 uint32_t scl_port_num;
<> 144:ef7eb2e8f9f7 40 uint32_t scl_pin_index;
<> 144:ef7eb2e8f9f7 41 uint32_t sda_port_num;
<> 144:ef7eb2e8f9f7 42 uint32_t sda_pin_index;
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 scl_port_num = I2C_PORT(conf->scl);
<> 144:ef7eb2e8f9f7 45 scl_pin_index = I2C_PIN_INDEX(conf->scl);
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 sda_port_num = I2C_PORT(conf->sda);
<> 144:ef7eb2e8f9f7 48 sda_pin_index = I2C_PIN_INDEX(conf->sda);
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 //SCL setting
<> 144:ef7eb2e8f9f7 51 GPIO_InitDef.GPIO_Pin = scl_pin_index;
<> 144:ef7eb2e8f9f7 52 GPIO_InitDef.GPIO_Mode = GPIO_Mode_OUT;
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 HAL_GPIO_Init((GPIO_TypeDef*)(GPIOA_BASE + (scl_port_num << 24)), &GPIO_InitDef);
<> 144:ef7eb2e8f9f7 55 HAL_GPIO_SetBits((GPIO_TypeDef*)(GPIOA_BASE + (scl_port_num << 24)), scl_pin_index);
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 //SDA setting
<> 144:ef7eb2e8f9f7 58 GPIO_InitDef.GPIO_Pin = sda_pin_index;
<> 144:ef7eb2e8f9f7 59 GPIO_InitDef.GPIO_Mode = GPIO_Mode_IN;
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 HAL_GPIO_Init((GPIO_TypeDef*)(GPIOA_BASE + (sda_port_num << 24)), &GPIO_InitDef);
<> 144:ef7eb2e8f9f7 62 HAL_GPIO_ResetBits((GPIO_TypeDef*)(GPIOA_BASE + (sda_port_num << 24)), sda_pin_index);
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 //Pin muxing
<> 144:ef7eb2e8f9f7 65 HAL_PAD_AFConfig((PAD_Type)scl_port_num, (uint16_t)scl_pin_index, PAD_AF1);
<> 144:ef7eb2e8f9f7 66 HAL_PAD_AFConfig((PAD_Type)sda_port_num, (uint16_t)sda_pin_index, PAD_AF1);
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 return 0;
<> 144:ef7eb2e8f9f7 69 }
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 void I2C_WriteBitSCL(I2C_ConfigStruct* conf, uint8_t data)
<> 144:ef7eb2e8f9f7 72 {
<> 144:ef7eb2e8f9f7 73 uint32_t scl_port_num = I2C_PORT(conf->scl);
<> 144:ef7eb2e8f9f7 74 uint32_t scl_pin_index = I2C_PIN_INDEX(conf->scl);
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 if(data == 1)
<> 144:ef7eb2e8f9f7 77 HAL_GPIO_SetBits((GPIO_TypeDef*)(GPIOA_BASE + (scl_port_num << 24)), scl_pin_index);
<> 144:ef7eb2e8f9f7 78 else
<> 144:ef7eb2e8f9f7 79 HAL_GPIO_ResetBits((GPIO_TypeDef*)(GPIOA_BASE + (scl_port_num << 24)), scl_pin_index);
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 }
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 void I2C_WriteBitSDA(I2C_ConfigStruct* conf, uint8_t data)
<> 144:ef7eb2e8f9f7 84 {
<> 144:ef7eb2e8f9f7 85 uint32_t sda_port_num = I2C_PORT(conf->sda);
<> 144:ef7eb2e8f9f7 86 uint32_t sda_pin_index = I2C_PIN_INDEX(conf->sda);
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 if(data == 1)
<> 144:ef7eb2e8f9f7 89 GPIO_OutEnClr((GPIO_TypeDef*)(GPIOA_BASE + (sda_port_num << 24)), sda_pin_index);
<> 144:ef7eb2e8f9f7 90 else
<> 144:ef7eb2e8f9f7 91 GPIO_OutEnSet((GPIO_TypeDef*)(GPIOA_BASE + (sda_port_num << 24)), sda_pin_index);
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 }
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 uint8_t I2C_ReadBitSDA(I2C_ConfigStruct* conf)
<> 144:ef7eb2e8f9f7 96 {
<> 144:ef7eb2e8f9f7 97 uint32_t sda_port_num = I2C_PORT(conf->sda);
<> 144:ef7eb2e8f9f7 98 uint32_t sda_pin_index = I2C_PIN_INDEX(conf->sda);
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 if(HAL_GPIO_ReadInputDataBit((GPIO_TypeDef*)(GPIOA_BASE + (sda_port_num << 24)), sda_pin_index))
<> 144:ef7eb2e8f9f7 101 return 1;
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 return 0;
<> 144:ef7eb2e8f9f7 104 }
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 void I2C_Start(I2C_ConfigStruct* conf)
<> 144:ef7eb2e8f9f7 107 {
<> 144:ef7eb2e8f9f7 108 I2C_WriteBitSCL(conf, 1);
<> 144:ef7eb2e8f9f7 109 I2C_WriteBitSDA(conf, 1);
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 I2C_WriteBitSDA(conf, 0);
<> 144:ef7eb2e8f9f7 112 I2C_WriteBitSCL(conf, 0);
<> 144:ef7eb2e8f9f7 113 }
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 void I2C_Stop(I2C_ConfigStruct* conf)
<> 144:ef7eb2e8f9f7 116 {
<> 144:ef7eb2e8f9f7 117 I2C_WriteBitSCL(conf, 0);
<> 144:ef7eb2e8f9f7 118 I2C_WriteBitSDA(conf, 0);
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 I2C_WriteBitSCL(conf, 1);
<> 144:ef7eb2e8f9f7 121 I2C_WriteBitSDA(conf, 1);
<> 144:ef7eb2e8f9f7 122 }
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 uint8_t I2C_WriteByte(I2C_ConfigStruct* conf, uint8_t data)
<> 144:ef7eb2e8f9f7 125 {
<> 144:ef7eb2e8f9f7 126 int i;
<> 144:ef7eb2e8f9f7 127 uint8_t ret;
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 //Write byte
<> 144:ef7eb2e8f9f7 130 for(i=0; i<8; i++)
<> 144:ef7eb2e8f9f7 131 {
<> 144:ef7eb2e8f9f7 132 if((data << i) & 0x80)
<> 144:ef7eb2e8f9f7 133 I2C_WriteBitSDA(conf, 1);
<> 144:ef7eb2e8f9f7 134 else
<> 144:ef7eb2e8f9f7 135 I2C_WriteBitSDA(conf, 0);
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 I2C_WriteBitSCL(conf, 1);
<> 144:ef7eb2e8f9f7 138 I2C_WriteBitSCL(conf, 0);
<> 144:ef7eb2e8f9f7 139 }
<> 144:ef7eb2e8f9f7 140 //Make clk for receiving ack
<> 144:ef7eb2e8f9f7 141 I2C_WriteBitSDA(conf, 1);
<> 144:ef7eb2e8f9f7 142 I2C_WriteBitSCL(conf, 1);
<> 144:ef7eb2e8f9f7 143 //Read Ack/Nack
<> 144:ef7eb2e8f9f7 144 ret = I2C_ReadBitSDA(conf);
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 I2C_WriteBitSCL(conf, 0);
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 return ret;
<> 144:ef7eb2e8f9f7 149 }
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 void I2C_SendACK(I2C_ConfigStruct* conf)
<> 144:ef7eb2e8f9f7 152 {
<> 144:ef7eb2e8f9f7 153 I2C_WriteBitSDA(conf, 0);
<> 144:ef7eb2e8f9f7 154 I2C_WriteBitSCL(conf, 1);
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 I2C_WriteBitSCL(conf, 0);
<> 144:ef7eb2e8f9f7 157 }
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 void I2C_SendNACK(I2C_ConfigStruct* conf)
<> 144:ef7eb2e8f9f7 160 {
<> 144:ef7eb2e8f9f7 161 I2C_WriteBitSDA(conf, 1);
<> 144:ef7eb2e8f9f7 162 I2C_WriteBitSCL(conf, 1);
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 I2C_WriteBitSCL(conf, 0);
<> 144:ef7eb2e8f9f7 165 }
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 uint8_t I2C_ReadByte(I2C_ConfigStruct* conf)
<> 144:ef7eb2e8f9f7 168 {
<> 144:ef7eb2e8f9f7 169 int i;
<> 144:ef7eb2e8f9f7 170 uint8_t ret = 0;
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 I2C_WriteBitSDA(conf, 1); //out enable clear(GPIO is input)
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 //Read byte
<> 144:ef7eb2e8f9f7 175 for(i=0; i<8; i++)
<> 144:ef7eb2e8f9f7 176 {
<> 144:ef7eb2e8f9f7 177 I2C_WriteBitSCL(conf, 1);
<> 144:ef7eb2e8f9f7 178 ret = (ret << 1) | (I2C_ReadBitSDA(conf));
<> 144:ef7eb2e8f9f7 179 I2C_WriteBitSCL(conf, 0);
<> 144:ef7eb2e8f9f7 180 }
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 return ret;
<> 144:ef7eb2e8f9f7 183 }
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 int I2C_Write(I2C_ConfigStruct* conf, uint8_t addr, uint8_t* data, uint32_t len)
<> 144:ef7eb2e8f9f7 186 {
<> 144:ef7eb2e8f9f7 187 int i;
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 I2C_Start(conf);
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 //Write addr
<> 144:ef7eb2e8f9f7 192 if(I2C_WriteByte(conf, addr) != 0)
<> 144:ef7eb2e8f9f7 193 {
<> 144:ef7eb2e8f9f7 194 //printf("Received NACK at address phase!!\r\n");
<> 144:ef7eb2e8f9f7 195 return -1;
<> 144:ef7eb2e8f9f7 196 }
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 //Write data
<> 144:ef7eb2e8f9f7 199 for(i=0; i<len; i++)
<> 144:ef7eb2e8f9f7 200 {
<> 144:ef7eb2e8f9f7 201 if(I2C_WriteByte(conf, data[i]))
<> 144:ef7eb2e8f9f7 202 return -1;
<> 144:ef7eb2e8f9f7 203 }
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 I2C_Stop(conf);
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 return 0;//success
<> 144:ef7eb2e8f9f7 208 }
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 int I2C_WriteRepeated(I2C_ConfigStruct* conf, uint8_t addr, uint8_t* data, uint32_t len)
<> 144:ef7eb2e8f9f7 211 {
<> 144:ef7eb2e8f9f7 212 int i;
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 I2C_Start(conf);
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 //Write addr
<> 144:ef7eb2e8f9f7 217 if(I2C_WriteByte(conf, addr) != 0)
<> 144:ef7eb2e8f9f7 218 {
<> 144:ef7eb2e8f9f7 219 //printf("Received NACK at address phase!!\r\n");
<> 144:ef7eb2e8f9f7 220 return -1;
<> 144:ef7eb2e8f9f7 221 }
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 //Write data
<> 144:ef7eb2e8f9f7 224 for(i=0; i<len; i++)
<> 144:ef7eb2e8f9f7 225 {
<> 144:ef7eb2e8f9f7 226 if(I2C_WriteByte(conf, data[i]))
<> 144:ef7eb2e8f9f7 227 return -1;
<> 144:ef7eb2e8f9f7 228 }
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 return 0;//success
<> 144:ef7eb2e8f9f7 231 }
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 int I2C_Read(I2C_ConfigStruct* conf, uint8_t addr, uint8_t* data, uint32_t len)
<> 144:ef7eb2e8f9f7 234 {
<> 144:ef7eb2e8f9f7 235 int i;
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 I2C_Start(conf);
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 //Write addr | read command
<> 144:ef7eb2e8f9f7 240 if(I2C_WriteByte(conf, (addr | 1)) != 0)
<> 144:ef7eb2e8f9f7 241 {
<> 144:ef7eb2e8f9f7 242 //printf("Received NACK at address phase!!\r\n");
<> 144:ef7eb2e8f9f7 243 return -1;
<> 144:ef7eb2e8f9f7 244 }
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 //Read data
<> 144:ef7eb2e8f9f7 247 for(i=0; i<len; i++)
<> 144:ef7eb2e8f9f7 248 {
<> 144:ef7eb2e8f9f7 249 data[i] = I2C_ReadByte(conf);
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 if( i == (len - 1) )
<> 144:ef7eb2e8f9f7 252 I2C_SendNACK(conf);
<> 144:ef7eb2e8f9f7 253 else
<> 144:ef7eb2e8f9f7 254 I2C_SendACK(conf);
<> 144:ef7eb2e8f9f7 255 }
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 I2C_Stop(conf);
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 return 0;//success
<> 144:ef7eb2e8f9f7 260 }
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 int I2C_ReadRepeated(I2C_ConfigStruct* conf, uint8_t addr, uint8_t* data, uint32_t len)
<> 144:ef7eb2e8f9f7 263 {
<> 144:ef7eb2e8f9f7 264 int i;
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 I2C_Start(conf);
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 //Write addr | read command
<> 144:ef7eb2e8f9f7 269 if(I2C_WriteByte(conf, (addr | 1)) != 0)
<> 144:ef7eb2e8f9f7 270 {
<> 144:ef7eb2e8f9f7 271 //printf("Received NACK at address phase!!\r\n");
<> 144:ef7eb2e8f9f7 272 return -1;
<> 144:ef7eb2e8f9f7 273 }
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 //Read data
<> 144:ef7eb2e8f9f7 276 for(i=0; i<len; i++)
<> 144:ef7eb2e8f9f7 277 {
<> 144:ef7eb2e8f9f7 278 data[i] = I2C_ReadByte(conf);
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 if( i == (len - 1) )
<> 144:ef7eb2e8f9f7 281 I2C_SendNACK(conf);
<> 144:ef7eb2e8f9f7 282 else
<> 144:ef7eb2e8f9f7 283 I2C_SendACK(conf);
<> 144:ef7eb2e8f9f7 284 }
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 return 0;//success
<> 144:ef7eb2e8f9f7 287 }
<> 144:ef7eb2e8f9f7 288