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targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_system.h@165:2dd56e6daeec, 2017-05-23 (annotated)

Committer:
ranaumarnaeem
Date:
Tue May 23 12:54:50 2017 +0000
Revision:
165:2dd56e6daeec
Parent:
157:ff67d9f36b67 
jhjg

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 157:ff67d9f36b67 1 /**
<> 157:ff67d9f36b67 2 ******************************************************************************
<> 157:ff67d9f36b67 3 * @file stm32f3xx_ll_system.h
<> 157:ff67d9f36b67 4 * @author MCD Application Team
<> 157:ff67d9f36b67 5 * @version V1.4.0
<> 157:ff67d9f36b67 6 * @date 16-December-2016
<> 157:ff67d9f36b67 7 * @brief Header file of SYSTEM LL module.
<> 157:ff67d9f36b67 8 @verbatim
<> 157:ff67d9f36b67 9 ==============================================================================
<> 157:ff67d9f36b67 10 ##### How to use this driver #####
<> 157:ff67d9f36b67 11 ==============================================================================
<> 157:ff67d9f36b67 12 [..]
<> 157:ff67d9f36b67 13 The LL SYSTEM driver contains a set of generic APIs that can be
<> 157:ff67d9f36b67 14 used by user:
<> 157:ff67d9f36b67 15 (+) Some of the FLASH features need to be handled in the SYSTEM file.
<> 157:ff67d9f36b67 16 (+) Access to DBGCMU registers
<> 157:ff67d9f36b67 17 (+) Access to SYSCFG registers
<> 157:ff67d9f36b67 18
<> 157:ff67d9f36b67 19 @endverbatim
<> 157:ff67d9f36b67 20 ******************************************************************************
<> 157:ff67d9f36b67 21 * @attention
<> 157:ff67d9f36b67 22 *
<> 157:ff67d9f36b67 23 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 157:ff67d9f36b67 24 *
<> 157:ff67d9f36b67 25 * Redistribution and use in source and binary forms, with or without modification,
<> 157:ff67d9f36b67 26 * are permitted provided that the following conditions are met:
<> 157:ff67d9f36b67 27 * 1. Redistributions of source code must retain the above copyright notice,
<> 157:ff67d9f36b67 28 * this list of conditions and the following disclaimer.
<> 157:ff67d9f36b67 29 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 157:ff67d9f36b67 30 * this list of conditions and the following disclaimer in the documentation
<> 157:ff67d9f36b67 31 * and/or other materials provided with the distribution.
<> 157:ff67d9f36b67 32 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 157:ff67d9f36b67 33 * may be used to endorse or promote products derived from this software
<> 157:ff67d9f36b67 34 * without specific prior written permission.
<> 157:ff67d9f36b67 35 *
<> 157:ff67d9f36b67 36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 157:ff67d9f36b67 37 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 157:ff67d9f36b67 38 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 157:ff67d9f36b67 39 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 157:ff67d9f36b67 40 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 157:ff67d9f36b67 41 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 157:ff67d9f36b67 42 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 157:ff67d9f36b67 43 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 157:ff67d9f36b67 44 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 157:ff67d9f36b67 45 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 157:ff67d9f36b67 46 *
<> 157:ff67d9f36b67 47 ******************************************************************************
<> 157:ff67d9f36b67 48 */
<> 157:ff67d9f36b67 49
<> 157:ff67d9f36b67 50 /* Define to prevent recursive inclusion -------------------------------------*/
<> 157:ff67d9f36b67 51 #ifndef __STM32F3xx_LL_SYSTEM_H
<> 157:ff67d9f36b67 52 #define __STM32F3xx_LL_SYSTEM_H
<> 157:ff67d9f36b67 53
<> 157:ff67d9f36b67 54 #ifdef __cplusplus
<> 157:ff67d9f36b67 55 extern "C" {
<> 157:ff67d9f36b67 56 #endif
<> 157:ff67d9f36b67 57
<> 157:ff67d9f36b67 58 /* Includes ------------------------------------------------------------------*/
<> 157:ff67d9f36b67 59 #include "stm32f3xx.h"
<> 157:ff67d9f36b67 60
<> 157:ff67d9f36b67 61 /** @addtogroup STM32F3xx_LL_Driver
<> 157:ff67d9f36b67 62 * @{
<> 157:ff67d9f36b67 63 */
<> 157:ff67d9f36b67 64
<> 157:ff67d9f36b67 65 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
<> 157:ff67d9f36b67 66
<> 157:ff67d9f36b67 67 /** @defgroup SYSTEM_LL SYSTEM
<> 157:ff67d9f36b67 68 * @{
<> 157:ff67d9f36b67 69 */
<> 157:ff67d9f36b67 70
<> 157:ff67d9f36b67 71 /* Private types -------------------------------------------------------------*/
<> 157:ff67d9f36b67 72 /* Private variables ---------------------------------------------------------*/
<> 157:ff67d9f36b67 73
<> 157:ff67d9f36b67 74 /* Private constants ---------------------------------------------------------*/
<> 157:ff67d9f36b67 75 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
<> 157:ff67d9f36b67 76 * @{
<> 157:ff67d9f36b67 77 */
<> 157:ff67d9f36b67 78
<> 157:ff67d9f36b67 79 /* Defines used for position in the register */
<> 157:ff67d9f36b67 80 #define DBGMCU_REVID_POSITION (uint32_t)POSITION_VAL(DBGMCU_IDCODE_REV_ID)
<> 157:ff67d9f36b67 81
<> 157:ff67d9f36b67 82 /* Offset used to access to SYSCFG_CFGR1 and SYSCFG_CFGR3 registers */
<> 157:ff67d9f36b67 83 #define SYSCFG_OFFSET_CFGR1 (uint32_t)0x00000000U
<> 157:ff67d9f36b67 84 #define SYSCFG_OFFSET_CFGR3 (uint32_t)0x00000050U
<> 157:ff67d9f36b67 85
<> 157:ff67d9f36b67 86 /* Mask used for TIM breaks functions */
<> 157:ff67d9f36b67 87 #if defined(SYSCFG_CFGR2_PVD_LOCK) && defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
<> 157:ff67d9f36b67 88 #define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK | SYSCFG_CFGR2_PVD_LOCK)
<> 157:ff67d9f36b67 89 #elif defined(SYSCFG_CFGR2_PVD_LOCK) && !defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
<> 157:ff67d9f36b67 90 #define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK)
<> 157:ff67d9f36b67 91 #elif !defined(SYSCFG_CFGR2_PVD_LOCK) && defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
<> 157:ff67d9f36b67 92 #define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK)
<> 157:ff67d9f36b67 93 #else
<> 157:ff67d9f36b67 94 #define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK)
<> 157:ff67d9f36b67 95 #endif /* SYSCFG_CFGR2_PVD_LOCK && SYSCFG_CFGR2_SRAM_PARITY_LOCK */
<> 157:ff67d9f36b67 96
<> 157:ff67d9f36b67 97 /**
<> 157:ff67d9f36b67 98 * @}
<> 157:ff67d9f36b67 99 */
<> 157:ff67d9f36b67 100
<> 157:ff67d9f36b67 101 /* Private macros ------------------------------------------------------------*/
<> 157:ff67d9f36b67 102
<> 157:ff67d9f36b67 103 /* Exported types ------------------------------------------------------------*/
<> 157:ff67d9f36b67 104 /* Exported constants --------------------------------------------------------*/
<> 157:ff67d9f36b67 105 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
<> 157:ff67d9f36b67 106 * @{
<> 157:ff67d9f36b67 107 */
<> 157:ff67d9f36b67 108
<> 157:ff67d9f36b67 109 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
<> 157:ff67d9f36b67 110 * @{
<> 157:ff67d9f36b67 111 */
<> 157:ff67d9f36b67 112 #define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000 /* Main Flash memory mapped at 0x00000000 */
<> 157:ff67d9f36b67 113 #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /* System Flash memory mapped at 0x00000000 */
<> 157:ff67d9f36b67 114 #define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /* Embedded SRAM mapped at 0x00000000 */
<> 157:ff67d9f36b67 115 #if defined(FMC_BANK1)
<> 157:ff67d9f36b67 116 #define LL_SYSCFG_REMAP_FMC SYSCFG_CFGR1_MEM_MODE_2 /*<! FMC Bank (Only the first two banks) */
<> 157:ff67d9f36b67 117 #endif /* FMC_BANK1 */
<> 157:ff67d9f36b67 118 /**
<> 157:ff67d9f36b67 119 * @}
<> 157:ff67d9f36b67 120 */
<> 157:ff67d9f36b67 121
<> 157:ff67d9f36b67 122 #if defined(SYSCFG_CFGR3_SPI1_RX_DMA_RMP)
<> 157:ff67d9f36b67 123 /** @defgroup SYSTEM_LL_EC_SPI1_DMA_RMP_RX SYSCFG SPI1 RX/TX DMA1 request REMAP
<> 157:ff67d9f36b67 124 * @{
<> 157:ff67d9f36b67 125 */
<> 157:ff67d9f36b67 126 #define LL_SYSCFG_SPI1RX_RMP_DMA1_CH2 (SYSCFG_CFGR3_SPI1_RX_DMA_RMP << 16U | (uint32_t)0x00000000U) /*!< SPI1_RX mapped on DMA1 CH2 */
<> 157:ff67d9f36b67 127 #define LL_SYSCFG_SPI1RX_RMP_DMA1_CH4 (SYSCFG_CFGR3_SPI1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_RX_DMA_RMP_0) /*!< SPI1_RX mapped on DMA1 CH4 */
<> 157:ff67d9f36b67 128 #define LL_SYSCFG_SPI1RX_RMP_DMA1_CH6 (SYSCFG_CFGR3_SPI1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_RX_DMA_RMP_1) /*!< SPI1_RX mapped on DMA1 CH6 */
<> 157:ff67d9f36b67 129 #define LL_SYSCFG_SPI1TX_RMP_DMA1_CH3 (SYSCFG_CFGR3_SPI1_TX_DMA_RMP << 16U | (uint32_t)0x00000000U) /*!< SPI1_TX mapped on DMA1 CH3 */
<> 157:ff67d9f36b67 130 #define LL_SYSCFG_SPI1TX_RMP_DMA1_CH5 (SYSCFG_CFGR3_SPI1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_TX_DMA_RMP_0) /*!< SPI1_TX mapped on DMA1 CH5 */
<> 157:ff67d9f36b67 131 #define LL_SYSCFG_SPI1TX_RMP_DMA1_CH7 (SYSCFG_CFGR3_SPI1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_TX_DMA_RMP_1) /*!< SPI1_TX mapped on DMA1 CH7 */
<> 157:ff67d9f36b67 132 /**
<> 157:ff67d9f36b67 133 * @}
<> 157:ff67d9f36b67 134 */
<> 157:ff67d9f36b67 135 #endif /* SYSCFG_CFGR3_SPI1_RX_DMA_RMP */
<> 157:ff67d9f36b67 136
<> 157:ff67d9f36b67 137 #if defined(SYSCFG_CFGR3_I2C1_RX_DMA_RMP)
<> 157:ff67d9f36b67 138 /** @defgroup SYSTEM_LL_EC_I2C1_DMA_RMP_RX SYSCFG I2C1 RX/TX DMA1 request REMAP
<> 157:ff67d9f36b67 139 * @{
<> 157:ff67d9f36b67 140 */
<> 157:ff67d9f36b67 141 #define LL_SYSCFG_I2C1RX_RMP_DMA1_CH7 (SYSCFG_CFGR3_I2C1_RX_DMA_RMP << 16U | (uint32_t)0x00000000U) /*!< I2C1_RX mapped on DMA1 CH7 */
<> 157:ff67d9f36b67 142 #define LL_SYSCFG_I2C1RX_RMP_DMA1_CH3 (SYSCFG_CFGR3_I2C1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_RX_DMA_RMP_0) /*!< I2C1_RX mapped on DMA1 CH3 */
<> 157:ff67d9f36b67 143 #define LL_SYSCFG_I2C1RX_RMP_DMA1_CH5 (SYSCFG_CFGR3_I2C1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_RX_DMA_RMP_1) /*!< I2C1_RX mapped on DMA1 CH5 */
<> 157:ff67d9f36b67 144 #define LL_SYSCFG_I2C1TX_RMP_DMA1_CH6 (SYSCFG_CFGR3_I2C1_TX_DMA_RMP << 16U | (uint32_t)0x00000000U) /*!< I2C1_TX mapped on DMA1 CH6 */
<> 157:ff67d9f36b67 145 #define LL_SYSCFG_I2C1TX_RMP_DMA1_CH2 (SYSCFG_CFGR3_I2C1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_TX_DMA_RMP_0) /*!< I2C1_TX mapped on DMA1 CH2 */
<> 157:ff67d9f36b67 146 #define LL_SYSCFG_I2C1TX_RMP_DMA1_CH4 (SYSCFG_CFGR3_I2C1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_TX_DMA_RMP_1) /*!< I2C1_TX mapped on DMA1 CH4 */
<> 157:ff67d9f36b67 147 /**
<> 157:ff67d9f36b67 148 * @}
<> 157:ff67d9f36b67 149 */
<> 157:ff67d9f36b67 150
<> 157:ff67d9f36b67 151 #endif /* SYSCFG_CFGR3_I2C1_RX_DMA_RMP */
<> 157:ff67d9f36b67 152
<> 157:ff67d9f36b67 153 #if defined(SYSCFG_CFGR1_ADC24_DMA_RMP) || defined(SYSCFG_CFGR3_ADC2_DMA_RMP)
<> 157:ff67d9f36b67 154 /** @defgroup SYSTEM_LL_EC_ADC24_DMA_REMAP SYSCFG ADC DMA request REMAP
<> 157:ff67d9f36b67 155 * @{
<> 157:ff67d9f36b67 156 */
<> 157:ff67d9f36b67 157 #if defined (SYSCFG_CFGR1_ADC24_DMA_RMP)
<> 157:ff67d9f36b67 158 #define LL_SYSCFG_ADC24_RMP_DMA2_CH12 (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_ADC24_DMA_RMP << 8U | (uint32_t)0x00000000U) /*!< ADC24 DMA requests mapped on DMA2 channels 1 and 2 */
<> 157:ff67d9f36b67 159 #define LL_SYSCFG_ADC24_RMP_DMA2_CH34 (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_ADC24_DMA_RMP << 8U | SYSCFG_CFGR1_ADC24_DMA_RMP) /*!< ADC24 DMA requests mapped on DMA2 channels 3 and 4 */
<> 157:ff67d9f36b67 160 #endif /*SYSCFG_CFGR1_ADC24_DMA_RMP*/
<> 157:ff67d9f36b67 161 #if defined (SYSCFG_CFGR3_ADC2_DMA_RMP)
<> 157:ff67d9f36b67 162 #define LL_SYSCFG_ADC2_RMP_DMA1_CH2 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_0 << 8U | (uint32_t)0x00000000U) /*!< ADC2 mapped on DMA1 channel 2 */
<> 157:ff67d9f36b67 163 #define LL_SYSCFG_ADC2_RMP_DMA1_CH4 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_0 << 8U | SYSCFG_CFGR3_ADC2_DMA_RMP_0) /*!< ADC2 mapped on DMA1 channel 4 */
<> 157:ff67d9f36b67 164 #define LL_SYSCFG_ADC2_RMP_DMA2 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_1 << 8U | (uint32_t)0x00000000U) /*!< ADC2 mapped on DMA2 */
<> 157:ff67d9f36b67 165 #define LL_SYSCFG_ADC2_RMP_DMA1 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_1 << 8U | SYSCFG_CFGR3_ADC2_DMA_RMP_1) /*!< ADC2 mapped on DMA1 */
<> 157:ff67d9f36b67 166 #endif /*SYSCFG_CFGR3_ADC2_DMA_RMP*/
<> 157:ff67d9f36b67 167 /**
<> 157:ff67d9f36b67 168 * @}
<> 157:ff67d9f36b67 169 */
<> 157:ff67d9f36b67 170
<> 157:ff67d9f36b67 171 #endif /* SYSCFG_CFGR1_ADC24_DMA_RMP || SYSCFG_CFGR3_ADC2_DMA_RMP */
<> 157:ff67d9f36b67 172
<> 157:ff67d9f36b67 173 /** @defgroup SYSTEM_LL_EC_DAC1_DMA2_REMAP SYSCFG DAC1/2 DMA1/2 request REMAP
<> 157:ff67d9f36b67 174 * @{
<> 157:ff67d9f36b67 175 */
<> 157:ff67d9f36b67 176 #define LL_SYSCFG_DAC1_CH1_RMP_DMA2_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< DAC_CH1 DMA requests mapped on DMA2 channel 3 */
<> 157:ff67d9f36b67 177 #define LL_SYSCFG_DAC1_CH1_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP) /*!< DAC_CH1 DMA requests mapped on DMA1 channel 3 */
<> 157:ff67d9f36b67 178 #if defined(SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP)
<> 157:ff67d9f36b67 179 #define LL_SYSCFG_DAC1_OUT2_RMP_DMA2_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< DAC1_OUT2 DMA requests mapped on DMA2 channel 4 */
<> 157:ff67d9f36b67 180 #define LL_SYSCFG_DAC1_OUT2_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP) /*!< DAC1_OUT2 DMA requests mapped on DMA1 channel 4 */
<> 157:ff67d9f36b67 181 #endif /*SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP*/
<> 157:ff67d9f36b67 182 #if defined(SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP)
<> 157:ff67d9f36b67 183 #define LL_SYSCFG_DAC2_OUT1_RMP_DMA2_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< DAC2_OUT1 DMA requests mapped on DMA2 channel 5 */
<> 157:ff67d9f36b67 184 #define LL_SYSCFG_DAC2_OUT1_RMP_DMA1_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP) /*!< DAC2_OUT1 DMA requests mapped on DMA1 channel 5 */
<> 157:ff67d9f36b67 185 #endif /*SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP*/
<> 157:ff67d9f36b67 186 #if defined(SYSCFG_CFGR1_DAC2Ch1_DMA_RMP)
<> 157:ff67d9f36b67 187 #define LL_SYSCFG_DAC2_CH1_RMP_NO ((SYSCFG_CFGR1_DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< No remap */
<> 157:ff67d9f36b67 188 #define LL_SYSCFG_DAC2_CH1_RMP_DMA1_CH5 ((SYSCFG_CFGR1_DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_DAC2Ch1_DMA_RMP) /*!< DAC2_CH1 DMA requests mapped on DMA1 channel 5 */
<> 157:ff67d9f36b67 189 #endif /*SYSCFG_CFGR1_DAC2Ch1_DMA_RMP*/
<> 157:ff67d9f36b67 190 /**
<> 157:ff67d9f36b67 191 * @}
<> 157:ff67d9f36b67 192 */
<> 157:ff67d9f36b67 193
<> 157:ff67d9f36b67 194 /** @defgroup SYSTEM_LL_EC_TIM16_DMA1_REMAP SYSCFG TIM DMA request REMAP
<> 157:ff67d9f36b67 195 * @{
<> 157:ff67d9f36b67 196 */
<> 157:ff67d9f36b67 197 #define LL_SYSCFG_TIM16_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM16_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 3 */
<> 157:ff67d9f36b67 198 #define LL_SYSCFG_TIM16_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM16_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6 */
<> 157:ff67d9f36b67 199 #define LL_SYSCFG_TIM17_RMP_DMA1_CH1 ((SYSCFG_CFGR1_TIM17_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 1 */
<> 157:ff67d9f36b67 200 #define LL_SYSCFG_TIM17_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM17_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7 */
<> 157:ff67d9f36b67 201 #define LL_SYSCFG_TIM6_RMP_DMA2_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM6 DMA requests mapped on DMA2 channel 3 */
<> 157:ff67d9f36b67 202 #define LL_SYSCFG_TIM6_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP) /*!< TIM6 DMA requests mapped on DMA1 channel 3 */
<> 157:ff67d9f36b67 203 #if defined(SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP)
<> 157:ff67d9f36b67 204 #define LL_SYSCFG_TIM7_RMP_DMA2_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM7 DMA requests mapped on DMA2 channel 4 */
<> 157:ff67d9f36b67 205 #define LL_SYSCFG_TIM7_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP) /*!< TIM7 DMA requests mapped on DMA1 channel 4 */
<> 157:ff67d9f36b67 206 #endif /*SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP*/
<> 157:ff67d9f36b67 207 #if defined(SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP)
<> 157:ff67d9f36b67 208 #define LL_SYSCFG_TIM18_RMP_DMA2_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM18 DMA requests mapped on DMA2 channel 5 */
<> 157:ff67d9f36b67 209 #define LL_SYSCFG_TIM18_RMP_DMA1_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP) /*!< TIM18 DMA requests mapped on DMA1 channel 5 */
<> 157:ff67d9f36b67 210 #endif /*SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP*/
<> 157:ff67d9f36b67 211 /**
<> 157:ff67d9f36b67 212 * @}
<> 157:ff67d9f36b67 213 */
<> 157:ff67d9f36b67 214
<> 157:ff67d9f36b67 215 #if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP) || defined(SYSCFG_CFGR1_ENCODER_MODE)
<> 157:ff67d9f36b67 216 /** @defgroup SYSTEM_LL_EC_TIM1_ITR3_RMP_TIM4 SYSCFG TIM REMAP
<> 157:ff67d9f36b67 217 * @{
<> 157:ff67d9f36b67 218 */
<> 157:ff67d9f36b67 219 #if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP)
<> 157:ff67d9f36b67 220 #define LL_SYSCFG_TIM1_ITR3_RMP_TIM4_TRGO ((SYSCFG_CFGR1_TIM1_ITR3_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM1_ITR3 = TIM4_TRGO */
<> 157:ff67d9f36b67 221 #define LL_SYSCFG_TIM1_ITR3_RMP_TIM17_OC ((SYSCFG_CFGR1_TIM1_ITR3_RMP << 8U) | SYSCFG_CFGR1_TIM1_ITR3_RMP) /*!< TIM1_ITR3 = TIM17_OC */
<> 157:ff67d9f36b67 222 #endif /* SYSCFG_CFGR1_TIM1_ITR3_RMP */
<> 157:ff67d9f36b67 223 #if defined(SYSCFG_CFGR1_ENCODER_MODE)
<> 157:ff67d9f36b67 224 #define LL_SYSCFG_TIM15_ENCODEMODE_NOREDIRECTION ((SYSCFG_CFGR1_ENCODER_MODE << 8U) | (uint32_t)0x00000000U) /*!< No redirection */
<> 157:ff67d9f36b67 225 #define LL_SYSCFG_TIM15_ENCODEMODE_TIM2 ((SYSCFG_CFGR1_ENCODER_MODE_0 << 8U) | SYSCFG_CFGR1_ENCODER_MODE_0) /*!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
<> 157:ff67d9f36b67 226 #if defined(SYSCFG_CFGR1_ENCODER_MODE_TIM3)
<> 157:ff67d9f36b67 227 #define LL_SYSCFG_TIM15_ENCODEMODE_TIM3 ((SYSCFG_CFGR1_ENCODER_MODE_TIM3 << 8U) | SYSCFG_CFGR1_ENCODER_MODE_TIM3) /*!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
<> 157:ff67d9f36b67 228 #endif /* SYSCFG_CFGR1_ENCODER_MODE_TIM3 */
<> 157:ff67d9f36b67 229 #if defined(SYSCFG_CFGR1_ENCODER_MODE_TIM4)
<> 157:ff67d9f36b67 230 #define LL_SYSCFG_TIM15_ENCODEMODE_TIM4 ((SYSCFG_CFGR1_ENCODER_MODE_TIM4 << 8U) | SYSCFG_CFGR1_ENCODER_MODE_TIM4) /*!< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
<> 157:ff67d9f36b67 231 #endif /* SYSCFG_CFGR1_ENCODER_MODE_TIM4 */
<> 157:ff67d9f36b67 232 #endif /* SYSCFG_CFGR1_ENCODER_MODE */
<> 157:ff67d9f36b67 233 /**
<> 157:ff67d9f36b67 234 * @}
<> 157:ff67d9f36b67 235 */
<> 157:ff67d9f36b67 236
<> 157:ff67d9f36b67 237 #endif /* SYSCFG_CFGR1_TIM1_ITR3_RMP || SYSCFG_CFGR1_ENCODER_MODE */
<> 157:ff67d9f36b67 238
<> 157:ff67d9f36b67 239 #if defined(SYSCFG_CFGR4_ADC12_EXT2_RMP)
<> 157:ff67d9f36b67 240 /** @defgroup SYSTEM_LL_EC_ADC12_EXT2_RMP_TIM1 SYSCFG ADC Trigger REMAP
<> 157:ff67d9f36b67 241 * @{
<> 157:ff67d9f36b67 242 */
<> 157:ff67d9f36b67 243 #define LL_SYSCFG_ADC12_EXT2_RMP_TIM1_CC3 ((SYSCFG_CFGR4_ADC12_EXT2_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel EXT2:Trigger source is TIM1_CC3 */
<> 157:ff67d9f36b67 244 #define LL_SYSCFG_ADC12_EXT2_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC12_EXT2_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT2_RMP) /*!< Input trigger of ADC12 regular channel EXT2:Trigger source is TIM20_TRGO */
<> 157:ff67d9f36b67 245 #define LL_SYSCFG_ADC12_EXT3_RMP_TIM2_CC2 ((SYSCFG_CFGR4_ADC12_EXT3_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel EXT3:Trigger source is TIM2_CC2 */
<> 157:ff67d9f36b67 246 #define LL_SYSCFG_ADC12_EXT3_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC12_EXT3_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT3_RMP) /*!< Input trigger of ADC12 regular channel EXT3:Trigger source is TIM20_TRGO2 */
<> 157:ff67d9f36b67 247 #define LL_SYSCFG_ADC12_EXT5_RMP_TIM4_CC4 ((SYSCFG_CFGR4_ADC12_EXT5_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel EXT5:Trigger source is TIM4_CC4 */
<> 157:ff67d9f36b67 248 #define LL_SYSCFG_ADC12_EXT5_RMP_TIM20_CC1 ((SYSCFG_CFGR4_ADC12_EXT5_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT5_RMP) /*!< Input trigger of ADC12 regular channel EXT5:Trigger source is TIM20_CC1 */
<> 157:ff67d9f36b67 249 #define LL_SYSCFG_ADC12_EXT13_RMP_TIM6_TRGO ((SYSCFG_CFGR4_ADC12_EXT13_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel EXT13:Trigger source is TIM6_TRGO */
<> 157:ff67d9f36b67 250 #define LL_SYSCFG_ADC12_EXT13_RMP_TIM20_CC2 ((SYSCFG_CFGR4_ADC12_EXT13_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT13_RMP) /*!< Input trigger of ADC12 regular channel EXT13:Trigger source is TIM20_CC2 */
<> 157:ff67d9f36b67 251 #define LL_SYSCFG_ADC12_EXT15_RMP_TIM3_CC4 ((SYSCFG_CFGR4_ADC12_EXT15_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel EXT15:Trigger source is TIM3_CC4 */
<> 157:ff67d9f36b67 252 #define LL_SYSCFG_ADC12_EXT15_RMP_TIM20_CC3 ((SYSCFG_CFGR4_ADC12_EXT15_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT15_RMP) /*!< Input trigger of ADC12 regular channel EXT15:Trigger source is TIM20_CC3 */
<> 157:ff67d9f36b67 253 #define LL_SYSCFG_ADC12_JEXT3_RMP_TIM2_CC1 ((SYSCFG_CFGR4_ADC12_JEXT3_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel JEXT3:Trigger source is TIM2_CC1 */
<> 157:ff67d9f36b67 254 #define LL_SYSCFG_ADC12_JEXT3_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC12_JEXT3_RMP << 16U) | SYSCFG_CFGR4_ADC12_JEXT3_RMP) /*!< Input trigger of ADC12 regular channel JEXT3:Trigger source is TIM20_TRGO */
<> 157:ff67d9f36b67 255 #define LL_SYSCFG_ADC12_JEXT6_RMP_EXTI_LINE_15 ((SYSCFG_CFGR4_ADC12_JEXT6_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel JEXT6:Trigger source is EXTI_LINE_15 */
<> 157:ff67d9f36b67 256 #define LL_SYSCFG_ADC12_JEXT6_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC12_JEXT6_RMP << 16U) | SYSCFG_CFGR4_ADC12_JEXT6_RMP) /*!< Input trigger of ADC12 regular channel JEXT6:Trigger source is TIM20_TRGO2 */
<> 157:ff67d9f36b67 257 #define LL_SYSCFG_ADC12_JEXT13_RMP_TIM3_CC1 ((SYSCFG_CFGR4_ADC12_JEXT13_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel JEXT13:Trigger source is TIM3_CC1 */
<> 157:ff67d9f36b67 258 #define LL_SYSCFG_ADC12_JEXT13_RMP_TIM20_CC4 ((SYSCFG_CFGR4_ADC12_JEXT13_RMP << 16U) | SYSCFG_CFGR4_ADC12_JEXT13_RMP) /*!< Input trigger of ADC12 regular channel JEXT13:Trigger source is TIM20_CC4 */
<> 157:ff67d9f36b67 259 #define LL_SYSCFG_ADC34_EXT5_RMP_EXTI_LINE_2 ((SYSCFG_CFGR4_ADC34_EXT5_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel EXT5:Trigger source is EXTI_LINE_2 */
<> 157:ff67d9f36b67 260 #define LL_SYSCFG_ADC34_EXT5_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC34_EXT5_RMP << 16U) | SYSCFG_CFGR4_ADC34_EXT5_RMP) /*!< Input trigger of ADC34 regular channel EXT5:Trigger source is TIM20_TRGO */
<> 157:ff67d9f36b67 261 #define LL_SYSCFG_ADC34_EXT6_RMP_TIM4_CC1 ((SYSCFG_CFGR4_ADC34_EXT6_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel EXT6:Trigger source is TIM4_CC1 */
<> 157:ff67d9f36b67 262 #define LL_SYSCFG_ADC34_EXT6_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC34_EXT6_RMP << 16U) | SYSCFG_CFGR4_ADC34_EXT6_RMP) /*!< Input trigger of ADC34 regular channel EXT6:Trigger source is TIM20_TRGO2 */
<> 157:ff67d9f36b67 263 #define LL_SYSCFG_ADC34_EXT15_RMP_TIM2_CC1 ((SYSCFG_CFGR4_ADC34_EXT15_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel EXT15:Trigger source is TIM2_CC1 */
<> 157:ff67d9f36b67 264 #define LL_SYSCFG_ADC34_EXT15_RMP_TIM20_CC1 ((SYSCFG_CFGR4_ADC34_EXT15_RMP << 16U) | SYSCFG_CFGR4_ADC34_EXT15_RMP) /*!< Input trigger of ADC34 regular channel EXT15:Trigger source is TIM20_CC1 */
<> 157:ff67d9f36b67 265 #define LL_SYSCFG_ADC34_JEXT5_RMP_TIM4_CC3 ((SYSCFG_CFGR4_ADC34_JEXT5_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel JEXT5:Trigger source is TIM4_CC3 */
<> 157:ff67d9f36b67 266 #define LL_SYSCFG_ADC34_JEXT5_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC34_JEXT5_RMP << 16U) | SYSCFG_CFGR4_ADC34_JEXT5_RMP) /*!< Input trigger of ADC34 regular channel JEXT5:Trigger source is TIM20_TRGO */
<> 157:ff67d9f36b67 267 #define LL_SYSCFG_ADC34_JEXT11_RMP_TIM1_CC3 ((SYSCFG_CFGR4_ADC34_JEXT11_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel JEXT11:Trigger source is TIM1_CC3 */
<> 157:ff67d9f36b67 268 #define LL_SYSCFG_ADC34_JEXT11_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC34_JEXT11_RMP << 16U) | SYSCFG_CFGR4_ADC34_JEXT11_RMP) /*!< Input trigger of ADC34 regular channel JEXT11:Trigger source is TIM20_TRGO2 */
<> 157:ff67d9f36b67 269 #define LL_SYSCFG_ADC34_JEXT14_RMP_TIM7_TRGO ((SYSCFG_CFGR4_ADC34_JEXT14_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel JEXT14:Trigger source is TIM7_TRGO */
<> 157:ff67d9f36b67 270 #define LL_SYSCFG_ADC34_JEXT14_RMP_TIM20_CC2 ((SYSCFG_CFGR4_ADC34_JEXT14_RMP << 16U) | SYSCFG_CFGR4_ADC34_JEXT14_RMP) /*!< Input trigger of ADC34 regular channel JEXT14:Trigger source is TIM20_CC2 */
<> 157:ff67d9f36b67 271 /**
<> 157:ff67d9f36b67 272 * @}
<> 157:ff67d9f36b67 273 */
<> 157:ff67d9f36b67 274
<> 157:ff67d9f36b67 275 #endif /* SYSCFG_CFGR4_ADC12_EXT2_RMP */
<> 157:ff67d9f36b67 276
<> 157:ff67d9f36b67 277 #if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP) || defined(SYSCFG_CFGR3_TRIGGER_RMP)
<> 157:ff67d9f36b67 278 /** @defgroup SYSTEM_LL_EC_DAC1_TRIG1_REMAP SYSCFG DAC1 Trigger REMAP
<> 157:ff67d9f36b67 279 * @{
<> 157:ff67d9f36b67 280 */
<> 157:ff67d9f36b67 281 #if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP)
<> 157:ff67d9f36b67 282 #define LL_SYSCFG_DAC1_TRIG1_RMP_TIM8_TRGO (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_DAC1_TRIG1_RMP << 4 | (uint32_t)0x00000000U) /*!< No remap: DAC trigger TRIG1 is TIM8_TRGO */
<> 157:ff67d9f36b67 283 #define LL_SYSCFG_DAC1_TRIG1_RMP_TIM3_TRGO (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_DAC1_TRIG1_RMP << 4 | SYSCFG_CFGR1_DAC1_TRIG1_RMP) /*!< DAC trigger is TIM3_TRGO */
<> 157:ff67d9f36b67 284 #endif /* SYSCFG_CFGR1_DAC1_TRIG1_RMP */
<> 157:ff67d9f36b67 285 #if defined(SYSCFG_CFGR3_DAC1_TRG3_RMP)
<> 157:ff67d9f36b67 286 #define LL_SYSCFG_DAC1_TRIG3_RMP_TIM15_TRGO (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG3_RMP << 4 | (uint32_t)0x00000000U) /*!< DAC trigger is TIM15_TRGO */
<> 157:ff67d9f36b67 287 #define LL_SYSCFG_DAC1_TRIG3_RMP_HRTIM1_DAC1_TRIG1 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG3_RMP << 4 | SYSCFG_CFGR3_DAC1_TRG3_RMP) /*!< DAC trigger is HRTIM1_DAC1_TRIG1 */
<> 157:ff67d9f36b67 288 #endif /* SYSCFG_CFGR3_DAC1_TRG3_RMP */
<> 157:ff67d9f36b67 289 #if defined(SYSCFG_CFGR3_DAC1_TRG5_RMP)
<> 157:ff67d9f36b67 290 #define LL_SYSCFG_DAC1_TRIG5_RMP_NO (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG5_RMP << 4 | (uint32_t)0x00000000U) /*!< No remap */
<> 157:ff67d9f36b67 291 #define LL_SYSCFG_DAC1_TRIG5_RMP_HRTIM1_DAC1_TRIG2 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG5_RMP << 4 | SYSCFG_CFGR3_DAC1_TRG5_RMP) /*!< DAC trigger is HRTIM1_DAC1_TRIG2 */
<> 157:ff67d9f36b67 292 #endif /* SYSCFG_CFGR3_DAC1_TRG5_RMP */
<> 157:ff67d9f36b67 293 /**
<> 157:ff67d9f36b67 294 * @}
<> 157:ff67d9f36b67 295 */
<> 157:ff67d9f36b67 296
<> 157:ff67d9f36b67 297 #endif /* SYSCFG_CFGR1_DAC1_TRIG1_RMP || SYSCFG_CFGR3_TRIGGER_RMP */
<> 157:ff67d9f36b67 298
<> 157:ff67d9f36b67 299 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
<> 157:ff67d9f36b67 300 * @{
<> 157:ff67d9f36b67 301 */
<> 157:ff67d9f36b67 302 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< I2C PB6 Fast mode plus */
<> 157:ff67d9f36b67 303 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< I2C PB7 Fast mode plus */
<> 157:ff67d9f36b67 304 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< I2C PB8 Fast mode plus */
<> 157:ff67d9f36b67 305 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< I2C PB9 Fast mode plus */
<> 157:ff67d9f36b67 306 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< I2C1 Fast mode plus */
<> 157:ff67d9f36b67 307 #if defined(SYSCFG_CFGR1_I2C2_FMP)
<> 157:ff67d9f36b67 308 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< I2C2 Fast mode plus */
<> 157:ff67d9f36b67 309 #endif /*SYSCFG_CFGR1_I2C2_FMP*/
<> 157:ff67d9f36b67 310 #if defined(SYSCFG_CFGR1_I2C3_FMP)
<> 157:ff67d9f36b67 311 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< I2C3 Fast mode plus */
<> 157:ff67d9f36b67 312 #endif /*SYSCFG_CFGR1_I2C3_FMP*/
<> 157:ff67d9f36b67 313 /**
<> 157:ff67d9f36b67 314 * @}
<> 157:ff67d9f36b67 315 */
<> 157:ff67d9f36b67 316
<> 157:ff67d9f36b67 317 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
<> 157:ff67d9f36b67 318 * @{
<> 157:ff67d9f36b67 319 */
<> 157:ff67d9f36b67 320 #define LL_SYSCFG_EXTI_PORTA (uint32_t)0U /*!< EXTI PORT A */
<> 157:ff67d9f36b67 321 #define LL_SYSCFG_EXTI_PORTB (uint32_t)1U /*!< EXTI PORT B */
<> 157:ff67d9f36b67 322 #define LL_SYSCFG_EXTI_PORTC (uint32_t)2U /*!< EXTI PORT C */
<> 157:ff67d9f36b67 323 #define LL_SYSCFG_EXTI_PORTD (uint32_t)3U /*!< EXTI PORT D */
<> 157:ff67d9f36b67 324 #if defined(GPIOE)
<> 157:ff67d9f36b67 325 #define LL_SYSCFG_EXTI_PORTE (uint32_t)4U /*!< EXTI PORT E */
<> 157:ff67d9f36b67 326 #endif /* GPIOE */
<> 157:ff67d9f36b67 327 #define LL_SYSCFG_EXTI_PORTF (uint32_t)5U /*!< EXTI PORT F */
<> 157:ff67d9f36b67 328 #if defined(GPIOG)
<> 157:ff67d9f36b67 329 #define LL_SYSCFG_EXTI_PORTG (uint32_t)6U /*!< EXTI PORT G */
<> 157:ff67d9f36b67 330 #endif /* GPIOG */
<> 157:ff67d9f36b67 331 #if defined(GPIOH)
<> 157:ff67d9f36b67 332 #define LL_SYSCFG_EXTI_PORTH (uint32_t)7U /*!< EXTI PORT H */
<> 157:ff67d9f36b67 333 #endif /* GPIOH */
<> 157:ff67d9f36b67 334 /**
<> 157:ff67d9f36b67 335 * @}
<> 157:ff67d9f36b67 336 */
<> 157:ff67d9f36b67 337
<> 157:ff67d9f36b67 338 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
<> 157:ff67d9f36b67 339 * @{
<> 157:ff67d9f36b67 340 */
<> 157:ff67d9f36b67 341 #define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16U | 0U) /* EXTI_POSITION_0 | EXTICR[0] */
<> 157:ff67d9f36b67 342 #define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16U | 0U) /* EXTI_POSITION_4 | EXTICR[0] */
<> 157:ff67d9f36b67 343 #define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16U | 0U) /* EXTI_POSITION_8 | EXTICR[0] */
<> 157:ff67d9f36b67 344 #define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16U | 0U) /* EXTI_POSITION_12 | EXTICR[0] */
<> 157:ff67d9f36b67 345 #define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16U | 1U) /* EXTI_POSITION_0 | EXTICR[1] */
<> 157:ff67d9f36b67 346 #define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16U | 1U) /* EXTI_POSITION_4 | EXTICR[1] */
<> 157:ff67d9f36b67 347 #define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16U | 1U) /* EXTI_POSITION_8 | EXTICR[1] */
<> 157:ff67d9f36b67 348 #define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16U | 1U) /* EXTI_POSITION_12 | EXTICR[1] */
<> 157:ff67d9f36b67 349 #define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16U | 2U) /* EXTI_POSITION_0 | EXTICR[2] */
<> 157:ff67d9f36b67 350 #define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16U | 2U) /* EXTI_POSITION_4 | EXTICR[2] */
<> 157:ff67d9f36b67 351 #define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16U | 2U) /* EXTI_POSITION_8 | EXTICR[2] */
<> 157:ff67d9f36b67 352 #define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16U | 2U) /* EXTI_POSITION_12 | EXTICR[2] */
<> 157:ff67d9f36b67 353 #define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16U | 3U) /* EXTI_POSITION_0 | EXTICR[3] */
<> 157:ff67d9f36b67 354 #define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16U | 3U) /* EXTI_POSITION_4 | EXTICR[3] */
<> 157:ff67d9f36b67 355 #define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16U | 3U) /* EXTI_POSITION_8 | EXTICR[3] */
<> 157:ff67d9f36b67 356 #define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16U | 3U) /* EXTI_POSITION_12 | EXTICR[3] */
<> 157:ff67d9f36b67 357 /**
<> 157:ff67d9f36b67 358 * @}
<> 157:ff67d9f36b67 359 */
<> 157:ff67d9f36b67 360
<> 157:ff67d9f36b67 361 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
<> 157:ff67d9f36b67 362 * @{
<> 157:ff67d9f36b67 363 */
<> 157:ff67d9f36b67 364 #if defined(SYSCFG_CFGR2_PVD_LOCK)
<> 157:ff67d9f36b67 365 #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection with TIMx Break Input and also the PVDE and PLS bits of the Power Control Interface */
<> 157:ff67d9f36b67 366 #endif /*SYSCFG_CFGR2_PVD_LOCK*/
<> 157:ff67d9f36b67 367 #if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
<> 157:ff67d9f36b67 368 #define LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
<> 157:ff67d9f36b67 369 #endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
<> 157:ff67d9f36b67 370 #define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMx */
<> 157:ff67d9f36b67 371 /**
<> 157:ff67d9f36b67 372 * @}
<> 157:ff67d9f36b67 373 */
<> 157:ff67d9f36b67 374
<> 157:ff67d9f36b67 375 #if defined(SYSCFG_RCR_PAGE0)
<> 157:ff67d9f36b67 376 /** @defgroup SYSTEM_LL_EC_CCMSRAMWRP SYSCFG CCM SRAM WRP
<> 157:ff67d9f36b67 377 * @{
<> 157:ff67d9f36b67 378 */
<> 157:ff67d9f36b67 379 #define LL_SYSCFG_CCMSRAMWRP_PAGE0 SYSCFG_RCR_PAGE0 /*!< ICODE SRAM Write protection page 0 */
<> 157:ff67d9f36b67 380 #define LL_SYSCFG_CCMSRAMWRP_PAGE1 SYSCFG_RCR_PAGE1 /*!< ICODE SRAM Write protection page 1 */
<> 157:ff67d9f36b67 381 #define LL_SYSCFG_CCMSRAMWRP_PAGE2 SYSCFG_RCR_PAGE2 /*!< ICODE SRAM Write protection page 2 */
<> 157:ff67d9f36b67 382 #define LL_SYSCFG_CCMSRAMWRP_PAGE3 SYSCFG_RCR_PAGE3 /*!< ICODE SRAM Write protection page 3 */
<> 157:ff67d9f36b67 383 #if defined(SYSCFG_RCR_PAGE4)
<> 157:ff67d9f36b67 384 #define LL_SYSCFG_CCMSRAMWRP_PAGE4 SYSCFG_RCR_PAGE4 /*!< ICODE SRAM Write protection page 4 */
<> 157:ff67d9f36b67 385 #define LL_SYSCFG_CCMSRAMWRP_PAGE5 SYSCFG_RCR_PAGE5 /*!< ICODE SRAM Write protection page 5 */
<> 157:ff67d9f36b67 386 #define LL_SYSCFG_CCMSRAMWRP_PAGE6 SYSCFG_RCR_PAGE6 /*!< ICODE SRAM Write protection page 6 */
<> 157:ff67d9f36b67 387 #define LL_SYSCFG_CCMSRAMWRP_PAGE7 SYSCFG_RCR_PAGE7 /*!< ICODE SRAM Write protection page 7 */
<> 157:ff67d9f36b67 388 #endif
<> 157:ff67d9f36b67 389 #if defined(SYSCFG_RCR_PAGE8)
<> 157:ff67d9f36b67 390 #define LL_SYSCFG_CCMSRAMWRP_PAGE8 SYSCFG_RCR_PAGE8 /*!< ICODE SRAM Write protection page 8 */
<> 157:ff67d9f36b67 391 #define LL_SYSCFG_CCMSRAMWRP_PAGE9 SYSCFG_RCR_PAGE9 /*!< ICODE SRAM Write protection page 9 */
<> 157:ff67d9f36b67 392 #define LL_SYSCFG_CCMSRAMWRP_PAGE10 SYSCFG_RCR_PAGE10 /*!< ICODE SRAM Write protection page 10 */
<> 157:ff67d9f36b67 393 #define LL_SYSCFG_CCMSRAMWRP_PAGE11 SYSCFG_RCR_PAGE11 /*!< ICODE SRAM Write protection page 11 */
<> 157:ff67d9f36b67 394 #define LL_SYSCFG_CCMSRAMWRP_PAGE12 SYSCFG_RCR_PAGE12 /*!< ICODE SRAM Write protection page 12 */
<> 157:ff67d9f36b67 395 #define LL_SYSCFG_CCMSRAMWRP_PAGE13 SYSCFG_RCR_PAGE13 /*!< ICODE SRAM Write protection page 13 */
<> 157:ff67d9f36b67 396 #define LL_SYSCFG_CCMSRAMWRP_PAGE14 SYSCFG_RCR_PAGE14 /*!< ICODE SRAM Write protection page 14 */
<> 157:ff67d9f36b67 397 #define LL_SYSCFG_CCMSRAMWRP_PAGE15 SYSCFG_RCR_PAGE15 /*!< ICODE SRAM Write protection page 15 */
<> 157:ff67d9f36b67 398 #endif
<> 157:ff67d9f36b67 399 /**
<> 157:ff67d9f36b67 400 * @}
<> 157:ff67d9f36b67 401 */
<> 157:ff67d9f36b67 402
<> 157:ff67d9f36b67 403 #endif /* SYSCFG_RCR_PAGE0 */
<> 157:ff67d9f36b67 404
<> 157:ff67d9f36b67 405 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
<> 157:ff67d9f36b67 406 * @{
<> 157:ff67d9f36b67 407 */
<> 157:ff67d9f36b67 408 #define LL_DBGMCU_TRACE_NONE (uint32_t)0x00000000U /*!< TRACE pins not assigned (default state) */
<> 157:ff67d9f36b67 409 #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
<> 157:ff67d9f36b67 410 #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
<> 157:ff67d9f36b67 411 #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
<> 157:ff67d9f36b67 412 #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
<> 157:ff67d9f36b67 413 /**
<> 157:ff67d9f36b67 414 * @}
<> 157:ff67d9f36b67 415 */
<> 157:ff67d9f36b67 416
<> 157:ff67d9f36b67 417 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
<> 157:ff67d9f36b67 418 * @{
<> 157:ff67d9f36b67 419 */
<> 157:ff67d9f36b67 420 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
<> 157:ff67d9f36b67 421 #if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
<> 157:ff67d9f36b67 422 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
<> 157:ff67d9f36b67 423 #endif /*DBGMCU_APB1_FZ_DBG_TIM3_STOP*/
<> 157:ff67d9f36b67 424 #if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
<> 157:ff67d9f36b67 425 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */
<> 157:ff67d9f36b67 426 #endif /*DBGMCU_APB1_FZ_DBG_TIM4_STOP*/
<> 157:ff67d9f36b67 427 #if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP)
<> 157:ff67d9f36b67 428 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */
<> 157:ff67d9f36b67 429 #endif /*DBGMCU_APB1_FZ_DBG_TIM5_STOP*/
<> 157:ff67d9f36b67 430 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
<> 157:ff67d9f36b67 431 #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
<> 157:ff67d9f36b67 432 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
<> 157:ff67d9f36b67 433 #endif /*DBGMCU_APB1_FZ_DBG_TIM7_STOP*/
<> 157:ff67d9f36b67 434 #if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
<> 157:ff67d9f36b67 435 #define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */
<> 157:ff67d9f36b67 436 #endif /*DBGMCU_APB1_FZ_DBG_TIM12_STOP*/
<> 157:ff67d9f36b67 437 #if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
<> 157:ff67d9f36b67 438 #define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */
<> 157:ff67d9f36b67 439 #endif /*DBGMCU_APB1_FZ_DBG_TIM13_STOP*/
<> 157:ff67d9f36b67 440 #if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
<> 157:ff67d9f36b67 441 #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */
<> 157:ff67d9f36b67 442 #endif /*DBGMCU_APB1_FZ_DBG_TIM14_STOP*/
<> 157:ff67d9f36b67 443 #if defined(DBGMCU_APB1_FZ_DBG_TIM18_STOP)
<> 157:ff67d9f36b67 444 #define LL_DBGMCU_APB1_GRP1_TIM18_STOP DBGMCU_APB1_FZ_DBG_TIM18_STOP /*!< TIM18 counter stopped when core is halted */
<> 157:ff67d9f36b67 445 #endif /*DBGMCU_APB1_FZ_DBG_TIM18_STOP*/
<> 157:ff67d9f36b67 446 #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC counter stopped when core is halted */
<> 157:ff67d9f36b67 447 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
<> 157:ff67d9f36b67 448 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
<> 157:ff67d9f36b67 449 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
<> 157:ff67d9f36b67 450 #if defined(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
<> 157:ff67d9f36b67 451 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
<> 157:ff67d9f36b67 452 #endif /*DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT*/
<> 157:ff67d9f36b67 453 #if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
<> 157:ff67d9f36b67 454 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
<> 157:ff67d9f36b67 455 #endif /*DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT*/
<> 157:ff67d9f36b67 456 #if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
<> 157:ff67d9f36b67 457 #define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP /*!< CAN debug stopped when Core is halted */
<> 157:ff67d9f36b67 458 #endif /*DBGMCU_APB1_FZ_DBG_CAN_STOP*/
<> 157:ff67d9f36b67 459 /**
<> 157:ff67d9f36b67 460 * @}
<> 157:ff67d9f36b67 461 */
<> 157:ff67d9f36b67 462
<> 157:ff67d9f36b67 463 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
<> 157:ff67d9f36b67 464 * @{
<> 157:ff67d9f36b67 465 */
<> 157:ff67d9f36b67 466 #if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
<> 157:ff67d9f36b67 467 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */
<> 157:ff67d9f36b67 468 #endif /*DBGMCU_APB2_FZ_DBG_TIM1_STOP*/
<> 157:ff67d9f36b67 469 #if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
<> 157:ff67d9f36b67 470 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */
<> 157:ff67d9f36b67 471 #endif /*DBGMCU_APB2_FZ_DBG_TIM8_STOP*/
<> 157:ff67d9f36b67 472 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */
<> 157:ff67d9f36b67 473 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */
<> 157:ff67d9f36b67 474 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */
<> 157:ff67d9f36b67 475 #if defined(DBGMCU_APB2_FZ_DBG_TIM19_STOP)
<> 157:ff67d9f36b67 476 #define LL_DBGMCU_APB2_GRP1_TIM19_STOP DBGMCU_APB2_FZ_DBG_TIM19_STOP /*!< TIM19 counter stopped when core is halted */
<> 157:ff67d9f36b67 477 #endif /*DBGMCU_APB2_FZ_DBG_TIM19_STOP*/
<> 157:ff67d9f36b67 478 #if defined(DBGMCU_APB2_FZ_DBG_TIM20_STOP)
<> 157:ff67d9f36b67 479 #define LL_DBGMCU_APB2_GRP1_TIM20_STOP DBGMCU_APB2_FZ_DBG_TIM20_STOP /*!< TIM20 counter stopped when core is halted */
<> 157:ff67d9f36b67 480 #endif /*DBGMCU_APB2_FZ_DBG_TIM20_STOP*/
<> 157:ff67d9f36b67 481 #if defined(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP)
<> 157:ff67d9f36b67 482 #define LL_DBGMCU_APB2_GRP1_HRTIM1_STOP DBGMCU_APB2_FZ_DBG_HRTIM1_STOP /*!< HRTIM1 counter stopped when core is halted */
<> 157:ff67d9f36b67 483 #endif /*DBGMCU_APB2_FZ_DBG_HRTIM1_STOP*/
<> 157:ff67d9f36b67 484 /**
<> 157:ff67d9f36b67 485 * @}
<> 157:ff67d9f36b67 486 */
<> 157:ff67d9f36b67 487
<> 157:ff67d9f36b67 488 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
<> 157:ff67d9f36b67 489 * @{
<> 157:ff67d9f36b67 490 */
<> 157:ff67d9f36b67 491 #define LL_FLASH_LATENCY_0 ((uint32_t)0x00000000U) /*!< FLASH Zero Latency cycle */
<> 157:ff67d9f36b67 492 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
<> 157:ff67d9f36b67 493 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */
<> 157:ff67d9f36b67 494 /**
<> 157:ff67d9f36b67 495 * @}
<> 157:ff67d9f36b67 496 */
<> 157:ff67d9f36b67 497
<> 157:ff67d9f36b67 498 /**
<> 157:ff67d9f36b67 499 * @}
<> 157:ff67d9f36b67 500 */
<> 157:ff67d9f36b67 501
<> 157:ff67d9f36b67 502 /* Exported macro ------------------------------------------------------------*/
<> 157:ff67d9f36b67 503
<> 157:ff67d9f36b67 504 /* Exported functions --------------------------------------------------------*/
<> 157:ff67d9f36b67 505 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
<> 157:ff67d9f36b67 506 * @{
<> 157:ff67d9f36b67 507 */
<> 157:ff67d9f36b67 508
<> 157:ff67d9f36b67 509 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
<> 157:ff67d9f36b67 510 * @{
<> 157:ff67d9f36b67 511 */
<> 157:ff67d9f36b67 512
<> 157:ff67d9f36b67 513 /**
<> 157:ff67d9f36b67 514 * @brief Set memory mapping at address 0x00000000
<> 157:ff67d9f36b67 515 * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_SetRemapMemory
<> 157:ff67d9f36b67 516 * @param Memory This parameter can be one of the following values:
<> 157:ff67d9f36b67 517 * @arg @ref LL_SYSCFG_REMAP_FLASH
<> 157:ff67d9f36b67 518 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
<> 157:ff67d9f36b67 519 * @arg @ref LL_SYSCFG_REMAP_SRAM
<> 157:ff67d9f36b67 520 * @arg @ref LL_SYSCFG_REMAP_FMC (*)
<> 157:ff67d9f36b67 521 *
<> 157:ff67d9f36b67 522 * (*) value not defined in all devices.
<> 157:ff67d9f36b67 523 * @retval None
<> 157:ff67d9f36b67 524 */
<> 157:ff67d9f36b67 525 __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
<> 157:ff67d9f36b67 526 {
<> 157:ff67d9f36b67 527 MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory);
<> 157:ff67d9f36b67 528 }
<> 157:ff67d9f36b67 529
<> 157:ff67d9f36b67 530 /**
<> 157:ff67d9f36b67 531 * @brief Get memory mapping at address 0x00000000
<> 157:ff67d9f36b67 532 * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory
<> 157:ff67d9f36b67 533 * @retval Returned value can be one of the following values:
<> 157:ff67d9f36b67 534 * @arg @ref LL_SYSCFG_REMAP_FLASH
<> 157:ff67d9f36b67 535 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
<> 157:ff67d9f36b67 536 * @arg @ref LL_SYSCFG_REMAP_SRAM
<> 157:ff67d9f36b67 537 * @arg @ref LL_SYSCFG_REMAP_FMC (*)
<> 157:ff67d9f36b67 538 *
<> 157:ff67d9f36b67 539 * (*) value not defined in all devices.
<> 157:ff67d9f36b67 540 */
<> 157:ff67d9f36b67 541 __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
<> 157:ff67d9f36b67 542 {
<> 157:ff67d9f36b67 543 return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE));
<> 157:ff67d9f36b67 544 }
<> 157:ff67d9f36b67 545
<> 157:ff67d9f36b67 546 #if defined(SYSCFG_CFGR3_SPI1_RX_DMA_RMP)
<> 157:ff67d9f36b67 547 /**
<> 157:ff67d9f36b67 548 * @brief Set DMA request remapping bits for SPI
<> 157:ff67d9f36b67 549 * @rmtoll SYSCFG_CFGR3 SPI1_RX_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI\n
<> 157:ff67d9f36b67 550 * SYSCFG_CFGR3 SPI1_TX_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI
<> 157:ff67d9f36b67 551 * @param Remap This parameter can be one of the following values:
<> 157:ff67d9f36b67 552 * @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH2
<> 157:ff67d9f36b67 553 * @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH4
<> 157:ff67d9f36b67 554 * @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH6
<> 157:ff67d9f36b67 555 * @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH3
<> 157:ff67d9f36b67 556 * @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH5
<> 157:ff67d9f36b67 557 * @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH7
<> 157:ff67d9f36b67 558 * @retval None
<> 157:ff67d9f36b67 559 */
<> 157:ff67d9f36b67 560 __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_SPI(uint32_t Remap)
<> 157:ff67d9f36b67 561 {
<> 157:ff67d9f36b67 562 MODIFY_REG(SYSCFG->CFGR3, (Remap >> 16U), (Remap & 0x0000FFFF));
<> 157:ff67d9f36b67 563 }
<> 157:ff67d9f36b67 564 #endif /* SYSCFG_CFGR3_SPI1_RX_DMA_RMP */
<> 157:ff67d9f36b67 565
<> 157:ff67d9f36b67 566 #if defined(SYSCFG_CFGR3_I2C1_RX_DMA_RMP)
<> 157:ff67d9f36b67 567 /**
<> 157:ff67d9f36b67 568 * @brief Set DMA request remapping bits for I2C
<> 157:ff67d9f36b67 569 * @rmtoll SYSCFG_CFGR3 I2C1_RX_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C\n
<> 157:ff67d9f36b67 570 * SYSCFG_CFGR3 I2C1_TX_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C
<> 157:ff67d9f36b67 571 * @param Remap This parameter can be one of the following values:
<> 157:ff67d9f36b67 572 * @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH7
<> 157:ff67d9f36b67 573 * @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH3
<> 157:ff67d9f36b67 574 * @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH5
<> 157:ff67d9f36b67 575 * @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH6
<> 157:ff67d9f36b67 576 * @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH2
<> 157:ff67d9f36b67 577 * @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH4
<> 157:ff67d9f36b67 578 * @retval None
<> 157:ff67d9f36b67 579 */
<> 157:ff67d9f36b67 580 __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_I2C(uint32_t Remap)
<> 157:ff67d9f36b67 581 {
<> 157:ff67d9f36b67 582 MODIFY_REG(SYSCFG->CFGR3, (Remap >> 16U), (Remap & 0x0000FFFF));
<> 157:ff67d9f36b67 583 }
<> 157:ff67d9f36b67 584 #endif /* SYSCFG_CFGR3_I2C1_RX_DMA_RMP */
<> 157:ff67d9f36b67 585
<> 157:ff67d9f36b67 586 #if defined(SYSCFG_CFGR1_ADC24_DMA_RMP) || defined(SYSCFG_CFGR3_ADC2_DMA_RMP)
<> 157:ff67d9f36b67 587 /**
<> 157:ff67d9f36b67 588 * @brief Set DMA request remapping bits for ADC
<> 157:ff67d9f36b67 589 * @rmtoll SYSCFG_CFGR1 ADC24_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC\n
<> 157:ff67d9f36b67 590 * SYSCFG_CFGR3 ADC2_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC
<> 157:ff67d9f36b67 591 * @param Remap This parameter can be one of the following values:
<> 157:ff67d9f36b67 592 * @arg @ref LL_SYSCFG_ADC24_RMP_DMA2_CH12 (*)
<> 157:ff67d9f36b67 593 * @arg @ref LL_SYSCFG_ADC24_RMP_DMA2_CH34 (*)
<> 157:ff67d9f36b67 594 * @arg @ref LL_SYSCFG_ADC2_RMP_DMA1_CH2 (*)
<> 157:ff67d9f36b67 595 * @arg @ref LL_SYSCFG_ADC2_RMP_DMA1_CH4 (*)
<> 157:ff67d9f36b67 596 * @arg @ref LL_SYSCFG_ADC2_RMP_DMA2 (*)
<> 157:ff67d9f36b67 597 * @arg @ref LL_SYSCFG_ADC2_RMP_DMA1 (*)
<> 157:ff67d9f36b67 598 *
<> 157:ff67d9f36b67 599 * (*) value not defined in all devices.
<> 157:ff67d9f36b67 600 * @retval None
<> 157:ff67d9f36b67 601 */
<> 157:ff67d9f36b67 602 __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_ADC(uint32_t Remap)
<> 157:ff67d9f36b67 603 {
<> 157:ff67d9f36b67 604 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(SYSCFG_BASE + (Remap >> 24U));
<> 157:ff67d9f36b67 605 MODIFY_REG(*reg, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FFFFU));
<> 157:ff67d9f36b67 606 }
<> 157:ff67d9f36b67 607 #endif /* SYSCFG_CFGR1_ADC24_DMA_RMP || SYSCFG_CFGR3_ADC2_DMA_RMP */
<> 157:ff67d9f36b67 608
<> 157:ff67d9f36b67 609 /**
<> 157:ff67d9f36b67 610 * @brief Set DMA request remapping bits for DAC
<> 157:ff67d9f36b67 611 * @rmtoll SYSCFG_CFGR1 TIM6DAC1Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_DAC\n
<> 157:ff67d9f36b67 612 * SYSCFG_CFGR1 DAC2Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_DAC
<> 157:ff67d9f36b67 613 * @param Remap This parameter can be one of the following values:
<> 157:ff67d9f36b67 614 * @arg @ref LL_SYSCFG_DAC1_CH1_RMP_DMA2_CH3
<> 157:ff67d9f36b67 615 * @arg @ref LL_SYSCFG_DAC1_CH1_RMP_DMA1_CH3
<> 157:ff67d9f36b67 616 * @arg @ref LL_SYSCFG_DAC1_OUT2_RMP_DMA2_CH4 (*)
<> 157:ff67d9f36b67 617 * @arg @ref LL_SYSCFG_DAC1_OUT2_RMP_DMA1_CH4 (*)
<> 157:ff67d9f36b67 618 * @arg @ref LL_SYSCFG_DAC2_OUT1_RMP_DMA2_CH5 (*)
<> 157:ff67d9f36b67 619 * @arg @ref LL_SYSCFG_DAC2_OUT1_RMP_DMA1_CH5 (*)
<> 157:ff67d9f36b67 620 * @arg @ref LL_SYSCFG_DAC2_CH1_RMP_NO (*)
<> 157:ff67d9f36b67 621 * @arg @ref LL_SYSCFG_DAC2_CH1_RMP_DMA1_CH5 (*)
<> 157:ff67d9f36b67 622 *
<> 157:ff67d9f36b67 623 * (*) value not defined in all devices.
<> 157:ff67d9f36b67 624 * @retval None
<> 157:ff67d9f36b67 625 */
<> 157:ff67d9f36b67 626 __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_DAC(uint32_t Remap)
<> 157:ff67d9f36b67 627 {
<> 157:ff67d9f36b67 628 MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FF00U));
<> 157:ff67d9f36b67 629 }
<> 157:ff67d9f36b67 630
<> 157:ff67d9f36b67 631 /**
<> 157:ff67d9f36b67 632 * @brief Set DMA request remapping bits for TIM
<> 157:ff67d9f36b67 633 * @rmtoll SYSCFG_CFGR1 TIM16_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
<> 157:ff67d9f36b67 634 * SYSCFG_CFGR1 TIM17_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
<> 157:ff67d9f36b67 635 * SYSCFG_CFGR1 TIM6DAC1Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
<> 157:ff67d9f36b67 636 * SYSCFG_CFGR1 TIM7DAC1Ch2_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
<> 157:ff67d9f36b67 637 * SYSCFG_CFGR1 TIM18DAC2Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM
<> 157:ff67d9f36b67 638 * @param Remap This parameter can be a combination of the following values:
<> 157:ff67d9f36b67 639 * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH3 or @ref LL_SYSCFG_TIM16_RMP_DMA1_CH6
<> 157:ff67d9f36b67 640 * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH1 or @ref LL_SYSCFG_TIM17_RMP_DMA1_CH7
<> 157:ff67d9f36b67 641 * @arg @ref LL_SYSCFG_TIM6_RMP_DMA2_CH3 or @ref LL_SYSCFG_TIM6_RMP_DMA1_CH3
<> 157:ff67d9f36b67 642 * @arg @ref LL_SYSCFG_TIM7_RMP_DMA2_CH4 or @ref LL_SYSCFG_TIM7_RMP_DMA1_CH4 (*)
<> 157:ff67d9f36b67 643 * @arg @ref LL_SYSCFG_TIM18_RMP_DMA2_CH5 or @ref LL_SYSCFG_TIM18_RMP_DMA1_CH5 (*)
<> 157:ff67d9f36b67 644 *
<> 157:ff67d9f36b67 645 * (*) value not defined in all devices.
<> 157:ff67d9f36b67 646 * @retval None
<> 157:ff67d9f36b67 647 */
<> 157:ff67d9f36b67 648 __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_TIM(uint32_t Remap)
<> 157:ff67d9f36b67 649 {
<> 157:ff67d9f36b67 650 MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FF00U));
<> 157:ff67d9f36b67 651 }
<> 157:ff67d9f36b67 652
<> 157:ff67d9f36b67 653 #if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP) || defined(SYSCFG_CFGR1_ENCODER_MODE)
<> 157:ff67d9f36b67 654 /**
<> 157:ff67d9f36b67 655 * @brief Set Timer input remap
<> 157:ff67d9f36b67 656 * @rmtoll SYSCFG_CFGR1 TIM1_ITR3_RMP LL_SYSCFG_SetRemapInput_TIM\n
<> 157:ff67d9f36b67 657 * SYSCFG_CFGR1 ENCODER_MODE LL_SYSCFG_SetRemapInput_TIM
<> 157:ff67d9f36b67 658 * @param Remap This parameter can be one of the following values:
<> 157:ff67d9f36b67 659 * @arg @ref LL_SYSCFG_TIM1_ITR3_RMP_TIM4_TRGO (*)
<> 157:ff67d9f36b67 660 * @arg @ref LL_SYSCFG_TIM1_ITR3_RMP_TIM17_OC (*)
<> 157:ff67d9f36b67 661 * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_NOREDIRECTION (*)
<> 157:ff67d9f36b67 662 * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM2 (*)
<> 157:ff67d9f36b67 663 * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM3 (*)
<> 157:ff67d9f36b67 664 * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM4 (*)
<> 157:ff67d9f36b67 665 *
<> 157:ff67d9f36b67 666 * (*) value not defined in all devices.
<> 157:ff67d9f36b67 667 * @retval None
<> 157:ff67d9f36b67 668 */
<> 157:ff67d9f36b67 669 __STATIC_INLINE void LL_SYSCFG_SetRemapInput_TIM(uint32_t Remap)
<> 157:ff67d9f36b67 670 {
<> 157:ff67d9f36b67 671 MODIFY_REG(SYSCFG->CFGR1, (Remap & 0xFF00FF00U) >> 8U, (Remap & 0x00FF00FFU));
<> 157:ff67d9f36b67 672 }
<> 157:ff67d9f36b67 673 #endif /* SYSCFG_CFGR1_TIM1_ITR3_RMP || SYSCFG_CFGR1_ENCODER_MODE */
<> 157:ff67d9f36b67 674
<> 157:ff67d9f36b67 675 #if defined(SYSCFG_CFGR4_ADC12_EXT2_RMP)
<> 157:ff67d9f36b67 676 /**
<> 157:ff67d9f36b67 677 * @brief Set ADC Trigger remap
<> 157:ff67d9f36b67 678 * @rmtoll SYSCFG_CFGR4 ADC12_EXT2_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
<> 157:ff67d9f36b67 679 * SYSCFG_CFGR4 ADC12_EXT3_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
<> 157:ff67d9f36b67 680 * SYSCFG_CFGR4 ADC12_EXT5_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
<> 157:ff67d9f36b67 681 * SYSCFG_CFGR4 ADC12_EXT13_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
<> 157:ff67d9f36b67 682 * SYSCFG_CFGR4 ADC12_EXT15_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
<> 157:ff67d9f36b67 683 * SYSCFG_CFGR4 ADC12_JEXT3_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
<> 157:ff67d9f36b67 684 * SYSCFG_CFGR4 ADC12_JEXT6_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
<> 157:ff67d9f36b67 685 * SYSCFG_CFGR4 ADC12_JEXT13_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
<> 157:ff67d9f36b67 686 * SYSCFG_CFGR4 ADC34_EXT5_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
<> 157:ff67d9f36b67 687 * SYSCFG_CFGR4 ADC34_EXT6_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
<> 157:ff67d9f36b67 688 * SYSCFG_CFGR4 ADC34_EXT15_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
<> 157:ff67d9f36b67 689 * SYSCFG_CFGR4 ADC34_JEXT5_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
<> 157:ff67d9f36b67 690 * SYSCFG_CFGR4 ADC34_JEXT11_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
<> 157:ff67d9f36b67 691 * SYSCFG_CFGR4 ADC34_JEXT14_RMP LL_SYSCFG_SetRemapTrigger_ADC
<> 157:ff67d9f36b67 692 * @param Remap This parameter can be one of the following values:
<> 157:ff67d9f36b67 693 * @arg @ref LL_SYSCFG_ADC12_EXT2_RMP_TIM1_CC3
<> 157:ff67d9f36b67 694 * @arg @ref LL_SYSCFG_ADC12_EXT2_RMP_TIM20_TRGO
<> 157:ff67d9f36b67 695 * @arg @ref LL_SYSCFG_ADC12_EXT3_RMP_TIM2_CC2
<> 157:ff67d9f36b67 696 * @arg @ref LL_SYSCFG_ADC12_EXT3_RMP_TIM20_TRGO2
<> 157:ff67d9f36b67 697 * @arg @ref LL_SYSCFG_ADC12_EXT5_RMP_TIM4_CC4
<> 157:ff67d9f36b67 698 * @arg @ref LL_SYSCFG_ADC12_EXT5_RMP_TIM20_CC1
<> 157:ff67d9f36b67 699 * @arg @ref LL_SYSCFG_ADC12_EXT13_RMP_TIM6_TRGO
<> 157:ff67d9f36b67 700 * @arg @ref LL_SYSCFG_ADC12_EXT13_RMP_TIM20_CC2
<> 157:ff67d9f36b67 701 * @arg @ref LL_SYSCFG_ADC12_EXT15_RMP_TIM3_CC4
<> 157:ff67d9f36b67 702 * @arg @ref LL_SYSCFG_ADC12_EXT15_RMP_TIM20_CC3
<> 157:ff67d9f36b67 703 * @arg @ref LL_SYSCFG_ADC12_JEXT3_RMP_TIM2_CC1
<> 157:ff67d9f36b67 704 * @arg @ref LL_SYSCFG_ADC12_JEXT3_RMP_TIM20_TRGO
<> 157:ff67d9f36b67 705 * @arg @ref LL_SYSCFG_ADC12_JEXT6_RMP_EXTI_LINE_15
<> 157:ff67d9f36b67 706 * @arg @ref LL_SYSCFG_ADC12_JEXT6_RMP_TIM20_TRGO2
<> 157:ff67d9f36b67 707 * @arg @ref LL_SYSCFG_ADC12_JEXT13_RMP_TIM3_CC1
<> 157:ff67d9f36b67 708 * @arg @ref LL_SYSCFG_ADC12_JEXT13_RMP_TIM20_CC4
<> 157:ff67d9f36b67 709 * @arg @ref LL_SYSCFG_ADC34_EXT5_RMP_EXTI_LINE_2
<> 157:ff67d9f36b67 710 * @arg @ref LL_SYSCFG_ADC34_EXT5_RMP_TIM20_TRGO
<> 157:ff67d9f36b67 711 * @arg @ref LL_SYSCFG_ADC34_EXT6_RMP_TIM4_CC1
<> 157:ff67d9f36b67 712 * @arg @ref LL_SYSCFG_ADC34_EXT6_RMP_TIM20_TRGO2
<> 157:ff67d9f36b67 713 * @arg @ref LL_SYSCFG_ADC34_EXT15_RMP_TIM2_CC1
<> 157:ff67d9f36b67 714 * @arg @ref LL_SYSCFG_ADC34_EXT15_RMP_TIM20_CC1
<> 157:ff67d9f36b67 715 * @arg @ref LL_SYSCFG_ADC34_JEXT5_RMP_TIM4_CC3
<> 157:ff67d9f36b67 716 * @arg @ref LL_SYSCFG_ADC34_JEXT5_RMP_TIM20_TRGO
<> 157:ff67d9f36b67 717 * @arg @ref LL_SYSCFG_ADC34_JEXT11_RMP_TIM1_CC3
<> 157:ff67d9f36b67 718 * @arg @ref LL_SYSCFG_ADC34_JEXT11_RMP_TIM20_TRGO2
<> 157:ff67d9f36b67 719 * @arg @ref LL_SYSCFG_ADC34_JEXT14_RMP_TIM7_TRGO
<> 157:ff67d9f36b67 720 * @arg @ref LL_SYSCFG_ADC34_JEXT14_RMP_TIM20_CC2
<> 157:ff67d9f36b67 721 * @retval None
<> 157:ff67d9f36b67 722 */
<> 157:ff67d9f36b67 723 __STATIC_INLINE void LL_SYSCFG_SetRemapTrigger_ADC(uint32_t Remap)
<> 157:ff67d9f36b67 724 {
<> 157:ff67d9f36b67 725 MODIFY_REG(SYSCFG->CFGR4, (Remap & 0xFFFF0000U) >> 16U, (Remap & 0x0000FFFFU));
<> 157:ff67d9f36b67 726 }
<> 157:ff67d9f36b67 727 #endif /* SYSCFG_CFGR4_ADC12_EXT2_RMP */
<> 157:ff67d9f36b67 728
<> 157:ff67d9f36b67 729 #if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP) || defined(SYSCFG_CFGR3_TRIGGER_RMP)
<> 157:ff67d9f36b67 730 /**
<> 157:ff67d9f36b67 731 * @brief Set DAC Trigger remap
<> 157:ff67d9f36b67 732 * @rmtoll SYSCFG_CFGR1 DAC1_TRIG1_RMP LL_SYSCFG_SetRemapTrigger_DAC\n
<> 157:ff67d9f36b67 733 * SYSCFG_CFGR3 DAC1_TRG3_RMP LL_SYSCFG_SetRemapTrigger_DAC\n
<> 157:ff67d9f36b67 734 * SYSCFG_CFGR3 DAC1_TRG5_RMP LL_SYSCFG_SetRemapTrigger_DAC
<> 157:ff67d9f36b67 735 * @param Remap This parameter can be one of the following values:
<> 157:ff67d9f36b67 736 * @arg @ref LL_SYSCFG_DAC1_TRIG1_RMP_TIM8_TRGO (*)
<> 157:ff67d9f36b67 737 * @arg @ref LL_SYSCFG_DAC1_TRIG1_RMP_TIM3_TRGO (*)
<> 157:ff67d9f36b67 738 * @arg @ref LL_SYSCFG_DAC1_TRIG3_RMP_TIM15_TRGO (*)
<> 157:ff67d9f36b67 739 * @arg @ref LL_SYSCFG_DAC1_TRIG3_RMP_HRTIM1_DAC1_TRIG1 (*)
<> 157:ff67d9f36b67 740 * @arg @ref LL_SYSCFG_DAC1_TRIG5_RMP_NO (*)
<> 157:ff67d9f36b67 741 * @arg @ref LL_SYSCFG_DAC1_TRIG5_RMP_HRTIM1_DAC1_TRIG2 (*)
<> 157:ff67d9f36b67 742 * (*) value not defined in all devices.
<> 157:ff67d9f36b67 743 * @retval None
<> 157:ff67d9f36b67 744 */
<> 157:ff67d9f36b67 745 __STATIC_INLINE void LL_SYSCFG_SetRemapTrigger_DAC(uint32_t Remap)
<> 157:ff67d9f36b67 746 {
<> 157:ff67d9f36b67 747 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(SYSCFG_BASE + (Remap >> 24U));
<> 157:ff67d9f36b67 748 MODIFY_REG(*reg, (Remap & 0x00F00F00U) >> 4U, (Remap & 0x000F00F0U));
<> 157:ff67d9f36b67 749 }
<> 157:ff67d9f36b67 750 #endif /* SYSCFG_CFGR1_DAC1_TRIG1_RMP || SYSCFG_CFGR3_TRIGGER_RMP */
<> 157:ff67d9f36b67 751
<> 157:ff67d9f36b67 752 #if defined(SYSCFG_CFGR1_USB_IT_RMP)
<> 157:ff67d9f36b67 753 /**
<> 157:ff67d9f36b67 754 * @brief Enable USB interrupt remap
<> 157:ff67d9f36b67 755 * @note Remap the USB interrupts (USB_HP, USB_LP and USB_WKUP) on interrupt lines 74, 75 and 76
<> 157:ff67d9f36b67 756 * respectively
<> 157:ff67d9f36b67 757 * @rmtoll SYSCFG_CFGR1 USB_IT_RMP LL_SYSCFG_EnableRemapIT_USB
<> 157:ff67d9f36b67 758 * @retval None
<> 157:ff67d9f36b67 759 */
<> 157:ff67d9f36b67 760 __STATIC_INLINE void LL_SYSCFG_EnableRemapIT_USB(void)
<> 157:ff67d9f36b67 761 {
<> 157:ff67d9f36b67 762 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_USB_IT_RMP);
<> 157:ff67d9f36b67 763 }
<> 157:ff67d9f36b67 764
<> 157:ff67d9f36b67 765 /**
<> 157:ff67d9f36b67 766 * @brief Disable USB interrupt remap
<> 157:ff67d9f36b67 767 * @rmtoll SYSCFG_CFGR1 USB_IT_RMP LL_SYSCFG_DisableRemapIT_USB
<> 157:ff67d9f36b67 768 * @retval None
<> 157:ff67d9f36b67 769 */
<> 157:ff67d9f36b67 770 __STATIC_INLINE void LL_SYSCFG_DisableRemapIT_USB(void)
<> 157:ff67d9f36b67 771 {
<> 157:ff67d9f36b67 772 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_USB_IT_RMP);
<> 157:ff67d9f36b67 773 }
<> 157:ff67d9f36b67 774 #endif /* SYSCFG_CFGR1_USB_IT_RMP */
<> 157:ff67d9f36b67 775
<> 157:ff67d9f36b67 776 #if defined(SYSCFG_CFGR1_VBAT)
<> 157:ff67d9f36b67 777 /**
<> 157:ff67d9f36b67 778 * @brief Enable VBAT monitoring (to enable the power switch to deliver VBAT voltage on ADC channel 18 input)
<> 157:ff67d9f36b67 779 * @rmtoll SYSCFG_CFGR1 VBAT LL_SYSCFG_EnableVBATMonitoring
<> 157:ff67d9f36b67 780 * @retval None
<> 157:ff67d9f36b67 781 */
<> 157:ff67d9f36b67 782 __STATIC_INLINE void LL_SYSCFG_EnableVBATMonitoring(void)
<> 157:ff67d9f36b67 783 {
<> 157:ff67d9f36b67 784 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT);
<> 157:ff67d9f36b67 785 }
<> 157:ff67d9f36b67 786
<> 157:ff67d9f36b67 787 /**
<> 157:ff67d9f36b67 788 * @brief Disable VBAT monitoring
<> 157:ff67d9f36b67 789 * @rmtoll SYSCFG_CFGR1 VBAT LL_SYSCFG_DisableVBATMonitoring
<> 157:ff67d9f36b67 790 * @retval None
<> 157:ff67d9f36b67 791 */
<> 157:ff67d9f36b67 792 __STATIC_INLINE void LL_SYSCFG_DisableVBATMonitoring(void)
<> 157:ff67d9f36b67 793 {
<> 157:ff67d9f36b67 794 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT);
<> 157:ff67d9f36b67 795 }
<> 157:ff67d9f36b67 796 #endif /* SYSCFG_CFGR1_VBAT */
<> 157:ff67d9f36b67 797
<> 157:ff67d9f36b67 798 /**
<> 157:ff67d9f36b67 799 * @brief Enable the I2C fast mode plus driving capability.
<> 157:ff67d9f36b67 800 * @rmtoll SYSCFG_CFGR1 I2C_PB6_FMP LL_SYSCFG_EnableFastModePlus\n
<> 157:ff67d9f36b67 801 * SYSCFG_CFGR1 I2C_PB7_FMP LL_SYSCFG_EnableFastModePlus\n
<> 157:ff67d9f36b67 802 * SYSCFG_CFGR1 I2C_PB8_FMP LL_SYSCFG_EnableFastModePlus\n
<> 157:ff67d9f36b67 803 * SYSCFG_CFGR1 I2C_PB9_FMP LL_SYSCFG_EnableFastModePlus\n
<> 157:ff67d9f36b67 804 * SYSCFG_CFGR1 I2C1_FMP LL_SYSCFG_EnableFastModePlus\n
<> 157:ff67d9f36b67 805 * SYSCFG_CFGR1 I2C2_FMP LL_SYSCFG_EnableFastModePlus\n
<> 157:ff67d9f36b67 806 * SYSCFG_CFGR1 I2C3_FMP LL_SYSCFG_EnableFastModePlus
<> 157:ff67d9f36b67 807 * @param ConfigFastModePlus This parameter can be a combination of the following values:
<> 157:ff67d9f36b67 808 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
<> 157:ff67d9f36b67 809 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
<> 157:ff67d9f36b67 810 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
<> 157:ff67d9f36b67 811 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
<> 157:ff67d9f36b67 812 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
<> 157:ff67d9f36b67 813 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
<> 157:ff67d9f36b67 814 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
<> 157:ff67d9f36b67 815 *
<> 157:ff67d9f36b67 816 * (*) value not defined in all devices.
<> 157:ff67d9f36b67 817 * @retval None
<> 157:ff67d9f36b67 818 */
<> 157:ff67d9f36b67 819 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
<> 157:ff67d9f36b67 820 {
<> 157:ff67d9f36b67 821 SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
<> 157:ff67d9f36b67 822 }
<> 157:ff67d9f36b67 823
<> 157:ff67d9f36b67 824 /**
<> 157:ff67d9f36b67 825 * @brief Disable the I2C fast mode plus driving capability.
<> 157:ff67d9f36b67 826 * @rmtoll SYSCFG_CFGR1 I2C_PB6_FMP LL_SYSCFG_DisableFastModePlus\n
<> 157:ff67d9f36b67 827 * SYSCFG_CFGR1 I2C_PB7_FMP LL_SYSCFG_DisableFastModePlus\n
<> 157:ff67d9f36b67 828 * SYSCFG_CFGR1 I2C_PB8_FMP LL_SYSCFG_DisableFastModePlus\n
<> 157:ff67d9f36b67 829 * SYSCFG_CFGR1 I2C_PB9_FMP LL_SYSCFG_DisableFastModePlus\n
<> 157:ff67d9f36b67 830 * SYSCFG_CFGR1 I2C1_FMP LL_SYSCFG_DisableFastModePlus\n
<> 157:ff67d9f36b67 831 * SYSCFG_CFGR1 I2C2_FMP LL_SYSCFG_DisableFastModePlus\n
<> 157:ff67d9f36b67 832 * SYSCFG_CFGR1 I2C3_FMP LL_SYSCFG_DisableFastModePlus
<> 157:ff67d9f36b67 833 * @param ConfigFastModePlus This parameter can be a combination of the following values:
<> 157:ff67d9f36b67 834 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
<> 157:ff67d9f36b67 835 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
<> 157:ff67d9f36b67 836 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
<> 157:ff67d9f36b67 837 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
<> 157:ff67d9f36b67 838 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
<> 157:ff67d9f36b67 839 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
<> 157:ff67d9f36b67 840 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
<> 157:ff67d9f36b67 841 *
<> 157:ff67d9f36b67 842 * (*) value not defined in all devices.
<> 157:ff67d9f36b67 843 * @retval None
<> 157:ff67d9f36b67 844 */
<> 157:ff67d9f36b67 845 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
<> 157:ff67d9f36b67 846 {
<> 157:ff67d9f36b67 847 CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
<> 157:ff67d9f36b67 848 }
<> 157:ff67d9f36b67 849
<> 157:ff67d9f36b67 850 /**
<> 157:ff67d9f36b67 851 * @brief Enable Floating Point Unit Invalid operation Interrupt
<> 157:ff67d9f36b67 852 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
<> 157:ff67d9f36b67 853 * @retval None
<> 157:ff67d9f36b67 854 */
<> 157:ff67d9f36b67 855 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
<> 157:ff67d9f36b67 856 {
<> 157:ff67d9f36b67 857 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
<> 157:ff67d9f36b67 858 }
<> 157:ff67d9f36b67 859
<> 157:ff67d9f36b67 860 /**
<> 157:ff67d9f36b67 861 * @brief Enable Floating Point Unit Divide-by-zero Interrupt
<> 157:ff67d9f36b67 862 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
<> 157:ff67d9f36b67 863 * @retval None
<> 157:ff67d9f36b67 864 */
<> 157:ff67d9f36b67 865 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
<> 157:ff67d9f36b67 866 {
<> 157:ff67d9f36b67 867 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
<> 157:ff67d9f36b67 868 }
<> 157:ff67d9f36b67 869
<> 157:ff67d9f36b67 870 /**
<> 157:ff67d9f36b67 871 * @brief Enable Floating Point Unit Underflow Interrupt
<> 157:ff67d9f36b67 872 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
<> 157:ff67d9f36b67 873 * @retval None
<> 157:ff67d9f36b67 874 */
<> 157:ff67d9f36b67 875 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
<> 157:ff67d9f36b67 876 {
<> 157:ff67d9f36b67 877 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
<> 157:ff67d9f36b67 878 }
<> 157:ff67d9f36b67 879
<> 157:ff67d9f36b67 880 /**
<> 157:ff67d9f36b67 881 * @brief Enable Floating Point Unit Overflow Interrupt
<> 157:ff67d9f36b67 882 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
<> 157:ff67d9f36b67 883 * @retval None
<> 157:ff67d9f36b67 884 */
<> 157:ff67d9f36b67 885 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
<> 157:ff67d9f36b67 886 {
<> 157:ff67d9f36b67 887 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
<> 157:ff67d9f36b67 888 }
<> 157:ff67d9f36b67 889
<> 157:ff67d9f36b67 890 /**
<> 157:ff67d9f36b67 891 * @brief Enable Floating Point Unit Input denormal Interrupt
<> 157:ff67d9f36b67 892 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
<> 157:ff67d9f36b67 893 * @retval None
<> 157:ff67d9f36b67 894 */
<> 157:ff67d9f36b67 895 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
<> 157:ff67d9f36b67 896 {
<> 157:ff67d9f36b67 897 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
<> 157:ff67d9f36b67 898 }
<> 157:ff67d9f36b67 899
<> 157:ff67d9f36b67 900 /**
<> 157:ff67d9f36b67 901 * @brief Enable Floating Point Unit Inexact Interrupt
<> 157:ff67d9f36b67 902 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
<> 157:ff67d9f36b67 903 * @retval None
<> 157:ff67d9f36b67 904 */
<> 157:ff67d9f36b67 905 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
<> 157:ff67d9f36b67 906 {
<> 157:ff67d9f36b67 907 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
<> 157:ff67d9f36b67 908 }
<> 157:ff67d9f36b67 909
<> 157:ff67d9f36b67 910 /**
<> 157:ff67d9f36b67 911 * @brief Disable Floating Point Unit Invalid operation Interrupt
<> 157:ff67d9f36b67 912 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
<> 157:ff67d9f36b67 913 * @retval None
<> 157:ff67d9f36b67 914 */
<> 157:ff67d9f36b67 915 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
<> 157:ff67d9f36b67 916 {
<> 157:ff67d9f36b67 917 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
<> 157:ff67d9f36b67 918 }
<> 157:ff67d9f36b67 919
<> 157:ff67d9f36b67 920 /**
<> 157:ff67d9f36b67 921 * @brief Disable Floating Point Unit Divide-by-zero Interrupt
<> 157:ff67d9f36b67 922 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
<> 157:ff67d9f36b67 923 * @retval None
<> 157:ff67d9f36b67 924 */
<> 157:ff67d9f36b67 925 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
<> 157:ff67d9f36b67 926 {
<> 157:ff67d9f36b67 927 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
<> 157:ff67d9f36b67 928 }
<> 157:ff67d9f36b67 929
<> 157:ff67d9f36b67 930 /**
<> 157:ff67d9f36b67 931 * @brief Disable Floating Point Unit Underflow Interrupt
<> 157:ff67d9f36b67 932 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
<> 157:ff67d9f36b67 933 * @retval None
<> 157:ff67d9f36b67 934 */
<> 157:ff67d9f36b67 935 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
<> 157:ff67d9f36b67 936 {
<> 157:ff67d9f36b67 937 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
<> 157:ff67d9f36b67 938 }
<> 157:ff67d9f36b67 939
<> 157:ff67d9f36b67 940 /**
<> 157:ff67d9f36b67 941 * @brief Disable Floating Point Unit Overflow Interrupt
<> 157:ff67d9f36b67 942 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
<> 157:ff67d9f36b67 943 * @retval None
<> 157:ff67d9f36b67 944 */
<> 157:ff67d9f36b67 945 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
<> 157:ff67d9f36b67 946 {
<> 157:ff67d9f36b67 947 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
<> 157:ff67d9f36b67 948 }
<> 157:ff67d9f36b67 949
<> 157:ff67d9f36b67 950 /**
<> 157:ff67d9f36b67 951 * @brief Disable Floating Point Unit Input denormal Interrupt
<> 157:ff67d9f36b67 952 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
<> 157:ff67d9f36b67 953 * @retval None
<> 157:ff67d9f36b67 954 */
<> 157:ff67d9f36b67 955 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
<> 157:ff67d9f36b67 956 {
<> 157:ff67d9f36b67 957 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
<> 157:ff67d9f36b67 958 }
<> 157:ff67d9f36b67 959
<> 157:ff67d9f36b67 960 /**
<> 157:ff67d9f36b67 961 * @brief Disable Floating Point Unit Inexact Interrupt
<> 157:ff67d9f36b67 962 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
<> 157:ff67d9f36b67 963 * @retval None
<> 157:ff67d9f36b67 964 */
<> 157:ff67d9f36b67 965 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
<> 157:ff67d9f36b67 966 {
<> 157:ff67d9f36b67 967 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
<> 157:ff67d9f36b67 968 }
<> 157:ff67d9f36b67 969
<> 157:ff67d9f36b67 970 /**
<> 157:ff67d9f36b67 971 * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
<> 157:ff67d9f36b67 972 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
<> 157:ff67d9f36b67 973 * @retval State of bit (1 or 0).
<> 157:ff67d9f36b67 974 */
<> 157:ff67d9f36b67 975 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
<> 157:ff67d9f36b67 976 {
<> 157:ff67d9f36b67 977 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0));
<> 157:ff67d9f36b67 978 }
<> 157:ff67d9f36b67 979
<> 157:ff67d9f36b67 980 /**
<> 157:ff67d9f36b67 981 * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
<> 157:ff67d9f36b67 982 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
<> 157:ff67d9f36b67 983 * @retval State of bit (1 or 0).
<> 157:ff67d9f36b67 984 */
<> 157:ff67d9f36b67 985 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
<> 157:ff67d9f36b67 986 {
<> 157:ff67d9f36b67 987 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1));
<> 157:ff67d9f36b67 988 }
<> 157:ff67d9f36b67 989
<> 157:ff67d9f36b67 990 /**
<> 157:ff67d9f36b67 991 * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
<> 157:ff67d9f36b67 992 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
<> 157:ff67d9f36b67 993 * @retval State of bit (1 or 0).
<> 157:ff67d9f36b67 994 */
<> 157:ff67d9f36b67 995 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
<> 157:ff67d9f36b67 996 {
<> 157:ff67d9f36b67 997 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2));
<> 157:ff67d9f36b67 998 }
<> 157:ff67d9f36b67 999
<> 157:ff67d9f36b67 1000 /**
<> 157:ff67d9f36b67 1001 * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
<> 157:ff67d9f36b67 1002 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
<> 157:ff67d9f36b67 1003 * @retval State of bit (1 or 0).
<> 157:ff67d9f36b67 1004 */
<> 157:ff67d9f36b67 1005 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
<> 157:ff67d9f36b67 1006 {
<> 157:ff67d9f36b67 1007 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3));
<> 157:ff67d9f36b67 1008 }
<> 157:ff67d9f36b67 1009
<> 157:ff67d9f36b67 1010 /**
<> 157:ff67d9f36b67 1011 * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
<> 157:ff67d9f36b67 1012 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
<> 157:ff67d9f36b67 1013 * @retval State of bit (1 or 0).
<> 157:ff67d9f36b67 1014 */
<> 157:ff67d9f36b67 1015 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
<> 157:ff67d9f36b67 1016 {
<> 157:ff67d9f36b67 1017 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4));
<> 157:ff67d9f36b67 1018 }
<> 157:ff67d9f36b67 1019
<> 157:ff67d9f36b67 1020 /**
<> 157:ff67d9f36b67 1021 * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
<> 157:ff67d9f36b67 1022 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
<> 157:ff67d9f36b67 1023 * @retval State of bit (1 or 0).
<> 157:ff67d9f36b67 1024 */
<> 157:ff67d9f36b67 1025 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
<> 157:ff67d9f36b67 1026 {
<> 157:ff67d9f36b67 1027 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5));
<> 157:ff67d9f36b67 1028 }
<> 157:ff67d9f36b67 1029
<> 157:ff67d9f36b67 1030 /**
<> 157:ff67d9f36b67 1031 * @brief Configure source input for the EXTI external interrupt.
<> 157:ff67d9f36b67 1032 * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1033 * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1034 * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1035 * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1036 * SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1037 * SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1038 * SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1039 * SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1040 * SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1041 * SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1042 * SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1043 * SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1044 * SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1045 * SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1046 * SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1047 * SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1048 * SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1049 * SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1050 * SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1051 * SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1052 * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1053 * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1054 * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1055 * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1056 * SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1057 * SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1058 * SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1059 * SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1060 * SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1061 * SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1062 * SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1063 * SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1064 * SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1065 * SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1066 * SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1067 * SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1068 * SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1069 * SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1070 * SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1071 * SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1072 * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1073 * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1074 * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1075 * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1076 * SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1077 * SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1078 * SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1079 * SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1080 * SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1081 * SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1082 * SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1083 * SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1084 * SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1085 * SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1086 * SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1087 * SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1088 * SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1089 * SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1090 * SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1091 * SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1092 * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1093 * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1094 * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n
<> 157:ff67d9f36b67 1095 * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource
<> 157:ff67d9f36b67 1096 * @param Port This parameter can be one of the following values:
<> 157:ff67d9f36b67 1097 * @arg @ref LL_SYSCFG_EXTI_PORTA
<> 157:ff67d9f36b67 1098 * @arg @ref LL_SYSCFG_EXTI_PORTB
<> 157:ff67d9f36b67 1099 * @arg @ref LL_SYSCFG_EXTI_PORTC
<> 157:ff67d9f36b67 1100 * @arg @ref LL_SYSCFG_EXTI_PORTD
<> 157:ff67d9f36b67 1101 * @arg @ref LL_SYSCFG_EXTI_PORTE (*)
<> 157:ff67d9f36b67 1102 * @arg @ref LL_SYSCFG_EXTI_PORTF
<> 157:ff67d9f36b67 1103 * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
<> 157:ff67d9f36b67 1104 * @arg @ref LL_SYSCFG_EXTI_PORTH (*)
<> 157:ff67d9f36b67 1105 *
<> 157:ff67d9f36b67 1106 * (*) value not defined in all devices.
<> 157:ff67d9f36b67 1107 * @param Line This parameter can be one of the following values:
<> 157:ff67d9f36b67 1108 * @arg @ref LL_SYSCFG_EXTI_LINE0
<> 157:ff67d9f36b67 1109 * @arg @ref LL_SYSCFG_EXTI_LINE1
<> 157:ff67d9f36b67 1110 * @arg @ref LL_SYSCFG_EXTI_LINE2
<> 157:ff67d9f36b67 1111 * @arg @ref LL_SYSCFG_EXTI_LINE3
<> 157:ff67d9f36b67 1112 * @arg @ref LL_SYSCFG_EXTI_LINE4
<> 157:ff67d9f36b67 1113 * @arg @ref LL_SYSCFG_EXTI_LINE5
<> 157:ff67d9f36b67 1114 * @arg @ref LL_SYSCFG_EXTI_LINE6
<> 157:ff67d9f36b67 1115 * @arg @ref LL_SYSCFG_EXTI_LINE7
<> 157:ff67d9f36b67 1116 * @arg @ref LL_SYSCFG_EXTI_LINE8
<> 157:ff67d9f36b67 1117 * @arg @ref LL_SYSCFG_EXTI_LINE9
<> 157:ff67d9f36b67 1118 * @arg @ref LL_SYSCFG_EXTI_LINE10
<> 157:ff67d9f36b67 1119 * @arg @ref LL_SYSCFG_EXTI_LINE11
<> 157:ff67d9f36b67 1120 * @arg @ref LL_SYSCFG_EXTI_LINE12
<> 157:ff67d9f36b67 1121 * @arg @ref LL_SYSCFG_EXTI_LINE13
<> 157:ff67d9f36b67 1122 * @arg @ref LL_SYSCFG_EXTI_LINE14
<> 157:ff67d9f36b67 1123 * @arg @ref LL_SYSCFG_EXTI_LINE15
<> 157:ff67d9f36b67 1124 * @retval None
<> 157:ff67d9f36b67 1125 */
<> 157:ff67d9f36b67 1126 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
<> 157:ff67d9f36b67 1127 {
<> 157:ff67d9f36b67 1128 MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16U), Port << POSITION_VAL((Line >> 16U)));
<> 157:ff67d9f36b67 1129 }
<> 157:ff67d9f36b67 1130
<> 157:ff67d9f36b67 1131 /**
<> 157:ff67d9f36b67 1132 * @brief Get the configured defined for specific EXTI Line
<> 157:ff67d9f36b67 1133 * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1134 * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1135 * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1136 * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1137 * SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1138 * SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1139 * SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1140 * SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1141 * SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1142 * SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1143 * SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1144 * SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1145 * SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1146 * SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1147 * SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1148 * SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1149 * SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1150 * SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1151 * SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1152 * SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1153 * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1154 * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1155 * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1156 * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1157 * SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1158 * SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1159 * SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1160 * SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1161 * SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1162 * SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1163 * SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1164 * SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1165 * SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1166 * SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1167 * SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1168 * SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1169 * SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1170 * SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1171 * SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1172 * SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1173 * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1174 * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1175 * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1176 * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1177 * SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1178 * SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1179 * SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1180 * SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1181 * SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1182 * SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1183 * SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1184 * SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1185 * SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1186 * SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1187 * SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1188 * SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1189 * SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1190 * SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1191 * SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1192 * SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1193 * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1194 * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1195 * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_GetEXTISource\n
<> 157:ff67d9f36b67 1196 * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_GetEXTISource
<> 157:ff67d9f36b67 1197 * @param Line This parameter can be one of the following values:
<> 157:ff67d9f36b67 1198 * @arg @ref LL_SYSCFG_EXTI_LINE0
<> 157:ff67d9f36b67 1199 * @arg @ref LL_SYSCFG_EXTI_LINE1
<> 157:ff67d9f36b67 1200 * @arg @ref LL_SYSCFG_EXTI_LINE2
<> 157:ff67d9f36b67 1201 * @arg @ref LL_SYSCFG_EXTI_LINE3
<> 157:ff67d9f36b67 1202 * @arg @ref LL_SYSCFG_EXTI_LINE4
<> 157:ff67d9f36b67 1203 * @arg @ref LL_SYSCFG_EXTI_LINE5
<> 157:ff67d9f36b67 1204 * @arg @ref LL_SYSCFG_EXTI_LINE6
<> 157:ff67d9f36b67 1205 * @arg @ref LL_SYSCFG_EXTI_LINE7
<> 157:ff67d9f36b67 1206 * @arg @ref LL_SYSCFG_EXTI_LINE8
<> 157:ff67d9f36b67 1207 * @arg @ref LL_SYSCFG_EXTI_LINE9
<> 157:ff67d9f36b67 1208 * @arg @ref LL_SYSCFG_EXTI_LINE10
<> 157:ff67d9f36b67 1209 * @arg @ref LL_SYSCFG_EXTI_LINE11
<> 157:ff67d9f36b67 1210 * @arg @ref LL_SYSCFG_EXTI_LINE12
<> 157:ff67d9f36b67 1211 * @arg @ref LL_SYSCFG_EXTI_LINE13
<> 157:ff67d9f36b67 1212 * @arg @ref LL_SYSCFG_EXTI_LINE14
<> 157:ff67d9f36b67 1213 * @arg @ref LL_SYSCFG_EXTI_LINE15
<> 157:ff67d9f36b67 1214 * @retval Returned value can be one of the following values:
<> 157:ff67d9f36b67 1215 * @arg @ref LL_SYSCFG_EXTI_PORTA
<> 157:ff67d9f36b67 1216 * @arg @ref LL_SYSCFG_EXTI_PORTB
<> 157:ff67d9f36b67 1217 * @arg @ref LL_SYSCFG_EXTI_PORTC
<> 157:ff67d9f36b67 1218 * @arg @ref LL_SYSCFG_EXTI_PORTD
<> 157:ff67d9f36b67 1219 * @arg @ref LL_SYSCFG_EXTI_PORTE (*)
<> 157:ff67d9f36b67 1220 * @arg @ref LL_SYSCFG_EXTI_PORTF
<> 157:ff67d9f36b67 1221 * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
<> 157:ff67d9f36b67 1222 * @arg @ref LL_SYSCFG_EXTI_PORTH (*)
<> 157:ff67d9f36b67 1223 *
<> 157:ff67d9f36b67 1224 * (*) value not defined in all devices.
<> 157:ff67d9f36b67 1225 */
<> 157:ff67d9f36b67 1226 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
<> 157:ff67d9f36b67 1227 {
<> 157:ff67d9f36b67 1228 return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16U)) >> POSITION_VAL(Line >> 16U));
<> 157:ff67d9f36b67 1229 }
<> 157:ff67d9f36b67 1230
<> 157:ff67d9f36b67 1231 /**
<> 157:ff67d9f36b67 1232 * @brief Set connections to TIMx Break inputs
<> 157:ff67d9f36b67 1233 * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_SetTIMBreakInputs\n
<> 157:ff67d9f36b67 1234 * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_SetTIMBreakInputs\n
<> 157:ff67d9f36b67 1235 * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_SetTIMBreakInputs
<> 157:ff67d9f36b67 1236 * @param Break This parameter can be a combination of the following values:
<> 157:ff67d9f36b67 1237 * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
<> 157:ff67d9f36b67 1238 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY (*)
<> 157:ff67d9f36b67 1239 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
<> 157:ff67d9f36b67 1240 *
<> 157:ff67d9f36b67 1241 * (*) value not defined in all devices.
<> 157:ff67d9f36b67 1242 * @retval None
<> 157:ff67d9f36b67 1243 */
<> 157:ff67d9f36b67 1244 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
<> 157:ff67d9f36b67 1245 {
<> 157:ff67d9f36b67 1246 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_MASK_TIM_BREAK, Break);
<> 157:ff67d9f36b67 1247 }
<> 157:ff67d9f36b67 1248
<> 157:ff67d9f36b67 1249 /**
<> 157:ff67d9f36b67 1250 * @brief Get connections to TIMx Break inputs
<> 157:ff67d9f36b67 1251 * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_GetTIMBreakInputs\n
<> 157:ff67d9f36b67 1252 * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_GetTIMBreakInputs\n
<> 157:ff67d9f36b67 1253 * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_GetTIMBreakInputs
<> 157:ff67d9f36b67 1254 * @retval Returned value can be can be a combination of the following values:
<> 157:ff67d9f36b67 1255 * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
<> 157:ff67d9f36b67 1256 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY (*)
<> 157:ff67d9f36b67 1257 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
<> 157:ff67d9f36b67 1258 *
<> 157:ff67d9f36b67 1259 * (*) value not defined in all devices.
<> 157:ff67d9f36b67 1260 */
<> 157:ff67d9f36b67 1261 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
<> 157:ff67d9f36b67 1262 {
<> 157:ff67d9f36b67 1263 return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_MASK_TIM_BREAK));
<> 157:ff67d9f36b67 1264 }
<> 157:ff67d9f36b67 1265
<> 157:ff67d9f36b67 1266 #if defined(SYSCFG_CFGR2_BYP_ADDR_PAR)
<> 157:ff67d9f36b67 1267 /**
<> 157:ff67d9f36b67 1268 * @brief Disable RAM Parity Check Disable
<> 157:ff67d9f36b67 1269 * @rmtoll SYSCFG_CFGR2 BYP_ADDR_PAR LL_SYSCFG_DisableSRAMParityCheck
<> 157:ff67d9f36b67 1270 * @retval None
<> 157:ff67d9f36b67 1271 */
<> 157:ff67d9f36b67 1272 __STATIC_INLINE void LL_SYSCFG_DisableSRAMParityCheck(void)
<> 157:ff67d9f36b67 1273 {
<> 157:ff67d9f36b67 1274 SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_BYP_ADDR_PAR);
<> 157:ff67d9f36b67 1275 }
<> 157:ff67d9f36b67 1276 #endif /* SYSCFG_CFGR2_BYP_ADDR_PAR */
<> 157:ff67d9f36b67 1277
<> 157:ff67d9f36b67 1278 #if defined(SYSCFG_CFGR2_SRAM_PE)
<> 157:ff67d9f36b67 1279 /**
<> 157:ff67d9f36b67 1280 * @brief Check if SRAM parity error detected
<> 157:ff67d9f36b67 1281 * @rmtoll SYSCFG_CFGR2 SRAM_PE LL_SYSCFG_IsActiveFlag_SP
<> 157:ff67d9f36b67 1282 * @retval State of bit (1 or 0).
<> 157:ff67d9f36b67 1283 */
<> 157:ff67d9f36b67 1284 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
<> 157:ff67d9f36b67 1285 {
<> 157:ff67d9f36b67 1286 return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PE) == (SYSCFG_CFGR2_SRAM_PE));
<> 157:ff67d9f36b67 1287 }
<> 157:ff67d9f36b67 1288
<> 157:ff67d9f36b67 1289 /**
<> 157:ff67d9f36b67 1290 * @brief Clear SRAM parity error flag
<> 157:ff67d9f36b67 1291 * @rmtoll SYSCFG_CFGR2 SRAM_PE LL_SYSCFG_ClearFlag_SP
<> 157:ff67d9f36b67 1292 * @retval None
<> 157:ff67d9f36b67 1293 */
<> 157:ff67d9f36b67 1294 __STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
<> 157:ff67d9f36b67 1295 {
<> 157:ff67d9f36b67 1296 SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PE);
<> 157:ff67d9f36b67 1297 }
<> 157:ff67d9f36b67 1298 #endif /* SYSCFG_CFGR2_SRAM_PE */
<> 157:ff67d9f36b67 1299
<> 157:ff67d9f36b67 1300 #if defined(SYSCFG_RCR_PAGE0)
<> 157:ff67d9f36b67 1301 /**
<> 157:ff67d9f36b67 1302 * @brief Enable CCM SRAM page write protection
<> 157:ff67d9f36b67 1303 * @note Write protection is cleared only by a system reset
<> 157:ff67d9f36b67 1304 * @rmtoll SYSCFG_RCR PAGE0 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
<> 157:ff67d9f36b67 1305 * SYSCFG_RCR PAGE1 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
<> 157:ff67d9f36b67 1306 * SYSCFG_RCR PAGE2 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
<> 157:ff67d9f36b67 1307 * SYSCFG_RCR PAGE3 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
<> 157:ff67d9f36b67 1308 * SYSCFG_RCR PAGE4 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
<> 157:ff67d9f36b67 1309 * SYSCFG_RCR PAGE5 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
<> 157:ff67d9f36b67 1310 * SYSCFG_RCR PAGE6 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
<> 157:ff67d9f36b67 1311 * SYSCFG_RCR PAGE7 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
<> 157:ff67d9f36b67 1312 * SYSCFG_RCR PAGE8 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
<> 157:ff67d9f36b67 1313 * SYSCFG_RCR PAGE9 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
<> 157:ff67d9f36b67 1314 * SYSCFG_RCR PAGE10 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
<> 157:ff67d9f36b67 1315 * SYSCFG_RCR PAGE11 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
<> 157:ff67d9f36b67 1316 * SYSCFG_RCR PAGE12 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
<> 157:ff67d9f36b67 1317 * SYSCFG_RCR PAGE13 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
<> 157:ff67d9f36b67 1318 * SYSCFG_RCR PAGE14 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
<> 157:ff67d9f36b67 1319 * SYSCFG_RCR PAGE15 LL_SYSCFG_EnableCCM_SRAMPageWRP
<> 157:ff67d9f36b67 1320 * @param PageWRP This parameter can be a combination of the following values:
<> 157:ff67d9f36b67 1321 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE0
<> 157:ff67d9f36b67 1322 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE1
<> 157:ff67d9f36b67 1323 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE2
<> 157:ff67d9f36b67 1324 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE3
<> 157:ff67d9f36b67 1325 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE4 (*)
<> 157:ff67d9f36b67 1326 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE5 (*)
<> 157:ff67d9f36b67 1327 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE6 (*)
<> 157:ff67d9f36b67 1328 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE7 (*)
<> 157:ff67d9f36b67 1329 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE8 (*)
<> 157:ff67d9f36b67 1330 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE9 (*)
<> 157:ff67d9f36b67 1331 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE10 (*)
<> 157:ff67d9f36b67 1332 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE11 (*)
<> 157:ff67d9f36b67 1333 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE12 (*)
<> 157:ff67d9f36b67 1334 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE13 (*)
<> 157:ff67d9f36b67 1335 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE14 (*)
<> 157:ff67d9f36b67 1336 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE15 (*)
<> 157:ff67d9f36b67 1337 *
<> 157:ff67d9f36b67 1338 * (*) value not defined in all devices.
<> 157:ff67d9f36b67 1339 * @retval None
<> 157:ff67d9f36b67 1340 */
<> 157:ff67d9f36b67 1341 __STATIC_INLINE void LL_SYSCFG_EnableCCM_SRAMPageWRP(uint32_t PageWRP)
<> 157:ff67d9f36b67 1342 {
<> 157:ff67d9f36b67 1343 SET_BIT(SYSCFG->RCR, PageWRP);
<> 157:ff67d9f36b67 1344 }
<> 157:ff67d9f36b67 1345 #endif /* SYSCFG_RCR_PAGE0 */
<> 157:ff67d9f36b67 1346
<> 157:ff67d9f36b67 1347 /**
<> 157:ff67d9f36b67 1348 * @}
<> 157:ff67d9f36b67 1349 */
<> 157:ff67d9f36b67 1350
<> 157:ff67d9f36b67 1351 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
<> 157:ff67d9f36b67 1352 * @{
<> 157:ff67d9f36b67 1353 */
<> 157:ff67d9f36b67 1354
<> 157:ff67d9f36b67 1355 /**
<> 157:ff67d9f36b67 1356 * @brief Return the device identifier
<> 157:ff67d9f36b67 1357 * @note For STM32F303xC, STM32F358xx and STM32F302xC devices, the device ID is 0x422
<> 157:ff67d9f36b67 1358 * @note For STM32F373xx and STM32F378xx devices, the device ID is 0x432
<> 157:ff67d9f36b67 1359 * @note For STM32F303x8, STM32F334xx and STM32F328xx devices, the device ID is 0x438.
<> 157:ff67d9f36b67 1360 * @note For STM32F302x8, STM32F301x8 and STM32F318xx devices, the device ID is 0x439
<> 157:ff67d9f36b67 1361 * @note For STM32F303xE, STM32F398xx and STM32F302xE devices, the device ID is 0x446
<> 157:ff67d9f36b67 1362 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
<> 157:ff67d9f36b67 1363 * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
<> 157:ff67d9f36b67 1364 */
<> 157:ff67d9f36b67 1365 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
<> 157:ff67d9f36b67 1366 {
<> 157:ff67d9f36b67 1367 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
<> 157:ff67d9f36b67 1368 }
<> 157:ff67d9f36b67 1369
<> 157:ff67d9f36b67 1370 /**
<> 157:ff67d9f36b67 1371 * @brief Return the device revision identifier
<> 157:ff67d9f36b67 1372 * @note This field indicates the revision of the device.
<> 157:ff67d9f36b67 1373 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
<> 157:ff67d9f36b67 1374 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
<> 157:ff67d9f36b67 1375 */
<> 157:ff67d9f36b67 1376 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
<> 157:ff67d9f36b67 1377 {
<> 157:ff67d9f36b67 1378 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_REVID_POSITION);
<> 157:ff67d9f36b67 1379 }
<> 157:ff67d9f36b67 1380
<> 157:ff67d9f36b67 1381 /**
<> 157:ff67d9f36b67 1382 * @brief Enable the Debug Module during SLEEP mode
<> 157:ff67d9f36b67 1383 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
<> 157:ff67d9f36b67 1384 * @retval None
<> 157:ff67d9f36b67 1385 */
<> 157:ff67d9f36b67 1386 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
<> 157:ff67d9f36b67 1387 {
<> 157:ff67d9f36b67 1388 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
<> 157:ff67d9f36b67 1389 }
<> 157:ff67d9f36b67 1390
<> 157:ff67d9f36b67 1391 /**
<> 157:ff67d9f36b67 1392 * @brief Disable the Debug Module during SLEEP mode
<> 157:ff67d9f36b67 1393 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
<> 157:ff67d9f36b67 1394 * @retval None
<> 157:ff67d9f36b67 1395 */
<> 157:ff67d9f36b67 1396 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
<> 157:ff67d9f36b67 1397 {
<> 157:ff67d9f36b67 1398 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
<> 157:ff67d9f36b67 1399 }
<> 157:ff67d9f36b67 1400
<> 157:ff67d9f36b67 1401 /**
<> 157:ff67d9f36b67 1402 * @brief Enable the Debug Module during STOP mode
<> 157:ff67d9f36b67 1403 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
<> 157:ff67d9f36b67 1404 * @retval None
<> 157:ff67d9f36b67 1405 */
<> 157:ff67d9f36b67 1406 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
<> 157:ff67d9f36b67 1407 {
<> 157:ff67d9f36b67 1408 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
<> 157:ff67d9f36b67 1409 }
<> 157:ff67d9f36b67 1410
<> 157:ff67d9f36b67 1411 /**
<> 157:ff67d9f36b67 1412 * @brief Disable the Debug Module during STOP mode
<> 157:ff67d9f36b67 1413 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
<> 157:ff67d9f36b67 1414 * @retval None
<> 157:ff67d9f36b67 1415 */
<> 157:ff67d9f36b67 1416 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
<> 157:ff67d9f36b67 1417 {
<> 157:ff67d9f36b67 1418 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
<> 157:ff67d9f36b67 1419 }
<> 157:ff67d9f36b67 1420
<> 157:ff67d9f36b67 1421 /**
<> 157:ff67d9f36b67 1422 * @brief Enable the Debug Module during STANDBY mode
<> 157:ff67d9f36b67 1423 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
<> 157:ff67d9f36b67 1424 * @retval None
<> 157:ff67d9f36b67 1425 */
<> 157:ff67d9f36b67 1426 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
<> 157:ff67d9f36b67 1427 {
<> 157:ff67d9f36b67 1428 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
<> 157:ff67d9f36b67 1429 }
<> 157:ff67d9f36b67 1430
<> 157:ff67d9f36b67 1431 /**
<> 157:ff67d9f36b67 1432 * @brief Disable the Debug Module during STANDBY mode
<> 157:ff67d9f36b67 1433 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
<> 157:ff67d9f36b67 1434 * @retval None
<> 157:ff67d9f36b67 1435 */
<> 157:ff67d9f36b67 1436 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
<> 157:ff67d9f36b67 1437 {
<> 157:ff67d9f36b67 1438 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
<> 157:ff67d9f36b67 1439 }
<> 157:ff67d9f36b67 1440
<> 157:ff67d9f36b67 1441 /**
<> 157:ff67d9f36b67 1442 * @brief Set Trace pin assignment control
<> 157:ff67d9f36b67 1443 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
<> 157:ff67d9f36b67 1444 * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
<> 157:ff67d9f36b67 1445 * @param PinAssignment This parameter can be one of the following values:
<> 157:ff67d9f36b67 1446 * @arg @ref LL_DBGMCU_TRACE_NONE
<> 157:ff67d9f36b67 1447 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
<> 157:ff67d9f36b67 1448 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
<> 157:ff67d9f36b67 1449 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
<> 157:ff67d9f36b67 1450 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
<> 157:ff67d9f36b67 1451 * @retval None
<> 157:ff67d9f36b67 1452 */
<> 157:ff67d9f36b67 1453 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
<> 157:ff67d9f36b67 1454 {
<> 157:ff67d9f36b67 1455 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
<> 157:ff67d9f36b67 1456 }
<> 157:ff67d9f36b67 1457
<> 157:ff67d9f36b67 1458 /**
<> 157:ff67d9f36b67 1459 * @brief Get Trace pin assignment control
<> 157:ff67d9f36b67 1460 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
<> 157:ff67d9f36b67 1461 * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
<> 157:ff67d9f36b67 1462 * @retval Returned value can be one of the following values:
<> 157:ff67d9f36b67 1463 * @arg @ref LL_DBGMCU_TRACE_NONE
<> 157:ff67d9f36b67 1464 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
<> 157:ff67d9f36b67 1465 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
<> 157:ff67d9f36b67 1466 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
<> 157:ff67d9f36b67 1467 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
<> 157:ff67d9f36b67 1468 */
<> 157:ff67d9f36b67 1469 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
<> 157:ff67d9f36b67 1470 {
<> 157:ff67d9f36b67 1471 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
<> 157:ff67d9f36b67 1472 }
<> 157:ff67d9f36b67 1473
<> 157:ff67d9f36b67 1474 /**
<> 157:ff67d9f36b67 1475 * @brief Freeze APB1 peripherals (group1 peripherals)
<> 157:ff67d9f36b67 1476 * @rmtoll APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 157:ff67d9f36b67 1477 * APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 157:ff67d9f36b67 1478 * APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 157:ff67d9f36b67 1479 * APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 157:ff67d9f36b67 1480 * APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 157:ff67d9f36b67 1481 * APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 157:ff67d9f36b67 1482 * APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 157:ff67d9f36b67 1483 * APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 157:ff67d9f36b67 1484 * APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 157:ff67d9f36b67 1485 * APB1_FZ DBG_TIM18_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 157:ff67d9f36b67 1486 * APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 157:ff67d9f36b67 1487 * APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 157:ff67d9f36b67 1488 * APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 157:ff67d9f36b67 1489 * APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 157:ff67d9f36b67 1490 * APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 157:ff67d9f36b67 1491 * APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 157:ff67d9f36b67 1492 * APB1_FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
<> 157:ff67d9f36b67 1493 * @param Periphs This parameter can be a combination of the following values:
<> 157:ff67d9f36b67 1494 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
<> 157:ff67d9f36b67 1495 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
<> 157:ff67d9f36b67 1496 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
<> 157:ff67d9f36b67 1497 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
<> 157:ff67d9f36b67 1498 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
<> 157:ff67d9f36b67 1499 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
<> 157:ff67d9f36b67 1500 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
<> 157:ff67d9f36b67 1501 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
<> 157:ff67d9f36b67 1502 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
<> 157:ff67d9f36b67 1503 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM18_STOP (*)
<> 157:ff67d9f36b67 1504 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
<> 157:ff67d9f36b67 1505 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
<> 157:ff67d9f36b67 1506 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
<> 157:ff67d9f36b67 1507 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
<> 157:ff67d9f36b67 1508 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
<> 157:ff67d9f36b67 1509 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
<> 157:ff67d9f36b67 1510 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*)
<> 157:ff67d9f36b67 1511 *
<> 157:ff67d9f36b67 1512 * (*) value not defined in all devices.
<> 157:ff67d9f36b67 1513 * @retval None
<> 157:ff67d9f36b67 1514 */
<> 157:ff67d9f36b67 1515 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
<> 157:ff67d9f36b67 1516 {
<> 157:ff67d9f36b67 1517 SET_BIT(DBGMCU->APB1FZ, Periphs);
<> 157:ff67d9f36b67 1518 }
<> 157:ff67d9f36b67 1519
<> 157:ff67d9f36b67 1520 /**
<> 157:ff67d9f36b67 1521 * @brief Unfreeze APB1 peripherals (group1 peripherals)
<> 157:ff67d9f36b67 1522 * @rmtoll APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 157:ff67d9f36b67 1523 * APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 157:ff67d9f36b67 1524 * APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 157:ff67d9f36b67 1525 * APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 157:ff67d9f36b67 1526 * APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 157:ff67d9f36b67 1527 * APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 157:ff67d9f36b67 1528 * APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 157:ff67d9f36b67 1529 * APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 157:ff67d9f36b67 1530 * APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 157:ff67d9f36b67 1531 * APB1_FZ DBG_TIM18_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 157:ff67d9f36b67 1532 * APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 157:ff67d9f36b67 1533 * APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 157:ff67d9f36b67 1534 * APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 157:ff67d9f36b67 1535 * APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 157:ff67d9f36b67 1536 * APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 157:ff67d9f36b67 1537 * APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 157:ff67d9f36b67 1538 * APB1_FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
<> 157:ff67d9f36b67 1539 * @param Periphs This parameter can be a combination of the following values:
<> 157:ff67d9f36b67 1540 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
<> 157:ff67d9f36b67 1541 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
<> 157:ff67d9f36b67 1542 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
<> 157:ff67d9f36b67 1543 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
<> 157:ff67d9f36b67 1544 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
<> 157:ff67d9f36b67 1545 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
<> 157:ff67d9f36b67 1546 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
<> 157:ff67d9f36b67 1547 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
<> 157:ff67d9f36b67 1548 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
<> 157:ff67d9f36b67 1549 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM18_STOP (*)
<> 157:ff67d9f36b67 1550 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
<> 157:ff67d9f36b67 1551 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
<> 157:ff67d9f36b67 1552 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
<> 157:ff67d9f36b67 1553 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
<> 157:ff67d9f36b67 1554 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
<> 157:ff67d9f36b67 1555 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
<> 157:ff67d9f36b67 1556 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*)
<> 157:ff67d9f36b67 1557 *
<> 157:ff67d9f36b67 1558 * (*) value not defined in all devices.
<> 157:ff67d9f36b67 1559 * @retval None
<> 157:ff67d9f36b67 1560 */
<> 157:ff67d9f36b67 1561 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
<> 157:ff67d9f36b67 1562 {
<> 157:ff67d9f36b67 1563 CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
<> 157:ff67d9f36b67 1564 }
<> 157:ff67d9f36b67 1565
<> 157:ff67d9f36b67 1566 /**
<> 157:ff67d9f36b67 1567 * @brief Freeze APB2 peripherals
<> 157:ff67d9f36b67 1568 * @rmtoll APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
<> 157:ff67d9f36b67 1569 * APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
<> 157:ff67d9f36b67 1570 * APB2_FZ DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
<> 157:ff67d9f36b67 1571 * APB2_FZ DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
<> 157:ff67d9f36b67 1572 * APB2_FZ DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
<> 157:ff67d9f36b67 1573 * APB2_FZ DBG_TIM19_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
<> 157:ff67d9f36b67 1574 * APB2_FZ DBG_TIM20_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
<> 157:ff67d9f36b67 1575 * APB2_FZ DBG_HRTIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
<> 157:ff67d9f36b67 1576 * @param Periphs This parameter can be a combination of the following values:
<> 157:ff67d9f36b67 1577 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP (*)
<> 157:ff67d9f36b67 1578 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
<> 157:ff67d9f36b67 1579 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
<> 157:ff67d9f36b67 1580 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
<> 157:ff67d9f36b67 1581 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
<> 157:ff67d9f36b67 1582 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM19_STOP (*)
<> 157:ff67d9f36b67 1583 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
<> 157:ff67d9f36b67 1584 * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
<> 157:ff67d9f36b67 1585 *
<> 157:ff67d9f36b67 1586 * (*) value not defined in all devices.
<> 157:ff67d9f36b67 1587 * @retval None
<> 157:ff67d9f36b67 1588 */
<> 157:ff67d9f36b67 1589 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
<> 157:ff67d9f36b67 1590 {
<> 157:ff67d9f36b67 1591 SET_BIT(DBGMCU->APB2FZ, Periphs);
<> 157:ff67d9f36b67 1592 }
<> 157:ff67d9f36b67 1593
<> 157:ff67d9f36b67 1594 /**
<> 157:ff67d9f36b67 1595 * @brief Unfreeze APB2 peripherals
<> 157:ff67d9f36b67 1596 * @rmtoll APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
<> 157:ff67d9f36b67 1597 * APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
<> 157:ff67d9f36b67 1598 * APB2_FZ DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
<> 157:ff67d9f36b67 1599 * APB2_FZ DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
<> 157:ff67d9f36b67 1600 * APB2_FZ DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
<> 157:ff67d9f36b67 1601 * APB2_FZ DBG_TIM19_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
<> 157:ff67d9f36b67 1602 * APB2_FZ DBG_TIM20_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
<> 157:ff67d9f36b67 1603 * APB2_FZ DBG_HRTIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
<> 157:ff67d9f36b67 1604 * @param Periphs This parameter can be a combination of the following values:
<> 157:ff67d9f36b67 1605 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP (*)
<> 157:ff67d9f36b67 1606 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
<> 157:ff67d9f36b67 1607 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
<> 157:ff67d9f36b67 1608 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
<> 157:ff67d9f36b67 1609 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
<> 157:ff67d9f36b67 1610 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM19_STOP (*)
<> 157:ff67d9f36b67 1611 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
<> 157:ff67d9f36b67 1612 * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
<> 157:ff67d9f36b67 1613 *
<> 157:ff67d9f36b67 1614 * (*) value not defined in all devices.
<> 157:ff67d9f36b67 1615 * @retval None
<> 157:ff67d9f36b67 1616 */
<> 157:ff67d9f36b67 1617 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
<> 157:ff67d9f36b67 1618 {
<> 157:ff67d9f36b67 1619 CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
<> 157:ff67d9f36b67 1620 }
<> 157:ff67d9f36b67 1621
<> 157:ff67d9f36b67 1622 /**
<> 157:ff67d9f36b67 1623 * @}
<> 157:ff67d9f36b67 1624 */
<> 157:ff67d9f36b67 1625
<> 157:ff67d9f36b67 1626 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
<> 157:ff67d9f36b67 1627 * @{
<> 157:ff67d9f36b67 1628 */
<> 157:ff67d9f36b67 1629
<> 157:ff67d9f36b67 1630 /**
<> 157:ff67d9f36b67 1631 * @brief Set FLASH Latency
<> 157:ff67d9f36b67 1632 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
<> 157:ff67d9f36b67 1633 * @param Latency This parameter can be one of the following values:
<> 157:ff67d9f36b67 1634 * @arg @ref LL_FLASH_LATENCY_0
<> 157:ff67d9f36b67 1635 * @arg @ref LL_FLASH_LATENCY_1
<> 157:ff67d9f36b67 1636 * @arg @ref LL_FLASH_LATENCY_2
<> 157:ff67d9f36b67 1637 * @retval None
<> 157:ff67d9f36b67 1638 */
<> 157:ff67d9f36b67 1639 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
<> 157:ff67d9f36b67 1640 {
<> 157:ff67d9f36b67 1641 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
<> 157:ff67d9f36b67 1642 }
<> 157:ff67d9f36b67 1643
<> 157:ff67d9f36b67 1644 /**
<> 157:ff67d9f36b67 1645 * @brief Get FLASH Latency
<> 157:ff67d9f36b67 1646 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
<> 157:ff67d9f36b67 1647 * @retval Returned value can be one of the following values:
<> 157:ff67d9f36b67 1648 * @arg @ref LL_FLASH_LATENCY_0
<> 157:ff67d9f36b67 1649 * @arg @ref LL_FLASH_LATENCY_1
<> 157:ff67d9f36b67 1650 * @arg @ref LL_FLASH_LATENCY_2
<> 157:ff67d9f36b67 1651 */
<> 157:ff67d9f36b67 1652 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
<> 157:ff67d9f36b67 1653 {
<> 157:ff67d9f36b67 1654 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
<> 157:ff67d9f36b67 1655 }
<> 157:ff67d9f36b67 1656
<> 157:ff67d9f36b67 1657 /**
<> 157:ff67d9f36b67 1658 * @brief Enable Prefetch
<> 157:ff67d9f36b67 1659 * @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch
<> 157:ff67d9f36b67 1660 * @retval None
<> 157:ff67d9f36b67 1661 */
<> 157:ff67d9f36b67 1662 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
<> 157:ff67d9f36b67 1663 {
<> 157:ff67d9f36b67 1664 SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE );
<> 157:ff67d9f36b67 1665 }
<> 157:ff67d9f36b67 1666
<> 157:ff67d9f36b67 1667 /**
<> 157:ff67d9f36b67 1668 * @brief Disable Prefetch
<> 157:ff67d9f36b67 1669 * @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch
<> 157:ff67d9f36b67 1670 * @retval None
<> 157:ff67d9f36b67 1671 */
<> 157:ff67d9f36b67 1672 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
<> 157:ff67d9f36b67 1673 {
<> 157:ff67d9f36b67 1674 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE );
<> 157:ff67d9f36b67 1675 }
<> 157:ff67d9f36b67 1676
<> 157:ff67d9f36b67 1677 /**
<> 157:ff67d9f36b67 1678 * @brief Check if Prefetch buffer is enabled
<> 157:ff67d9f36b67 1679 * @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled
<> 157:ff67d9f36b67 1680 * @retval State of bit (1 or 0).
<> 157:ff67d9f36b67 1681 */
<> 157:ff67d9f36b67 1682 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
<> 157:ff67d9f36b67 1683 {
<> 157:ff67d9f36b67 1684 return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS));
<> 157:ff67d9f36b67 1685 }
<> 157:ff67d9f36b67 1686
<> 157:ff67d9f36b67 1687 #if defined(FLASH_ACR_HLFCYA)
<> 157:ff67d9f36b67 1688 /**
<> 157:ff67d9f36b67 1689 * @brief Enable Flash Half Cycle Access
<> 157:ff67d9f36b67 1690 * @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess
<> 157:ff67d9f36b67 1691 * @retval None
<> 157:ff67d9f36b67 1692 */
<> 157:ff67d9f36b67 1693 __STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void)
<> 157:ff67d9f36b67 1694 {
<> 157:ff67d9f36b67 1695 SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
<> 157:ff67d9f36b67 1696 }
<> 157:ff67d9f36b67 1697
<> 157:ff67d9f36b67 1698 /**
<> 157:ff67d9f36b67 1699 * @brief Disable Flash Half Cycle Access
<> 157:ff67d9f36b67 1700 * @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess
<> 157:ff67d9f36b67 1701 * @retval None
<> 157:ff67d9f36b67 1702 */
<> 157:ff67d9f36b67 1703 __STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void)
<> 157:ff67d9f36b67 1704 {
<> 157:ff67d9f36b67 1705 CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
<> 157:ff67d9f36b67 1706 }
<> 157:ff67d9f36b67 1707
<> 157:ff67d9f36b67 1708 /**
<> 157:ff67d9f36b67 1709 * @brief Check if Flash Half Cycle Access is enabled or not
<> 157:ff67d9f36b67 1710 * @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled
<> 157:ff67d9f36b67 1711 * @retval State of bit (1 or 0).
<> 157:ff67d9f36b67 1712 */
<> 157:ff67d9f36b67 1713 __STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void)
<> 157:ff67d9f36b67 1714 {
<> 157:ff67d9f36b67 1715 return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA));
<> 157:ff67d9f36b67 1716 }
<> 157:ff67d9f36b67 1717 #endif /* FLASH_ACR_HLFCYA */
<> 157:ff67d9f36b67 1718
<> 157:ff67d9f36b67 1719
<> 157:ff67d9f36b67 1720
<> 157:ff67d9f36b67 1721 /**
<> 157:ff67d9f36b67 1722 * @}
<> 157:ff67d9f36b67 1723 */
<> 157:ff67d9f36b67 1724
<> 157:ff67d9f36b67 1725 /**
<> 157:ff67d9f36b67 1726 * @}
<> 157:ff67d9f36b67 1727 */
<> 157:ff67d9f36b67 1728
<> 157:ff67d9f36b67 1729 /**
<> 157:ff67d9f36b67 1730 * @}
<> 157:ff67d9f36b67 1731 */
<> 157:ff67d9f36b67 1732
<> 157:ff67d9f36b67 1733 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
<> 157:ff67d9f36b67 1734
<> 157:ff67d9f36b67 1735 /**
<> 157:ff67d9f36b67 1736 * @}
<> 157:ff67d9f36b67 1737 */
<> 157:ff67d9f36b67 1738
<> 157:ff67d9f36b67 1739 #ifdef __cplusplus
<> 157:ff67d9f36b67 1740 }
<> 157:ff67d9f36b67 1741 #endif
<> 157:ff67d9f36b67 1742
<> 157:ff67d9f36b67 1743 #endif /* __STM32F3xx_LL_SYSTEM_H */
<> 157:ff67d9f36b67 1744
<> 157:ff67d9f36b67 1745 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/