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targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_lptim.c@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_hal_lptim.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.5.1
<> 144:ef7eb2e8f9f7 6 * @date 31-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief LPTIM HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Low Power Timer (LPTIM) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions.
<> 144:ef7eb2e8f9f7 11 * + Start/Stop operation functions in polling mode.
<> 144:ef7eb2e8f9f7 12 * + Start/Stop operation functions in interrupt mode.
<> 144:ef7eb2e8f9f7 13 * + Reading operation functions.
<> 144:ef7eb2e8f9f7 14 * + Peripheral State functions.
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 @verbatim
<> 144:ef7eb2e8f9f7 17 ==============================================================================
<> 144:ef7eb2e8f9f7 18 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 19 ==============================================================================
<> 144:ef7eb2e8f9f7 20 [..]
<> 144:ef7eb2e8f9f7 21 The LPTIM HAL driver can be used as follows:
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 (#)Initialize the LPTIM low level resources by implementing the
<> 144:ef7eb2e8f9f7 24 HAL_LPTIM_MspInit():
<> 144:ef7eb2e8f9f7 25 (++) Enable the LPTIM interface clock using __HAL_RCC_LPTIMx_CLK_ENABLE().
<> 144:ef7eb2e8f9f7 26 (++) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
<> 144:ef7eb2e8f9f7 27 (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
<> 144:ef7eb2e8f9f7 28 (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
<> 144:ef7eb2e8f9f7 29 (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
<> 144:ef7eb2e8f9f7 32 configures mainly:
<> 144:ef7eb2e8f9f7 33 (++) The instance: LPTIM1 or LPTIM2.
<> 144:ef7eb2e8f9f7 34 (++) Clock: the counter clock.
<> 144:ef7eb2e8f9f7 35 (+++) Source : it can be either the ULPTIM input (IN1) or one of
<> 144:ef7eb2e8f9f7 36 the internal clock; (APB, LSE, LSI or MSI).
<> 144:ef7eb2e8f9f7 37 (+++) Prescaler: select the clock divider.
<> 144:ef7eb2e8f9f7 38 (++) UltraLowPowerClock : To be used only if the ULPTIM is selected
<> 144:ef7eb2e8f9f7 39 as counter clock source.
<> 144:ef7eb2e8f9f7 40 (+++) Polarity: polarity of the active edge for the counter unit
<> 144:ef7eb2e8f9f7 41 if the ULPTIM input is selected.
<> 144:ef7eb2e8f9f7 42 (+++) SampleTime: clock sampling time to configure the clock glitch
<> 144:ef7eb2e8f9f7 43 filter.
<> 144:ef7eb2e8f9f7 44 (++) Trigger: How the counter start.
<> 144:ef7eb2e8f9f7 45 (+++) Source: trigger can be software or one of the hardware triggers.
<> 144:ef7eb2e8f9f7 46 (+++) ActiveEdge : only for hardware trigger.
<> 144:ef7eb2e8f9f7 47 (+++) SampleTime : trigger sampling time to configure the trigger
<> 144:ef7eb2e8f9f7 48 glitch filter.
<> 144:ef7eb2e8f9f7 49 (++) OutputPolarity : 2 opposite polarities are possible.
<> 144:ef7eb2e8f9f7 50 (++) UpdateMode: specifies whether the update of the autoreload and
<> 144:ef7eb2e8f9f7 51 the compare values is done immediately or after the end of current
<> 144:ef7eb2e8f9f7 52 period.
<> 144:ef7eb2e8f9f7 53 (++) Input1Source: Source selected for input1 (GPIO or comparator output).
<> 144:ef7eb2e8f9f7 54 (++) Input2Source: Source selected for input2 (GPIO or comparator output).
<> 144:ef7eb2e8f9f7 55 Input2 is used only for encoder feature so is used only for LPTIM1 instance.
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 (#)Six modes are available:
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 (++) PWM Mode: To generate a PWM signal with specified period and pulse,
<> 144:ef7eb2e8f9f7 60 call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
<> 144:ef7eb2e8f9f7 61 mode.
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 (++) One Pulse Mode: To generate pulse with specified width in response
<> 144:ef7eb2e8f9f7 64 to a stimulus, call HAL_LPTIM_OnePulse_Start() or
<> 144:ef7eb2e8f9f7 65 HAL_LPTIM_OnePulse_Start_IT() for interruption mode.
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 (++) Set once Mode: In this mode, the output changes the level (from
<> 144:ef7eb2e8f9f7 68 low level to high level if the output polarity is configured high, else
<> 144:ef7eb2e8f9f7 69 the opposite) when a compare match occurs. To start this mode, call
<> 144:ef7eb2e8f9f7 70 HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
<> 144:ef7eb2e8f9f7 71 interruption mode.
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 (++) Encoder Mode: To use the encoder interface call
<> 144:ef7eb2e8f9f7 74 HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
<> 144:ef7eb2e8f9f7 75 interruption mode. Only available for LPTIM1 instance.
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 (++) Time out Mode: an active edge on one selected trigger input rests
<> 144:ef7eb2e8f9f7 78 the counter. The first trigger event will start the timer, any
<> 144:ef7eb2e8f9f7 79 successive trigger event will reset the counter and the timer will
<> 144:ef7eb2e8f9f7 80 restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
<> 144:ef7eb2e8f9f7 81 HAL_LPTIM_TimeOut_Start_IT() for interruption mode.
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 (++) Counter Mode: counter can be used to count external events on
<> 144:ef7eb2e8f9f7 84 the LPTIM Input1 or it can be used to count internal clock cycles.
<> 144:ef7eb2e8f9f7 85 To start this mode, call HAL_LPTIM_Counter_Start() or
<> 144:ef7eb2e8f9f7 86 HAL_LPTIM_Counter_Start_IT() for interruption mode.
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 (#) User can stop any process by calling the corresponding API:
<> 144:ef7eb2e8f9f7 90 HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
<> 144:ef7eb2e8f9f7 91 already started in interruption mode.
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 (#) De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit().
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 @endverbatim
<> 144:ef7eb2e8f9f7 96 ******************************************************************************
<> 144:ef7eb2e8f9f7 97 * @attention
<> 144:ef7eb2e8f9f7 98 *
<> 144:ef7eb2e8f9f7 99 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 100 *
<> 144:ef7eb2e8f9f7 101 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 102 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 103 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 104 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 105 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 106 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 107 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 108 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 109 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 110 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 111 *
<> 144:ef7eb2e8f9f7 112 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 113 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 114 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 115 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 116 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 117 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 118 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 119 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 120 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 121 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 122 *
<> 144:ef7eb2e8f9f7 123 ******************************************************************************
<> 144:ef7eb2e8f9f7 124 */
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 127 #include "stm32l4xx_hal.h"
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /** @addtogroup STM32L4xx_HAL_Driver
<> 144:ef7eb2e8f9f7 130 * @{
<> 144:ef7eb2e8f9f7 131 */
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /** @defgroup LPTIM LPTIM
<> 144:ef7eb2e8f9f7 134 * @brief LPTIM HAL module driver.
<> 144:ef7eb2e8f9f7 135 * @{
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 #ifdef HAL_LPTIM_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 139 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 140 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 141 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 142 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 143 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 144 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 /** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
<> 144:ef7eb2e8f9f7 147 * @{
<> 144:ef7eb2e8f9f7 148 */
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 /** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions
<> 144:ef7eb2e8f9f7 151 * @brief Initialization and Configuration functions.
<> 144:ef7eb2e8f9f7 152 *
<> 144:ef7eb2e8f9f7 153 @verbatim
<> 144:ef7eb2e8f9f7 154 ==============================================================================
<> 144:ef7eb2e8f9f7 155 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 156 ==============================================================================
<> 144:ef7eb2e8f9f7 157 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 158 (+) Initialize the LPTIM according to the specified parameters in the
<> 144:ef7eb2e8f9f7 159 LPTIM_InitTypeDef and initialize the associated handle.
<> 144:ef7eb2e8f9f7 160 (+) DeInitialize the LPTIM peripheral.
<> 144:ef7eb2e8f9f7 161 (+) Initialize the LPTIM MSP.
<> 144:ef7eb2e8f9f7 162 (+) DeInitialize the LPTIM MSP.
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 @endverbatim
<> 144:ef7eb2e8f9f7 165 * @{
<> 144:ef7eb2e8f9f7 166 */
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /**
<> 144:ef7eb2e8f9f7 169 * @brief Initialize the LPTIM according to the specified parameters in the
<> 144:ef7eb2e8f9f7 170 * LPTIM_InitTypeDef and initialize the associated handle.
<> 144:ef7eb2e8f9f7 171 * @param hlptim: LPTIM handle
<> 144:ef7eb2e8f9f7 172 * @retval HAL status
<> 144:ef7eb2e8f9f7 173 */
<> 144:ef7eb2e8f9f7 174 HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
<> 144:ef7eb2e8f9f7 175 {
<> 144:ef7eb2e8f9f7 176 uint32_t tmpcfgr = 0;
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 /* Check the LPTIM handle allocation */
<> 144:ef7eb2e8f9f7 179 if(hlptim == NULL)
<> 144:ef7eb2e8f9f7 180 {
<> 144:ef7eb2e8f9f7 181 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 182 }
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 /* Check the parameters */
<> 144:ef7eb2e8f9f7 185 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
<> 144:ef7eb2e8f9f7 188 assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
<> 144:ef7eb2e8f9f7 189 if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)
<> 144:ef7eb2e8f9f7 190 {
<> 144:ef7eb2e8f9f7 191 assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
<> 144:ef7eb2e8f9f7 192 assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
<> 144:ef7eb2e8f9f7 193 }
<> 144:ef7eb2e8f9f7 194 assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
<> 144:ef7eb2e8f9f7 195 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
<> 144:ef7eb2e8f9f7 196 {
<> 144:ef7eb2e8f9f7 197 assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
<> 144:ef7eb2e8f9f7 198 assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
<> 144:ef7eb2e8f9f7 199 }
<> 144:ef7eb2e8f9f7 200 assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));
<> 144:ef7eb2e8f9f7 201 assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
<> 144:ef7eb2e8f9f7 202 assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 if(hlptim->State == HAL_LPTIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 205 {
<> 144:ef7eb2e8f9f7 206 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 207 hlptim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 /* Init the low level hardware */
<> 144:ef7eb2e8f9f7 210 HAL_LPTIM_MspInit(hlptim);
<> 144:ef7eb2e8f9f7 211 }
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /* Change the LPTIM state */
<> 144:ef7eb2e8f9f7 214 hlptim->State = HAL_LPTIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /* Get the LPTIMx CFGR value */
<> 144:ef7eb2e8f9f7 217 tmpcfgr = hlptim->Instance->CFGR;
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)
<> 144:ef7eb2e8f9f7 220 {
<> 144:ef7eb2e8f9f7 221 tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
<> 144:ef7eb2e8f9f7 222 }
<> 144:ef7eb2e8f9f7 223 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
<> 144:ef7eb2e8f9f7 224 {
<> 144:ef7eb2e8f9f7 225 tmpcfgr &= (uint32_t)(~ (LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
<> 144:ef7eb2e8f9f7 226 }
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
<> 144:ef7eb2e8f9f7 229 tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
<> 144:ef7eb2e8f9f7 230 LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE ));
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /* Set initialization parameters */
<> 144:ef7eb2e8f9f7 233 tmpcfgr |= (hlptim->Init.Clock.Source |
<> 144:ef7eb2e8f9f7 234 hlptim->Init.Clock.Prescaler |
<> 144:ef7eb2e8f9f7 235 hlptim->Init.OutputPolarity |
<> 144:ef7eb2e8f9f7 236 hlptim->Init.UpdateMode |
<> 144:ef7eb2e8f9f7 237 hlptim->Init.CounterSource);
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)
<> 144:ef7eb2e8f9f7 240 {
<> 144:ef7eb2e8f9f7 241 tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
<> 144:ef7eb2e8f9f7 242 hlptim->Init.UltraLowPowerClock.SampleTime);
<> 144:ef7eb2e8f9f7 243 }
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
<> 144:ef7eb2e8f9f7 246 {
<> 144:ef7eb2e8f9f7 247 /* Enable External trigger and set the trigger source */
<> 144:ef7eb2e8f9f7 248 tmpcfgr |= (hlptim->Init.Trigger.Source |
<> 144:ef7eb2e8f9f7 249 hlptim->Init.Trigger.ActiveEdge |
<> 144:ef7eb2e8f9f7 250 hlptim->Init.Trigger.SampleTime);
<> 144:ef7eb2e8f9f7 251 }
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /* Write to LPTIMx CFGR */
<> 144:ef7eb2e8f9f7 254 hlptim->Instance->CFGR = tmpcfgr;
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /* Configure LPTIM input sources */
<> 144:ef7eb2e8f9f7 257 if(hlptim->Instance == LPTIM1)
<> 144:ef7eb2e8f9f7 258 {
<> 144:ef7eb2e8f9f7 259 /* Check LPTIM1 Input1 and Input2 sources */
<> 144:ef7eb2e8f9f7 260 assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance,hlptim->Init.Input1Source));
<> 144:ef7eb2e8f9f7 261 assert_param(IS_LPTIM_INPUT2_SOURCE(hlptim->Instance,hlptim->Init.Input2Source));
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /* Configure LPTIM1 Input1 and Input2 sources */
<> 144:ef7eb2e8f9f7 264 hlptim->Instance->OR = (hlptim->Init.Input1Source | hlptim->Init.Input2Source);
<> 144:ef7eb2e8f9f7 265 }
<> 144:ef7eb2e8f9f7 266 else
<> 144:ef7eb2e8f9f7 267 {
<> 144:ef7eb2e8f9f7 268 /* Check LPTIM2 Input1 source */
<> 144:ef7eb2e8f9f7 269 assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance,hlptim->Init.Input1Source));
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 /* Configure LPTIM2 Input1 source */
<> 144:ef7eb2e8f9f7 272 hlptim->Instance->OR = hlptim->Init.Input1Source;
<> 144:ef7eb2e8f9f7 273 }
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 /* Change the LPTIM state */
<> 144:ef7eb2e8f9f7 276 hlptim->State = HAL_LPTIM_STATE_READY;
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 /* Return function status */
<> 144:ef7eb2e8f9f7 279 return HAL_OK;
<> 144:ef7eb2e8f9f7 280 }
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /**
<> 144:ef7eb2e8f9f7 283 * @brief DeInitialize the LPTIM peripheral.
<> 144:ef7eb2e8f9f7 284 * @param hlptim: LPTIM handle
<> 144:ef7eb2e8f9f7 285 * @retval HAL status
<> 144:ef7eb2e8f9f7 286 */
<> 144:ef7eb2e8f9f7 287 HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
<> 144:ef7eb2e8f9f7 288 {
<> 144:ef7eb2e8f9f7 289 /* Check the LPTIM handle allocation */
<> 144:ef7eb2e8f9f7 290 if(hlptim == NULL)
<> 144:ef7eb2e8f9f7 291 {
<> 144:ef7eb2e8f9f7 292 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 293 }
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 /* Change the LPTIM state */
<> 144:ef7eb2e8f9f7 296 hlptim->State = HAL_LPTIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 /* Disable the LPTIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 299 __HAL_LPTIM_DISABLE(hlptim);
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 /* DeInit the low level hardware: CLOCK, NVIC.*/
<> 144:ef7eb2e8f9f7 302 HAL_LPTIM_MspDeInit(hlptim);
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 /* Change the LPTIM state */
<> 144:ef7eb2e8f9f7 305 hlptim->State = HAL_LPTIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /* Release Lock */
<> 144:ef7eb2e8f9f7 308 __HAL_UNLOCK(hlptim);
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 /* Return function status */
<> 144:ef7eb2e8f9f7 311 return HAL_OK;
<> 144:ef7eb2e8f9f7 312 }
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /**
<> 144:ef7eb2e8f9f7 315 * @brief Initialize the LPTIM MSP.
<> 144:ef7eb2e8f9f7 316 * @param hlptim: LPTIM handle
<> 144:ef7eb2e8f9f7 317 * @retval None
<> 144:ef7eb2e8f9f7 318 */
<> 144:ef7eb2e8f9f7 319 __weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
<> 144:ef7eb2e8f9f7 320 {
<> 144:ef7eb2e8f9f7 321 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 322 UNUSED(hlptim);
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 325 the HAL_LPTIM_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 326 */
<> 144:ef7eb2e8f9f7 327 }
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /**
<> 144:ef7eb2e8f9f7 330 * @brief DeInitialize LPTIM MSP.
<> 144:ef7eb2e8f9f7 331 * @param hlptim: LPTIM handle
<> 144:ef7eb2e8f9f7 332 * @retval None
<> 144:ef7eb2e8f9f7 333 */
<> 144:ef7eb2e8f9f7 334 __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
<> 144:ef7eb2e8f9f7 335 {
<> 144:ef7eb2e8f9f7 336 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 337 UNUSED(hlptim);
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 340 the HAL_LPTIM_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 341 */
<> 144:ef7eb2e8f9f7 342 }
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 /**
<> 144:ef7eb2e8f9f7 345 * @}
<> 144:ef7eb2e8f9f7 346 */
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 /** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions
<> 144:ef7eb2e8f9f7 349 * @brief Start-Stop operation functions.
<> 144:ef7eb2e8f9f7 350 *
<> 144:ef7eb2e8f9f7 351 @verbatim
<> 144:ef7eb2e8f9f7 352 ==============================================================================
<> 144:ef7eb2e8f9f7 353 ##### LPTIM Start Stop operation functions #####
<> 144:ef7eb2e8f9f7 354 ==============================================================================
<> 144:ef7eb2e8f9f7 355 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 356 (+) Start the PWM mode.
<> 144:ef7eb2e8f9f7 357 (+) Stop the PWM mode.
<> 144:ef7eb2e8f9f7 358 (+) Start the One pulse mode.
<> 144:ef7eb2e8f9f7 359 (+) Stop the One pulse mode.
<> 144:ef7eb2e8f9f7 360 (+) Start the Set once mode.
<> 144:ef7eb2e8f9f7 361 (+) Stop the Set once mode.
<> 144:ef7eb2e8f9f7 362 (+) Start the Encoder mode.
<> 144:ef7eb2e8f9f7 363 (+) Stop the Encoder mode.
<> 144:ef7eb2e8f9f7 364 (+) Start the Timeout mode.
<> 144:ef7eb2e8f9f7 365 (+) Stop the Timeout mode.
<> 144:ef7eb2e8f9f7 366 (+) Start the Counter mode.
<> 144:ef7eb2e8f9f7 367 (+) Stop the Counter mode.
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 @endverbatim
<> 144:ef7eb2e8f9f7 371 * @{
<> 144:ef7eb2e8f9f7 372 */
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /**
<> 144:ef7eb2e8f9f7 375 * @brief Start the LPTIM PWM generation.
<> 144:ef7eb2e8f9f7 376 * @param hlptim : LPTIM handle
<> 144:ef7eb2e8f9f7 377 * @param Period : Specifies the Autoreload value.
<> 144:ef7eb2e8f9f7 378 * This parameter must be a value between 0x0000 and 0xFFFF.
<> 144:ef7eb2e8f9f7 379 * @param Pulse : Specifies the compare value.
<> 144:ef7eb2e8f9f7 380 * This parameter must be a value between 0x0000 and 0xFFFF.
<> 144:ef7eb2e8f9f7 381 * @retval HAL status
<> 144:ef7eb2e8f9f7 382 */
<> 144:ef7eb2e8f9f7 383 HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
<> 144:ef7eb2e8f9f7 384 {
<> 144:ef7eb2e8f9f7 385 /* Check the parameters */
<> 144:ef7eb2e8f9f7 386 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
<> 144:ef7eb2e8f9f7 387 assert_param(IS_LPTIM_PERIOD(Period));
<> 144:ef7eb2e8f9f7 388 assert_param(IS_LPTIM_PULSE(Pulse));
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 /* Set the LPTIM state */
<> 144:ef7eb2e8f9f7 391 hlptim->State= HAL_LPTIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 /* Reset WAVE bit to set PWM mode */
<> 144:ef7eb2e8f9f7 394 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 397 __HAL_LPTIM_ENABLE(hlptim);
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 /* Load the period value in the autoreload register */
<> 144:ef7eb2e8f9f7 400 __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 /* Load the pulse value in the compare register */
<> 144:ef7eb2e8f9f7 403 __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 /* Start timer in continuous mode */
<> 144:ef7eb2e8f9f7 406 __HAL_LPTIM_START_CONTINUOUS(hlptim);
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 409 hlptim->State= HAL_LPTIM_STATE_READY;
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 /* Return function status */
<> 144:ef7eb2e8f9f7 412 return HAL_OK;
<> 144:ef7eb2e8f9f7 413 }
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 /**
<> 144:ef7eb2e8f9f7 416 * @brief Stop the LPTIM PWM generation.
<> 144:ef7eb2e8f9f7 417 * @param hlptim : LPTIM handle
<> 144:ef7eb2e8f9f7 418 * @retval HAL status
<> 144:ef7eb2e8f9f7 419 */
<> 144:ef7eb2e8f9f7 420 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)
<> 144:ef7eb2e8f9f7 421 {
<> 144:ef7eb2e8f9f7 422 /* Check the parameters */
<> 144:ef7eb2e8f9f7 423 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 /* Set the LPTIM state */
<> 144:ef7eb2e8f9f7 426 hlptim->State= HAL_LPTIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 429 __HAL_LPTIM_DISABLE(hlptim);
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 432 hlptim->State= HAL_LPTIM_STATE_READY;
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 /* Return function status */
<> 144:ef7eb2e8f9f7 435 return HAL_OK;
<> 144:ef7eb2e8f9f7 436 }
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 /**
<> 144:ef7eb2e8f9f7 439 * @brief Start the LPTIM PWM generation in interrupt mode.
<> 144:ef7eb2e8f9f7 440 * @param hlptim : LPTIM handle
<> 144:ef7eb2e8f9f7 441 * @param Period : Specifies the Autoreload value.
<> 144:ef7eb2e8f9f7 442 * This parameter must be a value between 0x0000 and 0xFFFF
<> 144:ef7eb2e8f9f7 443 * @param Pulse : Specifies the compare value.
<> 144:ef7eb2e8f9f7 444 * This parameter must be a value between 0x0000 and 0xFFFF
<> 144:ef7eb2e8f9f7 445 * @retval HAL status
<> 144:ef7eb2e8f9f7 446 */
<> 144:ef7eb2e8f9f7 447 HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
<> 144:ef7eb2e8f9f7 448 {
<> 144:ef7eb2e8f9f7 449 /* Check the parameters */
<> 144:ef7eb2e8f9f7 450 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
<> 144:ef7eb2e8f9f7 451 assert_param(IS_LPTIM_PERIOD(Period));
<> 144:ef7eb2e8f9f7 452 assert_param(IS_LPTIM_PULSE(Pulse));
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 /* Set the LPTIM state */
<> 144:ef7eb2e8f9f7 455 hlptim->State= HAL_LPTIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 /* Reset WAVE bit to set PWM mode */
<> 144:ef7eb2e8f9f7 458 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 /* Enable Autoreload write complete interrupt */
<> 144:ef7eb2e8f9f7 461 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 /* Enable Compare write complete interrupt */
<> 144:ef7eb2e8f9f7 464 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /* Enable Autoreload match interrupt */
<> 144:ef7eb2e8f9f7 467 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /* Enable Compare match interrupt */
<> 144:ef7eb2e8f9f7 470 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 /* If external trigger source is used, then enable external trigger interrupt */
<> 144:ef7eb2e8f9f7 473 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
<> 144:ef7eb2e8f9f7 474 {
<> 144:ef7eb2e8f9f7 475 /* Enable external trigger interrupt */
<> 144:ef7eb2e8f9f7 476 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
<> 144:ef7eb2e8f9f7 477 }
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 480 __HAL_LPTIM_ENABLE(hlptim);
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 /* Load the period value in the autoreload register */
<> 144:ef7eb2e8f9f7 483 __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 /* Load the pulse value in the compare register */
<> 144:ef7eb2e8f9f7 486 __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 /* Start timer in continuous mode */
<> 144:ef7eb2e8f9f7 489 __HAL_LPTIM_START_CONTINUOUS(hlptim);
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 492 hlptim->State= HAL_LPTIM_STATE_READY;
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 /* Return function status */
<> 144:ef7eb2e8f9f7 495 return HAL_OK;
<> 144:ef7eb2e8f9f7 496 }
<> 144:ef7eb2e8f9f7 497
<> 144:ef7eb2e8f9f7 498 /**
<> 144:ef7eb2e8f9f7 499 * @brief Stop the LPTIM PWM generation in interrupt mode.
<> 144:ef7eb2e8f9f7 500 * @param hlptim : LPTIM handle
<> 144:ef7eb2e8f9f7 501 * @retval HAL status
<> 144:ef7eb2e8f9f7 502 */
<> 144:ef7eb2e8f9f7 503 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)
<> 144:ef7eb2e8f9f7 504 {
<> 144:ef7eb2e8f9f7 505 /* Check the parameters */
<> 144:ef7eb2e8f9f7 506 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /* Set the LPTIM state */
<> 144:ef7eb2e8f9f7 509 hlptim->State= HAL_LPTIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 512 __HAL_LPTIM_DISABLE(hlptim);
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 /* Disable Autoreload write complete interrupt */
<> 144:ef7eb2e8f9f7 515 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 /* Disable Compare write complete interrupt */
<> 144:ef7eb2e8f9f7 518 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 /* Disable Autoreload match interrupt */
<> 144:ef7eb2e8f9f7 521 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 /* Disable Compare match interrupt */
<> 144:ef7eb2e8f9f7 524 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 /* If external trigger source is used, then disable external trigger interrupt */
<> 144:ef7eb2e8f9f7 527 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
<> 144:ef7eb2e8f9f7 528 {
<> 144:ef7eb2e8f9f7 529 /* Disable external trigger interrupt */
<> 144:ef7eb2e8f9f7 530 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
<> 144:ef7eb2e8f9f7 531 }
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 534 hlptim->State= HAL_LPTIM_STATE_READY;
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 /* Return function status */
<> 144:ef7eb2e8f9f7 537 return HAL_OK;
<> 144:ef7eb2e8f9f7 538 }
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 /**
<> 144:ef7eb2e8f9f7 541 * @brief Start the LPTIM One pulse generation.
<> 144:ef7eb2e8f9f7 542 * @param hlptim : LPTIM handle
<> 144:ef7eb2e8f9f7 543 * @param Period : Specifies the Autoreload value.
<> 144:ef7eb2e8f9f7 544 * This parameter must be a value between 0x0000 and 0xFFFF.
<> 144:ef7eb2e8f9f7 545 * @param Pulse : Specifies the compare value.
<> 144:ef7eb2e8f9f7 546 * This parameter must be a value between 0x0000 and 0xFFFF.
<> 144:ef7eb2e8f9f7 547 * @retval HAL status
<> 144:ef7eb2e8f9f7 548 */
<> 144:ef7eb2e8f9f7 549 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
<> 144:ef7eb2e8f9f7 550 {
<> 144:ef7eb2e8f9f7 551 /* Check the parameters */
<> 144:ef7eb2e8f9f7 552 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
<> 144:ef7eb2e8f9f7 553 assert_param(IS_LPTIM_PERIOD(Period));
<> 144:ef7eb2e8f9f7 554 assert_param(IS_LPTIM_PULSE(Pulse));
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 /* Set the LPTIM state */
<> 144:ef7eb2e8f9f7 557 hlptim->State= HAL_LPTIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559 /* Reset WAVE bit to set one pulse mode */
<> 144:ef7eb2e8f9f7 560 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 563 __HAL_LPTIM_ENABLE(hlptim);
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 /* Load the period value in the autoreload register */
<> 144:ef7eb2e8f9f7 566 __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 /* Load the pulse value in the compare register */
<> 144:ef7eb2e8f9f7 569 __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 /* Start timer in continuous mode */
<> 144:ef7eb2e8f9f7 572 __HAL_LPTIM_START_SINGLE(hlptim);
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 575 hlptim->State= HAL_LPTIM_STATE_READY;
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 /* Return function status */
<> 144:ef7eb2e8f9f7 578 return HAL_OK;
<> 144:ef7eb2e8f9f7 579 }
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 /**
<> 144:ef7eb2e8f9f7 582 * @brief Stop the LPTIM One pulse generation.
<> 144:ef7eb2e8f9f7 583 * @param hlptim : LPTIM handle
<> 144:ef7eb2e8f9f7 584 * @retval HAL status
<> 144:ef7eb2e8f9f7 585 */
<> 144:ef7eb2e8f9f7 586 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)
<> 144:ef7eb2e8f9f7 587 {
<> 144:ef7eb2e8f9f7 588 /* Check the parameters */
<> 144:ef7eb2e8f9f7 589 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 /* Set the LPTIM state */
<> 144:ef7eb2e8f9f7 592 hlptim->State= HAL_LPTIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 595 __HAL_LPTIM_DISABLE(hlptim);
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 598 hlptim->State= HAL_LPTIM_STATE_READY;
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600 /* Return function status */
<> 144:ef7eb2e8f9f7 601 return HAL_OK;
<> 144:ef7eb2e8f9f7 602 }
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 /**
<> 144:ef7eb2e8f9f7 605 * @brief Start the LPTIM One pulse generation in interrupt mode.
<> 144:ef7eb2e8f9f7 606 * @param hlptim : LPTIM handle
<> 144:ef7eb2e8f9f7 607 * @param Period : Specifies the Autoreload value.
<> 144:ef7eb2e8f9f7 608 * This parameter must be a value between 0x0000 and 0xFFFF.
<> 144:ef7eb2e8f9f7 609 * @param Pulse : Specifies the compare value.
<> 144:ef7eb2e8f9f7 610 * This parameter must be a value between 0x0000 and 0xFFFF.
<> 144:ef7eb2e8f9f7 611 * @retval HAL status
<> 144:ef7eb2e8f9f7 612 */
<> 144:ef7eb2e8f9f7 613 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
<> 144:ef7eb2e8f9f7 614 {
<> 144:ef7eb2e8f9f7 615 /* Check the parameters */
<> 144:ef7eb2e8f9f7 616 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
<> 144:ef7eb2e8f9f7 617 assert_param(IS_LPTIM_PERIOD(Period));
<> 144:ef7eb2e8f9f7 618 assert_param(IS_LPTIM_PULSE(Pulse));
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 /* Set the LPTIM state */
<> 144:ef7eb2e8f9f7 621 hlptim->State= HAL_LPTIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623 /* Reset WAVE bit to set one pulse mode */
<> 144:ef7eb2e8f9f7 624 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
<> 144:ef7eb2e8f9f7 625
<> 144:ef7eb2e8f9f7 626 /* Enable Autoreload write complete interrupt */
<> 144:ef7eb2e8f9f7 627 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 /* Enable Compare write complete interrupt */
<> 144:ef7eb2e8f9f7 630 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 /* Enable Autoreload match interrupt */
<> 144:ef7eb2e8f9f7 633 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 /* Enable Compare match interrupt */
<> 144:ef7eb2e8f9f7 636 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
<> 144:ef7eb2e8f9f7 637
<> 144:ef7eb2e8f9f7 638 /* If external trigger source is used, then enable external trigger interrupt */
<> 144:ef7eb2e8f9f7 639 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
<> 144:ef7eb2e8f9f7 640 {
<> 144:ef7eb2e8f9f7 641 /* Enable external trigger interrupt */
<> 144:ef7eb2e8f9f7 642 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
<> 144:ef7eb2e8f9f7 643 }
<> 144:ef7eb2e8f9f7 644
<> 144:ef7eb2e8f9f7 645 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 646 __HAL_LPTIM_ENABLE(hlptim);
<> 144:ef7eb2e8f9f7 647
<> 144:ef7eb2e8f9f7 648 /* Load the period value in the autoreload register */
<> 144:ef7eb2e8f9f7 649 __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651 /* Load the pulse value in the compare register */
<> 144:ef7eb2e8f9f7 652 __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
<> 144:ef7eb2e8f9f7 653
<> 144:ef7eb2e8f9f7 654 /* Start timer in continuous mode */
<> 144:ef7eb2e8f9f7 655 __HAL_LPTIM_START_SINGLE(hlptim);
<> 144:ef7eb2e8f9f7 656
<> 144:ef7eb2e8f9f7 657 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 658 hlptim->State= HAL_LPTIM_STATE_READY;
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660 /* Return function status */
<> 144:ef7eb2e8f9f7 661 return HAL_OK;
<> 144:ef7eb2e8f9f7 662 }
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 /**
<> 144:ef7eb2e8f9f7 665 * @brief Stop the LPTIM One pulse generation in interrupt mode.
<> 144:ef7eb2e8f9f7 666 * @param hlptim : LPTIM handle
<> 144:ef7eb2e8f9f7 667 * @retval HAL status
<> 144:ef7eb2e8f9f7 668 */
<> 144:ef7eb2e8f9f7 669 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)
<> 144:ef7eb2e8f9f7 670 {
<> 144:ef7eb2e8f9f7 671 /* Check the parameters */
<> 144:ef7eb2e8f9f7 672 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
<> 144:ef7eb2e8f9f7 673
<> 144:ef7eb2e8f9f7 674 /* Set the LPTIM state */
<> 144:ef7eb2e8f9f7 675 hlptim->State= HAL_LPTIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 678 __HAL_LPTIM_DISABLE(hlptim);
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680 /* Disable Autoreload write complete interrupt */
<> 144:ef7eb2e8f9f7 681 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683 /* Disable Compare write complete interrupt */
<> 144:ef7eb2e8f9f7 684 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
<> 144:ef7eb2e8f9f7 685
<> 144:ef7eb2e8f9f7 686 /* Disable Autoreload match interrupt */
<> 144:ef7eb2e8f9f7 687 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
<> 144:ef7eb2e8f9f7 688
<> 144:ef7eb2e8f9f7 689 /* Disable Compare match interrupt */
<> 144:ef7eb2e8f9f7 690 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
<> 144:ef7eb2e8f9f7 691
<> 144:ef7eb2e8f9f7 692 /* If external trigger source is used, then disable external trigger interrupt */
<> 144:ef7eb2e8f9f7 693 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
<> 144:ef7eb2e8f9f7 694 {
<> 144:ef7eb2e8f9f7 695 /* Disable external trigger interrupt */
<> 144:ef7eb2e8f9f7 696 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
<> 144:ef7eb2e8f9f7 697 }
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 700 hlptim->State= HAL_LPTIM_STATE_READY;
<> 144:ef7eb2e8f9f7 701
<> 144:ef7eb2e8f9f7 702 /* Return function status */
<> 144:ef7eb2e8f9f7 703 return HAL_OK;
<> 144:ef7eb2e8f9f7 704 }
<> 144:ef7eb2e8f9f7 705
<> 144:ef7eb2e8f9f7 706 /**
<> 144:ef7eb2e8f9f7 707 * @brief Start the LPTIM in Set once mode.
<> 144:ef7eb2e8f9f7 708 * @param hlptim : LPTIM handle
<> 144:ef7eb2e8f9f7 709 * @param Period : Specifies the Autoreload value.
<> 144:ef7eb2e8f9f7 710 * This parameter must be a value between 0x0000 and 0xFFFF.
<> 144:ef7eb2e8f9f7 711 * @param Pulse : Specifies the compare value.
<> 144:ef7eb2e8f9f7 712 * This parameter must be a value between 0x0000 and 0xFFFF.
<> 144:ef7eb2e8f9f7 713 * @retval HAL status
<> 144:ef7eb2e8f9f7 714 */
<> 144:ef7eb2e8f9f7 715 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
<> 144:ef7eb2e8f9f7 716 {
<> 144:ef7eb2e8f9f7 717 /* Check the parameters */
<> 144:ef7eb2e8f9f7 718 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
<> 144:ef7eb2e8f9f7 719 assert_param(IS_LPTIM_PERIOD(Period));
<> 144:ef7eb2e8f9f7 720 assert_param(IS_LPTIM_PULSE(Pulse));
<> 144:ef7eb2e8f9f7 721
<> 144:ef7eb2e8f9f7 722 /* Set the LPTIM state */
<> 144:ef7eb2e8f9f7 723 hlptim->State= HAL_LPTIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 724
<> 144:ef7eb2e8f9f7 725 /* Set WAVE bit to enable the set once mode */
<> 144:ef7eb2e8f9f7 726 hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
<> 144:ef7eb2e8f9f7 727
<> 144:ef7eb2e8f9f7 728 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 729 __HAL_LPTIM_ENABLE(hlptim);
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 /* Load the period value in the autoreload register */
<> 144:ef7eb2e8f9f7 732 __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
<> 144:ef7eb2e8f9f7 733
<> 144:ef7eb2e8f9f7 734 /* Load the pulse value in the compare register */
<> 144:ef7eb2e8f9f7 735 __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
<> 144:ef7eb2e8f9f7 736
<> 144:ef7eb2e8f9f7 737 /* Start timer in continuous mode */
<> 144:ef7eb2e8f9f7 738 __HAL_LPTIM_START_SINGLE(hlptim);
<> 144:ef7eb2e8f9f7 739
<> 144:ef7eb2e8f9f7 740 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 741 hlptim->State= HAL_LPTIM_STATE_READY;
<> 144:ef7eb2e8f9f7 742
<> 144:ef7eb2e8f9f7 743 /* Return function status */
<> 144:ef7eb2e8f9f7 744 return HAL_OK;
<> 144:ef7eb2e8f9f7 745 }
<> 144:ef7eb2e8f9f7 746
<> 144:ef7eb2e8f9f7 747 /**
<> 144:ef7eb2e8f9f7 748 * @brief Stop the LPTIM Set once mode.
<> 144:ef7eb2e8f9f7 749 * @param hlptim : LPTIM handle
<> 144:ef7eb2e8f9f7 750 * @retval HAL status
<> 144:ef7eb2e8f9f7 751 */
<> 144:ef7eb2e8f9f7 752 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim)
<> 144:ef7eb2e8f9f7 753 {
<> 144:ef7eb2e8f9f7 754 /* Check the parameters */
<> 144:ef7eb2e8f9f7 755 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
<> 144:ef7eb2e8f9f7 756
<> 144:ef7eb2e8f9f7 757 /* Set the LPTIM state */
<> 144:ef7eb2e8f9f7 758 hlptim->State= HAL_LPTIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 759
<> 144:ef7eb2e8f9f7 760 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 761 __HAL_LPTIM_DISABLE(hlptim);
<> 144:ef7eb2e8f9f7 762
<> 144:ef7eb2e8f9f7 763 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 764 hlptim->State= HAL_LPTIM_STATE_READY;
<> 144:ef7eb2e8f9f7 765
<> 144:ef7eb2e8f9f7 766 /* Return function status */
<> 144:ef7eb2e8f9f7 767 return HAL_OK;
<> 144:ef7eb2e8f9f7 768 }
<> 144:ef7eb2e8f9f7 769
<> 144:ef7eb2e8f9f7 770 /**
<> 144:ef7eb2e8f9f7 771 * @brief Start the LPTIM Set once mode in interrupt mode.
<> 144:ef7eb2e8f9f7 772 * @param hlptim : LPTIM handle
<> 144:ef7eb2e8f9f7 773 * @param Period : Specifies the Autoreload value.
<> 144:ef7eb2e8f9f7 774 * This parameter must be a value between 0x0000 and 0xFFFF.
<> 144:ef7eb2e8f9f7 775 * @param Pulse : Specifies the compare value.
<> 144:ef7eb2e8f9f7 776 * This parameter must be a value between 0x0000 and 0xFFFF.
<> 144:ef7eb2e8f9f7 777 * @retval HAL status
<> 144:ef7eb2e8f9f7 778 */
<> 144:ef7eb2e8f9f7 779 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
<> 144:ef7eb2e8f9f7 780 {
<> 144:ef7eb2e8f9f7 781 /* Check the parameters */
<> 144:ef7eb2e8f9f7 782 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
<> 144:ef7eb2e8f9f7 783 assert_param(IS_LPTIM_PERIOD(Period));
<> 144:ef7eb2e8f9f7 784 assert_param(IS_LPTIM_PULSE(Pulse));
<> 144:ef7eb2e8f9f7 785
<> 144:ef7eb2e8f9f7 786 /* Set the LPTIM state */
<> 144:ef7eb2e8f9f7 787 hlptim->State= HAL_LPTIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 788
<> 144:ef7eb2e8f9f7 789 /* Set WAVE bit to enable the set once mode */
<> 144:ef7eb2e8f9f7 790 hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
<> 144:ef7eb2e8f9f7 791
<> 144:ef7eb2e8f9f7 792 /* Enable Autoreload write complete interrupt */
<> 144:ef7eb2e8f9f7 793 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
<> 144:ef7eb2e8f9f7 794
<> 144:ef7eb2e8f9f7 795 /* Enable Compare write complete interrupt */
<> 144:ef7eb2e8f9f7 796 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
<> 144:ef7eb2e8f9f7 797
<> 144:ef7eb2e8f9f7 798 /* Enable Autoreload match interrupt */
<> 144:ef7eb2e8f9f7 799 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
<> 144:ef7eb2e8f9f7 800
<> 144:ef7eb2e8f9f7 801 /* Enable Compare match interrupt */
<> 144:ef7eb2e8f9f7 802 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
<> 144:ef7eb2e8f9f7 803
<> 144:ef7eb2e8f9f7 804 /* If external trigger source is used, then enable external trigger interrupt */
<> 144:ef7eb2e8f9f7 805 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
<> 144:ef7eb2e8f9f7 806 {
<> 144:ef7eb2e8f9f7 807 /* Enable external trigger interrupt */
<> 144:ef7eb2e8f9f7 808 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
<> 144:ef7eb2e8f9f7 809 }
<> 144:ef7eb2e8f9f7 810
<> 144:ef7eb2e8f9f7 811 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 812 __HAL_LPTIM_ENABLE(hlptim);
<> 144:ef7eb2e8f9f7 813
<> 144:ef7eb2e8f9f7 814 /* Load the period value in the autoreload register */
<> 144:ef7eb2e8f9f7 815 __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
<> 144:ef7eb2e8f9f7 816
<> 144:ef7eb2e8f9f7 817 /* Load the pulse value in the compare register */
<> 144:ef7eb2e8f9f7 818 __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
<> 144:ef7eb2e8f9f7 819
<> 144:ef7eb2e8f9f7 820 /* Start timer in continuous mode */
<> 144:ef7eb2e8f9f7 821 __HAL_LPTIM_START_SINGLE(hlptim);
<> 144:ef7eb2e8f9f7 822
<> 144:ef7eb2e8f9f7 823 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 824 hlptim->State= HAL_LPTIM_STATE_READY;
<> 144:ef7eb2e8f9f7 825
<> 144:ef7eb2e8f9f7 826 /* Return function status */
<> 144:ef7eb2e8f9f7 827 return HAL_OK;
<> 144:ef7eb2e8f9f7 828 }
<> 144:ef7eb2e8f9f7 829
<> 144:ef7eb2e8f9f7 830 /**
<> 144:ef7eb2e8f9f7 831 * @brief Stop the LPTIM Set once mode in interrupt mode.
<> 144:ef7eb2e8f9f7 832 * @param hlptim : LPTIM handle
<> 144:ef7eb2e8f9f7 833 * @retval HAL status
<> 144:ef7eb2e8f9f7 834 */
<> 144:ef7eb2e8f9f7 835 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)
<> 144:ef7eb2e8f9f7 836 {
<> 144:ef7eb2e8f9f7 837 /* Check the parameters */
<> 144:ef7eb2e8f9f7 838 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
<> 144:ef7eb2e8f9f7 839
<> 144:ef7eb2e8f9f7 840 /* Set the LPTIM state */
<> 144:ef7eb2e8f9f7 841 hlptim->State= HAL_LPTIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 842
<> 144:ef7eb2e8f9f7 843 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 844 __HAL_LPTIM_DISABLE(hlptim);
<> 144:ef7eb2e8f9f7 845
<> 144:ef7eb2e8f9f7 846 /* Disable Autoreload write complete interrupt */
<> 144:ef7eb2e8f9f7 847 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
<> 144:ef7eb2e8f9f7 848
<> 144:ef7eb2e8f9f7 849 /* Disable Compare write complete interrupt */
<> 144:ef7eb2e8f9f7 850 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
<> 144:ef7eb2e8f9f7 851
<> 144:ef7eb2e8f9f7 852 /* Disable Autoreload match interrupt */
<> 144:ef7eb2e8f9f7 853 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
<> 144:ef7eb2e8f9f7 854
<> 144:ef7eb2e8f9f7 855 /* Disable Compare match interrupt */
<> 144:ef7eb2e8f9f7 856 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
<> 144:ef7eb2e8f9f7 857
<> 144:ef7eb2e8f9f7 858 /* If external trigger source is used, then disable external trigger interrupt */
<> 144:ef7eb2e8f9f7 859 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
<> 144:ef7eb2e8f9f7 860 {
<> 144:ef7eb2e8f9f7 861 /* Disable external trigger interrupt */
<> 144:ef7eb2e8f9f7 862 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
<> 144:ef7eb2e8f9f7 863 }
<> 144:ef7eb2e8f9f7 864
<> 144:ef7eb2e8f9f7 865 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 866 hlptim->State= HAL_LPTIM_STATE_READY;
<> 144:ef7eb2e8f9f7 867
<> 144:ef7eb2e8f9f7 868 /* Return function status */
<> 144:ef7eb2e8f9f7 869 return HAL_OK;
<> 144:ef7eb2e8f9f7 870 }
<> 144:ef7eb2e8f9f7 871
<> 144:ef7eb2e8f9f7 872 /**
<> 144:ef7eb2e8f9f7 873 * @brief Start the Encoder interface.
<> 144:ef7eb2e8f9f7 874 * @param hlptim : LPTIM handle
<> 144:ef7eb2e8f9f7 875 * @param Period : Specifies the Autoreload value.
<> 144:ef7eb2e8f9f7 876 * This parameter must be a value between 0x0000 and 0xFFFF.
<> 144:ef7eb2e8f9f7 877 * @retval HAL status
<> 144:ef7eb2e8f9f7 878 */
<> 144:ef7eb2e8f9f7 879 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
<> 144:ef7eb2e8f9f7 880 {
<> 144:ef7eb2e8f9f7 881 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 882 uint32_t tmpcfgr;
<> 144:ef7eb2e8f9f7 883
<> 144:ef7eb2e8f9f7 884 /* Check the parameters */
<> 144:ef7eb2e8f9f7 885 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
<> 144:ef7eb2e8f9f7 886 assert_param(IS_LPTIM_PERIOD(Period));
<> 144:ef7eb2e8f9f7 887 assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
<> 144:ef7eb2e8f9f7 888 assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
<> 144:ef7eb2e8f9f7 889 assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
<> 144:ef7eb2e8f9f7 890
<> 144:ef7eb2e8f9f7 891 /* Encoder feature is only available for LPTIM1 instance */
<> 144:ef7eb2e8f9f7 892 if (hlptim->Instance == LPTIM1)
<> 144:ef7eb2e8f9f7 893 {
<> 144:ef7eb2e8f9f7 894 /* Set the LPTIM state */
<> 144:ef7eb2e8f9f7 895 hlptim->State= HAL_LPTIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 /* Get the LPTIMx CFGR value */
<> 144:ef7eb2e8f9f7 898 tmpcfgr = hlptim->Instance->CFGR;
<> 144:ef7eb2e8f9f7 899
<> 144:ef7eb2e8f9f7 900 /* Clear CKPOL bits */
<> 144:ef7eb2e8f9f7 901 tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
<> 144:ef7eb2e8f9f7 902
<> 144:ef7eb2e8f9f7 903 /* Set Input polarity */
<> 144:ef7eb2e8f9f7 904 tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity;
<> 144:ef7eb2e8f9f7 905
<> 144:ef7eb2e8f9f7 906 /* Write to LPTIMx CFGR */
<> 144:ef7eb2e8f9f7 907 hlptim->Instance->CFGR = tmpcfgr;
<> 144:ef7eb2e8f9f7 908
<> 144:ef7eb2e8f9f7 909 /* Set ENC bit to enable the encoder interface */
<> 144:ef7eb2e8f9f7 910 hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
<> 144:ef7eb2e8f9f7 911
<> 144:ef7eb2e8f9f7 912 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 913 __HAL_LPTIM_ENABLE(hlptim);
<> 144:ef7eb2e8f9f7 914
<> 144:ef7eb2e8f9f7 915 /* Load the period value in the autoreload register */
<> 144:ef7eb2e8f9f7 916 __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
<> 144:ef7eb2e8f9f7 917
<> 144:ef7eb2e8f9f7 918 /* Start timer in continuous mode */
<> 144:ef7eb2e8f9f7 919 __HAL_LPTIM_START_CONTINUOUS(hlptim);
<> 144:ef7eb2e8f9f7 920
<> 144:ef7eb2e8f9f7 921 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 922 hlptim->State= HAL_LPTIM_STATE_READY;
<> 144:ef7eb2e8f9f7 923 }
<> 144:ef7eb2e8f9f7 924 else
<> 144:ef7eb2e8f9f7 925 {
<> 144:ef7eb2e8f9f7 926 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 927 }
<> 144:ef7eb2e8f9f7 928
<> 144:ef7eb2e8f9f7 929 /* Return function status */
<> 144:ef7eb2e8f9f7 930 return status;
<> 144:ef7eb2e8f9f7 931 }
<> 144:ef7eb2e8f9f7 932
<> 144:ef7eb2e8f9f7 933 /**
<> 144:ef7eb2e8f9f7 934 * @brief Stop the Encoder interface.
<> 144:ef7eb2e8f9f7 935 * @param hlptim : LPTIM handle
<> 144:ef7eb2e8f9f7 936 * @retval HAL status
<> 144:ef7eb2e8f9f7 937 */
<> 144:ef7eb2e8f9f7 938 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
<> 144:ef7eb2e8f9f7 939 {
<> 144:ef7eb2e8f9f7 940 /* Check the parameters */
<> 144:ef7eb2e8f9f7 941 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
<> 144:ef7eb2e8f9f7 942
<> 144:ef7eb2e8f9f7 943 /* Set the LPTIM state */
<> 144:ef7eb2e8f9f7 944 hlptim->State= HAL_LPTIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 945
<> 144:ef7eb2e8f9f7 946 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 947 __HAL_LPTIM_DISABLE(hlptim);
<> 144:ef7eb2e8f9f7 948
<> 144:ef7eb2e8f9f7 949 /* Reset ENC bit to disable the encoder interface */
<> 144:ef7eb2e8f9f7 950 hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
<> 144:ef7eb2e8f9f7 951
<> 144:ef7eb2e8f9f7 952 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 953 hlptim->State= HAL_LPTIM_STATE_READY;
<> 144:ef7eb2e8f9f7 954
<> 144:ef7eb2e8f9f7 955 /* Return function status */
<> 144:ef7eb2e8f9f7 956 return HAL_OK;
<> 144:ef7eb2e8f9f7 957 }
<> 144:ef7eb2e8f9f7 958
<> 144:ef7eb2e8f9f7 959 /**
<> 144:ef7eb2e8f9f7 960 * @brief Start the Encoder interface in interrupt mode.
<> 144:ef7eb2e8f9f7 961 * @param hlptim : LPTIM handle
<> 144:ef7eb2e8f9f7 962 * @param Period : Specifies the Autoreload value.
<> 144:ef7eb2e8f9f7 963 * This parameter must be a value between 0x0000 and 0xFFFF.
<> 144:ef7eb2e8f9f7 964 * @retval HAL status
<> 144:ef7eb2e8f9f7 965 */
<> 144:ef7eb2e8f9f7 966 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
<> 144:ef7eb2e8f9f7 967 {
<> 144:ef7eb2e8f9f7 968 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 969 uint32_t tmpcfgr;
<> 144:ef7eb2e8f9f7 970
<> 144:ef7eb2e8f9f7 971 /* Check the parameters */
<> 144:ef7eb2e8f9f7 972 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
<> 144:ef7eb2e8f9f7 973 assert_param(IS_LPTIM_PERIOD(Period));
<> 144:ef7eb2e8f9f7 974 assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
<> 144:ef7eb2e8f9f7 975 assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
<> 144:ef7eb2e8f9f7 976 assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
<> 144:ef7eb2e8f9f7 977
<> 144:ef7eb2e8f9f7 978 /* Encoder feature is only available for LPTIM1 instance */
<> 144:ef7eb2e8f9f7 979 if (hlptim->Instance == LPTIM1)
<> 144:ef7eb2e8f9f7 980 {
<> 144:ef7eb2e8f9f7 981 /* Set the LPTIM state */
<> 144:ef7eb2e8f9f7 982 hlptim->State= HAL_LPTIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 983
<> 144:ef7eb2e8f9f7 984 /* Configure edge sensitivity for encoder mode */
<> 144:ef7eb2e8f9f7 985 /* Get the LPTIMx CFGR value */
<> 144:ef7eb2e8f9f7 986 tmpcfgr = hlptim->Instance->CFGR;
<> 144:ef7eb2e8f9f7 987
<> 144:ef7eb2e8f9f7 988 /* Clear CKPOL bits */
<> 144:ef7eb2e8f9f7 989 tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
<> 144:ef7eb2e8f9f7 990
<> 144:ef7eb2e8f9f7 991 /* Set Input polarity */
<> 144:ef7eb2e8f9f7 992 tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity;
<> 144:ef7eb2e8f9f7 993
<> 144:ef7eb2e8f9f7 994 /* Write to LPTIMx CFGR */
<> 144:ef7eb2e8f9f7 995 hlptim->Instance->CFGR = tmpcfgr;
<> 144:ef7eb2e8f9f7 996
<> 144:ef7eb2e8f9f7 997 /* Set ENC bit to enable the encoder interface */
<> 144:ef7eb2e8f9f7 998 hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
<> 144:ef7eb2e8f9f7 999
<> 144:ef7eb2e8f9f7 1000 /* Enable "switch to down direction" interrupt */
<> 144:ef7eb2e8f9f7 1001 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN);
<> 144:ef7eb2e8f9f7 1002
<> 144:ef7eb2e8f9f7 1003 /* Enable "switch to up direction" interrupt */
<> 144:ef7eb2e8f9f7 1004 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP);
<> 144:ef7eb2e8f9f7 1005
<> 144:ef7eb2e8f9f7 1006 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1007 __HAL_LPTIM_ENABLE(hlptim);
<> 144:ef7eb2e8f9f7 1008
<> 144:ef7eb2e8f9f7 1009 /* Load the period value in the autoreload register */
<> 144:ef7eb2e8f9f7 1010 __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
<> 144:ef7eb2e8f9f7 1011
<> 144:ef7eb2e8f9f7 1012 /* Start timer in continuous mode */
<> 144:ef7eb2e8f9f7 1013 __HAL_LPTIM_START_CONTINUOUS(hlptim);
<> 144:ef7eb2e8f9f7 1014
<> 144:ef7eb2e8f9f7 1015 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 1016 hlptim->State= HAL_LPTIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1017 }
<> 144:ef7eb2e8f9f7 1018 else
<> 144:ef7eb2e8f9f7 1019 {
<> 144:ef7eb2e8f9f7 1020 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1021 }
<> 144:ef7eb2e8f9f7 1022
<> 144:ef7eb2e8f9f7 1023 /* Return function status */
<> 144:ef7eb2e8f9f7 1024 return status;
<> 144:ef7eb2e8f9f7 1025 }
<> 144:ef7eb2e8f9f7 1026
<> 144:ef7eb2e8f9f7 1027 /**
<> 144:ef7eb2e8f9f7 1028 * @brief Stop the Encoder interface in interrupt mode.
<> 144:ef7eb2e8f9f7 1029 * @param hlptim : LPTIM handle
<> 144:ef7eb2e8f9f7 1030 * @retval HAL status
<> 144:ef7eb2e8f9f7 1031 */
<> 144:ef7eb2e8f9f7 1032 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
<> 144:ef7eb2e8f9f7 1033 {
<> 144:ef7eb2e8f9f7 1034 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1035 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
<> 144:ef7eb2e8f9f7 1036
<> 144:ef7eb2e8f9f7 1037 /* Set the LPTIM state */
<> 144:ef7eb2e8f9f7 1038 hlptim->State= HAL_LPTIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1039
<> 144:ef7eb2e8f9f7 1040 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1041 __HAL_LPTIM_DISABLE(hlptim);
<> 144:ef7eb2e8f9f7 1042
<> 144:ef7eb2e8f9f7 1043 /* Reset ENC bit to disable the encoder interface */
<> 144:ef7eb2e8f9f7 1044 hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
<> 144:ef7eb2e8f9f7 1045
<> 144:ef7eb2e8f9f7 1046 /* Disable "switch to down direction" interrupt */
<> 144:ef7eb2e8f9f7 1047 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_DOWN);
<> 144:ef7eb2e8f9f7 1048
<> 144:ef7eb2e8f9f7 1049 /* Disable "switch to up direction" interrupt */
<> 144:ef7eb2e8f9f7 1050 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP);
<> 144:ef7eb2e8f9f7 1051
<> 144:ef7eb2e8f9f7 1052 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 1053 hlptim->State= HAL_LPTIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1054
<> 144:ef7eb2e8f9f7 1055 /* Return function status */
<> 144:ef7eb2e8f9f7 1056 return HAL_OK;
<> 144:ef7eb2e8f9f7 1057 }
<> 144:ef7eb2e8f9f7 1058
<> 144:ef7eb2e8f9f7 1059 /**
<> 144:ef7eb2e8f9f7 1060 * @brief Start the Timeout function.
<> 144:ef7eb2e8f9f7 1061 * @note The first trigger event will start the timer, any successive
<> 144:ef7eb2e8f9f7 1062 * trigger event will reset the counter and the timer restarts.
<> 144:ef7eb2e8f9f7 1063 * @param hlptim : LPTIM handle
<> 144:ef7eb2e8f9f7 1064 * @param Period : Specifies the Autoreload value.
<> 144:ef7eb2e8f9f7 1065 * This parameter must be a value between 0x0000 and 0xFFFF.
<> 144:ef7eb2e8f9f7 1066 * @param Timeout : Specifies the TimeOut value to rest the counter.
<> 144:ef7eb2e8f9f7 1067 * This parameter must be a value between 0x0000 and 0xFFFF.
<> 144:ef7eb2e8f9f7 1068 * @retval HAL status
<> 144:ef7eb2e8f9f7 1069 */
<> 144:ef7eb2e8f9f7 1070 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1071 {
<> 144:ef7eb2e8f9f7 1072 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1073 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
<> 144:ef7eb2e8f9f7 1074 assert_param(IS_LPTIM_PERIOD(Period));
<> 144:ef7eb2e8f9f7 1075 assert_param(IS_LPTIM_PULSE(Timeout));
<> 144:ef7eb2e8f9f7 1076
<> 144:ef7eb2e8f9f7 1077 /* Set the LPTIM state */
<> 144:ef7eb2e8f9f7 1078 hlptim->State= HAL_LPTIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1079
<> 144:ef7eb2e8f9f7 1080 /* Set TIMOUT bit to enable the timeout function */
<> 144:ef7eb2e8f9f7 1081 hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
<> 144:ef7eb2e8f9f7 1082
<> 144:ef7eb2e8f9f7 1083 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1084 __HAL_LPTIM_ENABLE(hlptim);
<> 144:ef7eb2e8f9f7 1085
<> 144:ef7eb2e8f9f7 1086 /* Load the period value in the autoreload register */
<> 144:ef7eb2e8f9f7 1087 __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
<> 144:ef7eb2e8f9f7 1088
<> 144:ef7eb2e8f9f7 1089 /* Load the Timeout value in the compare register */
<> 144:ef7eb2e8f9f7 1090 __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
<> 144:ef7eb2e8f9f7 1091
<> 144:ef7eb2e8f9f7 1092 /* Start timer in continuous mode */
<> 144:ef7eb2e8f9f7 1093 __HAL_LPTIM_START_CONTINUOUS(hlptim);
<> 144:ef7eb2e8f9f7 1094
<> 144:ef7eb2e8f9f7 1095 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 1096 hlptim->State= HAL_LPTIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1097
<> 144:ef7eb2e8f9f7 1098 /* Return function status */
<> 144:ef7eb2e8f9f7 1099 return HAL_OK;
<> 144:ef7eb2e8f9f7 1100 }
<> 144:ef7eb2e8f9f7 1101
<> 144:ef7eb2e8f9f7 1102 /**
<> 144:ef7eb2e8f9f7 1103 * @brief Stop the Timeout function.
<> 144:ef7eb2e8f9f7 1104 * @param hlptim : LPTIM handle
<> 144:ef7eb2e8f9f7 1105 * @retval HAL status
<> 144:ef7eb2e8f9f7 1106 */
<> 144:ef7eb2e8f9f7 1107 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
<> 144:ef7eb2e8f9f7 1108 {
<> 144:ef7eb2e8f9f7 1109 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1110 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
<> 144:ef7eb2e8f9f7 1111
<> 144:ef7eb2e8f9f7 1112 /* Set the LPTIM state */
<> 144:ef7eb2e8f9f7 1113 hlptim->State= HAL_LPTIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1114
<> 144:ef7eb2e8f9f7 1115 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1116 __HAL_LPTIM_DISABLE(hlptim);
<> 144:ef7eb2e8f9f7 1117
<> 144:ef7eb2e8f9f7 1118 /* Reset TIMOUT bit to enable the timeout function */
<> 144:ef7eb2e8f9f7 1119 hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
<> 144:ef7eb2e8f9f7 1120
<> 144:ef7eb2e8f9f7 1121 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 1122 hlptim->State= HAL_LPTIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1123
<> 144:ef7eb2e8f9f7 1124 /* Return function status */
<> 144:ef7eb2e8f9f7 1125 return HAL_OK;
<> 144:ef7eb2e8f9f7 1126 }
<> 144:ef7eb2e8f9f7 1127
<> 144:ef7eb2e8f9f7 1128 /**
<> 144:ef7eb2e8f9f7 1129 * @brief Start the Timeout function in interrupt mode.
<> 144:ef7eb2e8f9f7 1130 * @note The first trigger event will start the timer, any successive
<> 144:ef7eb2e8f9f7 1131 * trigger event will reset the counter and the timer restarts.
<> 144:ef7eb2e8f9f7 1132 * @param hlptim : LPTIM handle
<> 144:ef7eb2e8f9f7 1133 * @param Period : Specifies the Autoreload value.
<> 144:ef7eb2e8f9f7 1134 * This parameter must be a value between 0x0000 and 0xFFFF.
<> 144:ef7eb2e8f9f7 1135 * @param Timeout : Specifies the TimeOut value to rest the counter.
<> 144:ef7eb2e8f9f7 1136 * This parameter must be a value between 0x0000 and 0xFFFF.
<> 144:ef7eb2e8f9f7 1137 * @retval HAL status
<> 144:ef7eb2e8f9f7 1138 */
<> 144:ef7eb2e8f9f7 1139 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1140 {
<> 144:ef7eb2e8f9f7 1141 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1142 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
<> 144:ef7eb2e8f9f7 1143 assert_param(IS_LPTIM_PERIOD(Period));
<> 144:ef7eb2e8f9f7 1144 assert_param(IS_LPTIM_PULSE(Timeout));
<> 144:ef7eb2e8f9f7 1145
<> 144:ef7eb2e8f9f7 1146 /* Set the LPTIM state */
<> 144:ef7eb2e8f9f7 1147 hlptim->State= HAL_LPTIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1148
<> 144:ef7eb2e8f9f7 1149 /* Set TIMOUT bit to enable the timeout function */
<> 144:ef7eb2e8f9f7 1150 hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
<> 144:ef7eb2e8f9f7 1151
<> 144:ef7eb2e8f9f7 1152 /* Enable Compare match interrupt */
<> 144:ef7eb2e8f9f7 1153 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
<> 144:ef7eb2e8f9f7 1154
<> 144:ef7eb2e8f9f7 1155 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1156 __HAL_LPTIM_ENABLE(hlptim);
<> 144:ef7eb2e8f9f7 1157
<> 144:ef7eb2e8f9f7 1158 /* Load the period value in the autoreload register */
<> 144:ef7eb2e8f9f7 1159 __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
<> 144:ef7eb2e8f9f7 1160
<> 144:ef7eb2e8f9f7 1161 /* Load the Timeout value in the compare register */
<> 144:ef7eb2e8f9f7 1162 __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
<> 144:ef7eb2e8f9f7 1163
<> 144:ef7eb2e8f9f7 1164 /* Start timer in continuous mode */
<> 144:ef7eb2e8f9f7 1165 __HAL_LPTIM_START_CONTINUOUS(hlptim);
<> 144:ef7eb2e8f9f7 1166
<> 144:ef7eb2e8f9f7 1167 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 1168 hlptim->State= HAL_LPTIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1169
<> 144:ef7eb2e8f9f7 1170 /* Return function status */
<> 144:ef7eb2e8f9f7 1171 return HAL_OK;
<> 144:ef7eb2e8f9f7 1172 }
<> 144:ef7eb2e8f9f7 1173
<> 144:ef7eb2e8f9f7 1174 /**
<> 144:ef7eb2e8f9f7 1175 * @brief Stop the Timeout function in interrupt mode.
<> 144:ef7eb2e8f9f7 1176 * @param hlptim : LPTIM handle
<> 144:ef7eb2e8f9f7 1177 * @retval HAL status
<> 144:ef7eb2e8f9f7 1178 */
<> 144:ef7eb2e8f9f7 1179 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
<> 144:ef7eb2e8f9f7 1180 {
<> 144:ef7eb2e8f9f7 1181 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1182 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
<> 144:ef7eb2e8f9f7 1183
<> 144:ef7eb2e8f9f7 1184 /* Set the LPTIM state */
<> 144:ef7eb2e8f9f7 1185 hlptim->State= HAL_LPTIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1186
<> 144:ef7eb2e8f9f7 1187 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1188 __HAL_LPTIM_DISABLE(hlptim);
<> 144:ef7eb2e8f9f7 1189
<> 144:ef7eb2e8f9f7 1190 /* Reset TIMOUT bit to enable the timeout function */
<> 144:ef7eb2e8f9f7 1191 hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
<> 144:ef7eb2e8f9f7 1192
<> 144:ef7eb2e8f9f7 1193 /* Disable Compare match interrupt */
<> 144:ef7eb2e8f9f7 1194 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
<> 144:ef7eb2e8f9f7 1195
<> 144:ef7eb2e8f9f7 1196 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 1197 hlptim->State= HAL_LPTIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1198
<> 144:ef7eb2e8f9f7 1199 /* Return function status */
<> 144:ef7eb2e8f9f7 1200 return HAL_OK;
<> 144:ef7eb2e8f9f7 1201 }
<> 144:ef7eb2e8f9f7 1202
<> 144:ef7eb2e8f9f7 1203 /**
<> 144:ef7eb2e8f9f7 1204 * @brief Start the Counter mode.
<> 144:ef7eb2e8f9f7 1205 * @param hlptim : LPTIM handle
<> 144:ef7eb2e8f9f7 1206 * @param Period : Specifies the Autoreload value.
<> 144:ef7eb2e8f9f7 1207 * This parameter must be a value between 0x0000 and 0xFFFF.
<> 144:ef7eb2e8f9f7 1208 * @retval HAL status
<> 144:ef7eb2e8f9f7 1209 */
<> 144:ef7eb2e8f9f7 1210 HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
<> 144:ef7eb2e8f9f7 1211 {
<> 144:ef7eb2e8f9f7 1212 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1213 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
<> 144:ef7eb2e8f9f7 1214 assert_param(IS_LPTIM_PERIOD(Period));
<> 144:ef7eb2e8f9f7 1215
<> 144:ef7eb2e8f9f7 1216 /* Set the LPTIM state */
<> 144:ef7eb2e8f9f7 1217 hlptim->State= HAL_LPTIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1218
<> 144:ef7eb2e8f9f7 1219 /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
<> 144:ef7eb2e8f9f7 1220 if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
<> 144:ef7eb2e8f9f7 1221 {
<> 144:ef7eb2e8f9f7 1222 /* Check if clock is prescaled */
<> 144:ef7eb2e8f9f7 1223 assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
<> 144:ef7eb2e8f9f7 1224 /* Set clock prescaler to 0 */
<> 144:ef7eb2e8f9f7 1225 hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
<> 144:ef7eb2e8f9f7 1226 }
<> 144:ef7eb2e8f9f7 1227
<> 144:ef7eb2e8f9f7 1228 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1229 __HAL_LPTIM_ENABLE(hlptim);
<> 144:ef7eb2e8f9f7 1230
<> 144:ef7eb2e8f9f7 1231 /* Load the period value in the autoreload register */
<> 144:ef7eb2e8f9f7 1232 __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
<> 144:ef7eb2e8f9f7 1233
<> 144:ef7eb2e8f9f7 1234 /* Start timer in continuous mode */
<> 144:ef7eb2e8f9f7 1235 __HAL_LPTIM_START_CONTINUOUS(hlptim);
<> 144:ef7eb2e8f9f7 1236
<> 144:ef7eb2e8f9f7 1237 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 1238 hlptim->State= HAL_LPTIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1239
<> 144:ef7eb2e8f9f7 1240 /* Return function status */
<> 144:ef7eb2e8f9f7 1241 return HAL_OK;
<> 144:ef7eb2e8f9f7 1242 }
<> 144:ef7eb2e8f9f7 1243
<> 144:ef7eb2e8f9f7 1244 /**
<> 144:ef7eb2e8f9f7 1245 * @brief Stop the Counter mode.
<> 144:ef7eb2e8f9f7 1246 * @param hlptim : LPTIM handle
<> 144:ef7eb2e8f9f7 1247 * @retval HAL status
<> 144:ef7eb2e8f9f7 1248 */
<> 144:ef7eb2e8f9f7 1249 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
<> 144:ef7eb2e8f9f7 1250 {
<> 144:ef7eb2e8f9f7 1251 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1252 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
<> 144:ef7eb2e8f9f7 1253
<> 144:ef7eb2e8f9f7 1254 /* Set the LPTIM state */
<> 144:ef7eb2e8f9f7 1255 hlptim->State= HAL_LPTIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1256
<> 144:ef7eb2e8f9f7 1257 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1258 __HAL_LPTIM_DISABLE(hlptim);
<> 144:ef7eb2e8f9f7 1259
<> 144:ef7eb2e8f9f7 1260 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 1261 hlptim->State= HAL_LPTIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1262
<> 144:ef7eb2e8f9f7 1263 /* Return function status */
<> 144:ef7eb2e8f9f7 1264 return HAL_OK;
<> 144:ef7eb2e8f9f7 1265 }
<> 144:ef7eb2e8f9f7 1266
<> 144:ef7eb2e8f9f7 1267 /**
<> 144:ef7eb2e8f9f7 1268 * @brief Start the Counter mode in interrupt mode.
<> 144:ef7eb2e8f9f7 1269 * @param hlptim : LPTIM handle
<> 144:ef7eb2e8f9f7 1270 * @param Period : Specifies the Autoreload value.
<> 144:ef7eb2e8f9f7 1271 * This parameter must be a value between 0x0000 and 0xFFFF.
<> 144:ef7eb2e8f9f7 1272 * @retval HAL status
<> 144:ef7eb2e8f9f7 1273 */
<> 144:ef7eb2e8f9f7 1274 HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
<> 144:ef7eb2e8f9f7 1275 {
<> 144:ef7eb2e8f9f7 1276 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1277 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
<> 144:ef7eb2e8f9f7 1278 assert_param(IS_LPTIM_PERIOD(Period));
<> 144:ef7eb2e8f9f7 1279
<> 144:ef7eb2e8f9f7 1280 /* Set the LPTIM state */
<> 144:ef7eb2e8f9f7 1281 hlptim->State= HAL_LPTIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1282
<> 144:ef7eb2e8f9f7 1283 /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
<> 144:ef7eb2e8f9f7 1284 if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
<> 144:ef7eb2e8f9f7 1285 {
<> 144:ef7eb2e8f9f7 1286 /* Check if clock is prescaled */
<> 144:ef7eb2e8f9f7 1287 assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
<> 144:ef7eb2e8f9f7 1288 /* Set clock prescaler to 0 */
<> 144:ef7eb2e8f9f7 1289 hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
<> 144:ef7eb2e8f9f7 1290 }
<> 144:ef7eb2e8f9f7 1291
<> 144:ef7eb2e8f9f7 1292 /* Enable Autoreload write complete interrupt */
<> 144:ef7eb2e8f9f7 1293 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
<> 144:ef7eb2e8f9f7 1294
<> 144:ef7eb2e8f9f7 1295 /* Enable Autoreload match interrupt */
<> 144:ef7eb2e8f9f7 1296 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
<> 144:ef7eb2e8f9f7 1297
<> 144:ef7eb2e8f9f7 1298 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1299 __HAL_LPTIM_ENABLE(hlptim);
<> 144:ef7eb2e8f9f7 1300
<> 144:ef7eb2e8f9f7 1301 /* Load the period value in the autoreload register */
<> 144:ef7eb2e8f9f7 1302 __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
<> 144:ef7eb2e8f9f7 1303
<> 144:ef7eb2e8f9f7 1304 /* Start timer in continuous mode */
<> 144:ef7eb2e8f9f7 1305 __HAL_LPTIM_START_CONTINUOUS(hlptim);
<> 144:ef7eb2e8f9f7 1306
<> 144:ef7eb2e8f9f7 1307 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 1308 hlptim->State= HAL_LPTIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1309
<> 144:ef7eb2e8f9f7 1310 /* Return function status */
<> 144:ef7eb2e8f9f7 1311 return HAL_OK;
<> 144:ef7eb2e8f9f7 1312 }
<> 144:ef7eb2e8f9f7 1313
<> 144:ef7eb2e8f9f7 1314 /**
<> 144:ef7eb2e8f9f7 1315 * @brief Stop the Counter mode in interrupt mode.
<> 144:ef7eb2e8f9f7 1316 * @param hlptim : LPTIM handle
<> 144:ef7eb2e8f9f7 1317 * @retval HAL status
<> 144:ef7eb2e8f9f7 1318 */
<> 144:ef7eb2e8f9f7 1319 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
<> 144:ef7eb2e8f9f7 1320 {
<> 144:ef7eb2e8f9f7 1321 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1322 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
<> 144:ef7eb2e8f9f7 1323
<> 144:ef7eb2e8f9f7 1324 /* Set the LPTIM state */
<> 144:ef7eb2e8f9f7 1325 hlptim->State= HAL_LPTIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1326
<> 144:ef7eb2e8f9f7 1327 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1328 __HAL_LPTIM_DISABLE(hlptim);
<> 144:ef7eb2e8f9f7 1329
<> 144:ef7eb2e8f9f7 1330 /* Disable Autoreload write complete interrupt */
<> 144:ef7eb2e8f9f7 1331 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
<> 144:ef7eb2e8f9f7 1332
<> 144:ef7eb2e8f9f7 1333 /* Disable Autoreload match interrupt */
<> 144:ef7eb2e8f9f7 1334 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
<> 144:ef7eb2e8f9f7 1335
<> 144:ef7eb2e8f9f7 1336 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 1337 hlptim->State= HAL_LPTIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1338
<> 144:ef7eb2e8f9f7 1339 /* Return function status */
<> 144:ef7eb2e8f9f7 1340 return HAL_OK;
<> 144:ef7eb2e8f9f7 1341 }
<> 144:ef7eb2e8f9f7 1342
<> 144:ef7eb2e8f9f7 1343 /**
<> 144:ef7eb2e8f9f7 1344 * @}
<> 144:ef7eb2e8f9f7 1345 */
<> 144:ef7eb2e8f9f7 1346
<> 144:ef7eb2e8f9f7 1347 /** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions
<> 144:ef7eb2e8f9f7 1348 * @brief Read operation functions.
<> 144:ef7eb2e8f9f7 1349 *
<> 144:ef7eb2e8f9f7 1350 @verbatim
<> 144:ef7eb2e8f9f7 1351 ==============================================================================
<> 144:ef7eb2e8f9f7 1352 ##### LPTIM Read operation functions #####
<> 144:ef7eb2e8f9f7 1353 ==============================================================================
<> 144:ef7eb2e8f9f7 1354 [..] This section provides LPTIM Reading functions.
<> 144:ef7eb2e8f9f7 1355 (+) Read the counter value.
<> 144:ef7eb2e8f9f7 1356 (+) Read the period (Auto-reload) value.
<> 144:ef7eb2e8f9f7 1357 (+) Read the pulse (Compare)value.
<> 144:ef7eb2e8f9f7 1358 @endverbatim
<> 144:ef7eb2e8f9f7 1359 * @{
<> 144:ef7eb2e8f9f7 1360 */
<> 144:ef7eb2e8f9f7 1361
<> 144:ef7eb2e8f9f7 1362 /**
<> 144:ef7eb2e8f9f7 1363 * @brief Return the current counter value.
<> 144:ef7eb2e8f9f7 1364 * @param hlptim: LPTIM handle
<> 144:ef7eb2e8f9f7 1365 * @retval Counter value.
<> 144:ef7eb2e8f9f7 1366 */
<> 144:ef7eb2e8f9f7 1367 uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim)
<> 144:ef7eb2e8f9f7 1368 {
<> 144:ef7eb2e8f9f7 1369 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1370 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
<> 144:ef7eb2e8f9f7 1371
<> 144:ef7eb2e8f9f7 1372 return (hlptim->Instance->CNT);
<> 144:ef7eb2e8f9f7 1373 }
<> 144:ef7eb2e8f9f7 1374
<> 144:ef7eb2e8f9f7 1375 /**
<> 144:ef7eb2e8f9f7 1376 * @brief Return the current Autoreload (Period) value.
<> 144:ef7eb2e8f9f7 1377 * @param hlptim: LPTIM handle
<> 144:ef7eb2e8f9f7 1378 * @retval Autoreload value.
<> 144:ef7eb2e8f9f7 1379 */
<> 144:ef7eb2e8f9f7 1380 uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim)
<> 144:ef7eb2e8f9f7 1381 {
<> 144:ef7eb2e8f9f7 1382 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1383 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
<> 144:ef7eb2e8f9f7 1384
<> 144:ef7eb2e8f9f7 1385 return (hlptim->Instance->ARR);
<> 144:ef7eb2e8f9f7 1386 }
<> 144:ef7eb2e8f9f7 1387
<> 144:ef7eb2e8f9f7 1388 /**
<> 144:ef7eb2e8f9f7 1389 * @brief Return the current Compare (Pulse) value.
<> 144:ef7eb2e8f9f7 1390 * @param hlptim: LPTIM handle
<> 144:ef7eb2e8f9f7 1391 * @retval Compare value.
<> 144:ef7eb2e8f9f7 1392 */
<> 144:ef7eb2e8f9f7 1393 uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim)
<> 144:ef7eb2e8f9f7 1394 {
<> 144:ef7eb2e8f9f7 1395 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1396 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
<> 144:ef7eb2e8f9f7 1397
<> 144:ef7eb2e8f9f7 1398 return (hlptim->Instance->CMP);
<> 144:ef7eb2e8f9f7 1399 }
<> 144:ef7eb2e8f9f7 1400
<> 144:ef7eb2e8f9f7 1401 /**
<> 144:ef7eb2e8f9f7 1402 * @}
<> 144:ef7eb2e8f9f7 1403 */
<> 144:ef7eb2e8f9f7 1404
<> 144:ef7eb2e8f9f7 1405
<> 144:ef7eb2e8f9f7 1406
<> 144:ef7eb2e8f9f7 1407 /** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks
<> 144:ef7eb2e8f9f7 1408 * @brief LPTIM IRQ handler.
<> 144:ef7eb2e8f9f7 1409 *
<> 144:ef7eb2e8f9f7 1410 @verbatim
<> 144:ef7eb2e8f9f7 1411 ==============================================================================
<> 144:ef7eb2e8f9f7 1412 ##### LPTIM IRQ handler and callbacks #####
<> 144:ef7eb2e8f9f7 1413 ==============================================================================
<> 144:ef7eb2e8f9f7 1414 [..] This section provides LPTIM IRQ handler and callback functions called within
<> 144:ef7eb2e8f9f7 1415 the IRQ handler.
<> 144:ef7eb2e8f9f7 1416
<> 144:ef7eb2e8f9f7 1417 @endverbatim
<> 144:ef7eb2e8f9f7 1418 * @{
<> 144:ef7eb2e8f9f7 1419 */
<> 144:ef7eb2e8f9f7 1420
<> 144:ef7eb2e8f9f7 1421 /**
<> 144:ef7eb2e8f9f7 1422 * @brief Handle LPTIM interrupt request.
<> 144:ef7eb2e8f9f7 1423 * @param hlptim: LPTIM handle
<> 144:ef7eb2e8f9f7 1424 * @retval None
<> 144:ef7eb2e8f9f7 1425 */
<> 144:ef7eb2e8f9f7 1426 void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
<> 144:ef7eb2e8f9f7 1427 {
<> 144:ef7eb2e8f9f7 1428 /* Compare match interrupt */
<> 144:ef7eb2e8f9f7 1429 if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET)
<> 144:ef7eb2e8f9f7 1430 {
<> 144:ef7eb2e8f9f7 1431 if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) != RESET)
<> 144:ef7eb2e8f9f7 1432 {
<> 144:ef7eb2e8f9f7 1433 /* Clear Compare match flag */
<> 144:ef7eb2e8f9f7 1434 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM);
<> 144:ef7eb2e8f9f7 1435
<> 144:ef7eb2e8f9f7 1436 /* Compare match Callback */
<> 144:ef7eb2e8f9f7 1437 HAL_LPTIM_CompareMatchCallback(hlptim);
<> 144:ef7eb2e8f9f7 1438 }
<> 144:ef7eb2e8f9f7 1439 }
<> 144:ef7eb2e8f9f7 1440
<> 144:ef7eb2e8f9f7 1441 /* Autoreload match interrupt */
<> 144:ef7eb2e8f9f7 1442 if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)
<> 144:ef7eb2e8f9f7 1443 {
<> 144:ef7eb2e8f9f7 1444 if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) != RESET)
<> 144:ef7eb2e8f9f7 1445 {
<> 144:ef7eb2e8f9f7 1446 /* Clear Autoreload match flag */
<> 144:ef7eb2e8f9f7 1447 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);
<> 144:ef7eb2e8f9f7 1448
<> 144:ef7eb2e8f9f7 1449 /* Autoreload match Callback */
<> 144:ef7eb2e8f9f7 1450 HAL_LPTIM_AutoReloadMatchCallback(hlptim);
<> 144:ef7eb2e8f9f7 1451 }
<> 144:ef7eb2e8f9f7 1452 }
<> 144:ef7eb2e8f9f7 1453
<> 144:ef7eb2e8f9f7 1454 /* Trigger detected interrupt */
<> 144:ef7eb2e8f9f7 1455 if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)
<> 144:ef7eb2e8f9f7 1456 {
<> 144:ef7eb2e8f9f7 1457 if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) != RESET)
<> 144:ef7eb2e8f9f7 1458 {
<> 144:ef7eb2e8f9f7 1459 /* Clear Trigger detected flag */
<> 144:ef7eb2e8f9f7 1460 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);
<> 144:ef7eb2e8f9f7 1461
<> 144:ef7eb2e8f9f7 1462 /* Trigger detected callback */
<> 144:ef7eb2e8f9f7 1463 HAL_LPTIM_TriggerCallback(hlptim);
<> 144:ef7eb2e8f9f7 1464 }
<> 144:ef7eb2e8f9f7 1465 }
<> 144:ef7eb2e8f9f7 1466
<> 144:ef7eb2e8f9f7 1467 /* Compare write interrupt */
<> 144:ef7eb2e8f9f7 1468 if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET)
<> 144:ef7eb2e8f9f7 1469 {
<> 144:ef7eb2e8f9f7 1470 if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPOK) != RESET)
<> 144:ef7eb2e8f9f7 1471 {
<> 144:ef7eb2e8f9f7 1472 /* Clear Compare write flag */
<> 144:ef7eb2e8f9f7 1473 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
<> 144:ef7eb2e8f9f7 1474
<> 144:ef7eb2e8f9f7 1475 /* Compare write Callback */
<> 144:ef7eb2e8f9f7 1476 HAL_LPTIM_CompareWriteCallback(hlptim);
<> 144:ef7eb2e8f9f7 1477 }
<> 144:ef7eb2e8f9f7 1478 }
<> 144:ef7eb2e8f9f7 1479
<> 144:ef7eb2e8f9f7 1480 /* Autoreload write interrupt */
<> 144:ef7eb2e8f9f7 1481 if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)
<> 144:ef7eb2e8f9f7 1482 {
<> 144:ef7eb2e8f9f7 1483 if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) != RESET)
<> 144:ef7eb2e8f9f7 1484 {
<> 144:ef7eb2e8f9f7 1485 /* Clear Autoreload write flag */
<> 144:ef7eb2e8f9f7 1486 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
<> 144:ef7eb2e8f9f7 1487
<> 144:ef7eb2e8f9f7 1488 /* Autoreload write Callback */
<> 144:ef7eb2e8f9f7 1489 HAL_LPTIM_AutoReloadWriteCallback(hlptim);
<> 144:ef7eb2e8f9f7 1490 }
<> 144:ef7eb2e8f9f7 1491 }
<> 144:ef7eb2e8f9f7 1492
<> 144:ef7eb2e8f9f7 1493 /* Direction counter changed from Down to Up interrupt */
<> 144:ef7eb2e8f9f7 1494 if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)
<> 144:ef7eb2e8f9f7 1495 {
<> 144:ef7eb2e8f9f7 1496 if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) != RESET)
<> 144:ef7eb2e8f9f7 1497 {
<> 144:ef7eb2e8f9f7 1498 /* Clear Direction counter changed from Down to Up flag */
<> 144:ef7eb2e8f9f7 1499 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);
<> 144:ef7eb2e8f9f7 1500
<> 144:ef7eb2e8f9f7 1501 /* Direction counter changed from Down to Up Callback */
<> 144:ef7eb2e8f9f7 1502 HAL_LPTIM_DirectionUpCallback(hlptim);
<> 144:ef7eb2e8f9f7 1503 }
<> 144:ef7eb2e8f9f7 1504 }
<> 144:ef7eb2e8f9f7 1505
<> 144:ef7eb2e8f9f7 1506 /* Direction counter changed from Up to Down interrupt */
<> 144:ef7eb2e8f9f7 1507 if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)
<> 144:ef7eb2e8f9f7 1508 {
<> 144:ef7eb2e8f9f7 1509 if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) != RESET)
<> 144:ef7eb2e8f9f7 1510 {
<> 144:ef7eb2e8f9f7 1511 /* Clear Direction counter changed from Up to Down flag */
<> 144:ef7eb2e8f9f7 1512 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);
<> 144:ef7eb2e8f9f7 1513
<> 144:ef7eb2e8f9f7 1514 /* Direction counter changed from Up to Down Callback */
<> 144:ef7eb2e8f9f7 1515 HAL_LPTIM_DirectionDownCallback(hlptim);
<> 144:ef7eb2e8f9f7 1516 }
<> 144:ef7eb2e8f9f7 1517 }
<> 144:ef7eb2e8f9f7 1518 }
<> 144:ef7eb2e8f9f7 1519
<> 144:ef7eb2e8f9f7 1520 /**
<> 144:ef7eb2e8f9f7 1521 * @brief Compare match callback in non-blocking mode.
<> 144:ef7eb2e8f9f7 1522 * @param hlptim : LPTIM handle
<> 144:ef7eb2e8f9f7 1523 * @retval None
<> 144:ef7eb2e8f9f7 1524 */
<> 144:ef7eb2e8f9f7 1525 __weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
<> 144:ef7eb2e8f9f7 1526 {
<> 144:ef7eb2e8f9f7 1527 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1528 UNUSED(hlptim);
<> 144:ef7eb2e8f9f7 1529
<> 144:ef7eb2e8f9f7 1530 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1531 the HAL_LPTIM_CompareMatchCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1532 */
<> 144:ef7eb2e8f9f7 1533 }
<> 144:ef7eb2e8f9f7 1534
<> 144:ef7eb2e8f9f7 1535 /**
<> 144:ef7eb2e8f9f7 1536 * @brief Autoreload match callback in non-blocking mode.
<> 144:ef7eb2e8f9f7 1537 * @param hlptim : LPTIM handle
<> 144:ef7eb2e8f9f7 1538 * @retval None
<> 144:ef7eb2e8f9f7 1539 */
<> 144:ef7eb2e8f9f7 1540 __weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
<> 144:ef7eb2e8f9f7 1541 {
<> 144:ef7eb2e8f9f7 1542 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1543 UNUSED(hlptim);
<> 144:ef7eb2e8f9f7 1544
<> 144:ef7eb2e8f9f7 1545 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1546 the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1547 */
<> 144:ef7eb2e8f9f7 1548 }
<> 144:ef7eb2e8f9f7 1549
<> 144:ef7eb2e8f9f7 1550 /**
<> 144:ef7eb2e8f9f7 1551 * @brief Trigger detected callback in non-blocking mode.
<> 144:ef7eb2e8f9f7 1552 * @param hlptim : LPTIM handle
<> 144:ef7eb2e8f9f7 1553 * @retval None
<> 144:ef7eb2e8f9f7 1554 */
<> 144:ef7eb2e8f9f7 1555 __weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
<> 144:ef7eb2e8f9f7 1556 {
<> 144:ef7eb2e8f9f7 1557 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1558 UNUSED(hlptim);
<> 144:ef7eb2e8f9f7 1559
<> 144:ef7eb2e8f9f7 1560 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1561 the HAL_LPTIM_TriggerCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1562 */
<> 144:ef7eb2e8f9f7 1563 }
<> 144:ef7eb2e8f9f7 1564
<> 144:ef7eb2e8f9f7 1565 /**
<> 144:ef7eb2e8f9f7 1566 * @brief Compare write callback in non-blocking mode.
<> 144:ef7eb2e8f9f7 1567 * @param hlptim : LPTIM handle
<> 144:ef7eb2e8f9f7 1568 * @retval None
<> 144:ef7eb2e8f9f7 1569 */
<> 144:ef7eb2e8f9f7 1570 __weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
<> 144:ef7eb2e8f9f7 1571 {
<> 144:ef7eb2e8f9f7 1572 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1573 UNUSED(hlptim);
<> 144:ef7eb2e8f9f7 1574
<> 144:ef7eb2e8f9f7 1575 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1576 the HAL_LPTIM_CompareWriteCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1577 */
<> 144:ef7eb2e8f9f7 1578 }
<> 144:ef7eb2e8f9f7 1579
<> 144:ef7eb2e8f9f7 1580 /**
<> 144:ef7eb2e8f9f7 1581 * @brief Autoreload write callback in non-blocking mode.
<> 144:ef7eb2e8f9f7 1582 * @param hlptim : LPTIM handle
<> 144:ef7eb2e8f9f7 1583 * @retval None
<> 144:ef7eb2e8f9f7 1584 */
<> 144:ef7eb2e8f9f7 1585 __weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
<> 144:ef7eb2e8f9f7 1586 {
<> 144:ef7eb2e8f9f7 1587 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1588 UNUSED(hlptim);
<> 144:ef7eb2e8f9f7 1589
<> 144:ef7eb2e8f9f7 1590 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1591 the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1592 */
<> 144:ef7eb2e8f9f7 1593 }
<> 144:ef7eb2e8f9f7 1594
<> 144:ef7eb2e8f9f7 1595 /**
<> 144:ef7eb2e8f9f7 1596 * @brief Direction counter changed from Down to Up callback in non-blocking mode.
<> 144:ef7eb2e8f9f7 1597 * @param hlptim : LPTIM handle
<> 144:ef7eb2e8f9f7 1598 * @retval None
<> 144:ef7eb2e8f9f7 1599 */
<> 144:ef7eb2e8f9f7 1600 __weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
<> 144:ef7eb2e8f9f7 1601 {
<> 144:ef7eb2e8f9f7 1602 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1603 UNUSED(hlptim);
<> 144:ef7eb2e8f9f7 1604
<> 144:ef7eb2e8f9f7 1605 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1606 the HAL_LPTIM_DirectionUpCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1607 */
<> 144:ef7eb2e8f9f7 1608 }
<> 144:ef7eb2e8f9f7 1609
<> 144:ef7eb2e8f9f7 1610 /**
<> 144:ef7eb2e8f9f7 1611 * @brief Direction counter changed from Up to Down callback in non-blocking mode.
<> 144:ef7eb2e8f9f7 1612 * @param hlptim : LPTIM handle
<> 144:ef7eb2e8f9f7 1613 * @retval None
<> 144:ef7eb2e8f9f7 1614 */
<> 144:ef7eb2e8f9f7 1615 __weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
<> 144:ef7eb2e8f9f7 1616 {
<> 144:ef7eb2e8f9f7 1617 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1618 UNUSED(hlptim);
<> 144:ef7eb2e8f9f7 1619
<> 144:ef7eb2e8f9f7 1620 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1621 the HAL_LPTIM_DirectionDownCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1622 */
<> 144:ef7eb2e8f9f7 1623 }
<> 144:ef7eb2e8f9f7 1624
<> 144:ef7eb2e8f9f7 1625 /**
<> 144:ef7eb2e8f9f7 1626 * @}
<> 144:ef7eb2e8f9f7 1627 */
<> 144:ef7eb2e8f9f7 1628
<> 144:ef7eb2e8f9f7 1629 /** @defgroup LPTIM_Exported_Functions_Group5 Peripheral State functions
<> 144:ef7eb2e8f9f7 1630 * @brief Peripheral State functions.
<> 144:ef7eb2e8f9f7 1631 *
<> 144:ef7eb2e8f9f7 1632 @verbatim
<> 144:ef7eb2e8f9f7 1633 ==============================================================================
<> 144:ef7eb2e8f9f7 1634 ##### Peripheral State functions #####
<> 144:ef7eb2e8f9f7 1635 ==============================================================================
<> 144:ef7eb2e8f9f7 1636 [..]
<> 144:ef7eb2e8f9f7 1637 This subsection permits to get in run-time the status of the peripheral.
<> 144:ef7eb2e8f9f7 1638
<> 144:ef7eb2e8f9f7 1639 @endverbatim
<> 144:ef7eb2e8f9f7 1640 * @{
<> 144:ef7eb2e8f9f7 1641 */
<> 144:ef7eb2e8f9f7 1642
<> 144:ef7eb2e8f9f7 1643 /**
<> 144:ef7eb2e8f9f7 1644 * @brief Return the LPTIM handle state.
<> 144:ef7eb2e8f9f7 1645 * @param hlptim: LPTIM handle
<> 144:ef7eb2e8f9f7 1646 * @retval HAL state
<> 144:ef7eb2e8f9f7 1647 */
<> 144:ef7eb2e8f9f7 1648 HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)
<> 144:ef7eb2e8f9f7 1649 {
<> 144:ef7eb2e8f9f7 1650 /* Return LPTIM handle state */
<> 144:ef7eb2e8f9f7 1651 return hlptim->State;
<> 144:ef7eb2e8f9f7 1652 }
<> 144:ef7eb2e8f9f7 1653
<> 144:ef7eb2e8f9f7 1654 /**
<> 144:ef7eb2e8f9f7 1655 * @}
<> 144:ef7eb2e8f9f7 1656 */
<> 144:ef7eb2e8f9f7 1657
<> 144:ef7eb2e8f9f7 1658
<> 144:ef7eb2e8f9f7 1659 /**
<> 144:ef7eb2e8f9f7 1660 * @}
<> 144:ef7eb2e8f9f7 1661 */
<> 144:ef7eb2e8f9f7 1662
<> 144:ef7eb2e8f9f7 1663 #endif /* HAL_LPTIM_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1664 /**
<> 144:ef7eb2e8f9f7 1665 * @}
<> 144:ef7eb2e8f9f7 1666 */
<> 144:ef7eb2e8f9f7 1667
<> 144:ef7eb2e8f9f7 1668 /**
<> 144:ef7eb2e8f9f7 1669 * @}
<> 144:ef7eb2e8f9f7 1670 */
<> 144:ef7eb2e8f9f7 1671
<> 144:ef7eb2e8f9f7 1672 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/