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stm32f4xx_tim_mort.h
00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_tim.h 00004 * @author MCD Application Team 00005 * @version V1.8.0 00006 * @date 04-November-2016 00007 * @brief This file contains all the functions prototypes for the TIM firmware 00008 * library. 00009 ****************************************************************************** 00010 * @attention 00011 * 00012 * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2> 00013 * 00014 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 00015 * You may not use this file except in compliance with the License. 00016 * You may obtain a copy of the License at: 00017 * 00018 * http://www.st.com/software_license_agreement_liberty_v2 00019 * 00020 * Unless required by applicable law or agreed to in writing, software 00021 * distributed under the License is distributed on an "AS IS" BASIS, 00022 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00023 * See the License for the specific language governing permissions and 00024 * limitations under the License. 00025 * 00026 ****************************************************************************** 00027 */ 00028 00029 /* Define to prevent recursive inclusion -------------------------------------*/ 00030 #ifndef __STM32F4xx_TIM_H_MORT_ 00031 #define __STM32F4xx_TIM_H_MORT_ 00032 00033 #ifdef __cplusplus 00034 extern "C" { 00035 #endif 00036 00037 /* Includes ------------------------------------------------------------------*/ 00038 #include "stm32f4xx_mort2.h" 00039 00040 /** @addtogroup STM32F4xx_StdPeriph_Driver 00041 * @{ 00042 */ 00043 00044 /** @addtogroup TIM 00045 * @{ 00046 */ 00047 00048 /* Exported types ------------------------------------------------------------*/ 00049 00050 /** 00051 * @brief TIM Time Base Init structure definition 00052 * @note This structure is used with all TIMx except for TIM6_MORT and TIM7_MORT. 00053 */ 00054 00055 typedef struct 00056 { 00057 uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 00058 This parameter can be a number between 0x0000 and 0xFFFF */ 00059 00060 uint16_t TIM_CounterMode; /*!< Specifies the counter mode. 00061 This parameter can be a value of @ref TIM_Counter_Mode */ 00062 00063 uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active 00064 Auto-Reload Register at the next update event. 00065 This parameter must be a number between 0x0000 and 0xFFFF. */ 00066 00067 uint16_t TIM_ClockDivision; /*!< Specifies the clock division. 00068 This parameter can be a value of @ref TIM_Clock_Division_CKD */ 00069 00070 uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter 00071 reaches zero, an update event is generated and counting restarts 00072 from the RCR value (N). 00073 This means in PWM mode that (N+1) corresponds to: 00074 - the number of PWM periods in edge-aligned mode 00075 - the number of half PWM period in center-aligned mode 00076 This parameter must be a number between 0x00 and 0xFF. 00077 @note This parameter is valid only for TIM1_MORT and TIM8_MORT. */ 00078 } TIM_TimeBaseInitTypeDef_mort; 00079 00080 /** 00081 * @brief TIM Output Compare Init structure definition 00082 */ 00083 00084 typedef struct 00085 { 00086 uint16_t TIM_OCMode; /*!< Specifies the TIM mode. 00087 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 00088 00089 uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. 00090 This parameter can be a value of @ref TIM_Output_Compare_State */ 00091 00092 uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. 00093 This parameter can be a value of @ref TIM_Output_Compare_N_State 00094 @note This parameter is valid only for TIM1_MORT and TIM8_MORT. */ 00095 00096 uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 00097 This parameter can be a number between 0x0000 and 0xFFFF */ 00098 00099 uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. 00100 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 00101 00102 uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. 00103 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 00104 @note This parameter is valid only for TIM1_MORT and TIM8_MORT. */ 00105 00106 uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00107 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 00108 @note This parameter is valid only for TIM1_MORT and TIM8_MORT. */ 00109 00110 uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00111 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 00112 @note This parameter is valid only for TIM1_MORT and TIM8_MORT. */ 00113 } TIM_OCInitTypeDef_mort; 00114 00115 /** 00116 * @brief TIM Input Capture Init structure definition 00117 */ 00118 00119 typedef struct 00120 { 00121 00122 uint16_t TIM_Channel; /*!< Specifies the TIM channel. 00123 This parameter can be a value of @ref TIM_Channel */ 00124 00125 uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. 00126 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 00127 00128 uint16_t TIM_ICSelection; /*!< Specifies the input. 00129 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 00130 00131 uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. 00132 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 00133 00134 uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. 00135 This parameter can be a number between 0x0 and 0xF */ 00136 } TIM_ICInitTypeDef_mort; 00137 00138 /** 00139 * @brief BDTR structure definition 00140 * @note This structure is used only with TIM1_MORT and TIM8_MORT. 00141 */ 00142 00143 typedef struct 00144 { 00145 00146 uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. 00147 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ 00148 00149 uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. 00150 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ 00151 00152 uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. 00153 This parameter can be a value of @ref TIM_Lock_level */ 00154 00155 uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the 00156 switching-on of the outputs. 00157 This parameter can be a number between 0x00 and 0xFF */ 00158 00159 uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. 00160 This parameter can be a value of @ref TIM_Break_Input_enable_disable */ 00161 00162 uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. 00163 This parameter can be a value of @ref TIM_Break_Polarity */ 00164 00165 uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. 00166 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ 00167 } TIM_BDTRInitTypeDef_mort; 00168 00169 /* Exported constants --------------------------------------------------------*/ 00170 00171 /** @defgroup TIM_Exported_constants 00172 * @{ 00173 */ 00174 00175 #define IS_TIM_ALL_PERIPH_MORT(PERIPH) (((PERIPH) == TIM1_MORT) || \ 00176 ((PERIPH) == TIM2_MORT) || \ 00177 ((PERIPH) == TIM3_MORT) || \ 00178 ((PERIPH) == TIM4_MORT) || \ 00179 ((PERIPH) == TIM5_MORT) || \ 00180 ((PERIPH) == TIM6_MORT) || \ 00181 ((PERIPH) == TIM7_MORT) || \ 00182 ((PERIPH) == TIM8_MORT) || \ 00183 ((PERIPH) == TIM9_MORT) || \ 00184 ((PERIPH) == TIM10_MORT) || \ 00185 ((PERIPH) == TIM11_MORT) || \ 00186 ((PERIPH) == TIM12_MORT) || \ 00187 (((PERIPH) == TIM13_MORT) || \ 00188 ((PERIPH) == TIM14_MORT))) 00189 /* LIST1: TIM1_MORT, TIM2_MORT, TIM3_MORT, TIM4_MORT, TIM5_MORT, TIM8_MORT, TIM9_MORT, TIM10_MORT, TIM11_MORT, TIM12_MORT, TIM13_MORT and TIM14_MORT */ 00190 #define IS_TIM_LIST1_PERIPH_MORT(PERIPH) (((PERIPH) == TIM1_MORT) || \ 00191 ((PERIPH) == TIM2_MORT) || \ 00192 ((PERIPH) == TIM3_MORT) || \ 00193 ((PERIPH) == TIM4_MORT) || \ 00194 ((PERIPH) == TIM5_MORT) || \ 00195 ((PERIPH) == TIM8_MORT) || \ 00196 ((PERIPH) == TIM9_MORT) || \ 00197 ((PERIPH) == TIM10_MORT) || \ 00198 ((PERIPH) == TIM11_MORT) || \ 00199 ((PERIPH) == TIM12_MORT) || \ 00200 ((PERIPH) == TIM13_MORT) || \ 00201 ((PERIPH) == TIM14_MORT)) 00202 00203 /* LIST2: TIM1_MORT, TIM2_MORT, TIM3_MORT, TIM4_MORT, TIM5_MORT, TIM8_MORT, TIM9_MORT and TIM12_MORT */ 00204 #define IS_TIM_LIST2_PERIPH_MORT(PERIPH) (((PERIPH) == TIM1_MORT) || \ 00205 ((PERIPH) == TIM2_MORT) || \ 00206 ((PERIPH) == TIM3_MORT) || \ 00207 ((PERIPH) == TIM4_MORT) || \ 00208 ((PERIPH) == TIM5_MORT) || \ 00209 ((PERIPH) == TIM8_MORT) || \ 00210 ((PERIPH) == TIM9_MORT) || \ 00211 ((PERIPH) == TIM12_MORT)) 00212 /* LIST3: TIM1_MORT, TIM2_MORT, TIM3_MORT, TIM4_MORT, TIM5_MORT and TIM8_MORT */ 00213 #define IS_TIM_LIST3_PERIPH_MORT(PERIPH) (((PERIPH) == TIM1_MORT) || \ 00214 ((PERIPH) == TIM2_MORT) || \ 00215 ((PERIPH) == TIM3_MORT) || \ 00216 ((PERIPH) == TIM4_MORT) || \ 00217 ((PERIPH) == TIM5_MORT) || \ 00218 ((PERIPH) == TIM8_MORT)) 00219 /* LIST4: TIM1_MORT and TIM8_MORT */ 00220 #define IS_TIM_LIST4_PERIPH_MORT(PERIPH) (((PERIPH) == TIM1_MORT) || \ 00221 ((PERIPH) == TIM8_MORT)) 00222 /* LIST5: TIM1_MORT, TIM2_MORT, TIM3_MORT, TIM4_MORT, TIM5_MORT, TIM6_MORT, TIM7_MORT and TIM8_MORT */ 00223 #define IS_TIM_LIST5_PERIPH_MORT(PERIPH) (((PERIPH) == TIM1_MORT) || \ 00224 ((PERIPH) == TIM2_MORT) || \ 00225 ((PERIPH) == TIM3_MORT) || \ 00226 ((PERIPH) == TIM4_MORT) || \ 00227 ((PERIPH) == TIM5_MORT) || \ 00228 ((PERIPH) == TIM6_MORT) || \ 00229 ((PERIPH) == TIM7_MORT) || \ 00230 ((PERIPH) == TIM8_MORT)) 00231 /* LIST6: TIM2_MORT, TIM5_MORT and TIM11_MORT */ 00232 #define IS_TIM_LIST6_PERIPH_MORT(TIMx)(((TIMx) == TIM2_MORT) || \ 00233 ((TIMx) == TIM5_MORT) || \ 00234 ((TIMx) == TIM11_MORT)) 00235 00236 /** @defgroup TIM_Output_Compare_and_PWM_modes 00237 * @{ 00238 */ 00239 00240 #define TIM_OCMode_Timing_MORT ((uint16_t)0x0000) 00241 #define TIM_OCMode_Active_MORT ((uint16_t)0x0010) 00242 #define TIM_OCMode_Inactive_MORT ((uint16_t)0x0020) 00243 #define TIM_OCMode_Toggle_MORT ((uint16_t)0x0030) 00244 #define TIM_OCMode_PWM1_MORT ((uint16_t)0x0060) 00245 #define TIM_OCMode_PWM2_MORT ((uint16_t)0x0070) 00246 #define IS_TIM_OC_MODE_MORT(MODE) (((MODE) == TIM_OCMode_Timing_MORT) || \ 00247 ((MODE) == TIM_OCMode_Active_MORT) || \ 00248 ((MODE) == TIM_OCMode_Inactive_MORT) || \ 00249 ((MODE) == TIM_OCMode_Toggle_MORT)|| \ 00250 ((MODE) == TIM_OCMode_PWM1_MORT) || \ 00251 ((MODE) == TIM_OCMode_PWM2_MORT)) 00252 #define IS_TIM_OCM_MORT(MODE) (((MODE) == TIM_OCMode_Timing_MORT) || \ 00253 ((MODE) == TIM_OCMode_Active_MORT) || \ 00254 ((MODE) == TIM_OCMode_Inactive_MORT) || \ 00255 ((MODE) == TIM_OCMode_Toggle_MORT)|| \ 00256 ((MODE) == TIM_OCMode_PWM1_MORT) || \ 00257 ((MODE) == TIM_OCMode_PWM2_MORT) || \ 00258 ((MODE) == TIM_ForcedAction_Active_MORT) || \ 00259 ((MODE) == TIM_ForcedAction_InActive_MORT)) 00260 /** 00261 * @} 00262 */ 00263 00264 /** @defgroup TIM_One_Pulse_Mode 00265 * @{ 00266 */ 00267 00268 #define TIM_OPMode_Single_MORT ((uint16_t)0x0008) 00269 #define TIM_OPMode_Repetitive_MORT ((uint16_t)0x0000) 00270 #define IS_TIM_OPM_MODE_MORT(MODE) (((MODE) == TIM_OPMode_Single_MORT) || \ 00271 ((MODE) == TIM_OPMode_Repetitive_MORT)) 00272 /** 00273 * @} 00274 */ 00275 00276 /** @defgroup TIM_Channel 00277 * @{ 00278 */ 00279 00280 #define TIM_Channel_1_MORT ((uint16_t)0x0000) 00281 #define TIM_Channel_2_MORT ((uint16_t)0x0004) 00282 #define TIM_Channel_3_MORT ((uint16_t)0x0008) 00283 #define TIM_Channel_4_MORT ((uint16_t)0x000C) 00284 00285 #define IS_TIM_CHANNEL_MORT(CHANNEL) (((CHANNEL) == TIM_Channel_1_MORT) || \ 00286 ((CHANNEL) == TIM_Channel_2_MORT) || \ 00287 ((CHANNEL) == TIM_Channel_3_MORT) || \ 00288 ((CHANNEL) == TIM_Channel_4_MORT)) 00289 00290 #define IS_TIM_PWMI_CHANNEL_MORT(CHANNEL) (((CHANNEL) == TIM_Channel_1_MORT) || \ 00291 ((CHANNEL) == TIM_Channel_2_MORT)) 00292 #define IS_TIM_COMPLEMENTARY_CHANNEL_MORT(CHANNEL) (((CHANNEL) == TIM_Channel_1_MORT) || \ 00293 ((CHANNEL) == TIM_Channel_2_MORT) || \ 00294 ((CHANNEL) == TIM_Channel_3_MORT)) 00295 /** 00296 * @} 00297 */ 00298 00299 /** @defgroup TIM_Clock_Division_CKD 00300 * @{ 00301 */ 00302 00303 #define TIM_CKD_DIV1_MORT ((uint16_t)0x0000) 00304 #define TIM_CKD_DIV2_MORT ((uint16_t)0x0100) 00305 #define TIM_CKD_DIV4_MORT ((uint16_t)0x0200) 00306 #define IS_TIM_CKD_DIV_MORT(DIV) (((DIV) == TIM_CKD_DIV1_MORT) || \ 00307 ((DIV) == TIM_CKD_DIV2_MORT) || \ 00308 ((DIV) == TIM_CKD_DIV4_MORT)) 00309 /** 00310 * @} 00311 */ 00312 00313 /** @defgroup TIM_Counter_Mode 00314 * @{ 00315 */ 00316 00317 #define TIM_CounterMode_Up_MORT ((uint16_t)0x0000) 00318 #define TIM_CounterMode_Down_MORT ((uint16_t)0x0010) 00319 #define TIM_CounterMode_CenterAligned1_MORT ((uint16_t)0x0020) 00320 #define TIM_CounterMode_CenterAligned2_MORT ((uint16_t)0x0040) 00321 #define TIM_CounterMode_CenterAligned3_MORT ((uint16_t)0x0060) 00322 #define IS_TIM_COUNTER_MODE_MORT(MODE) (((MODE) == TIM_CounterMode_Up_MORT) || \ 00323 ((MODE) == TIM_CounterMode_Down_MORT) || \ 00324 ((MODE) == TIM_CounterMode_CenterAligned1_MORT) || \ 00325 ((MODE) == TIM_CounterMode_CenterAligned2_MORT) || \ 00326 ((MODE) == TIM_CounterMode_CenterAligned3_MORT)) 00327 /** 00328 * @} 00329 */ 00330 00331 /** @defgroup TIM_Output_Compare_Polarity 00332 * @{ 00333 */ 00334 00335 #define TIM_OCPolarity_High_MORT ((uint16_t)0x0000) 00336 #define TIM_OCPolarity_Low_MORT ((uint16_t)0x0002) 00337 #define IS_TIM_OC_POLARITY_MORT(POLARITY) (((POLARITY) == TIM_OCPolarity_High_MORT) || \ 00338 ((POLARITY) == TIM_OCPolarity_Low_MORT)) 00339 /** 00340 * @} 00341 */ 00342 00343 /** @defgroup TIM_Output_Compare_N_Polarity 00344 * @{ 00345 */ 00346 00347 #define TIM_OCNPolarity_High_MORT ((uint16_t)0x0000) 00348 #define TIM_OCNPolarity_Low_MORT ((uint16_t)0x0008) 00349 #define IS_TIM_OCN_POLARITY_MORT(POLARITY) (((POLARITY) == TIM_OCNPolarity_High_MORT) || \ 00350 ((POLARITY) == TIM_OCNPolarity_Low_MORT)) 00351 /** 00352 * @} 00353 */ 00354 00355 /** @defgroup TIM_Output_Compare_State 00356 * @{ 00357 */ 00358 00359 #define TIM_OutputState_Disable_MORT ((uint16_t)0x0000) 00360 #define TIM_OutputState_Enable_MORT ((uint16_t)0x0001) 00361 #define IS_TIM_OUTPUT_STATE_MORT(STATE) (((STATE) == TIM_OutputState_Disable_MORT) || \ 00362 ((STATE) == TIM_OutputState_Enable_MORT)) 00363 /** 00364 * @} 00365 */ 00366 00367 /** @defgroup TIM_Output_Compare_N_State 00368 * @{ 00369 */ 00370 00371 #define TIM_OutputNState_Disable_MORT ((uint16_t)0x0000) 00372 #define TIM_OutputNState_Enable_MORT ((uint16_t)0x0004) 00373 #define IS_TIM_OUTPUTN_STATE_MORT(STATE) (((STATE) == TIM_OutputNState_Disable_MORT) || \ 00374 ((STATE) == TIM_OutputNState_Enable_MORT)) 00375 /** 00376 * @} 00377 */ 00378 00379 /** @defgroup TIM_Capture_Compare_State 00380 * @{ 00381 */ 00382 00383 #define TIM_CCx_Enable_MORT ((uint16_t)0x0001) 00384 #define TIM_CCx_Disable_MORT ((uint16_t)0x0000) 00385 #define IS_TIM_CCX_MORT(CCX) (((CCX) == TIM_CCx_Enable_MORT) || \ 00386 ((CCX) == TIM_CCx_Disable_MORT)) 00387 /** 00388 * @} 00389 */ 00390 00391 /** @defgroup TIM_Capture_Compare_N_State 00392 * @{ 00393 */ 00394 00395 #define TIM_CCxN_Enable_MORT ((uint16_t)0x0004) 00396 #define TIM_CCxN_Disable_MORT ((uint16_t)0x0000) 00397 #define IS_TIM_CCXN_MORT(CCXN) (((CCXN) == TIM_CCxN_Enable_MORT) || \ 00398 ((CCXN) == TIM_CCxN_Disable_MORT)) 00399 /** 00400 * @} 00401 */ 00402 00403 /** @defgroup TIM_Break_Input_enable_disable 00404 * @{ 00405 */ 00406 00407 #define TIM_Break_Enable_MORT ((uint16_t)0x1000) 00408 #define TIM_Break_Disable_MORT ((uint16_t)0x0000) 00409 #define IS_TIM_BREAK_STATE_MORT(STATE) (((STATE) == TIM_Break_Enable_MORT) || \ 00410 ((STATE) == TIM_Break_Disable_MORT)) 00411 /** 00412 * @} 00413 */ 00414 00415 /** @defgroup TIM_Break_Polarity 00416 * @{ 00417 */ 00418 00419 #define TIM_BreakPolarity_Low_MORT ((uint16_t)0x0000) 00420 #define TIM_BreakPolarity_High_MORT ((uint16_t)0x2000) 00421 #define IS_TIM_BREAK_POLARITY_MORT(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low_MORT) || \ 00422 ((POLARITY) == TIM_BreakPolarity_High_MORT)) 00423 /** 00424 * @} 00425 */ 00426 00427 /** @defgroup TIM_AOE_Bit_Set_Reset 00428 * @{ 00429 */ 00430 00431 #define TIM_AutomaticOutput_Enable_MORT ((uint16_t)0x4000) 00432 #define TIM_AutomaticOutput_Disable_MORT ((uint16_t)0x0000) 00433 #define IS_TIM_AUTOMATIC_OUTPUT_STATE_MORT(STATE) (((STATE) == TIM_AutomaticOutput_Enable_MORT) || \ 00434 ((STATE) == TIM_AutomaticOutput_Disable_MORT)) 00435 /** 00436 * @} 00437 */ 00438 00439 /** @defgroup TIM_Lock_level 00440 * @{ 00441 */ 00442 00443 #define TIM_LOCKLevel_OFF_MORT ((uint16_t)0x0000) 00444 #define TIM_LOCKLevel_1_MORT ((uint16_t)0x0100) 00445 #define TIM_LOCKLevel_2_MORT ((uint16_t)0x0200) 00446 #define TIM_LOCKLevel_3_MORT ((uint16_t)0x0300) 00447 #define IS_TIM_LOCK_LEVEL_MORT(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF_MORT) || \ 00448 ((LEVEL) == TIM_LOCKLevel_1_MORT) || \ 00449 ((LEVEL) == TIM_LOCKLevel_2_MORT) || \ 00450 ((LEVEL) == TIM_LOCKLevel_3_MORT)) 00451 /** 00452 * @} 00453 */ 00454 00455 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state 00456 * @{ 00457 */ 00458 00459 #define TIM_OSSIState_Enable_MORT ((uint16_t)0x0400) 00460 #define TIM_OSSIState_Disable_MORT ((uint16_t)0x0000) 00461 #define IS_TIM_OSSI_STATE_MORT(STATE) (((STATE) == TIM_OSSIState_Enable_MORT) || \ 00462 ((STATE) == TIM_OSSIState_Disable_MORT)) 00463 /** 00464 * @} 00465 */ 00466 00467 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state 00468 * @{ 00469 */ 00470 00471 #define TIM_OSSRState_Enable_MORT ((uint16_t)0x0800) 00472 #define TIM_OSSRState_Disable_MORT ((uint16_t)0x0000) 00473 #define IS_TIM_OSSR_STATE_MORT(STATE) (((STATE) == TIM_OSSRState_Enable_MORT) || \ 00474 ((STATE) == TIM_OSSRState_Disable_MORT)) 00475 /** 00476 * @} 00477 */ 00478 00479 /** @defgroup TIM_Output_Compare_Idle_State 00480 * @{ 00481 */ 00482 00483 #define TIM_OCIdleState_Set_MORT ((uint16_t)0x0100) 00484 #define TIM_OCIdleState_Reset_MORT ((uint16_t)0x0000) 00485 #define IS_TIM_OCIDLE_STATE_MORT(STATE) (((STATE) == TIM_OCIdleState_Set_MORT) || \ 00486 ((STATE) == TIM_OCIdleState_Reset_MORT)) 00487 /** 00488 * @} 00489 */ 00490 00491 /** @defgroup TIM_Output_Compare_N_Idle_State 00492 * @{ 00493 */ 00494 00495 #define TIM_OCNIdleState_Set_MORT ((uint16_t)0x0200) 00496 #define TIM_OCNIdleState_Reset_MORT ((uint16_t)0x0000) 00497 #define IS_TIM_OCNIDLE_STATE_MORT(STATE) (((STATE) == TIM_OCNIdleState_Set_MORT) || \ 00498 ((STATE) == TIM_OCNIdleState_Reset_MORT)) 00499 /** 00500 * @} 00501 */ 00502 00503 /** @defgroup TIM_Input_Capture_Polarity 00504 * @{ 00505 */ 00506 00507 #define TIM_ICPolarity_Rising_MORT ((uint16_t)0x0000) 00508 #define TIM_ICPolarity_Falling_MORT ((uint16_t)0x0002) 00509 #define TIM_ICPolarity_BothEdge_MORT ((uint16_t)0x000A) 00510 #define IS_TIM_IC_POLARITY_MORT(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising_MORT) || \ 00511 ((POLARITY) == TIM_ICPolarity_Falling_MORT)|| \ 00512 ((POLARITY) == TIM_ICPolarity_BothEdge_MORT)) 00513 /** 00514 * @} 00515 */ 00516 00517 /** @defgroup TIM_Input_Capture_Selection 00518 * @{ 00519 */ 00520 00521 #define TIM_ICSelection_DirectTI_MORT ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be 00522 connected to IC1, IC2, IC3 or IC4, respectively */ 00523 #define TIM_ICSelection_IndirectTI_MORT ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be 00524 connected to IC2, IC1, IC4 or IC3, respectively. */ 00525 #define TIM_ICSelection_TRC_MORT ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ 00526 #define IS_TIM_IC_SELECTION_MORT(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI_MORT) || \ 00527 ((SELECTION) == TIM_ICSelection_IndirectTI_MORT) || \ 00528 ((SELECTION) == TIM_ICSelection_TRC_MORT)) 00529 /** 00530 * @} 00531 */ 00532 00533 /** @defgroup TIM_Input_Capture_Prescaler 00534 * @{ 00535 */ 00536 00537 #define TIM_ICPSC_DIV1_MORT ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ 00538 #define TIM_ICPSC_DIV2_MORT ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ 00539 #define TIM_ICPSC_DIV4_MORT ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ 00540 #define TIM_ICPSC_DIV8_MORT ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ 00541 #define IS_TIM_IC_PRESCALER_MORT(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1_MORT) || \ 00542 ((PRESCALER) == TIM_ICPSC_DIV2_MORT) || \ 00543 ((PRESCALER) == TIM_ICPSC_DIV4_MORT) || \ 00544 ((PRESCALER) == TIM_ICPSC_DIV8_MORT)) 00545 /** 00546 * @} 00547 */ 00548 00549 /** @defgroup TIM_interrupt_sources 00550 * @{ 00551 */ 00552 00553 #define TIM_IT_Update_MORT ((uint16_t)0x0001) 00554 #define TIM_IT_CC1_MORT ((uint16_t)0x0002) 00555 #define TIM_IT_CC2_MORT ((uint16_t)0x0004) 00556 #define TIM_IT_CC3_MORT ((uint16_t)0x0008) 00557 #define TIM_IT_CC4_MORT ((uint16_t)0x0010) 00558 #define TIM_IT_COM_MORT ((uint16_t)0x0020) 00559 #define TIM_IT_Trigger_MORT ((uint16_t)0x0040) 00560 #define TIM_IT_Break_MORT ((uint16_t)0x0080) 00561 #define IS_TIM_IT_MORT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) 00562 00563 #define IS_TIM_GET_IT_MORT(IT) (((IT) == TIM_IT_Update_MORT) || \ 00564 ((IT) == TIM_IT_CC1_MORT) || \ 00565 ((IT) == TIM_IT_CC2_MORT) || \ 00566 ((IT) == TIM_IT_CC3_MORT) || \ 00567 ((IT) == TIM_IT_CC4_MORT) || \ 00568 ((IT) == TIM_IT_COM_MORT) || \ 00569 ((IT) == TIM_IT_Trigger_MORT) || \ 00570 ((IT) == TIM_IT_Break_MORT)) 00571 /** 00572 * @} 00573 */ 00574 00575 /** @defgroup TIM_DMA_Base_address 00576 * @{ 00577 */ 00578 00579 #define TIM_DMABase_CR1_MORT ((uint16_t)0x0000) 00580 #define TIM_DMABase_CR2_MORT ((uint16_t)0x0001) 00581 #define TIM_DMABase_SMCR_MORT ((uint16_t)0x0002) 00582 #define TIM_DMABase_DIER_MORT ((uint16_t)0x0003) 00583 #define TIM_DMABase_SR_MORT ((uint16_t)0x0004) 00584 #define TIM_DMABase_EGR_MORT ((uint16_t)0x0005) 00585 #define TIM_DMABase_CCMR1_MORT ((uint16_t)0x0006) 00586 #define TIM_DMABase_CCMR2_MORT ((uint16_t)0x0007) 00587 #define TIM_DMABase_CCER_MORT ((uint16_t)0x0008) 00588 #define TIM_DMABase_CNT_MORT ((uint16_t)0x0009) 00589 #define TIM_DMABase_PSC_MORT ((uint16_t)0x000A) 00590 #define TIM_DMABase_ARR_MORT ((uint16_t)0x000B) 00591 #define TIM_DMABase_RCR_MORT ((uint16_t)0x000C) 00592 #define TIM_DMABase_CCR1_MORT ((uint16_t)0x000D) 00593 #define TIM_DMABase_CCR2_MORT ((uint16_t)0x000E) 00594 #define TIM_DMABase_CCR3_MORT ((uint16_t)0x000F) 00595 #define TIM_DMABase_CCR4_MORT ((uint16_t)0x0010) 00596 #define TIM_DMABase_BDTR_MORT ((uint16_t)0x0011) 00597 #define TIM_DMABase_DCR_MORT ((uint16_t)0x0012) 00598 #define TIM_DMABase_OR_MORT ((uint16_t)0x0013) 00599 #define IS_TIM_DMA_BASE_MORT(BASE) (((BASE) == TIM_DMABase_CR1_MORT) || \ 00600 ((BASE) == TIM_DMABase_CR2_MORT) || \ 00601 ((BASE) == TIM_DMABase_SMCR_MORT) || \ 00602 ((BASE) == TIM_DMABase_DIER_MORT) || \ 00603 ((BASE) == TIM_DMABase_SR_MORT) || \ 00604 ((BASE) == TIM_DMABase_EGR_MORT) || \ 00605 ((BASE) == TIM_DMABase_CCMR1_MORT) || \ 00606 ((BASE) == TIM_DMABase_CCMR2_MORT) || \ 00607 ((BASE) == TIM_DMABase_CCER_MORT) || \ 00608 ((BASE) == TIM_DMABase_CNT_MORT) || \ 00609 ((BASE) == TIM_DMABase_PSC_MORT) || \ 00610 ((BASE) == TIM_DMABase_ARR_MORT) || \ 00611 ((BASE) == TIM_DMABase_RCR_MORT) || \ 00612 ((BASE) == TIM_DMABase_CCR1_MORT) || \ 00613 ((BASE) == TIM_DMABase_CCR2_MORT) || \ 00614 ((BASE) == TIM_DMABase_CCR3_MORT) || \ 00615 ((BASE) == TIM_DMABase_CCR4_MORT) || \ 00616 ((BASE) == TIM_DMABase_BDTR_MORT) || \ 00617 ((BASE) == TIM_DMABase_DCR_MORT) || \ 00618 ((BASE) == TIM_DMABase_OR_MORT)) 00619 /** 00620 * @} 00621 */ 00622 00623 /** @defgroup TIM_DMA_Burst_Length 00624 * @{ 00625 */ 00626 00627 #define TIM_DMABurstLength_1Transfer_MORT ((uint16_t)0x0000) 00628 #define TIM_DMABurstLength_2Transfers_MORT ((uint16_t)0x0100) 00629 #define TIM_DMABurstLength_3Transfers_MORT ((uint16_t)0x0200) 00630 #define TIM_DMABurstLength_4Transfers_MORT ((uint16_t)0x0300) 00631 #define TIM_DMABurstLength_5Transfers_MORT ((uint16_t)0x0400) 00632 #define TIM_DMABurstLength_6Transfers_MORT ((uint16_t)0x0500) 00633 #define TIM_DMABurstLength_7Transfers_MORT ((uint16_t)0x0600) 00634 #define TIM_DMABurstLength_8Transfers_MORT ((uint16_t)0x0700) 00635 #define TIM_DMABurstLength_9Transfers_MORT ((uint16_t)0x0800) 00636 #define TIM_DMABurstLength_10Transfers_MORT ((uint16_t)0x0900) 00637 #define TIM_DMABurstLength_11Transfers_MORT ((uint16_t)0x0A00) 00638 #define TIM_DMABurstLength_12Transfers_MORT ((uint16_t)0x0B00) 00639 #define TIM_DMABurstLength_13Transfers_MORT ((uint16_t)0x0C00) 00640 #define TIM_DMABurstLength_14Transfers_MORT ((uint16_t)0x0D00) 00641 #define TIM_DMABurstLength_15Transfers_MORT ((uint16_t)0x0E00) 00642 #define TIM_DMABurstLength_16Transfers_MORT ((uint16_t)0x0F00) 00643 #define TIM_DMABurstLength_17Transfers_MORT ((uint16_t)0x1000) 00644 #define TIM_DMABurstLength_18Transfers_MORT ((uint16_t)0x1100) 00645 #define IS_TIM_DMA_LENGTH_MORT(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer_MORT) || \ 00646 ((LENGTH) == TIM_DMABurstLength_2Transfers_MORT) || \ 00647 ((LENGTH) == TIM_DMABurstLength_3Transfers_MORT) || \ 00648 ((LENGTH) == TIM_DMABurstLength_4Transfers_MORT) || \ 00649 ((LENGTH) == TIM_DMABurstLength_5Transfers_MORT) || \ 00650 ((LENGTH) == TIM_DMABurstLength_6Transfers_MORT) || \ 00651 ((LENGTH) == TIM_DMABurstLength_7Transfers_MORT) || \ 00652 ((LENGTH) == TIM_DMABurstLength_8Transfers_MORT) || \ 00653 ((LENGTH) == TIM_DMABurstLength_9Transfers_MORT) || \ 00654 ((LENGTH) == TIM_DMABurstLength_10Transfers_MORT) || \ 00655 ((LENGTH) == TIM_DMABurstLength_11Transfers_MORT) || \ 00656 ((LENGTH) == TIM_DMABurstLength_12Transfers_MORT) || \ 00657 ((LENGTH) == TIM_DMABurstLength_13Transfers_MORT) || \ 00658 ((LENGTH) == TIM_DMABurstLength_14Transfers_MORT) || \ 00659 ((LENGTH) == TIM_DMABurstLength_15Transfers_MORT) || \ 00660 ((LENGTH) == TIM_DMABurstLength_16Transfers_MORT) || \ 00661 ((LENGTH) == TIM_DMABurstLength_17Transfers_MORT) || \ 00662 ((LENGTH) == TIM_DMABurstLength_18Transfers_MORT)) 00663 /** 00664 * @} 00665 */ 00666 00667 /** @defgroup TIM_DMA_sources 00668 * @{ 00669 */ 00670 00671 #define TIM_DMA_Update_MORT ((uint16_t)0x0100) 00672 #define TIM_DMA_CC1_MORT ((uint16_t)0x0200) 00673 #define TIM_DMA_CC2_MORT ((uint16_t)0x0400) 00674 #define TIM_DMA_CC3_MORT ((uint16_t)0x0800) 00675 #define TIM_DMA_CC4_MORT ((uint16_t)0x1000) 00676 #define TIM_DMA_COM_MORT ((uint16_t)0x2000) 00677 #define TIM_DMA_Trigger_MORT ((uint16_t)0x4000) 00678 #define IS_TIM_DMA_SOURCE_MORT(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) 00679 00680 /** 00681 * @} 00682 */ 00683 00684 /** @defgroup TIM_External_Trigger_Prescaler 00685 * @{ 00686 */ 00687 00688 #define TIM_ExtTRGPSC_OFF_MORT ((uint16_t)0x0000) 00689 #define TIM_ExtTRGPSC_DIV2_MORT ((uint16_t)0x1000) 00690 #define TIM_ExtTRGPSC_DIV4_MORT ((uint16_t)0x2000) 00691 #define TIM_ExtTRGPSC_DIV8_MORT ((uint16_t)0x3000) 00692 #define IS_TIM_EXT_PRESCALER_MORT(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF_MORT) || \ 00693 ((PRESCALER) == TIM_ExtTRGPSC_DIV2_MORT) || \ 00694 ((PRESCALER) == TIM_ExtTRGPSC_DIV4_MORT) || \ 00695 ((PRESCALER) == TIM_ExtTRGPSC_DIV8_MORT)) 00696 /** 00697 * @} 00698 */ 00699 00700 /** @defgroup TIM_Internal_Trigger_Selection 00701 * @{ 00702 */ 00703 00704 #define TIM_TS_ITR0_MORT ((uint16_t)0x0000) 00705 #define TIM_TS_ITR1_MORT ((uint16_t)0x0010) 00706 #define TIM_TS_ITR2_MORT ((uint16_t)0x0020) 00707 #define TIM_TS_ITR3_MORT ((uint16_t)0x0030) 00708 #define TIM_TS_TI1F_ED_MORT ((uint16_t)0x0040) 00709 #define TIM_TS_TI1FP1_MORT ((uint16_t)0x0050) 00710 #define TIM_TS_TI2FP2_MORT ((uint16_t)0x0060) 00711 #define TIM_TS_ETRF_MORT ((uint16_t)0x0070) 00712 #define IS_TIM_TRIGGER_SELECTION_MORT(SELECTION) (((SELECTION) == TIM_TS_ITR0_MORT) || \ 00713 ((SELECTION) == TIM_TS_ITR1_MORT) || \ 00714 ((SELECTION) == TIM_TS_ITR2_MORT) || \ 00715 ((SELECTION) == TIM_TS_ITR3_MORT) || \ 00716 ((SELECTION) == TIM_TS_TI1F_ED_MORT) || \ 00717 ((SELECTION) == TIM_TS_TI1FP1_MORT) || \ 00718 ((SELECTION) == TIM_TS_TI2FP2_MORT) || \ 00719 ((SELECTION) == TIM_TS_ETRF_MORT)) 00720 #define IS_TIM_INTERNAL_TRIGGER_SELECTION_MORT(SELECTION) (((SELECTION) == TIM_TS_ITR0_MORT) || \ 00721 ((SELECTION) == TIM_TS_ITR1_MORT) || \ 00722 ((SELECTION) == TIM_TS_ITR2_MORT) || \ 00723 ((SELECTION) == TIM_TS_ITR3_MORT)) 00724 /** 00725 * @} 00726 */ 00727 00728 /** @defgroup TIM_TIx_External_Clock_Source 00729 * @{ 00730 */ 00731 00732 #define TIM_TIxExternalCLK1Source_TI1_MORT ((uint16_t)0x0050) 00733 #define TIM_TIxExternalCLK1Source_TI2_MORT ((uint16_t)0x0060) 00734 #define TIM_TIxExternalCLK1Source_TI1ED_MORT ((uint16_t)0x0040) 00735 00736 /** 00737 * @} 00738 */ 00739 00740 /** @defgroup TIM_External_Trigger_Polarity 00741 * @{ 00742 */ 00743 #define TIM_ExtTRGPolarity_Inverted_MORT ((uint16_t)0x8000) 00744 #define TIM_ExtTRGPolarity_NonInverted_MORT ((uint16_t)0x0000) 00745 #define IS_TIM_EXT_POLARITY_MORT(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted_MORT) || \ 00746 ((POLARITY) == TIM_ExtTRGPolarity_NonInverted_MORT)) 00747 /** 00748 * @} 00749 */ 00750 00751 /** @defgroup TIM_Prescaler_Reload_Mode 00752 * @{ 00753 */ 00754 00755 #define TIM_PSCReloadMode_Update_MORT ((uint16_t)0x0000) 00756 #define TIM_PSCReloadMode_Immediate_MORT ((uint16_t)0x0001) 00757 #define IS_TIM_PRESCALER_RELOAD_MORT(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update_MORT) || \ 00758 ((RELOAD) == TIM_PSCReloadMode_Immediate_MORT)) 00759 /** 00760 * @} 00761 */ 00762 00763 /** @defgroup TIM_Forced_Action 00764 * @{ 00765 */ 00766 00767 #define TIM_ForcedAction_Active_MORT ((uint16_t)0x0050) 00768 #define TIM_ForcedAction_InActive_MORT ((uint16_t)0x0040) 00769 #define IS_TIM_FORCED_ACTION_MORT(ACTION) (((ACTION) == TIM_ForcedAction_Active_MORT) || \ 00770 ((ACTION) == TIM_ForcedAction_InActive_MORT)) 00771 /** 00772 * @} 00773 */ 00774 00775 /** @defgroup TIM_Encoder_Mode 00776 * @{ 00777 */ 00778 00779 #define TIM_EncoderMode_TI1_MORT ((uint16_t)0x0001) 00780 #define TIM_EncoderMode_TI2_MORT ((uint16_t)0x0002) 00781 #define TIM_EncoderMode_TI12_MORT ((uint16_t)0x0003) 00782 #define IS_TIM_ENCODER_MODE_MORT(MODE) (((MODE) == TIM_EncoderMode_TI1_MORT) || \ 00783 ((MODE) == TIM_EncoderMode_TI2_MORT) || \ 00784 ((MODE) == TIM_EncoderMode_TI12_MORT)) 00785 /** 00786 * @} 00787 */ 00788 00789 00790 /** @defgroup TIM_Event_Source 00791 * @{ 00792 */ 00793 00794 #define TIM_EventSource_Update_MORT ((uint16_t)0x0001) 00795 #define TIM_EventSource_CC1_MORT ((uint16_t)0x0002) 00796 #define TIM_EventSource_CC2_MORT ((uint16_t)0x0004) 00797 #define TIM_EventSource_CC3_MORT ((uint16_t)0x0008) 00798 #define TIM_EventSource_CC4_MORT ((uint16_t)0x0010) 00799 #define TIM_EventSource_COM_MORT ((uint16_t)0x0020) 00800 #define TIM_EventSource_Trigger_MORT ((uint16_t)0x0040) 00801 #define TIM_EventSource_Break_MORT ((uint16_t)0x0080) 00802 #define IS_TIM_EVENT_SOURCE_MORT(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) 00803 00804 /** 00805 * @} 00806 */ 00807 00808 /** @defgroup TIM_Update_Source 00809 * @{ 00810 */ 00811 00812 #define TIM_UpdateSource_Global_MORT ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow 00813 or the setting of UG bit, or an update generation 00814 through the slave mode controller. */ 00815 #define TIM_UpdateSource_Regular_MORT ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ 00816 #define IS_TIM_UPDATE_SOURCE_MORT(SOURCE) (((SOURCE) == TIM_UpdateSource_Global_MORT) || \ 00817 ((SOURCE) == TIM_UpdateSource_Regular_MORT)) 00818 /** 00819 * @} 00820 */ 00821 00822 /** @defgroup TIM_Output_Compare_Preload_State 00823 * @{ 00824 */ 00825 00826 #define TIM_OCPreload_Enable_MORT ((uint16_t)0x0008) 00827 #define TIM_OCPreload_Disable_MORT ((uint16_t)0x0000) 00828 #define IS_TIM_OCPRELOAD_STATE_MORT(STATE) (((STATE) == TIM_OCPreload_Enable_MORT) || \ 00829 ((STATE) == TIM_OCPreload_Disable_MORT)) 00830 /** 00831 * @} 00832 */ 00833 00834 /** @defgroup TIM_Output_Compare_Fast_State 00835 * @{ 00836 */ 00837 00838 #define TIM_OCFast_Enable_MORT ((uint16_t)0x0004) 00839 #define TIM_OCFast_Disable_MORT ((uint16_t)0x0000) 00840 #define IS_TIM_OCFAST_STATE_MORT(STATE) (((STATE) == TIM_OCFast_Enable_MORT) || \ 00841 ((STATE) == TIM_OCFast_Disable_MORT)) 00842 00843 /** 00844 * @} 00845 */ 00846 00847 /** @defgroup TIM_Output_Compare_Clear_State 00848 * @{ 00849 */ 00850 00851 #define TIM_OCClear_Enable_MORT ((uint16_t)0x0080) 00852 #define TIM_OCClear_Disable_MORT ((uint16_t)0x0000) 00853 #define IS_TIM_OCCLEAR_STATE_MORT(STATE) (((STATE) == TIM_OCClear_Enable_MORT) || \ 00854 ((STATE) == TIM_OCClear_Disable_MORT)) 00855 /** 00856 * @} 00857 */ 00858 00859 /** @defgroup TIM_Trigger_Output_Source 00860 * @{ 00861 */ 00862 00863 #define TIM_TRGOSource_Reset_MORT ((uint16_t)0x0000) 00864 #define TIM_TRGOSource_Enable_MORT ((uint16_t)0x0010) 00865 #define TIM_TRGOSource_Update_MORT ((uint16_t)0x0020) 00866 #define TIM_TRGOSource_OC1_MORT ((uint16_t)0x0030) 00867 #define TIM_TRGOSource_OC1Ref_MORT ((uint16_t)0x0040) 00868 #define TIM_TRGOSource_OC2Ref_MORT ((uint16_t)0x0050) 00869 #define TIM_TRGOSource_OC3Ref_MORT ((uint16_t)0x0060) 00870 #define TIM_TRGOSource_OC4Ref_MORT ((uint16_t)0x0070) 00871 #define IS_TIM_TRGO_SOURCE_MORT(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset_MORT) || \ 00872 ((SOURCE) == TIM_TRGOSource_Enable_MORT) || \ 00873 ((SOURCE) == TIM_TRGOSource_Update_MORT) || \ 00874 ((SOURCE) == TIM_TRGOSource_OC1_MORT) || \ 00875 ((SOURCE) == TIM_TRGOSource_OC1Ref_MORT) || \ 00876 ((SOURCE) == TIM_TRGOSource_OC2Ref_MORT) || \ 00877 ((SOURCE) == TIM_TRGOSource_OC3Ref_MORT) || \ 00878 ((SOURCE) == TIM_TRGOSource_OC4Ref_MORT)) 00879 /** 00880 * @} 00881 */ 00882 00883 /** @defgroup TIM_Slave_Mode 00884 * @{ 00885 */ 00886 00887 #define TIM_SlaveMode_Reset_MORT ((uint16_t)0x0004) 00888 #define TIM_SlaveMode_Gated_MORT ((uint16_t)0x0005) 00889 #define TIM_SlaveMode_Trigger_MORT ((uint16_t)0x0006) 00890 #define TIM_SlaveMode_External1_MORT ((uint16_t)0x0007) 00891 #define IS_TIM_SLAVE_MODE_MORT(MODE) (((MODE) == TIM_SlaveMode_Reset_MORT) || \ 00892 ((MODE) == TIM_SlaveMode_Gated_MORT) || \ 00893 ((MODE) == TIM_SlaveMode_Trigger_MORT) || \ 00894 ((MODE) == TIM_SlaveMode_External1_MORT)) 00895 /** 00896 * @} 00897 */ 00898 00899 /** @defgroup TIM_Master_Slave_Mode 00900 * @{ 00901 */ 00902 00903 #define TIM_MasterSlaveMode_Enable_MORT ((uint16_t)0x0080) 00904 #define TIM_MasterSlaveMode_Disable_MORT ((uint16_t)0x0000) 00905 #define IS_TIM_MSM_STATE_MORT(STATE) (((STATE) == TIM_MasterSlaveMode_Enable_MORT) || \ 00906 ((STATE) == TIM_MasterSlaveMode_Disable_MORT)) 00907 /** 00908 * @} 00909 */ 00910 /** @defgroup TIM_Remap 00911 * @{ 00912 */ 00913 00914 #define TIM2_TIM8_TRGO_MORT ((uint16_t)0x0000) 00915 #define TIM2_ETH_PTP_MORT ((uint16_t)0x0400) 00916 #define TIM2_USBFS_SOF_MORT ((uint16_t)0x0800) 00917 #define TIM2_USBHS_SOF_MORT ((uint16_t)0x0C00) 00918 00919 #define TIM5_GPIO_MORT ((uint16_t)0x0000) 00920 #define TIM5_LSI_MORT ((uint16_t)0x0040) 00921 #define TIM5_LSE_MORT ((uint16_t)0x0080) 00922 #define TIM5_RTC_MORT ((uint16_t)0x00C0) 00923 00924 #define TIM11_GPIO_MORT ((uint16_t)0x0000) 00925 #define TIM11_HSE_MORT ((uint16_t)0x0002) 00926 00927 #define IS_TIM_REMAP_MORT(TIM_REMAP) (((TIM_REMAP) == TIM2_TIM8_TRGO_MORT)||\ 00928 ((TIM_REMAP) == TIM2_ETH_PTP_MORT)||\ 00929 ((TIM_REMAP) == TIM2_USBFS_SOF_MORT)||\ 00930 ((TIM_REMAP) == TIM2_USBHS_SOF_MORT)||\ 00931 ((TIM_REMAP) == TIM5_GPIO_MORT)||\ 00932 ((TIM_REMAP) == TIM5_LSI_MORT)||\ 00933 ((TIM_REMAP) == TIM5_LSE_MORT)||\ 00934 ((TIM_REMAP) == TIM5_RTC_MORT)||\ 00935 ((TIM_REMAP) == TIM11_GPIO_MORT)||\ 00936 ((TIM_REMAP) == TIM11_HSE_MORT)) 00937 00938 /** 00939 * @} 00940 */ 00941 /** @defgroup TIM_Flags 00942 * @{ 00943 */ 00944 00945 #define TIM_FLAG_Update_MORT ((uint16_t)0x0001) 00946 #define TIM_FLAG_CC1_MORT ((uint16_t)0x0002) 00947 #define TIM_FLAG_CC2_MORT ((uint16_t)0x0004) 00948 #define TIM_FLAG_CC3_MORT ((uint16_t)0x0008) 00949 #define TIM_FLAG_CC4_MORT ((uint16_t)0x0010) 00950 #define TIM_FLAG_COM_MORT ((uint16_t)0x0020) 00951 #define TIM_FLAG_Trigger_MORT ((uint16_t)0x0040) 00952 #define TIM_FLAG_Break_MORT ((uint16_t)0x0080) 00953 #define TIM_FLAG_CC1OF_MORT ((uint16_t)0x0200) 00954 #define TIM_FLAG_CC2OF_MORT ((uint16_t)0x0400) 00955 #define TIM_FLAG_CC3OF_MORT ((uint16_t)0x0800) 00956 #define TIM_FLAG_CC4OF_MORT ((uint16_t)0x1000) 00957 #define IS_TIM_GET_FLAG_MORT(FLAG) (((FLAG) == TIM_FLAG_Update_MORT) || \ 00958 ((FLAG) == TIM_FLAG_CC1_MORT) || \ 00959 ((FLAG) == TIM_FLAG_CC2_MORT) || \ 00960 ((FLAG) == TIM_FLAG_CC3_MORT) || \ 00961 ((FLAG) == TIM_FLAG_CC4_MORT) || \ 00962 ((FLAG) == TIM_FLAG_COM_MORT) || \ 00963 ((FLAG) == TIM_FLAG_Trigger_MORT) || \ 00964 ((FLAG) == TIM_FLAG_Break_MORT) || \ 00965 ((FLAG) == TIM_FLAG_CC1OF_MORT) || \ 00966 ((FLAG) == TIM_FLAG_CC2OF_MORT) || \ 00967 ((FLAG) == TIM_FLAG_CC3OF_MORT) || \ 00968 ((FLAG) == TIM_FLAG_CC4OF_MORT)) 00969 00970 /** 00971 * @} 00972 */ 00973 00974 /** @defgroup TIM_Input_Capture_Filer_Value 00975 * @{ 00976 */ 00977 00978 #define IS_TIM_IC_FILTER_MORT(ICFILTER) ((ICFILTER) <= 0xF) 00979 /** 00980 * @} 00981 */ 00982 00983 /** @defgroup TIM_External_Trigger_Filter 00984 * @{ 00985 */ 00986 00987 #define IS_TIM_EXT_FILTER_MORT(EXTFILTER) ((EXTFILTER) <= 0xF) 00988 /** 00989 * @} 00990 */ 00991 00992 /** @defgroup TIM_Legacy 00993 * @{ 00994 */ 00995 00996 #define TIM_DMABurstLength_1Byte_MORT TIM_DMABurstLength_1Transfer_MORT 00997 #define TIM_DMABurstLength_2Bytes_MORT TIM_DMABurstLength_2Transfers_MORT 00998 #define TIM_DMABurstLength_3Bytes_MORT TIM_DMABurstLength_3Transfers_MORT 00999 #define TIM_DMABurstLength_4Bytes_MORT TIM_DMABurstLength_4Transfers_MORT 01000 #define TIM_DMABurstLength_5Bytes_MORT TIM_DMABurstLength_5Transfers_MORT 01001 #define TIM_DMABurstLength_6Bytes_MORT TIM_DMABurstLength_6Transfers_MORT 01002 #define TIM_DMABurstLength_7Bytes_MORT TIM_DMABurstLength_7Transfers_MORT 01003 #define TIM_DMABurstLength_8Bytes_MORT TIM_DMABurstLength_8Transfers_MORT 01004 #define TIM_DMABurstLength_9Bytes_MORT TIM_DMABurstLength_9Transfers_MORT 01005 #define TIM_DMABurstLength_10Bytes_MORT TIM_DMABurstLength_10Transfers_MORT 01006 #define TIM_DMABurstLength_11Bytes_MORT TIM_DMABurstLength_11Transfers_MORT 01007 #define TIM_DMABurstLength_12Bytes_MORT TIM_DMABurstLength_12Transfers_MORT 01008 #define TIM_DMABurstLength_13Bytes_MORT TIM_DMABurstLength_13Transfers_MORT 01009 #define TIM_DMABurstLength_14Bytes_MORT TIM_DMABurstLength_14Transfers_MORT 01010 #define TIM_DMABurstLength_15Bytes_MORT TIM_DMABurstLength_15Transfers_MORT 01011 #define TIM_DMABurstLength_16Bytes_MORT TIM_DMABurstLength_16Transfers_MORT 01012 #define TIM_DMABurstLength_17Bytes_MORT TIM_DMABurstLength_17Transfers_MORT 01013 #define TIM_DMABurstLength_18Bytes_MORT TIM_DMABurstLength_18Transfers_MORT 01014 /** 01015 * @} 01016 */ 01017 01018 /** 01019 * @} 01020 */ 01021 01022 /* Exported macro ------------------------------------------------------------*/ 01023 /* Exported functions --------------------------------------------------------*/ 01024 01025 /* TimeBase management ********************************************************/ 01026 void TIM_DeInit_mort(TIM_TypeDef_mort* TIMx); 01027 void TIM_TimeBaseInit_mort(TIM_TypeDef_mort* TIMx, TIM_TimeBaseInitTypeDef_mort* TIM_TimeBaseInitStruct); 01028 void TIM_TimeBaseStructInit_mort(TIM_TimeBaseInitTypeDef_mort* TIM_TimeBaseInitStruct); 01029 void TIM_PrescalerConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); 01030 void TIM_CounterModeConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_CounterMode); 01031 void TIM_SetCounter_mort(TIM_TypeDef_mort* TIMx, uint32_t Counter); 01032 void TIM_SetAutoreload_mort(TIM_TypeDef_mort* TIMx, uint32_t Autoreload); 01033 uint32_t TIM_GetCounter_mort(TIM_TypeDef_mort* TIMx); 01034 uint16_t TIM_GetPrescaler_mort(TIM_TypeDef_mort* TIMx); 01035 void TIM_UpdateDisableConfig_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState); 01036 void TIM_UpdateRequestConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_UpdateSource); 01037 void TIM_ARRPreloadConfig_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState); 01038 void TIM_SelectOnePulseMode_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OPMode); 01039 void TIM_SetClockDivision_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_CKD); 01040 void TIM_Cmd_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState); 01041 01042 /* Output Compare management **************************************************/ 01043 void TIM_OC1Init_mort(TIM_TypeDef_mort* TIMx, TIM_OCInitTypeDef_mort* TIM_OCInitStruct); 01044 void TIM_OC2Init_mort(TIM_TypeDef_mort* TIMx, TIM_OCInitTypeDef_mort* TIM_OCInitStruct); 01045 void TIM_OC3Init_mort(TIM_TypeDef_mort* TIMx, TIM_OCInitTypeDef_mort* TIM_OCInitStruct); 01046 void TIM_OC4Init_mort(TIM_TypeDef_mort* TIMx, TIM_OCInitTypeDef_mort* TIM_OCInitStruct); 01047 void TIM_OCStructInit_mort(TIM_OCInitTypeDef_mort* TIM_OCInitStruct); 01048 void TIM_SelectOCxM_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); 01049 void TIM_SetCompare1_mort(TIM_TypeDef_mort* TIMx, uint32_t Compare1); 01050 void TIM_SetCompare2_mort(TIM_TypeDef_mort* TIMx, uint32_t Compare2); 01051 void TIM_SetCompare3_mort(TIM_TypeDef_mort* TIMx, uint32_t Compare3); 01052 void TIM_SetCompare4_mort(TIM_TypeDef_mort* TIMx, uint32_t Compare4); 01053 void TIM_ForcedOC1Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ForcedAction); 01054 void TIM_ForcedOC2Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ForcedAction); 01055 void TIM_ForcedOC3Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ForcedAction); 01056 void TIM_ForcedOC4Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ForcedAction); 01057 void TIM_OC1PreloadConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPreload); 01058 void TIM_OC2PreloadConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPreload); 01059 void TIM_OC3PreloadConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPreload); 01060 void TIM_OC4PreloadConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPreload); 01061 void TIM_OC1FastConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCFast); 01062 void TIM_OC2FastConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCFast); 01063 void TIM_OC3FastConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCFast); 01064 void TIM_OC4FastConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCFast); 01065 void TIM_ClearOC1Ref_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCClear); 01066 void TIM_ClearOC2Ref_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCClear); 01067 void TIM_ClearOC3Ref_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCClear); 01068 void TIM_ClearOC4Ref_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCClear); 01069 void TIM_OC1PolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPolarity); 01070 void TIM_OC1NPolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCNPolarity); 01071 void TIM_OC2PolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPolarity); 01072 void TIM_OC2NPolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCNPolarity); 01073 void TIM_OC3PolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPolarity); 01074 void TIM_OC3NPolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCNPolarity); 01075 void TIM_OC4PolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPolarity); 01076 void TIM_CCxCmd_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); 01077 void TIM_CCxNCmd_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); 01078 01079 /* Input Capture management ***************************************************/ 01080 void TIM_ICInit_mort(TIM_TypeDef_mort* TIMx, TIM_ICInitTypeDef_mort* TIM_ICInitStruct); 01081 void TIM_ICStructInit_mort(TIM_ICInitTypeDef_mort* TIM_ICInitStruct); 01082 void TIM_PWMIConfig_mort(TIM_TypeDef_mort* TIMx, TIM_ICInitTypeDef_mort* TIM_ICInitStruct); 01083 uint32_t TIM_GetCapture1_mort(TIM_TypeDef_mort* TIMx); 01084 uint32_t TIM_GetCapture2_mort(TIM_TypeDef_mort* TIMx); 01085 uint32_t TIM_GetCapture3_mort(TIM_TypeDef_mort* TIMx); 01086 uint32_t TIM_GetCapture4_mort(TIM_TypeDef_mort* TIMx); 01087 void TIM_SetIC1Prescaler_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPSC); 01088 void TIM_SetIC2Prescaler_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPSC); 01089 void TIM_SetIC3Prescaler_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPSC); 01090 void TIM_SetIC4Prescaler_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPSC); 01091 01092 /* Advanced-control timers (TIM1_MORT and TIM8_MORT) specific features ******************/ 01093 void TIM_BDTRConfig_mort(TIM_TypeDef_mort* TIMx, TIM_BDTRInitTypeDef_mort *TIM_BDTRInitStruct); 01094 void TIM_BDTRStructInit_mort(TIM_BDTRInitTypeDef_mort* TIM_BDTRInitStruct); 01095 void TIM_CtrlPWMOutputs_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState); 01096 void TIM_SelectCOM_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState); 01097 void TIM_CCPreloadControl_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState); 01098 01099 /* Interrupts, DMA and flags management ***************************************/ 01100 void TIM_ITConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_IT, FunctionalState NewState); 01101 void TIM_GenerateEvent_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_EventSource); 01102 FlagStatus TIM_GetFlagStatus_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_FLAG); 01103 void TIM_ClearFlag_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_FLAG); 01104 ITStatus TIM_GetITStatus_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_IT); 01105 void TIM_ClearITPendingBit_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_IT); 01106 void TIM_DMAConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); 01107 void TIM_DMACmd_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); 01108 void TIM_SelectCCDMA_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState); 01109 01110 /* Clocks management **********************************************************/ 01111 void TIM_InternalClockConfig_mort(TIM_TypeDef_mort* TIMx); 01112 void TIM_ITRxExternalClockConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_InputTriggerSource); 01113 void TIM_TIxExternalClockConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_TIxExternalCLKSource, 01114 uint16_t TIM_ICPolarity, uint16_t ICFilter); 01115 void TIM_ETRClockMode1Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, 01116 uint16_t ExtTRGFilter); 01117 void TIM_ETRClockMode2Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ExtTRGPrescaler, 01118 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); 01119 01120 /* Synchronization management *************************************************/ 01121 void TIM_SelectInputTrigger_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_InputTriggerSource); 01122 void TIM_SelectOutputTrigger_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_TRGOSource); 01123 void TIM_SelectSlaveMode_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_SlaveMode); 01124 void TIM_SelectMasterSlaveMode_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_MasterSlaveMode); 01125 void TIM_ETRConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, 01126 uint16_t ExtTRGFilter); 01127 01128 /* Specific interface management **********************************************/ 01129 void TIM_EncoderInterfaceConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_EncoderMode, 01130 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); 01131 void TIM_SelectHallSensor_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState); 01132 01133 /* Specific remapping management **********************************************/ 01134 void TIM_RemapConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_Remap); 01135 01136 #ifdef __cplusplus 01137 } 01138 #endif 01139 01140 #endif /*__STM32F4xx_TIM_H */ 01141 01142 /** 01143 * @} 01144 */ 01145 01146 /** 01147 * @} 01148 */ 01149 01150 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 01151 01152 01153 01154 01155 01156
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