stm32f4xx_syscfg_mort.c

00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_syscfg.c
00004   * @author  MCD Application Team
00005   * @version V1.8.0
00006   * @date    04-November-2016
00007   * @brief   This file provides firmware functions to manage the SYSCFG_MORT peripheral.
00008   *
00009  @verbatim
00010     
00011  ===============================================================================
00012                      ##### How to use this driver #####
00013  ===============================================================================
00014     [..] This driver provides functions for:
00015             
00016        (#) Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig()
00017             
00018        (#) Swapping the internal flash Bank1 and Bank2 this features is only visible for 
00019            STM32F42xxx/43xxx devices Devices. 
00020                 
00021        (#) Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig_mort()
00022               
00023        (#) Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig_mort()
00024   
00025        -@- SYSCFG_MORT APB clock must be enabled to get write access to SYSCFG_MORT registers,
00026            using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
00027                    
00028  @endverbatim      
00029   ******************************************************************************
00030   * @attention
00031   *
00032   * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
00033   *
00034   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00035   * You may not use this file except in compliance with the License.
00036   * You may obtain a copy of the License at:
00037   *
00038   *        http://www.st.com/software_license_agreement_liberty_v2
00039   *
00040   * Unless required by applicable law or agreed to in writing, software 
00041   * distributed under the License is distributed on an "AS IS" BASIS, 
00042   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00043   * See the License for the specific language governing permissions and
00044   * limitations under the License.
00045   *
00046   ******************************************************************************
00047   */
00048 
00049 /* Includes ------------------------------------------------------------------*/
00050 #include "stm32f4xx_syscfg_mort.h"
00051 #include "stm32f4xx_rcc_mort.h"
00052 
00053 /** @addtogroup STM32F4xx_StdPeriph_Driver
00054   * @{
00055   */
00056 
00057 /** @defgroup SYSCFG_MORT 
00058   * @brief SYSCFG_MORT driver modules
00059   * @{
00060   */ 
00061 
00062 /* Private typedef -----------------------------------------------------------*/
00063 /* Private define ------------------------------------------------------------*/
00064 /* ------------ RCC registers bit address in the alias region ----------- */
00065 #define SYSCFG_OFFSET_MORT             (SYSCFG_BASE_MORT - PERIPH_BASE_MORT)
00066 /* ---  MEMRMP Register ---*/ 
00067 /* Alias word address of UFB_MODE bit */ 
00068 #define MEMRMP_OFFSET_MORT             SYSCFG_OFFSET_MORT 
00069 #define UFB_MODE_BitNumber_MORT        ((uint8_t)0x8) 
00070 #define UFB_MODE_BB_MORT               (PERIPH_BB_BASE + (MEMRMP_OFFSET_MORT * 32) + (UFB_MODE_BitNumber_MORT * 4)) 
00071     
00072 /* ---  PMC Register ---*/ 
00073 /* Alias word address of MII_RMII_SEL bit */ 
00074 #define PMC_OFFSET_MORT                (SYSCFG_OFFSET_MORT + 0x04) 
00075 #define MII_RMII_SEL_BitNumber_MORT    ((uint8_t)0x17) 
00076 #define PMC_MII_RMII_SEL_BB_MORT       (PERIPH_BB_BASE + (PMC_OFFSET_MORT * 32) + (MII_RMII_SEL_BitNumber_MORT * 4)) 
00077     
00078 /* ---  CMPCR Register ---*/ 
00079 /* Alias word address of CMP_PD bit */ 
00080 #define CMPCR_OFFSET_MORT              (SYSCFG_OFFSET_MORT + 0x20) 
00081 #define CMP_PD_BitNumber_MORT          ((uint8_t)0x00) 
00082 #define CMPCR_CMP_PD_BB_MORT           (PERIPH_BB_BASE + (CMPCR_OFFSET_MORT * 32) + (CMP_PD_BitNumber_MORT * 4)) 
00083 
00084 /* ---  MCHDLYCR Register ---*/ 
00085 /* Alias word address of BSCKSEL bit */ 
00086 #define MCHDLYCR_OFFSET_MORT            (SYSCFG_OFFSET_MORT + 0x30) 
00087 #define BSCKSEL_BIT_NUMBER_MORT         POSITION_VAL(SYSCFG_MCHDLYCR_BSCKSEL)
00088 #define MCHDLYCR_BSCKSEL_BB_MORT        (uint32_t)(PERIPH_BB_BASE + (MCHDLYCR_OFFSET_MORT * 32) + (BSCKSEL_BIT_NUMBER_MORT * 4))
00089 
00090 /* Private macro -------------------------------------------------------------*/
00091 /* Private variables ---------------------------------------------------------*/
00092 /* Private function prototypes -----------------------------------------------*/
00093 /* Private functions ---------------------------------------------------------*/
00094 
00095 /** @defgroup SYSCFG_Private_Functions
00096   * @{
00097   */ 
00098 
00099 /**
00100   * @brief  Deinitializes the Alternate Functions (remap and EXTI configuration)
00101   *   registers to their default reset values.
00102   * @param  None
00103   * @retval None
00104   */
00105 void SYSCFG_DeInit_mort(void)
00106 {
00107    RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE);
00108    RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE);
00109 }
00110 
00111 
00112 /**
00113   * @brief  Selects the GPIO pin used as EXTI Line.
00114   * @param  EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for
00115   *          EXTI lines where x can be (A..K) for STM32F42xxx/43xxx devices, (A..I) 
00116   *          for STM32F405xx/407xx and STM32F415xx/417xx devices or (A, B, C, D and H)
00117   *          for STM32401xx devices.  
00118   *            
00119   * @param  EXTI_PinSourcex: specifies the EXTI line to be configured.
00120   *           This parameter can be EXTI_PinSourcex where x can be (0..15, except
00121   *           for EXTI_PortSourceGPIOI_MORT x can be (0..11) for STM32F405xx/407xx
00122   *           and STM32F405xx/407xx devices and for EXTI_PortSourceGPIOK_MORT x can   
00123   *           be (0..7) for STM32F42xxx/43xxx devices. 
00124   *             
00125   * @retval None
00126   */
00127 void SYSCFG_EXTILineConfig_mort(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
00128 {
00129   uint32_t tmp = 0x00;
00130 
00131   /* Check the parameters */
00132   assert_param(IS_EXTI_PORT_SOURCE_MORT(EXTI_PortSourceGPIOx));
00133   assert_param(IS_EXTI_PIN_SOURCE_MORT(EXTI_PinSourcex));
00134 
00135   tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
00136   SYSCFG_MORT->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
00137   SYSCFG_MORT->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
00138 }
00139 
00140 /**
00141   * @brief  Selects the ETHERNET media interface 
00142   * @param  SYSCFG_ETH_MediaInterface: specifies the Media Interface mode. 
00143   *          This parameter can be one of the following values: 
00144   *            @arg SYSCFG_ETH_MediaInterface_MII_MORT: MII mode selected
00145   *            @arg SYSCFG_ETH_MediaInterface_RMII_MORT: RMII mode selected 
00146   * @retval None 
00147   */
00148 void SYSCFG_ETH_MediaInterfaceConfig_mort(uint32_t SYSCFG_ETH_MediaInterface) 
00149 { 
00150   assert_param(IS_SYSCFG_ETH_MEDIA_INTERFACE_MORT(SYSCFG_ETH_MediaInterface)); 
00151   /* Configure MII_RMII selection bit */ 
00152   *(__IO uint32_t *) PMC_MII_RMII_SEL_BB_MORT = SYSCFG_ETH_MediaInterface; 
00153 }
00154 
00155 /**
00156   * @brief  Enables or disables the I/O Compensation Cell.
00157   * @note   The I/O compensation cell can be used only when the device supply
00158   *         voltage ranges from 2.4 to 3.6 V.  
00159   * @param  NewState: new state of the I/O Compensation Cell.
00160   *          This parameter can be one of the following values:
00161   *            @arg ENABLE: I/O compensation cell enabled  
00162   *            @arg DISABLE: I/O compensation cell power-down mode  
00163   * @retval None
00164   */
00165 void SYSCFG_CompensationCellCmd_mort(FunctionalState NewState)
00166 {
00167   /* Check the parameters */
00168   assert_param(IS_FUNCTIONAL_STATE(NewState));
00169 
00170   *(__IO uint32_t *) CMPCR_CMP_PD_BB_MORT = (uint32_t)NewState;
00171 }
00172 
00173 /**
00174   * @brief  Checks whether the I/O Compensation Cell ready flag is set or not.
00175   * @param  None
00176   * @retval The new state of the I/O Compensation Cell ready flag (SET or RESET)
00177   */
00178 FlagStatus SYSCFG_GetCompensationCellStatus_mort(void)
00179 {
00180   FlagStatus bitstatus = RESET;
00181     
00182   if ((SYSCFG_MORT->CMPCR & SYSCFG_CMPCR_READY ) != (uint32_t)RESET)
00183   {
00184     bitstatus = SET;
00185   }
00186   else
00187   {
00188     bitstatus = RESET;
00189   }
00190   return bitstatus;
00191 }
00192 
00193 
00194 
00195 
00196 /**
00197   * @}
00198   */
00199 
00200 /**
00201   * @}
00202   */
00203 
00204 /**
00205   * @}
00206   */
00207 
00208 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/   
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