Rajath Ravi
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ravi_blinkycode
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stm32f4xx_dma_mort.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_dma_mort.h 00004 * @author MCD Application Team 00005 * @version V1.8.0 00006 * @date 04-November-2016 00007 * @brief This file contains all the functions prototypes for the DMA firmware 00008 * library. 00009 ****************************************************************************** 00010 * @attention 00011 * 00012 * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2> 00013 * 00014 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 00015 * You may not use this file except in compliance with the License. 00016 * You may obtain a copy of the License at: 00017 * 00018 * http://www.st.com/software_license_agreement_liberty_v2 00019 * 00020 * Unless required by applicable law or agreed to in writing, software 00021 * distributed under the License is distributed on an "AS IS" BASIS, 00022 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00023 * See the License for the specific language governing permissions and 00024 * limitations under the License. 00025 * 00026 ****************************************************************************** 00027 */ 00028 00029 /* Define to prevent recursive inclusion -------------------------------------*/ 00030 #ifndef __STM32F4xx_DMA_H_MORT 00031 #define __STM32F4xx_DMA_H_MORT 00032 00033 #ifdef __cplusplus 00034 extern "C" { 00035 #endif 00036 00037 /* Includes ------------------------------------------------------------------*/ 00038 #include "stm32f4xx_mort2.h" 00039 00040 /** @addtogroup STM32F4xx_StdPeriph_Driver 00041 * @{ 00042 */ 00043 00044 /** @addtogroup DMA 00045 * @{ 00046 */ 00047 00048 /* Exported types ------------------------------------------------------------*/ 00049 00050 /** 00051 * @brief DMA Init structure definition 00052 */ 00053 00054 typedef struct 00055 { 00056 uint32_t DMA_Channel; /*!< Specifies the channel used for the specified stream. 00057 This parameter can be a value of @ref DMA_channel */ 00058 00059 uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Streamx. */ 00060 00061 uint32_t DMA_Memory0BaseAddr; /*!< Specifies the memory 0 base address for DMAy Streamx. 00062 This memory is the default memory used when double buffer mode is 00063 not enabled. */ 00064 00065 uint32_t DMA_DIR; /*!< Specifies if the data will be transferred from memory to peripheral, 00066 from memory to memory or from peripheral to memory. 00067 This parameter can be a value of @ref DMA_data_transfer_direction */ 00068 00069 uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Stream. 00070 The data unit is equal to the configuration set in DMA_PeripheralDataSize 00071 or DMA_MemoryDataSize members depending in the transfer direction. */ 00072 00073 uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 00074 This parameter can be a value of @ref DMA_peripheral_incremented_mode */ 00075 00076 uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register should be incremented or not. 00077 This parameter can be a value of @ref DMA_memory_incremented_mode */ 00078 00079 uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. 00080 This parameter can be a value of @ref DMA_peripheral_data_size */ 00081 00082 uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. 00083 This parameter can be a value of @ref DMA_memory_data_size */ 00084 00085 uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Streamx. 00086 This parameter can be a value of @ref DMA_circular_normal_mode 00087 @note The circular buffer mode cannot be used if the memory-to-memory 00088 data transfer is configured on the selected Stream */ 00089 00090 uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Streamx. 00091 This parameter can be a value of @ref DMA_priority_level */ 00092 00093 uint32_t DMA_FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified Stream. 00094 This parameter can be a value of @ref DMA_fifo_direct_mode 00095 @note The Direct mode (FIFO mode disabled) cannot be used if the 00096 memory-to-memory data transfer is configured on the selected Stream */ 00097 00098 uint32_t DMA_FIFOThreshold; /*!< Specifies the FIFO threshold level. 00099 This parameter can be a value of @ref DMA_fifo_threshold_level */ 00100 00101 uint32_t DMA_MemoryBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. 00102 It specifies the amount of data to be transferred in a single non interruptable 00103 transaction. This parameter can be a value of @ref DMA_memory_burst 00104 @note The burst mode is possible only if the address Increment mode is enabled. */ 00105 00106 uint32_t DMA_PeripheralBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. 00107 It specifies the amount of data to be transferred in a single non interruptable 00108 transaction. This parameter can be a value of @ref DMA_peripheral_burst 00109 @note The burst mode is possible only if the address Increment mode is enabled. */ 00110 }DMA_InitTypeDef_mort; 00111 00112 /* Exported constants --------------------------------------------------------*/ 00113 00114 /** @defgroup DMA_Exported_Constants 00115 * @{ 00116 */ 00117 00118 #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \ 00119 ((PERIPH) == DMA1_Stream1) || \ 00120 ((PERIPH) == DMA1_Stream2) || \ 00121 ((PERIPH) == DMA1_Stream3) || \ 00122 ((PERIPH) == DMA1_Stream4) || \ 00123 ((PERIPH) == DMA1_Stream5) || \ 00124 ((PERIPH) == DMA1_Stream6) || \ 00125 ((PERIPH) == DMA1_Stream7) || \ 00126 ((PERIPH) == DMA2_Stream0) || \ 00127 ((PERIPH) == DMA2_Stream1) || \ 00128 ((PERIPH) == DMA2_Stream2) || \ 00129 ((PERIPH) == DMA2_Stream3) || \ 00130 ((PERIPH) == DMA2_Stream4) || \ 00131 ((PERIPH) == DMA2_Stream5) || \ 00132 ((PERIPH) == DMA2_Stream6) || \ 00133 ((PERIPH) == DMA2_Stream7)) 00134 00135 #define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1_MORT) || \ 00136 ((CONTROLLER) == DMA2_MORT)) 00137 00138 /** @defgroup DMA_channel 00139 * @{ 00140 */ 00141 #define DMA_Channel_0 ((uint32_t)0x00000000) 00142 #define DMA_Channel_1 ((uint32_t)0x02000000) 00143 #define DMA_Channel_2 ((uint32_t)0x04000000) 00144 #define DMA_Channel_3 ((uint32_t)0x06000000) 00145 #define DMA_Channel_4 ((uint32_t)0x08000000) 00146 #define DMA_Channel_5 ((uint32_t)0x0A000000) 00147 #define DMA_Channel_6 ((uint32_t)0x0C000000) 00148 #define DMA_Channel_7 ((uint32_t)0x0E000000) 00149 00150 #define IS_DMA_CHANNEL_MORT(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \ 00151 ((CHANNEL) == DMA_Channel_1) || \ 00152 ((CHANNEL) == DMA_Channel_2) || \ 00153 ((CHANNEL) == DMA_Channel_3) || \ 00154 ((CHANNEL) == DMA_Channel_4) || \ 00155 ((CHANNEL) == DMA_Channel_5) || \ 00156 ((CHANNEL) == DMA_Channel_6) || \ 00157 ((CHANNEL) == DMA_Channel_7)) 00158 /** 00159 * @} 00160 */ 00161 00162 00163 /** @defgroup DMA_data_transfer_direction 00164 * @{ 00165 */ 00166 #define DMA_DIR_PeripheralToMemory ((uint32_t)0x00000000) 00167 #define DMA_DIR_MemoryToPeripheral ((uint32_t)0x00000040) 00168 #define DMA_DIR_MemoryToMemory ((uint32_t)0x00000080) 00169 00170 #define IS_DMA_DIRECTION_MORT(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \ 00171 ((DIRECTION) == DMA_DIR_MemoryToPeripheral) || \ 00172 ((DIRECTION) == DMA_DIR_MemoryToMemory)) 00173 /** 00174 * @} 00175 */ 00176 00177 00178 /** @defgroup DMA_data_buffer_size 00179 * @{ 00180 */ 00181 #define IS_DMA_BUFFER_SIZE_MORT(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) 00182 /** 00183 * @} 00184 */ 00185 00186 00187 /** @defgroup DMA_peripheral_incremented_mode 00188 * @{ 00189 */ 00190 #define DMA_PeripheralInc_Enable ((uint32_t)0x00000200) 00191 #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) 00192 00193 #define IS_DMA_PERIPHERAL_INC_STATE_MORT(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ 00194 ((STATE) == DMA_PeripheralInc_Disable)) 00195 /** 00196 * @} 00197 */ 00198 00199 00200 /** @defgroup DMA_memory_incremented_mode 00201 * @{ 00202 */ 00203 #define DMA_MemoryInc_Enable ((uint32_t)0x00000400) 00204 #define DMA_MemoryInc_Disable ((uint32_t)0x00000000) 00205 00206 #define IS_DMA_MEMORY_INC_STATE_MORT(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ 00207 ((STATE) == DMA_MemoryInc_Disable)) 00208 /** 00209 * @} 00210 */ 00211 00212 00213 /** @defgroup DMA_peripheral_data_size 00214 * @{ 00215 */ 00216 #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) 00217 #define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000800) 00218 #define DMA_PeripheralDataSize_Word ((uint32_t)0x00001000) 00219 00220 #define IS_DMA_PERIPHERAL_DATA_SIZE_MORT(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ 00221 ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ 00222 ((SIZE) == DMA_PeripheralDataSize_Word)) 00223 /** 00224 * @} 00225 */ 00226 00227 00228 /** @defgroup DMA_memory_data_size 00229 * @{ 00230 */ 00231 #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) 00232 #define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00002000) 00233 #define DMA_MemoryDataSize_Word ((uint32_t)0x00004000) 00234 00235 #define IS_DMA_MEMORY_DATA_SIZE_MORT(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ 00236 ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ 00237 ((SIZE) == DMA_MemoryDataSize_Word )) 00238 /** 00239 * @} 00240 */ 00241 00242 00243 /** @defgroup DMA_circular_normal_mode 00244 * @{ 00245 */ 00246 #define DMA_Mode_Normal ((uint32_t)0x00000000) 00247 #define DMA_Mode_Circular ((uint32_t)0x00000100) 00248 00249 #define IS_DMA_MODE_MORT(MODE) (((MODE) == DMA_Mode_Normal ) || \ 00250 ((MODE) == DMA_Mode_Circular)) 00251 /** 00252 * @} 00253 */ 00254 00255 00256 /** @defgroup DMA_priority_level 00257 * @{ 00258 */ 00259 #define DMA_Priority_Low ((uint32_t)0x00000000) 00260 #define DMA_Priority_Medium ((uint32_t)0x00010000) 00261 #define DMA_Priority_High ((uint32_t)0x00020000) 00262 #define DMA_Priority_VeryHigh ((uint32_t)0x00030000) 00263 00264 #define IS_DMA_PRIORITY_MORT(PRIORITY) (((PRIORITY) == DMA_Priority_Low ) || \ 00265 ((PRIORITY) == DMA_Priority_Medium) || \ 00266 ((PRIORITY) == DMA_Priority_High) || \ 00267 ((PRIORITY) == DMA_Priority_VeryHigh)) 00268 /** 00269 * @} 00270 */ 00271 00272 00273 /** @defgroup DMA_fifo_direct_mode 00274 * @{ 00275 */ 00276 #define DMA_FIFOMode_Disable ((uint32_t)0x00000000) 00277 #define DMA_FIFOMode_Enable ((uint32_t)0x00000004) 00278 00279 #define IS_DMA_FIFO_MODE_STATE_MORT(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \ 00280 ((STATE) == DMA_FIFOMode_Enable)) 00281 /** 00282 * @} 00283 */ 00284 00285 00286 /** @defgroup DMA_fifo_threshold_level 00287 * @{ 00288 */ 00289 #define DMA_FIFOThreshold_1QuarterFull ((uint32_t)0x00000000) 00290 #define DMA_FIFOThreshold_HalfFull ((uint32_t)0x00000001) 00291 #define DMA_FIFOThreshold_3QuartersFull ((uint32_t)0x00000002) 00292 #define DMA_FIFOThreshold_Full ((uint32_t)0x00000003) 00293 00294 #define IS_DMA_FIFO_THRESHOLD_MORT(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \ 00295 ((THRESHOLD) == DMA_FIFOThreshold_HalfFull) || \ 00296 ((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \ 00297 ((THRESHOLD) == DMA_FIFOThreshold_Full)) 00298 /** 00299 * @} 00300 */ 00301 00302 00303 /** @defgroup DMA_memory_burst 00304 * @{ 00305 */ 00306 #define DMA_MemoryBurst_Single ((uint32_t)0x00000000) 00307 #define DMA_MemoryBurst_INC4 ((uint32_t)0x00800000) 00308 #define DMA_MemoryBurst_INC8 ((uint32_t)0x01000000) 00309 #define DMA_MemoryBurst_INC16 ((uint32_t)0x01800000) 00310 00311 #define IS_DMA_MEMORY_BURST_MORT(BURST) (((BURST) == DMA_MemoryBurst_Single) || \ 00312 ((BURST) == DMA_MemoryBurst_INC4) || \ 00313 ((BURST) == DMA_MemoryBurst_INC8) || \ 00314 ((BURST) == DMA_MemoryBurst_INC16)) 00315 /** 00316 * @} 00317 */ 00318 00319 00320 /** @defgroup DMA_peripheral_burst 00321 * @{ 00322 */ 00323 #define DMA_PeripheralBurst_Single ((uint32_t)0x00000000) 00324 #define DMA_PeripheralBurst_INC4 ((uint32_t)0x00200000) 00325 #define DMA_PeripheralBurst_INC8 ((uint32_t)0x00400000) 00326 #define DMA_PeripheralBurst_INC16 ((uint32_t)0x00600000) 00327 00328 #define IS_DMA_PERIPHERAL_BURST_MORT(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \ 00329 ((BURST) == DMA_PeripheralBurst_INC4) || \ 00330 ((BURST) == DMA_PeripheralBurst_INC8) || \ 00331 ((BURST) == DMA_PeripheralBurst_INC16)) 00332 /** 00333 * @} 00334 */ 00335 00336 00337 /** @defgroup DMA_fifo_status_level 00338 * @{ 00339 */ 00340 #define DMA_FIFOStatus_Less1QuarterFull ((uint32_t)0x00000000 << 3) 00341 #define DMA_FIFOStatus_1QuarterFull ((uint32_t)0x00000001 << 3) 00342 #define DMA_FIFOStatus_HalfFull ((uint32_t)0x00000002 << 3) 00343 #define DMA_FIFOStatus_3QuartersFull ((uint32_t)0x00000003 << 3) 00344 #define DMA_FIFOStatus_Empty ((uint32_t)0x00000004 << 3) 00345 #define DMA_FIFOStatus_Full ((uint32_t)0x00000005 << 3) 00346 00347 #define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \ 00348 ((STATUS) == DMA_FIFOStatus_HalfFull) || \ 00349 ((STATUS) == DMA_FIFOStatus_1QuarterFull) || \ 00350 ((STATUS) == DMA_FIFOStatus_3QuartersFull) || \ 00351 ((STATUS) == DMA_FIFOStatus_Full) || \ 00352 ((STATUS) == DMA_FIFOStatus_Empty)) 00353 /** 00354 * @} 00355 */ 00356 00357 /** @defgroup DMA_flags_definition 00358 * @{ 00359 */ 00360 #define DMA_FLAG_FEIF0 ((uint32_t)0x10800001) 00361 #define DMA_FLAG_DMEIF0 ((uint32_t)0x10800004) 00362 #define DMA_FLAG_TEIF0 ((uint32_t)0x10000008) 00363 #define DMA_FLAG_HTIF0 ((uint32_t)0x10000010) 00364 #define DMA_FLAG_TCIF0 ((uint32_t)0x10000020) 00365 #define DMA_FLAG_FEIF1 ((uint32_t)0x10000040) 00366 #define DMA_FLAG_DMEIF1 ((uint32_t)0x10000100) 00367 #define DMA_FLAG_TEIF1 ((uint32_t)0x10000200) 00368 #define DMA_FLAG_HTIF1 ((uint32_t)0x10000400) 00369 #define DMA_FLAG_TCIF1 ((uint32_t)0x10000800) 00370 #define DMA_FLAG_FEIF2 ((uint32_t)0x10010000) 00371 #define DMA_FLAG_DMEIF2 ((uint32_t)0x10040000) 00372 #define DMA_FLAG_TEIF2 ((uint32_t)0x10080000) 00373 #define DMA_FLAG_HTIF2 ((uint32_t)0x10100000) 00374 #define DMA_FLAG_TCIF2 ((uint32_t)0x10200000) 00375 #define DMA_FLAG_FEIF3 ((uint32_t)0x10400000) 00376 #define DMA_FLAG_DMEIF3 ((uint32_t)0x11000000) 00377 #define DMA_FLAG_TEIF3 ((uint32_t)0x12000000) 00378 #define DMA_FLAG_HTIF3 ((uint32_t)0x14000000) 00379 #define DMA_FLAG_TCIF3 ((uint32_t)0x18000000) 00380 #define DMA_FLAG_FEIF4 ((uint32_t)0x20000001) 00381 #define DMA_FLAG_DMEIF4 ((uint32_t)0x20000004) 00382 #define DMA_FLAG_TEIF4 ((uint32_t)0x20000008) 00383 #define DMA_FLAG_HTIF4 ((uint32_t)0x20000010) 00384 #define DMA_FLAG_TCIF4 ((uint32_t)0x20000020) 00385 #define DMA_FLAG_FEIF5 ((uint32_t)0x20000040) 00386 #define DMA_FLAG_DMEIF5 ((uint32_t)0x20000100) 00387 #define DMA_FLAG_TEIF5 ((uint32_t)0x20000200) 00388 #define DMA_FLAG_HTIF5 ((uint32_t)0x20000400) 00389 #define DMA_FLAG_TCIF5 ((uint32_t)0x20000800) 00390 #define DMA_FLAG_FEIF6 ((uint32_t)0x20010000) 00391 #define DMA_FLAG_DMEIF6 ((uint32_t)0x20040000) 00392 #define DMA_FLAG_TEIF6 ((uint32_t)0x20080000) 00393 #define DMA_FLAG_HTIF6 ((uint32_t)0x20100000) 00394 #define DMA_FLAG_TCIF6 ((uint32_t)0x20200000) 00395 #define DMA_FLAG_FEIF7 ((uint32_t)0x20400000) 00396 #define DMA_FLAG_DMEIF7 ((uint32_t)0x21000000) 00397 #define DMA_FLAG_TEIF7 ((uint32_t)0x22000000) 00398 #define DMA_FLAG_HTIF7 ((uint32_t)0x24000000) 00399 #define DMA_FLAG_TCIF7 ((uint32_t)0x28000000) 00400 00401 #define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \ 00402 (((FLAG) & 0xC002F082) == 0x00) && ((FLAG) != 0x00)) 00403 00404 #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \ 00405 ((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \ 00406 ((FLAG) == DMA_FLAG_FEIF0) || ((FLAG) == DMA_FLAG_TCIF1) || \ 00407 ((FLAG) == DMA_FLAG_HTIF1) || ((FLAG) == DMA_FLAG_TEIF1) || \ 00408 ((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1) || \ 00409 ((FLAG) == DMA_FLAG_TCIF2) || ((FLAG) == DMA_FLAG_HTIF2) || \ 00410 ((FLAG) == DMA_FLAG_TEIF2) || ((FLAG) == DMA_FLAG_DMEIF2) || \ 00411 ((FLAG) == DMA_FLAG_FEIF2) || ((FLAG) == DMA_FLAG_TCIF3) || \ 00412 ((FLAG) == DMA_FLAG_HTIF3) || ((FLAG) == DMA_FLAG_TEIF3) || \ 00413 ((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3) || \ 00414 ((FLAG) == DMA_FLAG_TCIF4) || ((FLAG) == DMA_FLAG_HTIF4) || \ 00415 ((FLAG) == DMA_FLAG_TEIF4) || ((FLAG) == DMA_FLAG_DMEIF4) || \ 00416 ((FLAG) == DMA_FLAG_FEIF4) || ((FLAG) == DMA_FLAG_TCIF5) || \ 00417 ((FLAG) == DMA_FLAG_HTIF5) || ((FLAG) == DMA_FLAG_TEIF5) || \ 00418 ((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5) || \ 00419 ((FLAG) == DMA_FLAG_TCIF6) || ((FLAG) == DMA_FLAG_HTIF6) || \ 00420 ((FLAG) == DMA_FLAG_TEIF6) || ((FLAG) == DMA_FLAG_DMEIF6) || \ 00421 ((FLAG) == DMA_FLAG_FEIF6) || ((FLAG) == DMA_FLAG_TCIF7) || \ 00422 ((FLAG) == DMA_FLAG_HTIF7) || ((FLAG) == DMA_FLAG_TEIF7) || \ 00423 ((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7)) 00424 /** 00425 * @} 00426 */ 00427 00428 00429 /** @defgroup DMA_interrupt_enable_definitions 00430 * @{ 00431 */ 00432 #define DMA_IT_TC_MORT ((uint32_t)0x00000010) 00433 #define DMA_IT_HT_MORT ((uint32_t)0x00000008) 00434 #define DMA_IT_TE_MORT ((uint32_t)0x00000004) 00435 #define DMA_IT_DME_MORT ((uint32_t)0x00000002) 00436 #define DMA_IT_FE_MORT ((uint32_t)0x00000080) 00437 00438 #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00)) 00439 /** 00440 * @} 00441 */ 00442 00443 00444 /** @defgroup DMA_interrupts_definitions 00445 * @{ 00446 */ 00447 #define DMA_IT_FEIF0 ((uint32_t)0x90000001) 00448 #define DMA_IT_DMEIF0 ((uint32_t)0x10001004) 00449 #define DMA_IT_TEIF0 ((uint32_t)0x10002008) 00450 #define DMA_IT_HTIF0 ((uint32_t)0x10004010) 00451 #define DMA_IT_TC_MORTIF0 ((uint32_t)0x10008020) 00452 #define DMA_IT_FEIF1 ((uint32_t)0x90000040) 00453 #define DMA_IT_DMEIF1 ((uint32_t)0x10001100) 00454 #define DMA_IT_TEIF1 ((uint32_t)0x10002200) 00455 #define DMA_IT_HTIF1 ((uint32_t)0x10004400) 00456 #define DMA_IT_TC_MORTIF1 ((uint32_t)0x10008800) 00457 #define DMA_IT_FEIF2 ((uint32_t)0x90010000) 00458 #define DMA_IT_DMEIF2 ((uint32_t)0x10041000) 00459 #define DMA_IT_TEIF2 ((uint32_t)0x10082000) 00460 #define DMA_IT_HTIF2 ((uint32_t)0x10104000) 00461 #define DMA_IT_TC_MORTIF2 ((uint32_t)0x10208000) 00462 #define DMA_IT_FEIF3 ((uint32_t)0x90400000) 00463 #define DMA_IT_DMEIF3 ((uint32_t)0x11001000) 00464 #define DMA_IT_TEIF3 ((uint32_t)0x12002000) 00465 #define DMA_IT_HTIF3 ((uint32_t)0x14004000) 00466 #define DMA_IT_TC_MORTIF3 ((uint32_t)0x18008000) 00467 #define DMA_IT_FEIF4 ((uint32_t)0xA0000001) 00468 #define DMA_IT_DMEIF4 ((uint32_t)0x20001004) 00469 #define DMA_IT_TEIF4 ((uint32_t)0x20002008) 00470 #define DMA_IT_HTIF4 ((uint32_t)0x20004010) 00471 #define DMA_IT_TC_MORTIF4 ((uint32_t)0x20008020) 00472 #define DMA_IT_FEIF5 ((uint32_t)0xA0000040) 00473 #define DMA_IT_DMEIF5 ((uint32_t)0x20001100) 00474 #define DMA_IT_TEIF5 ((uint32_t)0x20002200) 00475 #define DMA_IT_HTIF5 ((uint32_t)0x20004400) 00476 #define DMA_IT_TC_MORTIF5 ((uint32_t)0x20008800) 00477 #define DMA_IT_FEIF6 ((uint32_t)0xA0010000) 00478 #define DMA_IT_DMEIF6 ((uint32_t)0x20041000) 00479 #define DMA_IT_TEIF6 ((uint32_t)0x20082000) 00480 #define DMA_IT_HTIF6 ((uint32_t)0x20104000) 00481 #define DMA_IT_TC_MORTIF6 ((uint32_t)0x20208000) 00482 #define DMA_IT_FEIF7 ((uint32_t)0xA0400000) 00483 #define DMA_IT_DMEIF7 ((uint32_t)0x21001000) 00484 #define DMA_IT_TEIF7 ((uint32_t)0x22002000) 00485 #define DMA_IT_HTIF7 ((uint32_t)0x24004000) 00486 #define DMA_IT_TC_MORTIF7 ((uint32_t)0x28008000) 00487 00488 #define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \ 00489 (((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \ 00490 (((IT) & 0x40820082) == 0x00)) 00491 00492 #define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TC_MORT_MORT_MORTIF0) || ((IT) == DMA_IT_HTIF0) || \ 00493 ((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \ 00494 ((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TC_MORT_MORT_MORT_MORT_MORTIF1) || \ 00495 ((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1) || \ 00496 ((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1) || \ 00497 ((IT) == DMA_IT_TC_MORT_MORT_MORTIF2) || ((IT) == DMA_IT_HTIF2) || \ 00498 ((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \ 00499 ((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TC_MORT_MORT_MORT_MORT_MORTIF3) || \ 00500 ((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3) || \ 00501 ((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3) || \ 00502 ((IT) == DMA_IT_TC_MORT_MORT_MORTIF4) || ((IT) == DMA_IT_HTIF4) || \ 00503 ((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \ 00504 ((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TC_MORT_MORT_MORT_MORT_MORTIF5) || \ 00505 ((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5) || \ 00506 ((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5) || \ 00507 ((IT) == DMA_IT_TC_MORT_MORT_MORTIF6) || ((IT) == DMA_IT_HTIF6) || \ 00508 ((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \ 00509 ((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TC_MORT_MORT_MORT_MORT_MORTIF7) || \ 00510 ((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7) || \ 00511 ((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7)) 00512 /** 00513 * @} 00514 */ 00515 00516 00517 /** @defgroup DMA_peripheral_increment_offset 00518 * @{ 00519 */ 00520 #define DMA_PINCOS_Psize ((uint32_t)0x00000000) 00521 #define DMA_PINCOS_WordAligned ((uint32_t)0x00008000) 00522 00523 #define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \ 00524 ((SIZE) == DMA_PINCOS_WordAligned)) 00525 /** 00526 * @} 00527 */ 00528 00529 00530 /** @defgroup DMA_flow_controller_definitions 00531 * @{ 00532 */ 00533 #define DMA_FlowCtrl_Memory ((uint32_t)0x00000000) 00534 #define DMA_FlowCtrl_Peripheral ((uint32_t)0x00000020) 00535 00536 #define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \ 00537 ((CTRL) == DMA_FlowCtrl_Peripheral)) 00538 /** 00539 * @} 00540 */ 00541 00542 00543 /** @defgroup DMA_memory_targets_definitions 00544 * @{ 00545 */ 00546 #define DMA_Memory_0 ((uint32_t)0x00000000) 00547 #define DMA_Memory_1 ((uint32_t)0x00080000) 00548 00549 #define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1)) 00550 /** 00551 * @} 00552 */ 00553 00554 /** 00555 * @} 00556 */ 00557 00558 /* Exported macro ------------------------------------------------------------*/ 00559 /* Exported functions --------------------------------------------------------*/ 00560 00561 /* Function used to set the DMA configuration to the default reset state *****/ 00562 void DMA_DeInit_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx); 00563 00564 /* Initialization and Configuration functions *********************************/ 00565 void DMA_Init_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, DMA_InitTypeDef_mort* DMA_InitStruct); 00566 void DMA_StructInit_mort(DMA_InitTypeDef_mort* DMA_InitStruct); 00567 void DMA_Cmd_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, FunctionalState NewState); 00568 00569 /* Optional Configuration functions *******************************************/ 00570 void DMA_PeriphIncOffsetSizeConfig_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_Pincos); 00571 void DMA_FlowControllerConfig_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_FlowCtrl); 00572 00573 /* Data Counter functions *****************************************************/ 00574 void DMA_SetCurrDataCounter_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint16_t Counter); 00575 uint16_t DMA_GetCurrDataCounter_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx); 00576 00577 /* Double Buffer mode functions ***********************************************/ 00578 void DMA_DoubleBufferModeConfig_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t Memory1BaseAddr, 00579 uint32_t DMA_CurrentMemory); 00580 void DMA_DoubleBufferModeCmd_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, FunctionalState NewState); 00581 void DMA_MemoryTargetConfig_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t MemoryBaseAddr, 00582 uint32_t DMA_MemoryTarget); 00583 uint32_t DMA_GetCurrentMemoryTarget_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx); 00584 00585 /* Interrupts and flags management functions **********************************/ 00586 FunctionalState DMA_GetCmdStatus_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx); 00587 uint32_t DMA_GetFIFOStatus_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx); 00588 FlagStatus DMA_GetFlagStatus_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_FLAG); 00589 void DMA_ClearFlag_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_FLAG); 00590 void DMA_ITConfig_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState); 00591 ITStatus DMA_GetITStatus_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_IT); 00592 void DMA_ClearITPendingBit_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_IT); 00593 00594 #ifdef __cplusplus 00595 } 00596 #endif 00597 00598 #endif /*__STM32F4xx_DMA_H_MORT */ 00599 00600 /** 00601 * @} 00602 */ 00603 00604 /** 00605 * @} 00606 */ 00607 00608 00609 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 00610 00611 00612 00613 00614
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