stm32f4xx_dma_mort.c

00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_dma.c
00004   * @author  MCD Application Team
00005   * @version V1.8.0
00006   * @date    04-November-2016
00007   * @brief   This file provides firmware functions to manage the following 
00008   *          functionalities of the Direct Memory Access controller (DMA):           
00009   *           + Initialization and Configuration
00010   *           + Data Counter
00011   *           + Double Buffer mode configuration and command  
00012   *           + Interrupts and flags management
00013   *           
00014   @verbatim      
00015  ===============================================================================      
00016                        ##### How to use this driver #####
00017  ===============================================================================
00018     [..] 
00019       (#) Enable The DMA controller clock using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA1, ENABLE)
00020           function for DMA1_MORT or using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2, ENABLE)
00021           function for DMA2_MORT.
00022   
00023       (#) Enable and configure the peripheral to be connected to the DMA Stream
00024           (except for internal SRAM / FLASH memories: no initialization is 
00025           necessary). 
00026           
00027       (#) For a given Stream, program the required configuration through following parameters:   
00028           Source and Destination addresses, Transfer Direction, Transfer size, Source and Destination 
00029           data formats, Circular or Normal mode, Stream Priority level, Source and Destination 
00030           Incrementation mode, FIFO mode and its Threshold (if needed), Burst 
00031           mode for Source and/or Destination (if needed) using the DMA_Init() function.
00032           To avoid filling unnecessary fields, you can call DMA_StructInit() function
00033           to initialize a given structure with default values (reset values), the modify
00034           only necessary fields 
00035           (ie. Source and Destination addresses, Transfer size and Data Formats).
00036   
00037       (#) Enable the NVIC and the corresponding interrupt(s) using the function 
00038           DMA_ITConfig() if you need to use DMA interrupts. 
00039   
00040       (#) Optionally, if the Circular mode is enabled, you can use the Double buffer mode by configuring 
00041           the second Memory address and the first Memory to be used through the function 
00042           DMA_DoubleBufferModeConfig(). Then enable the Double buffer mode through the function
00043           DMA_DoubleBufferModeCmd(). These operations must be done before step 6.
00044       
00045       (#) Enable the DMA stream using the DMA_Cmd() function. 
00046                   
00047       (#) Activate the needed Stream Request using PPP_DMACmd() function for
00048           any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...)
00049           The function allowing this operation is provided in each PPP peripheral
00050           driver (ie. SPI_DMACmd for SPI peripheral).
00051           Once the Stream is enabled, it is not possible to modify its configuration
00052           unless the stream is stopped and disabled.
00053           After enabling the Stream, it is advised to monitor the EN bit status using
00054           the function DMA_GetCmdStatus(). In case of configuration errors or bus errors
00055           this bit will remain reset and all transfers on this Stream will remain on hold.      
00056   
00057       (#) Optionally, you can configure the number of data to be transferred
00058           when the Stream is disabled (ie. after each Transfer Complete event
00059           or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().
00060           And you can get the number of remaining data to be transferred using 
00061           the function DMA_GetCurrDataCounter() at run time (when the DMA Stream is
00062           enabled and running).  
00063                      
00064       (#) To control DMA events you can use one of the following two methods:
00065         (##) Check on DMA Stream flags using the function DMA_GetFlagStatus().  
00066         (##) Use DMA interrupts through the function DMA_ITConfig() at initialization
00067              phase and DMA_GetITStatus() function into interrupt routines in
00068              communication phase.
00069     [..]     
00070           After checking on a flag you should clear it using DMA_ClearFlag()
00071           function. And after checking on an interrupt event you should 
00072           clear it using DMA_ClearITPendingBit() function.    
00073                 
00074       (#) Optionally, if Circular mode and Double Buffer mode are enabled, you can modify
00075           the Memory Addresses using the function DMA_MemoryTargetConfig(). Make sure that
00076           the Memory Address to be modified is not the one currently in use by DMA Stream.
00077           This condition can be monitored using the function DMA_GetCurrentMemoryTarget().
00078                 
00079       (#) Optionally, Pause-Resume operations may be performed:
00080           The DMA_Cmd() function may be used to perform Pause-Resume operation. 
00081           When a transfer is ongoing, calling this function to disable the 
00082           Stream will cause the transfer to be paused. All configuration registers 
00083           and the number of remaining data will be preserved. When calling again 
00084           this function to re-enable the Stream, the transfer will be resumed from 
00085           the point where it was paused.          
00086                    
00087       -@- Memory-to-Memory transfer is possible by setting the address of the memory into
00088            the Peripheral registers. In this mode, Circular mode and Double Buffer mode
00089            are not allowed.
00090     
00091       -@- The FIFO is used mainly to reduce bus usage and to allow data 
00092            packing/unpacking: it is possible to set different Data Sizes for 
00093            the Peripheral and the Memory (ie. you can set Half-Word data size 
00094            for the peripheral to access its data register and set Word data size
00095            for the Memory to gain in access time. Each two Half-words will be 
00096            packed and written in a single access to a Word in the Memory).
00097       
00098       -@- When FIFO is disabled, it is not allowed to configure different 
00099            Data Sizes for Source and Destination. In this case the Peripheral 
00100            Data Size will be applied to both Source and Destination.               
00101   
00102   @endverbatim
00103   ******************************************************************************
00104   * @attention
00105   *
00106   * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
00107   *
00108   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00109   * You may not use this file except in compliance with the License.
00110   * You may obtain a copy of the License at:
00111   *
00112   *        http://www.st.com/software_license_agreement_liberty_v2
00113   *
00114   * Unless required by applicable law or agreed to in writing, software 
00115   * distributed under the License is distributed on an "AS IS" BASIS, 
00116   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00117   * See the License for the specific language governing permissions and
00118   * limitations under the License.
00119   *
00120   ******************************************************************************  
00121   */ 
00122 
00123 /* Includes ------------------------------------------------------------------*/
00124 #include "stm32f4xx_dma_mort.h"
00125 #include "stm32f4xx_rcc_mort.h"
00126 
00127 /** @addtogroup STM32F4xx_StdPeriph_Driver
00128   * @{
00129   */
00130 
00131 /** @defgroup DMA 
00132   * @brief DMA driver modules
00133   * @{
00134   */ 
00135 
00136 /* Private typedef -----------------------------------------------------------*/
00137 /* Private define ------------------------------------------------------------*/
00138 
00139 /* Masks Definition */
00140 #define TRANSFER_IT_ENABLE_MASK (uint32_t)(DMA_SxCR_TCIE_MORT | DMA_SxCR_HTIE_MORT | \
00141                                            DMA_SxCR_TEIE_MORT | DMA_SxCR_DMEIE_MORT)
00142 
00143 #define DMA_Stream0_IT_MASK     (uint32_t)(DMA_LISR_FEIF0_MORT | DMA_LISR_DMEIF0_MORT | \
00144                                            DMA_LISR_TEIF0_MORT | DMA_LISR_HTIF0_MORT | \
00145                                            DMA_LISR_TCIF0_MORT)
00146 
00147 #define DMA_Stream1_IT_MASK     (uint32_t)(DMA_Stream0_IT_MASK << 6)
00148 #define DMA_Stream2_IT_MASK     (uint32_t)(DMA_Stream0_IT_MASK << 16)
00149 #define DMA_Stream3_IT_MASK     (uint32_t)(DMA_Stream0_IT_MASK << 22)
00150 #define DMA_Stream4_IT_MASK     (uint32_t)(DMA_Stream0_IT_MASK | (uint32_t)0x20000000)
00151 #define DMA_Stream5_IT_MASK     (uint32_t)(DMA_Stream1_IT_MASK | (uint32_t)0x20000000)
00152 #define DMA_Stream6_IT_MASK     (uint32_t)(DMA_Stream2_IT_MASK | (uint32_t)0x20000000)
00153 #define DMA_Stream7_IT_MASK     (uint32_t)(DMA_Stream3_IT_MASK | (uint32_t)0x20000000)
00154 #define TRANSFER_IT_MASK        (uint32_t)0x0F3C0F3C
00155 #define HIGH_ISR_MASK           (uint32_t)0x20000000
00156 #define RESERVED_MASK           (uint32_t)0x0F7D0F7D  
00157 
00158 /* Private macro -------------------------------------------------------------*/
00159 /* Private variables ---------------------------------------------------------*/
00160 /* Private function prototypes -----------------------------------------------*/
00161 /* Private functions ---------------------------------------------------------*/
00162 
00163 
00164 /** @defgroup DMA_Private_Functions
00165   * @{
00166   */
00167 
00168 /** @defgroup DMA_Group1 Initialization and Configuration functions
00169  *  @brief   Initialization and Configuration functions
00170  *
00171 @verbatim   
00172  ===============================================================================
00173                 ##### Initialization and Configuration functions #####
00174  ===============================================================================  
00175     [..]
00176     This subsection provides functions allowing to initialize the DMA Stream source
00177     and destination addresses, incrementation and data sizes, transfer direction, 
00178     buffer size, circular/normal mode selection, memory-to-memory mode selection 
00179     and Stream priority value.
00180     [..]
00181     The DMA_Init() function follows the DMA configuration procedures as described in
00182     reference manual (RM0090) except the first point: waiting on EN bit to be reset.
00183     This condition should be checked by user application using the function DMA_GetCmdStatus()
00184     before calling the DMA_Init() function.
00185 
00186 @endverbatim
00187   * @{
00188   */
00189 
00190 /**
00191   * @brief  Deinitialize the DMAy Streamx registers to their default reset values.
00192   * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
00193   *         to 7 to select the DMA Stream.
00194   * @retval None
00195   */
00196 void DMA_DeInit_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx)
00197 {
00198   /* Check the parameters */
00199   assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
00200 
00201   /* Disable the selected DMAy Streamx */
00202   DMAy_Streamx->CR &= ~((uint32_t)DMA_SxCR_EN_MORT);
00203 
00204   /* Reset DMAy Streamx control register */
00205   DMAy_Streamx->CR  = 0;
00206   
00207   /* Reset DMAy Streamx Number of Data to Transfer register */
00208   DMAy_Streamx->NDTR = 0;
00209   
00210   /* Reset DMAy Streamx peripheral address register */
00211   DMAy_Streamx->PAR  = 0;
00212   
00213   /* Reset DMAy Streamx memory 0 address register */
00214   DMAy_Streamx->M0AR = 0;
00215 
00216   /* Reset DMAy Streamx memory 1 address register */
00217   DMAy_Streamx->M1AR = 0;
00218 
00219   /* Reset DMAy Streamx FIFO control register */
00220   DMAy_Streamx->FCR = (uint32_t)0x00000021; 
00221 
00222   /* Reset interrupt pending bits for the selected stream */
00223   if (DMAy_Streamx == DMA1_Stream0_MORT)
00224   {
00225     /* Reset interrupt pending bits for DMA1_MORT Stream0 */
00226     DMA1_MORT->LIFCR = DMA_Stream0_IT_MASK;
00227   }
00228   else if (DMAy_Streamx == DMA1_Stream1_MORT)
00229   {
00230     /* Reset interrupt pending bits for DMA1_MORT Stream1 */
00231     DMA1_MORT->LIFCR = DMA_Stream1_IT_MASK;
00232   }
00233   else if (DMAy_Streamx == DMA1_Stream2_MORT)
00234   {
00235     /* Reset interrupt pending bits for DMA1_MORT Stream2 */
00236     DMA1_MORT->LIFCR = DMA_Stream2_IT_MASK;
00237   }
00238   else if (DMAy_Streamx == DMA1_Stream3_MORT)
00239   {
00240     /* Reset interrupt pending bits for DMA1_MORT Stream3 */
00241     DMA1_MORT->LIFCR = DMA_Stream3_IT_MASK;
00242   }
00243   else if (DMAy_Streamx == DMA1_Stream4_MORT)
00244   {
00245     /* Reset interrupt pending bits for DMA1_MORT Stream4 */
00246     DMA1_MORT->HIFCR = DMA_Stream4_IT_MASK;
00247   }
00248   else if (DMAy_Streamx == DMA1_Stream5_MORT)
00249   {
00250     /* Reset interrupt pending bits for DMA1_MORT Stream5 */
00251     DMA1_MORT->HIFCR = DMA_Stream5_IT_MASK;
00252   }
00253   else if (DMAy_Streamx == DMA1_Stream6_MORT)
00254   {
00255     /* Reset interrupt pending bits for DMA1_MORT Stream6 */
00256     DMA1_MORT->HIFCR = (uint32_t)DMA_Stream6_IT_MASK;
00257   }
00258   else if (DMAy_Streamx == DMA1_Stream7_MORT)
00259   {
00260     /* Reset interrupt pending bits for DMA1_MORT Stream7 */
00261     DMA1_MORT->HIFCR = DMA_Stream7_IT_MASK;
00262   }
00263   else if (DMAy_Streamx == DMA2_Stream0_MORT)
00264   {
00265     /* Reset interrupt pending bits for DMA2_MORT Stream0 */
00266     DMA2_MORT->LIFCR = DMA_Stream0_IT_MASK;
00267   }
00268   else if (DMAy_Streamx == DMA2_Stream1_MORT)
00269   {
00270     /* Reset interrupt pending bits for DMA2_MORT Stream1 */
00271     DMA2_MORT->LIFCR = DMA_Stream1_IT_MASK;
00272   }
00273   else if (DMAy_Streamx == DMA2_Stream2_MORT)
00274   {
00275     /* Reset interrupt pending bits for DMA2_MORT Stream2 */
00276     DMA2_MORT->LIFCR = DMA_Stream2_IT_MASK;
00277   }
00278   else if (DMAy_Streamx == DMA2_Stream3_MORT)
00279   {
00280     /* Reset interrupt pending bits for DMA2_MORT Stream3 */
00281     DMA2_MORT->LIFCR = DMA_Stream3_IT_MASK;
00282   }
00283   else if (DMAy_Streamx == DMA2_Stream4_MORT)
00284   {
00285     /* Reset interrupt pending bits for DMA2_MORT Stream4 */
00286     DMA2_MORT->HIFCR = DMA_Stream4_IT_MASK;
00287   }
00288   else if (DMAy_Streamx == DMA2_Stream5_MORT)
00289   {
00290     /* Reset interrupt pending bits for DMA2_MORT Stream5 */
00291     DMA2_MORT->HIFCR = DMA_Stream5_IT_MASK;
00292   }
00293   else if (DMAy_Streamx == DMA2_Stream6_MORT)
00294   {
00295     /* Reset interrupt pending bits for DMA2_MORT Stream6 */
00296     DMA2_MORT->HIFCR = DMA_Stream6_IT_MASK;
00297   }
00298   else 
00299   {
00300     if (DMAy_Streamx == DMA2_Stream7_MORT)
00301     {
00302       /* Reset interrupt pending bits for DMA2_MORT Stream7 */
00303       DMA2_MORT->HIFCR = DMA_Stream7_IT_MASK;
00304     }
00305   }
00306 }
00307 
00308 /**
00309   * @brief  Initializes the DMAy Streamx according to the specified parameters in 
00310   *         the DMA_InitStruct structure.
00311   * @note   Before calling this function, it is recommended to check that the Stream 
00312   *         is actually disabled using the function DMA_GetCmdStatus().  
00313   * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
00314   *         to 7 to select the DMA Stream.
00315   * @param  DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains
00316   *         the configuration information for the specified DMA Stream.  
00317   * @retval None
00318   */
00319 void DMA_Init_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, DMA_InitTypeDef_mort* DMA_InitStruct)
00320 {
00321   uint32_t tmpreg = 0;
00322 
00323   /* Check the parameters */
00324   assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
00325   assert_param(IS_DMA_CHANNEL_MORT(DMA_InitStruct->DMA_Channel));
00326   assert_param(IS_DMA_DIRECTION_MORT(DMA_InitStruct->DMA_DIR));
00327   assert_param(IS_DMA_BUFFER_SIZE_MORT(DMA_InitStruct->DMA_BufferSize));
00328   assert_param(IS_DMA_PERIPHERAL_INC_STATE_MORT(DMA_InitStruct->DMA_PeripheralInc));
00329   assert_param(IS_DMA_MEMORY_INC_STATE_MORT(DMA_InitStruct->DMA_MemoryInc));
00330   assert_param(IS_DMA_PERIPHERAL_DATA_SIZE_MORT(DMA_InitStruct->DMA_PeripheralDataSize));
00331   assert_param(IS_DMA_MEMORY_DATA_SIZE_MORT(DMA_InitStruct->DMA_MemoryDataSize));
00332   assert_param(IS_DMA_MODE_MORT(DMA_InitStruct->DMA_Mode));
00333   assert_param(IS_DMA_PRIORITY_MORT(DMA_InitStruct->DMA_Priority));
00334   assert_param(IS_DMA_FIFO_MODE_STATE_MORT(DMA_InitStruct->DMA_FIFOMode));
00335   assert_param(IS_DMA_FIFO_THRESHOLD_MORT(DMA_InitStruct->DMA_FIFOThreshold));
00336   assert_param(IS_DMA_MEMORY_BURST_MORT(DMA_InitStruct->DMA_MemoryBurst));
00337   assert_param(IS_DMA_PERIPHERAL_BURST_MORT(DMA_InitStruct->DMA_PeripheralBurst));
00338 
00339   /*------------------------- DMAy Streamx CR Configuration ------------------*/
00340   /* Get the DMAy_Streamx CR value */
00341   tmpreg = DMAy_Streamx->CR;
00342 
00343   /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
00344   tmpreg &= ((uint32_t)~(DMA_SxCR_CHSEL_MORT | DMA_SxCR_MBURST_MORT | DMA_SxCR_PBURST_MORT | \
00345                          DMA_SxCR_PL_MORT | DMA_SxCR_MSIZE_MORT | DMA_SxCR_PSIZE_MORT | \
00346                          DMA_SxCR_MINC_MORT | DMA_SxCR_PINC_MORT | DMA_SxCR_CIRC_MORT | \
00347                          DMA_SxCR_DIR_MORT));
00348 
00349   /* Configure DMAy Streamx: */
00350   /* Set CHSEL bits according to DMA_CHSEL value */
00351   /* Set DIR bits according to DMA_DIR value */
00352   /* Set PINC bit according to DMA_PeripheralInc value */
00353   /* Set MINC bit according to DMA_MemoryInc value */
00354   /* Set PSIZE bits according to DMA_PeripheralDataSize value */
00355   /* Set MSIZE bits according to DMA_MemoryDataSize value */
00356   /* Set CIRC bit according to DMA_Mode value */
00357   /* Set PL bits according to DMA_Priority value */
00358   /* Set MBURST bits according to DMA_MemoryBurst value */
00359   /* Set PBURST bits according to DMA_PeripheralBurst value */
00360   tmpreg |= DMA_InitStruct->DMA_Channel | DMA_InitStruct->DMA_DIR |
00361             DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
00362             DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
00363             DMA_InitStruct->DMA_Mode | DMA_InitStruct->DMA_Priority |
00364             DMA_InitStruct->DMA_MemoryBurst | DMA_InitStruct->DMA_PeripheralBurst;
00365 
00366   /* Write to DMAy Streamx CR register */
00367   DMAy_Streamx->CR = tmpreg;
00368 
00369   /*------------------------- DMAy Streamx FCR Configuration -----------------*/
00370   /* Get the DMAy_Streamx FCR value */
00371   tmpreg = DMAy_Streamx->FCR;
00372 
00373   /* Clear DMDIS and FTH bits */
00374   tmpreg &= (uint32_t)~(DMA_SxFCR_DMDIS_MORT | DMA_SxFCR_FTH_MORT);
00375 
00376   /* Configure DMAy Streamx FIFO: 
00377     Set DMDIS bits according to DMA_FIFOMode value 
00378     Set FTH bits according to DMA_FIFOThreshold value */
00379   tmpreg |= DMA_InitStruct->DMA_FIFOMode | DMA_InitStruct->DMA_FIFOThreshold;
00380 
00381   /* Write to DMAy Streamx CR */
00382   DMAy_Streamx->FCR = tmpreg;
00383 
00384   /*------------------------- DMAy Streamx NDTR Configuration ----------------*/
00385   /* Write to DMAy Streamx NDTR register */
00386   DMAy_Streamx->NDTR = DMA_InitStruct->DMA_BufferSize;
00387 
00388   /*------------------------- DMAy Streamx PAR Configuration -----------------*/
00389   /* Write to DMAy Streamx PAR */
00390   DMAy_Streamx->PAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
00391 
00392   /*------------------------- DMAy Streamx M0AR Configuration ----------------*/
00393   /* Write to DMAy Streamx M0AR */
00394   DMAy_Streamx->M0AR = DMA_InitStruct->DMA_Memory0BaseAddr;
00395 }
00396 
00397 /**
00398   * @brief  Fills each DMA_InitStruct member with its default value.
00399   * @param  DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will 
00400   *         be initialized.
00401   * @retval None
00402   */
00403 void DMA_StructInit_mort(DMA_InitTypeDef_mort* DMA_InitStruct)
00404 {
00405   /*-------------- Reset DMA init structure parameters values ----------------*/
00406   /* Initialize the DMA_Channel member */
00407   DMA_InitStruct->DMA_Channel = 0;
00408 
00409   /* Initialize the DMA_PeripheralBaseAddr member */
00410   DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
00411 
00412   /* Initialize the DMA_Memory0BaseAddr member */
00413   DMA_InitStruct->DMA_Memory0BaseAddr = 0;
00414 
00415   /* Initialize the DMA_DIR member */
00416   DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralToMemory;
00417 
00418   /* Initialize the DMA_BufferSize member */
00419   DMA_InitStruct->DMA_BufferSize = 0;
00420 
00421   /* Initialize the DMA_PeripheralInc member */
00422   DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00423 
00424   /* Initialize the DMA_MemoryInc member */
00425   DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
00426 
00427   /* Initialize the DMA_PeripheralDataSize member */
00428   DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
00429 
00430   /* Initialize the DMA_MemoryDataSize member */
00431   DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
00432 
00433   /* Initialize the DMA_Mode member */
00434   DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
00435 
00436   /* Initialize the DMA_Priority member */
00437   DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
00438 
00439   /* Initialize the DMA_FIFOMode member */
00440   DMA_InitStruct->DMA_FIFOMode = DMA_FIFOMode_Disable;
00441 
00442   /* Initialize the DMA_FIFOThreshold member */
00443   DMA_InitStruct->DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull;
00444 
00445   /* Initialize the DMA_MemoryBurst member */
00446   DMA_InitStruct->DMA_MemoryBurst = DMA_MemoryBurst_Single;
00447 
00448   /* Initialize the DMA_PeripheralBurst member */
00449   DMA_InitStruct->DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
00450 }
00451 
00452 /**
00453   * @brief  Enables or disables the specified DMAy Streamx.
00454   * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
00455   *         to 7 to select the DMA Stream.
00456   * @param  NewState: new state of the DMAy Streamx. 
00457   *          This parameter can be: ENABLE or DISABLE.
00458   *
00459   * @note  This function may be used to perform Pause-Resume operation. When a
00460   *        transfer is ongoing, calling this function to disable the Stream will
00461   *        cause the transfer to be paused. All configuration registers and the
00462   *        number of remaining data will be preserved. When calling again this
00463   *        function to re-enable the Stream, the transfer will be resumed from
00464   *        the point where it was paused.          
00465   *    
00466   * @note  After configuring the DMA Stream (DMA_Init() function) and enabling the
00467   *        stream, it is recommended to check (or wait until) the DMA Stream is
00468   *        effectively enabled. A Stream may remain disabled if a configuration 
00469   *        parameter is wrong.
00470   *        After disabling a DMA Stream, it is also recommended to check (or wait
00471   *        until) the DMA Stream is effectively disabled. If a Stream is disabled 
00472   *        while a data transfer is ongoing, the current data will be transferred
00473   *        and the Stream will be effectively disabled only after the transfer of
00474   *        this single data is finished.            
00475   *    
00476   * @retval None
00477   */
00478 void DMA_Cmd_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, FunctionalState NewState)
00479 {
00480   /* Check the parameters */
00481   assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
00482   assert_param(IS_FUNCTIONAL_STATE(NewState));
00483 
00484   if (NewState != DISABLE)
00485   {
00486     /* Enable the selected DMAy Streamx by setting EN bit */
00487     DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_EN_MORT;
00488   }
00489   else
00490   {
00491     /* Disable the selected DMAy Streamx by clearing EN bit */
00492     DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_EN_MORT;
00493   }
00494 }
00495 
00496 /**
00497   * @brief  Configures, when the PINC (Peripheral Increment address mode) bit is
00498   *         set, if the peripheral address should be incremented with the data 
00499   *         size (configured with PSIZE bits) or by a fixed offset equal to 4
00500   *         (32-bit aligned addresses).
00501   *   
00502   * @note   This function has no effect if the Peripheral Increment mode is disabled.
00503   *     
00504   * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
00505   *          to 7 to select the DMA Stream.
00506   * @param  DMA_Pincos: specifies the Peripheral increment offset size.
00507   *          This parameter can be one of the following values:
00508   *            @arg DMA_PINCOS_Psize: Peripheral address increment is done  
00509   *                                   accordingly to PSIZE parameter.
00510   *            @arg DMA_PINCOS_WordAligned: Peripheral address increment offset is 
00511   *                                         fixed to 4 (32-bit aligned addresses). 
00512   * @retval None
00513   */
00514 void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_Pincos)
00515 {
00516   /* Check the parameters */
00517   assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
00518   assert_param(IS_DMA_PINCOS_SIZE(DMA_Pincos));
00519 
00520   /* Check the needed Peripheral increment offset */
00521   if(DMA_Pincos != DMA_PINCOS_Psize)
00522   {
00523     /* Configure DMA_SxCR_PINCOS_MORT bit with the input parameter */
00524     DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PINCOS_MORT;     
00525   }
00526   else
00527   {
00528     /* Clear the PINCOS bit: Peripheral address incremented according to PSIZE */
00529     DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PINCOS_MORT;    
00530   }
00531 }
00532 
00533 /**
00534   * @brief  Configures, when the DMAy Streamx is disabled, the flow controller for
00535   *         the next transactions (Peripheral or Memory).
00536   *       
00537   * @note   Before enabling this feature, check if the used peripheral supports 
00538   *         the Flow Controller mode or not.    
00539   *  
00540   * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
00541   *          to 7 to select the DMA Stream.
00542   * @param  DMA_FlowCtrl: specifies the DMA flow controller.
00543   *          This parameter can be one of the following values:
00544   *            @arg DMA_FlowCtrl_Memory: DMAy_Streamx transactions flow controller is 
00545   *                                      the DMA controller.
00546   *            @arg DMA_FlowCtrl_Peripheral: DMAy_Streamx transactions flow controller 
00547   *                                          is the peripheral.    
00548   * @retval None
00549   */
00550 void DMA_FlowControllerConfig(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_FlowCtrl)
00551 {
00552   /* Check the parameters */
00553   assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
00554   assert_param(IS_DMA_FLOW_CTRL(DMA_FlowCtrl));
00555 
00556   /* Check the needed flow controller  */
00557   if(DMA_FlowCtrl != DMA_FlowCtrl_Memory)
00558   {
00559     /* Configure DMA_SxCR_PFCTRL_MORT bit with the input parameter */
00560     DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PFCTRL_MORT;   
00561   }
00562   else
00563   {
00564     /* Clear the PFCTRL bit: Memory is the flow controller */
00565     DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PFCTRL_MORT;    
00566   }
00567 }
00568 /**
00569   * @}
00570   */
00571 
00572 /** @defgroup DMA_Group2 Data Counter functions
00573  *  @brief   Data Counter functions 
00574  *
00575 @verbatim   
00576  ===============================================================================
00577                       ##### Data Counter functions #####
00578  ===============================================================================  
00579     [..]
00580     This subsection provides function allowing to configure and read the buffer size
00581     (number of data to be transferred). 
00582     [..]
00583     The DMA data counter can be written only when the DMA Stream is disabled 
00584     (ie. after transfer complete event).
00585     [..]
00586     The following function can be used to write the Stream data counter value:
00587       (+) void DMA_SetCurrDataCounter(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint16_t Counter);
00588       -@- It is advised to use this function rather than DMA_Init() in situations 
00589           where only the Data buffer needs to be reloaded.
00590       -@- If the Source and Destination Data Sizes are different, then the value 
00591           written in data counter, expressing the number of transfers, is relative 
00592           to the number of transfers from the Peripheral point of view.
00593           ie. If Memory data size is Word, Peripheral data size is Half-Words, 
00594           then the value to be configured in the data counter is the number 
00595           of Half-Words to be transferred from/to the peripheral.
00596     [..]
00597     The DMA data counter can be read to indicate the number of remaining transfers for
00598     the relative DMA Stream. This counter is decremented at the end of each data 
00599     transfer and when the transfer is complete: 
00600       (+) If Normal mode is selected: the counter is set to 0.
00601       (+) If Circular mode is selected: the counter is reloaded with the initial value
00602           (configured before enabling the DMA Stream)
00603      [..]
00604      The following function can be used to read the Stream data counter value:
00605        (+) uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef_mort* DMAy_Streamx);
00606 
00607 @endverbatim
00608   * @{
00609   */
00610 
00611 /**
00612   * @brief  Writes the number of data units to be transferred on the DMAy Streamx.
00613   * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
00614   *          to 7 to select the DMA Stream.
00615   * @param  Counter: Number of data units to be transferred (from 0 to 65535) 
00616   *          Number of data items depends only on the Peripheral data format.
00617   *            
00618   * @note   If Peripheral data format is Bytes: number of data units is equal 
00619   *         to total number of bytes to be transferred.
00620   *           
00621   * @note   If Peripheral data format is Half-Word: number of data units is  
00622   *         equal to total number of bytes to be transferred / 2.
00623   *           
00624   * @note   If Peripheral data format is Word: number of data units is equal 
00625   *         to total  number of bytes to be transferred / 4.
00626   *      
00627   * @note   In Memory-to-Memory transfer mode, the memory buffer pointed by 
00628   *         DMAy_SxPAR register is considered as Peripheral.
00629   *      
00630   * @retval The number of remaining data units in the current DMAy Streamx transfer.
00631   */
00632 void DMA_SetCurrDataCounter(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint16_t Counter)
00633 {
00634   /* Check the parameters */
00635   assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
00636 
00637   /* Write the number of data units to be transferred */
00638   DMAy_Streamx->NDTR = (uint16_t)Counter;
00639 }
00640 
00641 /**
00642   * @brief  Returns the number of remaining data units in the current DMAy Streamx transfer.
00643   * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
00644   *          to 7 to select the DMA Stream.
00645   * @retval The number of remaining data units in the current DMAy Streamx transfer.
00646   */
00647 uint16_t DMA_GetCurrDataCounter_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx)
00648 {
00649   /* Check the parameters */
00650   assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
00651 
00652   /* Return the number of remaining data units for DMAy Streamx */
00653   return ((uint16_t)(DMAy_Streamx->NDTR));
00654 }
00655 /**
00656   * @}
00657   */
00658 
00659 /** @defgroup DMA_Group3 Double Buffer mode functions
00660  *  @brief   Double Buffer mode functions 
00661  *
00662 @verbatim   
00663  ===============================================================================
00664                     ##### Double Buffer mode functions #####
00665  ===============================================================================  
00666     [..]
00667     This subsection provides function allowing to configure and control the double 
00668     buffer mode parameters.
00669     
00670     [..]
00671     The Double Buffer mode can be used only when Circular mode is enabled.
00672     The Double Buffer mode cannot be used when transferring data from Memory to Memory.
00673     
00674     [..]
00675     The Double Buffer mode allows to set two different Memory addresses from/to which
00676     the DMA controller will access alternatively (after completing transfer to/from 
00677     target memory 0, it will start transfer to/from target memory 1).
00678     This allows to reduce software overhead for double buffering and reduce the CPU
00679     access time.
00680     
00681     [..]
00682     Two functions must be called before calling the DMA_Init() function:
00683       (+) void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef_mort* DMAy_Streamx, 
00684           uint32_t Memory1BaseAddr, uint32_t DMA_CurrentMemory);
00685       (+) void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef_mort* DMAy_Streamx, FunctionalState NewState);
00686       
00687     [..]
00688     DMA_DoubleBufferModeConfig() is called to configure the Memory 1 base address 
00689     and the first Memory target from/to which the transfer will start after 
00690     enabling the DMA Stream. Then DMA_DoubleBufferModeCmd() must be called 
00691     to enable the Double Buffer mode (or disable it when it should not be used).
00692   
00693     [..]
00694     Two functions can be called dynamically when the transfer is ongoing (or when the DMA Stream is 
00695     stopped) to modify on of the target Memories addresses or to check which Memory target is currently
00696     used:
00697       (+) void DMA_MemoryTargetConfig(DMA_Stream_TypeDef_mort* DMAy_Streamx, 
00698                 uint32_t MemoryBaseAddr, uint32_t DMA_MemoryTarget);
00699       (+) uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef_mort* DMAy_Streamx);
00700       
00701     [..]
00702     DMA_MemoryTargetConfig() can be called to modify the base address of one of 
00703     the two target Memories.
00704     The Memory of which the base address will be modified must not be currently 
00705     be used by the DMA Stream (ie. if the DMA Stream is currently transferring 
00706     from Memory 1 then you can only modify base address of target Memory 0 and vice versa).
00707     To check this condition, it is recommended to use the function DMA_GetCurrentMemoryTarget() which
00708     returns the index of the Memory target currently in use by the DMA Stream.
00709 
00710 @endverbatim
00711   * @{
00712   */
00713   
00714 /**
00715   * @brief  Configures, when the DMAy Streamx is disabled, the double buffer mode 
00716   *         and the current memory target.
00717   * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
00718   *          to 7 to select the DMA Stream.
00719   * @param  Memory1BaseAddr: the base address of the second buffer (Memory 1)  
00720   * @param  DMA_CurrentMemory: specifies which memory will be first buffer for
00721   *         the transactions when the Stream will be enabled. 
00722   *          This parameter can be one of the following values:
00723   *            @arg DMA_Memory_0: Memory 0 is the current buffer.
00724   *            @arg DMA_Memory_1: Memory 1 is the current buffer.  
00725   *       
00726   * @note   Memory0BaseAddr is set by the DMA structure configuration in DMA_Init().
00727   *   
00728   * @retval None
00729   */
00730 void DMA_DoubleBufferModeConfig_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t Memory1BaseAddr,
00731                                 uint32_t DMA_CurrentMemory)
00732 {  
00733   /* Check the parameters */
00734   assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
00735   assert_param(IS_DMA_CURRENT_MEM(DMA_CurrentMemory));
00736 
00737   if (DMA_CurrentMemory != DMA_Memory_0)
00738   {
00739     /* Set Memory 1 as current memory address */
00740     DMAy_Streamx->CR |= (uint32_t)(DMA_SxCR_CT_MORT);    
00741   }
00742   else
00743   {
00744     /* Set Memory 0 as current memory address */
00745     DMAy_Streamx->CR &= ~(uint32_t)(DMA_SxCR_CT_MORT);    
00746   }
00747 
00748   /* Write to DMAy Streamx M1AR */
00749   DMAy_Streamx->M1AR = Memory1BaseAddr;
00750 }
00751 
00752 /**
00753   * @brief  Enables or disables the double buffer mode for the selected DMA stream.
00754   * @note   This function can be called only when the DMA Stream is disabled.  
00755   * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
00756   *          to 7 to select the DMA Stream.
00757   * @param  NewState: new state of the DMAy Streamx double buffer mode. 
00758   *          This parameter can be: ENABLE or DISABLE.
00759   * @retval None
00760   */
00761 void DMA_DoubleBufferModeCmd_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, FunctionalState NewState)
00762 {  
00763   /* Check the parameters */
00764   assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
00765   assert_param(IS_FUNCTIONAL_STATE(NewState));
00766 
00767   /* Configure the Double Buffer mode */
00768   if (NewState != DISABLE)
00769   {
00770     /* Enable the Double buffer mode */
00771     DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_DBM_MORT;
00772   }
00773   else
00774   {
00775     /* Disable the Double buffer mode */
00776     DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_DBM_MORT;
00777   }
00778 }
00779 
00780 /**
00781   * @brief  Configures the Memory address for the next buffer transfer in double
00782   *         buffer mode (for dynamic use). This function can be called when the
00783   *         DMA Stream is enabled and when the transfer is ongoing.  
00784   * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
00785   *          to 7 to select the DMA Stream.
00786   * @param  MemoryBaseAddr: The base address of the target memory buffer
00787   * @param  DMA_MemoryTarget: Next memory target to be used. 
00788   *         This parameter can be one of the following values:
00789   *            @arg DMA_Memory_0: To use the memory address 0
00790   *            @arg DMA_Memory_1: To use the memory address 1
00791   * 
00792   * @note    It is not allowed to modify the Base Address of a target Memory when
00793   *          this target is involved in the current transfer. ie. If the DMA Stream
00794   *          is currently transferring to/from Memory 1, then it not possible to
00795   *          modify Base address of Memory 1, but it is possible to modify Base
00796   *          address of Memory 0.
00797   *          To know which Memory is currently used, you can use the function
00798   *          DMA_GetCurrentMemoryTarget().             
00799   *  
00800   * @retval None
00801   */
00802 void DMA_MemoryTargetConfig_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t MemoryBaseAddr,
00803                            uint32_t DMA_MemoryTarget)
00804 {
00805   /* Check the parameters */
00806   assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
00807   assert_param(IS_DMA_CURRENT_MEM(DMA_MemoryTarget));
00808     
00809   /* Check the Memory target to be configured */
00810   if (DMA_MemoryTarget != DMA_Memory_0)
00811   {
00812     /* Write to DMAy Streamx M1AR */
00813     DMAy_Streamx->M1AR = MemoryBaseAddr;    
00814   }  
00815   else
00816   {
00817     /* Write to DMAy Streamx M0AR */
00818     DMAy_Streamx->M0AR = MemoryBaseAddr;  
00819   }
00820 }
00821 
00822 /**
00823   * @brief  Returns the current memory target used by double buffer transfer.
00824   * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
00825   *          to 7 to select the DMA Stream.
00826   * @retval The memory target number: 0 for Memory0 or 1 for Memory1. 
00827   */
00828 uint32_t DMA_GetCurrentMemoryTarget_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx)
00829 {
00830   uint32_t tmp = 0;
00831   
00832   /* Check the parameters */
00833   assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
00834 
00835   /* Get the current memory target */
00836   if ((DMAy_Streamx->CR & DMA_SxCR_CT_MORT) != 0)
00837   {
00838     /* Current memory buffer used is Memory 1 */
00839     tmp = 1;
00840   }  
00841   else
00842   {
00843     /* Current memory buffer used is Memory 0 */
00844     tmp = 0;    
00845   }
00846   return tmp;
00847 }
00848 /**
00849   * @}
00850   */
00851 
00852 /** @defgroup DMA_Group4 Interrupts and flags management functions
00853  *  @brief   Interrupts and flags management functions 
00854  *
00855 @verbatim   
00856  ===============================================================================
00857               ##### Interrupts and flags management functions #####
00858  ===============================================================================  
00859     [..]
00860     This subsection provides functions allowing to
00861       (+) Check the DMA enable status
00862       (+) Check the FIFO status 
00863       (+) Configure the DMA Interrupts sources and check or clear the flags or 
00864           pending bits status.  
00865            
00866     [..]
00867       (#) DMA Enable status:
00868           After configuring the DMA Stream (DMA_Init() function) and enabling 
00869           the stream, it is recommended to check (or wait until) the DMA Stream 
00870           is effectively enabled. A Stream may remain disabled if a configuration 
00871           parameter is wrong. After disabling a DMA Stream, it is also recommended 
00872           to check (or wait until) the DMA Stream is effectively disabled. 
00873           If a Stream is disabled while a data transfer is ongoing, the current 
00874           data will be transferred and the Stream will be effectively disabled 
00875           only after this data transfer completion.
00876           To monitor this state it is possible to use the following function:
00877         (++) FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef_mort* DMAy_Streamx); 
00878  
00879       (#) FIFO Status:
00880           It is possible to monitor the FIFO status when a transfer is ongoing 
00881           using the following function:
00882         (++) uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef_mort* DMAy_Streamx); 
00883  
00884       (#) DMA Interrupts and Flags:
00885           The user should identify which mode will be used in his application 
00886           to manage the DMA controller events: Polling mode or Interrupt mode. 
00887     
00888     *** Polling Mode ***
00889     ====================
00890     [..]
00891     Each DMA stream can be managed through 4 event Flags:
00892     (x : DMA Stream number )
00893       (#) DMA_FLAG_FEIFx  : to indicate that a FIFO Mode Transfer Error event occurred.
00894       (#) DMA_FLAG_DMEIFx : to indicate that a Direct Mode Transfer Error event occurred.
00895       (#) DMA_FLAG_TEIFx  : to indicate that a Transfer Error event occurred.
00896       (#) DMA_FLAG_HTIFx  : to indicate that a Half-Transfer Complete event occurred.
00897       (#) DMA_FLAG_TCIFx  : to indicate that a Transfer Complete event occurred .       
00898     [..]
00899     In this Mode it is advised to use the following functions:
00900       (+) FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_FLAG);
00901       (+) void DMA_ClearFlag(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_FLAG);
00902 
00903     *** Interrupt Mode ***
00904     ======================
00905     [..]
00906     Each DMA Stream can be managed through 4 Interrupts:
00907 
00908     *** Interrupt Source ***
00909     ========================
00910     [..]
00911       (#) DMA_IT_FEIFx  : specifies the interrupt source for the  FIFO Mode Transfer Error event.
00912       (#) DMA_IT_DMEIFx : specifies the interrupt source for the Direct Mode Transfer Error event.
00913       (#) DMA_IT_TEIFx  : specifies the interrupt source for the Transfer Error event.
00914       (#) DMA_IT_HTIFx  : specifies the interrupt source for the Half-Transfer Complete event.
00915       (#) DMA_IT_TC_MORTIFx  : specifies the interrupt source for the a Transfer Complete event. 
00916     [..]
00917     In this Mode it is advised to use the following functions:
00918       (+) void DMA_ITConfig(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);
00919       (+) ITStatus DMA_GetITStatus(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_IT);
00920       (+) void DMA_ClearITPendingBit(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_IT);
00921 
00922 @endverbatim
00923   * @{
00924   */
00925 
00926 /**
00927   * @brief  Returns the status of EN bit for the specified DMAy Streamx.
00928   * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
00929   *          to 7 to select the DMA Stream.
00930   *   
00931   * @note    After configuring the DMA Stream (DMA_Init() function) and enabling
00932   *          the stream, it is recommended to check (or wait until) the DMA Stream
00933   *          is effectively enabled. A Stream may remain disabled if a configuration
00934   *          parameter is wrong.
00935   *          After disabling a DMA Stream, it is also recommended to check (or wait 
00936   *          until) the DMA Stream is effectively disabled. If a Stream is disabled
00937   *          while a data transfer is ongoing, the current data will be transferred
00938   *          and the Stream will be effectively disabled only after the transfer
00939   *          of this single data is finished.  
00940   *      
00941   * @retval Current state of the DMAy Streamx (ENABLE or DISABLE).
00942   */
00943 FunctionalState DMA_GetCmdStatus_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx)
00944 {
00945   FunctionalState state = DISABLE;
00946 
00947   /* Check the parameters */
00948   assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
00949 
00950   if ((DMAy_Streamx->CR & (uint32_t)DMA_SxCR_EN_MORT) != 0)
00951   {
00952     /* The selected DMAy Streamx EN bit is set (DMA is still transferring) */
00953     state = ENABLE;
00954   }
00955   else
00956   {
00957     /* The selected DMAy Streamx EN bit is cleared (DMA is disabled and 
00958         all transfers are complete) */
00959     state = DISABLE;
00960   }
00961   return state;
00962 }
00963 
00964 /**
00965   * @brief  Returns the current DMAy Streamx FIFO filled level.
00966   * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 
00967   *         to 7 to select the DMA Stream.
00968   * @retval The FIFO filling state.
00969   *           - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full 
00970   *                                               and not empty.
00971   *           - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
00972   *           - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
00973   *           - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
00974   *           - DMA_FIFOStatus_Empty: when FIFO is empty
00975   *           - DMA_FIFOStatus_Full: when FIFO is full
00976   */
00977 uint32_t DMA_GetFIFOStatus_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx)
00978 {
00979   uint32_t tmpreg = 0;
00980  
00981   /* Check the parameters */
00982   assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
00983   
00984   /* Get the FIFO level bits */
00985   tmpreg = (uint32_t)((DMAy_Streamx->FCR & DMA_SxFCR_FS_MORT));
00986   
00987   return tmpreg;
00988 }
00989 
00990 /**
00991   * @brief  Checks whether the specified DMAy Streamx flag is set or not.
00992   * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
00993   *          to 7 to select the DMA Stream.
00994   * @param  DMA_FLAG: specifies the flag to check.
00995   *          This parameter can be one of the following values:
00996   *            @arg DMA_FLAG_TCIFx:  Streamx transfer complete flag
00997   *            @arg DMA_FLAG_HTIFx:  Streamx half transfer complete flag
00998   *            @arg DMA_FLAG_TEIFx:  Streamx transfer error flag
00999   *            @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag
01000   *            @arg DMA_FLAG_FEIFx:  Streamx FIFO error flag
01001   *         Where x can be 0 to 7 to select the DMA Stream.
01002   * @retval The new state of DMA_FLAG (SET or RESET).
01003   */
01004 FlagStatus DMA_GetFlagStatus_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_FLAG)
01005 {
01006   FlagStatus bitstatus = RESET;
01007   DMA_TypeDef_mort* DMAy;
01008   uint32_t tmpreg = 0;
01009 
01010   /* Check the parameters */
01011   assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
01012   assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
01013 
01014   /* Determine the DMA to which belongs the stream */
01015   if (DMAy_Streamx < DMA2_Stream0_MORT)
01016   {
01017     /* DMAy_Streamx belongs to DMA1_MORT */
01018     DMAy = DMA1_MORT; 
01019   } 
01020   else 
01021   {
01022     /* DMAy_Streamx belongs to DMA2_MORT */
01023     DMAy = DMA2_MORT; 
01024   }
01025 
01026   /* Check if the flag is in HISR or LISR */
01027   if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET)
01028   {
01029     /* Get DMAy HISR register value */
01030     tmpreg = DMAy->HISR;
01031   }
01032   else
01033   {
01034     /* Get DMAy LISR register value */
01035     tmpreg = DMAy->LISR;
01036   }   
01037  
01038   /* Mask the reserved bits */
01039   tmpreg &= (uint32_t)RESERVED_MASK;
01040 
01041   /* Check the status of the specified DMA flag */
01042   if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)
01043   {
01044     /* DMA_FLAG is set */
01045     bitstatus = SET;
01046   }
01047   else
01048   {
01049     /* DMA_FLAG is reset */
01050     bitstatus = RESET;
01051   }
01052 
01053   /* Return the DMA_FLAG status */
01054   return  bitstatus;
01055 }
01056 
01057 /**
01058   * @brief  Clears the DMAy Streamx's pending flags.
01059   * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
01060   *          to 7 to select the DMA Stream.
01061   * @param  DMA_FLAG: specifies the flag to clear.
01062   *          This parameter can be any combination of the following values:
01063   *            @arg DMA_FLAG_TCIFx:  Streamx transfer complete flag
01064   *            @arg DMA_FLAG_HTIFx:  Streamx half transfer complete flag
01065   *            @arg DMA_FLAG_TEIFx:  Streamx transfer error flag
01066   *            @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag
01067   *            @arg DMA_FLAG_FEIFx:  Streamx FIFO error flag
01068   *         Where x can be 0 to 7 to select the DMA Stream.   
01069   * @retval None
01070   */
01071 void DMA_ClearFlag_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_FLAG)
01072 {
01073   DMA_TypeDef_mort* DMAy;
01074 
01075   /* Check the parameters */
01076   assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
01077   assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
01078 
01079   /* Determine the DMA to which belongs the stream */
01080   if (DMAy_Streamx < DMA2_Stream0_MORT)
01081   {
01082     /* DMAy_Streamx belongs to DMA1_MORT */
01083     DMAy = DMA1_MORT; 
01084   } 
01085   else 
01086   {
01087     /* DMAy_Streamx belongs to DMA2_MORT */
01088     DMAy = DMA2_MORT; 
01089   }
01090 
01091   /* Check if LIFCR or HIFCR register is targeted */
01092   if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET)
01093   {
01094     /* Set DMAy HIFCR register clear flag bits */
01095     DMAy->HIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK);
01096   }
01097   else 
01098   {
01099     /* Set DMAy LIFCR register clear flag bits */
01100     DMAy->LIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK);
01101   }    
01102 }
01103 
01104 /**
01105   * @brief  Enables or disables the specified DMAy Streamx interrupts.
01106   * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
01107   *          to 7 to select the DMA Stream.
01108   * @param DMA_IT: specifies the DMA interrupt sources to be enabled or disabled. 
01109   *          This parameter can be any combination of the following values:
01110   *            @arg DMA_IT_TC_MORT_MORT:  Transfer complete interrupt mask
01111   *            @arg DMA_IT_HT_MORT:  Half transfer complete interrupt mask
01112   *            @arg DMA_IT_TE_MORT:  Transfer error interrupt mask
01113   *            @arg DMA_IT_FE_MORT:  FIFO error interrupt mask
01114   * @param  NewState: new state of the specified DMA interrupts.
01115   *          This parameter can be: ENABLE or DISABLE.
01116   * @retval None
01117   */
01118 void DMA_ITConfig_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState)
01119 {
01120   /* Check the parameters */
01121   assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
01122   assert_param(IS_DMA_CONFIG_IT(DMA_IT));
01123   assert_param(IS_FUNCTIONAL_STATE(NewState));
01124 
01125   /* Check if the DMA_IT parameter contains a FIFO interrupt */
01126   if ((DMA_IT & DMA_IT_FE_MORT) != 0)
01127   {
01128     if (NewState != DISABLE)
01129     {
01130       /* Enable the selected DMA FIFO interrupts */
01131       DMAy_Streamx->FCR |= (uint32_t)DMA_IT_FE_MORT;
01132     }    
01133     else 
01134     {
01135       /* Disable the selected DMA FIFO interrupts */
01136       DMAy_Streamx->FCR &= ~(uint32_t)DMA_IT_FE_MORT;  
01137     }
01138   }
01139 
01140   /* Check if the DMA_IT parameter contains a Transfer interrupt */
01141   if (DMA_IT != DMA_IT_FE_MORT)
01142   {
01143     if (NewState != DISABLE)
01144     {
01145       /* Enable the selected DMA transfer interrupts */
01146       DMAy_Streamx->CR |= (uint32_t)(DMA_IT  & TRANSFER_IT_ENABLE_MASK);
01147     }
01148     else
01149     {
01150       /* Disable the selected DMA transfer interrupts */
01151       DMAy_Streamx->CR &= ~(uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK);
01152     }    
01153   }
01154 }
01155 
01156 /**
01157   * @brief  Checks whether the specified DMAy Streamx interrupt has occurred or not.
01158   * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
01159   *          to 7 to select the DMA Stream.
01160   * @param  DMA_IT: specifies the DMA interrupt source to check.
01161   *          This parameter can be one of the following values:
01162   *            @arg DMA_IT_TC_MORT_MORTIFx:  Streamx transfer complete interrupt
01163   *            @arg DMA_IT_HTIFx:  Streamx half transfer complete interrupt
01164   *            @arg DMA_IT_TEIFx:  Streamx transfer error interrupt
01165   *            @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt
01166   *            @arg DMA_IT_FEIFx:  Streamx FIFO error interrupt
01167   *         Where x can be 0 to 7 to select the DMA Stream.
01168   * @retval The new state of DMA_IT (SET or RESET).
01169   */
01170 ITStatus DMA_GetITStatus_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_IT)
01171 {
01172   ITStatus bitstatus = RESET;
01173   DMA_TypeDef_mort* DMAy;
01174   uint32_t tmpreg = 0, enablestatus = 0;
01175 
01176   /* Check the parameters */
01177   assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
01178   assert_param(IS_DMA_GET_IT(DMA_IT));
01179  
01180   /* Determine the DMA to which belongs the stream */
01181   if (DMAy_Streamx < DMA2_Stream0_MORT)
01182   {
01183     /* DMAy_Streamx belongs to DMA1_MORT */
01184     DMAy = DMA1_MORT; 
01185   } 
01186   else 
01187   {
01188     /* DMAy_Streamx belongs to DMA2_MORT */
01189     DMAy = DMA2_MORT; 
01190   }
01191 
01192   /* Check if the interrupt enable bit is in the CR or FCR register */
01193   if ((DMA_IT & TRANSFER_IT_MASK) != (uint32_t)RESET)
01194   {
01195     /* Get the interrupt enable position mask in CR register */
01196     tmpreg = (uint32_t)((DMA_IT >> 11) & TRANSFER_IT_ENABLE_MASK);   
01197     
01198     /* Check the enable bit in CR register */
01199     enablestatus = (uint32_t)(DMAy_Streamx->CR & tmpreg);
01200   }
01201   else 
01202   {
01203     /* Check the enable bit in FCR register */
01204     enablestatus = (uint32_t)(DMAy_Streamx->FCR & DMA_IT_FE_MORT); 
01205   }
01206  
01207   /* Check if the interrupt pending flag is in LISR or HISR */
01208   if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET)
01209   {
01210     /* Get DMAy HISR register value */
01211     tmpreg = DMAy->HISR ;
01212   }
01213   else
01214   {
01215     /* Get DMAy LISR register value */
01216     tmpreg = DMAy->LISR ;
01217   } 
01218 
01219   /* mask all reserved bits */
01220   tmpreg &= (uint32_t)RESERVED_MASK;
01221 
01222   /* Check the status of the specified DMA interrupt */
01223   if (((tmpreg & DMA_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
01224   {
01225     /* DMA_IT is set */
01226     bitstatus = SET;
01227   }
01228   else
01229   {
01230     /* DMA_IT is reset */
01231     bitstatus = RESET;
01232   }
01233 
01234   /* Return the DMA_IT status */
01235   return  bitstatus;
01236 }
01237 
01238 /**
01239   * @brief  Clears the DMAy Streamx's interrupt pending bits.
01240   * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
01241   *          to 7 to select the DMA Stream.
01242   * @param  DMA_IT: specifies the DMA interrupt pending bit to clear.
01243   *          This parameter can be any combination of the following values:
01244   *            @arg DMA_IT_TC_MORT_MORTIFx:  Streamx transfer complete interrupt
01245   *            @arg DMA_IT_HTIFx:  Streamx half transfer complete interrupt
01246   *            @arg DMA_IT_TEIFx:  Streamx transfer error interrupt
01247   *            @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt
01248   *            @arg DMA_IT_FEIFx:  Streamx FIFO error interrupt
01249   *         Where x can be 0 to 7 to select the DMA Stream.
01250   * @retval None
01251   */
01252 void DMA_ClearITPendingBit_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_IT)
01253 {
01254   DMA_TypeDef_mort* DMAy;
01255 
01256   /* Check the parameters */
01257   assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
01258   assert_param(IS_DMA_CLEAR_IT(DMA_IT));
01259 
01260   /* Determine the DMA to which belongs the stream */
01261   if (DMAy_Streamx < DMA2_Stream0_MORT)
01262   {
01263     /* DMAy_Streamx belongs to DMA1_MORT */
01264     DMAy = DMA1_MORT; 
01265   } 
01266   else 
01267   {
01268     /* DMAy_Streamx belongs to DMA2_MORT */
01269     DMAy = DMA2_MORT; 
01270   }
01271 
01272   /* Check if LIFCR or HIFCR register is targeted */
01273   if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET)
01274   {
01275     /* Set DMAy HIFCR register clear interrupt bits */
01276     DMAy->HIFCR = (uint32_t)(DMA_IT & RESERVED_MASK);
01277   }
01278   else 
01279   {
01280     /* Set DMAy LIFCR register clear interrupt bits */
01281     DMAy->LIFCR = (uint32_t)(DMA_IT & RESERVED_MASK);
01282   }   
01283 }
01284 
01285 /**
01286   * @}
01287   */
01288 
01289 /**
01290   * @}
01291   */
01292 
01293 /**
01294   * @}
01295   */
01296 
01297 /**
01298   * @}
01299   */
01300 
01301 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
01302 
01303 
01304 
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