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ravi_blinkycode
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stm32f4xx_adc_mort.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_adc_mort.h 00004 * @author MCD Application Team 00005 * @version V1.8.0 00006 * @date 04-November-2016 00007 * @brief This file contains all the functions prototypes for the ADC firmware 00008 * library. 00009 ****************************************************************************** 00010 * @attention 00011 * 00012 * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2> 00013 * 00014 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 00015 * You may not use this file except in compliance with the License. 00016 * You may obtain a copy of the License at: 00017 * 00018 * http://www.st.com/software_license_agreement_liberty_v2 00019 * 00020 * Unless required by applicable law or agreed to in writing, software 00021 * distributed under the License is distributed on an "AS IS" BASIS, 00022 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00023 * See the License for the specific language governing permissions and 00024 * limitations under the License. 00025 * 00026 ****************************************************************************** 00027 */ 00028 00029 /* Define to prevent recursive inclusion -------------------------------------*/ 00030 #ifndef __STM32F4xx_ADC_H_MORT 00031 #define __STM32F4xx_ADC_H_MORT 00032 00033 #ifdef __cplusplus 00034 extern "C" { 00035 #endif 00036 00037 /* Includes ------------------------------------------------------------------*/ 00038 #include "stm32f4xx_mort2.h" 00039 00040 /** @addtogroup STM32F4xx_StdPeriph_Driver 00041 * @{ 00042 */ 00043 00044 /** @addtogroup ADC 00045 * @{ 00046 */ 00047 00048 /* Exported types ------------------------------------------------------------*/ 00049 00050 /** 00051 * @brief ADC Init structure definition 00052 */ 00053 typedef struct 00054 { 00055 uint32_t ADC_Resolution; /*!< Configures the ADC resolution dual mode. 00056 This parameter can be a value of @ref ADC_resolution */ 00057 FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion 00058 is performed in Scan (multichannels) 00059 or Single (one channel) mode. 00060 This parameter can be set to ENABLE or DISABLE */ 00061 FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion 00062 is performed in Continuous or Single mode. 00063 This parameter can be set to ENABLE or DISABLE. */ 00064 uint32_t ADC_ExternalTrigConvEdge; /*!< Select the external trigger edge and 00065 enable the trigger of a regular group. 00066 This parameter can be a value of 00067 @ref ADC_external_trigger_edge_for_regular_channels_conversion */ 00068 uint32_t ADC_ExternalTrigConv; /*!< Select the external event used to trigger 00069 the start of conversion of a regular group. 00070 This parameter can be a value of 00071 @ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */ 00072 uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment 00073 is left or right. This parameter can be 00074 a value of @ref ADC_data_align */ 00075 uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions 00076 that will be done using the sequencer for 00077 regular channel group. 00078 This parameter must range from 1 to 16. */ 00079 }ADC_InitTypeDef_mort; 00080 00081 /** 00082 * @brief ADC Common Init structure definition 00083 */ 00084 typedef struct 00085 { 00086 uint32_t ADC_Mode; /*!< Configures the ADC to operate in 00087 independent or multi mode. 00088 This parameter can be a value of @ref ADC_Common_mode */ 00089 uint32_t ADC_Prescaler; /*!< Select the frequency of the clock 00090 to the ADC. The clock is common for all the ADCs. 00091 This parameter can be a value of @ref ADC_Prescaler */ 00092 uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access 00093 mode for multi ADC mode. 00094 This parameter can be a value of 00095 @ref ADC_Direct_memory_access_mode_for_multi_mode */ 00096 uint32_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. 00097 This parameter can be a value of 00098 @ref ADC_delay_between_2_sampling_phases */ 00099 00100 }ADC_CommonInitTypeDef_mort; 00101 00102 00103 /* Exported constants --------------------------------------------------------*/ 00104 00105 /** @defgroup ADC_Exported_Constants 00106 * @{ 00107 */ 00108 #define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ 00109 ((PERIPH) == ADC2) || \ 00110 ((PERIPH) == ADC3)) 00111 00112 /** @defgroup ADC_Common_mode 00113 * @{ 00114 */ 00115 #define ADC_Mode_Independent ((uint32_t)0x00000000) 00116 #define ADC_DualMode_RegSimult_InjecSimult ((uint32_t)0x00000001) 00117 #define ADC_DualMode_RegSimult_AlterTrig ((uint32_t)0x00000002) 00118 #define ADC_DualMode_InjecSimult ((uint32_t)0x00000005) 00119 #define ADC_DualMode_RegSimult ((uint32_t)0x00000006) 00120 #define ADC_DualMode_Interl ((uint32_t)0x00000007) 00121 #define ADC_DualMode_AlterTrig ((uint32_t)0x00000009) 00122 #define ADC_TripleMode_RegSimult_InjecSimult ((uint32_t)0x00000011) 00123 #define ADC_TripleMode_RegSimult_AlterTrig ((uint32_t)0x00000012) 00124 #define ADC_TripleMode_InjecSimult ((uint32_t)0x00000015) 00125 #define ADC_TripleMode_RegSimult ((uint32_t)0x00000016) 00126 #define ADC_TripleMode_Interl ((uint32_t)0x00000017) 00127 #define ADC_TripleMode_AlterTrig ((uint32_t)0x00000019) 00128 #define IS_ADC_MODE_MORT(MODE) (((MODE) == ADC_Mode_Independent) || \ 00129 ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \ 00130 ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \ 00131 ((MODE) == ADC_DualMode_InjecSimult) || \ 00132 ((MODE) == ADC_DualMode_RegSimult) || \ 00133 ((MODE) == ADC_DualMode_Interl) || \ 00134 ((MODE) == ADC_DualMode_AlterTrig) || \ 00135 ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \ 00136 ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \ 00137 ((MODE) == ADC_TripleMode_InjecSimult) || \ 00138 ((MODE) == ADC_TripleMode_RegSimult) || \ 00139 ((MODE) == ADC_TripleMode_Interl) || \ 00140 ((MODE) == ADC_TripleMode_AlterTrig)) 00141 /** 00142 * @} 00143 */ 00144 00145 00146 /** @defgroup ADC_Prescaler 00147 * @{ 00148 */ 00149 #define ADC_Prescaler_Div2 ((uint32_t)0x00000000) 00150 #define ADC_Prescaler_Div4 ((uint32_t)0x00010000) 00151 #define ADC_Prescaler_Div6 ((uint32_t)0x00020000) 00152 #define ADC_Prescaler_Div8 ((uint32_t)0x00030000) 00153 #define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \ 00154 ((PRESCALER) == ADC_Prescaler_Div4) || \ 00155 ((PRESCALER) == ADC_Prescaler_Div6) || \ 00156 ((PRESCALER) == ADC_Prescaler_Div8)) 00157 /** 00158 * @} 00159 */ 00160 00161 00162 /** @defgroup ADC_Direct_memory_access_mode_for_multi_mode 00163 * @{ 00164 */ 00165 #define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /* DMA mode disabled */ 00166 #define ADC_DMAAccessMode_1 ((uint32_t)0x00004000) /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/ 00167 #define ADC_DMAAccessMode_2 ((uint32_t)0x00008000) /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/ 00168 #define ADC_DMAAccessMode_3 ((uint32_t)0x0000C000) /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */ 00169 #define IS_ADC_DMA_ACCESS_MODE_MORT(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \ 00170 ((MODE) == ADC_DMAAccessMode_1) || \ 00171 ((MODE) == ADC_DMAAccessMode_2) || \ 00172 ((MODE) == ADC_DMAAccessMode_3)) 00173 00174 /** 00175 * @} 00176 */ 00177 00178 00179 /** @defgroup ADC_delay_between_2_sampling_phases 00180 * @{ 00181 */ 00182 #define ADC_TwoSamplingDelay_5Cycles ((uint32_t)0x00000000) 00183 #define ADC_TwoSamplingDelay_6Cycles ((uint32_t)0x00000100) 00184 #define ADC_TwoSamplingDelay_7Cycles ((uint32_t)0x00000200) 00185 #define ADC_TwoSamplingDelay_8Cycles ((uint32_t)0x00000300) 00186 #define ADC_TwoSamplingDelay_9Cycles ((uint32_t)0x00000400) 00187 #define ADC_TwoSamplingDelay_10Cycles ((uint32_t)0x00000500) 00188 #define ADC_TwoSamplingDelay_11Cycles ((uint32_t)0x00000600) 00189 #define ADC_TwoSamplingDelay_12Cycles ((uint32_t)0x00000700) 00190 #define ADC_TwoSamplingDelay_13Cycles ((uint32_t)0x00000800) 00191 #define ADC_TwoSamplingDelay_14Cycles ((uint32_t)0x00000900) 00192 #define ADC_TwoSamplingDelay_15Cycles ((uint32_t)0x00000A00) 00193 #define ADC_TwoSamplingDelay_16Cycles ((uint32_t)0x00000B00) 00194 #define ADC_TwoSamplingDelay_17Cycles ((uint32_t)0x00000C00) 00195 #define ADC_TwoSamplingDelay_18Cycles ((uint32_t)0x00000D00) 00196 #define ADC_TwoSamplingDelay_19Cycles ((uint32_t)0x00000E00) 00197 #define ADC_TwoSamplingDelay_20Cycles ((uint32_t)0x00000F00) 00198 #define IS_ADC_SAMPLING_DELAY_MORT(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \ 00199 ((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \ 00200 ((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \ 00201 ((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \ 00202 ((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \ 00203 ((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \ 00204 ((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \ 00205 ((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \ 00206 ((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \ 00207 ((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \ 00208 ((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \ 00209 ((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \ 00210 ((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \ 00211 ((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \ 00212 ((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \ 00213 ((DELAY) == ADC_TwoSamplingDelay_20Cycles)) 00214 00215 /** 00216 * @} 00217 */ 00218 00219 00220 /** @defgroup ADC_resolution 00221 * @{ 00222 */ 00223 #define ADC_Resolution_12b ((uint32_t)0x00000000) 00224 #define ADC_Resolution_10b ((uint32_t)0x01000000) 00225 #define ADC_Resolution_8b ((uint32_t)0x02000000) 00226 #define ADC_Resolution_6b ((uint32_t)0x03000000) 00227 #define IS_ADC_RESOLUTION_MORT(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \ 00228 ((RESOLUTION) == ADC_Resolution_10b) || \ 00229 ((RESOLUTION) == ADC_Resolution_8b) || \ 00230 ((RESOLUTION) == ADC_Resolution_6b)) 00231 00232 /** 00233 * @} 00234 */ 00235 00236 00237 /** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion 00238 * @{ 00239 */ 00240 #define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000) 00241 #define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000) 00242 #define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000) 00243 #define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000) 00244 #define IS_ADC_EXT_TRIG_EDGE_MORT(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \ 00245 ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \ 00246 ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \ 00247 ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling)) 00248 /** 00249 * @} 00250 */ 00251 00252 00253 /** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion 00254 * @{ 00255 */ 00256 #define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) 00257 #define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x01000000) 00258 #define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x02000000) 00259 #define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000) 00260 #define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x04000000) 00261 #define ADC_ExternalTrigConv_T2_CC4 ((uint32_t)0x05000000) 00262 #define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000) 00263 #define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000) 00264 #define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x08000000) 00265 #define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x09000000) 00266 #define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x0A000000) 00267 #define ADC_ExternalTrigConv_T5_CC2 ((uint32_t)0x0B000000) 00268 #define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x0C000000) 00269 #define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x0D000000) 00270 #define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x0E000000) 00271 #define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000) 00272 #define IS_ADC_EXT_TRIG_MORT(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ 00273 ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ 00274 ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ 00275 ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ 00276 ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ 00277 ((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \ 00278 ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \ 00279 ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ 00280 ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ 00281 ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ 00282 ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ 00283 ((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \ 00284 ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \ 00285 ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ 00286 ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ 00287 ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11)) 00288 /** 00289 * @} 00290 */ 00291 00292 00293 /** @defgroup ADC_data_align 00294 * @{ 00295 */ 00296 #define ADC_DataAlign_Right ((uint32_t)0x00000000) 00297 #define ADC_DataAlign_Left ((uint32_t)0x00000800) 00298 #define IS_ADC_DATA_ALIGN_MORT(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ 00299 ((ALIGN) == ADC_DataAlign_Left)) 00300 /** 00301 * @} 00302 */ 00303 00304 00305 /** @defgroup ADC_channels 00306 * @{ 00307 */ 00308 #define ADC_Channel_0 ((uint8_t)0x00) 00309 #define ADC_Channel_1 ((uint8_t)0x01) 00310 #define ADC_Channel_2 ((uint8_t)0x02) 00311 #define ADC_Channel_3 ((uint8_t)0x03) 00312 #define ADC_Channel_4 ((uint8_t)0x04) 00313 #define ADC_Channel_5 ((uint8_t)0x05) 00314 #define ADC_Channel_6 ((uint8_t)0x06) 00315 #define ADC_Channel_7 ((uint8_t)0x07) 00316 #define ADC_Channel_8 ((uint8_t)0x08) 00317 #define ADC_Channel_9 ((uint8_t)0x09) 00318 #define ADC_Channel_10 ((uint8_t)0x0A) 00319 #define ADC_Channel_11 ((uint8_t)0x0B) 00320 #define ADC_Channel_12 ((uint8_t)0x0C) 00321 #define ADC_Channel_13 ((uint8_t)0x0D) 00322 #define ADC_Channel_14 ((uint8_t)0x0E) 00323 #define ADC_Channel_15 ((uint8_t)0x0F) 00324 #define ADC_Channel_16 ((uint8_t)0x10) 00325 #define ADC_Channel_17 ((uint8_t)0x11) 00326 #define ADC_Channel_18 ((uint8_t)0x12) 00327 00328 #if defined (STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) 00329 #define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) 00330 #endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */ 00331 00332 #if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx) || defined (STM32F410xx) || defined (STM32F411xE) 00333 #define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_18) 00334 #endif /* STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE */ 00335 00336 #define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) 00337 #define ADC_Channel_Vbat ((uint8_t)ADC_Channel_18) 00338 00339 #define IS_ADC_CHANNEL_MORT(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \ 00340 ((CHANNEL) == ADC_Channel_1) || \ 00341 ((CHANNEL) == ADC_Channel_2) || \ 00342 ((CHANNEL) == ADC_Channel_3) || \ 00343 ((CHANNEL) == ADC_Channel_4) || \ 00344 ((CHANNEL) == ADC_Channel_5) || \ 00345 ((CHANNEL) == ADC_Channel_6) || \ 00346 ((CHANNEL) == ADC_Channel_7) || \ 00347 ((CHANNEL) == ADC_Channel_8) || \ 00348 ((CHANNEL) == ADC_Channel_9) || \ 00349 ((CHANNEL) == ADC_Channel_10) || \ 00350 ((CHANNEL) == ADC_Channel_11) || \ 00351 ((CHANNEL) == ADC_Channel_12) || \ 00352 ((CHANNEL) == ADC_Channel_13) || \ 00353 ((CHANNEL) == ADC_Channel_14) || \ 00354 ((CHANNEL) == ADC_Channel_15) || \ 00355 ((CHANNEL) == ADC_Channel_16) || \ 00356 ((CHANNEL) == ADC_Channel_17) || \ 00357 ((CHANNEL) == ADC_Channel_18)) 00358 /** 00359 * @} 00360 */ 00361 00362 00363 /** @defgroup ADC_sampling_times 00364 * @{ 00365 */ 00366 #define ADC_SampleTime_3Cycles ((uint8_t)0x00) 00367 #define ADC_SampleTime_15Cycles ((uint8_t)0x01) 00368 #define ADC_SampleTime_28Cycles ((uint8_t)0x02) 00369 #define ADC_SampleTime_56Cycles ((uint8_t)0x03) 00370 #define ADC_SampleTime_84Cycles ((uint8_t)0x04) 00371 #define ADC_SampleTime_112Cycles ((uint8_t)0x05) 00372 #define ADC_SampleTime_144Cycles ((uint8_t)0x06) 00373 #define ADC_SampleTime_480Cycles ((uint8_t)0x07) 00374 #define IS_ADC_SAMPLE_TIME_MORT(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \ 00375 ((TIME) == ADC_SampleTime_15Cycles) || \ 00376 ((TIME) == ADC_SampleTime_28Cycles) || \ 00377 ((TIME) == ADC_SampleTime_56Cycles) || \ 00378 ((TIME) == ADC_SampleTime_84Cycles) || \ 00379 ((TIME) == ADC_SampleTime_112Cycles) || \ 00380 ((TIME) == ADC_SampleTime_144Cycles) || \ 00381 ((TIME) == ADC_SampleTime_480Cycles)) 00382 /** 00383 * @} 00384 */ 00385 00386 00387 /** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion 00388 * @{ 00389 */ 00390 #define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000) 00391 #define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000) 00392 #define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000) 00393 #define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000) 00394 #define IS_ADC_EXT_INJEC_TRIG_EDGE_MORT(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \ 00395 ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \ 00396 ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \ 00397 ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling)) 00398 00399 /** 00400 * @} 00401 */ 00402 00403 00404 /** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion 00405 * @{ 00406 */ 00407 #define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00000000) 00408 #define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00010000) 00409 #define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00020000) 00410 #define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00030000) 00411 #define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00040000) 00412 #define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00050000) 00413 #define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000) 00414 #define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000) 00415 #define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000) 00416 #define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00090000) 00417 #define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x000A0000) 00418 #define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x000B0000) 00419 #define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x000C0000) 00420 #define ADC_ExternalTrigInjecConv_T8_CC3 ((uint32_t)0x000D0000) 00421 #define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x000E0000) 00422 #define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000) 00423 #define IS_ADC_EXT_INJEC_TRIG_MORT(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ 00424 ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ 00425 ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ 00426 ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ 00427 ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \ 00428 ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ 00429 ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \ 00430 ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \ 00431 ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ 00432 ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ 00433 ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \ 00434 ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ 00435 ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ 00436 ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \ 00437 ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ 00438 ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15)) 00439 /** 00440 * @} 00441 */ 00442 00443 00444 /** @defgroup ADC_injected_channel_selection 00445 * @{ 00446 */ 00447 #define ADC_InjectedChannel_1 ((uint8_t)0x14) 00448 #define ADC_InjectedChannel_2 ((uint8_t)0x18) 00449 #define ADC_InjectedChannel_3 ((uint8_t)0x1C) 00450 #define ADC_InjectedChannel_4 ((uint8_t)0x20) 00451 #define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ 00452 ((CHANNEL) == ADC_InjectedChannel_2) || \ 00453 ((CHANNEL) == ADC_InjectedChannel_3) || \ 00454 ((CHANNEL) == ADC_InjectedChannel_4)) 00455 /** 00456 * @} 00457 */ 00458 00459 00460 /** @defgroup ADC_analog_watchdog_selection 00461 * @{ 00462 */ 00463 #define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) 00464 #define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) 00465 #define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) 00466 #define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) 00467 #define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) 00468 #define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) 00469 #define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) 00470 #define IS_ADC_ANALOG_WATCHDOG_MORT(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ 00471 ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ 00472 ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ 00473 ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ 00474 ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ 00475 ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ 00476 ((WATCHDOG) == ADC_AnalogWatchdog_None)) 00477 /** 00478 * @} 00479 */ 00480 00481 00482 /** @defgroup ADC_interrupts_definition 00483 * @{ 00484 */ 00485 #define ADC_IT_EOC_MORT ((uint16_t)0x0205) 00486 #define ADC_IT_AWD_MORT ((uint16_t)0x0106) 00487 #define ADC_IT_JEOC_MORT ((uint16_t)0x0407) 00488 #define ADC_IT_OVR_MORT ((uint16_t)0x201A) 00489 #define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC_MORT) || ((IT) == ADC_IT_AWD_MORT) || \ 00490 ((IT) == ADC_IT_JEOC_MORT)|| ((IT) == ADC_IT_OVR_MORT)) 00491 /** 00492 * @} 00493 */ 00494 00495 00496 /** @defgroup ADC_flags_definition 00497 * @{ 00498 */ 00499 #define ADC_FLAG_AWD_MORT ((uint8_t)0x01) 00500 #define ADC_FLAG_EOC_MORT ((uint8_t)0x02) 00501 #define ADC_FLAG_JEOC_MORT ((uint8_t)0x04) 00502 #define ADC_FLAG_JSTRT_MORT ((uint8_t)0x08) 00503 #define ADC_FLAG_STRT_MORT ((uint8_t)0x10) 00504 #define ADC_FLAG_OVR_MORT ((uint8_t)0x20) 00505 00506 #define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00)) 00507 #define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD_MORT) || \ 00508 ((FLAG) == ADC_FLAG_EOC_MORT) || \ 00509 ((FLAG) == ADC_FLAG_JEOC_MORT) || \ 00510 ((FLAG)== ADC_FLAG_JSTRT_MORT) || \ 00511 ((FLAG) == ADC_FLAG_STRT_MORT) || \ 00512 ((FLAG)== ADC_FLAG_OVR_MORT)) 00513 /** 00514 * @} 00515 */ 00516 00517 00518 /** @defgroup ADC_thresholds 00519 * @{ 00520 */ 00521 #define IS_ADC_THRESHOLD_MORT(THRESHOLD) ((THRESHOLD) <= 0xFFF) 00522 /** 00523 * @} 00524 */ 00525 00526 00527 /** @defgroup ADC_injected_offset 00528 * @{ 00529 */ 00530 #define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) 00531 /** 00532 * @} 00533 */ 00534 00535 00536 /** @defgroup ADC_injected_length 00537 * @{ 00538 */ 00539 #define IS_ADC_INJECTED_LENGTH_MORT(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) 00540 /** 00541 * @} 00542 */ 00543 00544 00545 /** @defgroup ADC_injected_rank 00546 * @{ 00547 */ 00548 #define IS_ADC_INJECTED_RANK_MORT(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) 00549 /** 00550 * @} 00551 */ 00552 00553 00554 /** @defgroup ADC_regular_length 00555 * @{ 00556 */ 00557 #define IS_ADC_REGULAR_LENGTH_MORT(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) 00558 /** 00559 * @} 00560 */ 00561 00562 00563 /** @defgroup ADC_regular_rank 00564 * @{ 00565 */ 00566 #define IS_ADC_REGULAR_RANK_MORT(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) 00567 /** 00568 * @} 00569 */ 00570 00571 00572 /** @defgroup ADC_regular_discontinuous_mode_number 00573 * @{ 00574 */ 00575 #define IS_ADC_REGULAR_DISC_NUMBER_MORT(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) 00576 /** 00577 * @} 00578 */ 00579 00580 00581 /** 00582 * @} 00583 */ 00584 00585 /* Exported macro ------------------------------------------------------------*/ 00586 /* Exported functions --------------------------------------------------------*/ 00587 00588 /* Function used to set the ADC configuration to the default reset state *****/ 00589 void ADC_DeInit_mort(void); 00590 00591 /* Initialization and Configuration functions *********************************/ 00592 void ADC_Init_mort(ADC_TypeDef_mort* ADCx, ADC_InitTypeDef_mort* ADC_InitStruct); 00593 void ADC_StructInit_mort(ADC_InitTypeDef_mort* ADC_InitStruct); 00594 void ADC_CommonInit_mort(ADC_CommonInitTypeDef_mort* ADC_CommonInitStruct); 00595 void ADC_CommonStructInit_mort(ADC_CommonInitTypeDef_mort* ADC_CommonInitStruct); 00596 void ADC_Cmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState); 00597 00598 /* Analog Watchdog configuration functions ************************************/ 00599 void ADC_AnalogWatchdogCmd_mort(ADC_TypeDef_mort* ADCx, uint32_t ADC_AnalogWatchdog); 00600 void ADC_AnalogWatchdogThresholdsConfig_mort(ADC_TypeDef_mort* ADCx, uint16_t HighThreshold,uint16_t LowThreshold); 00601 void ADC_AnalogWatchdogSingleChannelConfig_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_Channel); 00602 00603 /* Temperature Sensor, Vrefint and VBAT management functions ******************/ 00604 void ADC_TempSensorVrefintCmd_mort(FunctionalState NewState); 00605 void ADC_VBATCmd_mort(FunctionalState NewState); 00606 00607 /* Regular Channels Configuration functions ***********************************/ 00608 void ADC_RegularChannelConfig_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); 00609 void ADC_SoftwareStartConv_mort(ADC_TypeDef_mort* ADCx); 00610 FlagStatus ADC_GetSoftwareStartConvStatus_mort(ADC_TypeDef_mort* ADCx); 00611 void ADC_EOCOnEachRegularChannelCmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState); 00612 void ADC_ContinuousModeCmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState); 00613 void ADC_DiscModeChannelCountConfig_mort(ADC_TypeDef_mort* ADCx, uint8_t Number); 00614 void ADC_DiscModeCmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState); 00615 uint16_t ADC_GetConversionValue_mort(ADC_TypeDef_mort* ADCx); 00616 uint32_t ADC_GetMultiModeConversionValue_mort(void); 00617 00618 /* Regular Channels DMA Configuration functions *******************************/ 00619 void ADC_DMACmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState); 00620 void ADC_DMARequestAfterLastTransferCmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState); 00621 void ADC_MultiModeDMARequestAfterLastTransferCmd_mort(FunctionalState NewState); 00622 00623 /* Injected channels Configuration functions **********************************/ 00624 void ADC_InjectedChannelConfig_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); 00625 void ADC_InjectedSequencerLengthConfig_mort(ADC_TypeDef_mort* ADCx, uint8_t Length); 00626 void ADC_SetInjectedOffset_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); 00627 void ADC_ExternalTrigInjectedConvConfig_mort(ADC_TypeDef_mort* ADCx, uint32_t ADC_ExternalTrigInjecConv); 00628 void ADC_ExternalTrigInjectedConvEdgeConfig_mort(ADC_TypeDef_mort* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge); 00629 void ADC_SoftwareStartInjectedConv_mort(ADC_TypeDef_mort* ADCx); 00630 FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus_mort(ADC_TypeDef_mort* ADCx); 00631 void ADC_AutoInjectedConvCmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState); 00632 void ADC_InjectedDiscModeCmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState); 00633 uint16_t ADC_GetInjectedConversionValue_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_InjectedChannel); 00634 00635 /* Interrupts and flags management functions **********************************/ 00636 void ADC_ITConfig_mort(ADC_TypeDef_mort* ADCx, uint16_t ADC_IT, FunctionalState NewState); 00637 FlagStatus ADC_GetFlagStatus_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_FLAG); 00638 void ADC_ClearFlag_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_FLAG); 00639 ITStatus ADC_GetITStatus_mort(ADC_TypeDef_mort* ADCx, uint16_t ADC_IT); 00640 void ADC_ClearITPendingBit_mort(ADC_TypeDef_mort* ADCx, uint16_t ADC_IT); 00641 00642 #ifdef __cplusplus 00643 } 00644 #endif 00645 00646 #endif /*__STM32F4xx_ADC_H_MORT */ 00647 00648 /** 00649 * @} 00650 */ 00651 00652 /** 00653 * @} 00654 */ 00655 00656 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 00657 00658 00659 00660 00661
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