interrupt.c

00001 #include "hardware_timer3.h"
00002 #include "gpio.h"
00003 #include "stm32f4xx_rcc_mort.h"
00004 #include "interrupt.h"
00005 
00006 /*Below are defined all Timers and flags required */ //COPYING ALL VALUES AND DEFINITIONS FROM HARDWARE_TIMER3.C
00007 #define TIM3_BASE_ADDRESS ((uint32_t)0x40000400)
00008 #define TIM3_STATUS_REGISTER (TIM3_BASE_ADDRESS + 0x10)
00009 #define TIM3_PSC_REGISTER (TIM3_BASE_ADDRESS + 0x28)
00010 #define TIM3_AUTORELOAD_REGISTER (TIM3_BASE_ADDRESS + 0x2C)
00011 #define TIM3_COUNTER_REGISTER (TIM3_BASE_ADDRESS + 0x24)
00012 #define TIM3_CAPTURE_COMPARE_MODE_2_REGISTER (TIM3_BASE_ADDRESS + 0x1C)
00013 #define TIM_CCMR13_OC1M_0 (0b00010000)
00014 #define TIM_CCMR13_OC1M_1 (0b00100000)
00015 #define TIM_CCMR13_OC1M_2 (0b01000000)
00016 #define TIM_CCMR13_OCPE (0b00001000)
00017 #define TIM_CCMR23_
00018 #define TIM_CCMR13_OUTPUT 0x00
00019 #define TIM3_COMPARE3_REGISTER (TIM3_BASE_ADDRESS + 0x3C)
00020 #define TIM3_CAPTURE_COMPARE_ENABLE_REGISTER (TIM3_BASE_ADDRESS + 0x20)
00021 #define TIM3_CR1_REGISTER1 (TIM3_BASE_ADDRESS + 0x00)
00022 #define TIM3_CAPTURE_COMPARE_MODE_1_REGISTER (TIM3_BASE_ADDRESS + 0x18)
00023 #define TIM3_CAPTURE_COMPARE_REGISTER_1 (TIM3_BASE_ADDRESS + 0x34)
00024 
00025 #define TIM3_CCMR2_CC3S_OUTPUT (0b11111100)
00026 #define TIM3_CCMR2_OC3FE (0b11111011)
00027 #define TIM3_CCMR2_OC3PE (0b00001000)
00028 #define TIM3_CCMR2_OC3M1 (0b11101111)
00029 #define TIM3_CCMR2_OC3M2 (0b01100000)
00030 
00031 # define TIM3_INTERRUPT_ENABLE_REGISTER (TIM3_BASE_ADDRESS + 0x0C)
00032 
00033 /* MACRO definitions----------------------------------------------------------*/
00034 #define SYSTEM_CONTROL_BASE_ADDRESS (0xE000E000)
00035 #define NVIC_BASE_ADDRESS (SYSTEM_CONTROL_BASE_ADDRESS + 0x100)
00036 #define NVIC_INTERRUPT_SET_ENABLE_REGISTER_0_31 (NVIC_BASE_ADDRESS)
00037 #define NVIC_INTERRUPT_SET_ENABLE_REGISTER_32_63 (NVIC_BASE_ADDRESS+0x4)
00038 #define NVIC_INTERRUPT_SET_ENABLE_REGISTER_64_95 (NVIC_BASE_ADDRESS+0x8)
00039 #define TIM3_INTERRUPT_BIT (0x20000000)
00040 
00041 #define NVIC_INTERRUPT_CLEAR_ENABLE_REGISTER_0_31 (NVIC_BASE_ADDRESS + 0x80)
00042 #define NVIC_INTERRUPT_CLEAR_ENABLE_REGISTER_32_63 (NVIC_INTERRUPT_CLEAR_ENABLE_REGISTER_0_31 + 0x4)
00043 #define NVIC_INTERRUPT_CLEAR_ENABLE_REGISTER_64_95 (NVIC_INTERRUPT_CLEAR_ENABLE_REGISTER_0_31 + 0x8)
00044 #define NVIC_INTERRUPT_SET_PENDING_REGISTER_0_31 (NVIC_BASE_ADDRESS + 0x100)
00045 #define NVIC_INTERRUPT_SET_PENDING_REGISTER_32_63 (NVIC_INTERRUPT_SET_PENDING_REGISTER_0_31 + 0x4)
00046 #define NVIC_INTERRUPT_SET_PENDING_REGISTER_64_95 (NVIC_INTERRUPT_SET_PENDING_REGISTER_0_31 + 0x8)
00047 #define NVIC_INTERRUPT_CLEAR_PENDING_REGISTER_0_31 (NVIC_BASE_ADDRESS + 0x180)
00048 #define NVIC_INTERRUPT_CLEAR_PENDING_REGISTER_32_63 (NVIC_INTERRUPT_CLEAR_PENDING_REGISTER_0_31 + 0x4)
00049 #define NVIC_INTERRUPT_CLEAR_PENDING_REGISTER_64_95 (NVIC_INTERRUPT_CLEAR_PENDING_REGISTER_0_31 + 0x8)
00050 #define EXTI9_5_INTERRUPT_BIT (0x800000)
00051 
00052 //For external interrupts:
00053 #define SYSCFG_BASE_ADDRESS ((uint32_t)(0x40013800))
00054 #define SYSCFG_EXTERNAL_INTERRUPT_REGISTER_2 (SYSCFG_BASE_ADDRESS + 0x0C)
00055 #define SYSCFG_EXTERNAL_INTERRUPT_6_BITS ((uint32_t)0xF00) //flags for External interrupt register 2
00056 #define SYSCFG_EXTERNAL_INTERRUPT_6_PORTC ((uint32_t)0x200) 
00057 //External interrupt controller :
00058 #define EXTERNAL_INTERRUPT_CONTROLLER_BASE_ADDRESS ((uint32_t)(0x40013C00))
00059 #define EXTERNAL_INTERRUPT_CONTROLLER_MASK_REGISTER (EXTERNAL_INTERRUPT_CONTROLLER_BASE_ADDRESS)
00060 #define EXTERNAL_INTERRUPT_CONTROLLER_MASK_REGISTER_EXTI6 ((uint32_t)0x40) //flags for external interrupt controller mask register
00061 #define EXTERNAL_INTERRUPT_CONTROLLER_RTSR (EXTERNAL_INTERRUPT_CONTROLLER_BASE_ADDRESS+0x08)
00062 #define EXTERNAL_INTERRUPT_CONTROLLER_RTSR_EXTI6 ((uint32_t)0x40)
00063 #define EXTERNAL_INTERRUPT_CONTROLLER_FTSR (EXTERNAL_INTERRUPT_CONTROLLER_BASE_ADDRESS+0x0C)
00064 #define EXTERNAL_INTERRUPT_CONTROLLER_FTSR_EXTI6 ((uint32_t)0x40)
00065 #define EXTERNAL_INTERRUPT_CONTROLLER_PENDING_REGISTER (EXTERNAL_INTERRUPT_CONTROLLER_BASE_ADDRESS+0x14)
00066 #define EXTERNAL_INTERRUPT_CONTROLLER_PENDING_EXTI6 ((uint32_t)0x40)
00067 
00068 
00069 void enableNVIC_Timer3(void)
00070 {
00071     uint32_t * reg;
00072     reg = (uint32_t *)NVIC_INTERRUPT_SET_ENABLE_REGISTER_0_31;
00073     *reg = TIM3_INTERRUPT_BIT; 
00074 }
00075 
00076 void TIM3_IRQHandler(void)
00077 {
00078     uint16_t * reg_pointer_16_sr;
00079     uint16_t * reg_pointer_16_dier;
00080     reg_pointer_16_sr = (uint16_t *)TIM3_STATUS_REGISTER;
00081     reg_pointer_16_dier = (uint16_t *)TIM3_INTERRUPT_ENABLE_REGISTER;
00082  //check which interrupts fired and if they were supposed to fire, then clear the flags so they don’t keep firing,
00083 // then perform actions according to these interrupts
00084 //check if Output Compare 3 triggered the interrupt:
00085     if (( (*reg_pointer_16_sr & 0x8) >0) && ( (*reg_pointer_16_dier & 0x8) >0))
00086     {
00087  //clear interrupt
00088     *reg_pointer_16_sr = ~((uint16_t)0x8);
00089  //perform action
00090     clearGPIOB0(); 
00091      }
00092 //check if Overflow triggered the interrupt: I.e. Timer Counter 3 >= Autorreload value
00093     if (( (*reg_pointer_16_sr & 0x01) >0) && ( (*reg_pointer_16_dier & 0x1) >0))
00094     {
00095  //clear interrupt
00096     *reg_pointer_16_sr = ~((uint16_t)0x01);
00097  //perform action
00098     setGPIOB0();
00099     } 
00100 }
00101 
00102 void enableEXTI6OnPortC(void)
00103 {
00104     uint32_t * reg;
00105  /*Init GPIO 6 C as input*/
00106     initGpioC6AsInput();
00107  /*As a test, Init GPIO B0 as output for debugging*/
00108     InitPortBPin0asOutput();
00109  /* Enable SYSCFG clock */
00110     RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
00111  /*map EXTI6 to port C bit 6*/
00112     reg = (uint32_t *)SYSCFG_EXTERNAL_INTERRUPT_REGISTER_2;
00113  //clear EXTI6
00114     *reg = *reg & ~SYSCFG_EXTERNAL_INTERRUPT_6_BITS;
00115  //set EXTI6 to Port C
00116     *reg = *reg | SYSCFG_EXTERNAL_INTERRUPT_6_PORTC; 
00117  /*un-mask EXTI6*/
00118     reg = (uint32_t *)EXTERNAL_INTERRUPT_CONTROLLER_MASK_REGISTER;
00119     *reg = *reg | EXTERNAL_INTERRUPT_CONTROLLER_MASK_REGISTER_EXTI6;
00120  /*trigger on rising edge*/
00121     reg = (uint32_t *)EXTERNAL_INTERRUPT_CONTROLLER_RTSR;
00122     *reg = *reg | EXTERNAL_INTERRUPT_CONTROLLER_RTSR_EXTI6;
00123  /* set the NVIC to respond to EXTI9_5*/
00124     reg = (uint32_t *)NVIC_INTERRUPT_SET_ENABLE_REGISTER_0_31;
00125     *reg = EXTI9_5_INTERRUPT_BIT; 
00126 }
00127 
00128 void EXTI9_5_IRQHandler(void)
00129 {
00130     uint32_t * reg;
00131     reg = (uint32_t *)EXTERNAL_INTERRUPT_CONTROLLER_PENDING_REGISTER;
00132  //check which interrupt fired:
00133     if ((*reg & EXTERNAL_INTERRUPT_CONTROLLER_PENDING_EXTI6)>0)
00134  {
00135  //clear the interrupt:
00136     *reg = EXTERNAL_INTERRUPT_CONTROLLER_PENDING_EXTI6;
00137  //toggle the LED
00138     toggleGPIOB0();
00139  }
00140 }
00141