Rajath Ravi
/
ADC_DMA_POST_LEC12
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stm32f4xx_mort2.h
00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx.h 00004 * @author MCD Application Team 00005 * @version V1.8.0 00006 * @date 09-November-2016 00007 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File. 00008 * This file contains all the peripheral register's definitions, bits 00009 * definitions and memory mapping for STM32F4xx devices. 00010 * 00011 * The file is the unique include file that the application programmer 00012 * is using in the C source code, usually in main.c. This file contains: 00013 * - Configuration section that allows to select: 00014 * - The device used in the target application 00015 * - To use or not the peripherals drivers in application code(i.e. 00016 * code will be based on direct access to peripherals registers 00017 * rather than drivers API), this option is controlled by 00018 * "#define USE_STDPERIPH_DRIVER" 00019 * - To change few application-specific parameters such as the HSE 00020 * crystal frequency 00021 * - Data structures and the address mapping for all peripherals 00022 * - Peripherals registers declarations and bits definition 00023 * - Macros to access peripherals registers hardware 00024 * 00025 ****************************************************************************** 00026 * @attention 00027 * 00028 * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2> 00029 * 00030 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 00031 * You may not use this file except in compliance with the License. 00032 * You may obtain a copy of the License at: 00033 * 00034 * http://www.st.com/software_license_agreement_liberty_v2 00035 * 00036 * Unless required by applicable law or agreed to in writing, software 00037 * distributed under the License is distributed on an "AS IS" BASIS, 00038 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00039 * See the License for the specific language governing permissions and 00040 * limitations under the License. 00041 * 00042 ****************************************************************************** 00043 */ 00044 00045 /** @addtogroup CMSIS 00046 * @{ 00047 */ 00048 00049 /** @addtogroup stm32f4xx 00050 * @{ 00051 */ 00052 00053 #ifndef __STM32F4xx_H_MORT2_ 00054 #define __STM32F4xx_H_MORT2_ 00055 00056 #ifdef __cplusplus 00057 extern "C" { 00058 #endif /* __cplusplus */ 00059 00060 /** @addtogroup Library_configuration_section 00061 * @{ 00062 */ 00063 00064 /* Uncomment the line below according to the target STM32 device used in your 00065 application 00066 */ 00067 00068 #if !defined(STM32F40_41xxx) && !defined(STM32F427_437xx) && !defined(STM32F429_439xx) && !defined(STM32F401xx) && !defined(STM32F410xx) && \ 00069 !defined(STM32F411xE) && !defined(STM32F412xG) && !defined(STM32F413_423xx) && !defined(STM32F446xx_MORT) && !defined(STM32F469_479xx) 00070 /* #define STM32F40_41xxx */ /*!< STM32F405RG, STM32F405VG, STM32F405ZG, STM32F415RG, STM32F415VG, STM32F415ZG, 00071 STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG, STM32F407IE, 00072 STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */ 00073 00074 /* #define STM32F427_437xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG, STM32F427II, 00075 STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG, STM32F437II Devices */ 00076 00077 /* #define STM32F429_439xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, 00078 STM32F429NG, STM32F439NI, STM32F429IG, STM32F429II, STM32F439VG, STM32F439VI, 00079 STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, STM32F439NI, 00080 STM32F439IG and STM32F439II Devices */ 00081 00082 /* #define STM32F401xx */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB, STM32F401VC, 00083 STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CExx, STM32F401RE and STM32F401VE Devices */ 00084 00085 /* #define STM32F410xx */ /*!< STM32F410Tx, STM32F410Cx and STM32F410Rx */ 00086 00087 /* #define STM32F411xE */ /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */ 00088 00089 /* #define STM32F412xG */ /*!< STM32F412CEU, STM32F412CGU, STM32F412ZET, STM32F412ZGT, STM32F412ZEJ, STM32F412ZGJ, 00090 STM32F412VET, STM32F412VGT, STM32F412VEH, STM32F412VGH, STM32F412RET, STM32F412RGT, 00091 STM32F412REY and STM32F412RGY Devices */ 00092 00093 /* #define STM32F413_423xx */ /*!< STM32F413CGU, STM32F413CHU, STM32F413MGY, STM32F413MHY, STM32F413RGT, STM32F413VGT, 00094 STM32F413ZGT, STM32F413RHT, STM32F413VHT, STM32F413ZHT, STM32F413VGH, STM32F413ZGJ, 00095 STM32F413VHH, STM32F413ZHJ, STM32F423CHU, STM32F423RHT, STM32F423VHT, STM32F423ZHT, 00096 STM32F423VHH and STM32F423ZHJ devices */ 00097 00098 #define STM32F446xx_MORT /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC 00099 and STM32F446ZE Devices */ 00100 00101 /* #define STM32F469_479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG, 00102 STM32F479NG, STM32F479AE, STM32F479IE, STM32F479BE, STM32F479NE Devices */ 00103 00104 #endif /* STM32F40_41xxx && STM32F427_437xx && STM32F429_439xx && STM32F401xx && STM32F410xx && STM32F411xE && STM32F412xG && STM32F413_423xx && STM32F446xx_MORT && STM32F469_479xx */ 00105 00106 /* Old STM32F40XX definition, maintained for legacy purpose */ 00107 #ifdef STM32F40XX 00108 #define STM32F40_41xxx 00109 #endif /* STM32F40XX */ 00110 00111 /* Old STM32F427X definition, maintained for legacy purpose */ 00112 #ifdef STM32F427X 00113 #define STM32F427_437xx 00114 #endif /* STM32F427X */ 00115 00116 /* Tip: To avoid modifying this file each time you need to switch between these 00117 devices, you can define the device in your toolchain compiler preprocessor. 00118 */ 00119 00120 #if !defined(STM32F40_41xxx) && !defined(STM32F427_437xx) && !defined(STM32F429_439xx) && !defined(STM32F401xx) && !defined(STM32F410xx) && \ 00121 !defined(STM32F411xE) && !defined(STM32F412xG) && !defined(STM32F413_423xx) && !defined(STM32F446xx_MORT) && !defined(STM32F469_479xx) 00122 #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" 00123 #endif /* STM32F40_41xxx && STM32F427_437xx && STM32F429_439xx && STM32F401xx && STM32F410xx && STM32F411xE && STM32F412xG && STM32F413_23xx && STM32F446xx_MORT && STM32F469_479xx */ 00124 00125 #if !defined (USE_STDPERIPH_DRIVER) 00126 /** 00127 * @brief Comment the line below if you will not use the peripherals drivers. 00128 In this case, these drivers will not be included and the application code will 00129 be based on direct access to peripherals registers 00130 */ 00131 /*#define USE_STDPERIPH_DRIVER */ 00132 #endif /* USE_STDPERIPH_DRIVER */ 00133 00134 /** 00135 * @brief In the following line adjust the value of External High Speed oscillator (HSE) 00136 used in your application 00137 00138 Tip: To avoid modifying this file each time you need to use different HSE, you 00139 can define the HSE value in your toolchain compiler preprocessor. 00140 */ 00141 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || \ 00142 defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx) 00143 #if !defined (HSE_VALUE) 00144 #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ 00145 #endif /* HSE_VALUE */ 00146 #elif defined (STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) 00147 #if !defined (HSE_VALUE) 00148 #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ 00149 #endif /* HSE_VALUE */ 00150 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */ 00151 /** 00152 * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 00153 Timeout value 00154 */ 00155 #if !defined (HSE_STARTUP_TIMEOUT) 00156 #define HSE_STARTUP_TIMEOUT ((uint16_t)0x05000) /*!< Time out for HSE start up */ 00157 #endif /* HSE_STARTUP_TIMEOUT */ 00158 00159 #if !defined (HSI_VALUE) 00160 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ 00161 #endif /* HSI_VALUE */ 00162 00163 /** 00164 * @brief STM32F4XX Standard Peripherals Library version number V1.8.0 00165 */ 00166 #define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ 00167 #define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x08) /*!< [23:16] sub1 version */ 00168 #define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ 00169 #define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ 00170 #define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\ 00171 |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\ 00172 |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\ 00173 |(__STM32F4XX_STDPERIPH_VERSION_RC)) 00174 00175 /** 00176 * @} 00177 */ 00178 00179 /** @addtogroup Configuration_section_for_CMSIS 00180 * @{ 00181 */ 00182 00183 /** 00184 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 00185 */ 00186 #define __CM4_REV_MORT 0x0001 /*!< Core revision r0p1 */ 00187 #define __MPU_PRESENT_MORT 1 /*!< STM32F4XX provides an MPU */ 00188 #define __NVIC_PRIO_BITS_MORT 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */ 00189 #define __Vendor_SysTickConfig_MORT 0 /*!< Set to 1 if different SysTick Config is used */ 00190 #define __FPU_PRESENT_MORT 1 /*!< FPU present */ 00191 00192 /** 00193 * @brief STM32F4XX Interrupt Number Definition, according to the selected device 00194 * in @ref Library_configuration_section 00195 */ 00196 typedef enum IRQn_MORT 00197 { 00198 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ 00199 NonMaskableInt_IRQn_MORT = -14, /*!< 2 Non Maskable Interrupt */ 00200 MemoryManagement_IRQn_MORT = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ 00201 BusFault_IRQn_MORT = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ 00202 UsageFault_IRQn_MORT = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ 00203 SVCall_IRQn_MORT = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ 00204 DebugMonitor_IRQn_MORT = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ 00205 PendSV_IRQn_MORT = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ 00206 SysTick_IRQn_MORT = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ 00207 /****** STM32 specific Interrupt Numbers **********************************************************************/ 00208 WWDG_IRQn_MORT = 0, /*!< Window WatchDog Interrupt */ 00209 PVD_IRQn_MORT = 1, /*!< PVD through EXTI_MORT Line detection Interrupt */ 00210 TAMP_STAMP_IRQn_MORT = 2, /*!< Tamper and TimeStamp interrupts through the EXTI_MORT line */ 00211 RTC_WKUP_IRQn_MORT = 3, /*!< RTC_MORT Wakeup interrupt through the EXTI_MORT line */ 00212 FLASH_IRQn_MORT = 4, /*!< FLASH_MORT global Interrupt */ 00213 RCC_IRQn_MORT = 5, /*!< RCC_MORT global Interrupt */ 00214 EXTI0_IRQn_MORT = 6, /*!< EXTI_MORT Line0 Interrupt */ 00215 EXTI1_IRQn_MORT = 7, /*!< EXTI_MORT Line1 Interrupt */ 00216 EXTI2_IRQn_MORT = 8, /*!< EXTI_MORT Line2 Interrupt */ 00217 EXTI3_IRQn_MORT = 9, /*!< EXTI_MORT Line3 Interrupt */ 00218 EXTI4_IRQn_MORT = 10, /*!< EXTI_MORT Line4 Interrupt */ 00219 DMA1_Stream0_IRQn_MORT = 11, /*!< DMA1_MORT Stream 0 global Interrupt */ 00220 DMA1_Stream1_IRQn_MORT = 12, /*!< DMA1_MORT Stream 1 global Interrupt */ 00221 DMA1_Stream2_IRQn_MORT = 13, /*!< DMA1_MORT Stream 2 global Interrupt */ 00222 DMA1_Stream3_IRQn_MORT = 14, /*!< DMA1_MORT Stream 3 global Interrupt */ 00223 DMA1_Stream4_IRQn_MORT = 15, /*!< DMA1_MORT Stream 4 global Interrupt */ 00224 DMA1_Stream5_IRQn_MORT = 16, /*!< DMA1_MORT Stream 5 global Interrupt */ 00225 DMA1_Stream6_IRQn_MORT = 17, /*!< DMA1_MORT Stream 6 global Interrupt */ 00226 ADC_IRQn_MORT = 18, /*!< ADC1_MORT, ADC2_MORT and ADC3_MORT global Interrupts */ 00227 00228 #if defined(STM32F40_41xxx) 00229 */ 00230 #endif /* STM32F40_41xxx */ 00231 00232 #if defined(STM32F427_437xx) 00233 */ 00234 #endif /* STM32F427_437xx */ 00235 00236 #if defined(STM32F429_439xx) 00237 */ 00238 #endif /* STM32F429_439xx */ 00239 00240 #if defined(STM32F410xx) 00241 */ 00242 #endif /* STM32F410xx */ 00243 00244 #if defined(STM32F401xx) || defined(STM32F411xE) 00245 */ 00246 #if defined(STM32F401xx) 00247 */ 00248 #endif /* STM32F411xE */ 00249 #if defined(STM32F411xE) 00250 */ 00251 #endif /* STM32F411xE */ 00252 #endif /* STM32F401xx || STM32F411xE */ 00253 00254 #if defined(STM32F469_479xx) 00255 */ 00256 #endif /* STM32F469_479xx */ 00257 00258 #if defined(STM32F446xx_MORT) 00259 CAN1_TX_IRQn_MORT = 19, /*!< CAN1_MORT TX Interrupt */ 00260 CAN1_RX0_IRQn_MORT = 20, /*!< CAN1_MORT RX0 Interrupt */ 00261 CAN1_RX1_IRQn_MORT = 21, /*!< CAN1_MORT RX1 Interrupt */ 00262 CAN1_SCE_IRQn_MORT = 22, /*!< CAN1_MORT SCE Interrupt */ 00263 EXTI9_5_IRQn_MORT = 23, /*!< External Line[9:5] Interrupts */ 00264 TIM1_BRK_TIM9_IRQn_MORT = 24, /*!< TIM1_MORT Break interrupt and TIM9_MORT global interrupt */ 00265 TIM1_UP_TIM10_IRQn_MORT = 25, /*!< TIM1_MORT Update Interrupt and TIM10_MORT global interrupt */ 00266 TIM1_TRG_COM_TIM11_IRQn_MORT = 26, /*!< TIM1_MORT Trigger and Commutation Interrupt and TIM11_MORT global interrupt */ 00267 TIM1_CC_IRQn_MORT = 27, /*!< TIM1_MORT Capture Compare Interrupt */ 00268 TIM2_IRQn_MORT = 28, /*!< TIM2_MORT global Interrupt */ 00269 TIM3_IRQn_MORT = 29, /*!< TIM3_MORT global Interrupt */ 00270 TIM4_IRQn_MORT = 30, /*!< TIM4_MORT global Interrupt */ 00271 I2C1_EV_IRQn_MORT = 31, /*!< I2C1_MORT Event Interrupt */ 00272 I2C1_ER_IRQn_MORT = 32, /*!< I2C1_MORT Error Interrupt */ 00273 I2C2_EV_IRQn_MORT = 33, /*!< I2C2_MORT Event Interrupt */ 00274 I2C2_ER_IRQn_MORT = 34, /*!< I2C2_MORT Error Interrupt */ 00275 SPI1_IRQn_MORT = 35, /*!< SPI1_MORT global Interrupt */ 00276 SPI2_IRQn_MORT = 36, /*!< SPI2_MORT global Interrupt */ 00277 USART1_IRQn_MORT = 37, /*!< USART1_MORT global Interrupt */ 00278 USART2_IRQn_MORT = 38, /*!< USART2_MORT global Interrupt */ 00279 USART3_IRQn_MORT = 39, /*!< USART3_MORT global Interrupt */ 00280 EXTI15_10_IRQn_MORT = 40, /*!< External Line[15:10] Interrupts */ 00281 RTC_Alarm_IRQn_MORT = 41, /*!< RTC_MORT Alarm (A and B) through EXTI_MORT Line Interrupt */ 00282 OTG_FS_WKUP_IRQn_MORT = 42, /*!< USB OTG FS Wakeup through EXTI_MORT line interrupt */ 00283 TIM8_BRK_IRQn_MORT = 43, /*!< TIM8_MORT Break Interrupt */ 00284 TIM8_BRK_TIM12_IRQn_MORT = 43, /*!< TIM8_MORT Break Interrupt and TIM12_MORT global interrupt */ 00285 TIM8_UP_TIM13_IRQn_MORT = 44, /*!< TIM8_MORT Update Interrupt and TIM13_MORT global interrupt */ 00286 TIM8_TRG_COM_TIM14_IRQn_MORT = 45, /*!< TIM8_MORT Trigger and Commutation Interrupt and TIM14_MORT global interrupt */ 00287 DMA1_Stream7_IRQn_MORT = 47, /*!< DMA1_MORT Stream7 Interrupt */ 00288 FMC_IRQn_MORT = 48, /*!< FMC global Interrupt */ 00289 SDIO_IRQn_MORT = 49, /*!< SDIO_MORT global Interrupt */ 00290 TIM5_IRQn_MORT = 50, /*!< TIM5_MORT global Interrupt */ 00291 SPI3_IRQn_MORT = 51, /*!< SPI3_MORT global Interrupt */ 00292 UART4_IRQn_MORT = 52, /*!< UART4_MORT global Interrupt */ 00293 UART5_IRQn_MORT = 53, /*!< UART5_MORT global Interrupt */ 00294 TIM6_DAC_IRQn_MORT = 54, /*!< TIM6_MORT global and DAC1&2 underrun error interrupts */ 00295 TIM7_IRQn_MORT = 55, /*!< TIM7_MORT global interrupt */ 00296 DMA2_Stream0_IRQn_MORT = 56, /*!< DMA2_MORT Stream 0 global Interrupt */ 00297 DMA2_Stream1_IRQn_MORT = 57, /*!< DMA2_MORT Stream 1 global Interrupt */ 00298 DMA2_Stream2_IRQn_MORT = 58, /*!< DMA2_MORT Stream 2 global Interrupt */ 00299 DMA2_Stream3_IRQn_MORT = 59, /*!< DMA2_MORT Stream 3 global Interrupt */ 00300 DMA2_Stream4_IRQn_MORT = 60, /*!< DMA2_MORT Stream 4 global Interrupt */ 00301 CAN2_TX_IRQn_MORT = 63, /*!< CAN2_MORT TX Interrupt */ 00302 CAN2_RX0_IRQn_MORT = 64, /*!< CAN2_MORT RX0 Interrupt */ 00303 CAN2_RX1_IRQn_MORT = 65, /*!< CAN2_MORT RX1 Interrupt */ 00304 CAN2_SCE_IRQn_MORT = 66, /*!< CAN2_MORT SCE Interrupt */ 00305 OTG_FS_IRQn_MORT = 67, /*!< USB OTG FS global Interrupt */ 00306 DMA2_Stream5_IRQn_MORT = 68, /*!< DMA2_MORT Stream 5 global interrupt */ 00307 DMA2_Stream6_IRQn_MORT = 69, /*!< DMA2_MORT Stream 6 global interrupt */ 00308 DMA2_Stream7_IRQn_MORT = 70, /*!< DMA2_MORT Stream 7 global interrupt */ 00309 USART6_IRQn_MORT = 71, /*!< USART6_MORT global interrupt */ 00310 I2C3_EV_IRQn_MORT = 72, /*!< I2C3_MORT event interrupt */ 00311 I2C3_ER_IRQn_MORT = 73, /*!< I2C3_MORT error interrupt */ 00312 OTG_HS_EP1_OUT_IRQn_MORT = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ 00313 OTG_HS_EP1_IN_IRQn_MORT = 75, /*!< USB OTG HS End Point 1 In global interrupt */ 00314 OTG_HS_WKUP_IRQn_MORT = 76, /*!< USB OTG HS Wakeup through EXTI_MORT interrupt */ 00315 OTG_HS_IRQn_MORT = 77, /*!< USB OTG HS global interrupt */ 00316 DCMI_IRQn_MORT = 78, /*!< DCMI_MORT global interrupt */ 00317 FPU_IRQn_MORT = 81, /*!< FPU global interrupt */ 00318 SPI4_IRQn_MORT = 84, /*!< SPI4_MORT global Interrupt */ 00319 SAI1_IRQn_MORT = 87, /*!< SAI1_MORT global Interrupt */ 00320 SAI2_IRQn_MORT = 91, /*!< SAI2_MORT global Interrupt */ 00321 QUADSPI_IRQn_MORT = 92, /*!< QUADSPI_MORT global Interrupt */ 00322 CEC_IRQn_MORT = 93, /*!< QUADSPI_MORT global Interrupt */ 00323 SPDIF_RX_IRQn_MORT = 94, /*!< QUADSPI_MORT global Interrupt */ 00324 FMPI2C1_EV_IRQn_MORT = 95, /*!< FMPI2C Event Interrupt */ 00325 FMPI2C1_ER_IRQn_MORT = 96 /*!< FMPCI2C Error Interrupt */ 00326 #endif /* STM32F446xx_MORT */ 00327 00328 #if defined(STM32F412xG) 00329 */ 00330 #endif /* STM32F412xG */ 00331 00332 #if defined(STM32F413_423xx) 00333 */ 00334 */ 00335 #endif /* STM32F413_423xx */ 00336 } IRQn_Type_MORT; 00337 00338 /** 00339 * @} 00340 */ 00341 #include "stm32f4xx.h" 00342 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ 00343 #include "system_stm32f4xx.h" 00344 #include <stdint.h> 00345 00346 /** @addtogroup Exported_types 00347 * @{ 00348 */ 00349 /*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ 00350 //typedef int32_t_mort s32; 00351 //typedef int16_t_mort s16; 00352 //typedef int8_t_mort s8; 00353 00354 //typedef const int32_t_mort sc32; /*!< Read Only */ 00355 //typedef const int16_t_mort sc16; /*!< Read Only */ 00356 //typedef const int8_t_mort sc8; /*!< Read Only */ 00357 00358 //typedef __IO int32_t_mort vs32; 00359 //typedef __IO int16_t_mort vs16; 00360 //typedef __IO int8_t_mort vs8; 00361 00362 //typedef __I int32_t_mort vsc32; /*!< Read Only */ 00363 //typedef __I int16_t_mort vsc16; /*!< Read Only */ 00364 //typedef __I int8_t_mort vsc8; /*!< Read Only */ 00365 00366 //typedef uint32_t_mort u32; 00367 //typedef uint16_t_mort u16; 00368 //typedef uint8_t_mort u8; 00369 00370 //typedef const uint32_t_mort uc32; /*!< Read Only */ 00371 //typedef const uint16_t_mort uc16; /*!< Read Only */ 00372 //typedef const uint8_t_mort uc8; /*!< Read Only */ 00373 00374 //typedef __IO uint32_t_mort vu32; 00375 //typedef __IO uint16_t_mort vu16; 00376 //typedef __IO uint8_t_mort vu8; 00377 00378 //typedef __I uint32_t_mort vuc32; /*!< Read Only */ 00379 //typedef __I uint16_t_mort vuc16; /*!< Read Only */ 00380 //typedef __I uint8_t_mort vuc8; /*!< Read Only */ 00381 00382 typedef enum {RESET_MORT = 0, SET_MORT = !RESET_MORT} FlagStatus_MORT, ITStatus_MORT; 00383 00384 typedef enum {DISABLE_MORT = 0, ENABLE_MORT = !DISABLE_MORT} FunctionalState_MORT; 00385 #define IS_FUNCTIONAL_STATE_MORT(STATE) (((STATE) == DISABLE_MORT) || ((STATE) == ENABLE_MORT)) 00386 00387 typedef enum {ERROR_MORT = 0, SUCCESS_MORT = !ERROR} ErrorStatus_MORT; 00388 00389 /** 00390 * @} 00391 */ 00392 00393 /** @addtogroup Peripheral_registers_structures 00394 * @{ 00395 */ 00396 00397 /** 00398 * @brief Analog to Digital Converter 00399 */ 00400 00401 typedef struct 00402 { 00403 __IO uint32_t SR; /*!< ADC_MORT status register, Address offset: 0x00 */ 00404 __IO uint32_t CR1; /*!< ADC_MORT control register 1, Address offset: 0x04 */ 00405 __IO uint32_t CR2; /*!< ADC_MORT control register 2, Address offset: 0x08 */ 00406 __IO uint32_t SMPR1; /*!< ADC_MORT sample time register 1, Address offset: 0x0C */ 00407 __IO uint32_t SMPR2; /*!< ADC_MORT sample time register 2, Address offset: 0x10 */ 00408 __IO uint32_t JOFR1; /*!< ADC_MORT injected channel data offset register 1, Address offset: 0x14 */ 00409 __IO uint32_t JOFR2; /*!< ADC_MORT injected channel data offset register 2, Address offset: 0x18 */ 00410 __IO uint32_t JOFR3; /*!< ADC_MORT injected channel data offset register 3, Address offset: 0x1C */ 00411 __IO uint32_t JOFR4; /*!< ADC_MORT injected channel data offset register 4, Address offset: 0x20 */ 00412 __IO uint32_t HTR; /*!< ADC_MORT watchdog higher threshold register, Address offset: 0x24 */ 00413 __IO uint32_t LTR; /*!< ADC_MORT watchdog lower threshold register, Address offset: 0x28 */ 00414 __IO uint32_t SQR1; /*!< ADC_MORT regular sequence register 1, Address offset: 0x2C */ 00415 __IO uint32_t SQR2; /*!< ADC_MORT regular sequence register 2, Address offset: 0x30 */ 00416 __IO uint32_t SQR3; /*!< ADC_MORT regular sequence register 3, Address offset: 0x34 */ 00417 __IO uint32_t JSQR; /*!< ADC_MORT injected sequence register, Address offset: 0x38 */ 00418 __IO uint32_t JDR1; /*!< ADC_MORT injected data register 1, Address offset: 0x3C */ 00419 __IO uint32_t JDR2; /*!< ADC_MORT injected data register 2, Address offset: 0x40 */ 00420 __IO uint32_t JDR3; /*!< ADC_MORT injected data register 3, Address offset: 0x44 */ 00421 __IO uint32_t JDR4; /*!< ADC_MORT injected data register 4, Address offset: 0x48 */ 00422 __IO uint32_t DR; /*!< ADC_MORT regular data register, Address offset: 0x4C */ 00423 } ADC_TypeDef_mort; 00424 00425 typedef struct 00426 { 00427 __IO uint32_t CSR; /*!< ADC_MORT Common status register, Address offset: ADC1_MORT base address + 0x300 */ 00428 __IO uint32_t CCR; /*!< ADC_MORT common control register, Address offset: ADC1_MORT base address + 0x304 */ 00429 __IO uint32_t CDR; /*!< ADC_MORT common regular data register for dual 00430 AND triple modes, Address offset: ADC1_MORT base address + 0x308 */ 00431 } ADC_Common_TypeDef_mort; 00432 00433 00434 /** 00435 * @brief Controller Area Network TxMailBox 00436 */ 00437 00438 typedef struct 00439 { 00440 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ 00441 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ 00442 __IO uint32_t TDLR; /*!< CAN mailbox data low register */ 00443 __IO uint32_t TDHR; /*!< CAN mailbox data high register */ 00444 } CAN_TxMailBox_TypeDef_mort; 00445 00446 /** 00447 * @brief Controller Area Network FIFOMailBox 00448 */ 00449 00450 typedef struct 00451 { 00452 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ 00453 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ 00454 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ 00455 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ 00456 } CAN_FIFOMailBox_TypeDef_mort; 00457 00458 /** 00459 * @brief Controller Area Network FilterRegister 00460 */ 00461 00462 typedef struct 00463 { 00464 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ 00465 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ 00466 } CAN_FilterRegister_TypeDef_mort; 00467 00468 /** 00469 * @brief Controller Area Network 00470 */ 00471 00472 typedef struct 00473 { 00474 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ 00475 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ 00476 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ 00477 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ 00478 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ 00479 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ 00480 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ 00481 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ 00482 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ 00483 CAN_TxMailBox_TypeDef_mort sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ 00484 CAN_FIFOMailBox_TypeDef_mort sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ 00485 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ 00486 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ 00487 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ 00488 uint32_t RESERVED2; /*!< Reserved, 0x208 */ 00489 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ 00490 uint32_t RESERVED3; /*!< Reserved, 0x210 */ 00491 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ 00492 uint32_t RESERVED4; /*!< Reserved, 0x218 */ 00493 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ 00494 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ 00495 CAN_FilterRegister_TypeDef_mort sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ 00496 } CAN_TypeDef_mort; 00497 00498 #if defined(STM32F446xx_MORT) 00499 /** 00500 * @brief Consumer Electronics Control 00501 */ 00502 typedef struct 00503 { 00504 __IO uint32_t CR; /*!< CEC_MORT control register, Address offset:0x00 */ 00505 __IO uint32_t CFGR; /*!< CEC_MORT configuration register, Address offset:0x04 */ 00506 __IO uint32_t TXDR; /*!< CEC_MORT Tx data register , Address offset:0x08 */ 00507 __IO uint32_t RXDR; /*!< CEC_MORT Rx Data Register, Address offset:0x0C */ 00508 __IO uint32_t ISR; /*!< CEC_MORT Interrupt and Status Register, Address offset:0x10 */ 00509 __IO uint32_t IER; /*!< CEC_MORT interrupt enable register, Address offset:0x14 */ 00510 }CEC_TypeDef_mort; 00511 #endif /* STM32F446xx_MORT */ 00512 00513 /** 00514 * @brief CRC_MORT calculation unit 00515 */ 00516 00517 typedef struct 00518 { 00519 __IO uint32_t DR; /*!< CRC_MORT Data register, Address offset: 0x00 */ 00520 __IO uint8_t IDR; /*!< CRC_MORT Independent data register, Address offset: 0x04 */ 00521 uint8_t RESERVED0; /*!< Reserved, 0x05 */ 00522 uint16_t RESERVED1; /*!< Reserved, 0x06 */ 00523 __IO uint32_t CR; /*!< CRC_MORT Control register, Address offset: 0x08 */ 00524 } CRC_TypeDef_mort; 00525 00526 /** 00527 * @brief Digital to Analog Converter 00528 */ 00529 00530 typedef struct 00531 { 00532 __IO uint32_t CR; /*!< DAC_MORT control register, Address offset: 0x00 */ 00533 __IO uint32_t SWTRIGR; /*!< DAC_MORT software trigger register, Address offset: 0x04 */ 00534 __IO uint32_t DHR12R1; /*!< DAC_MORT channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ 00535 __IO uint32_t DHR12L1; /*!< DAC_MORT channel1 12-bit left aligned data holding register, Address offset: 0x0C */ 00536 __IO uint32_t DHR8R1; /*!< DAC_MORT channel1 8-bit right aligned data holding register, Address offset: 0x10 */ 00537 __IO uint32_t DHR12R2; /*!< DAC_MORT channel2 12-bit right aligned data holding register, Address offset: 0x14 */ 00538 __IO uint32_t DHR12L2; /*!< DAC_MORT channel2 12-bit left aligned data holding register, Address offset: 0x18 */ 00539 __IO uint32_t DHR8R2; /*!< DAC_MORT channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ 00540 __IO uint32_t DHR12RD; /*!< Dual DAC_MORT 12-bit right-aligned data holding register, Address offset: 0x20 */ 00541 __IO uint32_t DHR12LD; /*!< DUAL DAC_MORT 12-bit left aligned data holding register, Address offset: 0x24 */ 00542 __IO uint32_t DHR8RD; /*!< DUAL DAC_MORT 8-bit right aligned data holding register, Address offset: 0x28 */ 00543 __IO uint32_t DOR1; /*!< DAC_MORT channel1 data output register, Address offset: 0x2C */ 00544 __IO uint32_t DOR2; /*!< DAC_MORT channel2 data output register, Address offset: 0x30 */ 00545 __IO uint32_t SR; /*!< DAC_MORT status register, Address offset: 0x34 */ 00546 } DAC_TypeDef_mort; 00547 00548 #if defined(STM32F412xG) || defined(STM32F413_423xx) 00549 /** 00550 * @brief DFSDM module registers 00551 */ 00552 typedef struct 00553 { 00554 __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ 00555 __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ 00556 __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ 00557 __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ 00558 __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ 00559 __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ 00560 __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ 00561 __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ 00562 __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ 00563 __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ 00564 __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ 00565 __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ 00566 __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ 00567 __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ 00568 __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ 00569 } DFSDM_Filter_TypeDef_mort; 00570 00571 /** 00572 * @brief DFSDM channel configuration registers 00573 */ 00574 typedef struct 00575 { 00576 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ 00577 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ 00578 __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and 00579 short circuit detector register, Address offset: 0x08 */ 00580 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ 00581 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ 00582 } DFSDM_Channel_TypeDef_mort; 00583 00584 /* Legacy Defines */ 00585 #define DFSDM_TypeDef DFSDM_Filter_TypeDef_mort 00586 #endif /* STM32F412xG || STM32F413_423xx */ 00587 /** 00588 * @brief Debug MCU 00589 */ 00590 00591 typedef struct 00592 { 00593 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ 00594 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ 00595 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ 00596 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ 00597 }DBGMCU_TypeDef_mort; 00598 00599 /** 00600 * @brief DCMI_MORT 00601 */ 00602 00603 typedef struct 00604 { 00605 __IO uint32_t CR; /*!< DCMI_MORT control register 1, Address offset: 0x00 */ 00606 __IO uint32_t SR; /*!< DCMI_MORT status register, Address offset: 0x04 */ 00607 __IO uint32_t RISR; /*!< DCMI_MORT raw interrupt status register, Address offset: 0x08 */ 00608 __IO uint32_t IER; /*!< DCMI_MORT interrupt enable register, Address offset: 0x0C */ 00609 __IO uint32_t MISR; /*!< DCMI_MORT masked interrupt status register, Address offset: 0x10 */ 00610 __IO uint32_t ICR; /*!< DCMI_MORT interrupt clear register, Address offset: 0x14 */ 00611 __IO uint32_t ESCR; /*!< DCMI_MORT embedded synchronization code register, Address offset: 0x18 */ 00612 __IO uint32_t ESUR; /*!< DCMI_MORT embedded synchronization unmask register, Address offset: 0x1C */ 00613 __IO uint32_t CWSTRTR; /*!< DCMI_MORT crop window start, Address offset: 0x20 */ 00614 __IO uint32_t CWSIZER; /*!< DCMI_MORT crop window size, Address offset: 0x24 */ 00615 __IO uint32_t DR; /*!< DCMI_MORT data register, Address offset: 0x28 */ 00616 } DCMI_TypeDef_mort; 00617 00618 /** 00619 * @brief DMA Controller 00620 */ 00621 00622 typedef struct 00623 { 00624 __IO uint32_t CR; /*!< DMA stream x configuration register */ 00625 __IO uint32_t NDTR; /*!< DMA stream x number of data register */ 00626 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ 00627 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ 00628 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ 00629 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ 00630 } DMA_Stream_TypeDef_mort; 00631 00632 typedef struct 00633 { 00634 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ 00635 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ 00636 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ 00637 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ 00638 } DMA_TypeDef_mort; 00639 00640 /** 00641 * @brief DMA2D_MORT Controller 00642 */ 00643 00644 typedef struct 00645 { 00646 __IO uint32_t CR; /*!< DMA2D_MORT Control Register, Address offset: 0x00 */ 00647 __IO uint32_t ISR; /*!< DMA2D_MORT Interrupt Status Register, Address offset: 0x04 */ 00648 __IO uint32_t IFCR; /*!< DMA2D_MORT Interrupt Flag Clear Register, Address offset: 0x08 */ 00649 __IO uint32_t FGMAR; /*!< DMA2D_MORT Foreground Memory Address Register, Address offset: 0x0C */ 00650 __IO uint32_t FGOR; /*!< DMA2D_MORT Foreground Offset Register, Address offset: 0x10 */ 00651 __IO uint32_t BGMAR; /*!< DMA2D_MORT Background Memory Address Register, Address offset: 0x14 */ 00652 __IO uint32_t BGOR; /*!< DMA2D_MORT Background Offset Register, Address offset: 0x18 */ 00653 __IO uint32_t FGPFCCR; /*!< DMA2D_MORT Foreground PFC Control Register, Address offset: 0x1C */ 00654 __IO uint32_t FGCOLR; /*!< DMA2D_MORT Foreground Color Register, Address offset: 0x20 */ 00655 __IO uint32_t BGPFCCR; /*!< DMA2D_MORT Background PFC Control Register, Address offset: 0x24 */ 00656 __IO uint32_t BGCOLR; /*!< DMA2D_MORT Background Color Register, Address offset: 0x28 */ 00657 __IO uint32_t FGCMAR; /*!< DMA2D_MORT Foreground CLUT Memory Address Register, Address offset: 0x2C */ 00658 __IO uint32_t BGCMAR; /*!< DMA2D_MORT Background CLUT Memory Address Register, Address offset: 0x30 */ 00659 __IO uint32_t OPFCCR; /*!< DMA2D_MORT Output PFC Control Register, Address offset: 0x34 */ 00660 __IO uint32_t OCOLR; /*!< DMA2D_MORT Output Color Register, Address offset: 0x38 */ 00661 __IO uint32_t OMAR; /*!< DMA2D_MORT Output Memory Address Register, Address offset: 0x3C */ 00662 __IO uint32_t OOR; /*!< DMA2D_MORT Output Offset Register, Address offset: 0x40 */ 00663 __IO uint32_t NLR; /*!< DMA2D_MORT Number of Line Register, Address offset: 0x44 */ 00664 __IO uint32_t LWR; /*!< DMA2D_MORT Line Watermark Register, Address offset: 0x48 */ 00665 __IO uint32_t AMTCR; /*!< DMA2D_MORT AHB Master Timer Configuration Register, Address offset: 0x4C */ 00666 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ 00667 __IO uint32_t FGCLUT[256]; /*!< DMA2D_MORT Foreground CLUT, Address offset:400-7FF */ 00668 __IO uint32_t BGCLUT[256]; /*!< DMA2D_MORT Background CLUT, Address offset:800-BFF */ 00669 } DMA2D_TypeDef_mort; 00670 00671 #if defined(STM32F469_479xx) 00672 /** 00673 * @brief DSI_MORT Controller 00674 */ 00675 00676 typedef struct 00677 { 00678 __IO uint32_t VR; /*!< DSI_MORT Host Version Register, Address offset: 0x00 */ 00679 __IO uint32_t CR; /*!< DSI_MORT Host Control Register, Address offset: 0x04 */ 00680 __IO uint32_t CCR; /*!< DSI_MORT HOST Clock Control Register, Address offset: 0x08 */ 00681 __IO uint32_t LVCIDR; /*!< DSI_MORT Host LTDC_MORT VCID Register, Address offset: 0x0C */ 00682 __IO uint32_t LCOLCR; /*!< DSI_MORT Host LTDC_MORT Color Coding Register, Address offset: 0x10 */ 00683 __IO uint32_t LPCR; /*!< DSI_MORT Host LTDC_MORT Polarity Configuration Register, Address offset: 0x14 */ 00684 __IO uint32_t LPMCR; /*!< DSI_MORT Host Low-Power Mode Configuration Register, Address offset: 0x18 */ 00685 uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */ 00686 __IO uint32_t PCR; /*!< DSI_MORT Host Protocol Configuration Register, Address offset: 0x2C */ 00687 __IO uint32_t GVCIDR; /*!< DSI_MORT Host Generic VCID Register, Address offset: 0x30 */ 00688 __IO uint32_t MCR; /*!< DSI_MORT Host Mode Configuration Register, Address offset: 0x34 */ 00689 __IO uint32_t VMCR; /*!< DSI_MORT Host Video Mode Configuration Register, Address offset: 0x38 */ 00690 __IO uint32_t VPCR; /*!< DSI_MORT Host Video Packet Configuration Register, Address offset: 0x3C */ 00691 __IO uint32_t VCCR; /*!< DSI_MORT Host Video Chunks Configuration Register, Address offset: 0x40 */ 00692 __IO uint32_t VNPCR; /*!< DSI_MORT Host Video Null Packet Configuration Register, Address offset: 0x44 */ 00693 __IO uint32_t VHSACR; /*!< DSI_MORT Host Video HSA Configuration Register, Address offset: 0x48 */ 00694 __IO uint32_t VHBPCR; /*!< DSI_MORT Host Video HBP Configuration Register, Address offset: 0x4C */ 00695 __IO uint32_t VLCR; /*!< DSI_MORT Host Video Line Configuration Register, Address offset: 0x50 */ 00696 __IO uint32_t VVSACR; /*!< DSI_MORT Host Video VSA Configuration Register, Address offset: 0x54 */ 00697 __IO uint32_t VVBPCR; /*!< DSI_MORT Host Video VBP Configuration Register, Address offset: 0x58 */ 00698 __IO uint32_t VVFPCR; /*!< DSI_MORT Host Video VFP Configuration Register, Address offset: 0x5C */ 00699 __IO uint32_t VVACR; /*!< DSI_MORT Host Video VA Configuration Register, Address offset: 0x60 */ 00700 __IO uint32_t LCCR; /*!< DSI_MORT Host LTDC_MORT Command Configuration Register, Address offset: 0x64 */ 00701 __IO uint32_t CMCR; /*!< DSI_MORT Host Command Mode Configuration Register, Address offset: 0x68 */ 00702 __IO uint32_t GHCR; /*!< DSI_MORT Host Generic Header Configuration Register, Address offset: 0x6C */ 00703 __IO uint32_t GPDR; /*!< DSI_MORT Host Generic Payload Data Register, Address offset: 0x70 */ 00704 __IO uint32_t GPSR; /*!< DSI_MORT Host Generic Packet Status Register, Address offset: 0x74 */ 00705 __IO uint32_t TCCR[6]; /*!< DSI_MORT Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */ 00706 __IO uint32_t TDCR; /*!< DSI_MORT Host 3D Configuration Register, Address offset: 0x90 */ 00707 __IO uint32_t CLCR; /*!< DSI_MORT Host Clock Lane Configuration Register, Address offset: 0x94 */ 00708 __IO uint32_t CLTCR; /*!< DSI_MORT Host Clock Lane Timer Configuration Register, Address offset: 0x98 */ 00709 __IO uint32_t DLTCR; /*!< DSI_MORT Host Data Lane Timer Configuration Register, Address offset: 0x9C */ 00710 __IO uint32_t PCTLR; /*!< DSI_MORT Host PHY Control Register, Address offset: 0xA0 */ 00711 __IO uint32_t PCONFR; /*!< DSI_MORT Host PHY Configuration Register, Address offset: 0xA4 */ 00712 __IO uint32_t PUCR; /*!< DSI_MORT Host PHY ULPS Control Register, Address offset: 0xA8 */ 00713 __IO uint32_t PTTCR; /*!< DSI_MORT Host PHY TX Triggers Configuration Register, Address offset: 0xAC */ 00714 __IO uint32_t PSR; /*!< DSI_MORT Host PHY Status Register, Address offset: 0xB0 */ 00715 uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */ 00716 __IO uint32_t ISR[2]; /*!< DSI_MORT Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */ 00717 __IO uint32_t IER[2]; /*!< DSI_MORT Host Interrupt Enable Register, Address offset: 0xC4-0xCB */ 00718 uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */ 00719 __IO uint32_t FIR[2]; /*!< DSI_MORT Host Force Interrupt Register, Address offset: 0xD8-0xDF */ 00720 uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */ 00721 __IO uint32_t VSCR; /*!< DSI_MORT Host Video Shadow Control Register, Address offset: 0x100 */ 00722 uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */ 00723 __IO uint32_t LCVCIDR; /*!< DSI_MORT Host LTDC_MORT Current VCID Register, Address offset: 0x10C */ 00724 __IO uint32_t LCCCR; /*!< DSI_MORT Host LTDC_MORT Current Color Coding Register, Address offset: 0x110 */ 00725 uint32_t RESERVED5; /*!< Reserved, 0x114 */ 00726 __IO uint32_t LPMCCR; /*!< DSI_MORT Host Low-power Mode Current Configuration Register, Address offset: 0x118 */ 00727 uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */ 00728 __IO uint32_t VMCCR; /*!< DSI_MORT Host Video Mode Current Configuration Register, Address offset: 0x138 */ 00729 __IO uint32_t VPCCR; /*!< DSI_MORT Host Video Packet Current Configuration Register, Address offset: 0x13C */ 00730 __IO uint32_t VCCCR; /*!< DSI_MORT Host Video Chuncks Current Configuration Register, Address offset: 0x140 */ 00731 __IO uint32_t VNPCCR; /*!< DSI_MORT Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ 00732 __IO uint32_t VHSACCR; /*!< DSI_MORT Host Video HSA Current Configuration Register, Address offset: 0x148 */ 00733 __IO uint32_t VHBPCCR; /*!< DSI_MORT Host Video HBP Current Configuration Register, Address offset: 0x14C */ 00734 __IO uint32_t VLCCR; /*!< DSI_MORT Host Video Line Current Configuration Register, Address offset: 0x150 */ 00735 __IO uint32_t VVSACCR; /*!< DSI_MORT Host Video VSA Current Configuration Register, Address offset: 0x154 */ 00736 __IO uint32_t VVBPCCR; /*!< DSI_MORT Host Video VBP Current Configuration Register, Address offset: 0x158 */ 00737 __IO uint32_t VVFPCCR; /*!< DSI_MORT Host Video VFP Current Configuration Register, Address offset: 0x15C */ 00738 __IO uint32_t VVACCR; /*!< DSI_MORT Host Video VA Current Configuration Register, Address offset: 0x160 */ 00739 uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */ 00740 __IO uint32_t TDCCR; /*!< DSI_MORT Host 3D Current Configuration Register, Address offset: 0x190 */ 00741 uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */ 00742 __IO uint32_t WCFGR; /*!< DSI_MORT Wrapper Configuration Register, Address offset: 0x400 */ 00743 __IO uint32_t WCR; /*!< DSI_MORT Wrapper Control Register, Address offset: 0x404 */ 00744 __IO uint32_t WIER; /*!< DSI_MORT Wrapper Interrupt Enable Register, Address offset: 0x408 */ 00745 __IO uint32_t WISR; /*!< DSI_MORT Wrapper Interrupt and Status Register, Address offset: 0x40C */ 00746 __IO uint32_t WIFCR; /*!< DSI_MORT Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */ 00747 uint32_t RESERVED9; /*!< Reserved, 0x414 */ 00748 __IO uint32_t WPCR[5]; /*!< DSI_MORT Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */ 00749 uint32_t RESERVED10; /*!< Reserved, 0x42C */ 00750 __IO uint32_t WRPCR; /*!< DSI_MORT Wrapper Regulator and PLL Control Register, Address offset: 0x430 */ 00751 } DSI_TypeDef_mort; 00752 #endif /* STM32F469_479xx */ 00753 00754 /** 00755 * @brief Ethernet MAC 00756 */ 00757 00758 typedef struct 00759 { 00760 __IO uint32_t MACCR; 00761 __IO uint32_t MACFFR; 00762 __IO uint32_t MACHTHR; 00763 __IO uint32_t MACHTLR; 00764 __IO uint32_t MACMIIAR; 00765 __IO uint32_t MACMIIDR; 00766 __IO uint32_t MACFCR; 00767 __IO uint32_t MACVLANTR; /* 8 */ 00768 uint32_t RESERVED0[2]; 00769 __IO uint32_t MACRWUFFR; /* 11 */ 00770 __IO uint32_t MACPMTCSR; 00771 uint32_t RESERVED1[2]; 00772 __IO uint32_t MACSR; /* 15 */ 00773 __IO uint32_t MACIMR; 00774 __IO uint32_t MACA0HR; 00775 __IO uint32_t MACA0LR; 00776 __IO uint32_t MACA1HR; 00777 __IO uint32_t MACA1LR; 00778 __IO uint32_t MACA2HR; 00779 __IO uint32_t MACA2LR; 00780 __IO uint32_t MACA3HR; 00781 __IO uint32_t MACA3LR; /* 24 */ 00782 uint32_t RESERVED2[40]; 00783 __IO uint32_t MMCCR; /* 65 */ 00784 __IO uint32_t MMCRIR; 00785 __IO uint32_t MMCTIR; 00786 __IO uint32_t MMCRIMR; 00787 __IO uint32_t MMCTIMR; /* 69 */ 00788 uint32_t RESERVED3[14]; 00789 __IO uint32_t MMCTGFSCCR; /* 84 */ 00790 __IO uint32_t MMCTGFMSCCR; 00791 uint32_t RESERVED4[5]; 00792 __IO uint32_t MMCTGFCR; 00793 uint32_t RESERVED5[10]; 00794 __IO uint32_t MMCRFCECR; 00795 __IO uint32_t MMCRFAECR; 00796 uint32_t RESERVED6[10]; 00797 __IO uint32_t MMCRGUFCR; 00798 uint32_t RESERVED7[334]; 00799 __IO uint32_t PTPTSCR; 00800 __IO uint32_t PTPSSIR; 00801 __IO uint32_t PTPTSHR; 00802 __IO uint32_t PTPTSLR; 00803 __IO uint32_t PTPTSHUR; 00804 __IO uint32_t PTPTSLUR; 00805 __IO uint32_t PTPTSAR; 00806 __IO uint32_t PTPTTHR; 00807 __IO uint32_t PTPTTLR; 00808 __IO uint32_t RESERVED8; 00809 __IO uint32_t PTPTSSR; 00810 uint32_t RESERVED9[565]; 00811 __IO uint32_t DMABMR; 00812 __IO uint32_t DMATPDR; 00813 __IO uint32_t DMARPDR; 00814 __IO uint32_t DMARDLAR; 00815 __IO uint32_t DMATDLAR; 00816 __IO uint32_t DMASR; 00817 __IO uint32_t DMAOMR; 00818 __IO uint32_t DMAIER; 00819 __IO uint32_t DMAMFBOCR; 00820 __IO uint32_t DMARSWTR; 00821 uint32_t RESERVED10[8]; 00822 __IO uint32_t DMACHTDR; 00823 __IO uint32_t DMACHRDR; 00824 __IO uint32_t DMACHTBAR; 00825 __IO uint32_t DMACHRBAR; 00826 } ETH_TypeDef_mort; 00827 00828 /** 00829 * @brief External Interrupt/Event Controller 00830 */ 00831 00832 typedef struct 00833 { 00834 __IO uint32_t IMR; /*!< EXTI_MORT Interrupt mask register, Address offset: 0x00 */ 00835 __IO uint32_t EMR; /*!< EXTI_MORT Event mask register, Address offset: 0x04 */ 00836 __IO uint32_t RTSR; /*!< EXTI_MORT Rising trigger selection register, Address offset: 0x08 */ 00837 __IO uint32_t FTSR; /*!< EXTI_MORT Falling trigger selection register, Address offset: 0x0C */ 00838 __IO uint32_t SWIER; /*!< EXTI_MORT Software interrupt event register, Address offset: 0x10 */ 00839 __IO uint32_t PR; /*!< EXTI_MORT Pending register, Address offset: 0x14 */ 00840 } EXTI_TypeDef_mort; 00841 00842 /** 00843 * @brief FLASH_MORT Registers 00844 */ 00845 00846 typedef struct 00847 { 00848 __IO uint32_t ACR; /*!< FLASH_MORT access control register, Address offset: 0x00 */ 00849 __IO uint32_t KEYR; /*!< FLASH_MORT key register, Address offset: 0x04 */ 00850 __IO uint32_t OPTKEYR; /*!< FLASH_MORT option key register, Address offset: 0x08 */ 00851 __IO uint32_t SR; /*!< FLASH_MORT status register, Address offset: 0x0C */ 00852 __IO uint32_t CR; /*!< FLASH_MORT control register, Address offset: 0x10 */ 00853 __IO uint32_t OPTCR; /*!< FLASH_MORT option control register , Address offset: 0x14 */ 00854 __IO uint32_t OPTCR1; /*!< FLASH_MORT option control register 1, Address offset: 0x18 */ 00855 } FLASH_TypeDef_mort; 00856 00857 #if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) 00858 /** 00859 * @brief Flexible Static Memory Controller 00860 */ 00861 00862 typedef struct 00863 { 00864 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ 00865 } FSMC_Bank1_TypeDef_mort; 00866 00867 /** 00868 * @brief Flexible Static Memory Controller Bank1E 00869 */ 00870 00871 typedef struct 00872 { 00873 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ 00874 } FSMC_Bank1E_TypeDef_mort; 00875 00876 /** 00877 * @brief Flexible Static Memory Controller Bank2 00878 */ 00879 00880 typedef struct 00881 { 00882 __IO uint32_t PCR2; /*!< NAND FLASH_MORT control register 2, Address offset: 0x60 */ 00883 __IO uint32_t SR2; /*!< NAND FLASH_MORT FIFO status and interrupt register 2, Address offset: 0x64 */ 00884 __IO uint32_t PMEM2; /*!< NAND FLASH_MORT Common memory space timing register 2, Address offset: 0x68 */ 00885 __IO uint32_t PATT2; /*!< NAND FLASH_MORT Attribute memory space timing register 2, Address offset: 0x6C */ 00886 uint32_t RESERVED0; /*!< Reserved, 0x70 */ 00887 __IO uint32_t ECCR2; /*!< NAND FLASH_MORT ECC result registers 2, Address offset: 0x74 */ 00888 } FSMC_Bank2_TypeDef_mort; 00889 00890 /** 00891 * @brief Flexible Static Memory Controller Bank3 00892 */ 00893 00894 typedef struct 00895 { 00896 __IO uint32_t PCR3; /*!< NAND FLASH_MORT control register 3, Address offset: 0x80 */ 00897 __IO uint32_t SR3; /*!< NAND FLASH_MORT FIFO status and interrupt register 3, Address offset: 0x84 */ 00898 __IO uint32_t PMEM3; /*!< NAND FLASH_MORT Common memory space timing register 3, Address offset: 0x88 */ 00899 __IO uint32_t PATT3; /*!< NAND FLASH_MORT Attribute memory space timing register 3, Address offset: 0x8C */ 00900 uint32_t RESERVED0; /*!< Reserved, 0x90 */ 00901 __IO uint32_t ECCR3; /*!< NAND FLASH_MORT ECC result registers 3, Address offset: 0x94 */ 00902 } FSMC_Bank3_TypeDef_mort; 00903 00904 /** 00905 * @brief Flexible Static Memory Controller Bank4 00906 */ 00907 00908 typedef struct 00909 { 00910 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ 00911 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ 00912 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ 00913 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ 00914 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ 00915 } FSMC_Bank4_TypeDef_mort; 00916 #endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */ 00917 00918 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) 00919 /** 00920 * @brief Flexible Memory Controller 00921 */ 00922 00923 typedef struct 00924 { 00925 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ 00926 } FMC_Bank1_TypeDef_mort; 00927 00928 /** 00929 * @brief Flexible Memory Controller Bank1E 00930 */ 00931 00932 typedef struct 00933 { 00934 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ 00935 } FMC_Bank1E_TypeDef_mort; 00936 00937 /** 00938 * @brief Flexible Memory Controller Bank2 00939 */ 00940 00941 typedef struct 00942 { 00943 __IO uint32_t PCR2; /*!< NAND FLASH_MORT control register 2, Address offset: 0x60 */ 00944 __IO uint32_t SR2; /*!< NAND FLASH_MORT FIFO status and interrupt register 2, Address offset: 0x64 */ 00945 __IO uint32_t PMEM2; /*!< NAND FLASH_MORT Common memory space timing register 2, Address offset: 0x68 */ 00946 __IO uint32_t PATT2; /*!< NAND FLASH_MORT Attribute memory space timing register 2, Address offset: 0x6C */ 00947 uint32_t RESERVED0; /*!< Reserved, 0x70 */ 00948 __IO uint32_t ECCR2; /*!< NAND FLASH_MORT ECC result registers 2, Address offset: 0x74 */ 00949 } FMC_Bank2_TypeDef_mort; 00950 00951 /** 00952 * @brief Flexible Memory Controller Bank3 00953 */ 00954 00955 typedef struct 00956 { 00957 __IO uint32_t PCR3; /*!< NAND FLASH_MORT control register 3, Address offset: 0x80 */ 00958 __IO uint32_t SR3; /*!< NAND FLASH_MORT FIFO status and interrupt register 3, Address offset: 0x84 */ 00959 __IO uint32_t PMEM3; /*!< NAND FLASH_MORT Common memory space timing register 3, Address offset: 0x88 */ 00960 __IO uint32_t PATT3; /*!< NAND FLASH_MORT Attribute memory space timing register 3, Address offset: 0x8C */ 00961 uint32_t RESERVED0; /*!< Reserved, 0x90 */ 00962 __IO uint32_t ECCR3; /*!< NAND FLASH_MORT ECC result registers 3, Address offset: 0x94 */ 00963 } FMC_Bank3_TypeDef_mort; 00964 00965 /** 00966 * @brief Flexible Memory Controller Bank4 00967 */ 00968 00969 typedef struct 00970 { 00971 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ 00972 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ 00973 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ 00974 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ 00975 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ 00976 } FMC_Bank4_TypeDef_mort; 00977 00978 /** 00979 * @brief Flexible Memory Controller Bank5_6 00980 */ 00981 00982 typedef struct 00983 { 00984 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ 00985 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ 00986 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ 00987 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ 00988 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ 00989 } FMC_Bank5_6_TypeDef_mort; 00990 #endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx_MORT || STM32F469_479xx */ 00991 00992 /** 00993 * @brief General Purpose I/O 00994 */ 00995 00996 typedef struct 00997 { 00998 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ 00999 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ 01000 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ 01001 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ 01002 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ 01003 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ 01004 __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ 01005 __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ 01006 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ 01007 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ 01008 } GPIO_TypeDef_mort; 01009 01010 /** 01011 * @brief System configuration controller 01012 */ 01013 01014 typedef struct 01015 { 01016 __IO uint32_t MEMRMP; /*!< SYSCFG_MORT memory remap register, Address offset: 0x00 */ 01017 __IO uint32_t PMC; /*!< SYSCFG_MORT peripheral mode configuration register, Address offset: 0x04 */ 01018 __IO uint32_t EXTICR[4]; /*!< SYSCFG_MORT external interrupt configuration registers, Address offset: 0x08-0x14 */ 01019 #if defined (STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) 01020 uint32_t RESERVED; /*!< Reserved, 0x18 */ 01021 __IO uint32_t CFGR2; /*!< Reserved, 0x1C */ 01022 __IO uint32_t CMPCR; /*!< SYSCFG_MORT Compensation cell control register, Address offset: 0x20 */ 01023 uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */ 01024 __IO uint32_t CFGR; /*!< SYSCFG_MORT Configuration register, Address offset: 0x2C */ 01025 #else /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F446xx_MORT || STM32F469_479xx */ 01026 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ 01027 __IO uint32_t CMPCR; /*!< SYSCFG_MORT Compensation cell control register, Address offset: 0x20 */ 01028 #endif /* STM32F410xx || defined(STM32F412xG) || defined(STM32F413_423xx) */ 01029 #if defined(STM32F413_423xx) 01030 __IO uint32_t MCHDLYCR; /*!< SYSCFG_MORT multi-channel delay register, Address offset: 0x30 */ 01031 #endif /* STM32F413_423xx */ 01032 } SYSCFG_TypeDef_mort; 01033 01034 /** 01035 * @brief Inter-integrated Circuit Interface 01036 */ 01037 01038 typedef struct 01039 { 01040 __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ 01041 uint16_t RESERVED0; /*!< Reserved, 0x02 */ 01042 __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ 01043 uint16_t RESERVED1; /*!< Reserved, 0x06 */ 01044 __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ 01045 uint16_t RESERVED2; /*!< Reserved, 0x0A */ 01046 __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ 01047 uint16_t RESERVED3; /*!< Reserved, 0x0E */ 01048 __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */ 01049 uint16_t RESERVED4; /*!< Reserved, 0x12 */ 01050 __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ 01051 uint16_t RESERVED5; /*!< Reserved, 0x16 */ 01052 __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ 01053 uint16_t RESERVED6; /*!< Reserved, 0x1A */ 01054 __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ 01055 uint16_t RESERVED7; /*!< Reserved, 0x1E */ 01056 __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ 01057 uint16_t RESERVED8; /*!< Reserved, 0x22 */ 01058 __IO uint16_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */ 01059 uint16_t RESERVED9; /*!< Reserved, 0x26 */ 01060 } I2C_TypeDef_mort; 01061 01062 #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) 01063 /** 01064 * @brief Inter-integrated Circuit Interface 01065 */ 01066 01067 typedef struct 01068 { 01069 __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */ 01070 __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */ 01071 __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */ 01072 __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */ 01073 __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */ 01074 __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */ 01075 __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */ 01076 __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */ 01077 __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */ 01078 __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */ 01079 __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */ 01080 }FMPI2C_TypeDef_mort; 01081 #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx_MORT */ 01082 01083 /** 01084 * @brief Independent WATCHDOG 01085 */ 01086 01087 typedef struct 01088 { 01089 __IO uint32_t KR; /*!< IWDG_MORT Key register, Address offset: 0x00 */ 01090 __IO uint32_t PR; /*!< IWDG_MORT Prescaler register, Address offset: 0x04 */ 01091 __IO uint32_t RLR; /*!< IWDG_MORT Reload register, Address offset: 0x08 */ 01092 __IO uint32_t SR; /*!< IWDG_MORT Status register, Address offset: 0x0C */ 01093 } IWDG_TypeDef_mort; 01094 01095 /** 01096 * @brief LCD-TFT Display Controller 01097 */ 01098 01099 typedef struct 01100 { 01101 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ 01102 __IO uint32_t SSCR; /*!< LTDC_MORT Synchronization Size Configuration Register, Address offset: 0x08 */ 01103 __IO uint32_t BPCR; /*!< LTDC_MORT Back Porch Configuration Register, Address offset: 0x0C */ 01104 __IO uint32_t AWCR; /*!< LTDC_MORT Active Width Configuration Register, Address offset: 0x10 */ 01105 __IO uint32_t TWCR; /*!< LTDC_MORT Total Width Configuration Register, Address offset: 0x14 */ 01106 __IO uint32_t GCR; /*!< LTDC_MORT Global Control Register, Address offset: 0x18 */ 01107 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ 01108 __IO uint32_t SRCR; /*!< LTDC_MORT Shadow Reload Configuration Register, Address offset: 0x24 */ 01109 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ 01110 __IO uint32_t BCCR; /*!< LTDC_MORT Background Color Configuration Register, Address offset: 0x2C */ 01111 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ 01112 __IO uint32_t IER; /*!< LTDC_MORT Interrupt Enable Register, Address offset: 0x34 */ 01113 __IO uint32_t ISR; /*!< LTDC_MORT Interrupt Status Register, Address offset: 0x38 */ 01114 __IO uint32_t ICR; /*!< LTDC_MORT Interrupt Clear Register, Address offset: 0x3C */ 01115 __IO uint32_t LIPCR; /*!< LTDC_MORT Line Interrupt Position Configuration Register, Address offset: 0x40 */ 01116 __IO uint32_t CPSR; /*!< LTDC_MORT Current Position Status Register, Address offset: 0x44 */ 01117 __IO uint32_t CDSR; /*!< LTDC_MORT Current Display Status Register, Address offset: 0x48 */ 01118 } LTDC_TypeDef_mort; 01119 01120 /** 01121 * @brief LCD-TFT Display layer x Controller 01122 */ 01123 01124 typedef struct 01125 { 01126 __IO uint32_t CR; /*!< LTDC_MORT Layerx Control Register Address offset: 0x84 */ 01127 __IO uint32_t WHPCR; /*!< LTDC_MORT Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ 01128 __IO uint32_t WVPCR; /*!< LTDC_MORT Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ 01129 __IO uint32_t CKCR; /*!< LTDC_MORT Layerx Color Keying Configuration Register Address offset: 0x90 */ 01130 __IO uint32_t PFCR; /*!< LTDC_MORT Layerx Pixel Format Configuration Register Address offset: 0x94 */ 01131 __IO uint32_t CACR; /*!< LTDC_MORT Layerx Constant Alpha Configuration Register Address offset: 0x98 */ 01132 __IO uint32_t DCCR; /*!< LTDC_MORT Layerx Default Color Configuration Register Address offset: 0x9C */ 01133 __IO uint32_t BFCR; /*!< LTDC_MORT Layerx Blending Factors Configuration Register Address offset: 0xA0 */ 01134 uint32_t RESERVED0[2]; /*!< Reserved */ 01135 __IO uint32_t CFBAR; /*!< LTDC_MORT Layerx Color Frame Buffer Address Register Address offset: 0xAC */ 01136 __IO uint32_t CFBLR; /*!< LTDC_MORT Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ 01137 __IO uint32_t CFBLNR; /*!< LTDC_MORT Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ 01138 uint32_t RESERVED1[3]; /*!< Reserved */ 01139 __IO uint32_t CLUTWR; /*!< LTDC_MORT Layerx CLUT Write Register Address offset: 0x144 */ 01140 01141 } LTDC_Layer_TypeDef_mort; 01142 01143 /** 01144 * @brief Power Control 01145 */ 01146 01147 typedef struct 01148 { 01149 __IO uint32_t CR; /*!< PWR_MORT power control register, Address offset: 0x00 */ 01150 __IO uint32_t CSR; /*!< PWR_MORT power control/status register, Address offset: 0x04 */ 01151 } PWR_TypeDef_mort; 01152 01153 /** 01154 * @brief Reset and Clock Control 01155 */ 01156 01157 typedef struct 01158 { 01159 __IO uint32_t CR; /*!< RCC_MORT clock control register, Address offset: 0x00 */ 01160 __IO uint32_t PLLCFGR; /*!< RCC_MORT PLL configuration register, Address offset: 0x04 */ 01161 __IO uint32_t CFGR; /*!< RCC_MORT clock configuration register, Address offset: 0x08 */ 01162 __IO uint32_t CIR; /*!< RCC_MORT clock interrupt register, Address offset: 0x0C */ 01163 __IO uint32_t AHB1RSTR; /*!< RCC_MORT AHB1 peripheral reset register, Address offset: 0x10 */ 01164 __IO uint32_t AHB2RSTR; /*!< RCC_MORT AHB2 peripheral reset register, Address offset: 0x14 */ 01165 __IO uint32_t AHB3RSTR; /*!< RCC_MORT AHB3 peripheral reset register, Address offset: 0x18 */ 01166 uint32_t RESERVED0; /*!< Reserved, 0x1C */ 01167 __IO uint32_t APB1RSTR; /*!< RCC_MORT APB1 peripheral reset register, Address offset: 0x20 */ 01168 __IO uint32_t APB2RSTR; /*!< RCC_MORT APB2 peripheral reset register, Address offset: 0x24 */ 01169 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ 01170 __IO uint32_t AHB1ENR; /*!< RCC_MORT AHB1 peripheral clock register, Address offset: 0x30 */ 01171 __IO uint32_t AHB2ENR; /*!< RCC_MORT AHB2 peripheral clock register, Address offset: 0x34 */ 01172 __IO uint32_t AHB3ENR; /*!< RCC_MORT AHB3 peripheral clock register, Address offset: 0x38 */ 01173 uint32_t RESERVED2; /*!< Reserved, 0x3C */ 01174 __IO uint32_t APB1ENR; /*!< RCC_MORT APB1 peripheral clock enable register, Address offset: 0x40 */ 01175 __IO uint32_t APB2ENR; /*!< RCC_MORT APB2 peripheral clock enable register, Address offset: 0x44 */ 01176 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ 01177 __IO uint32_t AHB1LPENR; /*!< RCC_MORT AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ 01178 __IO uint32_t AHB2LPENR; /*!< RCC_MORT AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ 01179 __IO uint32_t AHB3LPENR; /*!< RCC_MORT AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ 01180 uint32_t RESERVED4; /*!< Reserved, 0x5C */ 01181 __IO uint32_t APB1LPENR; /*!< RCC_MORT APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ 01182 __IO uint32_t APB2LPENR; /*!< RCC_MORT APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ 01183 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ 01184 __IO uint32_t BDCR; /*!< RCC_MORT Backup domain control register, Address offset: 0x70 */ 01185 __IO uint32_t CSR; /*!< RCC_MORT clock control & status register, Address offset: 0x74 */ 01186 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ 01187 __IO uint32_t SSCGR; /*!< RCC_MORT spread spectrum clock generation register, Address offset: 0x80 */ 01188 __IO uint32_t PLLI2SCFGR; /*!< RCC_MORT PLLI2S configuration register, Address offset: 0x84 */ 01189 __IO uint32_t PLLSAICFGR; /*!< RCC_MORT PLLSAI configuration register, Address offset: 0x88 */ 01190 __IO uint32_t DCKCFGR; /*!< RCC_MORT Dedicated Clocks configuration register, Address offset: 0x8C */ 01191 __IO uint32_t CKGATENR; /*!< RCC_MORT Clocks Gated Enable Register, Address offset: 0x90 */ /* Only for STM32F412xG, STM32413_423xx and STM32F446xx_MORT devices */ 01192 __IO uint32_t DCKCFGR2; /*!< RCC_MORT Dedicated Clocks configuration register 2, Address offset: 0x94 */ /* Only for STM32F410xx, STM32F412xG, STM32413_423xx and STM32F446xx_MORT devices */ 01193 01194 } RCC_TypeDef_mort; 01195 01196 /** 01197 * @brief Real-Time Clock 01198 */ 01199 01200 typedef struct 01201 { 01202 __IO uint32_t TR; /*!< RTC_MORT time register, Address offset: 0x00 */ 01203 __IO uint32_t DR; /*!< RTC_MORT date register, Address offset: 0x04 */ 01204 __IO uint32_t CR; /*!< RTC_MORT control register, Address offset: 0x08 */ 01205 __IO uint32_t ISR; /*!< RTC_MORT initialization and status register, Address offset: 0x0C */ 01206 __IO uint32_t PRER; /*!< RTC_MORT prescaler register, Address offset: 0x10 */ 01207 __IO uint32_t WUTR; /*!< RTC_MORT wakeup timer register, Address offset: 0x14 */ 01208 __IO uint32_t CALIBR; /*!< RTC_MORT calibration register, Address offset: 0x18 */ 01209 __IO uint32_t ALRMAR; /*!< RTC_MORT alarm A register, Address offset: 0x1C */ 01210 __IO uint32_t ALRMBR; /*!< RTC_MORT alarm B register, Address offset: 0x20 */ 01211 __IO uint32_t WPR; /*!< RTC_MORT write protection register, Address offset: 0x24 */ 01212 __IO uint32_t SSR; /*!< RTC_MORT sub second register, Address offset: 0x28 */ 01213 __IO uint32_t SHIFTR; /*!< RTC_MORT shift control register, Address offset: 0x2C */ 01214 __IO uint32_t TSTR; /*!< RTC_MORT time stamp time register, Address offset: 0x30 */ 01215 __IO uint32_t TSDR; /*!< RTC_MORT time stamp date register, Address offset: 0x34 */ 01216 __IO uint32_t TSSSR; /*!< RTC_MORT time-stamp sub second register, Address offset: 0x38 */ 01217 __IO uint32_t CALR; /*!< RTC_MORT calibration register, Address offset: 0x3C */ 01218 __IO uint32_t TAFCR; /*!< RTC_MORT tamper and alternate function configuration register, Address offset: 0x40 */ 01219 __IO uint32_t ALRMASSR;/*!< RTC_MORT alarm A sub second register, Address offset: 0x44 */ 01220 __IO uint32_t ALRMBSSR;/*!< RTC_MORT alarm B sub second register, Address offset: 0x48 */ 01221 uint32_t RESERVED7; /*!< Reserved, 0x4C */ 01222 __IO uint32_t BKP0R; /*!< RTC_MORT backup register 1, Address offset: 0x50 */ 01223 __IO uint32_t BKP1R; /*!< RTC_MORT backup register 1, Address offset: 0x54 */ 01224 __IO uint32_t BKP2R; /*!< RTC_MORT backup register 2, Address offset: 0x58 */ 01225 __IO uint32_t BKP3R; /*!< RTC_MORT backup register 3, Address offset: 0x5C */ 01226 __IO uint32_t BKP4R; /*!< RTC_MORT backup register 4, Address offset: 0x60 */ 01227 __IO uint32_t BKP5R; /*!< RTC_MORT backup register 5, Address offset: 0x64 */ 01228 __IO uint32_t BKP6R; /*!< RTC_MORT backup register 6, Address offset: 0x68 */ 01229 __IO uint32_t BKP7R; /*!< RTC_MORT backup register 7, Address offset: 0x6C */ 01230 __IO uint32_t BKP8R; /*!< RTC_MORT backup register 8, Address offset: 0x70 */ 01231 __IO uint32_t BKP9R; /*!< RTC_MORT backup register 9, Address offset: 0x74 */ 01232 __IO uint32_t BKP10R; /*!< RTC_MORT backup register 10, Address offset: 0x78 */ 01233 __IO uint32_t BKP11R; /*!< RTC_MORT backup register 11, Address offset: 0x7C */ 01234 __IO uint32_t BKP12R; /*!< RTC_MORT backup register 12, Address offset: 0x80 */ 01235 __IO uint32_t BKP13R; /*!< RTC_MORT backup register 13, Address offset: 0x84 */ 01236 __IO uint32_t BKP14R; /*!< RTC_MORT backup register 14, Address offset: 0x88 */ 01237 __IO uint32_t BKP15R; /*!< RTC_MORT backup register 15, Address offset: 0x8C */ 01238 __IO uint32_t BKP16R; /*!< RTC_MORT backup register 16, Address offset: 0x90 */ 01239 __IO uint32_t BKP17R; /*!< RTC_MORT backup register 17, Address offset: 0x94 */ 01240 __IO uint32_t BKP18R; /*!< RTC_MORT backup register 18, Address offset: 0x98 */ 01241 __IO uint32_t BKP19R; /*!< RTC_MORT backup register 19, Address offset: 0x9C */ 01242 } RTC_TypeDef_mort; 01243 01244 01245 /** 01246 * @brief Serial Audio Interface 01247 */ 01248 01249 typedef struct 01250 { 01251 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ 01252 } SAI_TypeDef_mort; 01253 01254 typedef struct 01255 { 01256 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ 01257 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ 01258 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ 01259 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ 01260 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ 01261 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ 01262 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ 01263 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ 01264 } SAI_Block_TypeDef_mort; 01265 01266 /** 01267 * @brief SD host Interface 01268 */ 01269 01270 typedef struct 01271 { 01272 __IO uint32_t POWER; /*!< SDIO_MORT power control register, Address offset: 0x00 */ 01273 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ 01274 __IO uint32_t ARG; /*!< SDIO_MORT argument register, Address offset: 0x08 */ 01275 __IO uint32_t CMD; /*!< SDIO_MORT command register, Address offset: 0x0C */ 01276 __I uint32_t RESPCMD; /*!< SDIO_MORT command response register, Address offset: 0x10 */ 01277 __I uint32_t RESP1; /*!< SDIO_MORT response 1 register, Address offset: 0x14 */ 01278 __I uint32_t RESP2; /*!< SDIO_MORT response 2 register, Address offset: 0x18 */ 01279 __I uint32_t RESP3; /*!< SDIO_MORT response 3 register, Address offset: 0x1C */ 01280 __I uint32_t RESP4; /*!< SDIO_MORT response 4 register, Address offset: 0x20 */ 01281 __IO uint32_t DTIMER; /*!< SDIO_MORT data timer register, Address offset: 0x24 */ 01282 __IO uint32_t DLEN; /*!< SDIO_MORT data length register, Address offset: 0x28 */ 01283 __IO uint32_t DCTRL; /*!< SDIO_MORT data control register, Address offset: 0x2C */ 01284 __I uint32_t DCOUNT; /*!< SDIO_MORT data counter register, Address offset: 0x30 */ 01285 __I uint32_t STA; /*!< SDIO_MORT status register, Address offset: 0x34 */ 01286 __IO uint32_t ICR; /*!< SDIO_MORT interrupt clear register, Address offset: 0x38 */ 01287 __IO uint32_t MASK; /*!< SDIO_MORT mask register, Address offset: 0x3C */ 01288 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ 01289 __I uint32_t FIFOCNT; /*!< SDIO_MORT FIFO counter register, Address offset: 0x48 */ 01290 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ 01291 __IO uint32_t FIFO; /*!< SDIO_MORT data FIFO register, Address offset: 0x80 */ 01292 } SDIO_TypeDef_mort; 01293 01294 /** 01295 * @brief Serial Peripheral Interface 01296 */ 01297 01298 typedef struct 01299 { 01300 __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ 01301 uint16_t RESERVED0; /*!< Reserved, 0x02 */ 01302 __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ 01303 uint16_t RESERVED1; /*!< Reserved, 0x06 */ 01304 __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */ 01305 uint16_t RESERVED2; /*!< Reserved, 0x0A */ 01306 __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ 01307 uint16_t RESERVED3; /*!< Reserved, 0x0E */ 01308 __IO uint16_t CRCPR; /*!< SPI CRC_MORT polynomial register (not used in I2S mode), Address offset: 0x10 */ 01309 uint16_t RESERVED4; /*!< Reserved, 0x12 */ 01310 __IO uint16_t RXCRCR; /*!< SPI RX CRC_MORT register (not used in I2S mode), Address offset: 0x14 */ 01311 uint16_t RESERVED5; /*!< Reserved, 0x16 */ 01312 __IO uint16_t TXCRCR; /*!< SPI TX CRC_MORT register (not used in I2S mode), Address offset: 0x18 */ 01313 uint16_t RESERVED6; /*!< Reserved, 0x1A */ 01314 __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ 01315 uint16_t RESERVED7; /*!< Reserved, 0x1E */ 01316 __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ 01317 uint16_t RESERVED8; /*!< Reserved, 0x22 */ 01318 } SPI_TypeDef_mort; 01319 01320 #if defined(STM32F446xx_MORT) 01321 /** 01322 * @brief SPDIFRX_MORT Interface 01323 */ 01324 typedef struct 01325 { 01326 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ 01327 __IO uint16_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ 01328 uint16_t RESERVED0; /*!< Reserved, 0x06 */ 01329 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ 01330 __IO uint16_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ 01331 uint16_t RESERVED1; /*!< Reserved, 0x0E */ 01332 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ 01333 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ 01334 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ 01335 uint16_t RESERVED2; /*!< Reserved, 0x1A */ 01336 } SPDIFRX_TypeDef_mort; 01337 #endif /* STM32F446xx_MORT */ 01338 01339 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) 01340 /** 01341 * @brief QUAD Serial Peripheral Interface 01342 */ 01343 typedef struct 01344 { 01345 __IO uint32_t CR; /*!< QUADSPI_MORT Control register, Address offset: 0x00 */ 01346 __IO uint32_t DCR; /*!< QUADSPI_MORT Device Configuration register, Address offset: 0x04 */ 01347 __IO uint32_t SR; /*!< QUADSPI_MORT Status register, Address offset: 0x08 */ 01348 __IO uint32_t FCR; /*!< QUADSPI_MORT Flag Clear register, Address offset: 0x0C */ 01349 __IO uint32_t DLR; /*!< QUADSPI_MORT Data Length register, Address offset: 0x10 */ 01350 __IO uint32_t CCR; /*!< QUADSPI_MORT Communication Configuration register, Address offset: 0x14 */ 01351 __IO uint32_t AR; /*!< QUADSPI_MORT Address register, Address offset: 0x18 */ 01352 __IO uint32_t ABR; /*!< QUADSPI_MORT Alternate Bytes register, Address offset: 0x1C */ 01353 __IO uint32_t DR; /*!< QUADSPI_MORT Data register, Address offset: 0x20 */ 01354 __IO uint32_t PSMKR; /*!< QUADSPI_MORT Polling Status Mask register, Address offset: 0x24 */ 01355 __IO uint32_t PSMAR; /*!< QUADSPI_MORT Polling Status Match register, Address offset: 0x28 */ 01356 __IO uint32_t PIR; /*!< QUADSPI_MORT Polling Interval register, Address offset: 0x2C */ 01357 __IO uint32_t LPTR; /*!< QUADSPI_MORT Low Power Timeout register, Address offset: 0x30 */ 01358 } QUADSPI_TypeDef_mort; 01359 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx_MORT || STM32F469_479xx */ 01360 01361 #if defined(STM32F446xx_MORT) 01362 /** 01363 * @brief SPDIF-RX Interface 01364 */ 01365 typedef struct 01366 { 01367 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ 01368 __IO uint16_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ 01369 uint16_t RESERVED0; /*!< Reserved, 0x06 */ 01370 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ 01371 __IO uint16_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ 01372 uint16_t RESERVED1; /*!< Reserved, 0x0E */ 01373 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ 01374 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ 01375 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ 01376 uint16_t RESERVED2; /*!< Reserved, 0x1A */ 01377 } SPDIF_TypeDef_mort; 01378 #endif /* STM32F446xx_MORT */ 01379 01380 /** 01381 * @brief TIM 01382 */ 01383 01384 typedef struct 01385 { 01386 __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ 01387 uint16_t RESERVED0; /*!< Reserved, 0x02 */ 01388 __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ 01389 uint16_t RESERVED1; /*!< Reserved, 0x06 */ 01390 __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ 01391 uint16_t RESERVED2; /*!< Reserved, 0x0A */ 01392 __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ 01393 uint16_t RESERVED3; /*!< Reserved, 0x0E */ 01394 __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */ 01395 uint16_t RESERVED4; /*!< Reserved, 0x12 */ 01396 __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ 01397 uint16_t RESERVED5; /*!< Reserved, 0x16 */ 01398 __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ 01399 uint16_t RESERVED6; /*!< Reserved, 0x1A */ 01400 __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ 01401 uint16_t RESERVED7; /*!< Reserved, 0x1E */ 01402 __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ 01403 uint16_t RESERVED8; /*!< Reserved, 0x22 */ 01404 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ 01405 __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ 01406 uint16_t RESERVED9; /*!< Reserved, 0x2A */ 01407 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ 01408 __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ 01409 uint16_t RESERVED10; /*!< Reserved, 0x32 */ 01410 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ 01411 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ 01412 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ 01413 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ 01414 __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ 01415 uint16_t RESERVED11; /*!< Reserved, 0x46 */ 01416 __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ 01417 uint16_t RESERVED12; /*!< Reserved, 0x4A */ 01418 __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ 01419 uint16_t RESERVED13; /*!< Reserved, 0x4E */ 01420 __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ 01421 uint16_t RESERVED14; /*!< Reserved, 0x52 */ 01422 } TIM_TypeDef_mort; 01423 01424 /** 01425 * @brief Universal Synchronous Asynchronous Receiver Transmitter 01426 */ 01427 01428 typedef struct 01429 { 01430 __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */ 01431 uint16_t RESERVED0; /*!< Reserved, 0x02 */ 01432 __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */ 01433 uint16_t RESERVED1; /*!< Reserved, 0x06 */ 01434 __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ 01435 uint16_t RESERVED2; /*!< Reserved, 0x0A */ 01436 __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ 01437 uint16_t RESERVED3; /*!< Reserved, 0x0E */ 01438 __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ 01439 uint16_t RESERVED4; /*!< Reserved, 0x12 */ 01440 __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ 01441 uint16_t RESERVED5; /*!< Reserved, 0x16 */ 01442 __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ 01443 uint16_t RESERVED6; /*!< Reserved, 0x1A */ 01444 } USART_TypeDef_mort; 01445 01446 /** 01447 * @brief Window WATCHDOG 01448 */ 01449 01450 typedef struct 01451 { 01452 __IO uint32_t CR; /*!< WWDG_MORT Control register, Address offset: 0x00 */ 01453 __IO uint32_t CFR; /*!< WWDG_MORT Configuration register, Address offset: 0x04 */ 01454 __IO uint32_t SR; /*!< WWDG_MORT Status register, Address offset: 0x08 */ 01455 } WWDG_TypeDef_mort; 01456 01457 /** 01458 * @brief Crypto Processor 01459 */ 01460 01461 typedef struct 01462 { 01463 __IO uint32_t CR; /*!< CRYP_MORT control register, Address offset: 0x00 */ 01464 __IO uint32_t SR; /*!< CRYP_MORT status register, Address offset: 0x04 */ 01465 __IO uint32_t DR; /*!< CRYP_MORT data input register, Address offset: 0x08 */ 01466 __IO uint32_t DOUT; /*!< CRYP_MORT data output register, Address offset: 0x0C */ 01467 __IO uint32_t DMACR; /*!< CRYP_MORT DMA control register, Address offset: 0x10 */ 01468 __IO uint32_t IMSCR; /*!< CRYP_MORT interrupt mask set/clear register, Address offset: 0x14 */ 01469 __IO uint32_t RISR; /*!< CRYP_MORT raw interrupt status register, Address offset: 0x18 */ 01470 __IO uint32_t MISR; /*!< CRYP_MORT masked interrupt status register, Address offset: 0x1C */ 01471 __IO uint32_t K0LR; /*!< CRYP_MORT key left register 0, Address offset: 0x20 */ 01472 __IO uint32_t K0RR; /*!< CRYP_MORT key right register 0, Address offset: 0x24 */ 01473 __IO uint32_t K1LR; /*!< CRYP_MORT key left register 1, Address offset: 0x28 */ 01474 __IO uint32_t K1RR; /*!< CRYP_MORT key right register 1, Address offset: 0x2C */ 01475 __IO uint32_t K2LR; /*!< CRYP_MORT key left register 2, Address offset: 0x30 */ 01476 __IO uint32_t K2RR; /*!< CRYP_MORT key right register 2, Address offset: 0x34 */ 01477 __IO uint32_t K3LR; /*!< CRYP_MORT key left register 3, Address offset: 0x38 */ 01478 __IO uint32_t K3RR; /*!< CRYP_MORT key right register 3, Address offset: 0x3C */ 01479 __IO uint32_t IV0LR; /*!< CRYP_MORT initialization vector left-word register 0, Address offset: 0x40 */ 01480 __IO uint32_t IV0RR; /*!< CRYP_MORT initialization vector right-word register 0, Address offset: 0x44 */ 01481 __IO uint32_t IV1LR; /*!< CRYP_MORT initialization vector left-word register 1, Address offset: 0x48 */ 01482 __IO uint32_t IV1RR; /*!< CRYP_MORT initialization vector right-word register 1, Address offset: 0x4C */ 01483 __IO uint32_t CSGCMCCM0R; /*!< CRYP_MORT GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */ 01484 __IO uint32_t CSGCMCCM1R; /*!< CRYP_MORT GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */ 01485 __IO uint32_t CSGCMCCM2R; /*!< CRYP_MORT GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */ 01486 __IO uint32_t CSGCMCCM3R; /*!< CRYP_MORT GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */ 01487 __IO uint32_t CSGCMCCM4R; /*!< CRYP_MORT GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */ 01488 __IO uint32_t CSGCMCCM5R; /*!< CRYP_MORT GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */ 01489 __IO uint32_t CSGCMCCM6R; /*!< CRYP_MORT GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */ 01490 __IO uint32_t CSGCMCCM7R; /*!< CRYP_MORT GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */ 01491 __IO uint32_t CSGCM0R; /*!< CRYP_MORT GCM/GMAC context swap register 0, Address offset: 0x70 */ 01492 __IO uint32_t CSGCM1R; /*!< CRYP_MORT GCM/GMAC context swap register 1, Address offset: 0x74 */ 01493 __IO uint32_t CSGCM2R; /*!< CRYP_MORT GCM/GMAC context swap register 2, Address offset: 0x78 */ 01494 __IO uint32_t CSGCM3R; /*!< CRYP_MORT GCM/GMAC context swap register 3, Address offset: 0x7C */ 01495 __IO uint32_t CSGCM4R; /*!< CRYP_MORT GCM/GMAC context swap register 4, Address offset: 0x80 */ 01496 __IO uint32_t CSGCM5R; /*!< CRYP_MORT GCM/GMAC context swap register 5, Address offset: 0x84 */ 01497 __IO uint32_t CSGCM6R; /*!< CRYP_MORT GCM/GMAC context swap register 6, Address offset: 0x88 */ 01498 __IO uint32_t CSGCM7R; /*!< CRYP_MORT GCM/GMAC context swap register 7, Address offset: 0x8C */ 01499 } CRYP_TypeDef_mort; 01500 01501 /** 01502 * @brief HASH_MORT 01503 */ 01504 01505 typedef struct 01506 { 01507 __IO uint32_t CR; /*!< HASH_MORT control register, Address offset: 0x00 */ 01508 __IO uint32_t DIN; /*!< HASH_MORT data input register, Address offset: 0x04 */ 01509 __IO uint32_t STR; /*!< HASH_MORT start register, Address offset: 0x08 */ 01510 __IO uint32_t HR[5]; /*!< HASH_MORT digest registers, Address offset: 0x0C-0x1C */ 01511 __IO uint32_t IMR; /*!< HASH_MORT interrupt enable register, Address offset: 0x20 */ 01512 __IO uint32_t SR; /*!< HASH_MORT status register, Address offset: 0x24 */ 01513 uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ 01514 __IO uint32_t CSR[54]; /*!< HASH_MORT context swap registers, Address offset: 0x0F8-0x1CC */ 01515 } HASH_TypeDef_mort; 01516 01517 /** 01518 * @brief HASH_DIGEST_MORT 01519 */ 01520 01521 typedef struct 01522 { 01523 __IO uint32_t HR[8]; /*!< HASH_MORT digest registers, Address offset: 0x310-0x32C */ 01524 } HASH_DIGEST_TypeDef_mort; 01525 01526 /** 01527 * @brief RNG_MORT 01528 */ 01529 01530 typedef struct 01531 { 01532 __IO uint32_t CR; /*!< RNG_MORT control register, Address offset: 0x00 */ 01533 __IO uint32_t SR; /*!< RNG_MORT status register, Address offset: 0x04 */ 01534 __IO uint32_t DR; /*!< RNG_MORT data register, Address offset: 0x08 */ 01535 } RNG_TypeDef_mort; 01536 01537 #if defined(STM32F410xx) || defined(STM32F413_423xx) 01538 /** 01539 * @brief LPTIMER 01540 */ 01541 typedef struct 01542 { 01543 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ 01544 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ 01545 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ 01546 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ 01547 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ 01548 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ 01549 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ 01550 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ 01551 __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ 01552 } LPTIM_TypeDef_mort; 01553 #endif /* STM32F410xx || STM32F413_423xx */ 01554 /** 01555 * @} 01556 */ 01557 01558 /** @addtogroup Peripheral_memory_map 01559 * @{ 01560 */ 01561 01562 #define FLASH_BASE_MORT ((uint32_t)0x08000000) /*!< FLASH_MORT(up to 1 MB) base address in the alias region */ 01563 #define CCMDATARAM_BASE_MORT ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ 01564 #define SRAM1_BASE_MORT ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */ 01565 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx_MORT) 01566 #define SRAM2_BASE_MORT ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */ 01567 #define SRAM3_BASE_MORT ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */ 01568 #elif defined(STM32F469_479xx) 01569 #define SRAM2_BASE_MORT ((uint32_t)0x20028000) /*!< SRAM2(16 KB) base address in the alias region */ 01570 #define SRAM3_BASE_MORT ((uint32_t)0x20030000) /*!< SRAM3(64 KB) base address in the alias region */ 01571 #elif defined(STM32F413_423xx) 01572 #define SRAM2_BASE_MORT ((uint32_t)0x20040000) /*!< SRAM2(16 KB) base address in the alias region */ 01573 #else /* STM32F411xE || STM32F410xx || STM32F412xG */ 01574 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx_MORT */ 01575 #define PERIPH_BASE_MORT ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ 01576 #define BKPSRAM_BASE_MORT ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */ 01577 01578 #if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) 01579 #define FSMC_R_BASE_MORT ((uint32_t)0xA0000000) /*!< FSMC registers base address */ 01580 #endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */ 01581 01582 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) 01583 #define FMC_R_BASE_MORT ((uint32_t)0xA0000000) /*!< FMC registers base address */ 01584 #endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx_MORT || STM32F469_479xx */ 01585 01586 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) 01587 #define QSPI_R_BASE_MORT ((uint32_t)0xA0001000) /*!< QUADSPI_MORT registers base address */ 01588 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx_MORT || STM32F469_479xx */ 01589 01590 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */ 01591 #define SRAM1_BB_BASE_MORT ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */ 01592 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx_MORT) 01593 #define SRAM2_BB_BASE_MORT ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */ 01594 #define SRAM3_BB_BASE_MORT ((uint32_t)0x22400000) /*!< SRAM3(64 KB) base address in the bit-band region */ 01595 #elif defined(STM32F469_479xx) 01596 #define SRAM2_BB_BASE_MORT ((uint32_t)0x22500000) /*!< SRAM2(16 KB) base address in the bit-band region */ 01597 #define SRAM3_BB_BASE_MORT ((uint32_t)0x22600000) /*!< SRAM3(64 KB) base address in the bit-band region */ 01598 #elif defined(STM32F413_423xx) 01599 #define SRAM2_BB_BASE_MORT ((uint32_t)0x22800000) /*!< SRAM2(64 KB) base address in the bit-band region */ 01600 #else /* STM32F411xE || STM32F410xx || STM32F412xG */ 01601 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx_MORT */ 01602 #define PERIPH_BB_BASE_MORT ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ 01603 #define BKPSRAM_BB_BASE_MORT ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ 01604 01605 /* Legacy defines */ 01606 #define SRAM_BASE_MORT SRAM1_BASE_MORT 01607 #define SRAM_BB_BASE_MORT SRAM1_BB_BASE_MORT 01608 01609 01610 /*!< Peripheral memory map */ 01611 #define APB1PERIPH_BASE_MORT PERIPH_BASE_MORT 01612 #define APB2PERIPH_BASE_MORT (PERIPH_BASE_MORT + 0x00010000) 01613 #define AHB1PERIPH_BASE_MORT (PERIPH_BASE_MORT + 0x00020000) 01614 #define AHB2PERIPH_BASE_MORT (PERIPH_BASE_MORT + 0x10000000) 01615 01616 /*!< APB1 peripherals */ 01617 #define TIM2_BASE_MORT (APB1PERIPH_BASE_MORT + 0x0000) 01618 #define TIM3_BASE_MORT (APB1PERIPH_BASE_MORT + 0x0400) 01619 #define TIM4_BASE_MORT (APB1PERIPH_BASE_MORT + 0x0800) 01620 #define TIM5_BASE_MORT (APB1PERIPH_BASE_MORT + 0x0C00) 01621 #define TIM6_BASE_MORT (APB1PERIPH_BASE_MORT + 0x1000) 01622 #define TIM7_BASE_MORT (APB1PERIPH_BASE_MORT + 0x1400) 01623 #if defined(STM32F410xx) || defined(STM32F413_423xx) 01624 #define LPTIM1_BASE_MORT (APB1PERIPH_BASE_MORT + 0x2400) 01625 #endif /* STM32F410xx || STM32F413_423xx */ 01626 #define TIM12_BASE_MORT (APB1PERIPH_BASE_MORT + 0x1800) 01627 #define TIM13_BASE_MORT (APB1PERIPH_BASE_MORT + 0x1C00) 01628 #define TIM14_BASE_MORT (APB1PERIPH_BASE_MORT + 0x2000) 01629 #define RTC_BASE_MORT (APB1PERIPH_BASE_MORT + 0x2800) 01630 #define WWDG_BASE_MORT (APB1PERIPH_BASE_MORT + 0x2C00) 01631 #define IWDG_BASE_MORT (APB1PERIPH_BASE_MORT + 0x3000) 01632 #define I2S2ext_BASE_MORT (APB1PERIPH_BASE_MORT + 0x3400) 01633 #define SPI2_BASE_MORT (APB1PERIPH_BASE_MORT + 0x3800) 01634 #define SPI3_BASE_MORT (APB1PERIPH_BASE_MORT + 0x3C00) 01635 #if defined(STM32F446xx_MORT) 01636 #define SPDIFRX_BASE_MORT (APB1PERIPH_BASE_MORT + 0x4000) 01637 #endif /* STM32F446xx_MORT */ 01638 #define I2S3ext_BASE_MORT (APB1PERIPH_BASE_MORT + 0x4000) 01639 #define USART2_BASE_MORT (APB1PERIPH_BASE_MORT + 0x4400) 01640 #define USART3_BASE_MORT (APB1PERIPH_BASE_MORT + 0x4800) 01641 #define UART4_BASE_MORT (APB1PERIPH_BASE_MORT + 0x4C00) 01642 #define UART5_BASE_MORT (APB1PERIPH_BASE_MORT + 0x5000) 01643 #define I2C1_BASE_MORT (APB1PERIPH_BASE_MORT + 0x5400) 01644 #define I2C2_BASE_MORT (APB1PERIPH_BASE_MORT + 0x5800) 01645 #define I2C3_BASE_MORT (APB1PERIPH_BASE_MORT + 0x5C00) 01646 #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) 01647 #define FMPI2C1_BASE_MORT (APB1PERIPH_BASE_MORT + 0x6000) 01648 #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx_MORT */ 01649 #define CAN1_BASE_MORT (APB1PERIPH_BASE_MORT + 0x6400) 01650 #define CAN2_BASE_MORT (APB1PERIPH_BASE_MORT + 0x6800) 01651 #if defined(STM32F413_423xx) 01652 #define CAN3_BASE_MORT (APB1PERIPH_BASE_MORT + 0x6C00) 01653 #endif /* STM32F413_423xx */ 01654 #if defined(STM32F446xx_MORT) 01655 #define CEC_BASE_MORT (APB1PERIPH_BASE_MORT + 0x6C00) 01656 #endif /* STM32F446xx_MORT */ 01657 #define PWR_BASE_MORT (APB1PERIPH_BASE_MORT + 0x7000) 01658 #define DAC_BASE_MORT (APB1PERIPH_BASE_MORT + 0x7400) 01659 #define UART7_BASE_MORT (APB1PERIPH_BASE_MORT + 0x7800) 01660 #define UART8_BASE_MORT (APB1PERIPH_BASE_MORT + 0x7C00) 01661 01662 /*!< APB2 peripherals */ 01663 #define TIM1_BASE_MORT (APB2PERIPH_BASE_MORT + 0x0000) 01664 #define TIM8_BASE_MORT (APB2PERIPH_BASE_MORT + 0x0400) 01665 #define USART1_BASE_MORT (APB2PERIPH_BASE_MORT + 0x1000) 01666 #define USART6_BASE_MORT (APB2PERIPH_BASE_MORT + 0x1400) 01667 #define UART9_BASE_MORT (APB2PERIPH_BASE_MORT + 0x1800U) 01668 #define UART10_BASE_MORT (APB2PERIPH_BASE_MORT + 0x1C00U) 01669 #define ADC1_BASE_MORT (APB2PERIPH_BASE_MORT + 0x2000) 01670 #define ADC2_BASE_MORT (APB2PERIPH_BASE_MORT + 0x2100) 01671 #define ADC3_BASE_MORT (APB2PERIPH_BASE_MORT + 0x2200) 01672 #define ADC_BASE_MORT (APB2PERIPH_BASE_MORT + 0x2300) 01673 #define SDIO_BASE_MORT (APB2PERIPH_BASE_MORT + 0x2C00) 01674 #define SPI1_BASE_MORT (APB2PERIPH_BASE_MORT + 0x3000) 01675 #define SPI4_BASE_MORT (APB2PERIPH_BASE_MORT + 0x3400) 01676 #define SYSCFG_BASE_MORT (APB2PERIPH_BASE_MORT + 0x3800) 01677 #define EXTI_BASE_MORT (APB2PERIPH_BASE_MORT + 0x3C00) 01678 #define TIM9_BASE_MORT (APB2PERIPH_BASE_MORT + 0x4000) 01679 #define TIM10_BASE_MORT (APB2PERIPH_BASE_MORT + 0x4400) 01680 #define TIM11_BASE_MORT (APB2PERIPH_BASE_MORT + 0x4800) 01681 #define SPI5_BASE_MORT (APB2PERIPH_BASE_MORT + 0x5000) 01682 #define SPI6_BASE_MORT (APB2PERIPH_BASE_MORT + 0x5400) 01683 #define SAI1_BASE_MORT (APB2PERIPH_BASE_MORT + 0x5800) 01684 #define SAI1_Block_A_BASE_MORT (SAI1_BASE_MORT + 0x004) 01685 #define SAI1_Block_B_BASE_MORT (SAI1_BASE_MORT + 0x024) 01686 #if defined(STM32F446xx_MORT) 01687 #define SAI2_BASE_MORT (APB2PERIPH_BASE_MORT + 0x5C00) 01688 #define SAI2_Block_A_BASE_MORT (SAI2_BASE_MORT + 0x004) 01689 #define SAI2_Block_B_BASE_MORT (SAI2_BASE_MORT + 0x024) 01690 #endif /* STM32F446xx_MORT */ 01691 #define LTDC_BASE_MORT (APB2PERIPH_BASE_MORT + 0x6800) 01692 #define LTDC_Layer1_BASE_MORT (LTDC_BASE_MORT + 0x84) 01693 #define LTDC_Layer2_BASE_MORT (LTDC_BASE_MORT + 0x104) 01694 #if defined(STM32F469_479xx) 01695 #define DSI_BASE_MORT (APB2PERIPH_BASE_MORT + 0x6C00) 01696 #endif /* STM32F469_479xx */ 01697 #if defined(STM32F412xG) || defined(STM32F413_423xx) 01698 #define DFSDM1_BASE_MORT (APB2PERIPH_BASE_MORT + 0x6000) 01699 #define DFSDM1_Channel0_BASE_MORT (DFSDM1_BASE_MORT + 0x00) 01700 #define DFSDM1_Channel1_BASE_MORT (DFSDM1_BASE_MORT + 0x20) 01701 #define DFSDM1_Channel2_BASE_MORT (DFSDM1_BASE_MORT + 0x40) 01702 #define DFSDM1_Channel3_BASE_MORT (DFSDM1_BASE_MORT + 0x60) 01703 #define DFSDM1_Filter0_BASE_MORT (DFSDM1_BASE_MORT + 0x100) 01704 #define DFSDM1_Filter1_BASE_MORT (DFSDM1_BASE_MORT + 0x180) 01705 #define DFSDM1_0_MORT ((DFSDM_TypeDef *) DFSDM1_Filter0_BASE_MORT) 01706 #define DFSDM1_1_MORT ((DFSDM_TypeDef *) DFSDM1_Filter1_BASE_MORT) 01707 /* Legacy Defines */ 01708 #define DFSDM0 DFSDM1_0_MORT 01709 #define DFSDM1 DFSDM1_1_MORT 01710 #if defined(STM32F413_423xx) 01711 #define DFSDM2_BASE_MORT (APB2PERIPH_BASE_MORT + 0x6400U) 01712 #define DFSDM2_Channel0_BASE_MORT (DFSDM2_BASE_MORT + 0x00U) 01713 #define DFSDM2_Channel1_BASE_MORT (DFSDM2_BASE_MORT + 0x20U) 01714 #define DFSDM2_Channel2_BASE_MORT (DFSDM2_BASE_MORT + 0x40U) 01715 #define DFSDM2_Channel3_BASE_MORT (DFSDM2_BASE_MORT + 0x60U) 01716 #define DFSDM2_Channel4_BASE_MORT (DFSDM2_BASE_MORT + 0x80U) 01717 #define DFSDM2_Channel5_BASE_MORT (DFSDM2_BASE_MORT + 0xA0U) 01718 #define DFSDM2_Channel6_BASE_MORT (DFSDM2_BASE_MORT + 0xC0U) 01719 #define DFSDM2_Channel7_BASE_MORT (DFSDM2_BASE_MORT + 0xE0U) 01720 #define DFSDM2_Filter0_BASE_MORT (DFSDM2_BASE_MORT + 0x100U) 01721 #define DFSDM2_Filter1_BASE_MORT (DFSDM2_BASE_MORT + 0x180U) 01722 #define DFSDM2_Filter2_BASE_MORT (DFSDM2_BASE_MORT + 0x200U) 01723 #define DFSDM2_Filter3_BASE_MORT (DFSDM2_BASE_MORT + 0x280U) 01724 #define DFSDM2_0_MORT ((DFSDM_TypeDef *) DFSDM2_Filter0_BASE_MORT) 01725 #define DFSDM2_1_MORT ((DFSDM_TypeDef *) DFSDM2_Filter1_BASE_MORT) 01726 #define DFSDM2_2_MORT ((DFSDM_TypeDef *) DFSDM2_Filter2_BASE_MORT) 01727 #define DFSDM2_3_MORT ((DFSDM_TypeDef *) DFSDM2_Filter3_BASE_MORT) 01728 #endif /* STM32F413_423xx */ 01729 #endif /* STM32F412xG || STM32F413_423xx */ 01730 01731 /*!< AHB1 peripherals */ 01732 #define GPIOA_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x0000) 01733 #define GPIOB_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x0400) 01734 #define GPIOC_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x0800) 01735 #define GPIOD_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x0C00) 01736 #define GPIOE_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x1000) 01737 #define GPIOF_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x1400) 01738 #define GPIOG_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x1800) 01739 #define GPIOH_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x1C00) 01740 #define GPIOI_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x2000) 01741 #define GPIOJ_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x2400) 01742 #define GPIOK_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x2800) 01743 #define CRC_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x3000) 01744 #define RCC_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x3800) 01745 #define FLASH_R_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x3C00) 01746 #define DMA1_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x6000) 01747 #define DMA1_Stream0_BASE_MORT (DMA1_BASE_MORT + 0x010) 01748 #define DMA1_Stream1_BASE_MORT (DMA1_BASE_MORT + 0x028) 01749 #define DMA1_Stream2_BASE_MORT (DMA1_BASE_MORT + 0x040) 01750 #define DMA1_Stream3_BASE_MORT (DMA1_BASE_MORT + 0x058) 01751 #define DMA1_Stream4_BASE_MORT (DMA1_BASE_MORT + 0x070) 01752 #define DMA1_Stream5_BASE_MORT (DMA1_BASE_MORT + 0x088) 01753 #define DMA1_Stream6_BASE_MORT (DMA1_BASE_MORT + 0x0A0) 01754 #define DMA1_Stream7_BASE_MORT (DMA1_BASE_MORT + 0x0B8) 01755 #define DMA2_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x6400) 01756 #define DMA2_Stream0_BASE_MORT (DMA2_BASE_MORT + 0x010) 01757 #define DMA2_Stream1_BASE_MORT (DMA2_BASE_MORT + 0x028) 01758 #define DMA2_Stream2_BASE_MORT (DMA2_BASE_MORT + 0x040) 01759 #define DMA2_Stream3_BASE_MORT (DMA2_BASE_MORT + 0x058) 01760 #define DMA2_Stream4_BASE_MORT (DMA2_BASE_MORT + 0x070) 01761 #define DMA2_Stream5_BASE_MORT (DMA2_BASE_MORT + 0x088) 01762 #define DMA2_Stream6_BASE_MORT (DMA2_BASE_MORT + 0x0A0) 01763 #define DMA2_Stream7_BASE_MORT (DMA2_BASE_MORT + 0x0B8) 01764 #define ETH_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x8000) 01765 #define ETH_MAC_BASE_MORT (ETH_BASE_MORT) 01766 #define ETH_MMC_BASE_MORT (ETH_BASE_MORT + 0x0100) 01767 #define ETH_PTP_BASE_MORT (ETH_BASE_MORT + 0x0700) 01768 #define ETH_DMA_BASE_MORT (ETH_BASE_MORT + 0x1000) 01769 #define DMA2D_BASE_MORT (AHB1PERIPH_BASE_MORT + 0xB000) 01770 01771 /*!< AHB2 peripherals */ 01772 #define DCMI_BASE_MORT (AHB2PERIPH_BASE_MORT + 0x50000) 01773 #define CRYP_BASE_MORT (AHB2PERIPH_BASE_MORT + 0x60000) 01774 #define HASH_BASE_MORT (AHB2PERIPH_BASE_MORT + 0x60400) 01775 #define HASH_DIGEST_BASE_MORT (AHB2PERIPH_BASE_MORT + 0x60710) 01776 #define RNG_BASE_MORT (AHB2PERIPH_BASE_MORT + 0x60800) 01777 01778 #if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) 01779 /*!< FSMC Bankx registers base address */ 01780 #define FSMC_Bank1_R_BASE_MORT (FSMC_R_BASE_MORT + 0x0000) 01781 #define FSMC_Bank1E_R_BASE_MORT (FSMC_R_BASE_MORT + 0x0104) 01782 #define FSMC_Bank2_R_BASE_MORT (FSMC_R_BASE_MORT + 0x0060) 01783 #define FSMC_Bank3_R_BASE_MORT (FSMC_R_BASE_MORT + 0x0080) 01784 #define FSMC_Bank4_R_BASE_MORT (FSMC_R_BASE_MORT + 0x00A0) 01785 #endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */ 01786 01787 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) 01788 /*!< FMC Bankx registers base address */ 01789 #define FMC_Bank1_R_BASE_MORT (FMC_R_BASE_MORT + 0x0000) 01790 #define FMC_Bank1E_R_BASE_MORT (FMC_R_BASE_MORT + 0x0104) 01791 #define FMC_Bank2_R_BASE_MORT (FMC_R_BASE_MORT + 0x0060) 01792 #define FMC_Bank3_R_BASE_MORT (FMC_R_BASE_MORT + 0x0080) 01793 #define FMC_Bank4_R_BASE_MORT (FMC_R_BASE_MORT + 0x00A0) 01794 #define FMC_Bank5_6_R_BASE_MORT (FMC_R_BASE_MORT + 0x0140) 01795 #endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx_MORT || STM32F469_479xx */ 01796 01797 /* Debug MCU registers base address */ 01798 #define DBGMCU_BASE_MORT ((uint32_t )0xE0042000) 01799 01800 /** 01801 * @} 01802 */ 01803 01804 /** @addtogroup Peripheral_declaration 01805 * @{ 01806 */ 01807 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) 01808 #define QUADSPI_MORT ((QUADSPI_TypeDef_mort *) QSPI_R_BASE_MORT) 01809 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx_MORT || STM32F469_479xx */ 01810 #define TIM2_MORT ((TIM_TypeDef_mort *) TIM2_BASE_MORT) 01811 #define TIM3_MORT ((TIM_TypeDef_mort *) TIM3_BASE_MORT) 01812 #define TIM4_MORT ((TIM_TypeDef_mort *) TIM4_BASE_MORT) 01813 #define TIM5_MORT ((TIM_TypeDef_mort *) TIM5_BASE_MORT) 01814 #define TIM6_MORT ((TIM_TypeDef_mort *) TIM6_BASE_MORT) 01815 #define TIM7_MORT ((TIM_TypeDef_mort *) TIM7_BASE_MORT) 01816 #define TIM12_MORT ((TIM_TypeDef_mort *) TIM12_BASE_MORT) 01817 #define TIM13_MORT ((TIM_TypeDef_mort *) TIM13_BASE_MORT) 01818 #define TIM14_MORT ((TIM_TypeDef_mort *) TIM14_BASE_MORT) 01819 #define RTC_MORT ((RTC_TypeDef_mort *) RTC_BASE_MORT) 01820 #define WWDG_MORT ((WWDG_TypeDef_mort *) WWDG_BASE_MORT) 01821 #define IWDG_MORT ((IWDG_TypeDef_mort *) IWDG_BASE_MORT) 01822 #define I2S2ext_MORT ((SPI_TypeDef_mort *) I2S2ext_BASE_MORT) 01823 #define SPI2_MORT ((SPI_TypeDef_mort *) SPI2_BASE_MORT) 01824 #define SPI3_MORT ((SPI_TypeDef_mort *) SPI3_BASE_MORT) 01825 #if defined(STM32F446xx_MORT) 01826 #define SPDIFRX_MORT ((SPDIFRX_TypeDef_mort *) SPDIFRX_BASE_MORT) 01827 #endif /* STM32F446xx_MORT */ 01828 #define I2S3ext_MORT ((SPI_TypeDef_mort *) I2S3ext_BASE_MORT) 01829 #define USART2_MORT ((USART_TypeDef_mort *) USART2_BASE_MORT) 01830 #define USART3_MORT ((USART_TypeDef_mort *) USART3_BASE_MORT) 01831 #define UART4_MORT ((USART_TypeDef_mort *) UART4_BASE_MORT) 01832 #define UART5_MORT ((USART_TypeDef_mort *) UART5_BASE_MORT) 01833 #define I2C1_MORT ((I2C_TypeDef_mort *) I2C1_BASE_MORT) 01834 #define I2C2_MORT ((I2C_TypeDef_mort *) I2C2_BASE_MORT) 01835 #define I2C3_MORT ((I2C_TypeDef_mort *) I2C3_BASE_MORT) 01836 #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) 01837 #define FMPI2C1_MORT ((FMPI2C_TypeDef_mort *) FMPI2C1_BASE_MORT) 01838 #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx_MORT */ 01839 #if defined(STM32F410xx) || defined(STM32F413_423xx) 01840 #define LPTIM1_MORT ((LPTIM_TypeDef_mort *) LPTIM1_BASE_MORT) 01841 #endif /* STM32F410xx || STM32F413_423xx */ 01842 #define CAN1_MORT ((CAN_TypeDef_mort *) CAN1_BASE_MORT) 01843 #define CAN2_MORT ((CAN_TypeDef_mort *) CAN2_BASE_MORT) 01844 #if defined(STM32F413_423xx) 01845 #define CAN3_MORT ((CAN_TypeDef_mort *) CAN3_BASE_MORT) 01846 #endif /* STM32F413_423xx */ 01847 #if defined(STM32F446xx_MORT) 01848 #define CEC_MORT ((CEC_TypeDef_mort *) CEC_BASE_MORT) 01849 #endif /* STM32F446xx_MORT */ 01850 #define PWR_MORT ((PWR_TypeDef_mort *) PWR_BASE_MORT) 01851 #define DAC_MORT ((DAC_TypeDef_mort *) DAC_BASE_MORT) 01852 #define UART7_MORT ((USART_TypeDef_mort *) UART7_BASE_MORT) 01853 #define UART8_MORT ((USART_TypeDef_mort *) UART8_BASE_MORT) 01854 #define UART9_MORT ((USART_TypeDef_mort *) UART9_BASE_MORT) 01855 #define UART10_MORT ((USART_TypeDef_mort *) UART10_BASE_MORT) 01856 #define TIM1_MORT ((TIM_TypeDef_mort *) TIM1_BASE_MORT) 01857 #define TIM8_MORT ((TIM_TypeDef_mort *) TIM8_BASE_MORT) 01858 #define USART1_MORT ((USART_TypeDef_mort *) USART1_BASE_MORT) 01859 #define USART6_MORT ((USART_TypeDef_mort *) USART6_BASE_MORT) 01860 #define ADC_MORT ((ADC_Common_TypeDef_mort *) ADC_BASE_MORT) 01861 #define ADC1_MORT ((ADC_TypeDef_mort *) ADC1_BASE_MORT) 01862 #define ADC2_MORT ((ADC_TypeDef_mort *) ADC2_BASE_MORT) 01863 #define ADC3_MORT ((ADC_TypeDef_mort *) ADC3_BASE_MORT) 01864 #define SDIO_MORT ((SDIO_TypeDef_mort *) SDIO_BASE_MORT) 01865 #define SPI1_MORT ((SPI_TypeDef_mort *) SPI1_BASE_MORT) 01866 #define SPI4_MORT ((SPI_TypeDef_mort *) SPI4_BASE_MORT) 01867 #define SYSCFG_MORT ((SYSCFG_TypeDef_mort *) SYSCFG_BASE_MORT) 01868 #define EXTI_MORT ((EXTI_TypeDef_mort *) EXTI_BASE_MORT) 01869 #define TIM9_MORT ((TIM_TypeDef_mort *) TIM9_BASE_MORT) 01870 #define TIM10_MORT ((TIM_TypeDef_mort *) TIM10_BASE_MORT) 01871 #define TIM11_MORT ((TIM_TypeDef_mort *) TIM11_BASE_MORT) 01872 #define SPI5_MORT ((SPI_TypeDef_mort *) SPI5_BASE_MORT) 01873 #define SPI6_MORT ((SPI_TypeDef_mort *) SPI6_BASE_MORT) 01874 #define SAI1_MORT ((SAI_TypeDef_mort *) SAI1_BASE_MORT) 01875 #define SAI1_Block_A_MORT ((SAI_Block_TypeDef_mort *)SAI1_Block_A_BASE_MORT) 01876 #define SAI1_Block_B_MORT ((SAI_Block_TypeDef_mort *)SAI1_Block_B_BASE_MORT) 01877 #if defined(STM32F446xx_MORT) 01878 #define SAI2_MORT ((SAI_TypeDef_mort *) SAI2_BASE_MORT) 01879 #define SAI2_Block_A_MORT ((SAI_Block_TypeDef_mort *)SAI2_Block_A_BASE_MORT) 01880 #define SAI2_Block_B_MORT ((SAI_Block_TypeDef_mort *)SAI2_Block_B_BASE_MORT) 01881 #endif /* STM32F446xx_MORT */ 01882 #define LTDC_MORT ((LTDC_TypeDef_mort *)LTDC_BASE_MORT) 01883 #define LTDC_Layer1_MORT ((LTDC_Layer_TypeDef_mort *)LTDC_Layer1_BASE_MORT) 01884 #define LTDC_Layer2_MORT ((LTDC_Layer_TypeDef_mort *)LTDC_Layer2_BASE_MORT) 01885 #if defined(STM32F469_479xx) 01886 #define DSI_MORT ((DSI_TypeDef_mort *)DSI_BASE_MORT) 01887 #endif /* STM32F469_479xx */ 01888 #if defined(STM32F412xG) || defined(STM32F413_423xx) 01889 #define DFSDM1_Channel0_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM1_Channel0_BASE_MORT) 01890 #define DFSDM1_Channel1_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM1_Channel1_BASE_MORT) 01891 #define DFSDM1_Channel2_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM1_Channel2_BASE_MORT) 01892 #define DFSDM1_Channel3_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM1_Channel3_BASE_MORT) 01893 #define DFSDM1_Filter0_MORT ((DFSDM_TypeDef *) DFSDM_Filter0_BASE) 01894 #define DFSDM1_Filter1_MORT ((DFSDM_TypeDef *) DFSDM_Filter1_BASE) 01895 #if defined(STM32F413_423xx) 01896 #define DFSDM2_Channel0_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM2_Channel0_BASE_MORT) 01897 #define DFSDM2_Channel1_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM2_Channel1_BASE_MORT) 01898 #define DFSDM2_Channel2_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM2_Channel2_BASE_MORT) 01899 #define DFSDM2_Channel3_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM2_Channel3_BASE_MORT) 01900 #define DFSDM2_Channel4_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM2_Channel4_BASE_MORT) 01901 #define DFSDM2_Channel5_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM2_Channel5_BASE_MORT) 01902 #define DFSDM2_Channel6_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM2_Channel6_BASE_MORT) 01903 #define DFSDM2_Channel7_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM2_Channel7_BASE_MORT) 01904 #define DFSDM2_Filter0_MORT ((DFSDM_Filter_TypeDef_mort *) DFSDM2_Filter0_BASE_MORT) 01905 #define DFSDM2_Filter1_MORT ((DFSDM_Filter_TypeDef_mort *) DFSDM2_Filter1_BASE_MORT) 01906 #define DFSDM2_Filter2_MORT ((DFSDM_Filter_TypeDef_mort *) DFSDM2_Filter2_BASE_MORT) 01907 #define DFSDM2_Filter3_MORT ((DFSDM_Filter_TypeDef_mort *) DFSDM2_Filter3_BASE_MORT) 01908 #endif /* STM32F413_423xx */ 01909 #endif /* STM32F412xG || STM32F413_423xx */ 01910 #define GPIOA_MORT ((GPIO_TypeDef_mort *) GPIOA_BASE_MORT) 01911 #define GPIOB_MORT ((GPIO_TypeDef_mort *) GPIOB_BASE_MORT) 01912 #define GPIOC_MORT ((GPIO_TypeDef_mort *) GPIOC_BASE_MORT) 01913 #define GPIOD_MORT ((GPIO_TypeDef_mort *) GPIOD_BASE_MORT) 01914 #define GPIOE_MORT ((GPIO_TypeDef_mort *) GPIOE_BASE_MORT) 01915 #define GPIOF_MORT ((GPIO_TypeDef_mort *) GPIOF_BASE_MORT) 01916 #define GPIOG_MORT ((GPIO_TypeDef_mort *) GPIOG_BASE_MORT) 01917 #define GPIOH_MORT ((GPIO_TypeDef_mort *) GPIOH_BASE_MORT) 01918 #define GPIOI_MORT ((GPIO_TypeDef_mort *) GPIOI_BASE_MORT) 01919 #define GPIOJ_MORT ((GPIO_TypeDef_mort *) GPIOJ_BASE_MORT) 01920 #define GPIOK_MORT ((GPIO_TypeDef_mort *) GPIOK_BASE_MORT) 01921 #define CRC_MORT ((CRC_TypeDef_mort *) CRC_BASE_MORT) 01922 #define RCC_MORT ((RCC_TypeDef_mort *) RCC_BASE_MORT) 01923 #define FLASH_MORT ((FLASH_TypeDef_mort *) FLASH_R_BASE_MORT) 01924 #define DMA1_MORT ((DMA_TypeDef_mort *) DMA1_BASE_MORT) 01925 #define DMA1_Stream0_MORT ((DMA_Stream_TypeDef_mort *) DMA1_Stream0_BASE_MORT) 01926 #define DMA1_Stream1_MORT ((DMA_Stream_TypeDef_mort *) DMA1_Stream1_BASE_MORT) 01927 #define DMA1_Stream2_MORT ((DMA_Stream_TypeDef_mort *) DMA1_Stream2_BASE_MORT) 01928 #define DMA1_Stream3_MORT ((DMA_Stream_TypeDef_mort *) DMA1_Stream3_BASE_MORT) 01929 #define DMA1_Stream4_MORT ((DMA_Stream_TypeDef_mort *) DMA1_Stream4_BASE_MORT) 01930 #define DMA1_Stream5_MORT ((DMA_Stream_TypeDef_mort *) DMA1_Stream5_BASE_MORT) 01931 #define DMA1_Stream6_MORT ((DMA_Stream_TypeDef_mort *) DMA1_Stream6_BASE_MORT) 01932 #define DMA1_Stream7_MORT ((DMA_Stream_TypeDef_mort *) DMA1_Stream7_BASE_MORT) 01933 #define DMA2_MORT ((DMA_TypeDef_mort *) DMA2_BASE_MORT) 01934 #define DMA2_Stream0_MORT ((DMA_Stream_TypeDef_mort *) DMA2_Stream0_BASE_MORT) 01935 #define DMA2_Stream1_MORT ((DMA_Stream_TypeDef_mort *) DMA2_Stream1_BASE_MORT) 01936 #define DMA2_Stream2_MORT ((DMA_Stream_TypeDef_mort *) DMA2_Stream2_BASE_MORT) 01937 #define DMA2_Stream3_MORT ((DMA_Stream_TypeDef_mort *) DMA2_Stream3_BASE_MORT) 01938 #define DMA2_Stream4_MORT ((DMA_Stream_TypeDef_mort *) DMA2_Stream4_BASE_MORT) 01939 #define DMA2_Stream5_MORT ((DMA_Stream_TypeDef_mort *) DMA2_Stream5_BASE_MORT) 01940 #define DMA2_Stream6_MORT ((DMA_Stream_TypeDef_mort *) DMA2_Stream6_BASE_MORT) 01941 #define DMA2_Stream7_MORT ((DMA_Stream_TypeDef_mort *) DMA2_Stream7_BASE_MORT) 01942 #define ETH_MORT ((ETH_TypeDef_mort *) ETH_BASE_MORT) 01943 #define DMA2D_MORT ((DMA2D_TypeDef_mort *)DMA2D_BASE_MORT) 01944 #define DCMI_MORT ((DCMI_TypeDef_mort *) DCMI_BASE_MORT) 01945 #define CRYP_MORT ((CRYP_TypeDef_mort *) CRYP_BASE_MORT) 01946 #define HASH_MORT ((HASH_TypeDef_mort *) HASH_BASE_MORT) 01947 #define HASH_DIGEST_MORT ((HASH_DIGEST_TypeDef_mort *) HASH_DIGEST_BASE_MORT) 01948 #define RNG_MORT ((RNG_TypeDef_mort *) RNG_BASE_MORT) 01949 01950 #if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) 01951 #define FSMC_Bank1_MORT ((FSMC_Bank1_TypeDef_mort *) FSMC_Bank1_R_BASE_MORT) 01952 #define FSMC_Bank1E_MORT ((FSMC_Bank1E_TypeDef_mort *) FSMC_Bank1E_R_BASE_MORT) 01953 #define FSMC_Bank2_MORT ((FSMC_Bank2_TypeDef_mort *) FSMC_Bank2_R_BASE_MORT) 01954 #define FSMC_Bank3_MORT ((FSMC_Bank3_TypeDef_mort *) FSMC_Bank3_R_BASE_MORT) 01955 #define FSMC_Bank4_MORT ((FSMC_Bank4_TypeDef_mort *) FSMC_Bank4_R_BASE_MORT) 01956 #endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */ 01957 01958 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) 01959 #define FMC_Bank1_MORT ((FMC_Bank1_TypeDef_mort *) FMC_Bank1_R_BASE_MORT) 01960 #define FMC_Bank1E_MORT ((FMC_Bank1E_TypeDef_mort *) FMC_Bank1E_R_BASE_MORT) 01961 #define FMC_Bank2_MORT ((FMC_Bank2_TypeDef_mort *) FMC_Bank2_R_BASE_MORT) 01962 #define FMC_Bank3_MORT ((FMC_Bank3_TypeDef_mort *) FMC_Bank3_R_BASE_MORT) 01963 #define FMC_Bank4_MORT ((FMC_Bank4_TypeDef_mort *) FMC_Bank4_R_BASE_MORT) 01964 #define FMC_Bank5_6_MORT ((FMC_Bank5_6_TypeDef_mort *) FMC_Bank5_6_R_BASE_MORT) 01965 #endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx_MORT || STM32F469_479xx */ 01966 01967 #define DBGMCU_MORT ((DBGMCU_TypeDef_mort *) DBGMCU_BASE_MORT) 01968 01969 /** 01970 * @} 01971 */ 01972 01973 /** @addtogroup Exported_constants 01974 * @{ 01975 */ 01976 01977 /** @addtogroup Peripheral_Registers_Bits_Definition 01978 * @{ 01979 */ 01980 01981 /******************************************************************************/ 01982 /* Peripheral Registers_Bits_Definition */ 01983 /******************************************************************************/ 01984 01985 /******************************************************************************/ 01986 /* */ 01987 /* Analog to Digital Converter */ 01988 /* */ 01989 /******************************************************************************/ 01990 /******************** Bit definition for ADC_SR register ********************/ 01991 #define ADC_SR_AWD_MORT ((uint8_t)0x01) /*!<Analog watchdog flag */ 01992 #define ADC_SR_EOC_MORT ((uint8_t)0x02) /*!<End of conversion */ 01993 #define ADC_SR_JEOC_MORT ((uint8_t)0x04) /*!<Injected channel end of conversion */ 01994 #define ADC_SR_JSTRT_MORT ((uint8_t)0x08) /*!<Injected channel Start flag */ 01995 #define ADC_SR_STRT_MORT ((uint8_t)0x10) /*!<Regular channel Start flag */ 01996 #define ADC_SR_OVR_MORT ((uint8_t)0x20) /*!<Overrun flag */ 01997 01998 /******************* Bit definition for ADC_CR1 register ********************/ 01999 #define ADC_CR1_AWDCH_MORT ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */ 02000 #define ADC_CR1_AWDCH_0_MORT ((uint32_t)0x00000001) /*!<Bit 0 */ 02001 #define ADC_CR1_AWDCH_1_MORT ((uint32_t)0x00000002) /*!<Bit 1 */ 02002 #define ADC_CR1_AWDCH_2_MORT ((uint32_t)0x00000004) /*!<Bit 2 */ 02003 #define ADC_CR1_AWDCH_3_MORT ((uint32_t)0x00000008) /*!<Bit 3 */ 02004 #define ADC_CR1_AWDCH_4_MORT ((uint32_t)0x00000010) /*!<Bit 4 */ 02005 #define ADC_CR1_EOCIE_MORT ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */ 02006 #define ADC_CR1_AWDIE_MORT ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */ 02007 #define ADC_CR1_JEOCIE_MORT ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */ 02008 #define ADC_CR1_SCAN_MORT ((uint32_t)0x00000100) /*!<Scan mode */ 02009 #define ADC_CR1_AWDSGL_MORT ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */ 02010 #define ADC_CR1_JAUTO_MORT ((uint32_t)0x00000400) /*!<Automatic injected group conversion */ 02011 #define ADC_CR1_DISCEN_MORT ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */ 02012 #define ADC_CR1_JDISCEN_MORT ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */ 02013 #define ADC_CR1_DISCNUM_MORT ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */ 02014 #define ADC_CR1_DISCNUM_0_MORT ((uint32_t)0x00002000) /*!<Bit 0 */ 02015 #define ADC_CR1_DISCNUM_1_MORT ((uint32_t)0x00004000) /*!<Bit 1 */ 02016 #define ADC_CR1_DISCNUM_2_MORT ((uint32_t)0x00008000) /*!<Bit 2 */ 02017 #define ADC_CR1_JAWDEN_MORT ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */ 02018 #define ADC_CR1_AWDEN_MORT ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */ 02019 #define ADC_CR1_RES_MORT ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */ 02020 #define ADC_CR1_RES_0_MORT ((uint32_t)0x01000000) /*!<Bit 0 */ 02021 #define ADC_CR1_RES_1_MORT ((uint32_t)0x02000000) /*!<Bit 1 */ 02022 #define ADC_CR1_OVRIE_MORT ((uint32_t)0x04000000) /*!<overrun interrupt enable */ 02023 02024 /******************* Bit definition for ADC_CR2 register ********************/ 02025 #define ADC_CR2_ADON_MORT ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */ 02026 #define ADC_CR2_CONT_MORT ((uint32_t)0x00000002) /*!<Continuous Conversion */ 02027 #define ADC_CR2_DMA_MORT ((uint32_t)0x00000100) /*!<Direct Memory access mode */ 02028 #define ADC_CR2_DDS_MORT ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC_MORT) */ 02029 #define ADC_CR2_EOCS_MORT ((uint32_t)0x00000400) /*!<End of conversion selection */ 02030 #define ADC_CR2_ALIGN_MORT ((uint32_t)0x00000800) /*!<Data Alignment */ 02031 #define ADC_CR2_JEXTSEL_MORT ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */ 02032 #define ADC_CR2_JEXTSEL_0_MORT ((uint32_t)0x00010000) /*!<Bit 0 */ 02033 #define ADC_CR2_JEXTSEL_1_MORT ((uint32_t)0x00020000) /*!<Bit 1 */ 02034 #define ADC_CR2_JEXTSEL_2_MORT ((uint32_t)0x00040000) /*!<Bit 2 */ 02035 #define ADC_CR2_JEXTSEL_3_MORT ((uint32_t)0x00080000) /*!<Bit 3 */ 02036 #define ADC_CR2_JEXTEN_MORT ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */ 02037 #define ADC_CR2_JEXTEN_0_MORT ((uint32_t)0x00100000) /*!<Bit 0 */ 02038 #define ADC_CR2_JEXTEN_1_MORT ((uint32_t)0x00200000) /*!<Bit 1 */ 02039 #define ADC_CR2_JSWSTART_MORT ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */ 02040 #define ADC_CR2_EXTSEL_MORT ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */ 02041 #define ADC_CR2_EXTSEL_0_MORT ((uint32_t)0x01000000) /*!<Bit 0 */ 02042 #define ADC_CR2_EXTSEL_1_MORT ((uint32_t)0x02000000) /*!<Bit 1 */ 02043 #define ADC_CR2_EXTSEL_2_MORT ((uint32_t)0x04000000) /*!<Bit 2 */ 02044 #define ADC_CR2_EXTSEL_3_MORT ((uint32_t)0x08000000) /*!<Bit 3 */ 02045 #define ADC_CR2_EXTEN_MORT ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */ 02046 #define ADC_CR2_EXTEN_0_MORT ((uint32_t)0x10000000) /*!<Bit 0 */ 02047 #define ADC_CR2_EXTEN_1_MORT ((uint32_t)0x20000000) /*!<Bit 1 */ 02048 #define ADC_CR2_SWSTART_MORT ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */ 02049 02050 /****************** Bit definition for ADC_SMPR1 register *******************/ 02051 #define ADC_SMPR1_SMP10_MORT ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */ 02052 #define ADC_SMPR1_SMP10_0_MORT ((uint32_t)0x00000001) /*!<Bit 0 */ 02053 #define ADC_SMPR1_SMP10_1_MORT ((uint32_t)0x00000002) /*!<Bit 1 */ 02054 #define ADC_SMPR1_SMP10_2_MORT ((uint32_t)0x00000004) /*!<Bit 2 */ 02055 #define ADC_SMPR1_SMP11_MORT ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */ 02056 #define ADC_SMPR1_SMP11_0_MORT ((uint32_t)0x00000008) /*!<Bit 0 */ 02057 #define ADC_SMPR1_SMP11_1_MORT ((uint32_t)0x00000010) /*!<Bit 1 */ 02058 #define ADC_SMPR1_SMP11_2_MORT ((uint32_t)0x00000020) /*!<Bit 2 */ 02059 #define ADC_SMPR1_SMP12_MORT ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */ 02060 #define ADC_SMPR1_SMP12_0_MORT ((uint32_t)0x00000040) /*!<Bit 0 */ 02061 #define ADC_SMPR1_SMP12_1_MORT ((uint32_t)0x00000080) /*!<Bit 1 */ 02062 #define ADC_SMPR1_SMP12_2_MORT ((uint32_t)0x00000100) /*!<Bit 2 */ 02063 #define ADC_SMPR1_SMP13_MORT ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */ 02064 #define ADC_SMPR1_SMP13_0_MORT ((uint32_t)0x00000200) /*!<Bit 0 */ 02065 #define ADC_SMPR1_SMP13_1_MORT ((uint32_t)0x00000400) /*!<Bit 1 */ 02066 #define ADC_SMPR1_SMP13_2_MORT ((uint32_t)0x00000800) /*!<Bit 2 */ 02067 #define ADC_SMPR1_SMP14_MORT ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */ 02068 #define ADC_SMPR1_SMP14_0_MORT ((uint32_t)0x00001000) /*!<Bit 0 */ 02069 #define ADC_SMPR1_SMP14_1_MORT ((uint32_t)0x00002000) /*!<Bit 1 */ 02070 #define ADC_SMPR1_SMP14_2_MORT ((uint32_t)0x00004000) /*!<Bit 2 */ 02071 #define ADC_SMPR1_SMP15_MORT ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */ 02072 #define ADC_SMPR1_SMP15_0_MORT ((uint32_t)0x00008000) /*!<Bit 0 */ 02073 #define ADC_SMPR1_SMP15_1_MORT ((uint32_t)0x00010000) /*!<Bit 1 */ 02074 #define ADC_SMPR1_SMP15_2_MORT ((uint32_t)0x00020000) /*!<Bit 2 */ 02075 #define ADC_SMPR1_SMP16_MORT ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */ 02076 #define ADC_SMPR1_SMP16_0_MORT ((uint32_t)0x00040000) /*!<Bit 0 */ 02077 #define ADC_SMPR1_SMP16_1_MORT ((uint32_t)0x00080000) /*!<Bit 1 */ 02078 #define ADC_SMPR1_SMP16_2_MORT ((uint32_t)0x00100000) /*!<Bit 2 */ 02079 #define ADC_SMPR1_SMP17_MORT ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */ 02080 #define ADC_SMPR1_SMP17_0_MORT ((uint32_t)0x00200000) /*!<Bit 0 */ 02081 #define ADC_SMPR1_SMP17_1_MORT ((uint32_t)0x00400000) /*!<Bit 1 */ 02082 #define ADC_SMPR1_SMP17_2_MORT ((uint32_t)0x00800000) /*!<Bit 2 */ 02083 #define ADC_SMPR1_SMP18_MORT ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */ 02084 #define ADC_SMPR1_SMP18_0_MORT ((uint32_t)0x01000000) /*!<Bit 0 */ 02085 #define ADC_SMPR1_SMP18_1_MORT ((uint32_t)0x02000000) /*!<Bit 1 */ 02086 #define ADC_SMPR1_SMP18_2_MORT ((uint32_t)0x04000000) /*!<Bit 2 */ 02087 02088 /****************** Bit definition for ADC_SMPR2 register *******************/ 02089 #define ADC_SMPR2_SMP0_MORT ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */ 02090 #define ADC_SMPR2_SMP0_0_MORT ((uint32_t)0x00000001) /*!<Bit 0 */ 02091 #define ADC_SMPR2_SMP0_1_MORT ((uint32_t)0x00000002) /*!<Bit 1 */ 02092 #define ADC_SMPR2_SMP0_2_MORT ((uint32_t)0x00000004) /*!<Bit 2 */ 02093 #define ADC_SMPR2_SMP1_MORT ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */ 02094 #define ADC_SMPR2_SMP1_0_MORT ((uint32_t)0x00000008) /*!<Bit 0 */ 02095 #define ADC_SMPR2_SMP1_1_MORT ((uint32_t)0x00000010) /*!<Bit 1 */ 02096 #define ADC_SMPR2_SMP1_2_MORT ((uint32_t)0x00000020) /*!<Bit 2 */ 02097 #define ADC_SMPR2_SMP2_MORT ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */ 02098 #define ADC_SMPR2_SMP2_0_MORT ((uint32_t)0x00000040) /*!<Bit 0 */ 02099 #define ADC_SMPR2_SMP2_1_MORT ((uint32_t)0x00000080) /*!<Bit 1 */ 02100 #define ADC_SMPR2_SMP2_2_MORT ((uint32_t)0x00000100) /*!<Bit 2 */ 02101 #define ADC_SMPR2_SMP3_MORT ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */ 02102 #define ADC_SMPR2_SMP3_0_MORT ((uint32_t)0x00000200) /*!<Bit 0 */ 02103 #define ADC_SMPR2_SMP3_1_MORT ((uint32_t)0x00000400) /*!<Bit 1 */ 02104 #define ADC_SMPR2_SMP3_2_MORT ((uint32_t)0x00000800) /*!<Bit 2 */ 02105 #define ADC_SMPR2_SMP4_MORT ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */ 02106 #define ADC_SMPR2_SMP4_0_MORT ((uint32_t)0x00001000) /*!<Bit 0 */ 02107 #define ADC_SMPR2_SMP4_1_MORT ((uint32_t)0x00002000) /*!<Bit 1 */ 02108 #define ADC_SMPR2_SMP4_2_MORT ((uint32_t)0x00004000) /*!<Bit 2 */ 02109 #define ADC_SMPR2_SMP5_MORT ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */ 02110 #define ADC_SMPR2_SMP5_0_MORT ((uint32_t)0x00008000) /*!<Bit 0 */ 02111 #define ADC_SMPR2_SMP5_1_MORT ((uint32_t)0x00010000) /*!<Bit 1 */ 02112 #define ADC_SMPR2_SMP5_2_MORT ((uint32_t)0x00020000) /*!<Bit 2 */ 02113 #define ADC_SMPR2_SMP6_MORT ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */ 02114 #define ADC_SMPR2_SMP6_0_MORT ((uint32_t)0x00040000) /*!<Bit 0 */ 02115 #define ADC_SMPR2_SMP6_1_MORT ((uint32_t)0x00080000) /*!<Bit 1 */ 02116 #define ADC_SMPR2_SMP6_2_MORT ((uint32_t)0x00100000) /*!<Bit 2 */ 02117 #define ADC_SMPR2_SMP7_MORT ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */ 02118 #define ADC_SMPR2_SMP7_0_MORT ((uint32_t)0x00200000) /*!<Bit 0 */ 02119 #define ADC_SMPR2_SMP7_1_MORT ((uint32_t)0x00400000) /*!<Bit 1 */ 02120 #define ADC_SMPR2_SMP7_2_MORT ((uint32_t)0x00800000) /*!<Bit 2 */ 02121 #define ADC_SMPR2_SMP8_MORT ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */ 02122 #define ADC_SMPR2_SMP8_0_MORT ((uint32_t)0x01000000) /*!<Bit 0 */ 02123 #define ADC_SMPR2_SMP8_1_MORT ((uint32_t)0x02000000) /*!<Bit 1 */ 02124 #define ADC_SMPR2_SMP8_2_MORT ((uint32_t)0x04000000) /*!<Bit 2 */ 02125 #define ADC_SMPR2_SMP9_MORT ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */ 02126 #define ADC_SMPR2_SMP9_0_MORT ((uint32_t)0x08000000) /*!<Bit 0 */ 02127 #define ADC_SMPR2_SMP9_1_MORT ((uint32_t)0x10000000) /*!<Bit 1 */ 02128 #define ADC_SMPR2_SMP9_2_MORT ((uint32_t)0x20000000) /*!<Bit 2 */ 02129 02130 /****************** Bit definition for ADC_JOFR1 register *******************/ 02131 #define ADC_JOFR1_JOFFSET1_MORT ((uint16_t)0x0FFF) /*!<Data offset for injected channel 1 */ 02132 02133 /****************** Bit definition for ADC_JOFR2 register *******************/ 02134 #define ADC_JOFR2_JOFFSET2_MORT ((uint16_t)0x0FFF) /*!<Data offset for injected channel 2 */ 02135 02136 /****************** Bit definition for ADC_JOFR3 register *******************/ 02137 #define ADC_JOFR3_JOFFSET3_MORT ((uint16_t)0x0FFF) /*!<Data offset for injected channel 3 */ 02138 02139 /****************** Bit definition for ADC_JOFR4 register *******************/ 02140 #define ADC_JOFR4_JOFFSET4_MORT ((uint16_t)0x0FFF) /*!<Data offset for injected channel 4 */ 02141 02142 /******************* Bit definition for ADC_HTR register ********************/ 02143 #define ADC_HTR_HT_MORT ((uint16_t)0x0FFF) /*!<Analog watchdog high threshold */ 02144 02145 /******************* Bit definition for ADC_LTR register ********************/ 02146 #define ADC_LTR_LT_MORT ((uint16_t)0x0FFF) /*!<Analog watchdog low threshold */ 02147 02148 /******************* Bit definition for ADC_SQR1 register *******************/ 02149 #define ADC_SQR1_SQ13_MORT ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */ 02150 #define ADC_SQR1_SQ13_0_MORT ((uint32_t)0x00000001) /*!<Bit 0 */ 02151 #define ADC_SQR1_SQ13_1_MORT ((uint32_t)0x00000002) /*!<Bit 1 */ 02152 #define ADC_SQR1_SQ13_2_MORT ((uint32_t)0x00000004) /*!<Bit 2 */ 02153 #define ADC_SQR1_SQ13_3_MORT ((uint32_t)0x00000008) /*!<Bit 3 */ 02154 #define ADC_SQR1_SQ13_4_MORT ((uint32_t)0x00000010) /*!<Bit 4 */ 02155 #define ADC_SQR1_SQ14_MORT ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */ 02156 #define ADC_SQR1_SQ14_0_MORT ((uint32_t)0x00000020) /*!<Bit 0 */ 02157 #define ADC_SQR1_SQ14_1_MORT ((uint32_t)0x00000040) /*!<Bit 1 */ 02158 #define ADC_SQR1_SQ14_2_MORT ((uint32_t)0x00000080) /*!<Bit 2 */ 02159 #define ADC_SQR1_SQ14_3_MORT ((uint32_t)0x00000100) /*!<Bit 3 */ 02160 #define ADC_SQR1_SQ14_4_MORT ((uint32_t)0x00000200) /*!<Bit 4 */ 02161 #define ADC_SQR1_SQ15_MORT ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */ 02162 #define ADC_SQR1_SQ15_0_MORT ((uint32_t)0x00000400) /*!<Bit 0 */ 02163 #define ADC_SQR1_SQ15_1_MORT ((uint32_t)0x00000800) /*!<Bit 1 */ 02164 #define ADC_SQR1_SQ15_2_MORT ((uint32_t)0x00001000) /*!<Bit 2 */ 02165 #define ADC_SQR1_SQ15_3_MORT ((uint32_t)0x00002000) /*!<Bit 3 */ 02166 #define ADC_SQR1_SQ15_4_MORT ((uint32_t)0x00004000) /*!<Bit 4 */ 02167 #define ADC_SQR1_SQ16_MORT ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */ 02168 #define ADC_SQR1_SQ16_0_MORT ((uint32_t)0x00008000) /*!<Bit 0 */ 02169 #define ADC_SQR1_SQ16_1_MORT ((uint32_t)0x00010000) /*!<Bit 1 */ 02170 #define ADC_SQR1_SQ16_2_MORT ((uint32_t)0x00020000) /*!<Bit 2 */ 02171 #define ADC_SQR1_SQ16_3_MORT ((uint32_t)0x00040000) /*!<Bit 3 */ 02172 #define ADC_SQR1_SQ16_4_MORT ((uint32_t)0x00080000) /*!<Bit 4 */ 02173 #define ADC_SQR1_L_MORT ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */ 02174 #define ADC_SQR1_L__0_MORT ((uint32_t)0x00100000) /*!<Bit 0 */ 02175 #define ADC_SQR1_L__1_MORT ((uint32_t)0x00200000) /*!<Bit 1 */ 02176 #define ADC_SQR1_L__2_MORT ((uint32_t)0x00400000) /*!<Bit 2 */ 02177 #define ADC_SQR1_L__3_MORT ((uint32_t)0x00800000) /*!<Bit 3 */ 02178 02179 /******************* Bit definition for ADC_SQR2 register *******************/ 02180 #define ADC_SQR2_SQ7_MORT ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */ 02181 #define ADC_SQR2_SQ7_0_MORT ((uint32_t)0x00000001) /*!<Bit 0 */ 02182 #define ADC_SQR2_SQ7_1_MORT ((uint32_t)0x00000002) /*!<Bit 1 */ 02183 #define ADC_SQR2_SQ7_2_MORT ((uint32_t)0x00000004) /*!<Bit 2 */ 02184 #define ADC_SQR2_SQ7_3_MORT ((uint32_t)0x00000008) /*!<Bit 3 */ 02185 #define ADC_SQR2_SQ7_4_MORT ((uint32_t)0x00000010) /*!<Bit 4 */ 02186 #define ADC_SQR2_SQ8_MORT ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */ 02187 #define ADC_SQR2_SQ8_0_MORT ((uint32_t)0x00000020) /*!<Bit 0 */ 02188 #define ADC_SQR2_SQ8_1_MORT ((uint32_t)0x00000040) /*!<Bit 1 */ 02189 #define ADC_SQR2_SQ8_2_MORT ((uint32_t)0x00000080) /*!<Bit 2 */ 02190 #define ADC_SQR2_SQ8_3_MORT ((uint32_t)0x00000100) /*!<Bit 3 */ 02191 #define ADC_SQR2_SQ8_4_MORT ((uint32_t)0x00000200) /*!<Bit 4 */ 02192 #define ADC_SQR2_SQ9_MORT ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */ 02193 #define ADC_SQR2_SQ9_0_MORT ((uint32_t)0x00000400) /*!<Bit 0 */ 02194 #define ADC_SQR2_SQ9_1_MORT ((uint32_t)0x00000800) /*!<Bit 1 */ 02195 #define ADC_SQR2_SQ9_2_MORT ((uint32_t)0x00001000) /*!<Bit 2 */ 02196 #define ADC_SQR2_SQ9_3_MORT ((uint32_t)0x00002000) /*!<Bit 3 */ 02197 #define ADC_SQR2_SQ9_4_MORT ((uint32_t)0x00004000) /*!<Bit 4 */ 02198 #define ADC_SQR2_SQ10_MORT ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */ 02199 #define ADC_SQR2_SQ10_0_MORT ((uint32_t)0x00008000) /*!<Bit 0 */ 02200 #define ADC_SQR2_SQ10_1_MORT ((uint32_t)0x00010000) /*!<Bit 1 */ 02201 #define ADC_SQR2_SQ10_2_MORT ((uint32_t)0x00020000) /*!<Bit 2 */ 02202 #define ADC_SQR2_SQ10_3_MORT ((uint32_t)0x00040000) /*!<Bit 3 */ 02203 #define ADC_SQR2_SQ10_4_MORT ((uint32_t)0x00080000) /*!<Bit 4 */ 02204 #define ADC_SQR2_SQ11_MORT ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */ 02205 #define ADC_SQR2_SQ11_0_MORT ((uint32_t)0x00100000) /*!<Bit 0 */ 02206 #define ADC_SQR2_SQ11_1_MORT ((uint32_t)0x00200000) /*!<Bit 1 */ 02207 #define ADC_SQR2_SQ11_2_MORT ((uint32_t)0x00400000) /*!<Bit 2 */ 02208 #define ADC_SQR2_SQ11_3_MORT ((uint32_t)0x00800000) /*!<Bit 3 */ 02209 #define ADC_SQR2_SQ11_4_MORT ((uint32_t)0x01000000) /*!<Bit 4 */ 02210 #define ADC_SQR2_SQ12_MORT ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */ 02211 #define ADC_SQR2_SQ12_0_MORT ((uint32_t)0x02000000) /*!<Bit 0 */ 02212 #define ADC_SQR2_SQ12_1_MORT ((uint32_t)0x04000000) /*!<Bit 1 */ 02213 #define ADC_SQR2_SQ12_2_MORT ((uint32_t)0x08000000) /*!<Bit 2 */ 02214 #define ADC_SQR2_SQ12_3_MORT ((uint32_t)0x10000000) /*!<Bit 3 */ 02215 #define ADC_SQR2_SQ12_4_MORT ((uint32_t)0x20000000) /*!<Bit 4 */ 02216 02217 /******************* Bit definition for ADC_SQR3 register *******************/ 02218 #define ADC_SQR3_SQ1_MORT ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */ 02219 #define ADC_SQR3_SQ1_0_MORT ((uint32_t)0x00000001) /*!<Bit 0 */ 02220 #define ADC_SQR3_SQ1_1_MORT ((uint32_t)0x00000002) /*!<Bit 1 */ 02221 #define ADC_SQR3_SQ1_2_MORT ((uint32_t)0x00000004) /*!<Bit 2 */ 02222 #define ADC_SQR3_SQ1_3_MORT ((uint32_t)0x00000008) /*!<Bit 3 */ 02223 #define ADC_SQR3_SQ1_4_MORT ((uint32_t)0x00000010) /*!<Bit 4 */ 02224 #define ADC_SQR3_SQ2_MORT ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */ 02225 #define ADC_SQR3_SQ2_0_MORT ((uint32_t)0x00000020) /*!<Bit 0 */ 02226 #define ADC_SQR3_SQ2_1_MORT ((uint32_t)0x00000040) /*!<Bit 1 */ 02227 #define ADC_SQR3_SQ2_2_MORT ((uint32_t)0x00000080) /*!<Bit 2 */ 02228 #define ADC_SQR3_SQ2_3_MORT ((uint32_t)0x00000100) /*!<Bit 3 */ 02229 #define ADC_SQR3_SQ2_4_MORT ((uint32_t)0x00000200) /*!<Bit 4 */ 02230 #define ADC_SQR3_SQ3_MORT ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */ 02231 #define ADC_SQR3_SQ3_0_MORT ((uint32_t)0x00000400) /*!<Bit 0 */ 02232 #define ADC_SQR3_SQ3_1_MORT ((uint32_t)0x00000800) /*!<Bit 1 */ 02233 #define ADC_SQR3_SQ3_2_MORT ((uint32_t)0x00001000) /*!<Bit 2 */ 02234 #define ADC_SQR3_SQ3_3_MORT ((uint32_t)0x00002000) /*!<Bit 3 */ 02235 #define ADC_SQR3_SQ3_4_MORT ((uint32_t)0x00004000) /*!<Bit 4 */ 02236 #define ADC_SQR3_SQ4_MORT ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */ 02237 #define ADC_SQR3_SQ4_0_MORT ((uint32_t)0x00008000) /*!<Bit 0 */ 02238 #define ADC_SQR3_SQ4_1_MORT ((uint32_t)0x00010000) /*!<Bit 1 */ 02239 #define ADC_SQR3_SQ4_2_MORT ((uint32_t)0x00020000) /*!<Bit 2 */ 02240 #define ADC_SQR3_SQ4_3_MORT ((uint32_t)0x00040000) /*!<Bit 3 */ 02241 #define ADC_SQR3_SQ4_4_MORT ((uint32_t)0x00080000) /*!<Bit 4 */ 02242 #define ADC_SQR3_SQ5_MORT ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */ 02243 #define ADC_SQR3_SQ5_0_MORT ((uint32_t)0x00100000) /*!<Bit 0 */ 02244 #define ADC_SQR3_SQ5_1_MORT ((uint32_t)0x00200000) /*!<Bit 1 */ 02245 #define ADC_SQR3_SQ5_2_MORT ((uint32_t)0x00400000) /*!<Bit 2 */ 02246 #define ADC_SQR3_SQ5_3_MORT ((uint32_t)0x00800000) /*!<Bit 3 */ 02247 #define ADC_SQR3_SQ5_4_MORT ((uint32_t)0x01000000) /*!<Bit 4 */ 02248 #define ADC_SQR3_SQ6_MORT ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */ 02249 #define ADC_SQR3_SQ6_0_MORT ((uint32_t)0x02000000) /*!<Bit 0 */ 02250 #define ADC_SQR3_SQ6_1_MORT ((uint32_t)0x04000000) /*!<Bit 1 */ 02251 #define ADC_SQR3_SQ6_2_MORT ((uint32_t)0x08000000) /*!<Bit 2 */ 02252 #define ADC_SQR3_SQ6_3_MORT ((uint32_t)0x10000000) /*!<Bit 3 */ 02253 #define ADC_SQR3_SQ6_4_MORT ((uint32_t)0x20000000) /*!<Bit 4 */ 02254 02255 /******************* Bit definition for ADC_JSQR register *******************/ 02256 #define ADC_JSQR_JSQ1_MORT ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */ 02257 #define ADC_JSQR_JSQ1_0_MORT ((uint32_t)0x00000001) /*!<Bit 0 */ 02258 #define ADC_JSQR_JSQ1_1_MORT ((uint32_t)0x00000002) /*!<Bit 1 */ 02259 #define ADC_JSQR_JSQ1_2_MORT ((uint32_t)0x00000004) /*!<Bit 2 */ 02260 #define ADC_JSQR_JSQ1_3_MORT ((uint32_t)0x00000008) /*!<Bit 3 */ 02261 #define ADC_JSQR_JSQ1_4_MORT ((uint32_t)0x00000010) /*!<Bit 4 */ 02262 #define ADC_JSQR_JSQ2_MORT ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */ 02263 #define ADC_JSQR_JSQ2_0_MORT ((uint32_t)0x00000020) /*!<Bit 0 */ 02264 #define ADC_JSQR_JSQ2_1_MORT ((uint32_t)0x00000040) /*!<Bit 1 */ 02265 #define ADC_JSQR_JSQ2_2_MORT ((uint32_t)0x00000080) /*!<Bit 2 */ 02266 #define ADC_JSQR_JSQ2_3_MORT ((uint32_t)0x00000100) /*!<Bit 3 */ 02267 #define ADC_JSQR_JSQ2_4_MORT ((uint32_t)0x00000200) /*!<Bit 4 */ 02268 #define ADC_JSQR_JSQ3_MORT ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */ 02269 #define ADC_JSQR_JSQ3_0_MORT ((uint32_t)0x00000400) /*!<Bit 0 */ 02270 #define ADC_JSQR_JSQ3_1_MORT ((uint32_t)0x00000800) /*!<Bit 1 */ 02271 #define ADC_JSQR_JSQ3_2_MORT ((uint32_t)0x00001000) /*!<Bit 2 */ 02272 #define ADC_JSQR_JSQ3_3_MORT ((uint32_t)0x00002000) /*!<Bit 3 */ 02273 #define ADC_JSQR_JSQ3_4_MORT ((uint32_t)0x00004000) /*!<Bit 4 */ 02274 #define ADC_JSQR_JSQ4_MORT ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */ 02275 #define ADC_JSQR_JSQ4_0_MORT ((uint32_t)0x00008000) /*!<Bit 0 */ 02276 #define ADC_JSQR_JSQ4_1_MORT ((uint32_t)0x00010000) /*!<Bit 1 */ 02277 #define ADC_JSQR_JSQ4_2_MORT ((uint32_t)0x00020000) /*!<Bit 2 */ 02278 #define ADC_JSQR_JSQ4_3_MORT ((uint32_t)0x00040000) /*!<Bit 3 */ 02279 #define ADC_JSQR_JSQ4_4_MORT ((uint32_t)0x00080000) /*!<Bit 4 */ 02280 #define ADC_JSQR_JL_MORT ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */ 02281 #define ADC_JSQR_JL_0_MORT ((uint32_t)0x00100000) /*!<Bit 0 */ 02282 #define ADC_JSQR_JL_1_MORT ((uint32_t)0x00200000) /*!<Bit 1 */ 02283 02284 /******************* Bit definition for ADC_JDR1 register *******************/ 02285 #define ADC_JDR1_JDATA_MORT ((uint16_t)0xFFFF) /*!<Injected data */ 02286 02287 /******************* Bit definition for ADC_JDR2 register *******************/ 02288 #define ADC_JDR2_JDATA_MORT ((uint16_t)0xFFFF) /*!<Injected data */ 02289 02290 /******************* Bit definition for ADC_JDR3 register *******************/ 02291 #define ADC_JDR3_JDATA_MORT ((uint16_t)0xFFFF) /*!<Injected data */ 02292 02293 /******************* Bit definition for ADC_JDR4 register *******************/ 02294 #define ADC_JDR4_JDATA_MORT ((uint16_t)0xFFFF) /*!<Injected data */ 02295 02296 /******************** Bit definition for ADC_DR register ********************/ 02297 #define ADC_DR_DATA_MORT ((uint32_t)0x0000FFFF) /*!<Regular data */ 02298 #define ADC_DR_ADC2DATA_MORT ((uint32_t)0xFFFF0000) /*!<ADC2_MORT data */ 02299 02300 /******************* Bit definition for ADC_CSR register ********************/ 02301 #define ADC_CSR_AWD1_MORT ((uint32_t)0x00000001) /*!<ADC1_MORT Analog watchdog flag */ 02302 #define ADC_CSR_EOC1_MORT ((uint32_t)0x00000002) /*!<ADC1_MORT End of conversion */ 02303 #define ADC_CSR_JEOC1_MORT ((uint32_t)0x00000004) /*!<ADC1_MORT Injected channel end of conversion */ 02304 #define ADC_CSR_JSTRT1_MORT ((uint32_t)0x00000008) /*!<ADC1_MORT Injected channel Start flag */ 02305 #define ADC_CSR_STRT1_MORT ((uint32_t)0x00000010) /*!<ADC1_MORT Regular channel Start flag */ 02306 #define ADC_CSR_OVR1_MORT ((uint32_t)0x00000020) /*!<ADC1_MORT DMA overrun flag */ 02307 #define ADC_CSR_AWD2_MORT ((uint32_t)0x00000100) /*!<ADC2_MORT Analog watchdog flag */ 02308 #define ADC_CSR_EOC2_MORT ((uint32_t)0x00000200) /*!<ADC2_MORT End of conversion */ 02309 #define ADC_CSR_JEOC2_MORT ((uint32_t)0x00000400) /*!<ADC2_MORT Injected channel end of conversion */ 02310 #define ADC_CSR_JSTRT2_MORT ((uint32_t)0x00000800) /*!<ADC2_MORT Injected channel Start flag */ 02311 #define ADC_CSR_STRT2_MORT ((uint32_t)0x00001000) /*!<ADC2_MORT Regular channel Start flag */ 02312 #define ADC_CSR_OVR2_MORT ((uint32_t)0x00002000) /*!<ADC2_MORT DMA overrun flag */ 02313 #define ADC_CSR_AWD3_MORT ((uint32_t)0x00010000) /*!<ADC3_MORT Analog watchdog flag */ 02314 #define ADC_CSR_EOC3_MORT ((uint32_t)0x00020000) /*!<ADC3_MORT End of conversion */ 02315 #define ADC_CSR_JEOC3_MORT ((uint32_t)0x00040000) /*!<ADC3_MORT Injected channel end of conversion */ 02316 #define ADC_CSR_JSTRT3_MORT ((uint32_t)0x00080000) /*!<ADC3_MORT Injected channel Start flag */ 02317 #define ADC_CSR_STRT3_MORT ((uint32_t)0x00100000) /*!<ADC3_MORT Regular channel Start flag */ 02318 #define ADC_CSR_OVR3_MORT ((uint32_t)0x00200000) /*!<ADC3_MORT DMA overrun flag */ 02319 02320 /* Legacy defines */ 02321 #define ADC_CSR_DOVR1_MORT ADC_CSR_OVR1_MORT 02322 #define ADC_CSR_DOVR2_MORT ADC_CSR_OVR2_MORT 02323 #define ADC_CSR_DOVR3_MORT ADC_CSR_OVR3_MORT 02324 02325 /******************* Bit definition for ADC_CCR register ********************/ 02326 #define ADC_CCR_MULTI_MORT ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC_MORT mode selection) */ 02327 #define ADC_CCR_MULTI_0_MORT ((uint32_t)0x00000001) /*!<Bit 0 */ 02328 #define ADC_CCR_MULTI_1_MORT ((uint32_t)0x00000002) /*!<Bit 1 */ 02329 #define ADC_CCR_MULTI_2_MORT ((uint32_t)0x00000004) /*!<Bit 2 */ 02330 #define ADC_CCR_MULTI_3_MORT ((uint32_t)0x00000008) /*!<Bit 3 */ 02331 #define ADC_CCR_MULTI_4_MORT ((uint32_t)0x00000010) /*!<Bit 4 */ 02332 #define ADC_CCR_DELAY_MORT ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */ 02333 #define ADC_CCR_DELAY_0_MORT ((uint32_t)0x00000100) /*!<Bit 0 */ 02334 #define ADC_CCR_DELAY_1_MORT ((uint32_t)0x00000200) /*!<Bit 1 */ 02335 #define ADC_CCR_DELAY_2_MORT ((uint32_t)0x00000400) /*!<Bit 2 */ 02336 #define ADC_CCR_DELAY_3_MORT ((uint32_t)0x00000800) /*!<Bit 3 */ 02337 #define ADC_CCR_DDS_MORT ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC_MORT mode) */ 02338 #define ADC_CCR_DMA_MORT ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */ 02339 #define ADC_CCR_DMA_0_MORT ((uint32_t)0x00004000) /*!<Bit 0 */ 02340 #define ADC_CCR_DMA_1_MORT ((uint32_t)0x00008000) /*!<Bit 1 */ 02341 #define ADC_CCR_ADCPRE_MORT ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC_MORT prescaler) */ 02342 #define ADC_CCR_ADCPRE_0_MORT ((uint32_t)0x00010000) /*!<Bit 0 */ 02343 #define ADC_CCR_ADCPRE_1_MORT ((uint32_t)0x00020000) /*!<Bit 1 */ 02344 #define ADC_CCR_VBATE_MORT ((uint32_t)0x00400000) /*!<VBAT Enable */ 02345 #define ADC_CCR_TSVREFE_MORT ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */ 02346 02347 /******************* Bit definition for ADC_CDR register ********************/ 02348 #define ADC_CDR_DATA1_MORT ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */ 02349 #define ADC_CDR_DATA2_MORT ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */ 02350 02351 /******************************************************************************/ 02352 /* */ 02353 /* Controller Area Network */ 02354 /* */ 02355 /******************************************************************************/ 02356 /*!<CAN control and status registers */ 02357 /******************* Bit definition for CAN_MCR register ********************/ 02358 02359 02360 /******************* Bit definition for CAN_MSR register ********************/ 02361 02362 02363 /******************* Bit definition for CAN_TSR register ********************/ 02364 02365 02366 /******************* Bit definition for CAN_RF0R register *******************/ 02367 02368 02369 /******************* Bit definition for CAN_RF1R register *******************/ 02370 02371 02372 /******************** Bit definition for CAN_IER register *******************/ 02373 02374 02375 /******************** Bit definition for CAN_ESR register *******************/ 02376 02377 /******************* Bit definition for CAN_BTR register ********************/ 02378 02379 02380 /*!<Mailbox registers */ 02381 /****************** Bit definition for CAN_TI0R register ********************/ 02382 02383 02384 /****************** Bit definition for CAN_TDT0R register *******************/ 02385 02386 /****************** Bit definition for CAN_TDL0R register *******************/ 02387 02388 02389 /****************** Bit definition for CAN_TDH0R register *******************/ 02390 02391 /******************* Bit definition for CAN_TI1R register *******************/ 02392 02393 02394 /******************* Bit definition for CAN_TDT1R register ******************/ 02395 02396 02397 /******************* Bit definition for CAN_TDL1R register ******************/ 02398 02399 02400 /******************* Bit definition for CAN_TDH1R register ******************/ 02401 02402 02403 /******************* Bit definition for CAN_TI2R register *******************/ 02404 02405 /******************* Bit definition for CAN_TDT2R register ******************/ 02406 02407 02408 /******************* Bit definition for CAN_TDL2R register ******************/ 02409 02410 02411 /******************* Bit definition for CAN_TDH2R register ******************/ 02412 02413 02414 /******************* Bit definition for CAN_RI0R register *******************/ 02415 02416 02417 /******************* Bit definition for CAN_RDT0R register ******************/ 02418 02419 02420 /******************* Bit definition for CAN_RDL0R register ******************/ 02421 02422 02423 /******************* Bit definition for CAN_RDH0R register ******************/ 02424 02425 02426 /******************* Bit definition for CAN_RI1R register *******************/ 02427 02428 02429 /******************* Bit definition for CAN_RDT1R register ******************/ 02430 02431 02432 /******************* Bit definition for CAN_RDL1R register ******************/ 02433 02434 02435 /******************* Bit definition for CAN_RDH1R register ******************/ 02436 02437 02438 /*!<CAN filter registers */ 02439 /******************* Bit definition for CAN_FMR register ********************/ 02440 02441 02442 /******************* Bit definition for CAN_FM1R register *******************/ 02443 02444 02445 /******************* Bit definition for CAN_FS1R register *******************/ 02446 02447 02448 /****************** Bit definition for CAN_FFA1R register *******************/ 02449 02450 02451 /******************* Bit definition for CAN_FA1R register *******************/ 02452 02453 02454 /******************* Bit definition for CAN_F0R1 register *******************/ 02455 02456 02457 /******************* Bit definition for CAN_F1R1 register *******************/ 02458 02459 02460 /******************* Bit definition for CAN_F2R1 register *******************/ 02461 02462 02463 /******************* Bit definition for CAN_F3R1 register *******************/ 02464 02465 02466 /******************* Bit definition for CAN_F4R1 register *******************/ 02467 02468 02469 /******************* Bit definition for CAN_F5R1 register *******************/ 02470 02471 02472 /******************* Bit definition for CAN_F6R1 register *******************/ 02473 02474 02475 /******************* Bit definition for CAN_F7R1 register *******************/ 02476 02477 02478 /******************* Bit definition for CAN_F8R1 register *******************/ 02479 02480 02481 /******************* Bit definition for CAN_F9R1 register *******************/ 02482 02483 02484 /******************* Bit definition for CAN_F10R1 register ******************/ 02485 02486 /******************* Bit definition for CAN_F11R1 register ******************/ 02487 02488 02489 /******************* Bit definition for CAN_F12R1 register ******************/ 02490 02491 02492 /******************* Bit definition for CAN_F13R1 register ******************/ 02493 02494 02495 /******************* Bit definition for CAN_F0R2 register *******************/ 02496 02497 02498 /******************* Bit definition for CAN_F1R2 register *******************/ 02499 02500 02501 /******************* Bit definition for CAN_F2R2 register *******************/ 02502 02503 02504 /******************* Bit definition for CAN_F3R2 register *******************/ 02505 02506 /******************* Bit definition for CAN_F4R2 register *******************/ 02507 02508 02509 /******************* Bit definition for CAN_F5R2 register *******************/ 02510 02511 /******************* Bit definition for CAN_F6R2 register *******************/ 02512 02513 02514 /******************* Bit definition for CAN_F7R2 register *******************/ 02515 02516 02517 /******************* Bit definition for CAN_F8R2 register *******************/ 02518 02519 02520 /******************* Bit definition for CAN_F9R2 register *******************/ 02521 02522 /******************* Bit definition for CAN_F10R2 register ******************/ 02523 02524 /******************* Bit definition for CAN_F11R2 register ******************/ 02525 02526 02527 /******************* Bit definition for CAN_F12R2 register ******************/ 02528 02529 02530 /******************* Bit definition for CAN_F13R2 register ******************/ 02531 02532 02533 02534 #if defined(STM32F446xx_MORT) 02535 /******************************************************************************/ 02536 /* */ 02537 /* HDMI-CEC_MORT (CEC_MORT) */ 02538 /* */ 02539 /******************************************************************************/ 02540 02541 /******************* Bit definition for CEC_CR register *********************/ 02542 #define CEC_CR_CECEN_MORT ((uint32_t)0x00000001) /*!< CEC_MORT Enable */ 02543 #define CEC_CR_TXSOM_MORT ((uint32_t)0x00000002) /*!< CEC_MORT Tx Start Of Message */ 02544 #define CEC_CR_TXEOM_MORT ((uint32_t)0x00000004) /*!< CEC_MORT Tx End Of Message */ 02545 02546 /******************* Bit definition for CEC_CFGR register *******************/ 02547 #define CEC_CFGR_SFT_MORT ((uint32_t)0x00000007) /*!< CEC_MORT Signal Free Time */ 02548 #define CEC_CFGR_RXTOL_MORT ((uint32_t)0x00000008) /*!< CEC_MORT Tolerance */ 02549 #define CEC_CFGR_BRESTP_MORT ((uint32_t)0x00000010) /*!< CEC_MORT Rx Stop */ 02550 #define CEC_CFGR_BREGEN_MORT ((uint32_t)0x00000020) /*!< CEC_MORT Bit Rising Error generation */ 02551 #define CEC_CFGR_LREGEN_MORT ((uint32_t)0x00000040) /*!< CEC_MORT Long Period Error generation */ 02552 #define CEC_CFGR_SFTOPT_MORT ((uint32_t)0x00000100) /*!< CEC_MORT Signal Free Time optional */ 02553 #define CEC_CFGR_BRDNOGEN_MORT ((uint32_t)0x00000080) /*!< CEC_MORT Broadcast No error generation */ 02554 #define CEC_CFGR_OAR_MORT ((uint32_t)0x7FFF0000) /*!< CEC_MORT Own Address */ 02555 #define CEC_CFGR_LSTN_MORT ((uint32_t)0x80000000) /*!< CEC_MORT Listen mode */ 02556 02557 /******************* Bit definition for CEC_TXDR register *******************/ 02558 #define CEC_TXDR_TXD_MORT ((uint32_t)0x000000FF) /*!< CEC_MORT Tx Data */ 02559 02560 /******************* Bit definition for CEC_RXDR register *******************/ 02561 #define CEC_TXDR_RXD_MORT ((uint32_t)0x000000FF) /*!< CEC_MORT Rx Data */ 02562 02563 /******************* Bit definition for CEC_ISR register ********************/ 02564 #define CEC_ISR_RXBR_MORT ((uint32_t)0x00000001) /*!< CEC_MORT Rx-Byte Received */ 02565 #define CEC_ISR_RXEND_MORT ((uint32_t)0x00000002) /*!< CEC_MORT End Of Reception */ 02566 #define CEC_ISR_RXOVR_MORT ((uint32_t)0x00000004) /*!< CEC_MORT Rx-Overrun */ 02567 #define CEC_ISR_BRE_MORT ((uint32_t)0x00000008) /*!< CEC_MORT Rx Bit Rising Error */ 02568 #define CEC_ISR_SBPE_MORT ((uint32_t)0x00000010) /*!< CEC_MORT Rx Short Bit period Error */ 02569 #define CEC_ISR_LBPE_MORT ((uint32_t)0x00000020) /*!< CEC_MORT Rx Long Bit period Error */ 02570 #define CEC_ISR_RXACKE_MORT ((uint32_t)0x00000040) /*!< CEC_MORT Rx Missing Acknowledge */ 02571 #define CEC_ISR_ARBLST_MORT ((uint32_t)0x00000080) /*!< CEC_MORT Arbitration Lost */ 02572 #define CEC_ISR_TXBR_MORT ((uint32_t)0x00000100) /*!< CEC_MORT Tx Byte Request */ 02573 #define CEC_ISR_TXEND_MORT ((uint32_t)0x00000200) /*!< CEC_MORT End of Transmission */ 02574 #define CEC_ISR_TXUDR_MORT ((uint32_t)0x00000400) /*!< CEC_MORT Tx-Buffer Underrun */ 02575 #define CEC_ISR_TXERR_MORT ((uint32_t)0x00000800) /*!< CEC_MORT Tx-Error */ 02576 #define CEC_ISR_TXACKE_MORT ((uint32_t)0x00001000) /*!< CEC_MORT Tx Missing Acknowledge */ 02577 02578 /******************* Bit definition for CEC_IER register ********************/ 02579 #define CEC_IER_RXBRIE_MORT ((uint32_t)0x00000001) /*!< CEC_MORT Rx-Byte Received IT Enable */ 02580 #define CEC_IER_RXENDIE_MORT ((uint32_t)0x00000002) /*!< CEC_MORT End Of Reception IT Enable */ 02581 #define CEC_IER_RXOVRIE_MORT ((uint32_t)0x00000004) /*!< CEC_MORT Rx-Overrun IT Enable */ 02582 #define CEC_IER_BREIEIE_MORT ((uint32_t)0x00000008) /*!< CEC_MORT Rx Bit Rising Error IT Enable */ 02583 #define CEC_IER_SBPEIE_MORT ((uint32_t)0x00000010) /*!< CEC_MORT Rx Short Bit period Error IT Enable */ 02584 #define CEC_IER_LBPEIE_MORT ((uint32_t)0x00000020) /*!< CEC_MORT Rx Long Bit period Error IT Enable */ 02585 #define CEC_IER_RXACKEIE_MORT ((uint32_t)0x00000040) /*!< CEC_MORT Rx Missing Acknowledge IT Enable */ 02586 #define CEC_IER_ARBLSTIE_MORT ((uint32_t)0x00000080) /*!< CEC_MORT Arbitration Lost IT Enable */ 02587 #define CEC_IER_TXBRIE_MORT ((uint32_t)0x00000100) /*!< CEC_MORT Tx Byte Request IT Enable */ 02588 #define CEC_IER_TXENDIE_MORT ((uint32_t)0x00000200) /*!< CEC_MORT End of Transmission IT Enable */ 02589 #define CEC_IER_TXUDRIE_MORT ((uint32_t)0x00000400) /*!< CEC_MORT Tx-Buffer Underrun IT Enable */ 02590 #define CEC_IER_TXERRIE_MORT ((uint32_t)0x00000800) /*!< CEC_MORT Tx-Error IT Enable */ 02591 #define CEC_IER_TXACKEIE_MORT ((uint32_t)0x00001000) /*!< CEC_MORT Tx Missing Acknowledge IT Enable */ 02592 #endif /* STM32F446xx_MORT */ 02593 02594 /******************************************************************************/ 02595 /* */ 02596 /* CRC_MORT calculation unit */ 02597 /* */ 02598 /******************************************************************************/ 02599 /******************* Bit definition for CRC_DR register *********************/ 02600 #define CRC_DR_DR_MORT ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ 02601 02602 02603 /******************* Bit definition for CRC_IDR register ********************/ 02604 #define CRC_IDR_IDR_MORT ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ 02605 02606 02607 /******************** Bit definition for CRC_CR register ********************/ 02608 #define CRC_CR_RESET_MORT ((uint8_t)0x01) /*!< RESET bit */ 02609 02610 /******************************************************************************/ 02611 /* */ 02612 /* Crypto Processor */ 02613 /* */ 02614 /******************************************************************************/ 02615 /******************* Bits definition for CRYP_CR register ********************/ 02616 02617 02618 /****************** Bits definition for CRYP_SR register *********************/ 02619 02620 /****************** Bits definition for CRYP_DMACR register ******************/ 02621 02622 /***************** Bits definition for CRYP_IMSCR register ******************/ 02623 02624 /****************** Bits definition for CRYP_RISR register *******************/ 02625 02626 /****************** Bits definition for CRYP_MISR register *******************/ 02627 02628 /******************************************************************************/ 02629 /* */ 02630 /* Digital to Analog Converter */ 02631 /* */ 02632 /******************************************************************************/ 02633 /******************** Bit definition for DAC_CR register ********************/ 02634 #define DAC_CR_EN1_MORT ((uint32_t)0x00000001) /*!<DAC_MORT channel1 enable */ 02635 #define DAC_CR_BOFF1_MORT ((uint32_t)0x00000002) /*!<DAC_MORT channel1 output buffer disable */ 02636 #define DAC_CR_TEN1_MORT ((uint32_t)0x00000004) /*!<DAC_MORT channel1 Trigger enable */ 02637 02638 #define DAC_CR_TSEL1_MORT ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC_MORT channel1 Trigger selection) */ 02639 #define DAC_CR_TSEL1_0_MORT ((uint32_t)0x00000008) /*!<Bit 0 */ 02640 #define DAC_CR_TSEL1_1_MORT ((uint32_t)0x00000010) /*!<Bit 1 */ 02641 #define DAC_CR_TSEL1_2_MORT ((uint32_t)0x00000020) /*!<Bit 2 */ 02642 02643 #define DAC_CR_WAVE1_MORT ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC_MORT channel1 noise/triangle wave generation enable) */ 02644 #define DAC_CR_WAVE1_0_MORT ((uint32_t)0x00000040) /*!<Bit 0 */ 02645 #define DAC_CR_WAVE1_1_MORT ((uint32_t)0x00000080) /*!<Bit 1 */ 02646 02647 #define DAC_CR_MAMP1_MORT ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC_MORT channel1 Mask/Amplitude selector) */ 02648 #define DAC_CR_MAMP1_0_MORT ((uint32_t)0x00000100) /*!<Bit 0 */ 02649 #define DAC_CR_MAMP1_1_MORT ((uint32_t)0x00000200) /*!<Bit 1 */ 02650 #define DAC_CR_MAMP1_2_MORT ((uint32_t)0x00000400) /*!<Bit 2 */ 02651 #define DAC_CR_MAMP1_3_MORT ((uint32_t)0x00000800) /*!<Bit 3 */ 02652 02653 #define DAC_CR_DMAEN1_MORT ((uint32_t)0x00001000) /*!<DAC_MORT channel1 DMA enable */ 02654 #define DAC_CR_DMAUDRIE1_MORT ((uint32_t)0x00002000) /*!<DAC_MORT channel1 DMA underrun interrupt enable*/ 02655 #define DAC_CR_EN2_MORT ((uint32_t)0x00010000) /*!<DAC_MORT channel2 enable */ 02656 #define DAC_CR_BOFF2_MORT ((uint32_t)0x00020000) /*!<DAC_MORT channel2 output buffer disable */ 02657 #define DAC_CR_TEN2_MORT ((uint32_t)0x00040000) /*!<DAC_MORT channel2 Trigger enable */ 02658 02659 #define DAC_CR_TSEL2_MORT ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC_MORT channel2 Trigger selection) */ 02660 #define DAC_CR_TSEL2_0_MORT ((uint32_t)0x00080000) /*!<Bit 0 */ 02661 #define DAC_CR_TSEL2_1_MORT ((uint32_t)0x00100000) /*!<Bit 1 */ 02662 #define DAC_CR_TSEL2_2_MORT ((uint32_t)0x00200000) /*!<Bit 2 */ 02663 02664 #define DAC_CR_WAVE2_MORT ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC_MORT channel2 noise/triangle wave generation enable) */ 02665 #define DAC_CR_WAVE2_0_MORT ((uint32_t)0x00400000) /*!<Bit 0 */ 02666 #define DAC_CR_WAVE2_1_MORT ((uint32_t)0x00800000) /*!<Bit 1 */ 02667 02668 #define DAC_CR_MAMP2_MORT ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC_MORT channel2 Mask/Amplitude selector) */ 02669 #define DAC_CR_MAMP2_0_MORT ((uint32_t)0x01000000) /*!<Bit 0 */ 02670 #define DAC_CR_MAMP2_1_MORT ((uint32_t)0x02000000) /*!<Bit 1 */ 02671 #define DAC_CR_MAMP2_2_MORT ((uint32_t)0x04000000) /*!<Bit 2 */ 02672 #define DAC_CR_MAMP2_3_MORT ((uint32_t)0x08000000) /*!<Bit 3 */ 02673 02674 #define DAC_CR_DMAEN2_MORT ((uint32_t)0x10000000) /*!<DAC_MORT channel2 DMA enabled */ 02675 #define DAC_CR_DMAUDRIE2_MORT ((uint32_t)0x20000000U) /*!<DAC_MORT channel2 DMA underrun interrupt enable*/ 02676 02677 /***************** Bit definition for DAC_SWTRIGR register ******************/ 02678 #define DAC_SWTRIGR_SWTRIG1_MORT ((uint8_t)0x01) /*!<DAC_MORT channel1 software trigger */ 02679 #define DAC_SWTRIGR_SWTRIG2_MORT ((uint8_t)0x02) /*!<DAC_MORT channel2 software trigger */ 02680 02681 /***************** Bit definition for DAC_DHR12R1 register ******************/ 02682 #define DAC_DHR12R1_DACC1DHR_MORT ((uint16_t)0x0FFF) /*!<DAC_MORT channel1 12-bit Right aligned data */ 02683 02684 /***************** Bit definition for DAC_DHR12L1 register ******************/ 02685 #define DAC_DHR12L1_DACC1DHR_MORT ((uint16_t)0xFFF0) /*!<DAC_MORT channel1 12-bit Left aligned data */ 02686 02687 /****************** Bit definition for DAC_DHR8R1 register ******************/ 02688 #define DAC_DHR8R1_DACC1DHR_MORT ((uint8_t)0xFF) /*!<DAC_MORT channel1 8-bit Right aligned data */ 02689 02690 /***************** Bit definition for DAC_DHR12R2 register ******************/ 02691 #define DAC_DHR12R2_DACC2DHR_MORT ((uint16_t)0x0FFF) /*!<DAC_MORT channel2 12-bit Right aligned data */ 02692 02693 /***************** Bit definition for DAC_DHR12L2 register ******************/ 02694 #define DAC_DHR12L2_DACC2DHR_MORT ((uint16_t)0xFFF0) /*!<DAC_MORT channel2 12-bit Left aligned data */ 02695 02696 /****************** Bit definition for DAC_DHR8R2 register ******************/ 02697 #define DAC_DHR8R2_DACC2DHR_MORT ((uint8_t)0xFF) /*!<DAC_MORT channel2 8-bit Right aligned data */ 02698 02699 /***************** Bit definition for DAC_DHR12RD register ******************/ 02700 #define DAC_DHR12RD_DACC1DHR_MORT ((uint32_t)0x00000FFF) /*!<DAC_MORT channel1 12-bit Right aligned data */ 02701 #define DAC_DHR12RD_DACC2DHR_MORT ((uint32_t)0x0FFF0000) /*!<DAC_MORT channel2 12-bit Right aligned data */ 02702 02703 /***************** Bit definition for DAC_DHR12LD register ******************/ 02704 #define DAC_DHR12LD_DACC1DHR_MORT ((uint32_t)0x0000FFF0) /*!<DAC_MORT channel1 12-bit Left aligned data */ 02705 #define DAC_DHR12LD_DACC2DHR_MORT ((uint32_t)0xFFF00000) /*!<DAC_MORT channel2 12-bit Left aligned data */ 02706 02707 /****************** Bit definition for DAC_DHR8RD register ******************/ 02708 #define DAC_DHR8RD_DACC1DHR_MORT ((uint16_t)0x00FF) /*!<DAC_MORT channel1 8-bit Right aligned data */ 02709 #define DAC_DHR8RD_DACC2DHR_MORT ((uint16_t)0xFF00) /*!<DAC_MORT channel2 8-bit Right aligned data */ 02710 02711 /******************* Bit definition for DAC_DOR1 register *******************/ 02712 #define DAC_DOR1_DACC1DOR_MORT ((uint16_t)0x0FFF) /*!<DAC_MORT channel1 data output */ 02713 02714 /******************* Bit definition for DAC_DOR2 register *******************/ 02715 #define DAC_DOR2_DACC2DOR_MORT ((uint16_t)0x0FFF) /*!<DAC_MORT channel2 data output */ 02716 02717 /******************** Bit definition for DAC_SR register ********************/ 02718 #define DAC_SR_DMAUDR1_MORT ((uint32_t)0x00002000) /*!<DAC_MORT channel1 DMA underrun flag */ 02719 #define DAC_SR_DMAUDR2_MORT ((uint32_t)0x20000000) /*!<DAC_MORT channel2 DMA underrun flag */ 02720 02721 /******************************************************************************/ 02722 /* */ 02723 /* Debug MCU */ 02724 /* */ 02725 /******************************************************************************/ 02726 02727 /******************************************************************************/ 02728 /* */ 02729 /* DCMI_MORT */ 02730 /* */ 02731 /******************************************************************************/ 02732 /******************** Bits definition for DCMI_CR register ******************/ 02733 02734 02735 /******************** Bits definition for DCMI_SR register ******************/ 02736 02737 02738 /******************** Bits definition for DCMI_RIS register *****************/ 02739 02740 /* Legacy defines */ 02741 02742 02743 /******************** Bits definition for DCMI_IER register *****************/ 02744 02745 02746 /* Legacy defines */ 02747 02748 02749 /******************** Bits definition for DCMI_MIS register ****************/ 02750 02751 02752 /* Legacy defines */ 02753 02754 02755 /******************** Bits definition for DCMI_ICR register *****************/ 02756 02757 02758 /* Legacy defines */ 02759 02760 /******************** Bits definition for DCMI_ESCR register ******************/ 02761 02762 02763 /******************** Bits definition for DCMI_ESUR register ******************/ 02764 02765 02766 /******************** Bits definition for DCMI_CWSTRT register ******************/ 02767 02768 02769 /******************** Bits definition for DCMI_CWSIZE register ******************/ 02770 02771 02772 /******************** Bits definition for DCMI_DR register ******************/ 02773 02774 02775 /******************************************************************************/ 02776 /* */ 02777 /* Digital Filter for Sigma Delta Modulators */ 02778 /* */ 02779 /******************************************************************************/ 02780 02781 /**************** DFSDM channel configuration registers ********************/ 02782 02783 /*************** Bit definition for DFSDM_CHCFGR1 register ******************/ 02784 02785 /*************** Bit definition for DFSDM_CHCFGR2 register ******************/ 02786 02787 /****************** Bit definition for DFSDM_CHAWSCDR register ***************/ 02788 02789 /**************** Bit definition for DFSDM_CHWDATR register *******************/ 02790 02791 /**************** Bit definition for DFSDM_CHDATINR register *****************/ 02792 02793 /************************ DFSDM module registers ****************************/ 02794 02795 /***************** Bit definition for DFSDM_FLTCR1 register *******************/ 02796 02797 /******************** Bit definition for DFSDM_FLTCR2 register ***************/ 02798 02799 /***************** Bit definition for DFSDM_FLTISR register *******************/ 02800 02801 /***************** Bit definition for DFSDM_FLTICR register *******************/ 02802 02803 /**************** Bit definition for DFSDM_FLTJCHGR register ******************/ 02804 02805 /***************** Bit definition for DFSDM_FLTFCR register *******************/ 02806 02807 /*************** Bit definition for DFSDM_FLTJDATAR register *****************/ 02808 02809 /*************** Bit definition for DFSDM_FLTRDATAR register *****************/ 02810 02811 /*************** Bit definition for DFSDM_FLTAWHTR register ******************/ 02812 02813 /*************** Bit definition for DFSDM_FLTAWLTR register ******************/ 02814 02815 /*************** Bit definition for DFSDM_FLTAWSR register *******************/ 02816 02817 /*************** Bit definition for DFSDM_FLTAWCFR register ******************/ 02818 02819 /*************** Bit definition for DFSDM_FLTEXMAX register ******************/ 02820 02821 /*************** Bit definition for DFSDM_FLTEXMIN register ******************/ 02822 02823 /*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/ 02824 02825 /******************************************************************************/ 02826 /* */ 02827 /* DMA Controller */ 02828 /* */ 02829 /******************************************************************************/ 02830 /******************** Bits definition for DMA_SxCR register *****************/ 02831 #define DMA_SxCR_CHSEL_MORT ((uint32_t)0x0E000000) 02832 #define DMA_SxCR_CHSEL_0_MORT ((uint32_t)0x02000000) 02833 #define DMA_SxCR_CHSEL_1_MORT ((uint32_t)0x04000000) 02834 #define DMA_SxCR_CHSEL_2_MORT ((uint32_t)0x08000000) 02835 #define DMA_SxCR_MBURST_MORT ((uint32_t)0x01800000) 02836 #define DMA_SxCR_MBURST_0_MORT ((uint32_t)0x00800000) 02837 #define DMA_SxCR_MBURST_1_MORT ((uint32_t)0x01000000) 02838 #define DMA_SxCR_PBURST_MORT ((uint32_t)0x00600000) 02839 #define DMA_SxCR_PBURST_0_MORT ((uint32_t)0x00200000) 02840 #define DMA_SxCR_PBURST_1_MORT ((uint32_t)0x00400000) 02841 #define DMA_SxCR_ACK_MORT ((uint32_t)0x00100000) 02842 #define DMA_SxCR_CT_MORT ((uint32_t)0x00080000) 02843 #define DMA_SxCR_DBM_MORT ((uint32_t)0x00040000) 02844 #define DMA_SxCR_PL_MORT ((uint32_t)0x00030000) 02845 #define DMA_SxCR_PL_0_MORT ((uint32_t)0x00010000) 02846 #define DMA_SxCR_PL_1_MORT ((uint32_t)0x00020000) 02847 #define DMA_SxCR_PINCOS_MORT ((uint32_t)0x00008000) 02848 #define DMA_SxCR_MSIZE_MORT ((uint32_t)0x00006000) 02849 #define DMA_SxCR_MSIZE_0_MORT ((uint32_t)0x00002000) 02850 #define DMA_SxCR_MSIZE_1_MORT ((uint32_t)0x00004000) 02851 #define DMA_SxCR_PSIZE_MORT ((uint32_t)0x00001800) 02852 #define DMA_SxCR_PSIZE_0_MORT ((uint32_t)0x00000800) 02853 #define DMA_SxCR_PSIZE_1_MORT ((uint32_t)0x00001000) 02854 #define DMA_SxCR_MINC_MORT ((uint32_t)0x00000400) 02855 #define DMA_SxCR_PINC_MORT ((uint32_t)0x00000200) 02856 #define DMA_SxCR_CIRC_MORT ((uint32_t)0x00000100) 02857 #define DMA_SxCR_DIR_MORT ((uint32_t)0x000000C0) 02858 #define DMA_SxCR_DIR_0_MORT ((uint32_t)0x00000040) 02859 #define DMA_SxCR_DIR_1_MORT ((uint32_t)0x00000080) 02860 #define DMA_SxCR_PFCTRL_MORT ((uint32_t)0x00000020) 02861 #define DMA_SxCR_TCIE_MORT ((uint32_t)0x00000010) 02862 #define DMA_SxCR_HTIE_MORT ((uint32_t)0x00000008) 02863 #define DMA_SxCR_TEIE_MORT ((uint32_t)0x00000004) 02864 #define DMA_SxCR_DMEIE_MORT ((uint32_t)0x00000002) 02865 #define DMA_SxCR_EN_MORT ((uint32_t)0x00000001) 02866 02867 /******************** Bits definition for DMA_SxCNDTR register **************/ 02868 #define DMA_SxNDT_MORT ((uint32_t)0x0000FFFF) 02869 #define DMA_SxNDT_0_MORT ((uint32_t)0x00000001) 02870 #define DMA_SxNDT_1_MORT ((uint32_t)0x00000002) 02871 #define DMA_SxNDT_2_MORT ((uint32_t)0x00000004) 02872 #define DMA_SxNDT_3_MORT ((uint32_t)0x00000008) 02873 #define DMA_SxNDT_4_MORT ((uint32_t)0x00000010) 02874 #define DMA_SxNDT_5_MORT ((uint32_t)0x00000020) 02875 #define DMA_SxNDT_6_MORT ((uint32_t)0x00000040) 02876 #define DMA_SxNDT_7_MORT ((uint32_t)0x00000080) 02877 #define DMA_SxNDT_8_MORT ((uint32_t)0x00000100) 02878 #define DMA_SxNDT_9_MORT ((uint32_t)0x00000200) 02879 #define DMA_SxNDT_10_MORT ((uint32_t)0x00000400) 02880 #define DMA_SxNDT_11_MORT ((uint32_t)0x00000800) 02881 #define DMA_SxNDT_12_MORT ((uint32_t)0x00001000) 02882 #define DMA_SxNDT_13_MORT ((uint32_t)0x00002000) 02883 #define DMA_SxNDT_14_MORT ((uint32_t)0x00004000) 02884 #define DMA_SxNDT_15_MORT ((uint32_t)0x00008000) 02885 02886 /******************** Bits definition for DMA_SxFCR register ****************/ 02887 #define DMA_SxFCR_FEIE_MORT ((uint32_t)0x00000080) 02888 #define DMA_SxFCR_FS_MORT ((uint32_t)0x00000038) 02889 #define DMA_SxFCR_FS_0_MORT ((uint32_t)0x00000008) 02890 #define DMA_SxFCR_FS_1_MORT ((uint32_t)0x00000010) 02891 #define DMA_SxFCR_FS_2_MORT ((uint32_t)0x00000020) 02892 #define DMA_SxFCR_DMDIS_MORT ((uint32_t)0x00000004) 02893 #define DMA_SxFCR_FTH_MORT ((uint32_t)0x00000003) 02894 #define DMA_SxFCR_FTH_0_MORT ((uint32_t)0x00000001) 02895 #define DMA_SxFCR_FTH_1_MORT ((uint32_t)0x00000002) 02896 02897 /******************** Bits definition for DMA_LISR register *****************/ 02898 #define DMA_LISR_TCIF3_MORT ((uint32_t)0x08000000) 02899 #define DMA_LISR_HTIF3_MORT ((uint32_t)0x04000000) 02900 #define DMA_LISR_TEIF3_MORT ((uint32_t)0x02000000) 02901 #define DMA_LISR_DMEIF3_MORT ((uint32_t)0x01000000) 02902 #define DMA_LISR_FEIF3_MORT ((uint32_t)0x00400000) 02903 #define DMA_LISR_TCIF2_MORT ((uint32_t)0x00200000) 02904 #define DMA_LISR_HTIF2_MORT ((uint32_t)0x00100000) 02905 #define DMA_LISR_TEIF2_MORT ((uint32_t)0x00080000) 02906 #define DMA_LISR_DMEIF2_MORT ((uint32_t)0x00040000) 02907 #define DMA_LISR_FEIF2_MORT ((uint32_t)0x00010000) 02908 #define DMA_LISR_TCIF1_MORT ((uint32_t)0x00000800) 02909 #define DMA_LISR_HTIF1_MORT ((uint32_t)0x00000400) 02910 #define DMA_LISR_TEIF1_MORT ((uint32_t)0x00000200) 02911 #define DMA_LISR_DMEIF1_MORT ((uint32_t)0x00000100) 02912 #define DMA_LISR_FEIF1_MORT ((uint32_t)0x00000040) 02913 #define DMA_LISR_TCIF0_MORT ((uint32_t)0x00000020) 02914 #define DMA_LISR_HTIF0_MORT ((uint32_t)0x00000010) 02915 #define DMA_LISR_TEIF0_MORT ((uint32_t)0x00000008) 02916 #define DMA_LISR_DMEIF0_MORT ((uint32_t)0x00000004) 02917 #define DMA_LISR_FEIF0_MORT ((uint32_t)0x00000001) 02918 02919 /******************** Bits definition for DMA_HISR register *****************/ 02920 #define DMA_HISR_TCIF7_MORT ((uint32_t)0x08000000) 02921 #define DMA_HISR_HTIF7_MORT ((uint32_t)0x04000000) 02922 #define DMA_HISR_TEIF7_MORT ((uint32_t)0x02000000) 02923 #define DMA_HISR_DMEIF7_MORT ((uint32_t)0x01000000) 02924 #define DMA_HISR_FEIF7_MORT ((uint32_t)0x00400000) 02925 #define DMA_HISR_TCIF6_MORT ((uint32_t)0x00200000) 02926 #define DMA_HISR_HTIF6_MORT ((uint32_t)0x00100000) 02927 #define DMA_HISR_TEIF6_MORT ((uint32_t)0x00080000) 02928 #define DMA_HISR_DMEIF6_MORT ((uint32_t)0x00040000) 02929 #define DMA_HISR_FEIF6_MORT ((uint32_t)0x00010000) 02930 #define DMA_HISR_TCIF5_MORT ((uint32_t)0x00000800) 02931 #define DMA_HISR_HTIF5_MORT ((uint32_t)0x00000400) 02932 #define DMA_HISR_TEIF5_MORT ((uint32_t)0x00000200) 02933 #define DMA_HISR_DMEIF5_MORT ((uint32_t)0x00000100) 02934 #define DMA_HISR_FEIF5_MORT ((uint32_t)0x00000040) 02935 #define DMA_HISR_TCIF4_MORT ((uint32_t)0x00000020) 02936 #define DMA_HISR_HTIF4_MORT ((uint32_t)0x00000010) 02937 #define DMA_HISR_TEIF4_MORT ((uint32_t)0x00000008) 02938 #define DMA_HISR_DMEIF4_MORT ((uint32_t)0x00000004) 02939 #define DMA_HISR_FEIF4_MORT ((uint32_t)0x00000001) 02940 02941 /******************** Bits definition for DMA_LIFCR register ****************/ 02942 #define DMA_LIFCR_CTCIF3_MORT ((uint32_t)0x08000000) 02943 #define DMA_LIFCR_CHTIF3_MORT ((uint32_t)0x04000000) 02944 #define DMA_LIFCR_CTEIF3_MORT ((uint32_t)0x02000000) 02945 #define DMA_LIFCR_CDMEIF3_MORT ((uint32_t)0x01000000) 02946 #define DMA_LIFCR_CFEIF3_MORT ((uint32_t)0x00400000) 02947 #define DMA_LIFCR_CTCIF2_MORT ((uint32_t)0x00200000) 02948 #define DMA_LIFCR_CHTIF2_MORT ((uint32_t)0x00100000) 02949 #define DMA_LIFCR_CTEIF2_MORT ((uint32_t)0x00080000) 02950 #define DMA_LIFCR_CDMEIF2_MORT ((uint32_t)0x00040000) 02951 #define DMA_LIFCR_CFEIF2_MORT ((uint32_t)0x00010000) 02952 #define DMA_LIFCR_CTCIF1_MORT ((uint32_t)0x00000800) 02953 #define DMA_LIFCR_CHTIF1_MORT ((uint32_t)0x00000400) 02954 #define DMA_LIFCR_CTEIF1_MORT ((uint32_t)0x00000200) 02955 #define DMA_LIFCR_CDMEIF1_MORT ((uint32_t)0x00000100) 02956 #define DMA_LIFCR_CFEIF1_MORT ((uint32_t)0x00000040) 02957 #define DMA_LIFCR_CTCIF0_MORT ((uint32_t)0x00000020) 02958 #define DMA_LIFCR_CHTIF0_MORT ((uint32_t)0x00000010) 02959 #define DMA_LIFCR_CTEIF0_MORT ((uint32_t)0x00000008) 02960 #define DMA_LIFCR_CDMEIF0_MORT ((uint32_t)0x00000004) 02961 #define DMA_LIFCR_CFEIF0_MORT ((uint32_t)0x00000001) 02962 02963 /******************** Bits definition for DMA_HIFCR register ****************/ 02964 #define DMA_HIFCR_CTCIF7_MORT ((uint32_t)0x08000000) 02965 #define DMA_HIFCR_CHTIF7_MORT ((uint32_t)0x04000000) 02966 #define DMA_HIFCR_CTEIF7_MORT ((uint32_t)0x02000000) 02967 #define DMA_HIFCR_CDMEIF7_MORT ((uint32_t)0x01000000) 02968 #define DMA_HIFCR_CFEIF7_MORT ((uint32_t)0x00400000) 02969 #define DMA_HIFCR_CTCIF6_MORT ((uint32_t)0x00200000) 02970 #define DMA_HIFCR_CHTIF6_MORT ((uint32_t)0x00100000) 02971 #define DMA_HIFCR_CTEIF6_MORT ((uint32_t)0x00080000) 02972 #define DMA_HIFCR_CDMEIF6_MORT ((uint32_t)0x00040000) 02973 #define DMA_HIFCR_CFEIF6_MORT ((uint32_t)0x00010000) 02974 #define DMA_HIFCR_CTCIF5_MORT ((uint32_t)0x00000800) 02975 #define DMA_HIFCR_CHTIF5_MORT ((uint32_t)0x00000400) 02976 #define DMA_HIFCR_CTEIF5_MORT ((uint32_t)0x00000200) 02977 #define DMA_HIFCR_CDMEIF5_MORT ((uint32_t)0x00000100) 02978 #define DMA_HIFCR_CFEIF5_MORT ((uint32_t)0x00000040) 02979 #define DMA_HIFCR_CTCIF4_MORT ((uint32_t)0x00000020) 02980 #define DMA_HIFCR_CHTIF4_MORT ((uint32_t)0x00000010) 02981 #define DMA_HIFCR_CTEIF4_MORT ((uint32_t)0x00000008) 02982 #define DMA_HIFCR_CDMEIF4_MORT ((uint32_t)0x00000004) 02983 #define DMA_HIFCR_CFEIF4_MORT ((uint32_t)0x00000001) 02984 02985 /******************************************************************************/ 02986 /* */ 02987 /* AHB Master DMA2D_MORT Controller (DMA2D_MORT) */ 02988 /* */ 02989 /******************************************************************************/ 02990 02991 /******************** Bit definition for DMA2D_CR register ******************/ 02992 02993 #define DMA2D_CR_START_MORT ((uint32_t)0x00000001) /*!< Start transfer */ 02994 #define DMA2D_CR_SUSP_MORT ((uint32_t)0x00000002) /*!< Suspend transfer */ 02995 #define DMA2D_CR_ABORT_MORT ((uint32_t)0x00000004) /*!< Abort transfer */ 02996 #define DMA2D_CR_TEIE_MORT ((uint32_t)0x00000100) /*!< Transfer Error Interrupt Enable */ 02997 #define DMA2D_CR_TCIE_MORT ((uint32_t)0x00000200) /*!< Transfer Complete Interrupt Enable */ 02998 #define DMA2D_CR_TWIE_MORT ((uint32_t)0x00000400) /*!< Transfer Watermark Interrupt Enable */ 02999 #define DMA2D_CR_CAEIE_MORT ((uint32_t)0x00000800) /*!< CLUT Access Error Interrupt Enable */ 03000 #define DMA2D_CR_CTCIE_MORT ((uint32_t)0x00001000) /*!< CLUT Transfer Complete Interrupt Enable */ 03001 #define DMA2D_CR_CEIE_MORT ((uint32_t)0x00002000) /*!< Configuration Error Interrupt Enable */ 03002 #define DMA2D_CR_MODE_MORT ((uint32_t)0x00030000) /*!< DMA2D_MORT Mode */ 03003 03004 /******************** Bit definition for DMA2D_ISR register *****************/ 03005 03006 #define DMA2D_ISR_TEIF_MORT ((uint32_t)0x00000001) /*!< Transfer Error Interrupt Flag */ 03007 #define DMA2D_ISR_TCIF_MORT ((uint32_t)0x00000002) /*!< Transfer Complete Interrupt Flag */ 03008 #define DMA2D_ISR_TWIF_MORT ((uint32_t)0x00000004) /*!< Transfer Watermark Interrupt Flag */ 03009 #define DMA2D_ISR_CAEIF_MORT ((uint32_t)0x00000008) /*!< CLUT Access Error Interrupt Flag */ 03010 #define DMA2D_ISR_CTCIF_MORT ((uint32_t)0x00000010) /*!< CLUT Transfer Complete Interrupt Flag */ 03011 #define DMA2D_ISR_CEIF_MORT ((uint32_t)0x00000020) /*!< Configuration Error Interrupt Flag */ 03012 03013 /******************** Bit definition for DMA2D_IFCR register ****************/ 03014 03015 #define DMA2D_IFCR_CTEIF_MORT ((uint32_t)0x00000001) /*!< Clears Transfer Error Interrupt Flag */ 03016 #define DMA2D_IFCR_CTCIF_MORT ((uint32_t)0x00000002) /*!< Clears Transfer Complete Interrupt Flag */ 03017 #define DMA2D_IFCR_CTWIF_MORT ((uint32_t)0x00000004) /*!< Clears Transfer Watermark Interrupt Flag */ 03018 #define DMA2D_IFCR_CAECIF_MORT ((uint32_t)0x00000008) /*!< Clears CLUT Access Error Interrupt Flag */ 03019 #define DMA2D_IFCR_CCTCIF_MORT ((uint32_t)0x00000010) /*!< Clears CLUT Transfer Complete Interrupt Flag */ 03020 #define DMA2D_IFCR_CCEIF_MORT ((uint32_t)0x00000020) /*!< Clears Configuration Error Interrupt Flag */ 03021 03022 /* Legacy defines */ 03023 #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF_MORT /*!< Clears Transfer Error Interrupt Flag */ 03024 #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF_MORT /*!< Clears Transfer Complete Interrupt Flag */ 03025 #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF_MORT /*!< Clears Transfer Watermark Interrupt Flag */ 03026 #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF_MORT /*!< Clears CLUT Access Error Interrupt Flag */ 03027 #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF_MORT /*!< Clears CLUT Transfer Complete Interrupt Flag */ 03028 #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF_MORT /*!< Clears Configuration Error Interrupt Flag */ 03029 03030 /******************** Bit definition for DMA2D_FGMAR register ***************/ 03031 03032 #define DMA2D_FGMAR_MA_MORT ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ 03033 03034 /******************** Bit definition for DMA2D_FGOR register ****************/ 03035 03036 #define DMA2D_FGOR_LO_MORT ((uint32_t)0x00003FFF) /*!< Line Offset */ 03037 03038 /******************** Bit definition for DMA2D_BGMAR register ***************/ 03039 03040 #define DMA2D_BGMAR_MA_MORT ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ 03041 03042 /******************** Bit definition for DMA2D_BGOR register ****************/ 03043 03044 #define DMA2D_BGOR_LO_MORT ((uint32_t)0x00003FFF) /*!< Line Offset */ 03045 03046 /******************** Bit definition for DMA2D_FGPFCCR register *************/ 03047 03048 #define DMA2D_FGPFCCR_CM_MORT ((uint32_t)0x0000000F) /*!< Input color mode CM[3:0] */ 03049 #define DMA2D_FGPFCCR_CM_0_MORT ((uint32_t)0x00000001) /*!< Input color mode CM bit 0 */ 03050 #define DMA2D_FGPFCCR_CM_1_MORT ((uint32_t)0x00000002) /*!< Input color mode CM bit 1 */ 03051 #define DMA2D_FGPFCCR_CM_2_MORT ((uint32_t)0x00000004) /*!< Input color mode CM bit 2 */ 03052 #define DMA2D_FGPFCCR_CM_3_MORT ((uint32_t)0x00000008) /*!< Input color mode CM bit 3 */ 03053 #define DMA2D_FGPFCCR_CCM_MORT ((uint32_t)0x00000010) /*!< CLUT Color mode */ 03054 #define DMA2D_FGPFCCR_START_MORT ((uint32_t)0x00000020) /*!< Start */ 03055 #define DMA2D_FGPFCCR_CS_MORT ((uint32_t)0x0000FF00) /*!< CLUT size */ 03056 #define DMA2D_FGPFCCR_AM_MORT ((uint32_t)0x00030000) /*!< Alpha mode AM[1:0] */ 03057 #define DMA2D_FGPFCCR_AM_0_MORT ((uint32_t)0x00010000) /*!< Alpha mode AM bit 0 */ 03058 #define DMA2D_FGPFCCR_AM_1_MORT ((uint32_t)0x00020000) /*!< Alpha mode AM bit 1 */ 03059 #define DMA2D_FGPFCCR_ALPHA_MORT ((uint32_t)0xFF000000) /*!< Alpha value */ 03060 03061 /******************** Bit definition for DMA2D_FGCOLR register **************/ 03062 03063 #define DMA2D_FGCOLR_BLUE_MORT ((uint32_t)0x000000FF) /*!< Blue Value */ 03064 #define DMA2D_FGCOLR_GREEN_MORT ((uint32_t)0x0000FF00) /*!< Green Value */ 03065 #define DMA2D_FGCOLR_RED_MORT ((uint32_t)0x00FF0000) /*!< Red Value */ 03066 03067 /******************** Bit definition for DMA2D_BGPFCCR register *************/ 03068 03069 #define DMA2D_BGPFCCR_CM_MORT ((uint32_t)0x0000000F) /*!< Input color mode CM[3:0] */ 03070 #define DMA2D_BGPFCCR_CM_0_MORT ((uint32_t)0x00000001) /*!< Input color mode CM bit 0 */ 03071 #define DMA2D_BGPFCCR_CM_1_MORT ((uint32_t)0x00000002) /*!< Input color mode CM bit 1 */ 03072 #define DMA2D_BGPFCCR_CM_2_MORT ((uint32_t)0x00000004) /*!< Input color mode CM bit 2 */ 03073 #define DMA2D_FGPFCCR_CM_3_MORT ((uint32_t)0x00000008) /*!< Input color mode CM bit 3 */ 03074 #define DMA2D_BGPFCCR_CCM_MORT ((uint32_t)0x00000010) /*!< CLUT Color mode */ 03075 #define DMA2D_BGPFCCR_START_MORT ((uint32_t)0x00000020) /*!< Start */ 03076 #define DMA2D_BGPFCCR_CS_MORT ((uint32_t)0x0000FF00) /*!< CLUT size */ 03077 #define DMA2D_BGPFCCR_AM_MORT ((uint32_t)0x00030000) /*!< Alpha mode AM[1:0] */ 03078 #define DMA2D_BGPFCCR_AM_0_MORT ((uint32_t)0x00010000) /*!< Alpha mode AM bit 0 */ 03079 #define DMA2D_BGPFCCR_AM_1_MORT ((uint32_t)0x00020000) /*!< Alpha mode AM bit 1 */ 03080 #define DMA2D_BGPFCCR_ALPHA_MORT ((uint32_t)0xFF000000) /*!< Alpha value */ 03081 03082 /******************** Bit definition for DMA2D_BGCOLR register **************/ 03083 03084 #define DMA2D_BGCOLR_BLUE_MORT ((uint32_t)0x000000FF) /*!< Blue Value */ 03085 #define DMA2D_BGCOLR_GREEN_MORT ((uint32_t)0x0000FF00) /*!< Green Value */ 03086 #define DMA2D_BGCOLR_RED_MORT ((uint32_t)0x00FF0000) /*!< Red Value */ 03087 03088 /******************** Bit definition for DMA2D_FGCMAR register **************/ 03089 03090 #define DMA2D_FGCMAR_MA_MORT ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ 03091 03092 /******************** Bit definition for DMA2D_BGCMAR register **************/ 03093 03094 #define DMA2D_BGCMAR_MA_MORT ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ 03095 03096 /******************** Bit definition for DMA2D_OPFCCR register **************/ 03097 03098 #define DMA2D_OPFCCR_CM_MORT ((uint32_t)0x00000007) /*!< Color mode CM[2:0] */ 03099 #define DMA2D_OPFCCR_CM_0_MORT ((uint32_t)0x00000001) /*!< Color mode CM bit 0 */ 03100 #define DMA2D_OPFCCR_CM_1_MORT ((uint32_t)0x00000002) /*!< Color mode CM bit 1 */ 03101 #define DMA2D_OPFCCR_CM_2_MORT ((uint32_t)0x00000004) /*!< Color mode CM bit 2 */ 03102 03103 /******************** Bit definition for DMA2D_OCOLR register ***************/ 03104 03105 /*!<Mode_ARGB8888/RGB888 */ 03106 03107 #define DMA2D_OCOLR_BLUE_1_MORT ((uint32_t)0x000000FF) /*!< BLUE Value */ 03108 #define DMA2D_OCOLR_GREEN_1_MORT ((uint32_t)0x0000FF00) /*!< GREEN Value */ 03109 #define DMA2D_OCOLR_RED_1_MORT ((uint32_t)0x00FF0000) /*!< Red Value */ 03110 #define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000) /*!< Alpha Channel Value */ 03111 03112 /*!<Mode_RGB565 */ 03113 #define DMA2D_OCOLR_BLUE_2_MORT ((uint32_t)0x0000001F) /*!< BLUE Value */ 03114 #define DMA2D_OCOLR_GREEN_2_MORT ((uint32_t)0x000007E0) /*!< GREEN Value */ 03115 #define DMA2D_OCOLR_RED_2_MORT ((uint32_t)0x0000F800) /*!< Red Value */ 03116 03117 /*!<Mode_ARGB1555 */ 03118 #define DMA2D_OCOLR_BLUE_3_MORT ((uint32_t)0x0000001F) /*!< BLUE Value */ 03119 #define DMA2D_OCOLR_GREEN_3_MORT ((uint32_t)0x000003E0) /*!< GREEN Value */ 03120 #define DMA2D_OCOLR_RED_3_MORT ((uint32_t)0x00007C00) /*!< Red Value */ 03121 #define DMA2D_OCOLR_ALPHA_3_MORT ((uint32_t)0x00008000) /*!< Alpha Channel Value */ 03122 03123 /*!<Mode_ARGB4444 */ 03124 #define DMA2D_OCOLR_BLUE_4_MORT ((uint32_t)0x0000000F) /*!< BLUE Value */ 03125 #define DMA2D_OCOLR_GREEN_4_MORT ((uint32_t)0x000000F0) /*!< GREEN Value */ 03126 #define DMA2D_OCOLR_RED_4_MORT ((uint32_t)0x00000F00) /*!< Red Value */ 03127 #define DMA2D_OCOLR_ALPHA_4_MORT ((uint32_t)0x0000F000) /*!< Alpha Channel Value */ 03128 03129 /******************** Bit definition for DMA2D_OMAR register ****************/ 03130 03131 #define DMA2D_OMAR_MA_MORT ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ 03132 03133 /******************** Bit definition for DMA2D_OOR register *****************/ 03134 03135 #define DMA2D_OOR_LO_MORT ((uint32_t)0x00003FFF) /*!< Line Offset */ 03136 03137 /******************** Bit definition for DMA2D_NLR register *****************/ 03138 03139 #define DMA2D_NLR_NL_MORT ((uint32_t)0x0000FFFF) /*!< Number of Lines */ 03140 #define DMA2D_NLR_PL_MORT ((uint32_t)0x3FFF0000) /*!< Pixel per Lines */ 03141 03142 /******************** Bit definition for DMA2D_LWR register *****************/ 03143 03144 #define DMA2D_LWR_LW_MORT ((uint32_t)0x0000FFFF) /*!< Line Watermark */ 03145 03146 /******************** Bit definition for DMA2D_AMTCR register ***************/ 03147 03148 #define DMA2D_AMTCR_EN_MORT ((uint32_t)0x00000001) /*!< Enable */ 03149 #define DMA2D_AMTCR_DT_MORT ((uint32_t)0x0000FF00) /*!< Dead Time */ 03150 03151 03152 03153 /******************** Bit definition for DMA2D_FGCLUT register **************/ 03154 03155 /******************** Bit definition for DMA2D_BGCLUT register **************/ 03156 03157 03158 /******************************************************************************/ 03159 /* */ 03160 /* External Interrupt/Event Controller */ 03161 /* */ 03162 /******************************************************************************/ 03163 /******************* Bit definition for EXTI_IMR register *******************/ 03164 #define EXTI_IMR_MR0_MORT ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ 03165 #define EXTI_IMR_MR1_MORT ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ 03166 #define EXTI_IMR_MR2_MORT ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ 03167 #define EXTI_IMR_MR3_MORT ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ 03168 #define EXTI_IMR_MR4_MORT ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ 03169 #define EXTI_IMR_MR5_MORT ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ 03170 #define EXTI_IMR_MR6_MORT ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ 03171 #define EXTI_IMR_MR7_MORT ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ 03172 #define EXTI_IMR_MR8_MORT ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ 03173 #define EXTI_IMR_MR9_MORT ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ 03174 #define EXTI_IMR_MR10_MORT ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ 03175 #define EXTI_IMR_MR11_MORT ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ 03176 #define EXTI_IMR_MR12_MORT ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ 03177 #define EXTI_IMR_MR13_MORT ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ 03178 #define EXTI_IMR_MR14_MORT ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ 03179 #define EXTI_IMR_MR15_MORT ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ 03180 #define EXTI_IMR_MR16_MORT ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ 03181 #define EXTI_IMR_MR17_MORT ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ 03182 #define EXTI_IMR_MR18_MORT ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ 03183 #define EXTI_IMR_MR19_MORT ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ 03184 #define EXTI_IMR_MR23_MORT ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */ 03185 03186 /******************* Bit definition for EXTI_EMR register *******************/ 03187 #define EXTI_EMR_MR0_MORT ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ 03188 #define EXTI_EMR_MR1_MORT ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ 03189 #define EXTI_EMR_MR2_MORT ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ 03190 #define EXTI_EMR_MR3_MORT ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ 03191 #define EXTI_EMR_MR4_MORT ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ 03192 #define EXTI_EMR_MR5_MORT ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ 03193 #define EXTI_EMR_MR6_MORT ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ 03194 #define EXTI_EMR_MR7_MORT ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ 03195 #define EXTI_EMR_MR8_MORT ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ 03196 #define EXTI_EMR_MR9_MORT ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ 03197 #define EXTI_EMR_MR10_MORT ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ 03198 #define EXTI_EMR_MR11_MORT ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ 03199 #define EXTI_EMR_MR12_MORT ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ 03200 #define EXTI_EMR_MR13_MORT ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ 03201 #define EXTI_EMR_MR14_MORT ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ 03202 #define EXTI_EMR_MR15_MORT ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ 03203 #define EXTI_EMR_MR16_MORT ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ 03204 #define EXTI_EMR_MR17_MORT ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ 03205 #define EXTI_EMR_MR18_MORT ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ 03206 #define EXTI_EMR_MR19_MORT ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ 03207 #define EXTI_EMR_MR23_MORT ((uint32_t)0x00800000) /*!< Event Mask on line 19 */ 03208 03209 /****************** Bit definition for EXTI_RTSR register *******************/ 03210 #define EXTI_RTSR_TR0_MORT ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ 03211 #define EXTI_RTSR_TR1_MORT ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ 03212 #define EXTI_RTSR_TR2_MORT ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ 03213 #define EXTI_RTSR_TR3_MORT ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ 03214 #define EXTI_RTSR_TR4_MORT ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ 03215 #define EXTI_RTSR_TR5_MORT ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ 03216 #define EXTI_RTSR_TR6_MORT ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ 03217 #define EXTI_RTSR_TR7_MORT ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ 03218 #define EXTI_RTSR_TR8_MORT ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ 03219 #define EXTI_RTSR_TR9_MORT ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ 03220 #define EXTI_RTSR_TR10_MORT ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ 03221 #define EXTI_RTSR_TR11_MORT ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ 03222 #define EXTI_RTSR_TR12_MORT ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ 03223 #define EXTI_RTSR_TR13_MORT ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ 03224 #define EXTI_RTSR_TR14_MORT ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ 03225 #define EXTI_RTSR_TR15_MORT ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ 03226 #define EXTI_RTSR_TR16_MORT ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ 03227 #define EXTI_RTSR_TR17_MORT ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ 03228 #define EXTI_RTSR_TR18_MORT ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ 03229 #define EXTI_RTSR_TR19_MORT ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ 03230 #define EXTI_RTSR_TR23_MORT ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */ 03231 03232 /****************** Bit definition for EXTI_FTSR register *******************/ 03233 #define EXTI_FTSR_TR0_MORT ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ 03234 #define EXTI_FTSR_TR1_MORT ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ 03235 #define EXTI_FTSR_TR2_MORT ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ 03236 #define EXTI_FTSR_TR3_MORT ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ 03237 #define EXTI_FTSR_TR4_MORT ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ 03238 #define EXTI_FTSR_TR5_MORT ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ 03239 #define EXTI_FTSR_TR6_MORT ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ 03240 #define EXTI_FTSR_TR7_MORT ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ 03241 #define EXTI_FTSR_TR8_MORT ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ 03242 #define EXTI_FTSR_TR9_MORT ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ 03243 #define EXTI_FTSR_TR10_MORT ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ 03244 #define EXTI_FTSR_TR11_MORT ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ 03245 #define EXTI_FTSR_TR12_MORT ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ 03246 #define EXTI_FTSR_TR13_MORT ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ 03247 #define EXTI_FTSR_TR14_MORT ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ 03248 #define EXTI_FTSR_TR15_MORT ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ 03249 #define EXTI_FTSR_TR16_MORT ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ 03250 #define EXTI_FTSR_TR17_MORT ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ 03251 #define EXTI_FTSR_TR18_MORT ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ 03252 #define EXTI_FTSR_TR19_MORT ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ 03253 #define EXTI_FTSR_TR23_MORT ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */ 03254 03255 /****************** Bit definition for EXTI_SWIER register ******************/ 03256 #define EXTI_SWIER_SWIER0_MORT ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ 03257 #define EXTI_SWIER_SWIER1_MORT ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ 03258 #define EXTI_SWIER_SWIER2_MORT ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ 03259 #define EXTI_SWIER_SWIER3_MORT ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ 03260 #define EXTI_SWIER_SWIER4_MORT ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ 03261 #define EXTI_SWIER_SWIER5_MORT ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ 03262 #define EXTI_SWIER_SWIER6_MORT ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ 03263 #define EXTI_SWIER_SWIER7_MORT ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ 03264 #define EXTI_SWIER_SWIER8_MORT ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ 03265 #define EXTI_SWIER_SWIER9_MORT ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ 03266 #define EXTI_SWIER_SWIER10_MORT ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ 03267 #define EXTI_SWIER_SWIER11_MORT ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ 03268 #define EXTI_SWIER_SWIER12_MORT ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ 03269 #define EXTI_SWIER_SWIER13_MORT ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ 03270 #define EXTI_SWIER_SWIER14_MORT ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ 03271 #define EXTI_SWIER_SWIER15_MORT ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ 03272 #define EXTI_SWIER_SWIER16_MORT ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ 03273 #define EXTI_SWIER_SWIER17_MORT ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ 03274 #define EXTI_SWIER_SWIER18_MORT ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ 03275 #define EXTI_SWIER_SWIER19_MORT ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ 03276 #define EXTI_SWIER_SWIER23_MORT ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */ 03277 03278 /******************* Bit definition for EXTI_PR register ********************/ 03279 #define EXTI_PR_PR0_MORT ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ 03280 #define EXTI_PR_PR1_MORT ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ 03281 #define EXTI_PR_PR2_MORT ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ 03282 #define EXTI_PR_PR3_MORT ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ 03283 #define EXTI_PR_PR4_MORT ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ 03284 #define EXTI_PR_PR5_MORT ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ 03285 #define EXTI_PR_PR6_MORT ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ 03286 #define EXTI_PR_PR7_MORT ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ 03287 #define EXTI_PR_PR8_MORT ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ 03288 #define EXTI_PR_PR9_MORT ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ 03289 #define EXTI_PR_PR10_MORT ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ 03290 #define EXTI_PR_PR11_MORT ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ 03291 #define EXTI_PR_PR12_MORT ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ 03292 #define EXTI_PR_PR13_MORT ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ 03293 #define EXTI_PR_PR14_MORT ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ 03294 #define EXTI_PR_PR15_MORT ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ 03295 #define EXTI_PR_PR16_MORT ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ 03296 #define EXTI_PR_PR17_MORT ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ 03297 #define EXTI_PR_PR18_MORT ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ 03298 #define EXTI_PR_PR19_MORT ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ 03299 #define EXTI_PR_PR23_MORT ((uint32_t)0x00800000) /*!< Pending bit for line 23 */ 03300 03301 /******************************************************************************/ 03302 /* */ 03303 /* FLASH_MORT */ 03304 /* */ 03305 /******************************************************************************/ 03306 /******************* Bits definition for FLASH_ACR register *****************/ 03307 03308 /******************* Bits definition for FLASH_SR register ******************/ 03309 03310 /******************* Bits definition for FLASH_CR register ******************/ 03311 03312 /******************* Bits definition for FLASH_OPTCR register ***************/ 03313 03314 /****************** Bits definition for FLASH_OPTCR1 register ***************/ 03315 03316 #if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) 03317 /******************************************************************************/ 03318 /* */ 03319 /* Flexible Static Memory Controller */ 03320 /* */ 03321 /******************************************************************************/ 03322 /****************** Bit definition for FSMC_BCR1 register *******************/ 03323 03324 03325 /****************** Bit definition for FSMC_BCR2 register *******************/ 03326 03327 03328 /****************** Bit definition for FSMC_BCR3 register *******************/ 03329 03330 03331 /****************** Bit definition for FSMC_BCR4 register *******************/ 03332 03333 03334 /****************** Bit definition for FSMC_BTR1 register ******************/ 03335 03336 03337 /****************** Bit definition for FSMC_BTR2 register *******************/ 03338 03339 03340 /******************* Bit definition for FSMC_BTR3 register *******************/ 03341 03342 03343 03344 /****************** Bit definition for FSMC_BTR4 register *******************/ 03345 03346 03347 /****************** Bit definition for FSMC_BWTR1 register ******************/ 03348 03349 03350 /****************** Bit definition for FSMC_BWTR2 register ******************/ 03351 03352 03353 /****************** Bit definition for FSMC_BWTR3 register ******************/ 03354 03355 03356 /****************** Bit definition for FSMC_BWTR4 register ******************/ 03357 03358 03359 /****************** Bit definition for FSMC_PCR2 register *******************/ 03360 03361 03362 /****************** Bit definition for FSMC_PCR3 register *******************/ 03363 03364 03365 /****************** Bit definition for FSMC_PCR4 register *******************/ 03366 03367 03368 /******************* Bit definition for FSMC_SR2 register *******************/ 03369 03370 03371 /******************* Bit definition for FSMC_SR3 register *******************/ 03372 03373 03374 /******************* Bit definition for FSMC_SR4 register *******************/ 03375 03376 /****************** Bit definition for FSMC_PMEM2 register ******************/ 03377 03378 03379 /****************** Bit definition for FSMC_PMEM3 register ******************/ 03380 03381 03382 /****************** Bit definition for FSMC_PMEM4 register ******************/ 03383 03384 03385 /****************** Bit definition for FSMC_PATT2 register ******************/ 03386 03387 03388 /****************** Bit definition for FSMC_PATT3 register ******************/ 03389 03390 03391 /****************** Bit definition for FSMC_PATT4 register ******************/ 03392 03393 /****************** Bit definition for FSMC_PIO4 register *******************/ 03394 03395 03396 /****************** Bit definition for FSMC_ECCR2 register ******************/ 03397 03398 03399 /****************** Bit definition for FSMC_ECCR3 register ******************/ 03400 03401 #endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */ 03402 03403 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) 03404 /******************************************************************************/ 03405 /* */ 03406 /* Flexible Memory Controller */ 03407 /* */ 03408 /******************************************************************************/ 03409 /****************** Bit definition for FMC_BCR1 register *******************/ 03410 03411 /****************** Bit definition for FMC_BCR2 register *******************/ 03412 03413 /****************** Bit definition for FMC_BCR3 register *******************/ 03414 03415 /****************** Bit definition for FMC_BCR4 register *******************/ 03416 03417 /****************** Bit definition for FMC_BTR1 register ******************/ 03418 03419 03420 /****************** Bit definition for FMC_BTR2 register *******************/ 03421 03422 03423 /******************* Bit definition for FMC_BTR3 register *******************/ 03424 03425 /****************** Bit definition for FMC_BTR4 register *******************/ 03426 03427 03428 /****************** Bit definition for FMC_BWTR1 register ******************/ 03429 03430 /****************** Bit definition for FMC_BWTR2 register ******************/ 03431 03432 /****************** Bit definition for FMC_BWTR3 register ******************/ 03433 03434 /****************** Bit definition for FMC_BWTR4 register ******************/ 03435 03436 /****************** Bit definition for FMC_PCR2 register *******************/ 03437 03438 /****************** Bit definition for FMC_PCR3 register *******************/ 03439 03440 /****************** Bit definition for FMC_PCR4 register *******************/ 03441 03442 /******************* Bit definition for FMC_SR2 register *******************/ 03443 03444 /******************* Bit definition for FMC_SR3 register *******************/ 03445 03446 /******************* Bit definition for FMC_SR4 register *******************/ 03447 03448 /****************** Bit definition for FMC_PMEM2 register ******************/ 03449 03450 03451 /****************** Bit definition for FMC_PMEM3 register ******************/ 03452 03453 /****************** Bit definition for FMC_PMEM4 register ******************/ 03454 03455 /****************** Bit definition for FMC_PATT2 register ******************/ 03456 03457 /****************** Bit definition for FMC_PATT3 register ******************/ 03458 03459 /****************** Bit definition for FMC_PATT4 register ******************/ 03460 03461 /****************** Bit definition for FMC_PIO4 register *******************/ 03462 03463 /****************** Bit definition for FMC_ECCR2 register ******************/ 03464 03465 /****************** Bit definition for FMC_ECCR3 register ******************/ 03466 03467 /****************** Bit definition for FMC_SDCR1 register ******************/ 03468 03469 /****************** Bit definition for FMC_SDCR2 register ******************/ 03470 03471 /****************** Bit definition for FMC_SDTR1 register ******************/ 03472 03473 /****************** Bit definition for FMC_SDTR2 register ******************/ 03474 03475 /****************** Bit definition for FMC_SDCMR register ******************/ 03476 03477 /****************** Bit definition for FMC_SDRTR register ******************/ 03478 03479 /****************** Bit definition for FMC_SDSR register ******************/ 03480 03481 #endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx_MORT || STM32F469_479xx */ 03482 03483 /******************************************************************************/ 03484 /* */ 03485 /* General Purpose I/O */ 03486 /* */ 03487 /******************************************************************************/ 03488 /****************** Bits definition for GPIO_MODER register *****************/ 03489 #define GPIO_MODER_MODER0_MORT ((uint32_t)0x00000003) 03490 #define GPIO_MODER_MODER0_0_MORT ((uint32_t)0x00000001) 03491 #define GPIO_MODER_MODER0_1_MORT ((uint32_t)0x00000002) 03492 03493 #define GPIO_MODER_MODER1_MORT ((uint32_t)0x0000000C) 03494 #define GPIO_MODER_MODER1_0_MORT ((uint32_t)0x00000004) 03495 #define GPIO_MODER_MODER1_1_MORT ((uint32_t)0x00000008) 03496 03497 #define GPIO_MODER_MODER2_MORT ((uint32_t)0x00000030) 03498 #define GPIO_MODER_MODER2_0_MORT ((uint32_t)0x00000010) 03499 #define GPIO_MODER_MODER2_1_MORT ((uint32_t)0x00000020) 03500 03501 #define GPIO_MODER_MODER3_MORT ((uint32_t)0x000000C0) 03502 #define GPIO_MODER_MODER3_0_MORT ((uint32_t)0x00000040) 03503 #define GPIO_MODER_MODER3_1_MORT ((uint32_t)0x00000080) 03504 03505 #define GPIO_MODER_MODER4_MORT ((uint32_t)0x00000300) 03506 #define GPIO_MODER_MODER4_0_MORT ((uint32_t)0x00000100) 03507 #define GPIO_MODER_MODER4_1_MORT ((uint32_t)0x00000200) 03508 03509 #define GPIO_MODER_MODER5_MORT ((uint32_t)0x00000C00) 03510 #define GPIO_MODER_MODER5_0_MORT ((uint32_t)0x00000400) 03511 #define GPIO_MODER_MODER5_1_MORT ((uint32_t)0x00000800) 03512 03513 #define GPIO_MODER_MODER6_MORT ((uint32_t)0x00003000) 03514 #define GPIO_MODER_MODER6_0_MORT ((uint32_t)0x00001000) 03515 #define GPIO_MODER_MODER6_1_MORT ((uint32_t)0x00002000) 03516 03517 #define GPIO_MODER_MODER7_MORT ((uint32_t)0x0000C000) 03518 #define GPIO_MODER_MODER7_0_MORT ((uint32_t)0x00004000) 03519 #define GPIO_MODER_MODER7_1_MORT ((uint32_t)0x00008000) 03520 03521 #define GPIO_MODER_MODER8_MORT ((uint32_t)0x00030000) 03522 #define GPIO_MODER_MODER8_0_MORT ((uint32_t)0x00010000) 03523 #define GPIO_MODER_MODER8_1_MORT ((uint32_t)0x00020000) 03524 03525 #define GPIO_MODER_MODER9_MORT ((uint32_t)0x000C0000) 03526 #define GPIO_MODER_MODER9_0_MORT ((uint32_t)0x00040000) 03527 #define GPIO_MODER_MODER9_1_MORT ((uint32_t)0x00080000) 03528 03529 #define GPIO_MODER_MODER10_MORT ((uint32_t)0x00300000) 03530 #define GPIO_MODER_MODER10_0_MORT ((uint32_t)0x00100000) 03531 #define GPIO_MODER_MODER10_1_MORT ((uint32_t)0x00200000) 03532 03533 #define GPIO_MODER_MODER11_MORT ((uint32_t)0x00C00000) 03534 #define GPIO_MODER_MODER11_0_MORT ((uint32_t)0x00400000) 03535 #define GPIO_MODER_MODER11_1_MORT ((uint32_t)0x00800000) 03536 03537 #define GPIO_MODER_MODER12_MORT ((uint32_t)0x03000000) 03538 #define GPIO_MODER_MODER12_0_MORT ((uint32_t)0x01000000) 03539 #define GPIO_MODER_MODER12_1_MORT ((uint32_t)0x02000000) 03540 03541 #define GPIO_MODER_MODER13_MORT ((uint32_t)0x0C000000) 03542 #define GPIO_MODER_MODER13_0_MORT ((uint32_t)0x04000000) 03543 #define GPIO_MODER_MODER13_1_MORT ((uint32_t)0x08000000) 03544 03545 #define GPIO_MODER_MODER14_MORT ((uint32_t)0x30000000) 03546 #define GPIO_MODER_MODER14_0_MORT ((uint32_t)0x10000000) 03547 #define GPIO_MODER_MODER14_1_MORT ((uint32_t)0x20000000) 03548 03549 #define GPIO_MODER_MODER15_MORT ((uint32_t)0xC0000000) 03550 #define GPIO_MODER_MODER15_0_MORT ((uint32_t)0x40000000) 03551 #define GPIO_MODER_MODER15_1_MORT ((uint32_t)0x80000000) 03552 03553 /****************** Bits definition for GPIO_OTYPER register ****************/ 03554 #define GPIO_OTYPER_OT_0_MORT ((uint32_t)0x00000001) 03555 #define GPIO_OTYPER_OT_1_MORT ((uint32_t)0x00000002) 03556 #define GPIO_OTYPER_OT_2_MORT ((uint32_t)0x00000004) 03557 #define GPIO_OTYPER_OT_3_MORT ((uint32_t)0x00000008) 03558 #define GPIO_OTYPER_OT_4_MORT ((uint32_t)0x00000010) 03559 #define GPIO_OTYPER_OT_5_MORT ((uint32_t)0x00000020) 03560 #define GPIO_OTYPER_OT_6_MORT ((uint32_t)0x00000040) 03561 #define GPIO_OTYPER_OT_7_MORT ((uint32_t)0x00000080) 03562 #define GPIO_OTYPER_OT_8_MORT ((uint32_t)0x00000100) 03563 #define GPIO_OTYPER_OT_9_MORT ((uint32_t)0x00000200) 03564 #define GPIO_OTYPER_OT_10_MORT ((uint32_t)0x00000400) 03565 #define GPIO_OTYPER_OT_11_MORT ((uint32_t)0x00000800) 03566 #define GPIO_OTYPER_OT_12_MORT ((uint32_t)0x00001000) 03567 #define GPIO_OTYPER_OT_13_MORT ((uint32_t)0x00002000) 03568 #define GPIO_OTYPER_OT_14_MORT ((uint32_t)0x00004000) 03569 #define GPIO_OTYPER_OT_15_MORT ((uint32_t)0x00008000) 03570 03571 /****************** Bits definition for GPIO_OSPEEDR register ***************/ 03572 #define GPIO_OSPEEDER_OSPEEDR0_MORT ((uint32_t)0x00000003) 03573 #define GPIO_OSPEEDER_OSPEEDR0_0_MORT ((uint32_t)0x00000001) 03574 #define GPIO_OSPEEDER_OSPEEDR0_1_MORT ((uint32_t)0x00000002) 03575 03576 #define GPIO_OSPEEDER_OSPEEDR1_MORT ((uint32_t)0x0000000C) 03577 #define GPIO_OSPEEDER_OSPEEDR1_0_MORT ((uint32_t)0x00000004) 03578 #define GPIO_OSPEEDER_OSPEEDR1_1_MORT ((uint32_t)0x00000008) 03579 03580 #define GPIO_OSPEEDER_OSPEEDR2_MORT ((uint32_t)0x00000030) 03581 #define GPIO_OSPEEDER_OSPEEDR2_0_MORT ((uint32_t)0x00000010) 03582 #define GPIO_OSPEEDER_OSPEEDR2_1_MORT ((uint32_t)0x00000020) 03583 03584 #define GPIO_OSPEEDER_OSPEEDR3_MORT ((uint32_t)0x000000C0) 03585 #define GPIO_OSPEEDER_OSPEEDR3_0_MORT ((uint32_t)0x00000040) 03586 #define GPIO_OSPEEDER_OSPEEDR3_1_MORT ((uint32_t)0x00000080) 03587 03588 #define GPIO_OSPEEDER_OSPEEDR4_MORT ((uint32_t)0x00000300) 03589 #define GPIO_OSPEEDER_OSPEEDR4_0_MORT ((uint32_t)0x00000100) 03590 #define GPIO_OSPEEDER_OSPEEDR4_1_MORT ((uint32_t)0x00000200) 03591 03592 #define GPIO_OSPEEDER_OSPEEDR5_MORT ((uint32_t)0x00000C00) 03593 #define GPIO_OSPEEDER_OSPEEDR5_0_MORT ((uint32_t)0x00000400) 03594 #define GPIO_OSPEEDER_OSPEEDR5_1_MORT ((uint32_t)0x00000800) 03595 03596 #define GPIO_OSPEEDER_OSPEEDR6_MORT ((uint32_t)0x00003000) 03597 #define GPIO_OSPEEDER_OSPEEDR6_0_MORT ((uint32_t)0x00001000) 03598 #define GPIO_OSPEEDER_OSPEEDR6_1_MORT ((uint32_t)0x00002000) 03599 03600 #define GPIO_OSPEEDER_OSPEEDR7_MORT ((uint32_t)0x0000C000) 03601 #define GPIO_OSPEEDER_OSPEEDR7_0_MORT ((uint32_t)0x00004000) 03602 #define GPIO_OSPEEDER_OSPEEDR7_1_MORT ((uint32_t)0x00008000) 03603 03604 #define GPIO_OSPEEDER_OSPEEDR8_MORT ((uint32_t)0x00030000) 03605 #define GPIO_OSPEEDER_OSPEEDR8_0_MORT ((uint32_t)0x00010000) 03606 #define GPIO_OSPEEDER_OSPEEDR8_1_MORT ((uint32_t)0x00020000) 03607 03608 #define GPIO_OSPEEDER_OSPEEDR9_MORT ((uint32_t)0x000C0000) 03609 #define GPIO_OSPEEDER_OSPEEDR9_0_MORT ((uint32_t)0x00040000) 03610 #define GPIO_OSPEEDER_OSPEEDR9_1_MORT ((uint32_t)0x00080000) 03611 03612 #define GPIO_OSPEEDER_OSPEEDR10_MORT ((uint32_t)0x00300000) 03613 #define GPIO_OSPEEDER_OSPEEDR10_0_MORT ((uint32_t)0x00100000) 03614 #define GPIO_OSPEEDER_OSPEEDR10_1_MORT ((uint32_t)0x00200000) 03615 03616 #define GPIO_OSPEEDER_OSPEEDR11_MORT ((uint32_t)0x00C00000) 03617 #define GPIO_OSPEEDER_OSPEEDR11_0_MORT ((uint32_t)0x00400000) 03618 #define GPIO_OSPEEDER_OSPEEDR11_1_MORT ((uint32_t)0x00800000) 03619 03620 #define GPIO_OSPEEDER_OSPEEDR12_MORT ((uint32_t)0x03000000) 03621 #define GPIO_OSPEEDER_OSPEEDR12_0_MORT ((uint32_t)0x01000000) 03622 #define GPIO_OSPEEDER_OSPEEDR12_1_MORT ((uint32_t)0x02000000) 03623 03624 #define GPIO_OSPEEDER_OSPEEDR13_MORT ((uint32_t)0x0C000000) 03625 #define GPIO_OSPEEDER_OSPEEDR13_0_MORT ((uint32_t)0x04000000) 03626 #define GPIO_OSPEEDER_OSPEEDR13_1_MORT ((uint32_t)0x08000000) 03627 03628 #define GPIO_OSPEEDER_OSPEEDR14_MORT ((uint32_t)0x30000000) 03629 #define GPIO_OSPEEDER_OSPEEDR14_0_MORT ((uint32_t)0x10000000) 03630 #define GPIO_OSPEEDER_OSPEEDR14_1_MORT ((uint32_t)0x20000000) 03631 03632 #define GPIO_OSPEEDER_OSPEEDR15_MORT ((uint32_t)0xC0000000) 03633 #define GPIO_OSPEEDER_OSPEEDR15_0_MORT ((uint32_t)0x40000000) 03634 #define GPIO_OSPEEDER_OSPEEDR15_1_MORT ((uint32_t)0x80000000) 03635 03636 /****************** Bits definition for GPIO_PUPDR register *****************/ 03637 #define GPIO_PUPDR_PUPDR0_MORT ((uint32_t)0x00000003) 03638 #define GPIO_PUPDR_PUPDR0_0_MORT ((uint32_t)0x00000001) 03639 #define GPIO_PUPDR_PUPDR0_1_MORT ((uint32_t)0x00000002) 03640 03641 #define GPIO_PUPDR_PUPDR1_MORT ((uint32_t)0x0000000C) 03642 #define GPIO_PUPDR_PUPDR1_0_MORT ((uint32_t)0x00000004) 03643 #define GPIO_PUPDR_PUPDR1_1_MORT ((uint32_t)0x00000008) 03644 03645 #define GPIO_PUPDR_PUPDR2_MORT ((uint32_t)0x00000030) 03646 #define GPIO_PUPDR_PUPDR2_0_MORT ((uint32_t)0x00000010) 03647 #define GPIO_PUPDR_PUPDR2_1_MORT ((uint32_t)0x00000020) 03648 03649 #define GPIO_PUPDR_PUPDR3_MORT ((uint32_t)0x000000C0) 03650 #define GPIO_PUPDR_PUPDR3_0_MORT ((uint32_t)0x00000040) 03651 #define GPIO_PUPDR_PUPDR3_1_MORT ((uint32_t)0x00000080) 03652 03653 #define GPIO_PUPDR_PUPDR4_MORT ((uint32_t)0x00000300) 03654 #define GPIO_PUPDR_PUPDR4_0_MORT ((uint32_t)0x00000100) 03655 #define GPIO_PUPDR_PUPDR4_1_MORT ((uint32_t)0x00000200) 03656 03657 #define GPIO_PUPDR_PUPDR5_MORT ((uint32_t)0x00000C00) 03658 #define GPIO_PUPDR_PUPDR5_0_MORT ((uint32_t)0x00000400) 03659 #define GPIO_PUPDR_PUPDR5_1_MORT ((uint32_t)0x00000800) 03660 03661 #define GPIO_PUPDR_PUPDR6_MORT ((uint32_t)0x00003000) 03662 #define GPIO_PUPDR_PUPDR6_0_MORT ((uint32_t)0x00001000) 03663 #define GPIO_PUPDR_PUPDR6_1_MORT ((uint32_t)0x00002000) 03664 03665 #define GPIO_PUPDR_PUPDR7_MORT ((uint32_t)0x0000C000) 03666 #define GPIO_PUPDR_PUPDR7_0_MORT ((uint32_t)0x00004000) 03667 #define GPIO_PUPDR_PUPDR7_1_MORT ((uint32_t)0x00008000) 03668 03669 #define GPIO_PUPDR_PUPDR8_MORT ((uint32_t)0x00030000) 03670 #define GPIO_PUPDR_PUPDR8_0_MORT ((uint32_t)0x00010000) 03671 #define GPIO_PUPDR_PUPDR8_1_MORT ((uint32_t)0x00020000) 03672 03673 #define GPIO_PUPDR_PUPDR9_MORT ((uint32_t)0x000C0000) 03674 #define GPIO_PUPDR_PUPDR9_0_MORT ((uint32_t)0x00040000) 03675 #define GPIO_PUPDR_PUPDR9_1_MORT ((uint32_t)0x00080000) 03676 03677 #define GPIO_PUPDR_PUPDR10_MORT ((uint32_t)0x00300000) 03678 #define GPIO_PUPDR_PUPDR10_0_MORT ((uint32_t)0x00100000) 03679 #define GPIO_PUPDR_PUPDR10_1_MORT ((uint32_t)0x00200000) 03680 03681 #define GPIO_PUPDR_PUPDR11_MORT ((uint32_t)0x00C00000) 03682 #define GPIO_PUPDR_PUPDR11_0_MORT ((uint32_t)0x00400000) 03683 #define GPIO_PUPDR_PUPDR11_1_MORT ((uint32_t)0x00800000) 03684 03685 #define GPIO_PUPDR_PUPDR12_MORT ((uint32_t)0x03000000) 03686 #define GPIO_PUPDR_PUPDR12_0_MORT ((uint32_t)0x01000000) 03687 #define GPIO_PUPDR_PUPDR12_1_MORT ((uint32_t)0x02000000) 03688 03689 #define GPIO_PUPDR_PUPDR13_MORT ((uint32_t)0x0C000000) 03690 #define GPIO_PUPDR_PUPDR13_0_MORT ((uint32_t)0x04000000) 03691 #define GPIO_PUPDR_PUPDR13_1_MORT ((uint32_t)0x08000000) 03692 03693 #define GPIO_PUPDR_PUPDR14_MORT ((uint32_t)0x30000000) 03694 #define GPIO_PUPDR_PUPDR14_0_MORT ((uint32_t)0x10000000) 03695 #define GPIO_PUPDR_PUPDR14_1_MORT ((uint32_t)0x20000000) 03696 03697 #define GPIO_PUPDR_PUPDR15_MORT ((uint32_t)0xC0000000) 03698 #define GPIO_PUPDR_PUPDR15_0_MORT ((uint32_t)0x40000000) 03699 #define GPIO_PUPDR_PUPDR15_1_MORT ((uint32_t)0x80000000) 03700 03701 /****************** Bits definition for GPIO_IDR register *******************/ 03702 #define GPIO_IDR_IDR_0_MORT ((uint32_t)0x00000001) 03703 #define GPIO_IDR_IDR_1_MORT ((uint32_t)0x00000002) 03704 #define GPIO_IDR_IDR_2_MORT ((uint32_t)0x00000004) 03705 #define GPIO_IDR_IDR_3_MORT ((uint32_t)0x00000008) 03706 #define GPIO_IDR_IDR_4_MORT ((uint32_t)0x00000010) 03707 #define GPIO_IDR_IDR_5_MORT ((uint32_t)0x00000020) 03708 #define GPIO_IDR_IDR_6_MORT ((uint32_t)0x00000040) 03709 #define GPIO_IDR_IDR_7_MORT ((uint32_t)0x00000080) 03710 #define GPIO_IDR_IDR_8_MORT ((uint32_t)0x00000100) 03711 #define GPIO_IDR_IDR_9_MORT ((uint32_t)0x00000200) 03712 #define GPIO_IDR_IDR_10_MORT ((uint32_t)0x00000400) 03713 #define GPIO_IDR_IDR_11_MORT ((uint32_t)0x00000800) 03714 #define GPIO_IDR_IDR_12_MORT ((uint32_t)0x00001000) 03715 #define GPIO_IDR_IDR_13_MORT ((uint32_t)0x00002000) 03716 #define GPIO_IDR_IDR_14_MORT ((uint32_t)0x00004000) 03717 #define GPIO_IDR_IDR_15_MORT ((uint32_t)0x00008000) 03718 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */ 03719 #define GPIO_OTYPER_IDR_0_MORT GPIO_IDR_IDR_0_MORT 03720 #define GPIO_OTYPER_IDR_1_MORT GPIO_IDR_IDR_1_MORT 03721 #define GPIO_OTYPER_IDR_2_MORT GPIO_IDR_IDR_2_MORT 03722 #define GPIO_OTYPER_IDR_3_MORT GPIO_IDR_IDR_3_MORT 03723 #define GPIO_OTYPER_IDR_4_MORT GPIO_IDR_IDR_4_MORT 03724 #define GPIO_OTYPER_IDR_5_MORT GPIO_IDR_IDR_5_MORT 03725 #define GPIO_OTYPER_IDR_6_MORT GPIO_IDR_IDR_6_MORT 03726 #define GPIO_OTYPER_IDR_7_MORT GPIO_IDR_IDR_7_MORT 03727 #define GPIO_OTYPER_IDR_8_MORT GPIO_IDR_IDR_8_MORT 03728 #define GPIO_OTYPER_IDR_9_MORT GPIO_IDR_IDR_9_MORT 03729 #define GPIO_OTYPER_IDR_10_MORT GPIO_IDR_IDR_10_MORT 03730 #define GPIO_OTYPER_IDR_11_MORT GPIO_IDR_IDR_11_MORT 03731 #define GPIO_OTYPER_IDR_12_MORT GPIO_IDR_IDR_12_MORT 03732 #define GPIO_OTYPER_IDR_13_MORT GPIO_IDR_IDR_13_MORT 03733 #define GPIO_OTYPER_IDR_14_MORT GPIO_IDR_IDR_14_MORT 03734 #define GPIO_OTYPER_IDR_15_MORT GPIO_IDR_IDR_15_MORT 03735 03736 /****************** Bits definition for GPIO_ODR register *******************/ 03737 #define GPIO_ODR_ODR_0_MORT ((uint32_t)0x00000001) 03738 #define GPIO_ODR_ODR_1_MORT ((uint32_t)0x00000002) 03739 #define GPIO_ODR_ODR_2_MORT ((uint32_t)0x00000004) 03740 #define GPIO_ODR_ODR_3_MORT ((uint32_t)0x00000008) 03741 #define GPIO_ODR_ODR_4_MORT ((uint32_t)0x00000010) 03742 #define GPIO_ODR_ODR_5_MORT ((uint32_t)0x00000020) 03743 #define GPIO_ODR_ODR_6_MORT ((uint32_t)0x00000040) 03744 #define GPIO_ODR_ODR_7_MORT ((uint32_t)0x00000080) 03745 #define GPIO_ODR_ODR_8_MORT ((uint32_t)0x00000100) 03746 #define GPIO_ODR_ODR_9_MORT ((uint32_t)0x00000200) 03747 #define GPIO_ODR_ODR_10_MORT ((uint32_t)0x00000400) 03748 #define GPIO_ODR_ODR_11_MORT ((uint32_t)0x00000800) 03749 #define GPIO_ODR_ODR_12_MORT ((uint32_t)0x00001000) 03750 #define GPIO_ODR_ODR_13_MORT ((uint32_t)0x00002000) 03751 #define GPIO_ODR_ODR_14_MORT ((uint32_t)0x00004000) 03752 #define GPIO_ODR_ODR_15_MORT ((uint32_t)0x00008000) 03753 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */ 03754 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0_MORT 03755 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1_MORT 03756 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2_MORT 03757 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3_MORT 03758 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4_MORT 03759 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5_MORT 03760 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6_MORT 03761 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7_MORT 03762 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8_MORT 03763 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9_MORT 03764 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10_MORT 03765 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11_MORT 03766 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12_MORT 03767 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13_MORT 03768 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14_MORT 03769 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15_MORT 03770 03771 /****************** Bits definition for GPIO_BSRR register ******************/ 03772 #define GPIO_BSRR_BS_0_MORT ((uint32_t)0x00000001) 03773 #define GPIO_BSRR_BS_1_MORT ((uint32_t)0x00000002) 03774 #define GPIO_BSRR_BS_2_MORT ((uint32_t)0x00000004) 03775 #define GPIO_BSRR_BS_3_MORT ((uint32_t)0x00000008) 03776 #define GPIO_BSRR_BS_4_MORT ((uint32_t)0x00000010) 03777 #define GPIO_BSRR_BS_5_MORT ((uint32_t)0x00000020) 03778 #define GPIO_BSRR_BS_6_MORT ((uint32_t)0x00000040) 03779 #define GPIO_BSRR_BS_7_MORT ((uint32_t)0x00000080) 03780 #define GPIO_BSRR_BS_8_MORT ((uint32_t)0x00000100) 03781 #define GPIO_BSRR_BS_9_MORT ((uint32_t)0x00000200) 03782 #define GPIO_BSRR_BS_10_MORT ((uint32_t)0x00000400) 03783 #define GPIO_BSRR_BS_11_MORT ((uint32_t)0x00000800) 03784 #define GPIO_BSRR_BS_12_MORT ((uint32_t)0x00001000) 03785 #define GPIO_BSRR_BS_13_MORT ((uint32_t)0x00002000) 03786 #define GPIO_BSRR_BS_14_MORT ((uint32_t)0x00004000) 03787 #define GPIO_BSRR_BS_15_MORT ((uint32_t)0x00008000) 03788 #define GPIO_BSRR_BR_0_MORT ((uint32_t)0x00010000) 03789 #define GPIO_BSRR_BR_1_MORT ((uint32_t)0x00020000) 03790 #define GPIO_BSRR_BR_2_MORT ((uint32_t)0x00040000) 03791 #define GPIO_BSRR_BR_3_MORT ((uint32_t)0x00080000) 03792 #define GPIO_BSRR_BR_4_MORT ((uint32_t)0x00100000) 03793 #define GPIO_BSRR_BR_5_MORT ((uint32_t)0x00200000) 03794 #define GPIO_BSRR_BR_6_MORT ((uint32_t)0x00400000) 03795 #define GPIO_BSRR_BR_7_MORT ((uint32_t)0x00800000) 03796 #define GPIO_BSRR_BR_8_MORT ((uint32_t)0x01000000) 03797 #define GPIO_BSRR_BR_9_MORT ((uint32_t)0x02000000) 03798 #define GPIO_BSRR_BR_10_MORT ((uint32_t)0x04000000) 03799 #define GPIO_BSRR_BR_11_MORT ((uint32_t)0x08000000) 03800 #define GPIO_BSRR_BR_12_MORT ((uint32_t)0x10000000) 03801 #define GPIO_BSRR_BR_13_MORT ((uint32_t)0x20000000) 03802 #define GPIO_BSRR_BR_14_MORT ((uint32_t)0x40000000) 03803 #define GPIO_BSRR_BR_15_MORT ((uint32_t)0x80000000) 03804 03805 /******************************************************************************/ 03806 /* */ 03807 /* HASH_MORT */ 03808 /* */ 03809 /******************************************************************************/ 03810 /****************** Bits definition for HASH_CR register ********************/ 03811 03812 03813 /****************** Bits definition for HASH_STR register *******************/ 03814 03815 03816 /****************** Bits definition for HASH_IMR register *******************/ 03817 03818 03819 /****************** Bits definition for HASH_SR register ********************/ 03820 03821 /******************************************************************************/ 03822 /* */ 03823 /* Inter-integrated Circuit Interface */ 03824 /* */ 03825 /******************************************************************************/ 03826 /******************* Bit definition for I2C_CR1 register ********************/ 03827 03828 /******************* Bit definition for I2C_CR2 register ********************/ 03829 03830 /******************* Bit definition for I2C_OAR1 register *******************/ 03831 03832 /******************* Bit definition for I2C_OAR2 register *******************/ 03833 03834 /******************** Bit definition for I2C_DR register ********************/ 03835 03836 /******************* Bit definition for I2C_SR1 register ********************/ 03837 03838 /******************* Bit definition for I2C_SR2 register ********************/ 03839 03840 /******************* Bit definition for I2C_CCR register ********************/ 03841 03842 /****************** Bit definition for I2C_TRISE register *******************/ 03843 03844 /****************** Bit definition for I2C_FLTR register *******************/ 03845 03846 #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) 03847 /******************************************************************************/ 03848 /* */ 03849 /* Fast-mode Plus Inter-integrated circuit (FMPI2C) */ 03850 /* */ 03851 /******************************************************************************/ 03852 /******************* Bit definition for I2C_CR1 register *******************/ 03853 03854 /****************** Bit definition for I2C_CR2 register ********************/ 03855 03856 /******************* Bit definition for I2C_OAR1 register ******************/ 03857 03858 /******************* Bit definition for I2C_OAR2 register *******************/ 03859 03860 /******************* Bit definition for I2C_TIMINGR register *****************/ 03861 03862 /******************* Bit definition for I2C_TIMEOUTR register *****************/ 03863 03864 /****************** Bit definition for I2C_ISR register *********************/ 03865 03866 /****************** Bit definition for I2C_ICR register *********************/ 03867 03868 /****************** Bit definition for I2C_PECR register ********************/ 03869 03870 /****************** Bit definition for I2C_RXDR register *********************/ 03871 03872 /****************** Bit definition for I2C_TXDR register *********************/ 03873 03874 #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx_MORT */ 03875 /******************************************************************************/ 03876 /* */ 03877 /* Independent WATCHDOG */ 03878 /* */ 03879 /******************************************************************************/ 03880 /******************* Bit definition for IWDG_KR register ********************/ 03881 03882 /******************* Bit definition for IWDG_PR register ********************/ 03883 03884 /******************* Bit definition for IWDG_RLR register *******************/ 03885 03886 /******************* Bit definition for IWDG_SR register ********************/ 03887 03888 /******************************************************************************/ 03889 /* */ 03890 /* LCD-TFT Display Controller (LTDC_MORT) */ 03891 /* */ 03892 /******************************************************************************/ 03893 03894 /******************** Bit definition for LTDC_SSCR register *****************/ 03895 03896 03897 /******************** Bit definition for LTDC_BPCR register *****************/ 03898 03899 03900 /******************** Bit definition for LTDC_AWCR register *****************/ 03901 03902 03903 /******************** Bit definition for LTDC_TWCR register *****************/ 03904 03905 03906 /******************** Bit definition for LTDC_GCR register ******************/ 03907 03908 03909 /* Legacy defines */ 03910 03911 /******************** Bit definition for LTDC_SRCR register *****************/ 03912 03913 03914 /******************** Bit definition for LTDC_BCCR register *****************/ 03915 03916 03917 /******************** Bit definition for LTDC_IER register ******************/ 03918 03919 03920 /******************** Bit definition for LTDC_ISR register ******************/ 03921 03922 03923 /******************** Bit definition for LTDC_ICR register ******************/ 03924 03925 03926 /******************** Bit definition for LTDC_LIPCR register ****************/ 03927 03928 03929 /******************** Bit definition for LTDC_CPSR register *****************/ 03930 03931 03932 /******************** Bit definition for LTDC_CDSR register *****************/ 03933 03934 03935 /******************** Bit definition for LTDC_LxCR register *****************/ 03936 03937 03938 /******************** Bit definition for LTDC_LxWHPCR register **************/ 03939 03940 03941 /******************** Bit definition for LTDC_LxWVPCR register **************/ 03942 03943 03944 /******************** Bit definition for LTDC_LxCKCR register ***************/ 03945 03946 03947 /******************** Bit definition for LTDC_LxPFCR register ***************/ 03948 03949 03950 /******************** Bit definition for LTDC_LxCACR register ***************/ 03951 03952 03953 /******************** Bit definition for LTDC_LxDCCR register ***************/ 03954 03955 03956 /******************** Bit definition for LTDC_LxBFCR register ***************/ 03957 03958 03959 /******************** Bit definition for LTDC_LxCFBAR register **************/ 03960 03961 03962 /******************** Bit definition for LTDC_LxCFBLR register **************/ 03963 03964 03965 /******************** Bit definition for LTDC_LxCFBLNR register *************/ 03966 03967 03968 /******************** Bit definition for LTDC_LxCLUTWR register *************/ 03969 03970 03971 #if defined(STM32F469_479xx) 03972 /******************************************************************************/ 03973 /* */ 03974 /* DSI_MORT */ 03975 /* */ 03976 /******************************************************************************/ 03977 /******************* Bit definition for DSI_VR register *****************/ 03978 03979 03980 /******************* Bit definition for DSI_CR register *****************/ 03981 03982 03983 /******************* Bit definition for DSI_CCR register ****************/ 03984 03985 03986 /******************* Bit definition for DSI_LVCIDR register *************/ 03987 03988 03989 /******************* Bit definition for DSI_LCOLCR register *************/ 03990 03991 03992 03993 /******************* Bit definition for DSI_LPCR register ***************/ 03994 03995 03996 /******************* Bit definition for DSI_LPMCR register **************/ 03997 03998 03999 /******************* Bit definition for DSI_PCR register ****************/ 04000 04001 04002 /******************* Bit definition for DSI_GVCIDR register *************/ 04003 04004 04005 /******************* Bit definition for DSI_MCR register ****************/ 04006 04007 04008 /******************* Bit definition for DSI_VMCR register ***************/ 04009 04010 04011 /******************* Bit definition for DSI_VPCR register ***************/ 04012 04013 04014 /******************* Bit definition for DSI_VCCR register ***************/ 04015 04016 04017 /******************* Bit definition for DSI_VNPCR register **************/ 04018 04019 04020 /******************* Bit definition for DSI_VHSACR register *************/ 04021 04022 04023 /******************* Bit definition for DSI_VHBPCR register *************/ 04024 04025 04026 /******************* Bit definition for DSI_VLCR register ***************/ 04027 04028 /******************* Bit definition for DSI_VVSACR register *************/ 04029 04030 04031 /******************* Bit definition for DSI_VVBPCR register *************/ 04032 04033 04034 /******************* Bit definition for DSI_VVFPCR register *************/ 04035 04036 04037 /******************* Bit definition for DSI_VVACR register **************/ 04038 04039 04040 /******************* Bit definition for DSI_LCCR register ***************/ 04041 04042 04043 /******************* Bit definition for DSI_CMCR register ***************/ 04044 04045 04046 /******************* Bit definition for DSI_GHCR register ***************/ 04047 04048 04049 /******************* Bit definition for DSI_GPDR register ***************/ 04050 04051 04052 /******************* Bit definition for DSI_GPSR register ***************/ 04053 04054 /******************* Bit definition for DSI_TCCR0 register **************/ 04055 04056 04057 /******************* Bit definition for DSI_TCCR1 register **************/ 04058 04059 04060 /******************* Bit definition for DSI_TCCR2 register **************/ 04061 04062 04063 /******************* Bit definition for DSI_TCCR3 register **************/ 04064 04065 04066 /******************* Bit definition for DSI_TCCR4 register **************/ 04067 04068 04069 /******************* Bit definition for DSI_TCCR5 register **************/ 04070 04071 04072 /******************* Bit definition for DSI_TDCR register ***************/ 04073 04074 04075 /******************* Bit definition for DSI_CLCR register ***************/ 04076 04077 04078 /******************* Bit definition for DSI_CLTCR register **************/ 04079 04080 04081 /******************* Bit definition for DSI_DLTCR register **************/ 04082 04083 04084 /******************* Bit definition for DSI_PCTLR register **************/ 04085 04086 04087 /******************* Bit definition for DSI_PCONFR register *************/ 04088 04089 04090 /******************* Bit definition for DSI_PUCR register ***************/ 04091 04092 04093 /******************* Bit definition for DSI_PTTCR register **************/ 04094 04095 04096 /******************* Bit definition for DSI_PSR register ****************/ 04097 04098 04099 /******************* Bit definition for DSI_ISR0 register ***************/ 04100 04101 /******************* Bit definition for DSI_ISR1 register ***************/ 04102 04103 04104 /******************* Bit definition for DSI_IER0 register ***************/ 04105 04106 04107 /******************* Bit definition for DSI_IER1 register ***************/ 04108 04109 04110 /******************* Bit definition for DSI_FIR0 register ***************/ 04111 04112 04113 /******************* Bit definition for DSI_FIR1 register ***************/ 04114 04115 04116 /******************* Bit definition for DSI_VSCR register ***************/ 04117 04118 04119 /******************* Bit definition for DSI_LCVCIDR register ************/ 04120 04121 04122 /******************* Bit definition for DSI_LCCCR register **************/ 04123 04124 04125 /******************* Bit definition for DSI_LPMCCR register *************/ 04126 04127 /******************* Bit definition for DSI_VMCCR register **************/ 04128 04129 04130 /******************* Bit definition for DSI_VPCCR register **************/ 04131 04132 04133 /******************* Bit definition for DSI_VCCCR register **************/ 04134 04135 04136 /******************* Bit definition for DSI_VNPCCR register *************/ 04137 04138 04139 /******************* Bit definition for DSI_VHSACCR register ************/ 04140 04141 04142 /******************* Bit definition for DSI_VHBPCCR register ************/ 04143 04144 04145 /******************* Bit definition for DSI_VLCCR register **************/ 04146 04147 04148 /******************* Bit definition for DSI_VVSACCR register ***************/ 04149 04150 04151 /******************* Bit definition for DSI_VVBPCCR register ************/ 04152 04153 04154 /******************* Bit definition for DSI_VVFPCCR register ************/ 04155 04156 04157 /******************* Bit definition for DSI_VVACCR register *************/ 04158 04159 04160 /******************* Bit definition for DSI_TDCCR register **************/ 04161 04162 04163 /******************* Bit definition for DSI_WCFGR register ***************/ 04164 04165 /******************* Bit definition for DSI_WCR register *****************/ 04166 04167 04168 /******************* Bit definition for DSI_WIER register ****************/ 04169 04170 04171 /******************* Bit definition for DSI_WISR register ****************/ 04172 04173 /******************* Bit definition for DSI_WIFCR register ***************/ 04174 04175 /******************* Bit definition for DSI_WPCR0 register ***************/ 04176 04177 /******************* Bit definition for DSI_WPCR1 register ***************/ 04178 04179 04180 /******************* Bit definition for DSI_WPCR2 register ***************/ 04181 04182 04183 /******************* Bit definition for DSI_WPCR3 register ***************/ 04184 04185 04186 /******************* Bit definition for DSI_WPCR4 register ***************/ 04187 04188 04189 /******************* Bit definition for DSI_WRPCR register ***************/ 04190 04191 #endif /* STM32F469_479xx */ 04192 04193 /******************************************************************************/ 04194 /* */ 04195 /* Power Control */ 04196 /* */ 04197 /******************************************************************************/ 04198 /******************** Bit definition for PWR_CR register ********************/ 04199 04200 /*!< PVD level configuration */ 04201 04202 /* Legacy define */ 04203 04204 /******************* Bit definition for PWR_CSR register ********************/ 04205 04206 /* Legacy define */ 04207 04208 04209 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) 04210 /******************************************************************************/ 04211 /* */ 04212 /* QUADSPI_MORT */ 04213 /* */ 04214 /******************************************************************************/ 04215 /***************** Bit definition for QUADSPI_CR register *******************/ 04216 04217 /***************** Bit definition for QUADSPI_DCR register ******************/ 04218 04219 /****************** Bit definition for QUADSPI_SR register *******************/ 04220 04221 /****************** Bit definition for QUADSPI_FCR register ******************/ 04222 04223 /****************** Bit definition for QUADSPI_DLR register ******************/ 04224 04225 /****************** Bit definition for QUADSPI_CCR register ******************/ 04226 04227 /****************** Bit definition for QUADSPI_AR register *******************/ 04228 04229 /****************** Bit definition for QUADSPI_ABR register ******************/ 04230 04231 /****************** Bit definition for QUADSPI_DR register *******************/ 04232 04233 /****************** Bit definition for QUADSPI_PSMKR register ****************/ 04234 04235 /****************** Bit definition for QUADSPI_PSMAR register ****************/ 04236 04237 /****************** Bit definition for QUADSPI_PIR register *****************/ 04238 04239 /****************** Bit definition for QUADSPI_LPTR register *****************/ 04240 04241 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx_MORT || STM32F469_479xx */ 04242 04243 /******************************************************************************/ 04244 /* */ 04245 /* Reset and Clock Control */ 04246 /* */ 04247 /******************************************************************************/ 04248 /******************** Bit definition for RCC_CR register ********************/ 04249 #define RCC_CR_HSION_MORT ((uint32_t)0x00000001) 04250 #define RCC_CR_HSIRDY_MORT ((uint32_t)0x00000002) 04251 04252 #define RCC_CR_HSITRIM_MORT ((uint32_t)0x000000F8) 04253 #define RCC_CR_HSITRIM_0_MORT ((uint32_t)0x00000008)/*!<Bit 0 */ 04254 #define RCC_CR_HSITRIM_1_MORT ((uint32_t)0x00000010)/*!<Bit 1 */ 04255 #define RCC_CR_HSITRIM_2_MORT ((uint32_t)0x00000020)/*!<Bit 2 */ 04256 #define RCC_CR_HSITRIM_3_MORT ((uint32_t)0x00000040)/*!<Bit 3 */ 04257 #define RCC_CR_HSITRIM_4_MORT ((uint32_t)0x00000080)/*!<Bit 4 */ 04258 04259 #define RCC_CR_HSICAL_MORT ((uint32_t)0x0000FF00) 04260 #define RCC_CR_HSICAL_0_MORT ((uint32_t)0x00000100)/*!<Bit 0 */ 04261 #define RCC_CR_HSICAL_1_MORT ((uint32_t)0x00000200)/*!<Bit 1 */ 04262 #define RCC_CR_HSICAL_2_MORT ((uint32_t)0x00000400)/*!<Bit 2 */ 04263 #define RCC_CR_HSICAL_3_MORT ((uint32_t)0x00000800)/*!<Bit 3 */ 04264 #define RCC_CR_HSICAL_4_MORT ((uint32_t)0x00001000)/*!<Bit 4 */ 04265 #define RCC_CR_HSICAL_5_MORT ((uint32_t)0x00002000)/*!<Bit 5 */ 04266 #define RCC_CR_HSICAL_6_MORT ((uint32_t)0x00004000)/*!<Bit 6 */ 04267 #define RCC_CR_HSICAL_7_MORT ((uint32_t)0x00008000)/*!<Bit 7 */ 04268 04269 #define RCC_CR_HSEON_MORT ((uint32_t)0x00010000) 04270 #define RCC_CR_HSERDY_MORT ((uint32_t)0x00020000) 04271 #define RCC_CR_HSEBYP_MORT ((uint32_t)0x00040000) 04272 #define RCC_CR_CSSON_MORT ((uint32_t)0x00080000) 04273 #define RCC_CR_PLLON_MORT ((uint32_t)0x01000000) 04274 #define RCC_CR_PLLRDY_MORT ((uint32_t)0x02000000) 04275 #define RCC_CR_PLLI2SON_MORT ((uint32_t)0x04000000) 04276 #define RCC_CR_PLLI2SRDY_MORT ((uint32_t)0x08000000) 04277 #define RCC_CR_PLLSAION_MORT ((uint32_t)0x10000000) 04278 #define RCC_CR_PLLSAIRDY_MORT ((uint32_t)0x20000000) 04279 04280 /******************** Bit definition for RCC_PLLCFGR register ***************/ 04281 #define RCC_PLLCFGR_PLLM_MORT ((uint32_t)0x0000003F) 04282 #define RCC_PLLCFGR_PLLM_0_MORT ((uint32_t)0x00000001) 04283 #define RCC_PLLCFGR_PLLM_1_MORT ((uint32_t)0x00000002) 04284 #define RCC_PLLCFGR_PLLM_2_MORT ((uint32_t)0x00000004) 04285 #define RCC_PLLCFGR_PLLM_3_MORT ((uint32_t)0x00000008) 04286 #define RCC_PLLCFGR_PLLM_4_MORT ((uint32_t)0x00000010) 04287 #define RCC_PLLCFGR_PLLM_5_MORT ((uint32_t)0x00000020) 04288 04289 #define RCC_PLLCFGR_PLLN_MORT ((uint32_t)0x00007FC0) 04290 #define RCC_PLLCFGR_PLLN_0_MORT ((uint32_t)0x00000040) 04291 #define RCC_PLLCFGR_PLLN_1_MORT ((uint32_t)0x00000080) 04292 #define RCC_PLLCFGR_PLLN_2_MORT ((uint32_t)0x00000100) 04293 #define RCC_PLLCFGR_PLLN_3_MORT ((uint32_t)0x00000200) 04294 #define RCC_PLLCFGR_PLLN_4_MORT ((uint32_t)0x00000400) 04295 #define RCC_PLLCFGR_PLLN_5_MORT ((uint32_t)0x00000800) 04296 #define RCC_PLLCFGR_PLLN_6_MORT ((uint32_t)0x00001000) 04297 #define RCC_PLLCFGR_PLLN_7_MORT ((uint32_t)0x00002000) 04298 #define RCC_PLLCFGR_PLLN_8_MORT ((uint32_t)0x00004000) 04299 04300 #define RCC_PLLCFGR_PLLP_MORT ((uint32_t)0x00030000) 04301 #define RCC_PLLCFGR_PLLP_0_MORT ((uint32_t)0x00010000) 04302 #define RCC_PLLCFGR_PLLP_1_MORT ((uint32_t)0x00020000) 04303 04304 #define RCC_PLLCFGR_PLLSRC_MORT ((uint32_t)0x00400000) 04305 #define RCC_PLLCFGR_PLLSRC_HSE_MORT ((uint32_t)0x00400000) 04306 #define RCC_PLLCFGR_PLLSRC_HSI_MORT ((uint32_t)0x00000000) 04307 04308 #define RCC_PLLCFGR_PLLQ_MORT ((uint32_t)0x0F000000) 04309 #define RCC_PLLCFGR_PLLQ_0_MORT ((uint32_t)0x01000000) 04310 #define RCC_PLLCFGR_PLLQ_1_MORT ((uint32_t)0x02000000) 04311 #define RCC_PLLCFGR_PLLQ_2_MORT ((uint32_t)0x04000000) 04312 #define RCC_PLLCFGR_PLLQ_3_MORT ((uint32_t)0x08000000) 04313 04314 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) 04315 #define RCC_PLLCFGR_PLLR_MORT ((uint32_t)0x70000000) 04316 #define RCC_PLLCFGR_PLLR_0_MORT ((uint32_t)0x10000000) 04317 #define RCC_PLLCFGR_PLLR_1_MORT ((uint32_t)0x20000000) 04318 #define RCC_PLLCFGR_PLLR_2_MORT ((uint32_t)0x40000000) 04319 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx_MORT || STM32F469_479xx */ 04320 04321 /******************** Bit definition for RCC_CFGR register ******************/ 04322 /*!< SW configuration */ 04323 #define RCC_CFGR_SW_MORT ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ 04324 #define RCC_CFGR_SW_0_MORT ((uint32_t)0x00000001) /*!< Bit 0 */ 04325 #define RCC_CFGR_SW_1_MORT ((uint32_t)0x00000002) /*!< Bit 1 */ 04326 04327 #define RCC_CFGR_SW_HSI_MORT ((uint32_t)0x00000000) /*!< HSI selected as system clock */ 04328 #define RCC_CFGR_SW_HSE_MORT ((uint32_t)0x00000001) /*!< HSE selected as system clock */ 04329 #define RCC_CFGR_SW_PLL_MORT ((uint32_t)0x00000002) /*!< PLL/PLLP selected as system clock */ 04330 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) 04331 #define RCC_CFGR_SW_PLLR_MORT ((uint32_t)0x00000003) /*!< PLL/PLLR selected as system clock */ 04332 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx_MORT || STM32F469_479xx */ 04333 04334 /*!< SWS configuration */ 04335 #define RCC_CFGR_SWS_MORT ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ 04336 #define RCC_CFGR_SWS_0_MORT ((uint32_t)0x00000004) /*!< Bit 0 */ 04337 #define RCC_CFGR_SWS_1_MORT ((uint32_t)0x00000008) /*!< Bit 1 */ 04338 04339 #define RCC_CFGR_SWS_HSI_MORT ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ 04340 #define RCC_CFGR_SWS_HSE_MORT ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ 04341 #define RCC_CFGR_SWS_PLL_MORT ((uint32_t)0x00000008) /*!< PLL/PLLP used as system clock */ 04342 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F469_479xx) || defined(STM32F446xx_MORT) 04343 #define RCC_CFGR_SWS_PLLR_MORT ((uint32_t)0x0000000C) /*!< PLL/PLLR used as system clock */ 04344 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx_MORT || STM32F469_479xx */ 04345 04346 /*!< HPRE configuration */ 04347 #define RCC_CFGR_HPRE_MORT ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ 04348 #define RCC_CFGR_HPRE_0_MORT ((uint32_t)0x00000010) /*!< Bit 0 */ 04349 #define RCC_CFGR_HPRE_1_MORT ((uint32_t)0x00000020) /*!< Bit 1 */ 04350 #define RCC_CFGR_HPRE_2_MORT ((uint32_t)0x00000040) /*!< Bit 2 */ 04351 #define RCC_CFGR_HPRE_3_MORT ((uint32_t)0x00000080) /*!< Bit 3 */ 04352 04353 #define RCC_CFGR_HPRE_DIV1_MORT ((uint32_t)0x00000000) /*!< SYSCLK not divided */ 04354 #define RCC_CFGR_HPRE_DIV2_MORT ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ 04355 #define RCC_CFGR_HPRE_DIV4_MORT ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ 04356 #define RCC_CFGR_HPRE_DIV8_MORT ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ 04357 #define RCC_CFGR_HPRE_DIV16_MORT ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ 04358 #define RCC_CFGR_HPRE_DIV64_MORT ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ 04359 #define RCC_CFGR_HPRE_DIV128_MORT ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ 04360 #define RCC_CFGR_HPRE_DIV256_MORT ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ 04361 #define RCC_CFGR_HPRE_DIV512_MORT ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ 04362 04363 #if defined(STM32F410xx) 04364 /*!< MCO1EN configuration */ 04365 04366 #endif /* STM32F410xx */ 04367 /*!< PPRE1 configuration */ 04368 #define RCC_CFGR_PPRE1_MORT ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */ 04369 #define RCC_CFGR_PPRE1_0_MORT ((uint32_t)0x00000400) /*!< Bit 0 */ 04370 #define RCC_CFGR_PPRE1_1_MORT ((uint32_t)0x00000800) /*!< Bit 1 */ 04371 #define RCC_CFGR_PPRE1_2_MORT ((uint32_t)0x00001000) /*!< Bit 2 */ 04372 04373 #define RCC_CFGR_PPRE1_DIV1_MORT ((uint32_t)0x00000000) /*!< HCLK not divided */ 04374 #define RCC_CFGR_PPRE1_DIV2_MORT ((uint32_t)0x00001000) /*!< HCLK divided by 2 */ 04375 #define RCC_CFGR_PPRE1_DIV4_MORT ((uint32_t)0x00001400) /*!< HCLK divided by 4 */ 04376 #define RCC_CFGR_PPRE1_DIV8_MORT ((uint32_t)0x00001800) /*!< HCLK divided by 8 */ 04377 #define RCC_CFGR_PPRE1_DIV16_MORT ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */ 04378 04379 /*!< PPRE2 configuration */ 04380 #define RCC_CFGR_PPRE2_MORT ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */ 04381 #define RCC_CFGR_PPRE2_0_MORT ((uint32_t)0x00002000) /*!< Bit 0 */ 04382 #define RCC_CFGR_PPRE2_1_MORT ((uint32_t)0x00004000) /*!< Bit 1 */ 04383 #define RCC_CFGR_PPRE2_2_MORT ((uint32_t)0x00008000) /*!< Bit 2 */ 04384 04385 #define RCC_CFGR_PPRE2_DIV1_MORT ((uint32_t)0x00000000) /*!< HCLK not divided */ 04386 #define RCC_CFGR_PPRE2_DIV2_MORT ((uint32_t)0x00008000) /*!< HCLK divided by 2 */ 04387 #define RCC_CFGR_PPRE2_DIV4_MORT ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */ 04388 #define RCC_CFGR_PPRE2_DIV8_MORT ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */ 04389 #define RCC_CFGR_PPRE2_DIV16_MORT ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */ 04390 04391 /*!< RTCPRE configuration */ 04392 #define RCC_CFGR_RTCPRE_MORT ((uint32_t)0x001F0000) 04393 #define RCC_CFGR_RTCPRE_0_MORT ((uint32_t)0x00010000) 04394 #define RCC_CFGR_RTCPRE_1_MORT ((uint32_t)0x00020000) 04395 #define RCC_CFGR_RTCPRE_2_MORT ((uint32_t)0x00040000) 04396 #define RCC_CFGR_RTCPRE_3_MORT ((uint32_t)0x00080000) 04397 #define RCC_CFGR_RTCPRE_4_MORT ((uint32_t)0x00100000) 04398 04399 /*!< MCO1 configuration */ 04400 #define RCC_CFGR_MCO1_MORT ((uint32_t)0x00600000) 04401 #define RCC_CFGR_MCO1_0_MORT ((uint32_t)0x00200000) 04402 #define RCC_CFGR_MCO1_1_MORT ((uint32_t)0x00400000) 04403 04404 #define RCC_CFGR_I2SSRC_MORT ((uint32_t)0x00800000) 04405 04406 #define RCC_CFGR_MCO1PRE_MORT ((uint32_t)0x07000000) 04407 #define RCC_CFGR_MCO1PRE_0_MORT ((uint32_t)0x01000000) 04408 #define RCC_CFGR_MCO1PRE_1_MORT ((uint32_t)0x02000000) 04409 #define RCC_CFGR_MCO1PRE_2_MORT ((uint32_t)0x04000000) 04410 04411 #define RCC_CFGR_MCO2PRE_MORT ((uint32_t)0x38000000) 04412 #define RCC_CFGR_MCO2PRE_0_MORT ((uint32_t)0x08000000) 04413 #define RCC_CFGR_MCO2PRE_1_MORT ((uint32_t)0x10000000) 04414 #define RCC_CFGR_MCO2PRE_2_MORT ((uint32_t)0x20000000) 04415 04416 #define RCC_CFGR_MCO2_MORT ((uint32_t)0xC0000000) 04417 #define RCC_CFGR_MCO2_0_MORT ((uint32_t)0x40000000) 04418 #define RCC_CFGR_MCO2_1_MORT ((uint32_t)0x80000000) 04419 04420 /******************** Bit definition for RCC_CIR register *******************/ 04421 #define RCC_CIR_LSIRDYF_MORT ((uint32_t)0x00000001) 04422 #define RCC_CIR_LSERDYF_MORT ((uint32_t)0x00000002) 04423 #define RCC_CIR_HSIRDYF_MORT ((uint32_t)0x00000004) 04424 #define RCC_CIR_HSERDYF_MORT ((uint32_t)0x00000008) 04425 #define RCC_CIR_PLLRDYF_MORT ((uint32_t)0x00000010) 04426 #define RCC_CIR_PLLI2SRDYF_MORT ((uint32_t)0x00000020) 04427 #define RCC_CIR_PLLSAIRDYF_MORT ((uint32_t)0x00000040) 04428 #define RCC_CIR_CSSF_MORT ((uint32_t)0x00000080) 04429 #define RCC_CIR_LSIRDYIE_MORT ((uint32_t)0x00000100) 04430 #define RCC_CIR_LSERDYIE_MORT ((uint32_t)0x00000200) 04431 #define RCC_CIR_HSIRDYIE_MORT ((uint32_t)0x00000400) 04432 #define RCC_CIR_HSERDYIE_MORT ((uint32_t)0x00000800) 04433 #define RCC_CIR_PLLRDYIE_MORT ((uint32_t)0x00001000) 04434 #define RCC_CIR_PLLI2SRDYIE_MORT ((uint32_t)0x00002000) 04435 #define RCC_CIR_PLLSAIRDYIE_MORT ((uint32_t)0x00004000) 04436 #define RCC_CIR_LSIRDYC_MORT ((uint32_t)0x00010000) 04437 #define RCC_CIR_LSERDYC_MORT ((uint32_t)0x00020000) 04438 #define RCC_CIR_HSIRDYC_MORT ((uint32_t)0x00040000) 04439 #define RCC_CIR_HSERDYC_MORT ((uint32_t)0x00080000) 04440 #define RCC_CIR_PLLRDYC_MORT ((uint32_t)0x00100000) 04441 #define RCC_CIR_PLLI2SRDYC_MORT ((uint32_t)0x00200000) 04442 #define RCC_CIR_PLLSAIRDYC_MORT ((uint32_t)0x00400000) 04443 #define RCC_CIR_CSSC_MORT ((uint32_t)0x00800000) 04444 04445 /******************** Bit definition for RCC_AHB1RSTR register **************/ 04446 #define RCC_AHB1RSTR_GPIOARST_MORT ((uint32_t)0x00000001) 04447 #define RCC_AHB1RSTR_GPIOBRST_MORT ((uint32_t)0x00000002) 04448 #define RCC_AHB1RSTR_GPIOCRST_MORT ((uint32_t)0x00000004) 04449 #define RCC_AHB1RSTR_GPIODRST_MORT ((uint32_t)0x00000008) 04450 #define RCC_AHB1RSTR_GPIOERST_MORT ((uint32_t)0x00000010) 04451 #define RCC_AHB1RSTR_GPIOFRST_MORT ((uint32_t)0x00000020) 04452 #define RCC_AHB1RSTR_GPIOGRST_MORT ((uint32_t)0x00000040) 04453 #define RCC_AHB1RSTR_GPIOHRST_MORT ((uint32_t)0x00000080) 04454 #define RCC_AHB1RSTR_GPIOIRST_MORT ((uint32_t)0x00000100) 04455 #define RCC_AHB1RSTR_GPIOJRST_MORT ((uint32_t)0x00000200) 04456 #define RCC_AHB1RSTR_GPIOKRST_MORT ((uint32_t)0x00000400) 04457 #define RCC_AHB1RSTR_CRCRST_MORT ((uint32_t)0x00001000) 04458 #define RCC_AHB1RSTR_DMA1RST_MORT ((uint32_t)0x00200000) 04459 #define RCC_AHB1RSTR_DMA2RST_MORT ((uint32_t)0x00400000) 04460 #define RCC_AHB1RSTR_DMA2DRST_MORT ((uint32_t)0x00800000) 04461 #define RCC_AHB1RSTR_ETHMACRST_MORT ((uint32_t)0x02000000) 04462 #define RCC_AHB1RSTR_OTGHRST_MORT ((uint32_t)0x10000000) 04463 04464 /******************** Bit definition for RCC_AHB2RSTR register **************/ 04465 #define RCC_AHB2RSTR_DCMIRST_MORT ((uint32_t)0x00000001) 04466 #define RCC_AHB2RSTR_CRYPRST_MORT ((uint32_t)0x00000010) 04467 #define RCC_AHB2RSTR_HASHRST_MORT ((uint32_t)0x00000020) 04468 /* maintained for legacy purpose */ 04469 #define RCC_AHB2RSTR_HSAHRST_MORT RCC_AHB2RSTR_HASHRST_MORT 04470 #define RCC_AHB2RSTR_RNGRST_MORT ((uint32_t)0x00000040) 04471 #define RCC_AHB2RSTR_OTGFSRST_MORT ((uint32_t)0x00000080) 04472 04473 /******************** Bit definition for RCC_AHB3RSTR register **************/ 04474 #if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) 04475 04476 #endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */ 04477 04478 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) 04479 #define RCC_AHB3RSTR_FMCRST_MORT ((uint32_t)0x00000001) 04480 #endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx_MORT || STM32F469_479xx */ 04481 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) 04482 #define RCC_AHB3RSTR_QSPIRST_MORT ((uint32_t)0x00000002) 04483 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx_MORT || STM32F469_479xx */ 04484 04485 /******************** Bit definition for RCC_APB1RSTR register **************/ 04486 #define RCC_APB1RSTR_TIM2RST_MORT ((uint32_t)0x00000001) 04487 #define RCC_APB1RSTR_TIM3RST_MORT ((uint32_t)0x00000002) 04488 #define RCC_APB1RSTR_TIM4RST_MORT ((uint32_t)0x00000004) 04489 #define RCC_APB1RSTR_TIM5RST_MORT ((uint32_t)0x00000008) 04490 #define RCC_APB1RSTR_TIM6RST_MORT ((uint32_t)0x00000010) 04491 #define RCC_APB1RSTR_TIM7RST_MORT ((uint32_t)0x00000020) 04492 #define RCC_APB1RSTR_TIM12RST_MORT ((uint32_t)0x00000040) 04493 #define RCC_APB1RSTR_TIM13RST_MORT ((uint32_t)0x00000080) 04494 #define RCC_APB1RSTR_TIM14RST_MORT ((uint32_t)0x00000100) 04495 #if defined(STM32F410xx) || defined(STM32F413_423xx) 04496 #define RCC_APB1RSTR_LPTIM1RST_MORT ((uint32_t)0x00000200) 04497 #endif /* STM32F410xx || STM32F413_423xx */ 04498 #define RCC_APB1RSTR_WWDGRST_MORT ((uint32_t)0x00000800) 04499 #define RCC_APB1RSTR_SPI2RST_MORT ((uint32_t)0x00004000) 04500 #define RCC_APB1RSTR_SPI3RST_MORT ((uint32_t)0x00008000) 04501 #if defined(STM32F446xx_MORT) 04502 #define RCC_APB1RSTR_SPDIFRXRST_MORT ((uint32_t)0x00010000) 04503 #endif /* STM32F446xx_MORT */ 04504 #define RCC_APB1RSTR_USART2RST_MORT ((uint32_t)0x00020000) 04505 #define RCC_APB1RSTR_USART3RST_MORT ((uint32_t)0x00040000) 04506 #define RCC_APB1RSTR_UART4RST_MORT ((uint32_t)0x00080000) 04507 #define RCC_APB1RSTR_UART5RST_MORT ((uint32_t)0x00100000) 04508 #define RCC_APB1RSTR_I2C1RST_MORT ((uint32_t)0x00200000) 04509 #define RCC_APB1RSTR_I2C2RST_MORT ((uint32_t)0x00400000) 04510 #define RCC_APB1RSTR_I2C3RST_MORT ((uint32_t)0x00800000) 04511 #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) 04512 #define RCC_APB1RSTR_FMPI2C1RST_MORT ((uint32_t)0x01000000) 04513 #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx_MORT */ 04514 #define RCC_APB1RSTR_CAN1RST_MORT ((uint32_t)0x02000000) 04515 #define RCC_APB1RSTR_CAN2RST_MORT ((uint32_t)0x04000000) 04516 #if defined(STM32F446xx_MORT) 04517 #define RCC_APB1RSTR_CECRST_MORT ((uint32_t)0x08000000) 04518 #endif /* STM32F446xx_MORT */ 04519 #define RCC_APB1RSTR_PWRRST_MORT ((uint32_t)0x10000000) 04520 #define RCC_APB1RSTR_DACRST_MORT ((uint32_t)0x20000000) 04521 #define RCC_APB1RSTR_UART7RST_MORT ((uint32_t)0x40000000) 04522 #define RCC_APB1RSTR_UART8RST_MORT ((uint32_t)0x80000000) 04523 04524 /******************** Bit definition for RCC_APB2RSTR register **************/ 04525 #define RCC_APB2RSTR_TIM1RST_MORT ((uint32_t)0x00000001) 04526 #define RCC_APB2RSTR_TIM8RST_MORT ((uint32_t)0x00000002) 04527 #define RCC_APB2RSTR_USART1RST_MORT ((uint32_t)0x00000010) 04528 #define RCC_APB2RSTR_USART6RST_MORT ((uint32_t)0x00000020) 04529 #define RCC_APB2RSTR_UART9RST_MORT ((uint32_t)0x00000040) 04530 #define RCC_APB2RSTR_UART10RST_MORT ((uint32_t)0x00000080) 04531 #define RCC_APB2RSTR_ADCRST_MORT ((uint32_t)0x00000100) 04532 #define RCC_APB2RSTR_SDIORST_MORT ((uint32_t)0x00000800) 04533 #define RCC_APB2RSTR_SPI1RST_MORT ((uint32_t)0x00001000) 04534 #define RCC_APB2RSTR_SPI4RST_MORT ((uint32_t)0x00002000) 04535 #define RCC_APB2RSTR_SYSCFGRST_MORT ((uint32_t)0x00004000) 04536 #define RCC_APB2RSTR_TIM9RST_MORT ((uint32_t)0x00010000) 04537 #define RCC_APB2RSTR_TIM10RST_MORT ((uint32_t)0x00020000) 04538 #define RCC_APB2RSTR_TIM11RST_MORT ((uint32_t)0x00040000) 04539 #define RCC_APB2RSTR_SPI5RST_MORT ((uint32_t)0x00100000) 04540 #define RCC_APB2RSTR_SPI6RST_MORT ((uint32_t)0x00200000) 04541 #define RCC_APB2RSTR_SAI1RST_MORT ((uint32_t)0x00400000) 04542 #if defined(STM32F446xx_MORT) 04543 #define RCC_APB2RSTR_SAI2RST_MORT ((uint32_t)0x00800000) 04544 #endif /* STM32F446xx_MORT */ 04545 #define RCC_APB2RSTR_LTDCRST_MORT ((uint32_t)0x04000000) 04546 #if defined(STM32F469_479xx) 04547 #define RCC_APB2RSTR_DSIRST_MORT ((uint32_t)0x08000000) 04548 #endif /* STM32F469_479xx */ 04549 #if defined(STM32F412xG) || defined(STM32F413_423xx) 04550 #define RCC_APB2RSTR_DFSDM1RST_MORT ((uint32_t)0x01000000) 04551 #endif /* STM32F412xG || STM32F413_423xx */ 04552 04553 #if defined(STM32F413_423xx) 04554 #define RCC_APB2RSTR_DFSDM2RST_MORT ((uint32_t)0x02000000) 04555 #endif /* STM32F413_423xx */ 04556 /* Old definitions, maintained for legacy purpose */ 04557 #define RCC_APB2RSTR_SPI1_MORT RCC_APB2RSTR_SPI1RST_MORT 04558 #define RCC_APB2RSTR_DFSDMRST RCC_APB2RSTR_DFSDM1RST_MORT 04559 04560 /******************** Bit definition for RCC_AHB1ENR register ***************/ 04561 #define RCC_AHB1ENR_GPIOAEN_MORT ((uint32_t)0x00000001) 04562 #define RCC_AHB1ENR_GPIOBEN_MORT ((uint32_t)0x00000002) 04563 #define RCC_AHB1ENR_GPIOCEN_MORT ((uint32_t)0x00000004) 04564 #define RCC_AHB1ENR_GPIODEN_MORT ((uint32_t)0x00000008) 04565 #define RCC_AHB1ENR_GPIOEEN_MORT ((uint32_t)0x00000010) 04566 #define RCC_AHB1ENR_GPIOFEN_MORT ((uint32_t)0x00000020) 04567 #define RCC_AHB1ENR_GPIOGEN_MORT ((uint32_t)0x00000040) 04568 #define RCC_AHB1ENR_GPIOHEN_MORT ((uint32_t)0x00000080) 04569 #define RCC_AHB1ENR_GPIOIEN_MORT ((uint32_t)0x00000100) 04570 #define RCC_AHB1ENR_GPIOJEN_MORT ((uint32_t)0x00000200) 04571 #define RCC_AHB1ENR_GPIOKEN_MORT ((uint32_t)0x00000400) 04572 #define RCC_AHB1ENR_CRCEN_MORT ((uint32_t)0x00001000) 04573 #define RCC_AHB1ENR_BKPSRAMEN_MORT ((uint32_t)0x00040000) 04574 #define RCC_AHB1ENR_CCMDATARAMEN_MORT ((uint32_t)0x00100000) 04575 #define RCC_AHB1ENR_DMA1EN_MORT ((uint32_t)0x00200000) 04576 #define RCC_AHB1ENR_DMA2EN_MORT ((uint32_t)0x00400000) 04577 #define RCC_AHB1ENR_DMA2DEN_MORT ((uint32_t)0x00800000) 04578 #define RCC_AHB1ENR_ETHMACEN_MORT ((uint32_t)0x02000000) 04579 #define RCC_AHB1ENR_ETHMACTXEN_MORT ((uint32_t)0x04000000) 04580 #define RCC_AHB1ENR_ETHMACRXEN_MORT ((uint32_t)0x08000000) 04581 #define RCC_AHB1ENR_ETHMACPTPEN_MORT ((uint32_t)0x10000000) 04582 #define RCC_AHB1ENR_OTGHSEN_MORT ((uint32_t)0x20000000) 04583 #define RCC_AHB1ENR_OTGHSULPIEN_MORT ((uint32_t)0x40000000) 04584 04585 /******************** Bit definition for RCC_AHB2ENR register ***************/ 04586 #define RCC_AHB2ENR_DCMIEN_MORT ((uint32_t)0x00000001) 04587 #define RCC_AHB2ENR_CRYPEN_MORT ((uint32_t)0x00000010) 04588 #define RCC_AHB2ENR_HASHEN_MORT ((uint32_t)0x00000020) 04589 #define RCC_AHB2ENR_RNGEN_MORT ((uint32_t)0x00000040) 04590 #define RCC_AHB2ENR_OTGFSEN_MORT ((uint32_t)0x00000080) 04591 04592 /******************** Bit definition for RCC_AHB3ENR register ***************/ 04593 04594 #if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) 04595 04596 #endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */ 04597 04598 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) 04599 #define RCC_AHB3ENR_FMCEN_MORT ((uint32_t)0x00000001) 04600 #endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx_MORT || STM32F469_479xx */ 04601 04602 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) 04603 #define RCC_AHB3ENR_QSPIEN_MORT ((uint32_t)0x00000002) 04604 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx_MORT || STM32F469_479xx */ 04605 04606 /******************** Bit definition for RCC_APB1ENR register ***************/ 04607 #define RCC_APB1ENR_TIM2EN_MORT ((uint32_t)0x00000001) 04608 #define RCC_APB1ENR_TIM3EN_MORT ((uint32_t)0x00000002) 04609 #define RCC_APB1ENR_TIM4EN_MORT ((uint32_t)0x00000004) 04610 #define RCC_APB1ENR_TIM5EN_MORT ((uint32_t)0x00000008) 04611 #define RCC_APB1ENR_TIM6EN_MORT ((uint32_t)0x00000010) 04612 #define RCC_APB1ENR_TIM7EN_MORT ((uint32_t)0x00000020) 04613 #define RCC_APB1ENR_TIM12EN_MORT ((uint32_t)0x00000040) 04614 #define RCC_APB1ENR_TIM13EN_MORT ((uint32_t)0x00000080) 04615 #define RCC_APB1ENR_TIM14EN_MORT ((uint32_t)0x00000100) 04616 #if defined(STM32F410xx) || defined(STM32F413_423xx) 04617 04618 #endif /* STM32F410xx || STM32F413_423xx */ 04619 #define RCC_APB1ENR_WWDGEN_MORT ((uint32_t)0x00000800) 04620 #define RCC_APB1ENR_SPI2EN_MORT ((uint32_t)0x00004000) 04621 #define RCC_APB1ENR_SPI3EN_MORT ((uint32_t)0x00008000) 04622 #if defined(STM32F446xx_MORT) 04623 #define RCC_APB1ENR_SPDIFRXEN_MORT ((uint32_t)0x00010000) 04624 #endif /* STM32F446xx_MORT */ 04625 #define RCC_APB1ENR_USART2EN_MORT ((uint32_t)0x00020000) 04626 #define RCC_APB1ENR_USART3EN_MORT ((uint32_t)0x00040000) 04627 #define RCC_APB1ENR_UART4EN_MORT ((uint32_t)0x00080000) 04628 #define RCC_APB1ENR_UART5EN_MORT ((uint32_t)0x00100000) 04629 #define RCC_APB1ENR_I2C1EN_MORT ((uint32_t)0x00200000) 04630 #define RCC_APB1ENR_I2C2EN_MORT ((uint32_t)0x00400000) 04631 #define RCC_APB1ENR_I2C3EN_MORT ((uint32_t)0x00800000) 04632 #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) 04633 #define RCC_APB1ENR_FMPI2C1EN_MORT ((uint32_t)0x01000000) 04634 #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx_MORT */ 04635 #define RCC_APB1ENR_CAN1EN_MORT ((uint32_t)0x02000000) 04636 #define RCC_APB1ENR_CAN2EN_MORT ((uint32_t)0x04000000) 04637 #if defined(STM32F446xx_MORT) 04638 #define RCC_APB1ENR_CECEN_MORT ((uint32_t)0x08000000) 04639 #endif /* STM32F446xx_MORT */ 04640 #define RCC_APB1ENR_PWREN_MORT ((uint32_t)0x10000000) 04641 #define RCC_APB1ENR_DACEN_MORT ((uint32_t)0x20000000) 04642 #define RCC_APB1ENR_UART7EN_MORT ((uint32_t)0x40000000) 04643 #define RCC_APB1ENR_UART8EN_MORT ((uint32_t)0x80000000) 04644 04645 /******************** Bit definition for RCC_APB2ENR register ***************/ 04646 #define RCC_APB2ENR_TIM1EN_MORT ((uint32_t)0x00000001) 04647 #define RCC_APB2ENR_TIM8EN_MORT ((uint32_t)0x00000002) 04648 #define RCC_APB2ENR_USART1EN_MORT ((uint32_t)0x00000010) 04649 #define RCC_APB2ENR_USART6EN_MORT ((uint32_t)0x00000020) 04650 #define RCC_APB2ENR_UART9EN_MORT ((uint32_t)0x00000040) 04651 #define RCC_APB2ENR_UART10EN_MORT ((uint32_t)0x00000080) 04652 #define RCC_APB2ENR_ADC1EN_MORT ((uint32_t)0x00000100) 04653 #define RCC_APB2ENR_ADC2EN_MORT ((uint32_t)0x00000200) 04654 #define RCC_APB2ENR_ADC3EN_MORT ((uint32_t)0x00000400) 04655 #define RCC_APB2ENR_SDIOEN_MORT ((uint32_t)0x00000800) 04656 #define RCC_APB2ENR_SPI1EN_MORT ((uint32_t)0x00001000) 04657 #define RCC_APB2ENR_SPI4EN_MORT ((uint32_t)0x00002000) 04658 #define RCC_APB2ENR_SYSCFGEN_MORT ((uint32_t)0x00004000) 04659 #define RCC_APB2ENR_EXTIEN_MORT ((uint32_t)0x00008000) 04660 #define RCC_APB2ENR_TIM9EN_MORT ((uint32_t)0x00010000) 04661 #define RCC_APB2ENR_TIM10EN_MORT ((uint32_t)0x00020000) 04662 #define RCC_APB2ENR_TIM11EN_MORT ((uint32_t)0x00040000) 04663 #define RCC_APB2ENR_SPI5EN_MORT ((uint32_t)0x00100000) 04664 #define RCC_APB2ENR_SPI6EN_MORT ((uint32_t)0x00200000) 04665 #define RCC_APB2ENR_SAI1EN_MORT ((uint32_t)0x00400000) 04666 #if defined(STM32F446xx_MORT) 04667 #define RCC_APB2ENR_SAI2EN_MORT ((uint32_t)0x00800000) 04668 #endif /* STM32F446xx_MORT */ 04669 #define RCC_APB2ENR_LTDCEN_MORT ((uint32_t)0x04000000) 04670 #if defined(STM32F469_479xx) 04671 #define RCC_APB2ENR_DSIEN_MORT ((uint32_t)0x08000000) 04672 #endif /* STM32F469_479xx */ 04673 #if defined(STM32F412xG) || defined(STM32F413_423xx) 04674 #define RCC_APB2ENR_DFSDM1EN_MORT ((uint32_t)0x01000000) 04675 #endif /* STM32F412xG || STM32F413_423xx */ 04676 #if defined(STM32F413_423xx) 04677 #define RCC_APB2ENR_DFSDM2EN_MORT ((uint32_t)0x02000000) 04678 #endif /* STM32F413_423xx */ 04679 /******************** Bit definition for RCC_AHB1LPENR register *************/ 04680 #define RCC_AHB1LPENR_GPIOALPEN_MORT ((uint32_t)0x00000001) 04681 #define RCC_AHB1LPENR_GPIOBLPEN_MORT ((uint32_t)0x00000002) 04682 #define RCC_AHB1LPENR_GPIOCLPEN_MORT ((uint32_t)0x00000004) 04683 #define RCC_AHB1LPENR_GPIODLPEN_MORT ((uint32_t)0x00000008) 04684 #define RCC_AHB1LPENR_GPIOELPEN_MORT ((uint32_t)0x00000010) 04685 #define RCC_AHB1LPENR_GPIOFLPEN_MORT ((uint32_t)0x00000020) 04686 #define RCC_AHB1LPENR_GPIOGLPEN_MORT ((uint32_t)0x00000040) 04687 #define RCC_AHB1LPENR_GPIOHLPEN_MORT ((uint32_t)0x00000080) 04688 #define RCC_AHB1LPENR_GPIOILPEN_MORT ((uint32_t)0x00000100) 04689 #define RCC_AHB1LPENR_GPIOJLPEN_MORT ((uint32_t)0x00000200) 04690 #define RCC_AHB1LPENR_GPIOKLPEN_MORT ((uint32_t)0x00000400) 04691 #define RCC_AHB1LPENR_CRCLPEN_MORT ((uint32_t)0x00001000) 04692 #define RCC_AHB1LPENR_FLITFLPEN_MORT ((uint32_t)0x00008000) 04693 #define RCC_AHB1LPENR_SRAM1LPEN_MORT ((uint32_t)0x00010000) 04694 #define RCC_AHB1LPENR_SRAM2LPEN_MORT ((uint32_t)0x00020000) 04695 #define RCC_AHB1LPENR_BKPSRAMLPEN_MORT ((uint32_t)0x00040000) 04696 #define RCC_AHB1LPENR_SRAM3LPEN_MORT ((uint32_t)0x00080000) 04697 #define RCC_AHB1LPENR_DMA1LPEN_MORT ((uint32_t)0x00200000) 04698 #define RCC_AHB1LPENR_DMA2LPEN_MORT ((uint32_t)0x00400000) 04699 #define RCC_AHB1LPENR_DMA2DLPEN_MORT ((uint32_t)0x00800000) 04700 #define RCC_AHB1LPENR_ETHMACLPEN_MORT ((uint32_t)0x02000000) 04701 #define RCC_AHB1LPENR_ETHMACTXLPEN_MORT ((uint32_t)0x04000000) 04702 #define RCC_AHB1LPENR_ETHMACRXLPEN_MORT ((uint32_t)0x08000000) 04703 #define RCC_AHB1LPENR_ETHMACPTPLPEN_MORT ((uint32_t)0x10000000) 04704 #define RCC_AHB1LPENR_OTGHSLPEN_MORT ((uint32_t)0x20000000) 04705 #define RCC_AHB1LPENR_OTGHSULPILPEN_MORT ((uint32_t)0x40000000) 04706 04707 /******************** Bit definition for RCC_AHB2LPENR register *************/ 04708 #define RCC_AHB2LPENR_DCMILPEN_MORT ((uint32_t)0x00000001) 04709 #define RCC_AHB2LPENR_CRYPLPEN_MORT ((uint32_t)0x00000010) 04710 #define RCC_AHB2LPENR_HASHLPEN_MORT ((uint32_t)0x00000020) 04711 #define RCC_AHB2LPENR_RNGLPEN_MORT ((uint32_t)0x00000040) 04712 #define RCC_AHB2LPENR_OTGFSLPEN_MORT ((uint32_t)0x00000080) 04713 04714 /******************** Bit definition for RCC_AHB3LPENR register *************/ 04715 #if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) 04716 #define RCC_AHB3LPENR_FSMCLPEN_MORT ((uint32_t)0x00000001) 04717 #endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */ 04718 04719 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) 04720 #define RCC_AHB3LPENR_FMCLPEN_MORT ((uint32_t)0x00000001) 04721 #endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx_MORT || STM32F469_479xx */ 04722 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) 04723 #define RCC_AHB3LPENR_QSPILPEN_MORT ((uint32_t)0x00000002) 04724 #endif /* STM32F412xG || STM32F413_423xx || STM32F469_479xx || STM32F446xx_MORT */ 04725 04726 /******************** Bit definition for RCC_APB1LPENR register *************/ 04727 #define RCC_APB1LPENR_TIM2LPEN_MORT ((uint32_t)0x00000001) 04728 #define RCC_APB1LPENR_TIM3LPEN_MORT ((uint32_t)0x00000002) 04729 #define RCC_APB1LPENR_TIM4LPEN_MORT ((uint32_t)0x00000004) 04730 #define RCC_APB1LPENR_TIM5LPEN_MORT ((uint32_t)0x00000008) 04731 #define RCC_APB1LPENR_TIM6LPEN_MORT ((uint32_t)0x00000010) 04732 #define RCC_APB1LPENR_TIM7LPEN_MORT ((uint32_t)0x00000020) 04733 #define RCC_APB1LPENR_TIM12LPEN_MORT ((uint32_t)0x00000040) 04734 #define RCC_APB1LPENR_TIM13LPEN_MORT ((uint32_t)0x00000080) 04735 #define RCC_APB1LPENR_TIM14LPEN_MORT ((uint32_t)0x00000100) 04736 #if defined(STM32F410xx) || defined(STM32F413_423xx) 04737 #define RCC_APB1LPENR_LPTIM1LPEN_MORT ((uint32_t)0x00000200) 04738 #endif /* STM32F410xx || STM32F413_423xx */ 04739 #define RCC_APB1LPENR_WWDGLPEN_MORT ((uint32_t)0x00000800) 04740 #define RCC_APB1LPENR_SPI2LPEN_MORT ((uint32_t)0x00004000) 04741 #define RCC_APB1LPENR_SPI3LPEN_MORT ((uint32_t)0x00008000) 04742 #if defined(STM32F446xx_MORT) 04743 #define RCC_APB1LPENR_SPDIFRXLPEN_MORT ((uint32_t)0x00010000) 04744 #endif /* STM32F446xx_MORT */ 04745 #define RCC_APB1LPENR_USART2LPEN_MORT ((uint32_t)0x00020000) 04746 #define RCC_APB1LPENR_USART3LPEN_MORT ((uint32_t)0x00040000) 04747 #define RCC_APB1LPENR_UART4LPEN_MORT ((uint32_t)0x00080000) 04748 #define RCC_APB1LPENR_UART5LPEN_MORT ((uint32_t)0x00100000) 04749 #define RCC_APB1LPENR_I2C1LPEN_MORT ((uint32_t)0x00200000) 04750 #define RCC_APB1LPENR_I2C2LPEN_MORT ((uint32_t)0x00400000) 04751 #define RCC_APB1LPENR_I2C3LPEN_MORT ((uint32_t)0x00800000) 04752 #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) 04753 #define RCC_APB1LPENR_FMPI2C1LPEN_MORT ((uint32_t)0x01000000) 04754 #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx_MORT */ 04755 #define RCC_APB1LPENR_CAN1LPEN_MORT ((uint32_t)0x02000000) 04756 #define RCC_APB1LPENR_CAN2LPEN_MORT ((uint32_t)0x04000000) 04757 #if defined(STM32F446xx_MORT) 04758 #define RCC_APB1LPENR_CECLPEN_MORT ((uint32_t)0x08000000) 04759 #endif /* STM32F446xx_MORT */ 04760 #define RCC_APB1LPENR_PWRLPEN_MORT ((uint32_t)0x10000000) 04761 #define RCC_APB1LPENR_DACLPEN_MORT ((uint32_t)0x20000000) 04762 #define RCC_APB1LPENR_UART7LPEN_MORT ((uint32_t)0x40000000) 04763 #define RCC_APB1LPENR_UART8LPEN_MORT ((uint32_t)0x80000000) 04764 04765 /******************** Bit definition for RCC_APB2LPENR register *************/ 04766 #define RCC_APB2LPENR_TIM1LPEN_MORT ((uint32_t)0x00000001) 04767 #define RCC_APB2LPENR_TIM8LPEN_MORT ((uint32_t)0x00000002) 04768 #define RCC_APB2LPENR_USART1LPEN_MORT ((uint32_t)0x00000010) 04769 #define RCC_APB2LPENR_USART6LPEN_MORT ((uint32_t)0x00000020) 04770 #define RCC_APB2LPENR_UART9LPEN_MORT ((uint32_t)0x00000040) 04771 #define RCC_APB2LPENR_UART10LPEN_MORT ((uint32_t)0x00000080) 04772 #define RCC_APB2LPENR_ADC1LPEN_MORT ((uint32_t)0x00000100) 04773 #define RCC_APB2LPENR_ADC2PEN_MORT ((uint32_t)0x00000200) 04774 #define RCC_APB2LPENR_ADC3LPEN_MORT ((uint32_t)0x00000400) 04775 #define RCC_APB2LPENR_SDIOLPEN_MORT ((uint32_t)0x00000800) 04776 #define RCC_APB2LPENR_SPI1LPEN_MORT ((uint32_t)0x00001000) 04777 #define RCC_APB2LPENR_SPI4LPEN_MORT ((uint32_t)0x00002000) 04778 #define RCC_APB2LPENR_SYSCFGLPEN_MORT ((uint32_t)0x00004000) 04779 #define RCC_APB2LPENR_TIM9LPEN_MORT ((uint32_t)0x00010000) 04780 #define RCC_APB2LPENR_TIM10LPEN_MORT ((uint32_t)0x00020000) 04781 #define RCC_APB2LPENR_TIM11LPEN_MORT ((uint32_t)0x00040000) 04782 #define RCC_APB2LPENR_SPI5LPEN_MORT ((uint32_t)0x00100000) 04783 #define RCC_APB2LPENR_SPI6LPEN_MORT ((uint32_t)0x00200000) 04784 #define RCC_APB2LPENR_SAI1LPEN_MORT ((uint32_t)0x00400000) 04785 #if defined(STM32F446xx_MORT) 04786 #define RCC_APB2LPENR_SAI2LPEN_MORT ((uint32_t)0x00800000) 04787 #endif /* STM32F446xx_MORT */ 04788 #define RCC_APB2LPENR_LTDCLPEN_MORT ((uint32_t)0x04000000) 04789 #if defined(STM32F469_479xx) 04790 04791 #endif /* STM32F469_479xx */ 04792 #if defined(STM32F412xG) || defined(STM32F413_423xx) 04793 04794 #endif /* STM32F412xG || STM32F413_423xx */ 04795 #if defined(STM32F413_423xx) 04796 04797 #endif /* STM32F413_423xx */ 04798 04799 /******************** Bit definition for RCC_BDCR register ******************/ 04800 #define RCC_BDCR_LSEON_MORT ((uint32_t)0x00000001) 04801 #define RCC_BDCR_LSERDY_MORT ((uint32_t)0x00000002) 04802 #define RCC_BDCR_LSEBYP_MORT ((uint32_t)0x00000004) 04803 #define RCC_BDCR_LSEMOD_MORT ((uint32_t)0x00000008) 04804 04805 #define RCC_BDCR_RTCSEL_MORT ((uint32_t)0x00000300) 04806 #define RCC_BDCR_RTCSEL_0_MORT ((uint32_t)0x00000100) 04807 #define RCC_BDCR_RTCSEL_1_MORT ((uint32_t)0x00000200) 04808 04809 #define RCC_BDCR_RTCEN_MORT ((uint32_t)0x00008000) 04810 #define RCC_BDCR_BDRST_MORT ((uint32_t)0x00010000) 04811 04812 /******************** Bit definition for RCC_CSR register *******************/ 04813 #define RCC_CSR_LSION_MORT ((uint32_t)0x00000001) 04814 #define RCC_CSR_LSIRDY_MORT ((uint32_t)0x00000002) 04815 #define RCC_CSR_RMVF_MORT ((uint32_t)0x01000000) 04816 #define RCC_CSR_BORRSTF_MORT ((uint32_t)0x02000000) 04817 #define RCC_CSR_PADRSTF_MORT ((uint32_t)0x04000000) 04818 #define RCC_CSR_PORRSTF_MORT ((uint32_t)0x08000000) 04819 #define RCC_CSR_SFTRSTF_MORT ((uint32_t)0x10000000) 04820 #define RCC_CSR_WDGRSTF_MORT ((uint32_t)0x20000000) 04821 #define RCC_CSR_WWDGRSTF_MORT ((uint32_t)0x40000000) 04822 #define RCC_CSR_LPWRRSTF_MORT ((uint32_t)0x80000000) 04823 04824 /******************** Bit definition for RCC_SSCGR register *****************/ 04825 #define RCC_SSCGR_MODPER_MORT ((uint32_t)0x00001FFF) 04826 #define RCC_SSCGR_INCSTEP_MORT ((uint32_t)0x0FFFE000) 04827 #define RCC_SSCGR_SPREADSEL_MORT ((uint32_t)0x40000000) 04828 #define RCC_SSCGR_SSCGEN_MORT ((uint32_t)0x80000000) 04829 04830 /******************** Bit definition for RCC_PLLI2SCFGR register ************/ 04831 #define RCC_PLLI2SCFGR_PLLI2SM_MORT ((uint32_t)0x0000003F) 04832 #define RCC_PLLI2SCFGR_PLLI2SM_0_MORT ((uint32_t)0x00000001) 04833 #define RCC_PLLI2SCFGR_PLLI2SM_1_MORT ((uint32_t)0x00000002) 04834 #define RCC_PLLI2SCFGR_PLLI2SM_2_MORT ((uint32_t)0x00000004) 04835 #define RCC_PLLI2SCFGR_PLLI2SM_3_MORT ((uint32_t)0x00000008) 04836 #define RCC_PLLI2SCFGR_PLLI2SM_4_MORT ((uint32_t)0x00000010) 04837 #define RCC_PLLI2SCFGR_PLLI2SM_5_MORT ((uint32_t)0x00000020) 04838 04839 #define RCC_PLLI2SCFGR_PLLI2SN_MORT ((uint32_t)0x00007FC0) 04840 #define RCC_PLLI2SCFGR_PLLI2SN_0_MORT ((uint32_t)0x00000040) 04841 #define RCC_PLLI2SCFGR_PLLI2SN_1_MORT ((uint32_t)0x00000080) 04842 #define RCC_PLLI2SCFGR_PLLI2SN_2_MORT ((uint32_t)0x00000100) 04843 #define RCC_PLLI2SCFGR_PLLI2SN_3_MORT ((uint32_t)0x00000200) 04844 #define RCC_PLLI2SCFGR_PLLI2SN_4_MORT ((uint32_t)0x00000400) 04845 #define RCC_PLLI2SCFGR_PLLI2SN_5_MORT ((uint32_t)0x00000800) 04846 #define RCC_PLLI2SCFGR_PLLI2SN_6_MORT ((uint32_t)0x00001000) 04847 #define RCC_PLLI2SCFGR_PLLI2SN_7_MORT ((uint32_t)0x00002000) 04848 #define RCC_PLLI2SCFGR_PLLI2SN_8_MORT ((uint32_t)0x00004000) 04849 04850 #if defined(STM32F412xG) || defined(STM32F413_423xx) 04851 04852 #endif /* STM32F412xG || STM32F413_423xx */ 04853 04854 #if defined(STM32F446xx_MORT) 04855 #define RCC_PLLI2SCFGR_PLLI2SP_MORT ((uint32_t)0x00030000) 04856 #define RCC_PLLI2SCFGR_PLLI2SP_0_MORT ((uint32_t)0x00010000) 04857 #define RCC_PLLI2SCFGR_PLLI2SP_1_MORT ((uint32_t)0x00020000) 04858 #endif /* STM32F446xx_MORT */ 04859 04860 #define RCC_PLLI2SCFGR_PLLI2SQ_MORT ((uint32_t)0x0F000000) 04861 #define RCC_PLLI2SCFGR_PLLI2SQ_0_MORT ((uint32_t)0x01000000) 04862 #define RCC_PLLI2SCFGR_PLLI2SQ_1_MORT ((uint32_t)0x02000000) 04863 #define RCC_PLLI2SCFGR_PLLI2SQ_2_MORT ((uint32_t)0x04000000) 04864 #define RCC_PLLI2SCFGR_PLLI2SQ_3_MORT ((uint32_t)0x08000000) 04865 04866 #define RCC_PLLI2SCFGR_PLLI2SR_MORT ((uint32_t)0x70000000) 04867 #define RCC_PLLI2SCFGR_PLLI2SR_0_MORT ((uint32_t)0x10000000) 04868 #define RCC_PLLI2SCFGR_PLLI2SR_1_MORT ((uint32_t)0x20000000) 04869 #define RCC_PLLI2SCFGR_PLLI2SR_2_MORT ((uint32_t)0x40000000) 04870 04871 /******************** Bit definition for RCC_PLLSAICFGR register ************/ 04872 #if defined(STM32F446xx_MORT) 04873 #define RCC_PLLSAICFGR_PLLSAIM_MORT ((uint32_t)0x0000003F) 04874 #define RCC_PLLSAICFGR_PLLSAIM_0_MORT ((uint32_t)0x00000001) 04875 #define RCC_PLLSAICFGR_PLLSAIM_1_MORT ((uint32_t)0x00000002) 04876 #define RCC_PLLSAICFGR_PLLSAIM_2_MORT ((uint32_t)0x00000004) 04877 #define RCC_PLLSAICFGR_PLLSAIM_3_MORT ((uint32_t)0x00000008) 04878 #define RCC_PLLSAICFGR_PLLSAIM_4_MORT ((uint32_t)0x00000010) 04879 #define RCC_PLLSAICFGR_PLLSAIM_5_MORT ((uint32_t)0x00000020) 04880 #endif /* STM32F446xx_MORT */ 04881 04882 #define RCC_PLLSAICFGR_PLLSAIN_MORT ((uint32_t)0x00007FC0) 04883 #define RCC_PLLSAICFGR_PLLSAIN_0_MORT ((uint32_t)0x00000040) 04884 #define RCC_PLLSAICFGR_PLLSAIN_1_MORT ((uint32_t)0x00000080) 04885 #define RCC_PLLSAICFGR_PLLSAIN_2_MORT ((uint32_t)0x00000100) 04886 #define RCC_PLLSAICFGR_PLLSAIN_3_MORT ((uint32_t)0x00000200) 04887 #define RCC_PLLSAICFGR_PLLSAIN_4_MORT ((uint32_t)0x00000400) 04888 #define RCC_PLLSAICFGR_PLLSAIN_5_MORT ((uint32_t)0x00000800) 04889 #define RCC_PLLSAICFGR_PLLSAIN_6_MORT ((uint32_t)0x00001000) 04890 #define RCC_PLLSAICFGR_PLLSAIN_7_MORT ((uint32_t)0x00002000) 04891 #define RCC_PLLSAICFGR_PLLSAIN_8_MORT ((uint32_t)0x00004000) 04892 04893 #if defined(STM32F446xx_MORT) || defined(STM32F469_479xx) 04894 #define RCC_PLLSAICFGR_PLLSAIP_MORT ((uint32_t)0x00030000) 04895 #define RCC_PLLSAICFGR_PLLSAIP_0_MORT ((uint32_t)0x00010000) 04896 #define RCC_PLLSAICFGR_PLLSAIP_1_MORT ((uint32_t)0x00020000) 04897 #endif /* STM32F446xx_MORT || STM32F469_479xx */ 04898 04899 #define RCC_PLLSAICFGR_PLLSAIQ_MORT ((uint32_t)0x0F000000) 04900 #define RCC_PLLSAICFGR_PLLSAIQ_0_MORT ((uint32_t)0x01000000) 04901 #define RCC_PLLSAICFGR_PLLSAIQ_1_MORT ((uint32_t)0x02000000) 04902 #define RCC_PLLSAICFGR_PLLSAIQ_2_MORT ((uint32_t)0x04000000) 04903 #define RCC_PLLSAICFGR_PLLSAIQ_3_MORT ((uint32_t)0x08000000) 04904 04905 #define RCC_PLLSAICFGR_PLLSAIR_MORT ((uint32_t)0x70000000) 04906 #define RCC_PLLSAICFGR_PLLSAIR_0_MORT ((uint32_t)0x10000000) 04907 #define RCC_PLLSAICFGR_PLLSAIR_1_MORT ((uint32_t)0x20000000) 04908 #define RCC_PLLSAICFGR_PLLSAIR_2_MORT ((uint32_t)0x40000000) 04909 04910 /******************** Bit definition for RCC_DCKCFGR register ***************/ 04911 #define RCC_DCKCFGR_PLLI2SDIVQ_MORT ((uint32_t)0x0000001F) 04912 #define RCC_DCKCFGR_PLLSAIDIVQ_MORT ((uint32_t)0x00001F00) 04913 #define RCC_DCKCFGR_PLLSAIDIVR_MORT ((uint32_t)0x00030000) 04914 04915 #if defined(STM32F412xG) || defined(STM32F413_423xx) 04916 04917 #endif /* STM32F412xG || STM32F413_423xx */ 04918 04919 #if defined(STM32F413_423xx) 04920 04921 #endif /* STM32F413_423xx */ 04922 04923 #define RCC_DCKCFGR_SAI1ASRC_MORT ((uint32_t)0x00300000) 04924 #define RCC_DCKCFGR_SAI1ASRC_0_MORT ((uint32_t)0x00100000) 04925 #define RCC_DCKCFGR_SAI1ASRC_1_MORT ((uint32_t)0x00200000) 04926 #if defined(STM32F446xx_MORT) 04927 #define RCC_DCKCFGR_SAI1SRC_MORT ((uint32_t)0x00300000) 04928 #define RCC_DCKCFGR_SAI1SRC_0_MORT ((uint32_t)0x00100000) 04929 #define RCC_DCKCFGR_SAI1SRC_1_MORT ((uint32_t)0x00200000) 04930 #endif /* STM32F446xx_MORT */ 04931 04932 #define RCC_DCKCFGR_SAI1BSRC_MORT ((uint32_t)0x00C00000) 04933 #define RCC_DCKCFGR_SAI1BSRC_0_MORT ((uint32_t)0x00400000) 04934 #define RCC_DCKCFGR_SAI1BSRC_1_MORT ((uint32_t)0x00800000) 04935 #if defined(STM32F446xx_MORT) 04936 #define RCC_DCKCFGR_SAI2SRC_MORT ((uint32_t)0x00C00000) 04937 #define RCC_DCKCFGR_SAI2SRC_0_MORT ((uint32_t)0x00400000) 04938 #define RCC_DCKCFGR_SAI2SRC_1_MORT ((uint32_t)0x00800000) 04939 #endif /* STM32F446xx_MORT */ 04940 04941 #define RCC_DCKCFGR_TIMPRE_MORT ((uint32_t)0x01000000) 04942 #if defined(STM32F469_479xx) 04943 04944 #endif /* STM32F469_479xx */ 04945 04946 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) 04947 #define RCC_DCKCFGR_I2S1SRC_MORT ((uint32_t)0x06000000) 04948 #define RCC_DCKCFGR_I2S1SRC_0_MORT ((uint32_t)0x02000000) 04949 #define RCC_DCKCFGR_I2S1SRC_1_MORT ((uint32_t)0x04000000) 04950 #define RCC_DCKCFGR_I2S2SRC_MORT ((uint32_t)0x18000000) 04951 #define RCC_DCKCFGR_I2S2SRC_0_MORT ((uint32_t)0x08000000) 04952 #define RCC_DCKCFGR_I2S2SRC_1_MORT ((uint32_t)0x10000000) 04953 04954 /******************** Bit definition for RCC_CKGATENR register ***************/ 04955 #define RCC_CKGATENR_AHB2APB1_CKEN_MORT ((uint32_t)0x00000001) 04956 #define RCC_CKGATENR_AHB2APB2_CKEN_MORT ((uint32_t)0x00000002) 04957 #define RCC_CKGATENR_CM4DBG_CKEN_MORT ((uint32_t)0x00000004) 04958 #define RCC_CKGATENR_SPARE_CKEN_MORT ((uint32_t)0x00000008) 04959 #define RCC_CKGATENR_SRAM_CKEN_MORT ((uint32_t)0x00000010) 04960 #define RCC_CKGATENR_FLITF_CKEN_MORT ((uint32_t)0x00000020) 04961 #define RCC_CKGATENR_RCC_CKEN_MORT ((uint32_t)0x00000040) 04962 #if defined(STM32F412xG) || defined(STM32F413_423xx) 04963 04964 #endif /* STM32F412xG || STM32F413_423xx */ 04965 04966 /******************** Bit definition for RCC_DCKCFGR2 register ***************/ 04967 #define RCC_DCKCFGR2_FMPI2C1SEL_MORT ((uint32_t)0x00C00000) 04968 #define RCC_DCKCFGR2_FMPI2C1SEL_0_MORT ((uint32_t)0x00400000) 04969 #define RCC_DCKCFGR2_FMPI2C1SEL_1_MORT ((uint32_t)0x00800000) 04970 #define RCC_DCKCFGR2_CECSEL_MORT ((uint32_t)0x04000000) 04971 #define RCC_DCKCFGR2_CK48MSEL_MORT ((uint32_t)0x08000000) 04972 #define RCC_DCKCFGR2_SDIOSEL_MORT ((uint32_t)0x10000000) 04973 #if defined(STM32F446xx_MORT) 04974 #define RCC_DCKCFGR2_SPDIFRXSEL_MORT ((uint32_t)0x20000000) 04975 #endif /* STM32F446xx_MORT */ 04976 #if defined(STM32F413_423xx) 04977 04978 #endif /* STM32F413_423xx */ 04979 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx_MORT */ 04980 04981 #if defined(STM32F410xx) 04982 04983 #endif /* STM32F410xx */ 04984 04985 #if defined(STM32F410xx) 04986 /******************** Bit definition for RCC_DCKCFGR2 register **************/ 04987 04988 #endif /* STM32F410xx */ 04989 /******************************************************************************/ 04990 /* */ 04991 /* RNG_MORT */ 04992 /* */ 04993 /******************************************************************************/ 04994 /******************** Bits definition for RNG_CR register *******************/ 04995 #define RNG_CR_RNGEN_MORT ((uint32_t)0x00000004) 04996 #define RNG_CR_IE_MORT ((uint32_t)0x00000008) 04997 04998 /******************** Bits definition for RNG_SR register *******************/ 04999 #define RNG_SR_DRDY_MORT ((uint32_t)0x00000001) 05000 #define RNG_SR_CECS_MORT ((uint32_t)0x00000002) 05001 #define RNG_SR_SECS_MORT ((uint32_t)0x00000004) 05002 #define RNG_SR_CEIS_MORT ((uint32_t)0x00000020) 05003 #define RNG_SR_SEIS_MORT ((uint32_t)0x00000040) 05004 05005 /******************************************************************************/ 05006 /* */ 05007 /* Real-Time Clock (RTC_MORT) */ 05008 /* */ 05009 /******************************************************************************/ 05010 /******************** Bits definition for RTC_TR register *******************/ 05011 05012 05013 /******************** Bits definition for RTC_DR register *******************/ 05014 05015 05016 /******************** Bits definition for RTC_CR register *******************/ 05017 05018 05019 /******************** Bits definition for RTC_ISR register ******************/ 05020 05021 05022 /******************** Bits definition for RTC_PRER register *****************/ 05023 05024 05025 /******************** Bits definition for RTC_WUTR register *****************/ 05026 05027 /******************** Bits definition for RTC_CALIBR register ***************/ 05028 05029 05030 /******************** Bits definition for RTC_ALRMAR register ***************/ 05031 05032 /******************** Bits definition for RTC_ALRMBR register ***************/ 05033 05034 /******************** Bits definition for RTC_WPR register ******************/ 05035 05036 05037 /******************** Bits definition for RTC_SSR register ******************/ 05038 05039 05040 /******************** Bits definition for RTC_SHIFTR register ***************/ 05041 05042 05043 /******************** Bits definition for RTC_TSTR register *****************/ 05044 05045 05046 /******************** Bits definition for RTC_TSDR register *****************/ 05047 05048 /******************** Bits definition for RTC_TSSSR register ****************/ 05049 05050 05051 /******************** Bits definition for RTC_CAL register *****************/ 05052 05053 /******************** Bits definition for RTC_TAFCR register ****************/ 05054 05055 /******************** Bits definition for RTC_ALRMASSR register *************/ 05056 05057 /******************** Bits definition for RTC_ALRMBSSR register *************/ 05058 05059 /******************** Bits definition for RTC_BKP0R register ****************/ 05060 05061 /******************** Bits definition for RTC_BKP1R register ****************/ 05062 05063 /******************** Bits definition for RTC_BKP2R register ****************/ 05064 05065 /******************** Bits definition for RTC_BKP3R register ****************/ 05066 05067 /******************** Bits definition for RTC_BKP4R register ****************/ 05068 05069 /******************** Bits definition for RTC_BKP5R register ****************/ 05070 05071 /******************** Bits definition for RTC_BKP6R register ****************/ 05072 05073 /******************** Bits definition for RTC_BKP7R register ****************/ 05074 05075 /******************** Bits definition for RTC_BKP8R register ****************/ 05076 05077 05078 /******************** Bits definition for RTC_BKP9R register ****************/ 05079 05080 05081 /******************** Bits definition for RTC_BKP10R register ***************/ 05082 05083 /******************** Bits definition for RTC_BKP11R register ***************/ 05084 05085 /******************** Bits definition for RTC_BKP12R register ***************/ 05086 05087 /******************** Bits definition for RTC_BKP13R register ***************/ 05088 05089 /******************** Bits definition for RTC_BKP14R register ***************/ 05090 05091 /******************** Bits definition for RTC_BKP15R register ***************/ 05092 05093 /******************** Bits definition for RTC_BKP16R register ***************/ 05094 05095 05096 /******************** Bits definition for RTC_BKP17R register ***************/ 05097 05098 /******************** Bits definition for RTC_BKP18R register ***************/ 05099 05100 /******************** Bits definition for RTC_BKP19R register ***************/ 05101 05102 /******************************************************************************/ 05103 /* */ 05104 /* Serial Audio Interface */ 05105 /* */ 05106 /******************************************************************************/ 05107 /******************** Bit definition for SAI_GCR register *******************/ 05108 05109 /******************* Bit definition for SAI_xCR1 register *******************/ 05110 05111 /******************* Bit definition for SAI_xCR2 register *******************/ 05112 05113 /****************** Bit definition for SAI_xFRCR register *******************/ 05114 05115 05116 /****************** Bit definition for SAI_xSLOTR register *******************/ 05117 05118 /******************* Bit definition for SAI_xIMR register *******************/ 05119 05120 /******************** Bit definition for SAI_xSR register *******************/ 05121 05122 /****************** Bit definition for SAI_xCLRFR register ******************/ 05123 05124 /****************** Bit definition for SAI_xDR register ******************/ 05125 05126 05127 #if defined(STM32F446xx_MORT) 05128 /******************************************************************************/ 05129 /* */ 05130 /* SPDIF-RX Interface */ 05131 /* */ 05132 /******************************************************************************/ 05133 /******************** Bit definition for SPDIFRX_CR register *******************/ 05134 05135 /******************* Bit definition for SPDIFRX_IMR register *******************/ 05136 05137 /******************* Bit definition for SPDIFRX_SR register *******************/ 05138 05139 /******************* Bit definition for SPDIFRX_IFCR register *******************/ 05140 05141 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/ 05142 05143 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/ 05144 05145 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/ 05146 05147 /******************* Bit definition for SPDIFRX_CSR register *******************/ 05148 05149 /******************* Bit definition for SPDIFRX_DIR register *******************/ 05150 05151 #endif /* STM32F446xx_MORT */ 05152 05153 /******************************************************************************/ 05154 /* */ 05155 /* SD host Interface */ 05156 /* */ 05157 /******************************************************************************/ 05158 /****************** Bit definition for SDIO_POWER register ******************/ 05159 05160 /****************** Bit definition for SDIO_CLKCR register ******************/ 05161 05162 /******************* Bit definition for SDIO_ARG register *******************/ 05163 05164 /******************* Bit definition for SDIO_CMD register *******************/ 05165 05166 /***************** Bit definition for SDIO_RESPCMD register *****************/ 05167 05168 /****************** Bit definition for SDIO_RESP0 register ******************/ 05169 05170 /****************** Bit definition for SDIO_RESP1 register ******************/ 05171 05172 /****************** Bit definition for SDIO_RESP2 register ******************/ 05173 05174 /****************** Bit definition for SDIO_RESP3 register ******************/ 05175 05176 /****************** Bit definition for SDIO_RESP4 register ******************/ 05177 05178 /****************** Bit definition for SDIO_DTIMER register *****************/ 05179 05180 /****************** Bit definition for SDIO_DLEN register *******************/ 05181 05182 /****************** Bit definition for SDIO_DCTRL register ******************/ 05183 05184 /****************** Bit definition for SDIO_DCOUNT register *****************/ 05185 05186 /****************** Bit definition for SDIO_STA register ********************/ 05187 05188 /******************* Bit definition for SDIO_ICR register *******************/ 05189 05190 05191 /****************** Bit definition for SDIO_MASK register *******************/ 05192 05193 /***************** Bit definition for SDIO_FIFOCNT register *****************/ 05194 05195 /****************** Bit definition for SDIO_FIFO register *******************/ 05196 05197 /******************************************************************************/ 05198 /* */ 05199 /* Serial Peripheral Interface */ 05200 /* */ 05201 /******************************************************************************/ 05202 /******************* Bit definition for SPI_CR1 register ********************/ 05203 #define SPI_CR1_CPHA_MORT ((uint16_t)0x0001) /*!<Clock Phase */ 05204 #define SPI_CR1_CPOL_MORT ((uint16_t)0x0002) /*!<Clock Polarity */ 05205 #define SPI_CR1_MSTR_MORT ((uint16_t)0x0004) /*!<Master Selection */ 05206 05207 #define SPI_CR1_BR_MORT ((uint16_t)0x0038) /*!<BR[2:0] bits (Baud Rate Control) */ 05208 #define SPI_CR1_BR_0_MORT ((uint16_t)0x0008) /*!<Bit 0 */ 05209 #define SPI_CR1_BR_1_MORT ((uint16_t)0x0010) /*!<Bit 1 */ 05210 #define SPI_CR1_BR_2_MORT ((uint16_t)0x0020) /*!<Bit 2 */ 05211 05212 #define SPI_CR1_SPE_MORT ((uint16_t)0x0040) /*!<SPI Enable */ 05213 #define SPI_CR1_LSBFIRST_MORT ((uint16_t)0x0080) /*!<Frame Format */ 05214 #define SPI_CR1_SSI_MORT ((uint16_t)0x0100) /*!<Internal slave select */ 05215 #define SPI_CR1_SSM_MORT ((uint16_t)0x0200) /*!<Software slave management */ 05216 #define SPI_CR1_RXONLY_MORT ((uint16_t)0x0400) /*!<Receive only */ 05217 #define SPI_CR1_DFF_MORT ((uint16_t)0x0800) /*!<Data Frame Format */ 05218 #define SPI_CR1_CRCNEXT_MORT ((uint16_t)0x1000) /*!<Transmit CRC_MORT next */ 05219 #define SPI_CR1_CRCEN_MORT ((uint16_t)0x2000) /*!<Hardware CRC_MORT calculation enable */ 05220 #define SPI_CR1_BIDIOE_MORT ((uint16_t)0x4000) /*!<Output enable in bidirectional mode */ 05221 #define SPI_CR1_BIDIMODE_MORT ((uint16_t)0x8000) /*!<Bidirectional data mode enable */ 05222 05223 /******************* Bit definition for SPI_CR2 register ********************/ 05224 #define SPI_CR2_RXDMAEN_MORT ((uint8_t)0x01) /*!<Rx Buffer DMA Enable */ 05225 #define SPI_CR2_TXDMAEN_MORT ((uint8_t)0x02) /*!<Tx Buffer DMA Enable */ 05226 #define SPI_CR2_SSOE_MORT ((uint8_t)0x04) /*!<SS Output Enable */ 05227 #define SPI_CR2_ERRIE_MORT ((uint8_t)0x20) /*!<Error Interrupt Enable */ 05228 #define SPI_CR2_RXNEIE_MORT ((uint8_t)0x40) /*!<RX buffer Not Empty Interrupt Enable */ 05229 #define SPI_CR2_TXEIE_MORT ((uint8_t)0x80) /*!<Tx buffer Empty Interrupt Enable */ 05230 05231 /******************** Bit definition for SPI_SR register ********************/ 05232 #define SPI_SR_RXNE_MORT ((uint8_t)0x01) /*!<Receive buffer Not Empty */ 05233 #define SPI_SR_TXE_MORT ((uint8_t)0x02) /*!<Transmit buffer Empty */ 05234 #define SPI_SR_CHSIDE_MORT ((uint8_t)0x04) /*!<Channel side */ 05235 #define SPI_SR_UDR_MORT ((uint8_t)0x08) /*!<Underrun flag */ 05236 #define SPI_SR_CRCERR_MORT ((uint8_t)0x10) /*!<CRC_MORT Error flag */ 05237 #define SPI_SR_MODF_MORT ((uint8_t)0x20) /*!<Mode fault */ 05238 #define SPI_SR_OVR_MORT ((uint8_t)0x40) /*!<Overrun flag */ 05239 #define SPI_SR_BSY_MORT ((uint8_t)0x80) /*!<Busy flag */ 05240 05241 /******************** Bit definition for SPI_DR register ********************/ 05242 #define SPI_DR_DR_MORT ((uint16_t)0xFFFF) /*!<Data Register */ 05243 05244 /******************* Bit definition for SPI_CRCPR register ******************/ 05245 #define SPI_CRCPR_CRCPOLY_MORT ((uint16_t)0xFFFF) /*!<CRC_MORT polynomial register */ 05246 05247 /****************** Bit definition for SPI_RXCRCR register ******************/ 05248 #define SPI_RXCRCR_RXCRC_MORT ((uint16_t)0xFFFF) /*!<Rx CRC_MORT Register */ 05249 05250 /****************** Bit definition for SPI_TXCRCR register ******************/ 05251 #define SPI_TXCRCR_TXCRC_MORT ((uint16_t)0xFFFF) /*!<Tx CRC_MORT Register */ 05252 05253 /****************** Bit definition for SPI_I2SCFGR register *****************/ 05254 #define SPI_I2SCFGR_CHLEN_MORT ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */ 05255 05256 #define SPI_I2SCFGR_DATLEN_MORT ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */ 05257 #define SPI_I2SCFGR_DATLEN_0_MORT ((uint16_t)0x0002) /*!<Bit 0 */ 05258 #define SPI_I2SCFGR_DATLEN_1_MORT ((uint16_t)0x0004) /*!<Bit 1 */ 05259 05260 #define SPI_I2SCFGR_CKPOL_MORT ((uint16_t)0x0008) /*!<steady state clock polarity */ 05261 05262 #define SPI_I2SCFGR_I2SSTD_MORT ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */ 05263 #define SPI_I2SCFGR_I2SSTD_0_MORT ((uint16_t)0x0010) /*!<Bit 0 */ 05264 #define SPI_I2SCFGR_I2SSTD_1_MORT ((uint16_t)0x0020) /*!<Bit 1 */ 05265 05266 #define SPI_I2SCFGR_PCMSYNC_MORT ((uint16_t)0x0080) /*!<PCM frame synchronization */ 05267 05268 #define SPI_I2SCFGR_I2SCFG_MORT ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */ 05269 #define SPI_I2SCFGR_I2SCFG_0_MORT ((uint16_t)0x0100) /*!<Bit 0 */ 05270 #define SPI_I2SCFGR_I2SCFG_1_MORT ((uint16_t)0x0200) /*!<Bit 1 */ 05271 05272 #define SPI_I2SCFGR_I2SE_MORT ((uint16_t)0x0400) /*!<I2S Enable */ 05273 #define SPI_I2SCFGR_I2SMOD_MORT ((uint16_t)0x0800) /*!<I2S mode selection */ 05274 #if defined(STM32F413_423xx) || defined(STM32F446xx_MORT) 05275 #define SPI_I2SCFGR_ASTRTEN_MORT ((uint16_t)0x1000) /*!<Asynchronous start enable */ 05276 #endif /* STM32F413_423xx */ 05277 05278 /****************** Bit definition for SPI_I2SPR register *******************/ 05279 #define SPI_I2SPR_I2SDIV_MORT ((uint16_t)0x00FF) /*!<I2S Linear prescaler */ 05280 #define SPI_I2SPR_ODD_MORT ((uint16_t)0x0100) /*!<Odd factor for the prescaler */ 05281 #define SPI_I2SPR_MCKOE_MORT ((uint16_t)0x0200) /*!<Master Clock Output Enable */ 05282 05283 /******************************************************************************/ 05284 /* */ 05285 /* SYSCFG_MORT */ 05286 /* */ 05287 /******************************************************************************/ 05288 /****************** Bit definition for SYSCFG_MEMRMP register ***************/ 05289 05290 /****************** Bit definition for SYSCFG_PMC register ******************/ 05291 05292 05293 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/ 05294 05295 /** 05296 * @brief EXTI0 configuration 05297 */ 05298 05299 05300 /** 05301 * @brief EXTI1 configuration 05302 */ 05303 05304 05305 /** 05306 * @brief EXTI2 configuration 05307 */ 05308 05309 05310 05311 /** 05312 * @brief EXTI3 configuration 05313 */ 05314 05315 05316 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ 05317 05318 /** 05319 * @brief EXTI4 configuration 05320 */ 05321 05322 05323 /** 05324 * @brief EXTI5 configuration 05325 */ 05326 05327 05328 /** 05329 * @brief EXTI6 configuration 05330 */ 05331 05332 05333 /** 05334 * @brief EXTI7 configuration 05335 */ 05336 05337 05338 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ 05339 05340 /** 05341 * @brief EXTI8 configuration 05342 */ 05343 05344 05345 /** 05346 * @brief EXTI9 configuration 05347 */ 05348 05349 05350 /** 05351 * @brief EXTI10 configuration 05352 */ 05353 05354 05355 /** 05356 * @brief EXTI11 configuration 05357 */ 05358 05359 05360 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ 05361 05362 /** 05363 * @brief EXTI12 configuration 05364 */ 05365 05366 05367 /** 05368 * @brief EXTI13 configuration 05369 */ 05370 05371 05372 /** 05373 * @brief EXTI14 configuration 05374 */ 05375 05376 /** 05377 * @brief EXTI15 configuration 05378 */ 05379 05380 05381 #if defined(STM32F412xG) || defined(STM32F413_423xx) 05382 /****************** Bit definition for SYSCFG_CFGR register *****************/ 05383 05384 #endif /* STM32F412xG || STM32413_423xx */ 05385 05386 #if defined (STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) 05387 /****************** Bit definition for SYSCFG_CFGR2 register ****************/ 05388 05389 #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx */ 05390 /****************** Bit definition for SYSCFG_CMPCR register ****************/ 05391 05392 #if defined(STM32F413_423xx) 05393 /****************** Bit definition for SYSCFG_MCHDLYCR register *****************/ 05394 05395 #endif /* STM32F413_423xx */ 05396 05397 /******************************************************************************/ 05398 /* */ 05399 /* TIM */ 05400 /* */ 05401 /******************************************************************************/ 05402 /******************* Bit definition for TIM_CR1 register ********************/ 05403 #define TIM_CR1_CEN_MORT ((uint16_t)0x0001) /*!<Counter enable */ 05404 #define TIM_CR1_UDIS_MORT ((uint16_t)0x0002) /*!<Update disable */ 05405 #define TIM_CR1_URS_MORT ((uint16_t)0x0004) /*!<Update request source */ 05406 #define TIM_CR1_OPM_MORT ((uint16_t)0x0008) /*!<One pulse mode */ 05407 #define TIM_CR1_DIR_MORT ((uint16_t)0x0010) /*!<Direction */ 05408 05409 #define TIM_CR1_CMS_MORT ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */ 05410 #define TIM_CR1_CMS_0_MORT ((uint16_t)0x0020) /*!<Bit 0 */ 05411 #define TIM_CR1_CMS_1_MORT ((uint16_t)0x0040) /*!<Bit 1 */ 05412 05413 #define TIM_CR1_ARPE_MORT ((uint16_t)0x0080) /*!<Auto-reload preload enable */ 05414 05415 #define TIM_CR1_CKD_MORT ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */ 05416 #define TIM_CR1_CKD_0_MORT ((uint16_t)0x0100) /*!<Bit 0 */ 05417 #define TIM_CR1_CKD_1_MORT ((uint16_t)0x0200) /*!<Bit 1 */ 05418 05419 /******************* Bit definition for TIM_CR2 register ********************/ 05420 #define TIM_CR2_CCPC_MORT ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */ 05421 #define TIM_CR2_CCUS_MORT ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */ 05422 #define TIM_CR2_CCDS_MORT ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */ 05423 05424 #define TIM_CR2_MMS_MORT ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */ 05425 #define TIM_CR2_MMS_0_MORT ((uint16_t)0x0010) /*!<Bit 0 */ 05426 #define TIM_CR2_MMS_1_MORT ((uint16_t)0x0020) /*!<Bit 1 */ 05427 #define TIM_CR2_MMS_2_MORT ((uint16_t)0x0040) /*!<Bit 2 */ 05428 05429 #define TIM_CR2_TI1S_MORT ((uint16_t)0x0080) /*!<TI1 Selection */ 05430 #define TIM_CR2_OIS1_MORT ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */ 05431 #define TIM_CR2_OIS1N_MORT ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */ 05432 #define TIM_CR2_OIS2_MORT ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */ 05433 #define TIM_CR2_OIS2N_MORT ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */ 05434 #define TIM_CR2_OIS3_MORT ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */ 05435 #define TIM_CR2_OIS3N_MORT ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */ 05436 #define TIM_CR2_OIS4_MORT ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */ 05437 05438 /******************* Bit definition for TIM_SMCR register *******************/ 05439 #define TIM_SMCR_SMS_MORT ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */ 05440 #define TIM_SMCR_SMS_0_MORT ((uint16_t)0x0001) /*!<Bit 0 */ 05441 #define TIM_SMCR_SMS_1_MORT ((uint16_t)0x0002) /*!<Bit 1 */ 05442 #define TIM_SMCR_SMS_2_MORT ((uint16_t)0x0004) /*!<Bit 2 */ 05443 05444 #define TIM_SMCR_TS_MORT ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */ 05445 #define TIM_SMCR_TS_0_MORT ((uint16_t)0x0010) /*!<Bit 0 */ 05446 #define TIM_SMCR_TS_1_MORT ((uint16_t)0x0020) /*!<Bit 1 */ 05447 #define TIM_SMCR_TS_2_MORT ((uint16_t)0x0040) /*!<Bit 2 */ 05448 05449 #define TIM_SMCR_MSM_MORT ((uint16_t)0x0080) /*!<Master/slave mode */ 05450 05451 #define TIM_SMCR_ETF_MORT ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */ 05452 #define TIM_SMCR_ETF_0_MORT ((uint16_t)0x0100) /*!<Bit 0 */ 05453 #define TIM_SMCR_ETF_1_MORT ((uint16_t)0x0200) /*!<Bit 1 */ 05454 #define TIM_SMCR_ETF_2_MORT ((uint16_t)0x0400) /*!<Bit 2 */ 05455 #define TIM_SMCR_ETF_3_MORT ((uint16_t)0x0800) /*!<Bit 3 */ 05456 05457 #define TIM_SMCR_ETPS_MORT ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */ 05458 #define TIM_SMCR_ETPS_0_MORT ((uint16_t)0x1000) /*!<Bit 0 */ 05459 #define TIM_SMCR_ETPS_1_MORT ((uint16_t)0x2000) /*!<Bit 1 */ 05460 05461 #define TIM_SMCR_ECE_MORT ((uint16_t)0x4000) /*!<External clock enable */ 05462 #define TIM_SMCR_ETP_MORT ((uint16_t)0x8000) /*!<External trigger polarity */ 05463 05464 /******************* Bit definition for TIM_DIER register *******************/ 05465 #define TIM_DIER_UIE_MORT ((uint16_t)0x0001) /*!<Update interrupt enable */ 05466 #define TIM_DIER_CC1IE_MORT ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */ 05467 #define TIM_DIER_CC2IE_MORT ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */ 05468 #define TIM_DIER_CC3IE_MORT ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */ 05469 #define TIM_DIER_CC4IE_MORT ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */ 05470 #define TIM_DIER_COMIE_MORT ((uint16_t)0x0020) /*!<COM interrupt enable */ 05471 #define TIM_DIER_TIE_MORT ((uint16_t)0x0040) /*!<Trigger interrupt enable */ 05472 #define TIM_DIER_BIE_MORT ((uint16_t)0x0080) /*!<Break interrupt enable */ 05473 #define TIM_DIER_UDE_MORT ((uint16_t)0x0100) /*!<Update DMA request enable */ 05474 #define TIM_DIER_CC1DE_MORT ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */ 05475 #define TIM_DIER_CC2DE_MORT ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */ 05476 #define TIM_DIER_CC3DE_MORT ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */ 05477 #define TIM_DIER_CC4DE_MORT ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */ 05478 #define TIM_DIER_COMDE_MORT ((uint16_t)0x2000) /*!<COM DMA request enable */ 05479 #define TIM_DIER_TDE_MORT ((uint16_t)0x4000) /*!<Trigger DMA request enable */ 05480 05481 /******************** Bit definition for TIM_SR register ********************/ 05482 #define TIM_SR_UIF_MORT ((uint16_t)0x0001) /*!<Update interrupt Flag */ 05483 #define TIM_SR_CC1IF_MORT ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */ 05484 #define TIM_SR_CC2IF_MORT ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */ 05485 #define TIM_SR_CC3IF_MORT ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */ 05486 #define TIM_SR_CC4IF_MORT ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */ 05487 #define TIM_SR_COMIF_MORT ((uint16_t)0x0020) /*!<COM interrupt Flag */ 05488 #define TIM_SR_TIF_MORT ((uint16_t)0x0040) /*!<Trigger interrupt Flag */ 05489 #define TIM_SR_BIF_MORT ((uint16_t)0x0080) /*!<Break interrupt Flag */ 05490 #define TIM_SR_CC1OF_MORT ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */ 05491 #define TIM_SR_CC2OF_MORT ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */ 05492 #define TIM_SR_CC3OF_MORT ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */ 05493 #define TIM_SR_CC4OF_MORT ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */ 05494 05495 /******************* Bit definition for TIM_EGR register ********************/ 05496 #define TIM_EGR_UG_MORT ((uint8_t)0x01) /*!<Update Generation */ 05497 #define TIM_EGR_CC1G_MORT ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */ 05498 #define TIM_EGR_CC2G_MORT ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */ 05499 #define TIM_EGR_CC3G_MORT ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */ 05500 #define TIM_EGR_CC4G_MORT ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */ 05501 #define TIM_EGR_COMG_MORT ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */ 05502 #define TIM_EGR_TG_MORT ((uint8_t)0x40) /*!<Trigger Generation */ 05503 #define TIM_EGR_BG_MORT ((uint8_t)0x80) /*!<Break Generation */ 05504 05505 /****************** Bit definition for TIM_CCMR1 register *******************/ 05506 #define TIM_CCMR1_CC1S_MORT ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ 05507 #define TIM_CCMR1_CC1S_0_MORT ((uint16_t)0x0001) /*!<Bit 0 */ 05508 #define TIM_CCMR1_CC1S_1_MORT ((uint16_t)0x0002) /*!<Bit 1 */ 05509 05510 #define TIM_CCMR1_OC1FE_MORT ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */ 05511 #define TIM_CCMR1_OC1PE_MORT ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */ 05512 05513 #define TIM_CCMR1_OC1M_MORT ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ 05514 #define TIM_CCMR1_OC1M_0_MORT ((uint16_t)0x0010) /*!<Bit 0 */ 05515 #define TIM_CCMR1_OC1M_1_MORT ((uint16_t)0x0020) /*!<Bit 1 */ 05516 #define TIM_CCMR1_OC1M_2_MORT ((uint16_t)0x0040) /*!<Bit 2 */ 05517 05518 #define TIM_CCMR1_OC1CE_MORT ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */ 05519 05520 #define TIM_CCMR1_CC2S_MORT ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ 05521 #define TIM_CCMR1_CC2S_0_MORT ((uint16_t)0x0100) /*!<Bit 0 */ 05522 #define TIM_CCMR1_CC2S_1_MORT ((uint16_t)0x0200) /*!<Bit 1 */ 05523 05524 #define TIM_CCMR1_OC2FE_MORT ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */ 05525 #define TIM_CCMR1_OC2PE_MORT ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */ 05526 05527 #define TIM_CCMR1_OC2M_MORT ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ 05528 #define TIM_CCMR1_OC2M_0_MORT ((uint16_t)0x1000) /*!<Bit 0 */ 05529 #define TIM_CCMR1_OC2M_1_MORT ((uint16_t)0x2000) /*!<Bit 1 */ 05530 #define TIM_CCMR1_OC2M_2_MORT ((uint16_t)0x4000) /*!<Bit 2 */ 05531 05532 #define TIM_CCMR1_OC2CE_MORT ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */ 05533 05534 /*----------------------------------------------------------------------------*/ 05535 05536 #define TIM_CCMR1_IC1PSC_MORT ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ 05537 #define TIM_CCMR1_IC1PSC_0_MORT ((uint16_t)0x0004) /*!<Bit 0 */ 05538 #define TIM_CCMR1_IC1PSC_1_MORT ((uint16_t)0x0008) /*!<Bit 1 */ 05539 05540 #define TIM_CCMR1_IC1F_MORT ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ 05541 #define TIM_CCMR1_IC1F_0_MORT ((uint16_t)0x0010) /*!<Bit 0 */ 05542 #define TIM_CCMR1_IC1F_1_MORT ((uint16_t)0x0020) /*!<Bit 1 */ 05543 #define TIM_CCMR1_IC1F_2_MORT ((uint16_t)0x0040) /*!<Bit 2 */ 05544 #define TIM_CCMR1_IC1F_3_MORT ((uint16_t)0x0080) /*!<Bit 3 */ 05545 05546 #define TIM_CCMR1_IC2PSC_MORT ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ 05547 #define TIM_CCMR1_IC2PSC_0_MORT ((uint16_t)0x0400) /*!<Bit 0 */ 05548 #define TIM_CCMR1_IC2PSC_1_MORT ((uint16_t)0x0800) /*!<Bit 1 */ 05549 05550 #define TIM_CCMR1_IC2F_MORT ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ 05551 #define TIM_CCMR1_IC2F_0_MORT ((uint16_t)0x1000) /*!<Bit 0 */ 05552 #define TIM_CCMR1_IC2F_1_MORT ((uint16_t)0x2000) /*!<Bit 1 */ 05553 #define TIM_CCMR1_IC2F_2_MORT ((uint16_t)0x4000) /*!<Bit 2 */ 05554 #define TIM_CCMR1_IC2F_3_MORT ((uint16_t)0x8000) /*!<Bit 3 */ 05555 05556 /****************** Bit definition for TIM_CCMR2 register *******************/ 05557 #define TIM_CCMR2_CC3S_MORT ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ 05558 #define TIM_CCMR2_CC3S_0_MORT ((uint16_t)0x0001) /*!<Bit 0 */ 05559 #define TIM_CCMR2_CC3S_1_MORT ((uint16_t)0x0002) /*!<Bit 1 */ 05560 05561 #define TIM_CCMR2_OC3FE_MORT ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */ 05562 #define TIM_CCMR2_OC3PE_MORT ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */ 05563 05564 #define TIM_CCMR2_OC3M_MORT ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ 05565 #define TIM_CCMR2_OC3M_0_MORT ((uint16_t)0x0010) /*!<Bit 0 */ 05566 #define TIM_CCMR2_OC3M_1_MORT ((uint16_t)0x0020) /*!<Bit 1 */ 05567 #define TIM_CCMR2_OC3M_2_MORT ((uint16_t)0x0040) /*!<Bit 2 */ 05568 05569 #define TIM_CCMR2_OC3CE_MORT ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */ 05570 05571 #define TIM_CCMR2_CC4S_MORT ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ 05572 #define TIM_CCMR2_CC4S_0_MORT ((uint16_t)0x0100) /*!<Bit 0 */ 05573 #define TIM_CCMR2_CC4S_1_MORT ((uint16_t)0x0200) /*!<Bit 1 */ 05574 05575 #define TIM_CCMR2_OC4FE_MORT ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */ 05576 #define TIM_CCMR2_OC4PE_MORT ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */ 05577 05578 #define TIM_CCMR2_OC4M_MORT ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ 05579 #define TIM_CCMR2_OC4M_0_MORT ((uint16_t)0x1000) /*!<Bit 0 */ 05580 #define TIM_CCMR2_OC4M_1_MORT ((uint16_t)0x2000) /*!<Bit 1 */ 05581 #define TIM_CCMR2_OC4M_2_MORT ((uint16_t)0x4000) /*!<Bit 2 */ 05582 05583 #define TIM_CCMR2_OC4CE_MORT ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */ 05584 05585 /*----------------------------------------------------------------------------*/ 05586 05587 #define TIM_CCMR2_IC3PSC_MORT ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ 05588 #define TIM_CCMR2_IC3PSC_0_MORT ((uint16_t)0x0004) /*!<Bit 0 */ 05589 #define TIM_CCMR2_IC3PSC_1_MORT ((uint16_t)0x0008) /*!<Bit 1 */ 05590 05591 #define TIM_CCMR2_IC3F_MORT ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ 05592 #define TIM_CCMR2_IC3F_0_MORT ((uint16_t)0x0010) /*!<Bit 0 */ 05593 #define TIM_CCMR2_IC3F_1_MORT ((uint16_t)0x0020) /*!<Bit 1 */ 05594 #define TIM_CCMR2_IC3F_2_MORT ((uint16_t)0x0040) /*!<Bit 2 */ 05595 #define TIM_CCMR2_IC3F_3_MORT ((uint16_t)0x0080) /*!<Bit 3 */ 05596 05597 #define TIM_CCMR2_IC4PSC_MORT ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ 05598 #define TIM_CCMR2_IC4PSC_0_MORT ((uint16_t)0x0400) /*!<Bit 0 */ 05599 #define TIM_CCMR2_IC4PSC_1_MORT ((uint16_t)0x0800) /*!<Bit 1 */ 05600 05601 #define TIM_CCMR2_IC4F_MORT ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ 05602 #define TIM_CCMR2_IC4F_0_MORT ((uint16_t)0x1000) /*!<Bit 0 */ 05603 #define TIM_CCMR2_IC4F_1_MORT ((uint16_t)0x2000) /*!<Bit 1 */ 05604 #define TIM_CCMR2_IC4F_2_MORT ((uint16_t)0x4000) /*!<Bit 2 */ 05605 #define TIM_CCMR2_IC4F_3_MORT ((uint16_t)0x8000) /*!<Bit 3 */ 05606 05607 /******************* Bit definition for TIM_CCER register *******************/ 05608 #define TIM_CCER_CC1E_MORT ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */ 05609 #define TIM_CCER_CC1P_MORT ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */ 05610 #define TIM_CCER_CC1NE_MORT ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */ 05611 #define TIM_CCER_CC1NP_MORT ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */ 05612 #define TIM_CCER_CC2E_MORT ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */ 05613 #define TIM_CCER_CC2P_MORT ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */ 05614 #define TIM_CCER_CC2NE_MORT ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */ 05615 #define TIM_CCER_CC2NP_MORT ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */ 05616 #define TIM_CCER_CC3E_MORT ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */ 05617 #define TIM_CCER_CC3P_MORT ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */ 05618 #define TIM_CCER_CC3NE_MORT ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */ 05619 #define TIM_CCER_CC3NP_MORT ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */ 05620 #define TIM_CCER_CC4E_MORT ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */ 05621 #define TIM_CCER_CC4P_MORT ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */ 05622 #define TIM_CCER_CC4NP_MORT ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */ 05623 05624 /******************* Bit definition for TIM_CNT register ********************/ 05625 #define TIM_CNT_CNT_MORT ((uint16_t)0xFFFF) /*!<Counter Value */ 05626 05627 /******************* Bit definition for TIM_PSC register ********************/ 05628 #define TIM_PSC_PSC_MORT ((uint16_t)0xFFFF) /*!<Prescaler Value */ 05629 05630 /******************* Bit definition for TIM_ARR register ********************/ 05631 #define TIM_ARR_ARR_MORT ((uint16_t)0xFFFF) /*!<actual auto-reload Value */ 05632 05633 /******************* Bit definition for TIM_RCR register ********************/ 05634 #define TIM_RCR_REP_MORT ((uint8_t)0xFF) /*!<Repetition Counter Value */ 05635 05636 /******************* Bit definition for TIM_CCR1 register *******************/ 05637 #define TIM_CCR1_CCR1_MORT ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */ 05638 05639 /******************* Bit definition for TIM_CCR2 register *******************/ 05640 #define TIM_CCR2_CCR2_MORT ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */ 05641 05642 /******************* Bit definition for TIM_CCR3 register *******************/ 05643 #define TIM_CCR3_CCR3_MORT ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */ 05644 05645 /******************* Bit definition for TIM_CCR4 register *******************/ 05646 #define TIM_CCR4_CCR4_MORT ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */ 05647 05648 /******************* Bit definition for TIM_BDTR register *******************/ 05649 #define TIM_BDTR_DTG_MORT ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ 05650 #define TIM_BDTR_DTG_0_MORT ((uint16_t)0x0001) /*!<Bit 0 */ 05651 #define TIM_BDTR_DTG_1_MORT ((uint16_t)0x0002) /*!<Bit 1 */ 05652 #define TIM_BDTR_DTG_2_MORT ((uint16_t)0x0004) /*!<Bit 2 */ 05653 #define TIM_BDTR_DTG_3_MORT ((uint16_t)0x0008) /*!<Bit 3 */ 05654 #define TIM_BDTR_DTG_4_MORT ((uint16_t)0x0010) /*!<Bit 4 */ 05655 #define TIM_BDTR_DTG_5_MORT ((uint16_t)0x0020) /*!<Bit 5 */ 05656 #define TIM_BDTR_DTG_6_MORT ((uint16_t)0x0040) /*!<Bit 6 */ 05657 #define TIM_BDTR_DTG_7_MORT ((uint16_t)0x0080) /*!<Bit 7 */ 05658 05659 #define TIM_BDTR_LOCK_MORT ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */ 05660 #define TIM_BDTR_LOCK_0_MORT ((uint16_t)0x0100) /*!<Bit 0 */ 05661 #define TIM_BDTR_LOCK_1_MORT ((uint16_t)0x0200) /*!<Bit 1 */ 05662 05663 #define TIM_BDTR_OSSI_MORT ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */ 05664 #define TIM_BDTR_OSSR_MORT ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */ 05665 #define TIM_BDTR_BKE_MORT ((uint16_t)0x1000) /*!<Break enable */ 05666 #define TIM_BDTR_BKP_MORT ((uint16_t)0x2000) /*!<Break Polarity */ 05667 #define TIM_BDTR_AOE_MORT ((uint16_t)0x4000) /*!<Automatic Output enable */ 05668 #define TIM_BDTR_MOE_MORT ((uint16_t)0x8000) /*!<Main Output enable */ 05669 05670 /******************* Bit definition for TIM_DCR register ********************/ 05671 #define TIM_DCR_DBA_MORT ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */ 05672 #define TIM_DCR_DBA_0_MORT ((uint16_t)0x0001) /*!<Bit 0 */ 05673 #define TIM_DCR_DBA_1_MORT ((uint16_t)0x0002) /*!<Bit 1 */ 05674 #define TIM_DCR_DBA_2_MORT ((uint16_t)0x0004) /*!<Bit 2 */ 05675 #define TIM_DCR_DBA_3_MORT ((uint16_t)0x0008) /*!<Bit 3 */ 05676 #define TIM_DCR_DBA_4_MORT ((uint16_t)0x0010) /*!<Bit 4 */ 05677 05678 #define TIM_DCR_DBL_MORT ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */ 05679 #define TIM_DCR_DBL_0_MORT ((uint16_t)0x0100) /*!<Bit 0 */ 05680 #define TIM_DCR_DBL_1_MORT ((uint16_t)0x0200) /*!<Bit 1 */ 05681 #define TIM_DCR_DBL_2_MORT ((uint16_t)0x0400) /*!<Bit 2 */ 05682 #define TIM_DCR_DBL_3_MORT ((uint16_t)0x0800) /*!<Bit 3 */ 05683 #define TIM_DCR_DBL_4_MORT ((uint16_t)0x1000) /*!<Bit 4 */ 05684 05685 /******************* Bit definition for TIM_DMAR register *******************/ 05686 #define TIM_DMAR_DMAB_MORT ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */ 05687 05688 /******************* Bit definition for TIM_OR register *********************/ 05689 #define TIM_OR_TI4_RMP_MORT ((uint16_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5_MORT Input 4 remap) */ 05690 #define TIM_OR_TI4_RMP_0_MORT ((uint16_t)0x0040) /*!<Bit 0 */ 05691 #define TIM_OR_TI4_RMP_1_MORT ((uint16_t)0x0080) /*!<Bit 1 */ 05692 #define TIM_OR_ITR1_RMP_MORT ((uint16_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2_MORT Internal trigger 1 remap) */ 05693 #define TIM_OR_ITR1_RMP_0_MORT ((uint16_t)0x0400) /*!<Bit 0 */ 05694 #define TIM_OR_ITR1_RMP_1_MORT ((uint16_t)0x0800) /*!<Bit 1 */ 05695 05696 #if defined(STM32F410xx) || defined(STM32F413_423xx) 05697 /******************************************************************************/ 05698 /* */ 05699 /* Low Power Timer (LPTIM) */ 05700 /* */ 05701 /******************************************************************************/ 05702 /****************** Bit definition for LPTIM_ISR register *******************/ 05703 05704 /****************** Bit definition for LPTIM_ICR register *******************/ 05705 05706 /****************** Bit definition for LPTIM_IER register ********************/ 05707 05708 /****************** Bit definition for LPTIM_CFGR register *******************/ 05709 05710 05711 /****************** Bit definition for LPTIM_CR register ********************/ 05712 05713 /****************** Bit definition for LPTIM_CMP register *******************/ 05714 05715 /****************** Bit definition for LPTIM_ARR register *******************/ 05716 05717 /****************** Bit definition for LPTIM_CNT register *******************/ 05718 05719 /****************** Bit definition for LPTIM_OR register *******************/ 05720 05721 #endif /* STM32F410xx || STM32F413_423xx */ 05722 05723 /******************************************************************************/ 05724 /* */ 05725 /* Universal Synchronous Asynchronous Receiver Transmitter */ 05726 /* */ 05727 /******************************************************************************/ 05728 /******************* Bit definition for USART_SR register *******************/ 05729 05730 /******************* Bit definition for USART_DR register *******************/ 05731 05732 /****************** Bit definition for USART_BRR register *******************/ 05733 05734 /****************** Bit definition for USART_CR1 register *******************/ 05735 05736 /****************** Bit definition for USART_CR2 register *******************/ 05737 05738 /****************** Bit definition for USART_CR3 register *******************/ 05739 05740 /****************** Bit definition for USART_GTPR register ******************/ 05741 05742 /******************************************************************************/ 05743 /* */ 05744 /* Window WATCHDOG */ 05745 /* */ 05746 /******************************************************************************/ 05747 /******************* Bit definition for WWDG_CR register ********************/ 05748 05749 /******************* Bit definition for WWDG_CFR register *******************/ 05750 05751 /******************* Bit definition for WWDG_SR register ********************/ 05752 05753 /******************************************************************************/ 05754 /* */ 05755 /* DBG */ 05756 /* */ 05757 /******************************************************************************/ 05758 /******************** Bit definition for DBGMCU_IDCODE register *************/ 05759 05760 /******************** Bit definition for DBGMCU_CR register *****************/ 05761 05762 05763 /******************** Bit definition for DBGMCU_APB1_FZ register ************/ 05764 05765 05766 /******************** Bit definition for DBGMCU_APB1_FZ register ************/ 05767 05768 05769 /******************************************************************************/ 05770 /* */ 05771 /* Ethernet MAC Registers bits definitions */ 05772 /* */ 05773 /******************************************************************************/ 05774 /* Bit definition for Ethernet MAC Control Register register */ 05775 05776 05777 /* Bit definition for Ethernet MAC Frame Filter Register */ 05778 05779 /* Bit definition for Ethernet MAC Flow Control Register */ 05780 05781 05782 /* Bit definition for Ethernet MAC Status Register */ 05783 05784 05785 /* Bit definition for Ethernet MAC Interrupt Mask Register */ 05786 05787 05788 /* Bit definition for Ethernet MAC Address0 High Register */ 05789 05790 05791 /* Bit definition for Ethernet MAC Address0 Low Register */ 05792 05793 05794 /* Bit definition for Ethernet MAC Address1 High Register */ 05795 05796 /* Bit definition for Ethernet MAC Address1 Low Register */ 05797 05798 05799 /* Bit definition for Ethernet MAC Address2 High Register */ 05800 05801 05802 /* Bit definition for Ethernet MAC Address2 Low Register */ 05803 05804 05805 /* Bit definition for Ethernet MAC Address3 High Register */ 05806 05807 05808 /* Bit definition for Ethernet MAC Address3 Low Register */ 05809 05810 05811 /******************************************************************************/ 05812 /* Ethernet MMC Registers bits definition */ 05813 /******************************************************************************/ 05814 05815 /* Bit definition for Ethernet MMC Contol Register */ 05816 05817 05818 /* Bit definition for Ethernet MMC Receive Interrupt Register */ 05819 05820 /* Bit definition for Ethernet MMC Transmit Interrupt Register */ 05821 05822 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ 05823 05824 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ 05825 05826 /******************************************************************************/ 05827 /* Ethernet PTP Registers bits definition */ 05828 /******************************************************************************/ 05829 05830 /* Bit definition for Ethernet PTP Time Stamp Contol Register */ 05831 05832 05833 05834 /******************************************************************************/ 05835 /* Ethernet DMA Registers bits definition */ 05836 /******************************************************************************/ 05837 05838 /* Bit definition for Ethernet DMA Bus Mode Register */ 05839 05840 05841 /** 05842 * 05843 */ 05844 05845 /** 05846 * @} 05847 */ 05848 05849 #ifdef USE_STDPERIPH_DRIVER 05850 #include "stm32f4xx_conf.h" 05851 #endif /* USE_STDPERIPH_DRIVER */ 05852 05853 /** @addtogroup Exported_macro 05854 * @{ 05855 */ 05856 05857 #define SET_BIT_MORT(REG, BIT) ((REG) |= (BIT)) 05858 05859 #define CLEAR_BIT_MORT(REG, BIT) ((REG) &= ~(BIT)) 05860 05861 #define READ_BIT_MORT(REG, BIT) ((REG) & (BIT)) 05862 05863 #define CLEAR_REG_MORT(REG) ((REG) = (0x0)) 05864 05865 #define WRITE_REG_MORT(REG, VAL) ((REG) = (VAL)) 05866 05867 #define READ_REG_MORT(REG) ((REG)) 05868 05869 #define MODIFY_REG_MORT(REG, CLEARMASK, SETMASK) WRITE_REG_MORT((REG), (((READ_REG_MORT(REG)) & (~(CLEARMASK))) | (SETMASK))) 05870 05871 /** 05872 * @} 05873 */ 05874 05875 #ifdef __cplusplus 05876 } 05877 #endif /* __cplusplus */ 05878 05879 #endif /* __STM32F4xx_H */ 05880 05881 /** 05882 * @} 05883 */ 05884 05885 /** 05886 * @} 05887 */ 05888 05889 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 05890 05891 05892 05893 05894 05895
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