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Dependencies:   mbed

mbed-rtos/rtx/TARGET_CORTEX_A/rt_HAL_CM.h@3:3bc2882232a6, 2021-04-15 (annotated)

Committer:
qmaker
Date:
Thu Apr 15 08:43:24 2021 +0000
Revision:
3:3bc2882232a6
Parent:
0:0d257bbf5c05 
en cours de dev

Who changed what in which revision?

UserRevisionLine numberNew contents of line
qmaker 0:0d257bbf5c05 1 /*----------------------------------------------------------------------------
qmaker 0:0d257bbf5c05 2 * RL-ARM - RTX
qmaker 0:0d257bbf5c05 3 *----------------------------------------------------------------------------
qmaker 0:0d257bbf5c05 4 * Name: RT_HAL_CM.H
qmaker 0:0d257bbf5c05 5 * Purpose: Hardware Abstraction Layer for Cortex-M definitions
qmaker 0:0d257bbf5c05 6 * Rev.: V4.70
qmaker 0:0d257bbf5c05 7 *----------------------------------------------------------------------------
qmaker 0:0d257bbf5c05 8 *
qmaker 0:0d257bbf5c05 9 * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
qmaker 0:0d257bbf5c05 10 * All rights reserved.
qmaker 0:0d257bbf5c05 11 * Redistribution and use in source and binary forms, with or without
qmaker 0:0d257bbf5c05 12 * modification, are permitted provided that the following conditions are met:
qmaker 0:0d257bbf5c05 13 * - Redistributions of source code must retain the above copyright
qmaker 0:0d257bbf5c05 14 * notice, this list of conditions and the following disclaimer.
qmaker 0:0d257bbf5c05 15 * - Redistributions in binary form must reproduce the above copyright
qmaker 0:0d257bbf5c05 16 * notice, this list of conditions and the following disclaimer in the
qmaker 0:0d257bbf5c05 17 * documentation and/or other materials provided with the distribution.
qmaker 0:0d257bbf5c05 18 * - Neither the name of ARM nor the names of its contributors may be used
qmaker 0:0d257bbf5c05 19 * to endorse or promote products derived from this software without
qmaker 0:0d257bbf5c05 20 * specific prior written permission.
qmaker 0:0d257bbf5c05 21 *
qmaker 0:0d257bbf5c05 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
qmaker 0:0d257bbf5c05 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
qmaker 0:0d257bbf5c05 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
qmaker 0:0d257bbf5c05 25 * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
qmaker 0:0d257bbf5c05 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
qmaker 0:0d257bbf5c05 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
qmaker 0:0d257bbf5c05 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
qmaker 0:0d257bbf5c05 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
qmaker 0:0d257bbf5c05 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
qmaker 0:0d257bbf5c05 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
qmaker 0:0d257bbf5c05 32 * POSSIBILITY OF SUCH DAMAGE.
qmaker 0:0d257bbf5c05 33 *---------------------------------------------------------------------------*/
qmaker 0:0d257bbf5c05 34
qmaker 0:0d257bbf5c05 35 /* Definitions */
qmaker 0:0d257bbf5c05 36 #define INITIAL_xPSR 0x01000000
qmaker 0:0d257bbf5c05 37 #define DEMCR_TRCENA 0x01000000
qmaker 0:0d257bbf5c05 38 #define ITM_ITMENA 0x00000001
qmaker 0:0d257bbf5c05 39 #define MAGIC_WORD 0xE25A2EA5
qmaker 0:0d257bbf5c05 40
qmaker 0:0d257bbf5c05 41 #if defined (__CC_ARM) /* ARM Compiler */
qmaker 0:0d257bbf5c05 42
qmaker 0:0d257bbf5c05 43 #if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M) && !defined(NO_EXCLUSIVE_ACCESS))
qmaker 0:0d257bbf5c05 44 #define __USE_EXCLUSIVE_ACCESS
qmaker 0:0d257bbf5c05 45 #else
qmaker 0:0d257bbf5c05 46 #undef __USE_EXCLUSIVE_ACCESS
qmaker 0:0d257bbf5c05 47 #endif
qmaker 0:0d257bbf5c05 48
qmaker 0:0d257bbf5c05 49 /* Supress __ldrex and __strex deprecated warnings - "#3731-D: intrinsic is deprecated" */
qmaker 0:0d257bbf5c05 50 #ifdef __USE_EXCLUSIVE_ACCESS
qmaker 0:0d257bbf5c05 51 #pragma diag_suppress 3731
qmaker 0:0d257bbf5c05 52 #endif
qmaker 0:0d257bbf5c05 53
qmaker 0:0d257bbf5c05 54 #elif defined (__GNUC__) /* GNU Compiler */
qmaker 0:0d257bbf5c05 55
qmaker 0:0d257bbf5c05 56 #undef __USE_EXCLUSIVE_ACCESS
qmaker 0:0d257bbf5c05 57
qmaker 0:0d257bbf5c05 58 #if defined (__CORTEX_M0)
qmaker 0:0d257bbf5c05 59 #define __TARGET_ARCH_6S_M 1
qmaker 0:0d257bbf5c05 60 #else
qmaker 0:0d257bbf5c05 61 #define __TARGET_ARCH_6S_M 0
qmaker 0:0d257bbf5c05 62 #endif
qmaker 0:0d257bbf5c05 63
qmaker 0:0d257bbf5c05 64 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
qmaker 0:0d257bbf5c05 65 #define __TARGET_FPU_VFP 1
qmaker 0:0d257bbf5c05 66 #else
qmaker 0:0d257bbf5c05 67 #define __TARGET_FPU_VFP 0
qmaker 0:0d257bbf5c05 68 #endif
qmaker 0:0d257bbf5c05 69
qmaker 0:0d257bbf5c05 70 #define __inline inline
qmaker 0:0d257bbf5c05 71 #define __weak __attribute__((weak))
qmaker 0:0d257bbf5c05 72
qmaker 0:0d257bbf5c05 73 #ifndef __CMSIS_GENERIC
qmaker 0:0d257bbf5c05 74
qmaker 0:0d257bbf5c05 75 __attribute__((always_inline)) static inline void __enable_irq(void)
qmaker 0:0d257bbf5c05 76 {
qmaker 0:0d257bbf5c05 77 __asm volatile ("cpsie i");
qmaker 0:0d257bbf5c05 78 }
qmaker 0:0d257bbf5c05 79
qmaker 0:0d257bbf5c05 80 __attribute__((always_inline)) static inline U32 __disable_irq(void)
qmaker 0:0d257bbf5c05 81 {
qmaker 0:0d257bbf5c05 82 U32 result;
qmaker 0:0d257bbf5c05 83
qmaker 0:0d257bbf5c05 84 __asm volatile ("mrs %0, primask" : "=r" (result));
qmaker 0:0d257bbf5c05 85 __asm volatile ("cpsid i");
qmaker 0:0d257bbf5c05 86 return(result & 1);
qmaker 0:0d257bbf5c05 87 }
qmaker 0:0d257bbf5c05 88
qmaker 0:0d257bbf5c05 89 #endif
qmaker 0:0d257bbf5c05 90
qmaker 0:0d257bbf5c05 91 __attribute__(( always_inline)) static inline U8 __clz(U32 value)
qmaker 0:0d257bbf5c05 92 {
qmaker 0:0d257bbf5c05 93 U8 result;
qmaker 0:0d257bbf5c05 94
qmaker 0:0d257bbf5c05 95 __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
qmaker 0:0d257bbf5c05 96 return(result);
qmaker 0:0d257bbf5c05 97 }
qmaker 0:0d257bbf5c05 98
qmaker 0:0d257bbf5c05 99 #elif defined (__ICCARM__) /* IAR Compiler */
qmaker 0:0d257bbf5c05 100
qmaker 0:0d257bbf5c05 101 #undef __USE_EXCLUSIVE_ACCESS
qmaker 0:0d257bbf5c05 102
qmaker 0:0d257bbf5c05 103 #if (__CORE__ == __ARM6M__)
qmaker 0:0d257bbf5c05 104 #define __TARGET_ARCH_6S_M 1
qmaker 0:0d257bbf5c05 105 #else
qmaker 0:0d257bbf5c05 106 #define __TARGET_ARCH_6S_M 0
qmaker 0:0d257bbf5c05 107 #endif
qmaker 0:0d257bbf5c05 108
qmaker 0:0d257bbf5c05 109 #if defined __ARMVFP__
qmaker 0:0d257bbf5c05 110 #define __TARGET_FPU_VFP 1
qmaker 0:0d257bbf5c05 111 #else
qmaker 0:0d257bbf5c05 112 #define __TARGET_FPU_VFP 0
qmaker 0:0d257bbf5c05 113 #endif
qmaker 0:0d257bbf5c05 114
qmaker 0:0d257bbf5c05 115 #define __inline inline
qmaker 0:0d257bbf5c05 116
qmaker 0:0d257bbf5c05 117 #ifndef __CMSIS_GENERIC
qmaker 0:0d257bbf5c05 118
qmaker 0:0d257bbf5c05 119 static inline void __enable_irq(void)
qmaker 0:0d257bbf5c05 120 {
qmaker 0:0d257bbf5c05 121 __asm volatile ("cpsie i");
qmaker 0:0d257bbf5c05 122 }
qmaker 0:0d257bbf5c05 123
qmaker 0:0d257bbf5c05 124 static inline U32 __disable_irq(void)
qmaker 0:0d257bbf5c05 125 {
qmaker 0:0d257bbf5c05 126 U32 result;
qmaker 0:0d257bbf5c05 127
qmaker 0:0d257bbf5c05 128 __asm volatile ("mrs %0, primask" : "=r" (result));
qmaker 0:0d257bbf5c05 129 __asm volatile ("cpsid i");
qmaker 0:0d257bbf5c05 130 return(result & 1);
qmaker 0:0d257bbf5c05 131 }
qmaker 0:0d257bbf5c05 132
qmaker 0:0d257bbf5c05 133 #endif
qmaker 0:0d257bbf5c05 134
qmaker 0:0d257bbf5c05 135 static inline U8 __clz(U32 value)
qmaker 0:0d257bbf5c05 136 {
qmaker 0:0d257bbf5c05 137 U8 result;
qmaker 0:0d257bbf5c05 138
qmaker 0:0d257bbf5c05 139 __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
qmaker 0:0d257bbf5c05 140 return(result);
qmaker 0:0d257bbf5c05 141 }
qmaker 0:0d257bbf5c05 142
qmaker 0:0d257bbf5c05 143 #endif
qmaker 0:0d257bbf5c05 144
qmaker 0:0d257bbf5c05 145 /* NVIC registers */
qmaker 0:0d257bbf5c05 146 #define NVIC_ST_CTRL (*((volatile U32 *)0xE000E010))
qmaker 0:0d257bbf5c05 147 #define NVIC_ST_RELOAD (*((volatile U32 *)0xE000E014))
qmaker 0:0d257bbf5c05 148 #define NVIC_ST_CURRENT (*((volatile U32 *)0xE000E018))
qmaker 0:0d257bbf5c05 149 #define NVIC_ISER ((volatile U32 *)0xE000E100)
qmaker 0:0d257bbf5c05 150 #define NVIC_ICER ((volatile U32 *)0xE000E180)
qmaker 0:0d257bbf5c05 151 #if (__TARGET_ARCH_6S_M)
qmaker 0:0d257bbf5c05 152 #define NVIC_IP ((volatile U32 *)0xE000E400)
qmaker 0:0d257bbf5c05 153 #else
qmaker 0:0d257bbf5c05 154 #define NVIC_IP ((volatile U8 *)0xE000E400)
qmaker 0:0d257bbf5c05 155 #endif
qmaker 0:0d257bbf5c05 156 #define NVIC_INT_CTRL (*((volatile U32 *)0xE000ED04))
qmaker 0:0d257bbf5c05 157 #define NVIC_AIR_CTRL (*((volatile U32 *)0xE000ED0C))
qmaker 0:0d257bbf5c05 158 #define NVIC_SYS_PRI2 (*((volatile U32 *)0xE000ED1C))
qmaker 0:0d257bbf5c05 159 #define NVIC_SYS_PRI3 (*((volatile U32 *)0xE000ED20))
qmaker 0:0d257bbf5c05 160
qmaker 0:0d257bbf5c05 161 #define OS_PEND_IRQ() NVIC_INT_CTRL = (1<<28)
qmaker 0:0d257bbf5c05 162 #define OS_PENDING ((NVIC_INT_CTRL >> 26) & (1<<2 | 1))
qmaker 0:0d257bbf5c05 163 #define OS_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_PENDING) << 25
qmaker 0:0d257bbf5c05 164 #define OS_PEND(fl,p) NVIC_INT_CTRL = (fl | p<<2) << 26
qmaker 0:0d257bbf5c05 165 #define OS_LOCK() NVIC_ST_CTRL = 0x0005
qmaker 0:0d257bbf5c05 166 #define OS_UNLOCK() NVIC_ST_CTRL = 0x0007
qmaker 0:0d257bbf5c05 167
qmaker 0:0d257bbf5c05 168 #define OS_X_PENDING ((NVIC_INT_CTRL >> 28) & 1)
qmaker 0:0d257bbf5c05 169 #define OS_X_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_X_PENDING) << 27
qmaker 0:0d257bbf5c05 170 #define OS_X_PEND(fl,p) NVIC_INT_CTRL = (fl | p) << 28
qmaker 0:0d257bbf5c05 171 #if (__TARGET_ARCH_6S_M)
qmaker 0:0d257bbf5c05 172 #define OS_X_INIT(n) NVIC_IP[n>>2] |= 0xFF << (8*(n & 0x03)); \
qmaker 0:0d257bbf5c05 173 NVIC_ISER[n>>5] = 1 << (n & 0x1F)
qmaker 0:0d257bbf5c05 174 #else
qmaker 0:0d257bbf5c05 175 #define OS_X_INIT(n) NVIC_IP[n] = 0xFF; \
qmaker 0:0d257bbf5c05 176 NVIC_ISER[n>>5] = 1 << (n & 0x1F)
qmaker 0:0d257bbf5c05 177 #endif
qmaker 0:0d257bbf5c05 178 #define OS_X_LOCK(n) NVIC_ICER[n>>5] = 1 << (n & 0x1F)
qmaker 0:0d257bbf5c05 179 #define OS_X_UNLOCK(n) NVIC_ISER[n>>5] = 1 << (n & 0x1F)
qmaker 0:0d257bbf5c05 180
qmaker 0:0d257bbf5c05 181 /* Core Debug registers */
qmaker 0:0d257bbf5c05 182 #define DEMCR (*((volatile U32 *)0xE000EDFC))
qmaker 0:0d257bbf5c05 183
qmaker 0:0d257bbf5c05 184 /* ITM registers */
qmaker 0:0d257bbf5c05 185 #define ITM_CONTROL (*((volatile U32 *)0xE0000E80))
qmaker 0:0d257bbf5c05 186 #define ITM_ENABLE (*((volatile U32 *)0xE0000E00))
qmaker 0:0d257bbf5c05 187 #define ITM_PORT30_U32 (*((volatile U32 *)0xE0000078))
qmaker 0:0d257bbf5c05 188 #define ITM_PORT31_U32 (*((volatile U32 *)0xE000007C))
qmaker 0:0d257bbf5c05 189 #define ITM_PORT31_U16 (*((volatile U16 *)0xE000007C))
qmaker 0:0d257bbf5c05 190 #define ITM_PORT31_U8 (*((volatile U8 *)0xE000007C))
qmaker 0:0d257bbf5c05 191
qmaker 0:0d257bbf5c05 192 /* Variables */
qmaker 0:0d257bbf5c05 193 extern BIT dbg_msg;
qmaker 0:0d257bbf5c05 194
qmaker 0:0d257bbf5c05 195 /* Functions */
qmaker 0:0d257bbf5c05 196 #ifdef __USE_EXCLUSIVE_ACCESS
qmaker 0:0d257bbf5c05 197 #define rt_inc(p) while(__strex((__ldrex(p)+1),p))
qmaker 0:0d257bbf5c05 198 #define rt_dec(p) while(__strex((__ldrex(p)-1),p))
qmaker 0:0d257bbf5c05 199 #else
qmaker 0:0d257bbf5c05 200 #define rt_inc(p) __disable_irq();(*p)++;__enable_irq();
qmaker 0:0d257bbf5c05 201 #define rt_dec(p) __disable_irq();(*p)--;__enable_irq();
qmaker 0:0d257bbf5c05 202 #endif
qmaker 0:0d257bbf5c05 203
qmaker 0:0d257bbf5c05 204 __inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
qmaker 0:0d257bbf5c05 205 U32 cnt,c2;
qmaker 0:0d257bbf5c05 206 #ifdef __USE_EXCLUSIVE_ACCESS
qmaker 0:0d257bbf5c05 207 do {
qmaker 0:0d257bbf5c05 208 if ((cnt = __ldrex(count)) == size) {
qmaker 0:0d257bbf5c05 209 __clrex();
qmaker 0:0d257bbf5c05 210 return (cnt); }
qmaker 0:0d257bbf5c05 211 } while (__strex(cnt+1, count));
qmaker 0:0d257bbf5c05 212 do {
qmaker 0:0d257bbf5c05 213 c2 = (cnt = __ldrex(first)) + 1;
qmaker 0:0d257bbf5c05 214 if (c2 == size) c2 = 0;
qmaker 0:0d257bbf5c05 215 } while (__strex(c2, first));
qmaker 0:0d257bbf5c05 216 #else
qmaker 0:0d257bbf5c05 217 __disable_irq();
qmaker 0:0d257bbf5c05 218 if ((cnt = *count) < size) {
qmaker 0:0d257bbf5c05 219 *count = cnt+1;
qmaker 0:0d257bbf5c05 220 c2 = (cnt = *first) + 1;
qmaker 0:0d257bbf5c05 221 if (c2 == size) c2 = 0;
qmaker 0:0d257bbf5c05 222 *first = c2;
qmaker 0:0d257bbf5c05 223 }
qmaker 0:0d257bbf5c05 224 __enable_irq ();
qmaker 0:0d257bbf5c05 225 #endif
qmaker 0:0d257bbf5c05 226 return (cnt);
qmaker 0:0d257bbf5c05 227 }
qmaker 0:0d257bbf5c05 228
qmaker 0:0d257bbf5c05 229 __inline static void rt_systick_init (void) {
qmaker 0:0d257bbf5c05 230 NVIC_ST_RELOAD = os_trv;
qmaker 0:0d257bbf5c05 231 NVIC_ST_CURRENT = 0;
qmaker 0:0d257bbf5c05 232 NVIC_ST_CTRL = 0x0007;
qmaker 0:0d257bbf5c05 233 NVIC_SYS_PRI3 |= 0xFF000000;
qmaker 0:0d257bbf5c05 234 }
qmaker 0:0d257bbf5c05 235
qmaker 0:0d257bbf5c05 236 __inline static U32 rt_systick_val (void) {
qmaker 0:0d257bbf5c05 237 return (os_trv - NVIC_ST_CURRENT);
qmaker 0:0d257bbf5c05 238 }
qmaker 0:0d257bbf5c05 239
qmaker 0:0d257bbf5c05 240 __inline static U32 rt_systick_ovf (void) {
qmaker 0:0d257bbf5c05 241 return ((NVIC_INT_CTRL >> 26) & 1);
qmaker 0:0d257bbf5c05 242 }
qmaker 0:0d257bbf5c05 243
qmaker 0:0d257bbf5c05 244 __inline static void rt_svc_init (void) {
qmaker 0:0d257bbf5c05 245 #if !(__TARGET_ARCH_6S_M)
qmaker 0:0d257bbf5c05 246 int sh,prigroup;
qmaker 0:0d257bbf5c05 247 #endif
qmaker 0:0d257bbf5c05 248 NVIC_SYS_PRI3 |= 0x00FF0000;
qmaker 0:0d257bbf5c05 249 #if (__TARGET_ARCH_6S_M)
qmaker 0:0d257bbf5c05 250 NVIC_SYS_PRI2 |= (NVIC_SYS_PRI3<<(8+1)) & 0xFC000000;
qmaker 0:0d257bbf5c05 251 #else
qmaker 0:0d257bbf5c05 252 sh = 8 - __clz (~((NVIC_SYS_PRI3 << 8) & 0xFF000000));
qmaker 0:0d257bbf5c05 253 prigroup = ((NVIC_AIR_CTRL >> 8) & 0x07);
qmaker 0:0d257bbf5c05 254 if (prigroup >= sh) {
qmaker 0:0d257bbf5c05 255 sh = prigroup + 1;
qmaker 0:0d257bbf5c05 256 }
qmaker 0:0d257bbf5c05 257 NVIC_SYS_PRI2 = ((0xFEFFFFFF << sh) & 0xFF000000) | (NVIC_SYS_PRI2 & 0x00FFFFFF);
qmaker 0:0d257bbf5c05 258 #endif
qmaker 0:0d257bbf5c05 259 }
qmaker 0:0d257bbf5c05 260
qmaker 0:0d257bbf5c05 261 extern void rt_set_PSP (U32 stack);
qmaker 0:0d257bbf5c05 262 extern U32 rt_get_PSP (void);
qmaker 0:0d257bbf5c05 263 extern void os_set_env (void);
qmaker 0:0d257bbf5c05 264 extern void *_alloc_box (void *box_mem);
qmaker 0:0d257bbf5c05 265 extern int _free_box (void *box_mem, void *box);
qmaker 0:0d257bbf5c05 266
qmaker 0:0d257bbf5c05 267 extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
qmaker 0:0d257bbf5c05 268 extern void rt_ret_val (P_TCB p_TCB, U32 v0);
qmaker 0:0d257bbf5c05 269 extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);
qmaker 0:0d257bbf5c05 270
qmaker 0:0d257bbf5c05 271 extern void dbg_init (void);
qmaker 0:0d257bbf5c05 272 extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
qmaker 0:0d257bbf5c05 273 extern void dbg_task_switch (U32 task_id);
qmaker 0:0d257bbf5c05 274
qmaker 0:0d257bbf5c05 275 #ifdef DBG_MSG
qmaker 0:0d257bbf5c05 276 #define DBG_INIT() dbg_init()
qmaker 0:0d257bbf5c05 277 #define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create)
qmaker 0:0d257bbf5c05 278 #define DBG_TASK_SWITCH(task_id) if (dbg_msg && (os_tsk.new_tsk!=os_tsk.run)) \
qmaker 0:0d257bbf5c05 279 dbg_task_switch(task_id)
qmaker 0:0d257bbf5c05 280 #else
qmaker 0:0d257bbf5c05 281 #define DBG_INIT()
qmaker 0:0d257bbf5c05 282 #define DBG_TASK_NOTIFY(p_tcb,create)
qmaker 0:0d257bbf5c05 283 #define DBG_TASK_SWITCH(task_id)
qmaker 0:0d257bbf5c05 284 #endif
qmaker 0:0d257bbf5c05 285
qmaker 0:0d257bbf5c05 286 /*----------------------------------------------------------------------------
qmaker 0:0d257bbf5c05 287 * end of file
qmaker 0:0d257bbf5c05 288 *---------------------------------------------------------------------------*/
qmaker 0:0d257bbf5c05 289