Paul Paterson / mbed-src-CanNucleoF0

mbed library sources, include can_api for nucleo-f091rc

Dependents:   CanNucleoF0_example

Fork of mbed-src by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC176X/system_LPC17xx.h@645:13c87cbecd54, 2016-01-07 (annotated)

Committer:
ptpaterson
Date:
Thu Jan 07 05:49:05 2016 +0000
Revision:
645:13c87cbecd54
Parent:
13:0645d8841f51 
corrected freeze on CAN_RECEIVE_IT

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /******************************************************************************
emilmont 10:3bc89ef62ce7 2 * @file: system_LPC17xx.h
emilmont 10:3bc89ef62ce7 3 * @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Header File
emilmont 10:3bc89ef62ce7 4 * for the NXP LPC17xx Device Series
emilmont 10:3bc89ef62ce7 5 * @version: V1.02
emilmont 10:3bc89ef62ce7 6 * @date: 27. July 2009
emilmont 10:3bc89ef62ce7 7 *----------------------------------------------------------------------------
emilmont 10:3bc89ef62ce7 8 *
emilmont 10:3bc89ef62ce7 9 * Copyright (C) 2009 ARM Limited. All rights reserved.
emilmont 10:3bc89ef62ce7 10 *
emilmont 10:3bc89ef62ce7 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M3
emilmont 10:3bc89ef62ce7 12 * processor based microcontrollers. This file can be freely distributed
emilmont 10:3bc89ef62ce7 13 * within development tools that are supporting such ARM based processors.
emilmont 10:3bc89ef62ce7 14 *
emilmont 10:3bc89ef62ce7 15 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont 10:3bc89ef62ce7 16 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont 10:3bc89ef62ce7 17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont 10:3bc89ef62ce7 18 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont 10:3bc89ef62ce7 19 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont 10:3bc89ef62ce7 20 *
emilmont 10:3bc89ef62ce7 21 ******************************************************************************/
emilmont 10:3bc89ef62ce7 22
emilmont 10:3bc89ef62ce7 23
emilmont 10:3bc89ef62ce7 24 #ifndef __SYSTEM_LPC17xx_H
emilmont 10:3bc89ef62ce7 25 #define __SYSTEM_LPC17xx_H
emilmont 10:3bc89ef62ce7 26
emilmont 10:3bc89ef62ce7 27 #ifdef __cplusplus
emilmont 10:3bc89ef62ce7 28 extern "C" {
emilmont 10:3bc89ef62ce7 29 #endif
emilmont 10:3bc89ef62ce7 30
emilmont 10:3bc89ef62ce7 31 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
emilmont 10:3bc89ef62ce7 32
emilmont 10:3bc89ef62ce7 33
emilmont 10:3bc89ef62ce7 34 /**
emilmont 10:3bc89ef62ce7 35 * Initialize the system
emilmont 10:3bc89ef62ce7 36 *
emilmont 10:3bc89ef62ce7 37 * @param none
emilmont 10:3bc89ef62ce7 38 * @return none
emilmont 10:3bc89ef62ce7 39 *
emilmont 10:3bc89ef62ce7 40 * @brief Setup the microcontroller system.
emilmont 10:3bc89ef62ce7 41 * Initialize the System and update the SystemCoreClock variable.
emilmont 10:3bc89ef62ce7 42 */
emilmont 10:3bc89ef62ce7 43 extern void SystemInit (void);
emilmont 10:3bc89ef62ce7 44
emilmont 10:3bc89ef62ce7 45 /**
emilmont 10:3bc89ef62ce7 46 * Update SystemCoreClock variable
emilmont 10:3bc89ef62ce7 47 *
emilmont 10:3bc89ef62ce7 48 * @param none
emilmont 10:3bc89ef62ce7 49 * @return none
emilmont 10:3bc89ef62ce7 50 *
emilmont 10:3bc89ef62ce7 51 * @brief Updates the SystemCoreClock with current core Clock
emilmont 10:3bc89ef62ce7 52 * retrieved from cpu registers.
emilmont 10:3bc89ef62ce7 53 */
emilmont 10:3bc89ef62ce7 54 extern void SystemCoreClockUpdate (void);
emilmont 10:3bc89ef62ce7 55
emilmont 10:3bc89ef62ce7 56 #ifdef __cplusplus
emilmont 10:3bc89ef62ce7 57 }
emilmont 10:3bc89ef62ce7 58 #endif
emilmont 10:3bc89ef62ce7 59
emilmont 10:3bc89ef62ce7 60 #endif /* __SYSTEM_LPC17xx_H */