Paul Paterson / mbed-dev

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targets/TARGET_WIZNET/TARGET_W7500x/rtc_api.c@150:cd63f849362a, 2016-11-03 (annotated)

Committer:
ptpaterson
Date:
Thu Nov 03 16:21:53 2016 +0000
Revision:
150:cd63f849362a
Parent:
149:156823d33999 
targets LPC11Cxx, LPC15xx:  can_api can_filter function properly returns 0 if handle argument is out of bounds (handle > 32).

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #include "rtc_api.h"
<> 144:ef7eb2e8f9f7 17 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 18 #include "W7500x_pwm.h"
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 time_t wiz_rtc_time;
<> 144:ef7eb2e8f9f7 21 char rtc_enabled = 0;
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 24 extern "C"{
<> 144:ef7eb2e8f9f7 25 #endif
<> 144:ef7eb2e8f9f7 26 void PWM3_Handler(void)
<> 144:ef7eb2e8f9f7 27 {
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 wiz_rtc_time++;
<> 144:ef7eb2e8f9f7 30 PWM_CH3_ClearOverflowInt();
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 }
<> 144:ef7eb2e8f9f7 33 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 34 }
<> 144:ef7eb2e8f9f7 35 #endif
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 void rtc_init(void) {
<> 144:ef7eb2e8f9f7 40 PWM_TimerModeInitTypeDef TimerModeStructure;
<> 144:ef7eb2e8f9f7 41 *(volatile uint32_t *)(0x410010e0) = 0x03;
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /* Timer mode configuration */
<> 144:ef7eb2e8f9f7 44 TimerModeStructure.PWM_CHn_PR = 7;
<> 144:ef7eb2e8f9f7 45 TimerModeStructure.PWM_CHn_MR = 1;
<> 144:ef7eb2e8f9f7 46 TimerModeStructure.PWM_CHn_LR = 0xF4240;
<> 144:ef7eb2e8f9f7 47 TimerModeStructure.PWM_CHn_UDMR = PWM_CHn_UDMR_UpCount;
<> 144:ef7eb2e8f9f7 48 TimerModeStructure.PWM_CHn_PDMR = PWM_CHn_PDMR_Periodic;
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 PWM_TimerModeInit(PWM_CH3, &TimerModeStructure);
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /* PWM interrupt configuration */
<> 144:ef7eb2e8f9f7 53 PWM_IntConfig(PWM_CH3, ENABLE);
<> 144:ef7eb2e8f9f7 54 PWM_CHn_IntConfig(PWM_CH3, PWM_CHn_IER_OIE, ENABLE);
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /* PWM channel 0 start */
<> 144:ef7eb2e8f9f7 57 PWM_CHn_Start(PWM_CH3);
<> 144:ef7eb2e8f9f7 58 NVIC_SetVector(PWM3_IRQn, (uint32_t)PWM3_Handler);
<> 144:ef7eb2e8f9f7 59 NVIC_EnableIRQ(PWM3_IRQn);
<> 144:ef7eb2e8f9f7 60 rtc_enabled = 1;
<> 144:ef7eb2e8f9f7 61 }
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 void rtc_free(void) {
<> 144:ef7eb2e8f9f7 64 // [TODO]
<> 144:ef7eb2e8f9f7 65 }
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 int rtc_isenabled(void) {
<> 144:ef7eb2e8f9f7 69 return rtc_enabled;
<> 144:ef7eb2e8f9f7 70 }
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 time_t rtc_read(void) {
<> 144:ef7eb2e8f9f7 74 return wiz_rtc_time;
<> 144:ef7eb2e8f9f7 75 }
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 void rtc_write(time_t t) {
<> 144:ef7eb2e8f9f7 78 //*(volatile uint32_t *)(0x41001008) = 0x42; // timer disable, interrupt disable
<> 144:ef7eb2e8f9f7 79 wiz_rtc_time = t;
<> 144:ef7eb2e8f9f7 80 //*(volatile uint32_t *)(0x41001008) = 0x72; // timer enable interrupt enable
<> 144:ef7eb2e8f9f7 81 }