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targets/hal/TARGET_NXP/TARGET_LPC15XX/gpio_irq_api.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /* mbed Microcontroller Library
bogdanm 0:9b334a45a8ff 2 * Copyright (c) 2006-2013 ARM Limited
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Licensed under the Apache License, Version 2.0 (the "License");
bogdanm 0:9b334a45a8ff 5 * you may not use this file except in compliance with the License.
bogdanm 0:9b334a45a8ff 6 * You may obtain a copy of the License at
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * http://www.apache.org/licenses/LICENSE-2.0
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * Unless required by applicable law or agreed to in writing, software
bogdanm 0:9b334a45a8ff 11 * distributed under the License is distributed on an "AS IS" BASIS,
bogdanm 0:9b334a45a8ff 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bogdanm 0:9b334a45a8ff 13 * See the License for the specific language governing permissions and
bogdanm 0:9b334a45a8ff 14 * limitations under the License.
bogdanm 0:9b334a45a8ff 15 */
bogdanm 0:9b334a45a8ff 16 #include <stddef.h>
bogdanm 0:9b334a45a8ff 17
bogdanm 0:9b334a45a8ff 18 #include "cmsis.h"
bogdanm 0:9b334a45a8ff 19 #include "gpio_irq_api.h"
bogdanm 0:9b334a45a8ff 20 #include "mbed_error.h"
bogdanm 0:9b334a45a8ff 21
bogdanm 0:9b334a45a8ff 22 #define CHANNEL_NUM 8
bogdanm 0:9b334a45a8ff 23 #define LPC_GPIO_X LPC_PINT
bogdanm 0:9b334a45a8ff 24 #define PININT_IRQ PIN_INT0_IRQn
bogdanm 0:9b334a45a8ff 25
bogdanm 0:9b334a45a8ff 26 static uint32_t channel_ids[CHANNEL_NUM] = {0};
bogdanm 0:9b334a45a8ff 27 static gpio_irq_handler irq_handler;
bogdanm 0:9b334a45a8ff 28
bogdanm 0:9b334a45a8ff 29 static inline void handle_interrupt_in(uint32_t channel) {
bogdanm 0:9b334a45a8ff 30 uint32_t ch_bit = (1 << channel);
bogdanm 0:9b334a45a8ff 31 // Return immediately if:
bogdanm 0:9b334a45a8ff 32 // * The interrupt was already served
bogdanm 0:9b334a45a8ff 33 // * There is no user handler
bogdanm 0:9b334a45a8ff 34 // * It is a level interrupt, not an edge interrupt
bogdanm 0:9b334a45a8ff 35 if ( ((LPC_GPIO_X->IST & ch_bit) == 0) ||
bogdanm 0:9b334a45a8ff 36 (channel_ids[channel] == 0 ) ||
bogdanm 0:9b334a45a8ff 37 (LPC_GPIO_X->ISEL & ch_bit ) ) return;
bogdanm 0:9b334a45a8ff 38
bogdanm 0:9b334a45a8ff 39 if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) {
bogdanm 0:9b334a45a8ff 40 irq_handler(channel_ids[channel], IRQ_RISE);
bogdanm 0:9b334a45a8ff 41 LPC_GPIO_X->RISE = ch_bit;
bogdanm 0:9b334a45a8ff 42 }
bogdanm 0:9b334a45a8ff 43 if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) {
bogdanm 0:9b334a45a8ff 44 irq_handler(channel_ids[channel], IRQ_FALL);
bogdanm 0:9b334a45a8ff 45 LPC_GPIO_X->FALL = ch_bit;
bogdanm 0:9b334a45a8ff 46 }
bogdanm 0:9b334a45a8ff 47 LPC_GPIO_X->IST = ch_bit;
bogdanm 0:9b334a45a8ff 48 }
bogdanm 0:9b334a45a8ff 49
bogdanm 0:9b334a45a8ff 50 void gpio_irq0(void) {handle_interrupt_in(0);}
bogdanm 0:9b334a45a8ff 51 void gpio_irq1(void) {handle_interrupt_in(1);}
bogdanm 0:9b334a45a8ff 52 void gpio_irq2(void) {handle_interrupt_in(2);}
bogdanm 0:9b334a45a8ff 53 void gpio_irq3(void) {handle_interrupt_in(3);}
bogdanm 0:9b334a45a8ff 54 void gpio_irq4(void) {handle_interrupt_in(4);}
bogdanm 0:9b334a45a8ff 55 void gpio_irq5(void) {handle_interrupt_in(5);}
bogdanm 0:9b334a45a8ff 56 void gpio_irq6(void) {handle_interrupt_in(6);}
bogdanm 0:9b334a45a8ff 57 void gpio_irq7(void) {handle_interrupt_in(7);}
bogdanm 0:9b334a45a8ff 58
bogdanm 0:9b334a45a8ff 59 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
bogdanm 0:9b334a45a8ff 60 // PINT only supprt GPIO port 0 and 1 interrupt
bogdanm 0:9b334a45a8ff 61 if (pin >= P2_0) return -1;
bogdanm 0:9b334a45a8ff 62
bogdanm 0:9b334a45a8ff 63 irq_handler = handler;
bogdanm 0:9b334a45a8ff 64
bogdanm 0:9b334a45a8ff 65 int found_free_channel = 0;
bogdanm 0:9b334a45a8ff 66 int i = 0;
bogdanm 0:9b334a45a8ff 67 for (i=0; i<CHANNEL_NUM; i++) {
bogdanm 0:9b334a45a8ff 68 if (channel_ids[i] == 0) {
bogdanm 0:9b334a45a8ff 69 channel_ids[i] = id;
bogdanm 0:9b334a45a8ff 70 obj->ch = i;
bogdanm 0:9b334a45a8ff 71 found_free_channel = 1;
bogdanm 0:9b334a45a8ff 72 break;
bogdanm 0:9b334a45a8ff 73 }
bogdanm 0:9b334a45a8ff 74 }
bogdanm 0:9b334a45a8ff 75 if (!found_free_channel) return -1;
bogdanm 0:9b334a45a8ff 76
bogdanm 0:9b334a45a8ff 77 /* Enable AHB clock to the PIN, GPIO0/1, IOCON and MUX domain. */
bogdanm 0:9b334a45a8ff 78 LPC_SYSCON->SYSAHBCLKCTRL0 |= ((1 << 18) | (0x1D << 11));
bogdanm 0:9b334a45a8ff 79
bogdanm 0:9b334a45a8ff 80 LPC_INMUX->PINTSEL[obj->ch] = pin;
bogdanm 0:9b334a45a8ff 81
bogdanm 0:9b334a45a8ff 82 // Interrupt Wake-Up Enable
bogdanm 0:9b334a45a8ff 83 LPC_SYSCON->STARTERP0 |= (1 << (obj->ch + 5));
bogdanm 0:9b334a45a8ff 84
bogdanm 0:9b334a45a8ff 85 LPC_GPIO_PORT->DIR[pin >> 5] &= ~(1 << (pin & 0x1F));
bogdanm 0:9b334a45a8ff 86
bogdanm 0:9b334a45a8ff 87 void (*channels_irq)(void) = NULL;
bogdanm 0:9b334a45a8ff 88 switch (obj->ch) {
bogdanm 0:9b334a45a8ff 89 case 0: channels_irq = &gpio_irq0; break;
bogdanm 0:9b334a45a8ff 90 case 1: channels_irq = &gpio_irq1; break;
bogdanm 0:9b334a45a8ff 91 case 2: channels_irq = &gpio_irq2; break;
bogdanm 0:9b334a45a8ff 92 case 3: channels_irq = &gpio_irq3; break;
bogdanm 0:9b334a45a8ff 93 case 4: channels_irq = &gpio_irq4; break;
bogdanm 0:9b334a45a8ff 94 case 5: channels_irq = &gpio_irq5; break;
bogdanm 0:9b334a45a8ff 95 case 6: channels_irq = &gpio_irq6; break;
bogdanm 0:9b334a45a8ff 96 case 7: channels_irq = &gpio_irq7; break;
bogdanm 0:9b334a45a8ff 97 }
bogdanm 0:9b334a45a8ff 98 NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
bogdanm 0:9b334a45a8ff 99 NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 return 0;
bogdanm 0:9b334a45a8ff 102 }
bogdanm 0:9b334a45a8ff 103
bogdanm 0:9b334a45a8ff 104 void gpio_irq_free(gpio_irq_t *obj) {
bogdanm 0:9b334a45a8ff 105 channel_ids[obj->ch] = 0;
bogdanm 0:9b334a45a8ff 106 LPC_SYSCON->STARTERP0 &= ~(1 << (obj->ch + 5));
bogdanm 0:9b334a45a8ff 107 }
bogdanm 0:9b334a45a8ff 108
bogdanm 0:9b334a45a8ff 109 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
bogdanm 0:9b334a45a8ff 110 unsigned int ch_bit = (1 << obj->ch);
bogdanm 0:9b334a45a8ff 111
bogdanm 0:9b334a45a8ff 112 // Clear interrupt
bogdanm 0:9b334a45a8ff 113 if (!(LPC_GPIO_X->ISEL & ch_bit))
bogdanm 0:9b334a45a8ff 114 LPC_GPIO_X->IST = ch_bit;
bogdanm 0:9b334a45a8ff 115
bogdanm 0:9b334a45a8ff 116 // Edge trigger
bogdanm 0:9b334a45a8ff 117 LPC_GPIO_X->ISEL &= ~ch_bit;
bogdanm 0:9b334a45a8ff 118 if (event == IRQ_RISE) {
bogdanm 0:9b334a45a8ff 119 if (enable) {
bogdanm 0:9b334a45a8ff 120 LPC_GPIO_X->IENR |= ch_bit;
bogdanm 0:9b334a45a8ff 121 } else {
bogdanm 0:9b334a45a8ff 122 LPC_GPIO_X->IENR &= ~ch_bit;
bogdanm 0:9b334a45a8ff 123 }
bogdanm 0:9b334a45a8ff 124 } else {
bogdanm 0:9b334a45a8ff 125 if (enable) {
bogdanm 0:9b334a45a8ff 126 LPC_GPIO_X->IENF |= ch_bit;
bogdanm 0:9b334a45a8ff 127 } else {
bogdanm 0:9b334a45a8ff 128 LPC_GPIO_X->IENF &= ~ch_bit;
bogdanm 0:9b334a45a8ff 129 }
bogdanm 0:9b334a45a8ff 130 }
bogdanm 0:9b334a45a8ff 131 }
bogdanm 0:9b334a45a8ff 132
bogdanm 0:9b334a45a8ff 133 void gpio_irq_enable(gpio_irq_t *obj) {
bogdanm 0:9b334a45a8ff 134 NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
bogdanm 0:9b334a45a8ff 135 }
bogdanm 0:9b334a45a8ff 136
bogdanm 0:9b334a45a8ff 137 void gpio_irq_disable(gpio_irq_t *obj) {
bogdanm 0:9b334a45a8ff 138 NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
bogdanm 0:9b334a45a8ff 139 }