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targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pwr.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
113:b3775bf36a83 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l0xx_hal_pwr.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.5.0
<> 144:ef7eb2e8f9f7 6 * @date 8-January-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of PWR HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32L0xx_HAL_PWR_H
<> 144:ef7eb2e8f9f7 40 #define __STM32L0xx_HAL_PWR_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32l0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32L0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @defgroup PWR PWR
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /** @defgroup PWR_Exported_Types PWR Exported Types
<> 144:ef7eb2e8f9f7 58 * @{
<> 144:ef7eb2e8f9f7 59 */
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /**
<> 144:ef7eb2e8f9f7 62 * @brief PWR PVD configuration structure definition
<> 144:ef7eb2e8f9f7 63 */
<> 144:ef7eb2e8f9f7 64 typedef struct
<> 144:ef7eb2e8f9f7 65 {
<> 144:ef7eb2e8f9f7 66 uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
<> 144:ef7eb2e8f9f7 67 This parameter can be a value of @ref PWR_PVD_detection_level */
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
<> 144:ef7eb2e8f9f7 70 This parameter can be a value of @ref PWR_PVD_Mode */
<> 144:ef7eb2e8f9f7 71 }PWR_PVDTypeDef;
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 /**
<> 144:ef7eb2e8f9f7 74 * @}
<> 144:ef7eb2e8f9f7 75 */
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 /** @addtogroup PWR_Private
<> 144:ef7eb2e8f9f7 78 * @{
<> 144:ef7eb2e8f9f7 79 */
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 #define PWR_EXTI_LINE_PVD EXTI_FTSR_TR16 /*!< External interrupt line 16 Connected to the PVD EXTI Line */
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 /**
<> 144:ef7eb2e8f9f7 84 * @}
<> 144:ef7eb2e8f9f7 85 */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /** @defgroup PWR_Exported_Constants PWR Exported Constants
<> 144:ef7eb2e8f9f7 88 * @{
<> 144:ef7eb2e8f9f7 89 */
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 /** @defgroup PWR_register_alias_address PWR Register alias address
<> 144:ef7eb2e8f9f7 92 * @{
<> 144:ef7eb2e8f9f7 93 */
<> 144:ef7eb2e8f9f7 94 #define PWR_WAKEUP_PIN1 PWR_CSR_EWUP1
<> 144:ef7eb2e8f9f7 95 #define PWR_WAKEUP_PIN2 PWR_CSR_EWUP2
<> 144:ef7eb2e8f9f7 96 #if defined (STM32L011xx) || defined (STM32L021xx) || defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L071xx) || \
<> 144:ef7eb2e8f9f7 97 defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
<> 144:ef7eb2e8f9f7 98 #define PWR_WAKEUP_PIN3 PWR_CSR_EWUP3
<> 144:ef7eb2e8f9f7 99 #endif
<> 144:ef7eb2e8f9f7 100 /**
<> 144:ef7eb2e8f9f7 101 * @}
<> 144:ef7eb2e8f9f7 102 */
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 /** @defgroup PWR_PVD_detection_level PVD detection level
<> 144:ef7eb2e8f9f7 105 * @{
<> 144:ef7eb2e8f9f7 106 */
<> 144:ef7eb2e8f9f7 107 #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
<> 144:ef7eb2e8f9f7 108 #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
<> 144:ef7eb2e8f9f7 109 #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
<> 144:ef7eb2e8f9f7 110 #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
<> 144:ef7eb2e8f9f7 111 #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
<> 144:ef7eb2e8f9f7 112 #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
<> 144:ef7eb2e8f9f7 113 #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
<> 144:ef7eb2e8f9f7 114 #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /* External input analog voltage
<> 144:ef7eb2e8f9f7 115 (Compare internally to VREFINT) */
<> 144:ef7eb2e8f9f7 116 /**
<> 144:ef7eb2e8f9f7 117 * @}
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 /** @defgroup PWR_PVD_Mode PWR PVD Mode
<> 144:ef7eb2e8f9f7 121 * @{
<> 144:ef7eb2e8f9f7 122 */
<> 144:ef7eb2e8f9f7 123 #define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */
<> 144:ef7eb2e8f9f7 124 #define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
<> 144:ef7eb2e8f9f7 125 #define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
<> 144:ef7eb2e8f9f7 126 #define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
<> 144:ef7eb2e8f9f7 127 #define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
<> 144:ef7eb2e8f9f7 128 #define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
<> 144:ef7eb2e8f9f7 129 #define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /**
<> 144:ef7eb2e8f9f7 132 * @}
<> 144:ef7eb2e8f9f7 133 */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
<> 144:ef7eb2e8f9f7 136 * @{
<> 144:ef7eb2e8f9f7 137 */
<> 144:ef7eb2e8f9f7 138 #define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 139 #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPSDSR
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 /**
<> 144:ef7eb2e8f9f7 142 * @}
<> 144:ef7eb2e8f9f7 143 */
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
<> 144:ef7eb2e8f9f7 146 * @{
<> 144:ef7eb2e8f9f7 147 */
<> 144:ef7eb2e8f9f7 148 #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
<> 144:ef7eb2e8f9f7 149 #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
<> 144:ef7eb2e8f9f7 150 /**
<> 144:ef7eb2e8f9f7 151 * @}
<> 144:ef7eb2e8f9f7 152 */
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
<> 144:ef7eb2e8f9f7 155 * @{
<> 144:ef7eb2e8f9f7 156 */
<> 144:ef7eb2e8f9f7 157 #define PWR_STOPENTRY_WFI ((uint8_t)0x01)
<> 144:ef7eb2e8f9f7 158 #define PWR_STOPENTRY_WFE ((uint8_t)0x02)
<> 144:ef7eb2e8f9f7 159 /**
<> 144:ef7eb2e8f9f7 160 * @}
<> 144:ef7eb2e8f9f7 161 */
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
<> 144:ef7eb2e8f9f7 164 * @{
<> 144:ef7eb2e8f9f7 165 */
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS_0
<> 144:ef7eb2e8f9f7 168 #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1
<> 144:ef7eb2e8f9f7 169 #define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
<> 144:ef7eb2e8f9f7 172 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
<> 144:ef7eb2e8f9f7 173 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
<> 144:ef7eb2e8f9f7 174 /**
<> 144:ef7eb2e8f9f7 175 * @}
<> 144:ef7eb2e8f9f7 176 */
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 /** @defgroup PWR_Flag PWR Flag
<> 144:ef7eb2e8f9f7 179 * @{
<> 144:ef7eb2e8f9f7 180 */
<> 144:ef7eb2e8f9f7 181 #define PWR_FLAG_WU PWR_CSR_WUF
<> 144:ef7eb2e8f9f7 182 #define PWR_FLAG_SB PWR_CSR_SBF
<> 144:ef7eb2e8f9f7 183 #define PWR_FLAG_PVDO PWR_CSR_PVDO
<> 144:ef7eb2e8f9f7 184 #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
<> 144:ef7eb2e8f9f7 185 #define PWR_FLAG_VOS PWR_CSR_VOSF
<> 144:ef7eb2e8f9f7 186 #define PWR_FLAG_REGLP PWR_CSR_REGLPF
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /**
<> 144:ef7eb2e8f9f7 190 * @}
<> 144:ef7eb2e8f9f7 191 */
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /**
<> 144:ef7eb2e8f9f7 194 * @}
<> 144:ef7eb2e8f9f7 195 */
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 /** @defgroup PWR_Exported_Macro PWR Exported Macros
<> 144:ef7eb2e8f9f7 198 * @{
<> 144:ef7eb2e8f9f7 199 */
<> 144:ef7eb2e8f9f7 200 /** @brief macros configure the main internal regulator output voltage.
<> 144:ef7eb2e8f9f7 201 * When exiting Low Power Run Mode or during dynamic voltage scaling configuration,
<> 144:ef7eb2e8f9f7 202 * the reference manual recommends to poll PWR_FLAG_REGLP bit to wait for the regulator
<> 144:ef7eb2e8f9f7 203 * to reach main mode (resp. to get stabilized) for a transition from 0 to 1.
<> 144:ef7eb2e8f9f7 204 * Only then the clock can be increased.
<> 144:ef7eb2e8f9f7 205 *
<> 144:ef7eb2e8f9f7 206 * @param __REGULATOR__: specifies the regulator output voltage to achieve
<> 144:ef7eb2e8f9f7 207 * a tradeoff between performance and power consumption when the device does
<> 144:ef7eb2e8f9f7 208 * not operate at the maximum frequency (refer to the datasheets for more details).
<> 144:ef7eb2e8f9f7 209 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 210 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode,
<> 144:ef7eb2e8f9f7 211 * System frequency up to 32 MHz.
<> 144:ef7eb2e8f9f7 212 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode,
<> 144:ef7eb2e8f9f7 213 * System frequency up to 16 MHz.
<> 144:ef7eb2e8f9f7 214 * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode,
<> 144:ef7eb2e8f9f7 215 * System frequency up to 4.2 MHz
<> 144:ef7eb2e8f9f7 216 * @retval None
<> 144:ef7eb2e8f9f7 217 */
<> 144:ef7eb2e8f9f7 218 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)))
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 /** @brief Check PWR flag is set or not.
<> 144:ef7eb2e8f9f7 221 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 222 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 223 * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
<> 144:ef7eb2e8f9f7 224 * was received from the WKUP pin or from the RTC alarm (Alarm B),
<> 144:ef7eb2e8f9f7 225 * RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
<> 144:ef7eb2e8f9f7 226 * An additional wakeup event is detected if the WKUP pin is enabled
<> 144:ef7eb2e8f9f7 227 * (by setting the EWUP bit) when the WKUP pin level is already high.
<> 144:ef7eb2e8f9f7 228 * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
<> 144:ef7eb2e8f9f7 229 * resumed from StandBy mode.
<> 144:ef7eb2e8f9f7 230 * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
<> 144:ef7eb2e8f9f7 231 * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode.
<> 144:ef7eb2e8f9f7 232 * For this reason, this bit is equal to 0 after Standby or reset
<> 144:ef7eb2e8f9f7 233 * until the PVDE bit is set.
<> 144:ef7eb2e8f9f7 234 * @arg PWR_FLAG_VREFINTRDY: Internal voltage reference (VREFINT) ready flag.
<> 144:ef7eb2e8f9f7 235 * This bit indicates the state of the internal voltage reference, VREFINT.
<> 144:ef7eb2e8f9f7 236 * @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for
<> 144:ef7eb2e8f9f7 237 * the internal regulator to be ready after the voltage range is changed.
<> 144:ef7eb2e8f9f7 238 * The VOSF bit indicates that the regulator has reached the voltage level
<> 144:ef7eb2e8f9f7 239 * defined with bits VOS of PWR_CR register.
<> 144:ef7eb2e8f9f7 240 * @arg PWR_FLAG_REGLP: Regulator LP flag. When the MCU exits from Low power run
<> 144:ef7eb2e8f9f7 241 * mode, this bit stays at 1 until the regulator is ready in main mode.
<> 144:ef7eb2e8f9f7 242 * A polling on this bit is recommended to wait for the regulator main mode.
<> 144:ef7eb2e8f9f7 243 * This bit is reset by hardware when the regulator is ready.
<> 144:ef7eb2e8f9f7 244 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 245 */
<> 144:ef7eb2e8f9f7 246 #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /** @brief Clear the PWR pending flags.
<> 144:ef7eb2e8f9f7 249 * @param __FLAG__: specifies the flag to clear.
<> 144:ef7eb2e8f9f7 250 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 251 * @arg PWR_FLAG_WU: Wake Up flag
<> 144:ef7eb2e8f9f7 252 * @arg PWR_FLAG_SB: StandBy flag
<> 144:ef7eb2e8f9f7 253 */
<> 144:ef7eb2e8f9f7 254 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, (__FLAG__) << 2)
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /**
<> 144:ef7eb2e8f9f7 257 * @brief Enable interrupt on PVD Exti Line 16.
<> 144:ef7eb2e8f9f7 258 * @retval None.
<> 144:ef7eb2e8f9f7 259 */
<> 144:ef7eb2e8f9f7 260 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /**
<> 144:ef7eb2e8f9f7 263 * @brief Disable interrupt on PVD Exti Line 16.
<> 144:ef7eb2e8f9f7 264 * @retval None.
<> 144:ef7eb2e8f9f7 265 */
<> 144:ef7eb2e8f9f7 266 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 /**
<> 144:ef7eb2e8f9f7 269 * @brief Enable event on PVD Exti Line 16.
<> 144:ef7eb2e8f9f7 270 * @retval None.
<> 144:ef7eb2e8f9f7 271 */
<> 144:ef7eb2e8f9f7 272 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /**
<> 144:ef7eb2e8f9f7 275 * @brief Disable event on PVD Exti Line 16.
<> 144:ef7eb2e8f9f7 276 * @retval None.
<> 144:ef7eb2e8f9f7 277 */
<> 144:ef7eb2e8f9f7 278 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 /**
<> 144:ef7eb2e8f9f7 282 * @brief PVD EXTI line configuration: set falling edge trigger.
<> 144:ef7eb2e8f9f7 283 * @retval None.
<> 144:ef7eb2e8f9f7 284 */
<> 144:ef7eb2e8f9f7 285 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /**
<> 144:ef7eb2e8f9f7 289 * @brief Disable the PVD Extended Interrupt Falling Trigger.
<> 144:ef7eb2e8f9f7 290 * @retval None.
<> 144:ef7eb2e8f9f7 291 */
<> 144:ef7eb2e8f9f7 292 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 /**
<> 144:ef7eb2e8f9f7 296 * @brief PVD EXTI line configuration: set rising edge trigger.
<> 144:ef7eb2e8f9f7 297 * @retval None.
<> 144:ef7eb2e8f9f7 298 */
<> 144:ef7eb2e8f9f7 299 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 /**
<> 144:ef7eb2e8f9f7 302 * @brief Disable the PVD Extended Interrupt Rising Trigger.
<> 144:ef7eb2e8f9f7 303 * This parameter can be:
<> 144:ef7eb2e8f9f7 304 * @retval None.
<> 144:ef7eb2e8f9f7 305 */
<> 144:ef7eb2e8f9f7 306 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /**
<> 144:ef7eb2e8f9f7 309 * @brief PVD EXTI line configuration: set rising & falling edge trigger.
<> 144:ef7eb2e8f9f7 310 * @retval None.
<> 144:ef7eb2e8f9f7 311 */
<> 144:ef7eb2e8f9f7 312 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); } while(0);
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /**
<> 144:ef7eb2e8f9f7 315 * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
<> 144:ef7eb2e8f9f7 316 * This parameter can be:
<> 144:ef7eb2e8f9f7 317 * @retval None.
<> 144:ef7eb2e8f9f7 318 */
<> 144:ef7eb2e8f9f7 319 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0);
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 /**
<> 144:ef7eb2e8f9f7 324 * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
<> 144:ef7eb2e8f9f7 325 * @retval EXTI PVD Line Status.
<> 144:ef7eb2e8f9f7 326 */
<> 144:ef7eb2e8f9f7 327 #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /**
<> 144:ef7eb2e8f9f7 330 * @brief Clear the PVD EXTI flag.
<> 144:ef7eb2e8f9f7 331 * @retval None.
<> 144:ef7eb2e8f9f7 332 */
<> 144:ef7eb2e8f9f7 333 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 /**
<> 144:ef7eb2e8f9f7 336 * @brief Generate a Software interrupt on selected EXTI line.
<> 144:ef7eb2e8f9f7 337 * @retval None.
<> 144:ef7eb2e8f9f7 338 */
<> 144:ef7eb2e8f9f7 339 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 /**
<> 144:ef7eb2e8f9f7 342 * @brief Generate a Software interrupt on selected EXTI line.
<> 144:ef7eb2e8f9f7 343 * @retval None.
<> 144:ef7eb2e8f9f7 344 */
<> 144:ef7eb2e8f9f7 345 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 /**
<> 144:ef7eb2e8f9f7 348 * @}
<> 144:ef7eb2e8f9f7 349 */
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 /** @addtogroup PWR_Private
<> 144:ef7eb2e8f9f7 352 * @{
<> 144:ef7eb2e8f9f7 353 */
<> 144:ef7eb2e8f9f7 354 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
<> 144:ef7eb2e8f9f7 355 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
<> 144:ef7eb2e8f9f7 356 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
<> 144:ef7eb2e8f9f7 357 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
<> 144:ef7eb2e8f9f7 360 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
<> 144:ef7eb2e8f9f7 361 ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
<> 144:ef7eb2e8f9f7 362 ((MODE) == PWR_PVD_MODE_NORMAL))
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
<> 144:ef7eb2e8f9f7 365 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
<> 144:ef7eb2e8f9f7 366 ((PIN) == PWR_WAKEUP_PIN2) || \
<> 144:ef7eb2e8f9f7 367 ((PIN) == PWR_WAKEUP_PIN3))
<> 144:ef7eb2e8f9f7 368 #elif defined (STM32L051xx) || defined (STM32L052xx) || defined (STM32L053xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx)
<> 144:ef7eb2e8f9f7 369 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
<> 144:ef7eb2e8f9f7 370 ((PIN) == PWR_WAKEUP_PIN2))
<> 144:ef7eb2e8f9f7 371 #elif defined (STM32L031xx) || defined (STM32L041xx)
<> 144:ef7eb2e8f9f7 372 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
<> 144:ef7eb2e8f9f7 373 ((PIN) == PWR_WAKEUP_PIN2))
<> 144:ef7eb2e8f9f7 374 #elif defined (STM32L011xx) || defined (STM32L021xx)
<> 144:ef7eb2e8f9f7 375 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
<> 144:ef7eb2e8f9f7 376 ((PIN) == PWR_WAKEUP_PIN3))
<> 144:ef7eb2e8f9f7 377 #endif
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
<> 144:ef7eb2e8f9f7 380 ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
<> 144:ef7eb2e8f9f7 381 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 /**
<> 144:ef7eb2e8f9f7 386 * @}
<> 144:ef7eb2e8f9f7 387 */
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 /* Include PWR HAL Extension module */
<> 144:ef7eb2e8f9f7 390 #include "stm32l0xx_hal_pwr_ex.h"
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 /** @defgroup PWR_Exported_Functions PWR Exported Functions
<> 144:ef7eb2e8f9f7 393 * @{
<> 144:ef7eb2e8f9f7 394 */
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 397 * @{
<> 144:ef7eb2e8f9f7 398 */
<> 144:ef7eb2e8f9f7 399 void HAL_PWR_DeInit(void);
<> 144:ef7eb2e8f9f7 400 void HAL_PWR_EnableBkUpAccess(void);
<> 144:ef7eb2e8f9f7 401 void HAL_PWR_DisableBkUpAccess(void);
<> 144:ef7eb2e8f9f7 402 /**
<> 144:ef7eb2e8f9f7 403 * @}
<> 144:ef7eb2e8f9f7 404 */
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 /** @defgroup PWR_Exported_Functions_Group2 Low Power modes configuration functions
<> 144:ef7eb2e8f9f7 407 * @{
<> 144:ef7eb2e8f9f7 408 */
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 /* PVD control functions ************************************************/
<> 144:ef7eb2e8f9f7 411 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
<> 144:ef7eb2e8f9f7 412 void HAL_PWR_EnablePVD(void);
<> 144:ef7eb2e8f9f7 413 void HAL_PWR_DisablePVD(void);
<> 144:ef7eb2e8f9f7 414 void HAL_PWR_PVD_IRQHandler(void);
<> 144:ef7eb2e8f9f7 415 void HAL_PWR_PVDCallback(void);
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 /* WakeUp pins configuration functions ****************************************/
<> 144:ef7eb2e8f9f7 418 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
<> 144:ef7eb2e8f9f7 419 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 /* Low Power modes configuration functions ************************************/
<> 144:ef7eb2e8f9f7 422 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
<> 144:ef7eb2e8f9f7 423 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
<> 144:ef7eb2e8f9f7 424 void HAL_PWR_EnterSTANDBYMode(void);
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 void HAL_PWR_EnableSleepOnExit(void);
<> 144:ef7eb2e8f9f7 427 void HAL_PWR_DisableSleepOnExit(void);
<> 144:ef7eb2e8f9f7 428 void HAL_PWR_EnableSEVOnPend(void);
<> 144:ef7eb2e8f9f7 429 void HAL_PWR_DisableSEVOnPend(void);
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 /**
<> 144:ef7eb2e8f9f7 432 * @}
<> 144:ef7eb2e8f9f7 433 */
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 /**
<> 144:ef7eb2e8f9f7 436 * @}
<> 144:ef7eb2e8f9f7 437 */
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 /* Define the private group ***********************************/
<> 144:ef7eb2e8f9f7 440 /**************************************************************/
<> 144:ef7eb2e8f9f7 441 /** @defgroup PWR_Private PWR Private
<> 144:ef7eb2e8f9f7 442 * @{
<> 144:ef7eb2e8f9f7 443 */
<> 144:ef7eb2e8f9f7 444 /**
<> 144:ef7eb2e8f9f7 445 * @}
<> 144:ef7eb2e8f9f7 446 */
<> 144:ef7eb2e8f9f7 447 /**************************************************************/
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 /**
<> 144:ef7eb2e8f9f7 450 * @}
<> 144:ef7eb2e8f9f7 451 */
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /**
<> 144:ef7eb2e8f9f7 454 * @}
<> 144:ef7eb2e8f9f7 455 */
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 458 }
<> 144:ef7eb2e8f9f7 459 #endif
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 #endif /* __STM32L0xx_HAL_PWR_H */
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 465