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targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_can.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
19:112740acecfa 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f4xx_hal_can.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.5.0
<> 144:ef7eb2e8f9f7 6 * @date 06-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 8 * functionalities of the Controller Area Network (CAN) peripheral:
<> 144:ef7eb2e8f9f7 9 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 10 * + IO operation functions
<> 144:ef7eb2e8f9f7 11 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral State and Error functions
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 @verbatim
<> 144:ef7eb2e8f9f7 15 ==============================================================================
<> 144:ef7eb2e8f9f7 16 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 17 ==============================================================================
<> 144:ef7eb2e8f9f7 18 [..]
<> 144:ef7eb2e8f9f7 19 (#) Enable the CAN controller interface clock using
<> 144:ef7eb2e8f9f7 20 __HAL_RCC_CAN1_CLK_ENABLE() for CAN1 and __HAL_RCC_CAN2_CLK_ENABLE() for CAN2
<> 144:ef7eb2e8f9f7 21 -@- In case you are using CAN2 only, you have to enable the CAN1 clock.
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 (#) CAN pins configuration
<> 144:ef7eb2e8f9f7 24 (++) Enable the clock for the CAN GPIOs using the following function:
<> 144:ef7eb2e8f9f7 25 __GPIOx_CLK_ENABLE()
<> 144:ef7eb2e8f9f7 26 (++) Connect and configure the involved CAN pins to AF9 using the
<> 144:ef7eb2e8f9f7 27 following function HAL_GPIO_Init()
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 (#) Initialize and configure the CAN using CAN_Init() function.
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 (#) Receive a CAN frame using HAL_CAN_Receive() function.
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 36 =================================
<> 144:ef7eb2e8f9f7 37 [..]
<> 144:ef7eb2e8f9f7 38 (+) Start the CAN peripheral transmission and wait the end of this operation
<> 144:ef7eb2e8f9f7 39 using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
<> 144:ef7eb2e8f9f7 40 according to his end application
<> 144:ef7eb2e8f9f7 41 (+) Start the CAN peripheral reception and wait the end of this operation
<> 144:ef7eb2e8f9f7 42 using HAL_CAN_Receive(), at this stage user can specify the value of timeout
<> 144:ef7eb2e8f9f7 43 according to his end application
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 46 ===================================
<> 144:ef7eb2e8f9f7 47 [..]
<> 144:ef7eb2e8f9f7 48 (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
<> 144:ef7eb2e8f9f7 49 (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
<> 144:ef7eb2e8f9f7 50 (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
<> 144:ef7eb2e8f9f7 51 (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 52 add his own code by customization of function pointer HAL_CAN_TxCpltCallback
<> 144:ef7eb2e8f9f7 53 (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 54 add his own code by customization of function pointer HAL_CAN_ErrorCallback
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 *** CAN HAL driver macros list ***
<> 144:ef7eb2e8f9f7 57 =============================================
<> 144:ef7eb2e8f9f7 58 [..]
<> 144:ef7eb2e8f9f7 59 Below the list of most used macros in CAN HAL driver.
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
<> 144:ef7eb2e8f9f7 62 (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
<> 144:ef7eb2e8f9f7 63 (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
<> 144:ef7eb2e8f9f7 64 (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
<> 144:ef7eb2e8f9f7 65 (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 [..]
<> 144:ef7eb2e8f9f7 68 (@) You can refer to the CAN HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 @endverbatim
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 ******************************************************************************
<> 144:ef7eb2e8f9f7 73 * @attention
<> 144:ef7eb2e8f9f7 74 *
<> 144:ef7eb2e8f9f7 75 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 76 *
<> 144:ef7eb2e8f9f7 77 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 78 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 79 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 80 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 81 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 82 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 83 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 84 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 85 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 86 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 87 *
<> 144:ef7eb2e8f9f7 88 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 89 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 90 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 91 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 92 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 93 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 94 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 95 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 96 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 97 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 98 *
<> 144:ef7eb2e8f9f7 99 ******************************************************************************
<> 144:ef7eb2e8f9f7 100 */
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 103 #include "stm32f4xx_hal.h"
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /** @addtogroup STM32F4xx_HAL_Driver
<> 144:ef7eb2e8f9f7 106 * @{
<> 144:ef7eb2e8f9f7 107 */
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 /** @defgroup CAN CAN
<> 144:ef7eb2e8f9f7 110 * @brief CAN driver modules
<> 144:ef7eb2e8f9f7 111 * @{
<> 144:ef7eb2e8f9f7 112 */
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 #ifdef HAL_CAN_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
<> 144:ef7eb2e8f9f7 117 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
<> 144:ef7eb2e8f9f7 118 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
<> 144:ef7eb2e8f9f7 119 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 122 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 123 /** @addtogroup CAN_Private_Constants
<> 144:ef7eb2e8f9f7 124 * @{
<> 144:ef7eb2e8f9f7 125 */
<> 144:ef7eb2e8f9f7 126 #define CAN_TIMEOUT_VALUE 10U
<> 144:ef7eb2e8f9f7 127 /**
<> 144:ef7eb2e8f9f7 128 * @}
<> 144:ef7eb2e8f9f7 129 */
<> 144:ef7eb2e8f9f7 130 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 131 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 132 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 133 /** @addtogroup CAN_Private_Functions
<> 144:ef7eb2e8f9f7 134 * @{
<> 144:ef7eb2e8f9f7 135 */
<> 144:ef7eb2e8f9f7 136 static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
<> 144:ef7eb2e8f9f7 137 static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
<> 144:ef7eb2e8f9f7 138 /**
<> 144:ef7eb2e8f9f7 139 * @}
<> 144:ef7eb2e8f9f7 140 */
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 143 /** @defgroup CAN_Exported_Functions CAN Exported Functions
<> 144:ef7eb2e8f9f7 144 * @{
<> 144:ef7eb2e8f9f7 145 */
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 /** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 148 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 149 *
<> 144:ef7eb2e8f9f7 150 @verbatim
<> 144:ef7eb2e8f9f7 151 ==============================================================================
<> 144:ef7eb2e8f9f7 152 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 153 ==============================================================================
<> 144:ef7eb2e8f9f7 154 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 155 (+) Initialize and configure the CAN.
<> 144:ef7eb2e8f9f7 156 (+) De-initialize the CAN.
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 @endverbatim
<> 144:ef7eb2e8f9f7 159 * @{
<> 144:ef7eb2e8f9f7 160 */
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 /**
<> 144:ef7eb2e8f9f7 163 * @brief Initializes the CAN peripheral according to the specified
<> 144:ef7eb2e8f9f7 164 * parameters in the CAN_InitStruct.
<> 144:ef7eb2e8f9f7 165 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 166 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 167 * @retval HAL status
<> 144:ef7eb2e8f9f7 168 */
<> 144:ef7eb2e8f9f7 169 HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 170 {
<> 144:ef7eb2e8f9f7 171 uint32_t InitStatus = 3U;
<> 144:ef7eb2e8f9f7 172 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /* Check CAN handle */
<> 144:ef7eb2e8f9f7 175 if(hcan == NULL)
<> 144:ef7eb2e8f9f7 176 {
<> 144:ef7eb2e8f9f7 177 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 178 }
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /* Check the parameters */
<> 144:ef7eb2e8f9f7 181 assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
<> 144:ef7eb2e8f9f7 182 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
<> 144:ef7eb2e8f9f7 183 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
<> 144:ef7eb2e8f9f7 184 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
<> 144:ef7eb2e8f9f7 185 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
<> 144:ef7eb2e8f9f7 186 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
<> 144:ef7eb2e8f9f7 187 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
<> 144:ef7eb2e8f9f7 188 assert_param(IS_CAN_MODE(hcan->Init.Mode));
<> 144:ef7eb2e8f9f7 189 assert_param(IS_CAN_SJW(hcan->Init.SJW));
<> 144:ef7eb2e8f9f7 190 assert_param(IS_CAN_BS1(hcan->Init.BS1));
<> 144:ef7eb2e8f9f7 191 assert_param(IS_CAN_BS2(hcan->Init.BS2));
<> 144:ef7eb2e8f9f7 192 assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 if(hcan->State == HAL_CAN_STATE_RESET)
<> 144:ef7eb2e8f9f7 196 {
<> 144:ef7eb2e8f9f7 197 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 198 hcan->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 199 /* Init the low level hardware */
<> 144:ef7eb2e8f9f7 200 HAL_CAN_MspInit(hcan);
<> 144:ef7eb2e8f9f7 201 }
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /* Initialize the CAN state*/
<> 144:ef7eb2e8f9f7 204 hcan->State = HAL_CAN_STATE_BUSY;
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /* Exit from sleep mode */
<> 144:ef7eb2e8f9f7 207 hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 /* Request initialisation */
<> 144:ef7eb2e8f9f7 210 hcan->Instance->MCR |= CAN_MCR_INRQ ;
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /* Get tick */
<> 144:ef7eb2e8f9f7 213 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 /* Wait the acknowledge */
<> 144:ef7eb2e8f9f7 216 while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
<> 144:ef7eb2e8f9f7 217 {
<> 144:ef7eb2e8f9f7 218 if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 219 {
<> 144:ef7eb2e8f9f7 220 hcan->State= HAL_CAN_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 221 /* Process unlocked */
<> 144:ef7eb2e8f9f7 222 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 223 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 224 }
<> 144:ef7eb2e8f9f7 225 }
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /* Check acknowledge */
<> 144:ef7eb2e8f9f7 228 if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
<> 144:ef7eb2e8f9f7 229 {
<> 144:ef7eb2e8f9f7 230 InitStatus = CAN_INITSTATUS_FAILED;
<> 144:ef7eb2e8f9f7 231 }
<> 144:ef7eb2e8f9f7 232 else
<> 144:ef7eb2e8f9f7 233 {
<> 144:ef7eb2e8f9f7 234 /* Set the time triggered communication mode */
<> 144:ef7eb2e8f9f7 235 if (hcan->Init.TTCM == ENABLE)
<> 144:ef7eb2e8f9f7 236 {
<> 144:ef7eb2e8f9f7 237 hcan->Instance->MCR |= CAN_MCR_TTCM;
<> 144:ef7eb2e8f9f7 238 }
<> 144:ef7eb2e8f9f7 239 else
<> 144:ef7eb2e8f9f7 240 {
<> 144:ef7eb2e8f9f7 241 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM;
<> 144:ef7eb2e8f9f7 242 }
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /* Set the automatic bus-off management */
<> 144:ef7eb2e8f9f7 245 if (hcan->Init.ABOM == ENABLE)
<> 144:ef7eb2e8f9f7 246 {
<> 144:ef7eb2e8f9f7 247 hcan->Instance->MCR |= CAN_MCR_ABOM;
<> 144:ef7eb2e8f9f7 248 }
<> 144:ef7eb2e8f9f7 249 else
<> 144:ef7eb2e8f9f7 250 {
<> 144:ef7eb2e8f9f7 251 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM;
<> 144:ef7eb2e8f9f7 252 }
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /* Set the automatic wake-up mode */
<> 144:ef7eb2e8f9f7 255 if (hcan->Init.AWUM == ENABLE)
<> 144:ef7eb2e8f9f7 256 {
<> 144:ef7eb2e8f9f7 257 hcan->Instance->MCR |= CAN_MCR_AWUM;
<> 144:ef7eb2e8f9f7 258 }
<> 144:ef7eb2e8f9f7 259 else
<> 144:ef7eb2e8f9f7 260 {
<> 144:ef7eb2e8f9f7 261 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM;
<> 144:ef7eb2e8f9f7 262 }
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 /* Set the no automatic retransmission */
<> 144:ef7eb2e8f9f7 265 if (hcan->Init.NART == ENABLE)
<> 144:ef7eb2e8f9f7 266 {
<> 144:ef7eb2e8f9f7 267 hcan->Instance->MCR |= CAN_MCR_NART;
<> 144:ef7eb2e8f9f7 268 }
<> 144:ef7eb2e8f9f7 269 else
<> 144:ef7eb2e8f9f7 270 {
<> 144:ef7eb2e8f9f7 271 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART;
<> 144:ef7eb2e8f9f7 272 }
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /* Set the receive FIFO locked mode */
<> 144:ef7eb2e8f9f7 275 if (hcan->Init.RFLM == ENABLE)
<> 144:ef7eb2e8f9f7 276 {
<> 144:ef7eb2e8f9f7 277 hcan->Instance->MCR |= CAN_MCR_RFLM;
<> 144:ef7eb2e8f9f7 278 }
<> 144:ef7eb2e8f9f7 279 else
<> 144:ef7eb2e8f9f7 280 {
<> 144:ef7eb2e8f9f7 281 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM;
<> 144:ef7eb2e8f9f7 282 }
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /* Set the transmit FIFO priority */
<> 144:ef7eb2e8f9f7 285 if (hcan->Init.TXFP == ENABLE)
<> 144:ef7eb2e8f9f7 286 {
<> 144:ef7eb2e8f9f7 287 hcan->Instance->MCR |= CAN_MCR_TXFP;
<> 144:ef7eb2e8f9f7 288 }
<> 144:ef7eb2e8f9f7 289 else
<> 144:ef7eb2e8f9f7 290 {
<> 144:ef7eb2e8f9f7 291 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP;
<> 144:ef7eb2e8f9f7 292 }
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 /* Set the bit timing register */
<> 144:ef7eb2e8f9f7 295 hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \
<> 144:ef7eb2e8f9f7 296 ((uint32_t)hcan->Init.SJW) | \
<> 144:ef7eb2e8f9f7 297 ((uint32_t)hcan->Init.BS1) | \
<> 144:ef7eb2e8f9f7 298 ((uint32_t)hcan->Init.BS2) | \
<> 144:ef7eb2e8f9f7 299 ((uint32_t)hcan->Init.Prescaler - 1U);
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 /* Request leave initialisation */
<> 144:ef7eb2e8f9f7 302 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 /* Get tick */
<> 144:ef7eb2e8f9f7 305 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /* Wait the acknowledge */
<> 144:ef7eb2e8f9f7 308 while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
<> 144:ef7eb2e8f9f7 309 {
<> 144:ef7eb2e8f9f7 310 if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 311 {
<> 144:ef7eb2e8f9f7 312 hcan->State= HAL_CAN_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 313 /* Process unlocked */
<> 144:ef7eb2e8f9f7 314 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 315 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 316 }
<> 144:ef7eb2e8f9f7 317 }
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /* Check acknowledged */
<> 144:ef7eb2e8f9f7 320 if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
<> 144:ef7eb2e8f9f7 321 {
<> 144:ef7eb2e8f9f7 322 InitStatus = CAN_INITSTATUS_FAILED;
<> 144:ef7eb2e8f9f7 323 }
<> 144:ef7eb2e8f9f7 324 else
<> 144:ef7eb2e8f9f7 325 {
<> 144:ef7eb2e8f9f7 326 InitStatus = CAN_INITSTATUS_SUCCESS;
<> 144:ef7eb2e8f9f7 327 }
<> 144:ef7eb2e8f9f7 328 }
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 if(InitStatus == CAN_INITSTATUS_SUCCESS)
<> 144:ef7eb2e8f9f7 331 {
<> 144:ef7eb2e8f9f7 332 /* Set CAN error code to none */
<> 144:ef7eb2e8f9f7 333 hcan->ErrorCode = HAL_CAN_ERROR_NONE;
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 /* Initialize the CAN state */
<> 144:ef7eb2e8f9f7 336 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 /* Return function status */
<> 144:ef7eb2e8f9f7 339 return HAL_OK;
<> 144:ef7eb2e8f9f7 340 }
<> 144:ef7eb2e8f9f7 341 else
<> 144:ef7eb2e8f9f7 342 {
<> 144:ef7eb2e8f9f7 343 /* Initialize the CAN state */
<> 144:ef7eb2e8f9f7 344 hcan->State = HAL_CAN_STATE_ERROR;
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 /* Return function status */
<> 144:ef7eb2e8f9f7 347 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 348 }
<> 144:ef7eb2e8f9f7 349 }
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 /**
<> 144:ef7eb2e8f9f7 352 * @brief Configures the CAN reception filter according to the specified
<> 144:ef7eb2e8f9f7 353 * parameters in the CAN_FilterInitStruct.
<> 144:ef7eb2e8f9f7 354 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 355 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 356 * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that
<> 144:ef7eb2e8f9f7 357 * contains the filter configuration information.
<> 144:ef7eb2e8f9f7 358 * @retval None
<> 144:ef7eb2e8f9f7 359 */
<> 144:ef7eb2e8f9f7 360 HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
<> 144:ef7eb2e8f9f7 361 {
<> 144:ef7eb2e8f9f7 362 uint32_t filternbrbitpos = 0U;
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /* Check the parameters */
<> 144:ef7eb2e8f9f7 365 assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
<> 144:ef7eb2e8f9f7 366 assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
<> 144:ef7eb2e8f9f7 367 assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
<> 144:ef7eb2e8f9f7 368 assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
<> 144:ef7eb2e8f9f7 369 assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
<> 144:ef7eb2e8f9f7 370 assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 filternbrbitpos = ((uint32_t)1U) << sFilterConfig->FilterNumber;
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /* Initialisation mode for the filter */
<> 144:ef7eb2e8f9f7 375 CAN1->FMR |= (uint32_t)CAN_FMR_FINIT;
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 /* Select the start slave bank */
<> 144:ef7eb2e8f9f7 378 CAN1->FMR &= ~((uint32_t)CAN_FMR_CAN2SB);
<> 144:ef7eb2e8f9f7 379 CAN1->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8U);
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 /* Filter Deactivation */
<> 144:ef7eb2e8f9f7 382 CAN1->FA1R &= ~(uint32_t)filternbrbitpos;
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 /* Filter Scale */
<> 144:ef7eb2e8f9f7 385 if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
<> 144:ef7eb2e8f9f7 386 {
<> 144:ef7eb2e8f9f7 387 /* 16-bit scale for the filter */
<> 144:ef7eb2e8f9f7 388 CAN1->FS1R &= ~(uint32_t)filternbrbitpos;
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 /* First 16-bit identifier and First 16-bit mask */
<> 144:ef7eb2e8f9f7 391 /* Or First 16-bit identifier and Second 16-bit identifier */
<> 144:ef7eb2e8f9f7 392 CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
<> 144:ef7eb2e8f9f7 393 ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
<> 144:ef7eb2e8f9f7 394 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /* Second 16-bit identifier and Second 16-bit mask */
<> 144:ef7eb2e8f9f7 397 /* Or Third 16-bit identifier and Fourth 16-bit identifier */
<> 144:ef7eb2e8f9f7 398 CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
<> 144:ef7eb2e8f9f7 399 ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
<> 144:ef7eb2e8f9f7 400 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
<> 144:ef7eb2e8f9f7 401 }
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
<> 144:ef7eb2e8f9f7 404 {
<> 144:ef7eb2e8f9f7 405 /* 32-bit scale for the filter */
<> 144:ef7eb2e8f9f7 406 CAN1->FS1R |= filternbrbitpos;
<> 144:ef7eb2e8f9f7 407 /* 32-bit identifier or First 32-bit identifier */
<> 144:ef7eb2e8f9f7 408 CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
<> 144:ef7eb2e8f9f7 409 ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
<> 144:ef7eb2e8f9f7 410 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
<> 144:ef7eb2e8f9f7 411 /* 32-bit mask or Second 32-bit identifier */
<> 144:ef7eb2e8f9f7 412 CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
<> 144:ef7eb2e8f9f7 413 ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
<> 144:ef7eb2e8f9f7 414 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
<> 144:ef7eb2e8f9f7 415 }
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 /* Filter Mode */
<> 144:ef7eb2e8f9f7 418 if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
<> 144:ef7eb2e8f9f7 419 {
<> 144:ef7eb2e8f9f7 420 /*Id/Mask mode for the filter*/
<> 144:ef7eb2e8f9f7 421 CAN1->FM1R &= ~(uint32_t)filternbrbitpos;
<> 144:ef7eb2e8f9f7 422 }
<> 144:ef7eb2e8f9f7 423 else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
<> 144:ef7eb2e8f9f7 424 {
<> 144:ef7eb2e8f9f7 425 /*Identifier list mode for the filter*/
<> 144:ef7eb2e8f9f7 426 CAN1->FM1R |= (uint32_t)filternbrbitpos;
<> 144:ef7eb2e8f9f7 427 }
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /* Filter FIFO assignment */
<> 144:ef7eb2e8f9f7 430 if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
<> 144:ef7eb2e8f9f7 431 {
<> 144:ef7eb2e8f9f7 432 /* FIFO 0 assignation for the filter */
<> 144:ef7eb2e8f9f7 433 CAN1->FFA1R &= ~(uint32_t)filternbrbitpos;
<> 144:ef7eb2e8f9f7 434 }
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1)
<> 144:ef7eb2e8f9f7 437 {
<> 144:ef7eb2e8f9f7 438 /* FIFO 1 assignation for the filter */
<> 144:ef7eb2e8f9f7 439 CAN1->FFA1R |= (uint32_t)filternbrbitpos;
<> 144:ef7eb2e8f9f7 440 }
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442 /* Filter activation */
<> 144:ef7eb2e8f9f7 443 if (sFilterConfig->FilterActivation == ENABLE)
<> 144:ef7eb2e8f9f7 444 {
<> 144:ef7eb2e8f9f7 445 CAN1->FA1R |= filternbrbitpos;
<> 144:ef7eb2e8f9f7 446 }
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 /* Leave the initialisation mode for the filter */
<> 144:ef7eb2e8f9f7 449 CAN1->FMR &= ~((uint32_t)CAN_FMR_FINIT);
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 /* Return function status */
<> 144:ef7eb2e8f9f7 452 return HAL_OK;
<> 144:ef7eb2e8f9f7 453 }
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 /**
<> 144:ef7eb2e8f9f7 456 * @brief Deinitializes the CANx peripheral registers to their default reset values.
<> 144:ef7eb2e8f9f7 457 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 458 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 459 * @retval HAL status
<> 144:ef7eb2e8f9f7 460 */
<> 144:ef7eb2e8f9f7 461 HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 462 {
<> 144:ef7eb2e8f9f7 463 /* Check CAN handle */
<> 144:ef7eb2e8f9f7 464 if(hcan == NULL)
<> 144:ef7eb2e8f9f7 465 {
<> 144:ef7eb2e8f9f7 466 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 467 }
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /* Check the parameters */
<> 144:ef7eb2e8f9f7 470 assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 /* Change CAN state */
<> 144:ef7eb2e8f9f7 473 hcan->State = HAL_CAN_STATE_BUSY;
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 /* DeInit the low level hardware */
<> 144:ef7eb2e8f9f7 476 HAL_CAN_MspDeInit(hcan);
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 /* Change CAN state */
<> 144:ef7eb2e8f9f7 479 hcan->State = HAL_CAN_STATE_RESET;
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 /* Release Lock */
<> 144:ef7eb2e8f9f7 482 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 /* Return function status */
<> 144:ef7eb2e8f9f7 485 return HAL_OK;
<> 144:ef7eb2e8f9f7 486 }
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 /**
<> 144:ef7eb2e8f9f7 489 * @brief Initializes the CAN MSP.
<> 144:ef7eb2e8f9f7 490 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 491 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 492 * @retval None
<> 144:ef7eb2e8f9f7 493 */
<> 144:ef7eb2e8f9f7 494 __weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 495 {
<> 144:ef7eb2e8f9f7 496 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 497 UNUSED(hcan);
<> 144:ef7eb2e8f9f7 498 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 499 the HAL_CAN_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 500 */
<> 144:ef7eb2e8f9f7 501 }
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /**
<> 144:ef7eb2e8f9f7 504 * @brief DeInitializes the CAN MSP.
<> 144:ef7eb2e8f9f7 505 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 506 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 507 * @retval None
<> 144:ef7eb2e8f9f7 508 */
<> 144:ef7eb2e8f9f7 509 __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 510 {
<> 144:ef7eb2e8f9f7 511 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 512 UNUSED(hcan);
<> 144:ef7eb2e8f9f7 513 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 514 the HAL_CAN_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 515 */
<> 144:ef7eb2e8f9f7 516 }
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 /**
<> 144:ef7eb2e8f9f7 519 * @}
<> 144:ef7eb2e8f9f7 520 */
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 /** @defgroup CAN_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 523 * @brief IO operation functions
<> 144:ef7eb2e8f9f7 524 *
<> 144:ef7eb2e8f9f7 525 @verbatim
<> 144:ef7eb2e8f9f7 526 ==============================================================================
<> 144:ef7eb2e8f9f7 527 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 528 ==============================================================================
<> 144:ef7eb2e8f9f7 529 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 530 (+) Transmit a CAN frame message.
<> 144:ef7eb2e8f9f7 531 (+) Receive a CAN frame message.
<> 144:ef7eb2e8f9f7 532 (+) Enter CAN peripheral in sleep mode.
<> 144:ef7eb2e8f9f7 533 (+) Wake up the CAN peripheral from sleep mode.
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 @endverbatim
<> 144:ef7eb2e8f9f7 536 * @{
<> 144:ef7eb2e8f9f7 537 */
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 /**
<> 144:ef7eb2e8f9f7 540 * @brief Initiates and transmits a CAN frame message.
<> 144:ef7eb2e8f9f7 541 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 542 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 543 * @param Timeout: Specify Timeout value
<> 144:ef7eb2e8f9f7 544 * @retval HAL status
<> 144:ef7eb2e8f9f7 545 */
<> 144:ef7eb2e8f9f7 546 HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 547 {
<> 144:ef7eb2e8f9f7 548 uint32_t transmitmailbox = 5U;
<> 144:ef7eb2e8f9f7 549 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 /* Check the parameters */
<> 144:ef7eb2e8f9f7 552 assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
<> 144:ef7eb2e8f9f7 553 assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
<> 144:ef7eb2e8f9f7 554 assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
<> 144:ef7eb2e8f9f7 557 ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
<> 144:ef7eb2e8f9f7 558 ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
<> 144:ef7eb2e8f9f7 559 {
<> 144:ef7eb2e8f9f7 560 /* Process locked */
<> 144:ef7eb2e8f9f7 561 __HAL_LOCK(hcan);
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 if(hcan->State == HAL_CAN_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 564 {
<> 144:ef7eb2e8f9f7 565 /* Change CAN state */
<> 144:ef7eb2e8f9f7 566 hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 567 }
<> 144:ef7eb2e8f9f7 568 else
<> 144:ef7eb2e8f9f7 569 {
<> 144:ef7eb2e8f9f7 570 /* Change CAN state */
<> 144:ef7eb2e8f9f7 571 hcan->State = HAL_CAN_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 572 }
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 /* Select one empty transmit mailbox */
<> 144:ef7eb2e8f9f7 575 if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
<> 144:ef7eb2e8f9f7 576 {
<> 144:ef7eb2e8f9f7 577 transmitmailbox = 0U;
<> 144:ef7eb2e8f9f7 578 }
<> 144:ef7eb2e8f9f7 579 else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
<> 144:ef7eb2e8f9f7 580 {
<> 144:ef7eb2e8f9f7 581 transmitmailbox = 1U;
<> 144:ef7eb2e8f9f7 582 }
<> 144:ef7eb2e8f9f7 583 else
<> 144:ef7eb2e8f9f7 584 {
<> 144:ef7eb2e8f9f7 585 transmitmailbox = 2U;
<> 144:ef7eb2e8f9f7 586 }
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 /* Set up the Id */
<> 144:ef7eb2e8f9f7 589 hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
<> 144:ef7eb2e8f9f7 590 if (hcan->pTxMsg->IDE == CAN_ID_STD)
<> 144:ef7eb2e8f9f7 591 {
<> 144:ef7eb2e8f9f7 592 assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
<> 144:ef7eb2e8f9f7 593 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \
<> 144:ef7eb2e8f9f7 594 hcan->pTxMsg->RTR);
<> 144:ef7eb2e8f9f7 595 }
<> 144:ef7eb2e8f9f7 596 else
<> 144:ef7eb2e8f9f7 597 {
<> 144:ef7eb2e8f9f7 598 assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
<> 144:ef7eb2e8f9f7 599 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \
<> 144:ef7eb2e8f9f7 600 hcan->pTxMsg->IDE | \
<> 144:ef7eb2e8f9f7 601 hcan->pTxMsg->RTR);
<> 144:ef7eb2e8f9f7 602 }
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 /* Set up the DLC */
<> 144:ef7eb2e8f9f7 605 hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
<> 144:ef7eb2e8f9f7 606 hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
<> 144:ef7eb2e8f9f7 607 hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
<> 144:ef7eb2e8f9f7 608
<> 144:ef7eb2e8f9f7 609 /* Set up the data field */
<> 144:ef7eb2e8f9f7 610 hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) |
<> 144:ef7eb2e8f9f7 611 ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) |
<> 144:ef7eb2e8f9f7 612 ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) |
<> 144:ef7eb2e8f9f7 613 ((uint32_t)hcan->pTxMsg->Data[0U]));
<> 144:ef7eb2e8f9f7 614 hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) |
<> 144:ef7eb2e8f9f7 615 ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) |
<> 144:ef7eb2e8f9f7 616 ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) |
<> 144:ef7eb2e8f9f7 617 ((uint32_t)hcan->pTxMsg->Data[4U]));
<> 144:ef7eb2e8f9f7 618 /* Request transmission */
<> 144:ef7eb2e8f9f7 619 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 /* Get tick */
<> 144:ef7eb2e8f9f7 622 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 /* Check End of transmission flag */
<> 144:ef7eb2e8f9f7 625 while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
<> 144:ef7eb2e8f9f7 626 {
<> 144:ef7eb2e8f9f7 627 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 628 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 629 {
<> 144:ef7eb2e8f9f7 630 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 631 {
<> 144:ef7eb2e8f9f7 632 hcan->State = HAL_CAN_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 633 /* Process unlocked */
<> 144:ef7eb2e8f9f7 634 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 635 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 636 }
<> 144:ef7eb2e8f9f7 637 }
<> 144:ef7eb2e8f9f7 638 }
<> 144:ef7eb2e8f9f7 639 if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 640 {
<> 144:ef7eb2e8f9f7 641 /* Change CAN state */
<> 144:ef7eb2e8f9f7 642 hcan->State = HAL_CAN_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 643 }
<> 144:ef7eb2e8f9f7 644 else
<> 144:ef7eb2e8f9f7 645 {
<> 144:ef7eb2e8f9f7 646 /* Change CAN state */
<> 144:ef7eb2e8f9f7 647 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 648 }
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650 /* Process unlocked */
<> 144:ef7eb2e8f9f7 651 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 /* Return function status */
<> 144:ef7eb2e8f9f7 654 return HAL_OK;
<> 144:ef7eb2e8f9f7 655 }
<> 144:ef7eb2e8f9f7 656 else
<> 144:ef7eb2e8f9f7 657 {
<> 144:ef7eb2e8f9f7 658 /* Change CAN state */
<> 144:ef7eb2e8f9f7 659 hcan->State = HAL_CAN_STATE_ERROR;
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 /* Return function status */
<> 144:ef7eb2e8f9f7 662 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 663 }
<> 144:ef7eb2e8f9f7 664 }
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 /**
<> 144:ef7eb2e8f9f7 667 * @brief Initiates and transmits a CAN frame message.
<> 144:ef7eb2e8f9f7 668 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 669 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 670 * @retval HAL status
<> 144:ef7eb2e8f9f7 671 */
<> 144:ef7eb2e8f9f7 672 HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 673 {
<> 144:ef7eb2e8f9f7 674 uint32_t transmitmailbox = 5U;
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 /* Check the parameters */
<> 144:ef7eb2e8f9f7 677 assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
<> 144:ef7eb2e8f9f7 678 assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
<> 144:ef7eb2e8f9f7 679 assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
<> 144:ef7eb2e8f9f7 680
<> 144:ef7eb2e8f9f7 681 if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
<> 144:ef7eb2e8f9f7 682 ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
<> 144:ef7eb2e8f9f7 683 ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
<> 144:ef7eb2e8f9f7 684 {
<> 144:ef7eb2e8f9f7 685 /* Process Locked */
<> 144:ef7eb2e8f9f7 686 __HAL_LOCK(hcan);
<> 144:ef7eb2e8f9f7 687
<> 144:ef7eb2e8f9f7 688 /* Select one empty transmit mailbox */
<> 144:ef7eb2e8f9f7 689 if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
<> 144:ef7eb2e8f9f7 690 {
<> 144:ef7eb2e8f9f7 691 transmitmailbox = 0U;
<> 144:ef7eb2e8f9f7 692 }
<> 144:ef7eb2e8f9f7 693 else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
<> 144:ef7eb2e8f9f7 694 {
<> 144:ef7eb2e8f9f7 695 transmitmailbox = 1U;
<> 144:ef7eb2e8f9f7 696 }
<> 144:ef7eb2e8f9f7 697 else
<> 144:ef7eb2e8f9f7 698 {
<> 144:ef7eb2e8f9f7 699 transmitmailbox = 2U;
<> 144:ef7eb2e8f9f7 700 }
<> 144:ef7eb2e8f9f7 701
<> 144:ef7eb2e8f9f7 702 /* Set up the Id */
<> 144:ef7eb2e8f9f7 703 hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
<> 144:ef7eb2e8f9f7 704 if(hcan->pTxMsg->IDE == CAN_ID_STD)
<> 144:ef7eb2e8f9f7 705 {
<> 144:ef7eb2e8f9f7 706 assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
<> 144:ef7eb2e8f9f7 707 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \
<> 144:ef7eb2e8f9f7 708 hcan->pTxMsg->RTR);
<> 144:ef7eb2e8f9f7 709 }
<> 144:ef7eb2e8f9f7 710 else
<> 144:ef7eb2e8f9f7 711 {
<> 144:ef7eb2e8f9f7 712 assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
<> 144:ef7eb2e8f9f7 713 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \
<> 144:ef7eb2e8f9f7 714 hcan->pTxMsg->IDE | \
<> 144:ef7eb2e8f9f7 715 hcan->pTxMsg->RTR);
<> 144:ef7eb2e8f9f7 716 }
<> 144:ef7eb2e8f9f7 717
<> 144:ef7eb2e8f9f7 718 /* Set up the DLC */
<> 144:ef7eb2e8f9f7 719 hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
<> 144:ef7eb2e8f9f7 720 hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
<> 144:ef7eb2e8f9f7 721 hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723 /* Set up the data field */
<> 144:ef7eb2e8f9f7 724 hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) |
<> 144:ef7eb2e8f9f7 725 ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) |
<> 144:ef7eb2e8f9f7 726 ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) |
<> 144:ef7eb2e8f9f7 727 ((uint32_t)hcan->pTxMsg->Data[0U]));
<> 144:ef7eb2e8f9f7 728 hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) |
<> 144:ef7eb2e8f9f7 729 ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) |
<> 144:ef7eb2e8f9f7 730 ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) |
<> 144:ef7eb2e8f9f7 731 ((uint32_t)hcan->pTxMsg->Data[4U]));
<> 144:ef7eb2e8f9f7 732
<> 144:ef7eb2e8f9f7 733 if(hcan->State == HAL_CAN_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 734 {
<> 144:ef7eb2e8f9f7 735 /* Change CAN state */
<> 144:ef7eb2e8f9f7 736 hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 737 }
<> 144:ef7eb2e8f9f7 738 else
<> 144:ef7eb2e8f9f7 739 {
<> 144:ef7eb2e8f9f7 740 /* Change CAN state */
<> 144:ef7eb2e8f9f7 741 hcan->State = HAL_CAN_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 742 }
<> 144:ef7eb2e8f9f7 743
<> 144:ef7eb2e8f9f7 744 /* Set CAN error code to none */
<> 144:ef7eb2e8f9f7 745 hcan->ErrorCode = HAL_CAN_ERROR_NONE;
<> 144:ef7eb2e8f9f7 746
<> 144:ef7eb2e8f9f7 747 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 748 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 749
<> 144:ef7eb2e8f9f7 750 /* Enable Error warning Interrupt */
<> 144:ef7eb2e8f9f7 751 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753 /* Enable Error passive Interrupt */
<> 144:ef7eb2e8f9f7 754 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
<> 144:ef7eb2e8f9f7 755
<> 144:ef7eb2e8f9f7 756 /* Enable Bus-off Interrupt */
<> 144:ef7eb2e8f9f7 757 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
<> 144:ef7eb2e8f9f7 758
<> 144:ef7eb2e8f9f7 759 /* Enable Last error code Interrupt */
<> 144:ef7eb2e8f9f7 760 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 /* Enable Error Interrupt */
<> 144:ef7eb2e8f9f7 763 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765 /* Enable Transmit mailbox empty Interrupt */
<> 144:ef7eb2e8f9f7 766 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_TME);
<> 144:ef7eb2e8f9f7 767
<> 144:ef7eb2e8f9f7 768 /* Request transmission */
<> 144:ef7eb2e8f9f7 769 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
<> 144:ef7eb2e8f9f7 770 }
<> 144:ef7eb2e8f9f7 771 else
<> 144:ef7eb2e8f9f7 772 {
<> 144:ef7eb2e8f9f7 773 /* Change CAN state */
<> 144:ef7eb2e8f9f7 774 hcan->State = HAL_CAN_STATE_ERROR;
<> 144:ef7eb2e8f9f7 775
<> 144:ef7eb2e8f9f7 776 /* Return function status */
<> 144:ef7eb2e8f9f7 777 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 778 }
<> 144:ef7eb2e8f9f7 779
<> 144:ef7eb2e8f9f7 780 return HAL_OK;
<> 144:ef7eb2e8f9f7 781 }
<> 144:ef7eb2e8f9f7 782
<> 144:ef7eb2e8f9f7 783 /**
<> 144:ef7eb2e8f9f7 784 * @brief Receives a correct CAN frame.
<> 144:ef7eb2e8f9f7 785 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 786 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 787 * @param FIFONumber: FIFO Number value
<> 144:ef7eb2e8f9f7 788 * @param Timeout: Specify Timeout value
<> 144:ef7eb2e8f9f7 789 * @retval HAL status
<> 144:ef7eb2e8f9f7 790 */
<> 144:ef7eb2e8f9f7 791 HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 792 {
<> 144:ef7eb2e8f9f7 793 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 794
<> 144:ef7eb2e8f9f7 795 /* Check the parameters */
<> 144:ef7eb2e8f9f7 796 assert_param(IS_CAN_FIFO(FIFONumber));
<> 144:ef7eb2e8f9f7 797
<> 144:ef7eb2e8f9f7 798 /* Process locked */
<> 144:ef7eb2e8f9f7 799 __HAL_LOCK(hcan);
<> 144:ef7eb2e8f9f7 800
<> 144:ef7eb2e8f9f7 801 if(hcan->State == HAL_CAN_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 802 {
<> 144:ef7eb2e8f9f7 803 /* Change CAN state */
<> 144:ef7eb2e8f9f7 804 hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 805 }
<> 144:ef7eb2e8f9f7 806 else
<> 144:ef7eb2e8f9f7 807 {
<> 144:ef7eb2e8f9f7 808 /* Change CAN state */
<> 144:ef7eb2e8f9f7 809 hcan->State = HAL_CAN_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 810 }
<> 144:ef7eb2e8f9f7 811
<> 144:ef7eb2e8f9f7 812 /* Get tick */
<> 144:ef7eb2e8f9f7 813 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 814
<> 144:ef7eb2e8f9f7 815 /* Check pending message */
<> 144:ef7eb2e8f9f7 816 while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U)
<> 144:ef7eb2e8f9f7 817 {
<> 144:ef7eb2e8f9f7 818 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 819 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 820 {
<> 144:ef7eb2e8f9f7 821 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 822 {
<> 144:ef7eb2e8f9f7 823 hcan->State = HAL_CAN_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 824 /* Process unlocked */
<> 144:ef7eb2e8f9f7 825 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 826 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 827 }
<> 144:ef7eb2e8f9f7 828 }
<> 144:ef7eb2e8f9f7 829 }
<> 144:ef7eb2e8f9f7 830
<> 144:ef7eb2e8f9f7 831 /* Get the Id */
<> 144:ef7eb2e8f9f7 832 hcan->pRxMsg->IDE = (uint8_t)0x04U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
<> 144:ef7eb2e8f9f7 833 if (hcan->pRxMsg->IDE == CAN_ID_STD)
<> 144:ef7eb2e8f9f7 834 {
<> 144:ef7eb2e8f9f7 835 hcan->pRxMsg->StdId = (uint32_t)0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
<> 144:ef7eb2e8f9f7 836 }
<> 144:ef7eb2e8f9f7 837 else
<> 144:ef7eb2e8f9f7 838 {
<> 144:ef7eb2e8f9f7 839 hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
<> 144:ef7eb2e8f9f7 840 }
<> 144:ef7eb2e8f9f7 841
<> 144:ef7eb2e8f9f7 842 hcan->pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
<> 144:ef7eb2e8f9f7 843 /* Get the DLC */
<> 144:ef7eb2e8f9f7 844 hcan->pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
<> 144:ef7eb2e8f9f7 845 /* Get the FMI */
<> 144:ef7eb2e8f9f7 846 hcan->pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
<> 144:ef7eb2e8f9f7 847 /* Get the data field */
<> 144:ef7eb2e8f9f7 848 hcan->pRxMsg->Data[0U] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
<> 144:ef7eb2e8f9f7 849 hcan->pRxMsg->Data[1U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
<> 144:ef7eb2e8f9f7 850 hcan->pRxMsg->Data[2U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
<> 144:ef7eb2e8f9f7 851 hcan->pRxMsg->Data[3U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
<> 144:ef7eb2e8f9f7 852 hcan->pRxMsg->Data[4U] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
<> 144:ef7eb2e8f9f7 853 hcan->pRxMsg->Data[5U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
<> 144:ef7eb2e8f9f7 854 hcan->pRxMsg->Data[6U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
<> 144:ef7eb2e8f9f7 855 hcan->pRxMsg->Data[7U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
<> 144:ef7eb2e8f9f7 856
<> 144:ef7eb2e8f9f7 857 /* Release the FIFO */
<> 144:ef7eb2e8f9f7 858 if(FIFONumber == CAN_FIFO0)
<> 144:ef7eb2e8f9f7 859 {
<> 144:ef7eb2e8f9f7 860 /* Release FIFO0 */
<> 144:ef7eb2e8f9f7 861 __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
<> 144:ef7eb2e8f9f7 862 }
<> 144:ef7eb2e8f9f7 863 else /* FIFONumber == CAN_FIFO1 */
<> 144:ef7eb2e8f9f7 864 {
<> 144:ef7eb2e8f9f7 865 /* Release FIFO1 */
<> 144:ef7eb2e8f9f7 866 __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
<> 144:ef7eb2e8f9f7 867 }
<> 144:ef7eb2e8f9f7 868
<> 144:ef7eb2e8f9f7 869 if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 870 {
<> 144:ef7eb2e8f9f7 871 /* Change CAN state */
<> 144:ef7eb2e8f9f7 872 hcan->State = HAL_CAN_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 873
<> 144:ef7eb2e8f9f7 874 /* Process unlocked */
<> 144:ef7eb2e8f9f7 875 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 876 }
<> 144:ef7eb2e8f9f7 877 else
<> 144:ef7eb2e8f9f7 878 {
<> 144:ef7eb2e8f9f7 879 /* Change CAN state */
<> 144:ef7eb2e8f9f7 880 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 881
<> 144:ef7eb2e8f9f7 882 /* Process unlocked */
<> 144:ef7eb2e8f9f7 883 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 884 }
<> 144:ef7eb2e8f9f7 885
<> 144:ef7eb2e8f9f7 886 /* Return function status */
<> 144:ef7eb2e8f9f7 887 return HAL_OK;
<> 144:ef7eb2e8f9f7 888 }
<> 144:ef7eb2e8f9f7 889
<> 144:ef7eb2e8f9f7 890 /**
<> 144:ef7eb2e8f9f7 891 * @brief Receives a correct CAN frame.
<> 144:ef7eb2e8f9f7 892 * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 893 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 894 * @param FIFONumber: Specify the FIFO number
<> 144:ef7eb2e8f9f7 895 * @retval HAL status
<> 144:ef7eb2e8f9f7 896 */
<> 144:ef7eb2e8f9f7 897 HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
<> 144:ef7eb2e8f9f7 898 {
<> 144:ef7eb2e8f9f7 899 uint32_t tmp = 0U;
<> 144:ef7eb2e8f9f7 900
<> 144:ef7eb2e8f9f7 901 /* Check the parameters */
<> 144:ef7eb2e8f9f7 902 assert_param(IS_CAN_FIFO(FIFONumber));
<> 144:ef7eb2e8f9f7 903
<> 144:ef7eb2e8f9f7 904 tmp = hcan->State;
<> 144:ef7eb2e8f9f7 905 if((tmp == HAL_CAN_STATE_READY) || (tmp == HAL_CAN_STATE_BUSY_TX))
<> 144:ef7eb2e8f9f7 906 {
<> 144:ef7eb2e8f9f7 907 /* Process locked */
<> 144:ef7eb2e8f9f7 908 __HAL_LOCK(hcan);
<> 144:ef7eb2e8f9f7 909
<> 144:ef7eb2e8f9f7 910 if(hcan->State == HAL_CAN_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 911 {
<> 144:ef7eb2e8f9f7 912 /* Change CAN state */
<> 144:ef7eb2e8f9f7 913 hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 914 }
<> 144:ef7eb2e8f9f7 915 else
<> 144:ef7eb2e8f9f7 916 {
<> 144:ef7eb2e8f9f7 917 /* Change CAN state */
<> 144:ef7eb2e8f9f7 918 hcan->State = HAL_CAN_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 919 }
<> 144:ef7eb2e8f9f7 920
<> 144:ef7eb2e8f9f7 921 /* Set CAN error code to none */
<> 144:ef7eb2e8f9f7 922 hcan->ErrorCode = HAL_CAN_ERROR_NONE;
<> 144:ef7eb2e8f9f7 923
<> 144:ef7eb2e8f9f7 924 /* Enable Error warning Interrupt */
<> 144:ef7eb2e8f9f7 925 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
<> 144:ef7eb2e8f9f7 926
<> 144:ef7eb2e8f9f7 927 /* Enable Error passive Interrupt */
<> 144:ef7eb2e8f9f7 928 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
<> 144:ef7eb2e8f9f7 929
<> 144:ef7eb2e8f9f7 930 /* Enable Bus-off Interrupt */
<> 144:ef7eb2e8f9f7 931 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
<> 144:ef7eb2e8f9f7 932
<> 144:ef7eb2e8f9f7 933 /* Enable Last error code Interrupt */
<> 144:ef7eb2e8f9f7 934 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
<> 144:ef7eb2e8f9f7 935
<> 144:ef7eb2e8f9f7 936 /* Enable Error Interrupt */
<> 144:ef7eb2e8f9f7 937 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
<> 144:ef7eb2e8f9f7 938
<> 144:ef7eb2e8f9f7 939 /* Process unlocked */
<> 144:ef7eb2e8f9f7 940 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 941
<> 144:ef7eb2e8f9f7 942 if(FIFONumber == CAN_FIFO0)
<> 144:ef7eb2e8f9f7 943 {
<> 144:ef7eb2e8f9f7 944 /* Enable FIFO 0 message pending Interrupt */
<> 144:ef7eb2e8f9f7 945 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0);
<> 144:ef7eb2e8f9f7 946 }
<> 144:ef7eb2e8f9f7 947 else
<> 144:ef7eb2e8f9f7 948 {
<> 144:ef7eb2e8f9f7 949 /* Enable FIFO 1 message pending Interrupt */
<> 144:ef7eb2e8f9f7 950 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1);
<> 144:ef7eb2e8f9f7 951 }
<> 144:ef7eb2e8f9f7 952
<> 144:ef7eb2e8f9f7 953 }
<> 144:ef7eb2e8f9f7 954 else
<> 144:ef7eb2e8f9f7 955 {
<> 144:ef7eb2e8f9f7 956 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 957 }
<> 144:ef7eb2e8f9f7 958
<> 144:ef7eb2e8f9f7 959 /* Return function status */
<> 144:ef7eb2e8f9f7 960 return HAL_OK;
<> 144:ef7eb2e8f9f7 961 }
<> 144:ef7eb2e8f9f7 962
<> 144:ef7eb2e8f9f7 963 /**
<> 144:ef7eb2e8f9f7 964 * @brief Enters the Sleep (low power) mode.
<> 144:ef7eb2e8f9f7 965 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 966 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 967 * @retval HAL status.
<> 144:ef7eb2e8f9f7 968 */
<> 144:ef7eb2e8f9f7 969 HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 970 {
<> 144:ef7eb2e8f9f7 971 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 972
<> 144:ef7eb2e8f9f7 973 /* Process locked */
<> 144:ef7eb2e8f9f7 974 __HAL_LOCK(hcan);
<> 144:ef7eb2e8f9f7 975
<> 144:ef7eb2e8f9f7 976 /* Change CAN state */
<> 144:ef7eb2e8f9f7 977 hcan->State = HAL_CAN_STATE_BUSY;
<> 144:ef7eb2e8f9f7 978
<> 144:ef7eb2e8f9f7 979 /* Request Sleep mode */
<> 144:ef7eb2e8f9f7 980 hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
<> 144:ef7eb2e8f9f7 981
<> 144:ef7eb2e8f9f7 982 /* Sleep mode status */
<> 144:ef7eb2e8f9f7 983 if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
<> 144:ef7eb2e8f9f7 984 {
<> 144:ef7eb2e8f9f7 985 /* Process unlocked */
<> 144:ef7eb2e8f9f7 986 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 987
<> 144:ef7eb2e8f9f7 988 /* Return function status */
<> 144:ef7eb2e8f9f7 989 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 990 }
<> 144:ef7eb2e8f9f7 991
<> 144:ef7eb2e8f9f7 992 /* Get tick */
<> 144:ef7eb2e8f9f7 993 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 994
<> 144:ef7eb2e8f9f7 995 /* Wait the acknowledge */
<> 144:ef7eb2e8f9f7 996 while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
<> 144:ef7eb2e8f9f7 997 {
<> 144:ef7eb2e8f9f7 998 if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 999 {
<> 144:ef7eb2e8f9f7 1000 hcan->State = HAL_CAN_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1001 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1002 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 1003 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1004 }
<> 144:ef7eb2e8f9f7 1005 }
<> 144:ef7eb2e8f9f7 1006
<> 144:ef7eb2e8f9f7 1007 /* Change CAN state */
<> 144:ef7eb2e8f9f7 1008 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 1009
<> 144:ef7eb2e8f9f7 1010 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1011 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 1012
<> 144:ef7eb2e8f9f7 1013 /* Return function status */
<> 144:ef7eb2e8f9f7 1014 return HAL_OK;
<> 144:ef7eb2e8f9f7 1015 }
<> 144:ef7eb2e8f9f7 1016
<> 144:ef7eb2e8f9f7 1017 /**
<> 144:ef7eb2e8f9f7 1018 * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
<> 144:ef7eb2e8f9f7 1019 * is in the normal mode.
<> 144:ef7eb2e8f9f7 1020 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1021 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1022 * @retval HAL status.
<> 144:ef7eb2e8f9f7 1023 */
<> 144:ef7eb2e8f9f7 1024 HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1025 {
<> 144:ef7eb2e8f9f7 1026 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 1027
<> 144:ef7eb2e8f9f7 1028 /* Process locked */
<> 144:ef7eb2e8f9f7 1029 __HAL_LOCK(hcan);
<> 144:ef7eb2e8f9f7 1030
<> 144:ef7eb2e8f9f7 1031 /* Change CAN state */
<> 144:ef7eb2e8f9f7 1032 hcan->State = HAL_CAN_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1033
<> 144:ef7eb2e8f9f7 1034 /* Wake up request */
<> 144:ef7eb2e8f9f7 1035 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
<> 144:ef7eb2e8f9f7 1036
<> 144:ef7eb2e8f9f7 1037 /* Get tick */
<> 144:ef7eb2e8f9f7 1038 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1039
<> 144:ef7eb2e8f9f7 1040 /* Sleep mode status */
<> 144:ef7eb2e8f9f7 1041 while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
<> 144:ef7eb2e8f9f7 1042 {
<> 144:ef7eb2e8f9f7 1043 if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 1044 {
<> 144:ef7eb2e8f9f7 1045 hcan->State= HAL_CAN_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1046 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1047 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 1048 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1049 }
<> 144:ef7eb2e8f9f7 1050 }
<> 144:ef7eb2e8f9f7 1051 if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
<> 144:ef7eb2e8f9f7 1052 {
<> 144:ef7eb2e8f9f7 1053 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1054 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 1055
<> 144:ef7eb2e8f9f7 1056 /* Return function status */
<> 144:ef7eb2e8f9f7 1057 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1058 }
<> 144:ef7eb2e8f9f7 1059
<> 144:ef7eb2e8f9f7 1060 /* Change CAN state */
<> 144:ef7eb2e8f9f7 1061 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 1062
<> 144:ef7eb2e8f9f7 1063 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1064 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 1065
<> 144:ef7eb2e8f9f7 1066 /* Return function status */
<> 144:ef7eb2e8f9f7 1067 return HAL_OK;
<> 144:ef7eb2e8f9f7 1068 }
<> 144:ef7eb2e8f9f7 1069
<> 144:ef7eb2e8f9f7 1070 /**
<> 144:ef7eb2e8f9f7 1071 * @brief Handles CAN interrupt request
<> 144:ef7eb2e8f9f7 1072 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1073 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1074 * @retval None
<> 144:ef7eb2e8f9f7 1075 */
<> 144:ef7eb2e8f9f7 1076 void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1077 {
<> 144:ef7eb2e8f9f7 1078 uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U;
<> 144:ef7eb2e8f9f7 1079
<> 144:ef7eb2e8f9f7 1080 /* Check End of transmission flag */
<> 144:ef7eb2e8f9f7 1081 if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
<> 144:ef7eb2e8f9f7 1082 {
<> 144:ef7eb2e8f9f7 1083 tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0);
<> 144:ef7eb2e8f9f7 1084 tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1);
<> 144:ef7eb2e8f9f7 1085 tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2);
<> 144:ef7eb2e8f9f7 1086 if(tmp1 || tmp2 || tmp3)
<> 144:ef7eb2e8f9f7 1087 {
<> 144:ef7eb2e8f9f7 1088 /* Call transmit function */
<> 144:ef7eb2e8f9f7 1089 CAN_Transmit_IT(hcan);
<> 144:ef7eb2e8f9f7 1090 }
<> 144:ef7eb2e8f9f7 1091 }
<> 144:ef7eb2e8f9f7 1092
<> 144:ef7eb2e8f9f7 1093 tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0);
<> 144:ef7eb2e8f9f7 1094 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0);
<> 144:ef7eb2e8f9f7 1095 /* Check End of reception flag for FIFO0 */
<> 144:ef7eb2e8f9f7 1096 if((tmp1 != 0U) && tmp2)
<> 144:ef7eb2e8f9f7 1097 {
<> 144:ef7eb2e8f9f7 1098 /* Call receive function */
<> 144:ef7eb2e8f9f7 1099 CAN_Receive_IT(hcan, CAN_FIFO0);
<> 144:ef7eb2e8f9f7 1100 }
<> 144:ef7eb2e8f9f7 1101
<> 144:ef7eb2e8f9f7 1102 tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1);
<> 144:ef7eb2e8f9f7 1103 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1);
<> 144:ef7eb2e8f9f7 1104 /* Check End of reception flag for FIFO1 */
<> 144:ef7eb2e8f9f7 1105 if((tmp1 != 0U) && tmp2)
<> 144:ef7eb2e8f9f7 1106 {
<> 144:ef7eb2e8f9f7 1107 /* Call receive function */
<> 144:ef7eb2e8f9f7 1108 CAN_Receive_IT(hcan, CAN_FIFO1);
<> 144:ef7eb2e8f9f7 1109 }
<> 144:ef7eb2e8f9f7 1110
<> 144:ef7eb2e8f9f7 1111 tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG);
<> 144:ef7eb2e8f9f7 1112 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG);
<> 144:ef7eb2e8f9f7 1113 tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
<> 144:ef7eb2e8f9f7 1114 /* Check Error Warning Flag */
<> 144:ef7eb2e8f9f7 1115 if(tmp1 && tmp2 && tmp3)
<> 144:ef7eb2e8f9f7 1116 {
<> 144:ef7eb2e8f9f7 1117 /* Set CAN error code to EWG error */
<> 144:ef7eb2e8f9f7 1118 hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
<> 144:ef7eb2e8f9f7 1119 }
<> 144:ef7eb2e8f9f7 1120
<> 144:ef7eb2e8f9f7 1121 tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV);
<> 144:ef7eb2e8f9f7 1122 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV);
<> 144:ef7eb2e8f9f7 1123 tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
<> 144:ef7eb2e8f9f7 1124 /* Check Error Passive Flag */
<> 144:ef7eb2e8f9f7 1125 if(tmp1 && tmp2 && tmp3)
<> 144:ef7eb2e8f9f7 1126 {
<> 144:ef7eb2e8f9f7 1127 /* Set CAN error code to EPV error */
<> 144:ef7eb2e8f9f7 1128 hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
<> 144:ef7eb2e8f9f7 1129 }
<> 144:ef7eb2e8f9f7 1130
<> 144:ef7eb2e8f9f7 1131 tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF);
<> 144:ef7eb2e8f9f7 1132 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF);
<> 144:ef7eb2e8f9f7 1133 tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
<> 144:ef7eb2e8f9f7 1134 /* Check Bus-Off Flag */
<> 144:ef7eb2e8f9f7 1135 if(tmp1 && tmp2 && tmp3)
<> 144:ef7eb2e8f9f7 1136 {
<> 144:ef7eb2e8f9f7 1137 /* Set CAN error code to BOF error */
<> 144:ef7eb2e8f9f7 1138 hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
<> 144:ef7eb2e8f9f7 1139 }
<> 144:ef7eb2e8f9f7 1140
<> 144:ef7eb2e8f9f7 1141 tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC);
<> 144:ef7eb2e8f9f7 1142 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC);
<> 144:ef7eb2e8f9f7 1143 tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
<> 144:ef7eb2e8f9f7 1144 /* Check Last error code Flag */
<> 144:ef7eb2e8f9f7 1145 if((!tmp1) && tmp2 && tmp3)
<> 144:ef7eb2e8f9f7 1146 {
<> 144:ef7eb2e8f9f7 1147 tmp1 = (hcan->Instance->ESR) & CAN_ESR_LEC;
<> 144:ef7eb2e8f9f7 1148 switch(tmp1)
<> 144:ef7eb2e8f9f7 1149 {
<> 144:ef7eb2e8f9f7 1150 case(CAN_ESR_LEC_0):
<> 144:ef7eb2e8f9f7 1151 /* Set CAN error code to STF error */
<> 144:ef7eb2e8f9f7 1152 hcan->ErrorCode |= HAL_CAN_ERROR_STF;
<> 144:ef7eb2e8f9f7 1153 break;
<> 144:ef7eb2e8f9f7 1154 case(CAN_ESR_LEC_1):
<> 144:ef7eb2e8f9f7 1155 /* Set CAN error code to FOR error */
<> 144:ef7eb2e8f9f7 1156 hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
<> 144:ef7eb2e8f9f7 1157 break;
<> 144:ef7eb2e8f9f7 1158 case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
<> 144:ef7eb2e8f9f7 1159 /* Set CAN error code to ACK error */
<> 144:ef7eb2e8f9f7 1160 hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
<> 144:ef7eb2e8f9f7 1161 break;
<> 144:ef7eb2e8f9f7 1162 case(CAN_ESR_LEC_2):
<> 144:ef7eb2e8f9f7 1163 /* Set CAN error code to BR error */
<> 144:ef7eb2e8f9f7 1164 hcan->ErrorCode |= HAL_CAN_ERROR_BR;
<> 144:ef7eb2e8f9f7 1165 break;
<> 144:ef7eb2e8f9f7 1166 case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
<> 144:ef7eb2e8f9f7 1167 /* Set CAN error code to BD error */
<> 144:ef7eb2e8f9f7 1168 hcan->ErrorCode |= HAL_CAN_ERROR_BD;
<> 144:ef7eb2e8f9f7 1169 break;
<> 144:ef7eb2e8f9f7 1170 case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
<> 144:ef7eb2e8f9f7 1171 /* Set CAN error code to CRC error */
<> 144:ef7eb2e8f9f7 1172 hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
<> 144:ef7eb2e8f9f7 1173 break;
<> 144:ef7eb2e8f9f7 1174 default:
<> 144:ef7eb2e8f9f7 1175 break;
<> 144:ef7eb2e8f9f7 1176 }
<> 144:ef7eb2e8f9f7 1177
<> 144:ef7eb2e8f9f7 1178 /* Clear Last error code Flag */
<> 144:ef7eb2e8f9f7 1179 hcan->Instance->ESR &= ~(CAN_ESR_LEC);
<> 144:ef7eb2e8f9f7 1180 }
<> 144:ef7eb2e8f9f7 1181
<> 144:ef7eb2e8f9f7 1182 /* Call the Error call Back in case of Errors */
<> 144:ef7eb2e8f9f7 1183 if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
<> 144:ef7eb2e8f9f7 1184 {
<> 144:ef7eb2e8f9f7 1185 /* Clear ERRI Flag */
<> 144:ef7eb2e8f9f7 1186 hcan->Instance->MSR = CAN_MSR_ERRI;
<> 144:ef7eb2e8f9f7 1187 /* Set the CAN state ready to be able to start again the process */
<> 144:ef7eb2e8f9f7 1188 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 1189 /* Call Error callback function */
<> 144:ef7eb2e8f9f7 1190 HAL_CAN_ErrorCallback(hcan);
<> 144:ef7eb2e8f9f7 1191 }
<> 144:ef7eb2e8f9f7 1192 }
<> 144:ef7eb2e8f9f7 1193
<> 144:ef7eb2e8f9f7 1194 /**
<> 144:ef7eb2e8f9f7 1195 * @brief Transmission complete callback in non blocking mode
<> 144:ef7eb2e8f9f7 1196 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1197 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1198 * @retval None
<> 144:ef7eb2e8f9f7 1199 */
<> 144:ef7eb2e8f9f7 1200 __weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1201 {
<> 144:ef7eb2e8f9f7 1202 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1203 UNUSED(hcan);
<> 144:ef7eb2e8f9f7 1204 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1205 the HAL_CAN_TxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1206 */
<> 144:ef7eb2e8f9f7 1207 }
<> 144:ef7eb2e8f9f7 1208
<> 144:ef7eb2e8f9f7 1209 /**
<> 144:ef7eb2e8f9f7 1210 * @brief Transmission complete callback in non blocking mode
<> 144:ef7eb2e8f9f7 1211 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1212 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1213 * @retval None
<> 144:ef7eb2e8f9f7 1214 */
<> 144:ef7eb2e8f9f7 1215 __weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1216 {
<> 144:ef7eb2e8f9f7 1217 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1218 UNUSED(hcan);
<> 144:ef7eb2e8f9f7 1219 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1220 the HAL_CAN_RxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1221 */
<> 144:ef7eb2e8f9f7 1222 }
<> 144:ef7eb2e8f9f7 1223
<> 144:ef7eb2e8f9f7 1224 /**
<> 144:ef7eb2e8f9f7 1225 * @brief Error CAN callback.
<> 144:ef7eb2e8f9f7 1226 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1227 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1228 * @retval None
<> 144:ef7eb2e8f9f7 1229 */
<> 144:ef7eb2e8f9f7 1230 __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
<> 144:ef7eb2e8f9f7 1231 {
<> 144:ef7eb2e8f9f7 1232 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1233 UNUSED(hcan);
<> 144:ef7eb2e8f9f7 1234 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1235 the HAL_CAN_ErrorCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1236 */
<> 144:ef7eb2e8f9f7 1237 }
<> 144:ef7eb2e8f9f7 1238
<> 144:ef7eb2e8f9f7 1239 /**
<> 144:ef7eb2e8f9f7 1240 * @}
<> 144:ef7eb2e8f9f7 1241 */
<> 144:ef7eb2e8f9f7 1242
<> 144:ef7eb2e8f9f7 1243 /** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
<> 144:ef7eb2e8f9f7 1244 * @brief CAN Peripheral State functions
<> 144:ef7eb2e8f9f7 1245 *
<> 144:ef7eb2e8f9f7 1246 @verbatim
<> 144:ef7eb2e8f9f7 1247 ==============================================================================
<> 144:ef7eb2e8f9f7 1248 ##### Peripheral State and Error functions #####
<> 144:ef7eb2e8f9f7 1249 ==============================================================================
<> 144:ef7eb2e8f9f7 1250 [..]
<> 144:ef7eb2e8f9f7 1251 This subsection provides functions allowing to :
<> 144:ef7eb2e8f9f7 1252 (+) Check the CAN state.
<> 144:ef7eb2e8f9f7 1253 (+) Check CAN Errors detected during interrupt process
<> 144:ef7eb2e8f9f7 1254
<> 144:ef7eb2e8f9f7 1255 @endverbatim
<> 144:ef7eb2e8f9f7 1256 * @{
<> 144:ef7eb2e8f9f7 1257 */
<> 144:ef7eb2e8f9f7 1258
<> 144:ef7eb2e8f9f7 1259 /**
<> 144:ef7eb2e8f9f7 1260 * @brief return the CAN state
<> 144:ef7eb2e8f9f7 1261 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1262 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1263 * @retval HAL state
<> 144:ef7eb2e8f9f7 1264 */
<> 144:ef7eb2e8f9f7 1265 HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1266 {
<> 144:ef7eb2e8f9f7 1267 /* Return CAN state */
<> 144:ef7eb2e8f9f7 1268 return hcan->State;
<> 144:ef7eb2e8f9f7 1269 }
<> 144:ef7eb2e8f9f7 1270
<> 144:ef7eb2e8f9f7 1271 /**
<> 144:ef7eb2e8f9f7 1272 * @brief Return the CAN error code
<> 144:ef7eb2e8f9f7 1273 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1274 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1275 * @retval CAN Error Code
<> 144:ef7eb2e8f9f7 1276 */
<> 144:ef7eb2e8f9f7 1277 uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
<> 144:ef7eb2e8f9f7 1278 {
<> 144:ef7eb2e8f9f7 1279 return hcan->ErrorCode;
<> 144:ef7eb2e8f9f7 1280 }
<> 144:ef7eb2e8f9f7 1281
<> 144:ef7eb2e8f9f7 1282 /**
<> 144:ef7eb2e8f9f7 1283 * @}
<> 144:ef7eb2e8f9f7 1284 */
<> 144:ef7eb2e8f9f7 1285 /**
<> 144:ef7eb2e8f9f7 1286 * @brief Initiates and transmits a CAN frame message.
<> 144:ef7eb2e8f9f7 1287 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1288 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1289 * @retval HAL status
<> 144:ef7eb2e8f9f7 1290 */
<> 144:ef7eb2e8f9f7 1291 static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1292 {
<> 144:ef7eb2e8f9f7 1293 /* Disable Transmit mailbox empty Interrupt */
<> 144:ef7eb2e8f9f7 1294 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
<> 144:ef7eb2e8f9f7 1295
<> 144:ef7eb2e8f9f7 1296 if(hcan->State == HAL_CAN_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 1297 {
<> 144:ef7eb2e8f9f7 1298 /* Disable Error warning Interrupt */
<> 144:ef7eb2e8f9f7 1299 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);
<> 144:ef7eb2e8f9f7 1300
<> 144:ef7eb2e8f9f7 1301 /* Disable Error passive Interrupt */
<> 144:ef7eb2e8f9f7 1302 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);
<> 144:ef7eb2e8f9f7 1303
<> 144:ef7eb2e8f9f7 1304 /* Disable Bus-off Interrupt */
<> 144:ef7eb2e8f9f7 1305 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);
<> 144:ef7eb2e8f9f7 1306
<> 144:ef7eb2e8f9f7 1307 /* Disable Last error code Interrupt */
<> 144:ef7eb2e8f9f7 1308 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);
<> 144:ef7eb2e8f9f7 1309
<> 144:ef7eb2e8f9f7 1310 /* Disable Error Interrupt */
<> 144:ef7eb2e8f9f7 1311 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);
<> 144:ef7eb2e8f9f7 1312 }
<> 144:ef7eb2e8f9f7 1313
<> 144:ef7eb2e8f9f7 1314 if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 1315 {
<> 144:ef7eb2e8f9f7 1316 /* Change CAN state */
<> 144:ef7eb2e8f9f7 1317 hcan->State = HAL_CAN_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 1318 }
<> 144:ef7eb2e8f9f7 1319 else
<> 144:ef7eb2e8f9f7 1320 {
<> 144:ef7eb2e8f9f7 1321 /* Change CAN state */
<> 144:ef7eb2e8f9f7 1322 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 1323 }
<> 144:ef7eb2e8f9f7 1324
<> 144:ef7eb2e8f9f7 1325 /* Transmission complete callback */
<> 144:ef7eb2e8f9f7 1326 HAL_CAN_TxCpltCallback(hcan);
<> 144:ef7eb2e8f9f7 1327
<> 144:ef7eb2e8f9f7 1328 return HAL_OK;
<> 144:ef7eb2e8f9f7 1329 }
<> 144:ef7eb2e8f9f7 1330
<> 144:ef7eb2e8f9f7 1331 /**
<> 144:ef7eb2e8f9f7 1332 * @brief Receives a correct CAN frame.
<> 144:ef7eb2e8f9f7 1333 * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1334 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1335 * @param FIFONumber: Specify the FIFO number
<> 144:ef7eb2e8f9f7 1336 * @retval HAL status
<> 144:ef7eb2e8f9f7 1337 * @retval None
<> 144:ef7eb2e8f9f7 1338 */
<> 144:ef7eb2e8f9f7 1339 static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
<> 144:ef7eb2e8f9f7 1340 {
<> 144:ef7eb2e8f9f7 1341 /* Get the Id */
<> 144:ef7eb2e8f9f7 1342 hcan->pRxMsg->IDE = (uint8_t)0x04U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
<> 144:ef7eb2e8f9f7 1343 if (hcan->pRxMsg->IDE == CAN_ID_STD)
<> 144:ef7eb2e8f9f7 1344 {
<> 144:ef7eb2e8f9f7 1345 hcan->pRxMsg->StdId = (uint32_t)0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
<> 144:ef7eb2e8f9f7 1346 }
<> 144:ef7eb2e8f9f7 1347 else
<> 144:ef7eb2e8f9f7 1348 {
<> 144:ef7eb2e8f9f7 1349 hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
<> 144:ef7eb2e8f9f7 1350 }
<> 144:ef7eb2e8f9f7 1351
<> 144:ef7eb2e8f9f7 1352 hcan->pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
<> 144:ef7eb2e8f9f7 1353 /* Get the DLC */
<> 144:ef7eb2e8f9f7 1354 hcan->pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
<> 144:ef7eb2e8f9f7 1355 /* Get the FMI */
<> 144:ef7eb2e8f9f7 1356 hcan->pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
<> 144:ef7eb2e8f9f7 1357 /* Get the data field */
<> 144:ef7eb2e8f9f7 1358 hcan->pRxMsg->Data[0U] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
<> 144:ef7eb2e8f9f7 1359 hcan->pRxMsg->Data[1U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
<> 144:ef7eb2e8f9f7 1360 hcan->pRxMsg->Data[2U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
<> 144:ef7eb2e8f9f7 1361 hcan->pRxMsg->Data[3U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
<> 144:ef7eb2e8f9f7 1362 hcan->pRxMsg->Data[4U] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
<> 144:ef7eb2e8f9f7 1363 hcan->pRxMsg->Data[5U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
<> 144:ef7eb2e8f9f7 1364 hcan->pRxMsg->Data[6U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
<> 144:ef7eb2e8f9f7 1365 hcan->pRxMsg->Data[7U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
<> 144:ef7eb2e8f9f7 1366 /* Release the FIFO */
<> 144:ef7eb2e8f9f7 1367 /* Release FIFO0 */
<> 144:ef7eb2e8f9f7 1368 if (FIFONumber == CAN_FIFO0)
<> 144:ef7eb2e8f9f7 1369 {
<> 144:ef7eb2e8f9f7 1370 __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
<> 144:ef7eb2e8f9f7 1371
<> 144:ef7eb2e8f9f7 1372 /* Disable FIFO 0 message pending Interrupt */
<> 144:ef7eb2e8f9f7 1373 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0);
<> 144:ef7eb2e8f9f7 1374 }
<> 144:ef7eb2e8f9f7 1375 /* Release FIFO1 */
<> 144:ef7eb2e8f9f7 1376 else /* FIFONumber == CAN_FIFO1 */
<> 144:ef7eb2e8f9f7 1377 {
<> 144:ef7eb2e8f9f7 1378 __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
<> 144:ef7eb2e8f9f7 1379
<> 144:ef7eb2e8f9f7 1380 /* Disable FIFO 1 message pending Interrupt */
<> 144:ef7eb2e8f9f7 1381 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1);
<> 144:ef7eb2e8f9f7 1382 }
<> 144:ef7eb2e8f9f7 1383
<> 144:ef7eb2e8f9f7 1384 if(hcan->State == HAL_CAN_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1385 {
<> 144:ef7eb2e8f9f7 1386 /* Disable Error warning Interrupt */
<> 144:ef7eb2e8f9f7 1387 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);
<> 144:ef7eb2e8f9f7 1388
<> 144:ef7eb2e8f9f7 1389 /* Disable Error passive Interrupt */
<> 144:ef7eb2e8f9f7 1390 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);
<> 144:ef7eb2e8f9f7 1391
<> 144:ef7eb2e8f9f7 1392 /* Disable Bus-off Interrupt */
<> 144:ef7eb2e8f9f7 1393 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);
<> 144:ef7eb2e8f9f7 1394
<> 144:ef7eb2e8f9f7 1395 /* Disable Last error code Interrupt */
<> 144:ef7eb2e8f9f7 1396 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);
<> 144:ef7eb2e8f9f7 1397
<> 144:ef7eb2e8f9f7 1398 /* Disable Error Interrupt */
<> 144:ef7eb2e8f9f7 1399 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);
<> 144:ef7eb2e8f9f7 1400 }
<> 144:ef7eb2e8f9f7 1401
<> 144:ef7eb2e8f9f7 1402 if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 1403 {
<> 144:ef7eb2e8f9f7 1404 /* Disable CAN state */
<> 144:ef7eb2e8f9f7 1405 hcan->State = HAL_CAN_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 1406 }
<> 144:ef7eb2e8f9f7 1407 else
<> 144:ef7eb2e8f9f7 1408 {
<> 144:ef7eb2e8f9f7 1409 /* Change CAN state */
<> 144:ef7eb2e8f9f7 1410 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 1411 }
<> 144:ef7eb2e8f9f7 1412
<> 144:ef7eb2e8f9f7 1413 /* Receive complete callback */
<> 144:ef7eb2e8f9f7 1414 HAL_CAN_RxCpltCallback(hcan);
<> 144:ef7eb2e8f9f7 1415
<> 144:ef7eb2e8f9f7 1416 /* Return function status */
<> 144:ef7eb2e8f9f7 1417 return HAL_OK;
<> 144:ef7eb2e8f9f7 1418 }
<> 144:ef7eb2e8f9f7 1419
<> 144:ef7eb2e8f9f7 1420 /**
<> 144:ef7eb2e8f9f7 1421 * @}
<> 144:ef7eb2e8f9f7 1422 */
<> 144:ef7eb2e8f9f7 1423 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
<> 144:ef7eb2e8f9f7 1424 STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
<> 144:ef7eb2e8f9f7 1425 STM32F412Vx || STM32F412Rx || STM32F412Cx */
<> 144:ef7eb2e8f9f7 1426
<> 144:ef7eb2e8f9f7 1427 #endif /* HAL_CAN_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1428 /**
<> 144:ef7eb2e8f9f7 1429 * @}
<> 144:ef7eb2e8f9f7 1430 */
<> 144:ef7eb2e8f9f7 1431
<> 144:ef7eb2e8f9f7 1432 /**
<> 144:ef7eb2e8f9f7 1433 * @}
<> 144:ef7eb2e8f9f7 1434 */
<> 144:ef7eb2e8f9f7 1435
<> 144:ef7eb2e8f9f7 1436 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/