Paul Paterson / mbed-dev

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tim_ex.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f3xx_hal_tim_ex.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.3.0
<> 144:ef7eb2e8f9f7 6 * @date 01-July-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of TIM HAL Extended module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F3xx_HAL_TIM_EX_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F3xx_HAL_TIM_EX_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f3xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F3xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup TIMEx
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /** @defgroup TIMEx_Exported_Types TIMEx Exported Types
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /**
<> 144:ef7eb2e8f9f7 63 * @brief TIM Hall sensor Configuration Structure definition
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 typedef struct
<> 144:ef7eb2e8f9f7 67 {
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
<> 144:ef7eb2e8f9f7 70 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
<> 144:ef7eb2e8f9f7 73 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 uint32_t IC1Filter; /*!< Specifies the input capture filter.
<> 144:ef7eb2e8f9f7 76 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<> 144:ef7eb2e8f9f7 77 uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
<> 144:ef7eb2e8f9f7 78 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
<> 144:ef7eb2e8f9f7 79 } TIM_HallSensor_InitTypeDef;
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 82 /**
<> 144:ef7eb2e8f9f7 83 * @brief TIM Master configuration Structure definition
<> 144:ef7eb2e8f9f7 84 * @note STM32F373xC and STM32F378xx: timer instances provide a single TRGO
<> 144:ef7eb2e8f9f7 85 * output
<> 144:ef7eb2e8f9f7 86 */
<> 144:ef7eb2e8f9f7 87 typedef struct {
<> 144:ef7eb2e8f9f7 88 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
<> 144:ef7eb2e8f9f7 89 This parameter can be a value of @ref TIM_Master_Mode_Selection */
<> 144:ef7eb2e8f9f7 90 uint32_t MasterSlaveMode; /*!< Master/slave mode selection
<> 144:ef7eb2e8f9f7 91 This parameter can be a value of @ref TIM_Master_Slave_Mode */
<> 144:ef7eb2e8f9f7 92 }TIM_MasterConfigTypeDef;
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 /**
<> 144:ef7eb2e8f9f7 95 * @brief TIM Break and Dead time configuration Structure definition
<> 144:ef7eb2e8f9f7 96 * @note STM32F373xC and STM32F378xx: single break input with configurable polarity.
<> 144:ef7eb2e8f9f7 97 */
<> 144:ef7eb2e8f9f7 98 typedef struct
<> 144:ef7eb2e8f9f7 99 {
<> 144:ef7eb2e8f9f7 100 uint32_t OffStateRunMode; /*!< TIM off state in run mode
<> 144:ef7eb2e8f9f7 101 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
<> 144:ef7eb2e8f9f7 102 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
<> 144:ef7eb2e8f9f7 103 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
<> 144:ef7eb2e8f9f7 104 uint32_t LockLevel; /*!< TIM Lock level
<> 144:ef7eb2e8f9f7 105 This parameter can be a value of @ref TIM_Lock_level */
<> 144:ef7eb2e8f9f7 106 uint32_t DeadTime; /*!< TIM dead Time
<> 144:ef7eb2e8f9f7 107 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
<> 144:ef7eb2e8f9f7 108 uint32_t BreakState; /*!< TIM Break State
<> 144:ef7eb2e8f9f7 109 This parameter can be a value of @ref TIM_Break_Input_enable_disable */
<> 144:ef7eb2e8f9f7 110 uint32_t BreakPolarity; /*!< TIM Break input polarity
<> 144:ef7eb2e8f9f7 111 This parameter can be a value of @ref TIM_Break_Polarity */
<> 144:ef7eb2e8f9f7 112 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
<> 144:ef7eb2e8f9f7 113 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
<> 144:ef7eb2e8f9f7 114 } TIM_BreakDeadTimeConfigTypeDef;
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 119 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 120 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 121 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 122 /**
<> 144:ef7eb2e8f9f7 123 * @brief TIM Break input(s) and Dead time configuration Structure definition
<> 144:ef7eb2e8f9f7 124 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
<> 144:ef7eb2e8f9f7 125 * filter and polarity.
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127 typedef struct
<> 144:ef7eb2e8f9f7 128 {
<> 144:ef7eb2e8f9f7 129 uint32_t OffStateRunMode; /*!< TIM off state in run mode
<> 144:ef7eb2e8f9f7 130 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
<> 144:ef7eb2e8f9f7 131 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
<> 144:ef7eb2e8f9f7 132 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
<> 144:ef7eb2e8f9f7 133 uint32_t LockLevel; /*!< TIM Lock level
<> 144:ef7eb2e8f9f7 134 This parameter can be a value of @ref TIM_Lock_level */
<> 144:ef7eb2e8f9f7 135 uint32_t DeadTime; /*!< TIM dead Time
<> 144:ef7eb2e8f9f7 136 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
<> 144:ef7eb2e8f9f7 137 uint32_t BreakState; /*!< TIM Break State
<> 144:ef7eb2e8f9f7 138 This parameter can be a value of @ref TIM_Break_Input_enable_disable */
<> 144:ef7eb2e8f9f7 139 uint32_t BreakPolarity; /*!< TIM Break input polarity
<> 144:ef7eb2e8f9f7 140 This parameter can be a value of @ref TIM_Break_Polarity */
<> 144:ef7eb2e8f9f7 141 uint32_t BreakFilter; /*!< Specifies the brek input filter.
<> 144:ef7eb2e8f9f7 142 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<> 144:ef7eb2e8f9f7 143 uint32_t Break2State; /*!< TIM Break2 State
<> 144:ef7eb2e8f9f7 144 This parameter can be a value of @ref TIMEx_Break2_Input_enable_disable */
<> 144:ef7eb2e8f9f7 145 uint32_t Break2Polarity; /*!< TIM Break2 input polarity
<> 144:ef7eb2e8f9f7 146 This parameter can be a value of @ref TIMEx_Break2_Polarity */
<> 144:ef7eb2e8f9f7 147 uint32_t Break2Filter; /*!< TIM break2 input filter.
<> 144:ef7eb2e8f9f7 148 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<> 144:ef7eb2e8f9f7 149 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
<> 144:ef7eb2e8f9f7 150 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
<> 144:ef7eb2e8f9f7 151 } TIM_BreakDeadTimeConfigTypeDef;
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /**
<> 144:ef7eb2e8f9f7 154 * @brief TIM Master configuration Structure definition
<> 144:ef7eb2e8f9f7 155 * @note Advanced timers provide TRGO2 internal line which is redirected
<> 144:ef7eb2e8f9f7 156 * to the ADC
<> 144:ef7eb2e8f9f7 157 */
<> 144:ef7eb2e8f9f7 158 typedef struct {
<> 144:ef7eb2e8f9f7 159 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
<> 144:ef7eb2e8f9f7 160 This parameter can be a value of @ref TIM_Master_Mode_Selection */
<> 144:ef7eb2e8f9f7 161 uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
<> 144:ef7eb2e8f9f7 162 This parameter can be a value of @ref TIMEx_Master_Mode_Selection_2 */
<> 144:ef7eb2e8f9f7 163 uint32_t MasterSlaveMode; /*!< Master/slave mode selection
<> 144:ef7eb2e8f9f7 164 This parameter can be a value of @ref TIM_Master_Slave_Mode */
<> 144:ef7eb2e8f9f7 165 }TIM_MasterConfigTypeDef;
<> 144:ef7eb2e8f9f7 166 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 167 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 168 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 169 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 170 /**
<> 144:ef7eb2e8f9f7 171 * @}
<> 144:ef7eb2e8f9f7 172 */
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 175 /** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants
<> 144:ef7eb2e8f9f7 176 * @{
<> 144:ef7eb2e8f9f7 177 */
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 180 /** @defgroup TIMEx_Channel TIMEx Channel
<> 144:ef7eb2e8f9f7 181 * @{
<> 144:ef7eb2e8f9f7 182 */
<> 144:ef7eb2e8f9f7 183 #define TIM_CHANNEL_1 ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 184 #define TIM_CHANNEL_2 ((uint32_t)0x0004)
<> 144:ef7eb2e8f9f7 185 #define TIM_CHANNEL_3 ((uint32_t)0x0008)
<> 144:ef7eb2e8f9f7 186 #define TIM_CHANNEL_4 ((uint32_t)0x000C)
<> 144:ef7eb2e8f9f7 187 #define TIM_CHANNEL_ALL ((uint32_t)0x0018)
<> 144:ef7eb2e8f9f7 188 /**
<> 144:ef7eb2e8f9f7 189 * @}
<> 144:ef7eb2e8f9f7 190 */
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 /** @defgroup TIMEx_Output_Compare_and_PWM_modes TIMEx Output Compare and PWM Modes
<> 144:ef7eb2e8f9f7 193 * @{
<> 144:ef7eb2e8f9f7 194 */
<> 144:ef7eb2e8f9f7 195 #define TIM_OCMODE_TIMING ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 196 #define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
<> 144:ef7eb2e8f9f7 197 #define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
<> 144:ef7eb2e8f9f7 198 #define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
<> 144:ef7eb2e8f9f7 199 #define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
<> 144:ef7eb2e8f9f7 200 #define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M)
<> 144:ef7eb2e8f9f7 201 #define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
<> 144:ef7eb2e8f9f7 202 #define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
<> 144:ef7eb2e8f9f7 203 /**
<> 144:ef7eb2e8f9f7 204 * @}
<> 144:ef7eb2e8f9f7 205 */
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /** @defgroup TIMEx_ClearInput_Source TIMEx Clear Input Source
<> 144:ef7eb2e8f9f7 208 * @{
<> 144:ef7eb2e8f9f7 209 */
<> 144:ef7eb2e8f9f7 210 #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
<> 144:ef7eb2e8f9f7 211 #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 212 /**
<> 144:ef7eb2e8f9f7 213 * @}
<> 144:ef7eb2e8f9f7 214 */
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /** @defgroup TIMEx_Slave_Mode TIMEx Slave Mode
<> 144:ef7eb2e8f9f7 217 * @{
<> 144:ef7eb2e8f9f7 218 */
<> 144:ef7eb2e8f9f7 219 #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 220 #define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
<> 144:ef7eb2e8f9f7 221 #define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
<> 144:ef7eb2e8f9f7 222 #define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
<> 144:ef7eb2e8f9f7 223 #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
<> 144:ef7eb2e8f9f7 224 /**
<> 144:ef7eb2e8f9f7 225 * @}
<> 144:ef7eb2e8f9f7 226 */
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /** @defgroup TIMEx_Event_Source TIMEx Event Source
<> 144:ef7eb2e8f9f7 229 * @{
<> 144:ef7eb2e8f9f7 230 */
<> 144:ef7eb2e8f9f7 231 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
<> 144:ef7eb2e8f9f7 232 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
<> 144:ef7eb2e8f9f7 233 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
<> 144:ef7eb2e8f9f7 234 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
<> 144:ef7eb2e8f9f7 235 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
<> 144:ef7eb2e8f9f7 236 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
<> 144:ef7eb2e8f9f7 237 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
<> 144:ef7eb2e8f9f7 238 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
<> 144:ef7eb2e8f9f7 239 /**
<> 144:ef7eb2e8f9f7 240 * @}
<> 144:ef7eb2e8f9f7 241 */
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 /** @defgroup TIMEx_DMA_Base_address TIMEx DMA BAse Address
<> 144:ef7eb2e8f9f7 244 * @{
<> 144:ef7eb2e8f9f7 245 */
<> 144:ef7eb2e8f9f7 246 #define TIM_DMABASE_CR1 (0x00000000)
<> 144:ef7eb2e8f9f7 247 #define TIM_DMABASE_CR2 (0x00000001)
<> 144:ef7eb2e8f9f7 248 #define TIM_DMABASE_SMCR (0x00000002)
<> 144:ef7eb2e8f9f7 249 #define TIM_DMABASE_DIER (0x00000003)
<> 144:ef7eb2e8f9f7 250 #define TIM_DMABASE_SR (0x00000004)
<> 144:ef7eb2e8f9f7 251 #define TIM_DMABASE_EGR (0x00000005)
<> 144:ef7eb2e8f9f7 252 #define TIM_DMABASE_CCMR1 (0x00000006)
<> 144:ef7eb2e8f9f7 253 #define TIM_DMABASE_CCMR2 (0x00000007)
<> 144:ef7eb2e8f9f7 254 #define TIM_DMABASE_CCER (0x00000008)
<> 144:ef7eb2e8f9f7 255 #define TIM_DMABASE_CNT (0x00000009)
<> 144:ef7eb2e8f9f7 256 #define TIM_DMABASE_PSC (0x0000000A)
<> 144:ef7eb2e8f9f7 257 #define TIM_DMABASE_ARR (0x0000000B)
<> 144:ef7eb2e8f9f7 258 #define TIM_DMABASE_RCR (0x0000000C)
<> 144:ef7eb2e8f9f7 259 #define TIM_DMABASE_CCR1 (0x0000000D)
<> 144:ef7eb2e8f9f7 260 #define TIM_DMABASE_CCR2 (0x0000000E)
<> 144:ef7eb2e8f9f7 261 #define TIM_DMABASE_CCR3 (0x0000000F)
<> 144:ef7eb2e8f9f7 262 #define TIM_DMABASE_CCR4 (0x00000010)
<> 144:ef7eb2e8f9f7 263 #define TIM_DMABASE_BDTR (0x00000011)
<> 144:ef7eb2e8f9f7 264 #define TIM_DMABASE_DCR (0x00000012)
<> 144:ef7eb2e8f9f7 265 #define TIM_DMABASE_OR (0x00000013)
<> 144:ef7eb2e8f9f7 266 /**
<> 144:ef7eb2e8f9f7 267 * @}
<> 144:ef7eb2e8f9f7 268 */
<> 144:ef7eb2e8f9f7 269 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 272 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 273 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 274 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 275 /** @defgroup TIMEx_Channel TIMEx Channel
<> 144:ef7eb2e8f9f7 276 * @{
<> 144:ef7eb2e8f9f7 277 */
<> 144:ef7eb2e8f9f7 278 #define TIM_CHANNEL_1 ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 279 #define TIM_CHANNEL_2 ((uint32_t)0x0004)
<> 144:ef7eb2e8f9f7 280 #define TIM_CHANNEL_3 ((uint32_t)0x0008)
<> 144:ef7eb2e8f9f7 281 #define TIM_CHANNEL_4 ((uint32_t)0x000C)
<> 144:ef7eb2e8f9f7 282 #define TIM_CHANNEL_5 ((uint32_t)0x0010)
<> 144:ef7eb2e8f9f7 283 #define TIM_CHANNEL_6 ((uint32_t)0x0014)
<> 144:ef7eb2e8f9f7 284 #define TIM_CHANNEL_ALL ((uint32_t)0x003C)
<> 144:ef7eb2e8f9f7 285 /**
<> 144:ef7eb2e8f9f7 286 * @}
<> 144:ef7eb2e8f9f7 287 */
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /** @defgroup TIMEx_Output_Compare_and_PWM_modes TIMEx Output Compare and PWM Modes
<> 144:ef7eb2e8f9f7 290 * @{
<> 144:ef7eb2e8f9f7 291 */
<> 144:ef7eb2e8f9f7 292 #define TIM_OCMODE_TIMING ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 293 #define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
<> 144:ef7eb2e8f9f7 294 #define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
<> 144:ef7eb2e8f9f7 295 #define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
<> 144:ef7eb2e8f9f7 296 #define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
<> 144:ef7eb2e8f9f7 297 #define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
<> 144:ef7eb2e8f9f7 298 #define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
<> 144:ef7eb2e8f9f7 299 #define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 #define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3)
<> 144:ef7eb2e8f9f7 302 #define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
<> 144:ef7eb2e8f9f7 303 #define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
<> 144:ef7eb2e8f9f7 304 #define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
<> 144:ef7eb2e8f9f7 305 #define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
<> 144:ef7eb2e8f9f7 306 #define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /**
<> 144:ef7eb2e8f9f7 309 * @}
<> 144:ef7eb2e8f9f7 310 */
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 /** @defgroup TIMEx_ClearInput_Source TIMEx Clear Input Source
<> 144:ef7eb2e8f9f7 313 * @{
<> 144:ef7eb2e8f9f7 314 */
<> 144:ef7eb2e8f9f7 315 #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
<> 144:ef7eb2e8f9f7 316 #define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002)
<> 144:ef7eb2e8f9f7 317 #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 318 /**
<> 144:ef7eb2e8f9f7 319 * @}
<> 144:ef7eb2e8f9f7 320 */
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 /** @defgroup TIMEx_Break2_Input_enable_disable TIMEX Break input 2 Enable
<> 144:ef7eb2e8f9f7 323 * @{
<> 144:ef7eb2e8f9f7 324 */
<> 144:ef7eb2e8f9f7 325 #define TIM_BREAK2_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 326 #define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E)
<> 144:ef7eb2e8f9f7 327 /**
<> 144:ef7eb2e8f9f7 328 * @}
<> 144:ef7eb2e8f9f7 329 */
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /** @defgroup TIMEx_Break2_Polarity TIMEx Break Input 2 Polarity
<> 144:ef7eb2e8f9f7 332 * @{
<> 144:ef7eb2e8f9f7 333 */
<> 144:ef7eb2e8f9f7 334 #define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 335 #define TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P)
<> 144:ef7eb2e8f9f7 336 /**
<> 144:ef7eb2e8f9f7 337 * @}
<> 144:ef7eb2e8f9f7 338 */
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 /** @defgroup TIMEx_Master_Mode_Selection_2 TIMEx Master Mode Selection 2 (TRGO2)
<> 144:ef7eb2e8f9f7 341 * @{
<> 144:ef7eb2e8f9f7 342 */
<> 144:ef7eb2e8f9f7 343 #define TIM_TRGO2_RESET ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 344 #define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0))
<> 144:ef7eb2e8f9f7 345 #define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1))
<> 144:ef7eb2e8f9f7 346 #define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
<> 144:ef7eb2e8f9f7 347 #define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2))
<> 144:ef7eb2e8f9f7 348 #define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
<> 144:ef7eb2e8f9f7 349 #define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))
<> 144:ef7eb2e8f9f7 350 #define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
<> 144:ef7eb2e8f9f7 351 #define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3))
<> 144:ef7eb2e8f9f7 352 #define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))
<> 144:ef7eb2e8f9f7 353 #define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))
<> 144:ef7eb2e8f9f7 354 #define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
<> 144:ef7eb2e8f9f7 355 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))
<> 144:ef7eb2e8f9f7 356 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
<> 144:ef7eb2e8f9f7 357 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))
<> 144:ef7eb2e8f9f7 358 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
<> 144:ef7eb2e8f9f7 359 /**
<> 144:ef7eb2e8f9f7 360 * @}
<> 144:ef7eb2e8f9f7 361 */
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /** @defgroup TIMEx_Slave_Mode TIMEx Slave mode
<> 144:ef7eb2e8f9f7 364 * @{
<> 144:ef7eb2e8f9f7 365 */
<> 144:ef7eb2e8f9f7 366 #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 367 #define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
<> 144:ef7eb2e8f9f7 368 #define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
<> 144:ef7eb2e8f9f7 369 #define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
<> 144:ef7eb2e8f9f7 370 #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
<> 144:ef7eb2e8f9f7 371 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3))
<> 144:ef7eb2e8f9f7 372 /**
<> 144:ef7eb2e8f9f7 373 * @}
<> 144:ef7eb2e8f9f7 374 */
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 /** @defgroup TIM_Event_Source TIMEx Event Source
<> 144:ef7eb2e8f9f7 377 * @{
<> 144:ef7eb2e8f9f7 378 */
<> 144:ef7eb2e8f9f7 379 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
<> 144:ef7eb2e8f9f7 380 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
<> 144:ef7eb2e8f9f7 381 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
<> 144:ef7eb2e8f9f7 382 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
<> 144:ef7eb2e8f9f7 383 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
<> 144:ef7eb2e8f9f7 384 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
<> 144:ef7eb2e8f9f7 385 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
<> 144:ef7eb2e8f9f7 386 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
<> 144:ef7eb2e8f9f7 387 #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */
<> 144:ef7eb2e8f9f7 388 /**
<> 144:ef7eb2e8f9f7 389 * @}
<> 144:ef7eb2e8f9f7 390 */
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 /** @defgroup TIM_DMA_Base_address TIMEx DMA Base Address
<> 144:ef7eb2e8f9f7 393 * @{
<> 144:ef7eb2e8f9f7 394 */
<> 144:ef7eb2e8f9f7 395 #define TIM_DMABASE_CR1 (0x00000000)
<> 144:ef7eb2e8f9f7 396 #define TIM_DMABASE_CR2 (0x00000001)
<> 144:ef7eb2e8f9f7 397 #define TIM_DMABASE_SMCR (0x00000002)
<> 144:ef7eb2e8f9f7 398 #define TIM_DMABASE_DIER (0x00000003)
<> 144:ef7eb2e8f9f7 399 #define TIM_DMABASE_SR (0x00000004)
<> 144:ef7eb2e8f9f7 400 #define TIM_DMABASE_EGR (0x00000005)
<> 144:ef7eb2e8f9f7 401 #define TIM_DMABASE_CCMR1 (0x00000006)
<> 144:ef7eb2e8f9f7 402 #define TIM_DMABASE_CCMR2 (0x00000007)
<> 144:ef7eb2e8f9f7 403 #define TIM_DMABASE_CCER (0x00000008)
<> 144:ef7eb2e8f9f7 404 #define TIM_DMABASE_CNT (0x00000009)
<> 144:ef7eb2e8f9f7 405 #define TIM_DMABASE_PSC (0x0000000A)
<> 144:ef7eb2e8f9f7 406 #define TIM_DMABASE_ARR (0x0000000B)
<> 144:ef7eb2e8f9f7 407 #define TIM_DMABASE_RCR (0x0000000C)
<> 144:ef7eb2e8f9f7 408 #define TIM_DMABASE_CCR1 (0x0000000D)
<> 144:ef7eb2e8f9f7 409 #define TIM_DMABASE_CCR2 (0x0000000E)
<> 144:ef7eb2e8f9f7 410 #define TIM_DMABASE_CCR3 (0x0000000F)
<> 144:ef7eb2e8f9f7 411 #define TIM_DMABASE_CCR4 (0x00000010)
<> 144:ef7eb2e8f9f7 412 #define TIM_DMABASE_BDTR (0x00000011)
<> 144:ef7eb2e8f9f7 413 #define TIM_DMABASE_DCR (0x00000012)
<> 144:ef7eb2e8f9f7 414 #define TIM_DMABASE_CCMR3 (0x00000015)
<> 144:ef7eb2e8f9f7 415 #define TIM_DMABASE_CCR5 (0x00000016)
<> 144:ef7eb2e8f9f7 416 #define TIM_DMABASE_CCR6 (0x00000017)
<> 144:ef7eb2e8f9f7 417 #define TIM_DMABASE_OR (0x00000018)
<> 144:ef7eb2e8f9f7 418 /**
<> 144:ef7eb2e8f9f7 419 * @}
<> 144:ef7eb2e8f9f7 420 */
<> 144:ef7eb2e8f9f7 421 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 422 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 423 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 424 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 #if defined(STM32F302xE) || \
<> 144:ef7eb2e8f9f7 427 defined(STM32F302xC) || \
<> 144:ef7eb2e8f9f7 428 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 429 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 430 /** @defgroup TIMEx_Remap TIMEx Remapping
<> 144:ef7eb2e8f9f7 431 * @{
<> 144:ef7eb2e8f9f7 432 */
<> 144:ef7eb2e8f9f7 433 #define TIM_TIM1_ADC1_NONE (0x00000000) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
<> 144:ef7eb2e8f9f7 434 #define TIM_TIM1_ADC1_AWD1 (0x00000001) /*!< TIM1_ETR is connected to ADC1 AWD1 */
<> 144:ef7eb2e8f9f7 435 #define TIM_TIM1_ADC1_AWD2 (0x00000002) /*!< TIM1_ETR is connected to ADC1 AWD2 */
<> 144:ef7eb2e8f9f7 436 #define TIM_TIM1_ADC1_AWD3 (0x00000003) /*!< TIM1_ETR is connected to ADC1 AWD3 */
<> 144:ef7eb2e8f9f7 437 #define TIM_TIM16_GPIO (0x00000000) /*!< TIM16 TI1 is connected to GPIO */
<> 144:ef7eb2e8f9f7 438 #define TIM_TIM16_RTC (0x00000001) /*!< TIM16 TI1 is connected to RTC_clock */
<> 144:ef7eb2e8f9f7 439 #define TIM_TIM16_HSE (0x00000002) /*!< TIM16 TI1 is connected to HSE/32 */
<> 144:ef7eb2e8f9f7 440 #define TIM_TIM16_MCO (0x00000003) /*!< TIM16 TI1 is connected to MCO */
<> 144:ef7eb2e8f9f7 441 /**
<> 144:ef7eb2e8f9f7 442 * @}
<> 144:ef7eb2e8f9f7 443 */
<> 144:ef7eb2e8f9f7 444 #endif /* STM32F302xE || */
<> 144:ef7eb2e8f9f7 445 /* STM32F302xC || */
<> 144:ef7eb2e8f9f7 446 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 447 /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 #if defined(STM32F303xC) || defined(STM32F358xx)
<> 144:ef7eb2e8f9f7 450 /** @defgroup TIMEx_Remap TIMEx Remapping 1
<> 144:ef7eb2e8f9f7 451 * @{
<> 144:ef7eb2e8f9f7 452 */
<> 144:ef7eb2e8f9f7 453 #define TIM_TIM1_ADC1_NONE (0x00000000) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
<> 144:ef7eb2e8f9f7 454 #define TIM_TIM1_ADC1_AWD1 (0x00000001) /*!< TIM1_ETR is connected to ADC1 AWD1 */
<> 144:ef7eb2e8f9f7 455 #define TIM_TIM1_ADC1_AWD2 (0x00000002) /*!< TIM1_ETR is connected to ADC1 AWD2 */
<> 144:ef7eb2e8f9f7 456 #define TIM_TIM1_ADC1_AWD3 (0x00000003) /*!< TIM1_ETR is connected to ADC1 AWD3 */
<> 144:ef7eb2e8f9f7 457 #define TIM_TIM8_ADC2_NONE (0x00000000) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
<> 144:ef7eb2e8f9f7 458 #define TIM_TIM8_ADC2_AWD1 (0x00000001) /*!< TIM8_ETR is connected to ADC2 AWD1 */
<> 144:ef7eb2e8f9f7 459 #define TIM_TIM8_ADC2_AWD2 (0x00000002) /*!< TIM8_ETR is connected to ADC2 AWD2 */
<> 144:ef7eb2e8f9f7 460 #define TIM_TIM8_ADC2_AWD3 (0x00000003) /*!< TIM8_ETR is connected to ADC2 AWD3 */
<> 144:ef7eb2e8f9f7 461 #define TIM_TIM16_GPIO (0x00000000) /*!< TIM16 TI1 is connected to GPIO */
<> 144:ef7eb2e8f9f7 462 #define TIM_TIM16_RTC (0x00000001) /*!< TIM16 TI1 is connected to RTC_clock */
<> 144:ef7eb2e8f9f7 463 #define TIM_TIM16_HSE (0x00000002) /*!< TIM16 TI1 is connected to HSE/32 */
<> 144:ef7eb2e8f9f7 464 #define TIM_TIM16_MCO (0x00000003) /*!< TIM16 TI1 is connected to MCO */
<> 144:ef7eb2e8f9f7 465 /**
<> 144:ef7eb2e8f9f7 466 * @}
<> 144:ef7eb2e8f9f7 467 */
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /** @defgroup TIMEx_Remap2 TIMEx Remapping 2
<> 144:ef7eb2e8f9f7 470 * @{
<> 144:ef7eb2e8f9f7 471 */
<> 144:ef7eb2e8f9f7 472 #define TIM_TIM1_ADC4_NONE (0x00000000) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
<> 144:ef7eb2e8f9f7 473 #define TIM_TIM1_ADC4_AWD1 (0x00000004) /*!< TIM1_ETR is connected to ADC4 AWD1 */
<> 144:ef7eb2e8f9f7 474 #define TIM_TIM1_ADC4_AWD2 (0x00000008) /*!< TIM1_ETR is connected to ADC4 AWD2 */
<> 144:ef7eb2e8f9f7 475 #define TIM_TIM1_ADC4_AWD3 (0x0000000C) /*!< TIM1_ETR is connected to ADC4 AWD3 */
<> 144:ef7eb2e8f9f7 476 #define TIM_TIM8_ADC3_NONE (0x00000000) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
<> 144:ef7eb2e8f9f7 477 #define TIM_TIM8_ADC3_AWD1 (0x00000004) /*!< TIM8_ETR is connected to ADC3 AWD1 */
<> 144:ef7eb2e8f9f7 478 #define TIM_TIM8_ADC3_AWD2 (0x00000008) /*!< TIM8_ETR is connected to ADC3 AWD2 */
<> 144:ef7eb2e8f9f7 479 #define TIM_TIM8_ADC3_AWD3 (0x0000000C) /*!< TIM8_ETR is connected to ADC3 AWD3 */
<> 144:ef7eb2e8f9f7 480 #define TIM_TIM16_NONE (0x00000000) /*!< Non significant value for TIM16 */
<> 144:ef7eb2e8f9f7 481 /**
<> 144:ef7eb2e8f9f7 482 * @}
<> 144:ef7eb2e8f9f7 483 */
<> 144:ef7eb2e8f9f7 484 #endif /* STM32F303xC || STM32F358xx */
<> 144:ef7eb2e8f9f7 485
<> 144:ef7eb2e8f9f7 486 #if defined(STM32F303xE) || defined(STM32F398xx)
<> 144:ef7eb2e8f9f7 487 /** @defgroup TIMEx_Remap TIMEx Remapping 1
<> 144:ef7eb2e8f9f7 488 * @{
<> 144:ef7eb2e8f9f7 489 */
<> 144:ef7eb2e8f9f7 490 #define TIM_TIM1_ADC1_NONE (0x00000000) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
<> 144:ef7eb2e8f9f7 491 #define TIM_TIM1_ADC1_AWD1 (0x00000001) /*!< TIM1_ETR is connected to ADC1 AWD1 */
<> 144:ef7eb2e8f9f7 492 #define TIM_TIM1_ADC1_AWD2 (0x00000002) /*!< TIM1_ETR is connected to ADC1 AWD2 */
<> 144:ef7eb2e8f9f7 493 #define TIM_TIM1_ADC1_AWD3 (0x00000003) /*!< TIM1_ETR is connected to ADC1 AWD3 */
<> 144:ef7eb2e8f9f7 494 #define TIM_TIM8_ADC2_NONE (0x00000000) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
<> 144:ef7eb2e8f9f7 495 #define TIM_TIM8_ADC2_AWD1 (0x00000001) /*!< TIM8_ETR is connected to ADC2 AWD1 */
<> 144:ef7eb2e8f9f7 496 #define TIM_TIM8_ADC2_AWD2 (0x00000002) /*!< TIM8_ETR is connected to ADC2 AWD2 */
<> 144:ef7eb2e8f9f7 497 #define TIM_TIM8_ADC2_AWD3 (0x00000003) /*!< TIM8_ETR is connected to ADC2 AWD3 */
<> 144:ef7eb2e8f9f7 498 #define TIM_TIM16_GPIO (0x00000000) /*!< TIM16 TI1 is connected to GPIO */
<> 144:ef7eb2e8f9f7 499 #define TIM_TIM16_RTC (0x00000001) /*!< TIM16 TI1 is connected to RTC_clock */
<> 144:ef7eb2e8f9f7 500 #define TIM_TIM16_HSE (0x00000002) /*!< TIM16 TI1 is connected to HSE/32 */
<> 144:ef7eb2e8f9f7 501 #define TIM_TIM16_MCO (0x00000003) /*!< TIM16 TI1 is connected to MCO */
<> 144:ef7eb2e8f9f7 502 #define TIM_TIM20_ADC3_NONE (0x00000000) /*!< TIM20_ETR is not connected to any AWD (analog watchdog) */
<> 144:ef7eb2e8f9f7 503 #define TIM_TIM20_ADC3_AWD1 (0x00000001) /*!< TIM20_ETR is connected to ADC3 AWD1 */
<> 144:ef7eb2e8f9f7 504 #define TIM_TIM20_ADC3_AWD2 (0x00000002) /*!< TIM20_ETR is connected to ADC3 AWD2 */
<> 144:ef7eb2e8f9f7 505 #define TIM_TIM20_ADC3_AWD3 (0x00000003) /*!< TIM20_ETR is connected to ADC3 AWD3 */
<> 144:ef7eb2e8f9f7 506 /**
<> 144:ef7eb2e8f9f7 507 * @}
<> 144:ef7eb2e8f9f7 508 */
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 /** @defgroup TIMEx_Remap2 TIMEx Remapping 2
<> 144:ef7eb2e8f9f7 511 * @{
<> 144:ef7eb2e8f9f7 512 */
<> 144:ef7eb2e8f9f7 513 #define TIM_TIM1_ADC4_NONE (0x00000000) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
<> 144:ef7eb2e8f9f7 514 #define TIM_TIM1_ADC4_AWD1 (0x00000004) /*!< TIM1_ETR is connected to ADC4 AWD1 */
<> 144:ef7eb2e8f9f7 515 #define TIM_TIM1_ADC4_AWD2 (0x00000008) /*!< TIM1_ETR is connected to ADC4 AWD2 */
<> 144:ef7eb2e8f9f7 516 #define TIM_TIM1_ADC4_AWD3 (0x0000000C) /*!< TIM1_ETR is connected to ADC4 AWD3 */
<> 144:ef7eb2e8f9f7 517 #define TIM_TIM8_ADC3_NONE (0x00000000) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
<> 144:ef7eb2e8f9f7 518 #define TIM_TIM8_ADC3_AWD1 (0x00000004) /*!< TIM8_ETR is connected to ADC3 AWD1 */
<> 144:ef7eb2e8f9f7 519 #define TIM_TIM8_ADC3_AWD2 (0x00000008) /*!< TIM8_ETR is connected to ADC3 AWD2 */
<> 144:ef7eb2e8f9f7 520 #define TIM_TIM8_ADC3_AWD3 (0x0000000C) /*!< TIM8_ETR is connected to ADC3 AWD3 */
<> 144:ef7eb2e8f9f7 521 #define TIM_TIM16_NONE (0x00000000) /*!< Non significant value for TIM16 */
<> 144:ef7eb2e8f9f7 522 #define TIM_TIM20_ADC4_NONE (0x00000000) /*!< TIM20_ETR is not connected to any AWD (analog watchdog) */
<> 144:ef7eb2e8f9f7 523 #define TIM_TIM20_ADC4_AWD1 (0x00000004) /*!< TIM20_ETR is connected to ADC4 AWD1 */
<> 144:ef7eb2e8f9f7 524 #define TIM_TIM20_ADC4_AWD2 (0x00000008) /*!< TIM20_ETR is connected to ADC4 AWD2 */
<> 144:ef7eb2e8f9f7 525 #define TIM_TIM20_ADC4_AWD3 (0x0000000C) /*!< TIM20_ETR is connected to ADC4 AWD3 */
<> 144:ef7eb2e8f9f7 526 /**
<> 144:ef7eb2e8f9f7 527 * @}
<> 144:ef7eb2e8f9f7 528 */
<> 144:ef7eb2e8f9f7 529 #endif /* STM32F303xE || STM32F398xx */
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 533 /** @defgroup TIMEx_Remap TIMEx remapping
<> 144:ef7eb2e8f9f7 534 * @{
<> 144:ef7eb2e8f9f7 535 */
<> 144:ef7eb2e8f9f7 536 #define TIM_TIM2_TIM8_TRGO (0x00000000) /*!< TIM8 TRGOUT is connected to TIM2_ITR1 */
<> 144:ef7eb2e8f9f7 537 #define TIM_TIM2_ETH_PTP (0x00000400) /*!< PTP trigger output is connected to TIM2_ITR1 */
<> 144:ef7eb2e8f9f7 538 #define TIM_TIM2_USBFS_SOF (0x00000800) /*!< OTG FS SOF is connected to the TIM2_ITR1 input */
<> 144:ef7eb2e8f9f7 539 #define TIM_TIM2_USBHS_SOF (0x00000C00) /*!< OTG HS SOF is connected to the TIM2_ITR1 input */
<> 144:ef7eb2e8f9f7 540 #define TIM_TIM14_GPIO (0x00000000) /*!< TIM14 TI1 is connected to GPIO */
<> 144:ef7eb2e8f9f7 541 #define TIM_TIM14_RTC (0x00000001) /*!< TIM14 TI1 is connected to RTC_clock */
<> 144:ef7eb2e8f9f7 542 #define TIM_TIM14_HSE (0x00000002) /*!< TIM14 TI1 is connected to HSE/32 */
<> 144:ef7eb2e8f9f7 543 #define TIM_TIM14_MCO (0x00000003) /*!< TIM14 TI1 is connected to MCO */
<> 144:ef7eb2e8f9f7 544 /**
<> 144:ef7eb2e8f9f7 545 * @}
<> 144:ef7eb2e8f9f7 546 */
<> 144:ef7eb2e8f9f7 547 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 550 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 551 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 552 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 553 /** @defgroup TIMEx_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
<> 144:ef7eb2e8f9f7 554 * @{
<> 144:ef7eb2e8f9f7 555 */
<> 144:ef7eb2e8f9f7 556 #define TIM_GROUPCH5_NONE (uint32_t)0x00000000 /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
<> 144:ef7eb2e8f9f7 557 #define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
<> 144:ef7eb2e8f9f7 558 #define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
<> 144:ef7eb2e8f9f7 559 #define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
<> 144:ef7eb2e8f9f7 560 /**
<> 144:ef7eb2e8f9f7 561 * @}
<> 144:ef7eb2e8f9f7 562 */
<> 144:ef7eb2e8f9f7 563 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 564 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 565 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 566 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 /**
<> 144:ef7eb2e8f9f7 569 * @}
<> 144:ef7eb2e8f9f7 570 */
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572
<> 144:ef7eb2e8f9f7 573 /* Private Macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 574 /** @defgroup TIM_Private_Macros TIM Private Macros
<> 144:ef7eb2e8f9f7 575 * @{
<> 144:ef7eb2e8f9f7 576 */
<> 144:ef7eb2e8f9f7 577 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 578
<> 144:ef7eb2e8f9f7 579 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 580 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 581 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 582 ((CHANNEL) == TIM_CHANNEL_4) || \
<> 144:ef7eb2e8f9f7 583 ((CHANNEL) == TIM_CHANNEL_ALL))
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 586 ((CHANNEL) == TIM_CHANNEL_2))
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 589 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 590 ((CHANNEL) == TIM_CHANNEL_3))
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
<> 144:ef7eb2e8f9f7 593 ((MODE) == TIM_OCMODE_PWM2))
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
<> 144:ef7eb2e8f9f7 596 ((MODE) == TIM_OCMODE_ACTIVE) || \
<> 144:ef7eb2e8f9f7 597 ((MODE) == TIM_OCMODE_INACTIVE) || \
<> 144:ef7eb2e8f9f7 598 ((MODE) == TIM_OCMODE_TOGGLE) || \
<> 144:ef7eb2e8f9f7 599 ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
<> 144:ef7eb2e8f9f7 600 ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
<> 144:ef7eb2e8f9f7 603 ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
<> 144:ef7eb2e8f9f7 604
<> 144:ef7eb2e8f9f7 605 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
<> 144:ef7eb2e8f9f7 606 ((MODE) == TIM_SLAVEMODE_RESET) || \
<> 144:ef7eb2e8f9f7 607 ((MODE) == TIM_SLAVEMODE_GATED) || \
<> 144:ef7eb2e8f9f7 608 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
<> 144:ef7eb2e8f9f7 609 ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000) && ((SOURCE) != 0x00000000))
<> 144:ef7eb2e8f9f7 612
<> 144:ef7eb2e8f9f7 613 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
<> 144:ef7eb2e8f9f7 614 ((BASE) == TIM_DMABASE_CR2) || \
<> 144:ef7eb2e8f9f7 615 ((BASE) == TIM_DMABASE_SMCR) || \
<> 144:ef7eb2e8f9f7 616 ((BASE) == TIM_DMABASE_DIER) || \
<> 144:ef7eb2e8f9f7 617 ((BASE) == TIM_DMABASE_SR) || \
<> 144:ef7eb2e8f9f7 618 ((BASE) == TIM_DMABASE_EGR) || \
<> 144:ef7eb2e8f9f7 619 ((BASE) == TIM_DMABASE_CCMR1) || \
<> 144:ef7eb2e8f9f7 620 ((BASE) == TIM_DMABASE_CCMR2) || \
<> 144:ef7eb2e8f9f7 621 ((BASE) == TIM_DMABASE_CCER) || \
<> 144:ef7eb2e8f9f7 622 ((BASE) == TIM_DMABASE_CNT) || \
<> 144:ef7eb2e8f9f7 623 ((BASE) == TIM_DMABASE_PSC) || \
<> 144:ef7eb2e8f9f7 624 ((BASE) == TIM_DMABASE_ARR) || \
<> 144:ef7eb2e8f9f7 625 ((BASE) == TIM_DMABASE_RCR) || \
<> 144:ef7eb2e8f9f7 626 ((BASE) == TIM_DMABASE_CCR1) || \
<> 144:ef7eb2e8f9f7 627 ((BASE) == TIM_DMABASE_CCR2) || \
<> 144:ef7eb2e8f9f7 628 ((BASE) == TIM_DMABASE_CCR3) || \
<> 144:ef7eb2e8f9f7 629 ((BASE) == TIM_DMABASE_CCR4) || \
<> 144:ef7eb2e8f9f7 630 ((BASE) == TIM_DMABASE_BDTR) || \
<> 144:ef7eb2e8f9f7 631 ((BASE) == TIM_DMABASE_DCR) || \
<> 144:ef7eb2e8f9f7 632 ((BASE) == TIM_DMABASE_OR))
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637
<> 144:ef7eb2e8f9f7 638 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 639 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 640 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 641 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 644 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 645 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 646 ((CHANNEL) == TIM_CHANNEL_4) || \
<> 144:ef7eb2e8f9f7 647 ((CHANNEL) == TIM_CHANNEL_5) || \
<> 144:ef7eb2e8f9f7 648 ((CHANNEL) == TIM_CHANNEL_6) || \
<> 144:ef7eb2e8f9f7 649 ((CHANNEL) == TIM_CHANNEL_ALL))
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 652 ((CHANNEL) == TIM_CHANNEL_2))
<> 144:ef7eb2e8f9f7 653
<> 144:ef7eb2e8f9f7 654 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 655 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 656 ((CHANNEL) == TIM_CHANNEL_3))
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
<> 144:ef7eb2e8f9f7 659 ((MODE) == TIM_OCMODE_PWM2) || \
<> 144:ef7eb2e8f9f7 660 ((MODE) == TIM_OCMODE_COMBINED_PWM1) || \
<> 144:ef7eb2e8f9f7 661 ((MODE) == TIM_OCMODE_COMBINED_PWM2) || \
<> 144:ef7eb2e8f9f7 662 ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
<> 144:ef7eb2e8f9f7 663 ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM2))
<> 144:ef7eb2e8f9f7 664
<> 144:ef7eb2e8f9f7 665 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
<> 144:ef7eb2e8f9f7 666 ((MODE) == TIM_OCMODE_ACTIVE) || \
<> 144:ef7eb2e8f9f7 667 ((MODE) == TIM_OCMODE_INACTIVE) || \
<> 144:ef7eb2e8f9f7 668 ((MODE) == TIM_OCMODE_TOGGLE) || \
<> 144:ef7eb2e8f9f7 669 ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
<> 144:ef7eb2e8f9f7 670 ((MODE) == TIM_OCMODE_FORCED_INACTIVE) || \
<> 144:ef7eb2e8f9f7 671 ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
<> 144:ef7eb2e8f9f7 672 ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM2))
<> 144:ef7eb2e8f9f7 673
<> 144:ef7eb2e8f9f7 674 #define IS_TIM_CLEARINPUT_SOURCE(MODE) (((MODE) == TIM_CLEARINPUTSOURCE_ETR) || \
<> 144:ef7eb2e8f9f7 675 ((MODE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
<> 144:ef7eb2e8f9f7 676 ((MODE) == TIM_CLEARINPUTSOURCE_NONE))
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 #define IS_TIM_BREAK_FILTER(BRKFILTER) ((BRKFILTER) <= 0xF)
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680 #define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_BREAK2_ENABLE) || \
<> 144:ef7eb2e8f9f7 681 ((STATE) == TIM_BREAK2_DISABLE))
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683 #define IS_TIM_BREAK2_POLARITY(POLARITY) (((POLARITY) == TIM_BREAK2POLARITY_LOW) || \
<> 144:ef7eb2e8f9f7 684 ((POLARITY) == TIM_BREAK2POLARITY_HIGH))
<> 144:ef7eb2e8f9f7 685
<> 144:ef7eb2e8f9f7 686 #define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2_RESET) || \
<> 144:ef7eb2e8f9f7 687 ((SOURCE) == TIM_TRGO2_ENABLE) || \
<> 144:ef7eb2e8f9f7 688 ((SOURCE) == TIM_TRGO2_UPDATE) || \
<> 144:ef7eb2e8f9f7 689 ((SOURCE) == TIM_TRGO2_OC1) || \
<> 144:ef7eb2e8f9f7 690 ((SOURCE) == TIM_TRGO2_OC1REF) || \
<> 144:ef7eb2e8f9f7 691 ((SOURCE) == TIM_TRGO2_OC2REF) || \
<> 144:ef7eb2e8f9f7 692 ((SOURCE) == TIM_TRGO2_OC3REF) || \
<> 144:ef7eb2e8f9f7 693 ((SOURCE) == TIM_TRGO2_OC3REF) || \
<> 144:ef7eb2e8f9f7 694 ((SOURCE) == TIM_TRGO2_OC4REF) || \
<> 144:ef7eb2e8f9f7 695 ((SOURCE) == TIM_TRGO2_OC5REF) || \
<> 144:ef7eb2e8f9f7 696 ((SOURCE) == TIM_TRGO2_OC6REF) || \
<> 144:ef7eb2e8f9f7 697 ((SOURCE) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
<> 144:ef7eb2e8f9f7 698 ((SOURCE) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
<> 144:ef7eb2e8f9f7 699 ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \
<> 144:ef7eb2e8f9f7 700 ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
<> 144:ef7eb2e8f9f7 701 ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \
<> 144:ef7eb2e8f9f7 702 ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
<> 144:ef7eb2e8f9f7 703
<> 144:ef7eb2e8f9f7 704 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
<> 144:ef7eb2e8f9f7 705 ((MODE) == TIM_SLAVEMODE_RESET) || \
<> 144:ef7eb2e8f9f7 706 ((MODE) == TIM_SLAVEMODE_GATED) || \
<> 144:ef7eb2e8f9f7 707 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
<> 144:ef7eb2e8f9f7 708 ((MODE) == TIM_SLAVEMODE_EXTERNAL1) || \
<> 144:ef7eb2e8f9f7 709 ((MODE) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
<> 144:ef7eb2e8f9f7 710
<> 144:ef7eb2e8f9f7 711 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFE00U) == 0x00000000) && ((SOURCE) != 0x00000000))
<> 144:ef7eb2e8f9f7 712
<> 144:ef7eb2e8f9f7 713 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
<> 144:ef7eb2e8f9f7 714 ((BASE) == TIM_DMABASE_CR2) || \
<> 144:ef7eb2e8f9f7 715 ((BASE) == TIM_DMABASE_SMCR) || \
<> 144:ef7eb2e8f9f7 716 ((BASE) == TIM_DMABASE_DIER) || \
<> 144:ef7eb2e8f9f7 717 ((BASE) == TIM_DMABASE_SR) || \
<> 144:ef7eb2e8f9f7 718 ((BASE) == TIM_DMABASE_EGR) || \
<> 144:ef7eb2e8f9f7 719 ((BASE) == TIM_DMABASE_CCMR1) || \
<> 144:ef7eb2e8f9f7 720 ((BASE) == TIM_DMABASE_CCMR2) || \
<> 144:ef7eb2e8f9f7 721 ((BASE) == TIM_DMABASE_CCER) || \
<> 144:ef7eb2e8f9f7 722 ((BASE) == TIM_DMABASE_CNT) || \
<> 144:ef7eb2e8f9f7 723 ((BASE) == TIM_DMABASE_PSC) || \
<> 144:ef7eb2e8f9f7 724 ((BASE) == TIM_DMABASE_ARR) || \
<> 144:ef7eb2e8f9f7 725 ((BASE) == TIM_DMABASE_RCR) || \
<> 144:ef7eb2e8f9f7 726 ((BASE) == TIM_DMABASE_CCR1) || \
<> 144:ef7eb2e8f9f7 727 ((BASE) == TIM_DMABASE_CCR2) || \
<> 144:ef7eb2e8f9f7 728 ((BASE) == TIM_DMABASE_CCR3) || \
<> 144:ef7eb2e8f9f7 729 ((BASE) == TIM_DMABASE_CCR4) || \
<> 144:ef7eb2e8f9f7 730 ((BASE) == TIM_DMABASE_BDTR) || \
<> 144:ef7eb2e8f9f7 731 ((BASE) == TIM_DMABASE_CCMR3) || \
<> 144:ef7eb2e8f9f7 732 ((BASE) == TIM_DMABASE_CCR5) || \
<> 144:ef7eb2e8f9f7 733 ((BASE) == TIM_DMABASE_CCR6) || \
<> 144:ef7eb2e8f9f7 734 ((BASE) == TIM_DMABASE_OR))
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 737 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 738 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 739 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 740
<> 144:ef7eb2e8f9f7 741 #if defined(STM32F302xE) || \
<> 144:ef7eb2e8f9f7 742 defined(STM32F302xC) || \
<> 144:ef7eb2e8f9f7 743 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 744 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 745
<> 144:ef7eb2e8f9f7 746 #define IS_TIM_REMAP(REMAP) (((REMAP) == TIM_TIM1_ADC1_NONE) ||\
<> 144:ef7eb2e8f9f7 747 ((REMAP) == TIM_TIM1_ADC1_AWD1) ||\
<> 144:ef7eb2e8f9f7 748 ((REMAP) == TIM_TIM1_ADC1_AWD2) ||\
<> 144:ef7eb2e8f9f7 749 ((REMAP) == TIM_TIM1_ADC1_AWD3) ||\
<> 144:ef7eb2e8f9f7 750 ((REMAP) == TIM_TIM16_GPIO) ||\
<> 144:ef7eb2e8f9f7 751 ((REMAP) == TIM_TIM16_RTC) ||\
<> 144:ef7eb2e8f9f7 752 ((REMAP) == TIM_TIM16_HSE) ||\
<> 144:ef7eb2e8f9f7 753 ((REMAP) == TIM_TIM16_MCO))
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 #endif /* STM32F302xE || */
<> 144:ef7eb2e8f9f7 756 /* STM32F302xC || */
<> 144:ef7eb2e8f9f7 757 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 758 /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
<> 144:ef7eb2e8f9f7 759
<> 144:ef7eb2e8f9f7 760 #if defined(STM32F303xC) || defined(STM32F358xx)
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 #define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) ||\
<> 144:ef7eb2e8f9f7 763 ((REMAP1) == TIM_TIM1_ADC1_AWD1) ||\
<> 144:ef7eb2e8f9f7 764 ((REMAP1) == TIM_TIM1_ADC1_AWD2) ||\
<> 144:ef7eb2e8f9f7 765 ((REMAP1) == TIM_TIM1_ADC1_AWD3) ||\
<> 144:ef7eb2e8f9f7 766 ((REMAP1) == TIM_TIM8_ADC2_NONE) ||\
<> 144:ef7eb2e8f9f7 767 ((REMAP1) == TIM_TIM8_ADC2_AWD1) ||\
<> 144:ef7eb2e8f9f7 768 ((REMAP1) == TIM_TIM8_ADC2_AWD2) ||\
<> 144:ef7eb2e8f9f7 769 ((REMAP1) == TIM_TIM8_ADC2_AWD3) ||\
<> 144:ef7eb2e8f9f7 770 ((REMAP1) == TIM_TIM16_GPIO) ||\
<> 144:ef7eb2e8f9f7 771 ((REMAP1) == TIM_TIM16_RTC) ||\
<> 144:ef7eb2e8f9f7 772 ((REMAP1) == TIM_TIM16_HSE) ||\
<> 144:ef7eb2e8f9f7 773 ((REMAP1) == TIM_TIM16_MCO))
<> 144:ef7eb2e8f9f7 774
<> 144:ef7eb2e8f9f7 775 #define IS_TIM_REMAP2(REMAP2) (((REMAP2) == TIM_TIM1_ADC4_NONE) ||\
<> 144:ef7eb2e8f9f7 776 ((REMAP2) == TIM_TIM1_ADC4_AWD1) ||\
<> 144:ef7eb2e8f9f7 777 ((REMAP2) == TIM_TIM1_ADC4_AWD2) ||\
<> 144:ef7eb2e8f9f7 778 ((REMAP2) == TIM_TIM1_ADC4_AWD3) ||\
<> 144:ef7eb2e8f9f7 779 ((REMAP2) == TIM_TIM8_ADC3_NONE) ||\
<> 144:ef7eb2e8f9f7 780 ((REMAP2) == TIM_TIM8_ADC3_AWD1) ||\
<> 144:ef7eb2e8f9f7 781 ((REMAP2) == TIM_TIM8_ADC3_AWD2) ||\
<> 144:ef7eb2e8f9f7 782 ((REMAP2) == TIM_TIM8_ADC3_AWD3) ||\
<> 144:ef7eb2e8f9f7 783 ((REMAP2) == TIM_TIM16_NONE))
<> 144:ef7eb2e8f9f7 784
<> 144:ef7eb2e8f9f7 785 #endif /* STM32F303xC || STM32F358xx */
<> 144:ef7eb2e8f9f7 786
<> 144:ef7eb2e8f9f7 787 #if defined(STM32F303xE) || defined(STM32F398xx)
<> 144:ef7eb2e8f9f7 788
<> 144:ef7eb2e8f9f7 789 #define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) ||\
<> 144:ef7eb2e8f9f7 790 ((REMAP1) == TIM_TIM1_ADC1_AWD1) ||\
<> 144:ef7eb2e8f9f7 791 ((REMAP1) == TIM_TIM1_ADC1_AWD2) ||\
<> 144:ef7eb2e8f9f7 792 ((REMAP1) == TIM_TIM1_ADC1_AWD3) ||\
<> 144:ef7eb2e8f9f7 793 ((REMAP1) == TIM_TIM8_ADC2_NONE) ||\
<> 144:ef7eb2e8f9f7 794 ((REMAP1) == TIM_TIM8_ADC2_AWD1) ||\
<> 144:ef7eb2e8f9f7 795 ((REMAP1) == TIM_TIM8_ADC2_AWD2) ||\
<> 144:ef7eb2e8f9f7 796 ((REMAP1) == TIM_TIM8_ADC2_AWD3) ||\
<> 144:ef7eb2e8f9f7 797 ((REMAP1) == TIM_TIM16_GPIO) ||\
<> 144:ef7eb2e8f9f7 798 ((REMAP1) == TIM_TIM16_RTC) ||\
<> 144:ef7eb2e8f9f7 799 ((REMAP1) == TIM_TIM16_HSE) ||\
<> 144:ef7eb2e8f9f7 800 ((REMAP1) == TIM_TIM16_MCO) ||\
<> 144:ef7eb2e8f9f7 801 ((REMAP1) == TIM_TIM20_ADC3_NONE) ||\
<> 144:ef7eb2e8f9f7 802 ((REMAP1) == TIM_TIM20_ADC3_AWD1) ||\
<> 144:ef7eb2e8f9f7 803 ((REMAP1) == TIM_TIM20_ADC3_AWD2) ||\
<> 144:ef7eb2e8f9f7 804 ((REMAP1) == TIM_TIM20_ADC3_AWD3))
<> 144:ef7eb2e8f9f7 805
<> 144:ef7eb2e8f9f7 806 #define IS_TIM_REMAP2(REMAP2) (((REMAP2) == TIM_TIM1_ADC4_NONE) ||\
<> 144:ef7eb2e8f9f7 807 ((REMAP2) == TIM_TIM1_ADC4_AWD1) ||\
<> 144:ef7eb2e8f9f7 808 ((REMAP2) == TIM_TIM1_ADC4_AWD2) ||\
<> 144:ef7eb2e8f9f7 809 ((REMAP2) == TIM_TIM1_ADC4_AWD3) ||\
<> 144:ef7eb2e8f9f7 810 ((REMAP2) == TIM_TIM8_ADC3_NONE) ||\
<> 144:ef7eb2e8f9f7 811 ((REMAP2) == TIM_TIM8_ADC3_AWD1) ||\
<> 144:ef7eb2e8f9f7 812 ((REMAP2) == TIM_TIM8_ADC3_AWD2) ||\
<> 144:ef7eb2e8f9f7 813 ((REMAP2) == TIM_TIM8_ADC3_AWD3) ||\
<> 144:ef7eb2e8f9f7 814 ((REMAP2) == TIM_TIM16_NONE) ||\
<> 144:ef7eb2e8f9f7 815 ((REMAP2) == TIM_TIM20_ADC4_NONE) ||\
<> 144:ef7eb2e8f9f7 816 ((REMAP2) == TIM_TIM20_ADC4_AWD1) ||\
<> 144:ef7eb2e8f9f7 817 ((REMAP2) == TIM_TIM20_ADC4_AWD2) ||\
<> 144:ef7eb2e8f9f7 818 ((REMAP2) == TIM_TIM20_ADC4_AWD3))
<> 144:ef7eb2e8f9f7 819
<> 144:ef7eb2e8f9f7 820 #endif /* STM32F303xE || STM32F398xx */
<> 144:ef7eb2e8f9f7 821
<> 144:ef7eb2e8f9f7 822 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 823
<> 144:ef7eb2e8f9f7 824 #define IS_TIM_REMAP(REMAP) (((REMAP) == TIM_TIM2_TIM8_TRGO) ||\
<> 144:ef7eb2e8f9f7 825 ((REMAP) == TIM_TIM2_ETH_PTP) ||\
<> 144:ef7eb2e8f9f7 826 ((REMAP) == TIM_TIM2_USBFS_SOF) ||\
<> 144:ef7eb2e8f9f7 827 ((REMAP) == TIM_TIM2_USBHS_SOF) ||\
<> 144:ef7eb2e8f9f7 828 ((REMAP) == TIM_TIM14_GPIO) ||\
<> 144:ef7eb2e8f9f7 829 ((REMAP) == TIM_TIM14_RTC) ||\
<> 144:ef7eb2e8f9f7 830 ((REMAP) == TIM_TIM14_HSE) ||\
<> 144:ef7eb2e8f9f7 831 ((REMAP) == TIM_TIM14_MCO))
<> 144:ef7eb2e8f9f7 832
<> 144:ef7eb2e8f9f7 833 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 834
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 837 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 838 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 839 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 840
<> 144:ef7eb2e8f9f7 841 #define IS_TIM_GROUPCH5(OCREF) ((((OCREF) & 0x1FFFFFFF) == 0x00000000))
<> 144:ef7eb2e8f9f7 842
<> 144:ef7eb2e8f9f7 843 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 844 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 845 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 846 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 847
<> 144:ef7eb2e8f9f7 848 #define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFF)
<> 144:ef7eb2e8f9f7 849
<> 144:ef7eb2e8f9f7 850 /**
<> 144:ef7eb2e8f9f7 851 * @}
<> 144:ef7eb2e8f9f7 852 */
<> 144:ef7eb2e8f9f7 853 /* End of private macros -----------------------------------------------------*/
<> 144:ef7eb2e8f9f7 854
<> 144:ef7eb2e8f9f7 855
<> 144:ef7eb2e8f9f7 856 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 857 /** @defgroup TIMEx_Exported_Macros TIMEx Exported Macros
<> 144:ef7eb2e8f9f7 858 * @{
<> 144:ef7eb2e8f9f7 859 */
<> 144:ef7eb2e8f9f7 860
<> 144:ef7eb2e8f9f7 861 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 862 /**
<> 144:ef7eb2e8f9f7 863 * @brief Sets the TIM Capture Compare Register value on runtime without
<> 144:ef7eb2e8f9f7 864 * calling another time ConfigChannel function.
<> 144:ef7eb2e8f9f7 865 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 866 * @param __CHANNEL__: TIM Channels to be configured.
<> 144:ef7eb2e8f9f7 867 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 868 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 869 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 870 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 871 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 872 * @param __COMPARE__: specifies the Capture Compare register new value.
<> 144:ef7eb2e8f9f7 873 * @retval None
<> 144:ef7eb2e8f9f7 874 */
<> 144:ef7eb2e8f9f7 875 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
<> 144:ef7eb2e8f9f7 876 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
<> 144:ef7eb2e8f9f7 877
<> 144:ef7eb2e8f9f7 878 /**
<> 144:ef7eb2e8f9f7 879 * @brief Gets the TIM Capture Compare Register value on runtime
<> 144:ef7eb2e8f9f7 880 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 881 * @param __CHANNEL__: TIM Channel associated with the capture compare register
<> 144:ef7eb2e8f9f7 882 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 883 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
<> 144:ef7eb2e8f9f7 884 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
<> 144:ef7eb2e8f9f7 885 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
<> 144:ef7eb2e8f9f7 886 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
<> 144:ef7eb2e8f9f7 887 * @retval None
<> 144:ef7eb2e8f9f7 888 */
<> 144:ef7eb2e8f9f7 889 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
<> 144:ef7eb2e8f9f7 890 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
<> 144:ef7eb2e8f9f7 891 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 892
<> 144:ef7eb2e8f9f7 893 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 894 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 895 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 896 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 897 /**
<> 144:ef7eb2e8f9f7 898 * @brief Sets the TIM Capture Compare Register value on runtime without
<> 144:ef7eb2e8f9f7 899 * calling another time ConfigChannel function.
<> 144:ef7eb2e8f9f7 900 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 901 * @param __CHANNEL__: TIM Channels to be configured.
<> 144:ef7eb2e8f9f7 902 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 903 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 904 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 905 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 906 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 907 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
<> 144:ef7eb2e8f9f7 908 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
<> 144:ef7eb2e8f9f7 909 * @param __COMPARE__: specifies the Capture Compare register new value.
<> 144:ef7eb2e8f9f7 910 * @retval None
<> 144:ef7eb2e8f9f7 911 */
<> 144:ef7eb2e8f9f7 912 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
<> 144:ef7eb2e8f9f7 913 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
<> 144:ef7eb2e8f9f7 914 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
<> 144:ef7eb2e8f9f7 915 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
<> 144:ef7eb2e8f9f7 916 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
<> 144:ef7eb2e8f9f7 917 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
<> 144:ef7eb2e8f9f7 918 ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
<> 144:ef7eb2e8f9f7 919
<> 144:ef7eb2e8f9f7 920 /**
<> 144:ef7eb2e8f9f7 921 * @brief Gets the TIM Capture Compare Register value on runtime
<> 144:ef7eb2e8f9f7 922 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 923 * @param __CHANNEL__: TIM Channel associated with the capture compare register
<> 144:ef7eb2e8f9f7 924 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 925 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
<> 144:ef7eb2e8f9f7 926 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
<> 144:ef7eb2e8f9f7 927 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
<> 144:ef7eb2e8f9f7 928 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
<> 144:ef7eb2e8f9f7 929 * @arg TIM_CHANNEL_5: get capture/compare 5 register value
<> 144:ef7eb2e8f9f7 930 * @arg TIM_CHANNEL_6: get capture/compare 6 register value
<> 144:ef7eb2e8f9f7 931 * @retval None
<> 144:ef7eb2e8f9f7 932 */
<> 144:ef7eb2e8f9f7 933 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
<> 144:ef7eb2e8f9f7 934 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
<> 144:ef7eb2e8f9f7 935 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
<> 144:ef7eb2e8f9f7 936 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
<> 144:ef7eb2e8f9f7 937 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
<> 144:ef7eb2e8f9f7 938 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
<> 144:ef7eb2e8f9f7 939 ((__HANDLE__)->Instance->CCR6))
<> 144:ef7eb2e8f9f7 940 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 941 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 942 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 943 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 944 /**
<> 144:ef7eb2e8f9f7 945 * @}
<> 144:ef7eb2e8f9f7 946 */
<> 144:ef7eb2e8f9f7 947
<> 144:ef7eb2e8f9f7 948 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 949 /** @addtogroup TIMEx_Exported_Functions
<> 144:ef7eb2e8f9f7 950 * @{
<> 144:ef7eb2e8f9f7 951 */
<> 144:ef7eb2e8f9f7 952
<> 144:ef7eb2e8f9f7 953 /** @addtogroup TIMEx_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 954 * @{
<> 144:ef7eb2e8f9f7 955 */
<> 144:ef7eb2e8f9f7 956 /* Timer Hall Sensor functions **********************************************/
<> 144:ef7eb2e8f9f7 957 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig);
<> 144:ef7eb2e8f9f7 958 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 959
<> 144:ef7eb2e8f9f7 960 void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 961 void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 962
<> 144:ef7eb2e8f9f7 963 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 964 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 965 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 966 /* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 967 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 968 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 969 /* Non-Blocking mode: DMA */
<> 144:ef7eb2e8f9f7 970 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
<> 144:ef7eb2e8f9f7 971 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 972 /**
<> 144:ef7eb2e8f9f7 973 * @}
<> 144:ef7eb2e8f9f7 974 */
<> 144:ef7eb2e8f9f7 975
<> 144:ef7eb2e8f9f7 976 /** @addtogroup TIMEx_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 977 * @{
<> 144:ef7eb2e8f9f7 978 */
<> 144:ef7eb2e8f9f7 979 /* Timer Complementary Output Compare functions *****************************/
<> 144:ef7eb2e8f9f7 980 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 981 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 982 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 983
<> 144:ef7eb2e8f9f7 984 /* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 985 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 986 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 987
<> 144:ef7eb2e8f9f7 988 /* Non-Blocking mode: DMA */
<> 144:ef7eb2e8f9f7 989 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
<> 144:ef7eb2e8f9f7 990 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 991 /**
<> 144:ef7eb2e8f9f7 992 * @}
<> 144:ef7eb2e8f9f7 993 */
<> 144:ef7eb2e8f9f7 994
<> 144:ef7eb2e8f9f7 995 /** @addtogroup TIMEx_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 996 * @{
<> 144:ef7eb2e8f9f7 997 */
<> 144:ef7eb2e8f9f7 998 /* Timer Complementary PWM functions ****************************************/
<> 144:ef7eb2e8f9f7 999 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 1000 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1001 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1002
<> 144:ef7eb2e8f9f7 1003 /* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 1004 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1005 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1006 /* Non-Blocking mode: DMA */
<> 144:ef7eb2e8f9f7 1007 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
<> 144:ef7eb2e8f9f7 1008 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1009 /**
<> 144:ef7eb2e8f9f7 1010 * @}
<> 144:ef7eb2e8f9f7 1011 */
<> 144:ef7eb2e8f9f7 1012
<> 144:ef7eb2e8f9f7 1013 /** @addtogroup TIMEx_Exported_Functions_Group4
<> 144:ef7eb2e8f9f7 1014 * @{
<> 144:ef7eb2e8f9f7 1015 */
<> 144:ef7eb2e8f9f7 1016 /* Timer Complementary One Pulse functions **********************************/
<> 144:ef7eb2e8f9f7 1017 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 1018 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<> 144:ef7eb2e8f9f7 1019 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<> 144:ef7eb2e8f9f7 1020
<> 144:ef7eb2e8f9f7 1021 /* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 1022 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<> 144:ef7eb2e8f9f7 1023 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<> 144:ef7eb2e8f9f7 1024 /**
<> 144:ef7eb2e8f9f7 1025 * @}
<> 144:ef7eb2e8f9f7 1026 */
<> 144:ef7eb2e8f9f7 1027
<> 144:ef7eb2e8f9f7 1028 /** @addtogroup TIMEx_Exported_Functions_Group5
<> 144:ef7eb2e8f9f7 1029 * @{
<> 144:ef7eb2e8f9f7 1030 */
<> 144:ef7eb2e8f9f7 1031 /* Extended Control functions ************************************************/
<> 144:ef7eb2e8f9f7 1032 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
<> 144:ef7eb2e8f9f7 1033 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
<> 144:ef7eb2e8f9f7 1034 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
<> 144:ef7eb2e8f9f7 1035 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig);
<> 144:ef7eb2e8f9f7 1036 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
<> 144:ef7eb2e8f9f7 1037
<> 144:ef7eb2e8f9f7 1038 #if defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 1039 defined(STM32F303xC) || defined(STM32F358xx)
<> 144:ef7eb2e8f9f7 1040 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap1, uint32_t Remap2);
<> 144:ef7eb2e8f9f7 1041 #endif /* STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 1042 /* STM32F303xC || STM32F358xx */
<> 144:ef7eb2e8f9f7 1043
<> 144:ef7eb2e8f9f7 1044 #if defined(STM32F302xE) || \
<> 144:ef7eb2e8f9f7 1045 defined(STM32F302xC) || \
<> 144:ef7eb2e8f9f7 1046 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 1047 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
<> 144:ef7eb2e8f9f7 1048 defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 1049 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
<> 144:ef7eb2e8f9f7 1050 #endif /* STM32F302xE || */
<> 144:ef7eb2e8f9f7 1051 /* STM32F302xC || */
<> 144:ef7eb2e8f9f7 1052 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 1053 /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
<> 144:ef7eb2e8f9f7 1054 /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 1055
<> 144:ef7eb2e8f9f7 1056 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 1057 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 1058 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 1059 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 1060 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
<> 144:ef7eb2e8f9f7 1061 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 1062 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 1063 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 1064 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 1065 /**
<> 144:ef7eb2e8f9f7 1066 * @}
<> 144:ef7eb2e8f9f7 1067 */
<> 144:ef7eb2e8f9f7 1068
<> 144:ef7eb2e8f9f7 1069 /** @addtogroup TIMEx_Exported_Functions_Group6
<> 144:ef7eb2e8f9f7 1070 * @{
<> 144:ef7eb2e8f9f7 1071 */
<> 144:ef7eb2e8f9f7 1072 /* Extended Callback *********************************************************/
<> 144:ef7eb2e8f9f7 1073 void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1074 void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1075 /**
<> 144:ef7eb2e8f9f7 1076 * @}
<> 144:ef7eb2e8f9f7 1077 */
<> 144:ef7eb2e8f9f7 1078
<> 144:ef7eb2e8f9f7 1079 /** @addtogroup TIMEx_Exported_Functions_Group7
<> 144:ef7eb2e8f9f7 1080 * @{
<> 144:ef7eb2e8f9f7 1081 */
<> 144:ef7eb2e8f9f7 1082 /* Extended Peripheral State functions **************************************/
<> 144:ef7eb2e8f9f7 1083 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1084 /**
<> 144:ef7eb2e8f9f7 1085 * @}
<> 144:ef7eb2e8f9f7 1086 */
<> 144:ef7eb2e8f9f7 1087
<> 144:ef7eb2e8f9f7 1088 /**
<> 144:ef7eb2e8f9f7 1089 * @}
<> 144:ef7eb2e8f9f7 1090 */
<> 144:ef7eb2e8f9f7 1091 /* End of exported functions -------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1092
<> 144:ef7eb2e8f9f7 1093 /* Private functions----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1094 /** @defgroup TIMEx_Private_Functions TIMEx Private Functions
<> 144:ef7eb2e8f9f7 1095 * @{
<> 144:ef7eb2e8f9f7 1096 */
<> 144:ef7eb2e8f9f7 1097 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 1098 /**
<> 144:ef7eb2e8f9f7 1099 * @}
<> 144:ef7eb2e8f9f7 1100 */
<> 144:ef7eb2e8f9f7 1101 /* End of private functions --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1102
<> 144:ef7eb2e8f9f7 1103 /**
<> 144:ef7eb2e8f9f7 1104 * @}
<> 144:ef7eb2e8f9f7 1105 */
<> 144:ef7eb2e8f9f7 1106
<> 144:ef7eb2e8f9f7 1107 /**
<> 144:ef7eb2e8f9f7 1108 * @}
<> 144:ef7eb2e8f9f7 1109 */
<> 144:ef7eb2e8f9f7 1110
<> 144:ef7eb2e8f9f7 1111 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 1112 }
<> 144:ef7eb2e8f9f7 1113 #endif
<> 144:ef7eb2e8f9f7 1114
<> 144:ef7eb2e8f9f7 1115
<> 144:ef7eb2e8f9f7 1116 #endif /* __STM32F3xx_HAL_TIM_EX_H */
<> 144:ef7eb2e8f9f7 1117
<> 144:ef7eb2e8f9f7 1118 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/