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targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_flash_ex.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
124:6a4a5b7d7324 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_flash_ex.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.0.4
<> 144:ef7eb2e8f9f7 6 * @date 29-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of Flash HAL Extended module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F1xx_HAL_FLASH_EX_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F1xx_HAL_FLASH_EX_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f1xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup FLASHEx
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /** @addtogroup FLASHEx_Private_Constants
<> 144:ef7eb2e8f9f7 58 * @{
<> 144:ef7eb2e8f9f7 59 */
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 #define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFFF7E0)
<> 144:ef7eb2e8f9f7 62 #define OBR_REG_INDEX ((uint32_t)1)
<> 144:ef7eb2e8f9f7 63 #define SR_FLAG_MASK ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP))
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 /**
<> 144:ef7eb2e8f9f7 66 * @}
<> 144:ef7eb2e8f9f7 67 */
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 /** @addtogroup FLASHEx_Private_Macros
<> 144:ef7eb2e8f9f7 70 * @{
<> 144:ef7eb2e8f9f7 71 */
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || ((VALUE) == FLASH_TYPEERASE_MASSERASE))
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA)))
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 #define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE))
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1))
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 #define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 #if defined(FLASH_BANK2_END)
<> 144:ef7eb2e8f9f7 90 #define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
<> 144:ef7eb2e8f9f7 91 #endif /* FLASH_BANK2_END */
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /* Low Density */
<> 144:ef7eb2e8f9f7 94 #if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
<> 144:ef7eb2e8f9f7 95 #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFF) : \
<> 144:ef7eb2e8f9f7 96 ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFF))
<> 144:ef7eb2e8f9f7 97 #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 /* Medium Density */
<> 144:ef7eb2e8f9f7 100 #if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
<> 144:ef7eb2e8f9f7 101 #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFF) : \
<> 144:ef7eb2e8f9f7 102 (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFF) : \
<> 144:ef7eb2e8f9f7 103 (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFF) : \
<> 144:ef7eb2e8f9f7 104 ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFF))))
<> 144:ef7eb2e8f9f7 105 #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 /* High Density */
<> 144:ef7eb2e8f9f7 108 #if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
<> 144:ef7eb2e8f9f7 109 #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0807FFFF) : \
<> 144:ef7eb2e8f9f7 110 (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0805FFFF) : \
<> 144:ef7eb2e8f9f7 111 ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFF)))
<> 144:ef7eb2e8f9f7 112 #endif /* STM32F100xE || STM32F101xE || STM32F103xE */
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /* XL Density */
<> 144:ef7eb2e8f9f7 115 #if defined(FLASH_BANK2_END)
<> 144:ef7eb2e8f9f7 116 #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080FFFFF) : \
<> 144:ef7eb2e8f9f7 117 ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080BFFFF))
<> 144:ef7eb2e8f9f7 118 #endif /* FLASH_BANK2_END */
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 /* Connectivity Line */
<> 144:ef7eb2e8f9f7 121 #if (defined(STM32F105xC) || defined(STM32F107xC))
<> 144:ef7eb2e8f9f7 122 #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFF) : \
<> 144:ef7eb2e8f9f7 123 (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFF) : \
<> 144:ef7eb2e8f9f7 124 ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFF)))
<> 144:ef7eb2e8f9f7 125 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 #define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 #if defined(FLASH_BANK2_END)
<> 144:ef7eb2e8f9f7 130 #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
<> 144:ef7eb2e8f9f7 131 ((BANK) == FLASH_BANK_2) || \
<> 144:ef7eb2e8f9f7 132 ((BANK) == FLASH_BANK_BOTH))
<> 144:ef7eb2e8f9f7 133 #else
<> 144:ef7eb2e8f9f7 134 #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
<> 144:ef7eb2e8f9f7 135 #endif /* FLASH_BANK2_END */
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 /* Low Density */
<> 144:ef7eb2e8f9f7 138 #if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
<> 144:ef7eb2e8f9f7 139 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? \
<> 144:ef7eb2e8f9f7 140 ((ADDRESS) <= FLASH_BANK1_END) : ((ADDRESS) <= 0x08003FFF)))
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 /* Medium Density */
<> 144:ef7eb2e8f9f7 145 #if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
<> 144:ef7eb2e8f9f7 146 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? \
<> 144:ef7eb2e8f9f7 147 ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40) ? \
<> 144:ef7eb2e8f9f7 148 ((ADDRESS) <= 0x0800FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? \
<> 144:ef7eb2e8f9f7 149 ((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFF)))))
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /* High Density */
<> 144:ef7eb2e8f9f7 154 #if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
<> 144:ef7eb2e8f9f7 155 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200) ? \
<> 144:ef7eb2e8f9f7 156 ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180) ? \
<> 144:ef7eb2e8f9f7 157 ((ADDRESS) <= 0x0805FFFF) : ((ADDRESS) <= 0x0803FFFF))))
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 #endif /* STM32F100xE || STM32F101xE || STM32F103xE */
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /* XL Density */
<> 144:ef7eb2e8f9f7 162 #if defined(FLASH_BANK2_END)
<> 144:ef7eb2e8f9f7 163 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400) ? \
<> 144:ef7eb2e8f9f7 164 ((ADDRESS) <= FLASH_BANK2_END) : ((ADDRESS) <= 0x080BFFFF)))
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 #endif /* FLASH_BANK2_END */
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /* Connectivity Line */
<> 144:ef7eb2e8f9f7 169 #if (defined(STM32F105xC) || defined(STM32F107xC))
<> 144:ef7eb2e8f9f7 170 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100) ? \
<> 144:ef7eb2e8f9f7 171 ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? \
<> 144:ef7eb2e8f9f7 172 ((ADDRESS) <= 0x0801FFFF) : ((ADDRESS) <= 0x0800FFFF))))
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /**
<> 144:ef7eb2e8f9f7 177 * @}
<> 144:ef7eb2e8f9f7 178 */
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 181 /** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
<> 144:ef7eb2e8f9f7 182 * @{
<> 144:ef7eb2e8f9f7 183 */
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /**
<> 144:ef7eb2e8f9f7 186 * @brief FLASH Erase structure definition
<> 144:ef7eb2e8f9f7 187 */
<> 144:ef7eb2e8f9f7 188 typedef struct
<> 144:ef7eb2e8f9f7 189 {
<> 144:ef7eb2e8f9f7 190 uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase.
<> 144:ef7eb2e8f9f7 191 This parameter can be a value of @ref FLASHEx_Type_Erase */
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.
<> 144:ef7eb2e8f9f7 194 This parameter must be a value of @ref FLASHEx_Banks */
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled
<> 144:ef7eb2e8f9f7 197 This parameter must be a number between Min_Data = 0x08000000 and Max_Data = FLASH_BANKx_END
<> 144:ef7eb2e8f9f7 198 (x = 1 or 2 depending on devices)*/
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 uint32_t NbPages; /*!< NbPages: Number of pagess to be erased.
<> 144:ef7eb2e8f9f7 201 This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 } FLASH_EraseInitTypeDef;
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /**
<> 144:ef7eb2e8f9f7 206 * @brief FLASH Options bytes program structure definition
<> 144:ef7eb2e8f9f7 207 */
<> 144:ef7eb2e8f9f7 208 typedef struct
<> 144:ef7eb2e8f9f7 209 {
<> 144:ef7eb2e8f9f7 210 uint32_t OptionType; /*!< OptionType: Option byte to be configured.
<> 144:ef7eb2e8f9f7 211 This parameter can be a value of @ref FLASHEx_OB_Type */
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
<> 144:ef7eb2e8f9f7 214 This parameter can be a value of @ref FLASHEx_OB_WRP_State */
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected
<> 144:ef7eb2e8f9f7 217 This parameter can be a value of @ref FLASHEx_OB_Write_Protection */
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors.
<> 144:ef7eb2e8f9f7 220 This parameter must be a value of @ref FLASHEx_Banks */
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level..
<> 144:ef7eb2e8f9f7 223 This parameter can be a value of @ref FLASHEx_OB_Read_Protection */
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 #if defined(FLASH_BANK2_END)
<> 144:ef7eb2e8f9f7 226 uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
<> 144:ef7eb2e8f9f7 227 IWDG / STOP / STDBY / BOOT1
<> 144:ef7eb2e8f9f7 228 This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
<> 144:ef7eb2e8f9f7 229 @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1 */
<> 144:ef7eb2e8f9f7 230 #else
<> 144:ef7eb2e8f9f7 231 uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
<> 144:ef7eb2e8f9f7 232 IWDG / STOP / STDBY
<> 144:ef7eb2e8f9f7 233 This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
<> 144:ef7eb2e8f9f7 234 @ref FLASHEx_OB_nRST_STDBY */
<> 144:ef7eb2e8f9f7 235 #endif /* FLASH_BANK2_END */
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed
<> 144:ef7eb2e8f9f7 238 This parameter can be a value of @ref FLASHEx_OB_Data_Address */
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA
<> 144:ef7eb2e8f9f7 241 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
<> 144:ef7eb2e8f9f7 242 } FLASH_OBProgramInitTypeDef;
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /**
<> 144:ef7eb2e8f9f7 245 * @}
<> 144:ef7eb2e8f9f7 246 */
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 249 /** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
<> 144:ef7eb2e8f9f7 250 * @{
<> 144:ef7eb2e8f9f7 251 */
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /** @defgroup FLASHEx_Constants FLASH Constants
<> 144:ef7eb2e8f9f7 254 * @{
<> 144:ef7eb2e8f9f7 255 */
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /** @defgroup FLASHEx_Page_Size Page Size
<> 144:ef7eb2e8f9f7 258 * @{
<> 144:ef7eb2e8f9f7 259 */
<> 144:ef7eb2e8f9f7 260 #if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
<> 144:ef7eb2e8f9f7 261 #define FLASH_PAGE_SIZE ((uint32_t)0x400)
<> 144:ef7eb2e8f9f7 262 #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
<> 144:ef7eb2e8f9f7 263 /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 #if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC))
<> 144:ef7eb2e8f9f7 266 #define FLASH_PAGE_SIZE ((uint32_t)0x800)
<> 144:ef7eb2e8f9f7 267 #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
<> 144:ef7eb2e8f9f7 268 /* STM32F101xG || STM32F103xG */
<> 144:ef7eb2e8f9f7 269 /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 /**
<> 144:ef7eb2e8f9f7 272 * @}
<> 144:ef7eb2e8f9f7 273 */
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 /** @defgroup FLASHEx_Type_Erase Type Erase
<> 144:ef7eb2e8f9f7 276 * @{
<> 144:ef7eb2e8f9f7 277 */
<> 144:ef7eb2e8f9f7 278 #define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /*!<Pages erase only*/
<> 144:ef7eb2e8f9f7 279 #define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x02) /*!<Flash mass erase activation*/
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 /**
<> 144:ef7eb2e8f9f7 282 * @}
<> 144:ef7eb2e8f9f7 283 */
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /** @defgroup FLASHEx_Banks Banks
<> 144:ef7eb2e8f9f7 286 * @{
<> 144:ef7eb2e8f9f7 287 */
<> 144:ef7eb2e8f9f7 288 #if defined(FLASH_BANK2_END)
<> 144:ef7eb2e8f9f7 289 #define FLASH_BANK_1 ((uint32_t)1) /*!< Bank 1 */
<> 144:ef7eb2e8f9f7 290 #define FLASH_BANK_2 ((uint32_t)2) /*!< Bank 2 */
<> 144:ef7eb2e8f9f7 291 #define FLASH_BANK_BOTH ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 #else
<> 144:ef7eb2e8f9f7 294 #define FLASH_BANK_1 ((uint32_t)1) /*!< Bank 1 */
<> 144:ef7eb2e8f9f7 295 #endif
<> 144:ef7eb2e8f9f7 296 /**
<> 144:ef7eb2e8f9f7 297 * @}
<> 144:ef7eb2e8f9f7 298 */
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /**
<> 144:ef7eb2e8f9f7 301 * @}
<> 144:ef7eb2e8f9f7 302 */
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 /** @defgroup FLASHEx_OptionByte_Constants Option Byte Constants
<> 144:ef7eb2e8f9f7 305 * @{
<> 144:ef7eb2e8f9f7 306 */
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /** @defgroup FLASHEx_OB_Type Option Bytes Type
<> 144:ef7eb2e8f9f7 309 * @{
<> 144:ef7eb2e8f9f7 310 */
<> 144:ef7eb2e8f9f7 311 #define OPTIONBYTE_WRP ((uint32_t)0x01) /*!<WRP option byte configuration*/
<> 144:ef7eb2e8f9f7 312 #define OPTIONBYTE_RDP ((uint32_t)0x02) /*!<RDP option byte configuration*/
<> 144:ef7eb2e8f9f7 313 #define OPTIONBYTE_USER ((uint32_t)0x04) /*!<USER option byte configuration*/
<> 144:ef7eb2e8f9f7 314 #define OPTIONBYTE_DATA ((uint32_t)0x08) /*!<DATA option byte configuration*/
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 /**
<> 144:ef7eb2e8f9f7 317 * @}
<> 144:ef7eb2e8f9f7 318 */
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 /** @defgroup FLASHEx_OB_WRP_State Option Byte WRP State
<> 144:ef7eb2e8f9f7 321 * @{
<> 144:ef7eb2e8f9f7 322 */
<> 144:ef7eb2e8f9f7 323 #define OB_WRPSTATE_DISABLE ((uint32_t)0x00) /*!<Disable the write protection of the desired pages*/
<> 144:ef7eb2e8f9f7 324 #define OB_WRPSTATE_ENABLE ((uint32_t)0x01) /*!<Enable the write protection of the desired pagess*/
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 /**
<> 144:ef7eb2e8f9f7 327 * @}
<> 144:ef7eb2e8f9f7 328 */
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /** @defgroup FLASHEx_OB_Write_Protection Option Bytes Write Protection
<> 144:ef7eb2e8f9f7 331 * @{
<> 144:ef7eb2e8f9f7 332 */
<> 144:ef7eb2e8f9f7 333 /* STM32 Low and Medium density devices */
<> 144:ef7eb2e8f9f7 334 #if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) \
<> 144:ef7eb2e8f9f7 335 || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) \
<> 144:ef7eb2e8f9f7 336 || defined(STM32F103xB)
<> 144:ef7eb2e8f9f7 337 #define OB_WRP_PAGES0TO3 ((uint32_t)0x00000001) /*!< Write protection of page 0 to 3 */
<> 144:ef7eb2e8f9f7 338 #define OB_WRP_PAGES4TO7 ((uint32_t)0x00000002) /*!< Write protection of page 4 to 7 */
<> 144:ef7eb2e8f9f7 339 #define OB_WRP_PAGES8TO11 ((uint32_t)0x00000004) /*!< Write protection of page 8 to 11 */
<> 144:ef7eb2e8f9f7 340 #define OB_WRP_PAGES12TO15 ((uint32_t)0x00000008) /*!< Write protection of page 12 to 15 */
<> 144:ef7eb2e8f9f7 341 #define OB_WRP_PAGES16TO19 ((uint32_t)0x00000010) /*!< Write protection of page 16 to 19 */
<> 144:ef7eb2e8f9f7 342 #define OB_WRP_PAGES20TO23 ((uint32_t)0x00000020) /*!< Write protection of page 20 to 23 */
<> 144:ef7eb2e8f9f7 343 #define OB_WRP_PAGES24TO27 ((uint32_t)0x00000040) /*!< Write protection of page 24 to 27 */
<> 144:ef7eb2e8f9f7 344 #define OB_WRP_PAGES28TO31 ((uint32_t)0x00000080) /*!< Write protection of page 28 to 31 */
<> 144:ef7eb2e8f9f7 345 #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
<> 144:ef7eb2e8f9f7 346 /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 /* STM32 Medium-density devices */
<> 144:ef7eb2e8f9f7 349 #if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
<> 144:ef7eb2e8f9f7 350 #define OB_WRP_PAGES32TO35 ((uint32_t)0x00000100) /*!< Write protection of page 32 to 35 */
<> 144:ef7eb2e8f9f7 351 #define OB_WRP_PAGES36TO39 ((uint32_t)0x00000200) /*!< Write protection of page 36 to 39 */
<> 144:ef7eb2e8f9f7 352 #define OB_WRP_PAGES40TO43 ((uint32_t)0x00000400) /*!< Write protection of page 40 to 43 */
<> 144:ef7eb2e8f9f7 353 #define OB_WRP_PAGES44TO47 ((uint32_t)0x00000800) /*!< Write protection of page 44 to 47 */
<> 144:ef7eb2e8f9f7 354 #define OB_WRP_PAGES48TO51 ((uint32_t)0x00001000) /*!< Write protection of page 48 to 51 */
<> 144:ef7eb2e8f9f7 355 #define OB_WRP_PAGES52TO55 ((uint32_t)0x00002000) /*!< Write protection of page 52 to 55 */
<> 144:ef7eb2e8f9f7 356 #define OB_WRP_PAGES56TO59 ((uint32_t)0x00004000) /*!< Write protection of page 56 to 59 */
<> 144:ef7eb2e8f9f7 357 #define OB_WRP_PAGES60TO63 ((uint32_t)0x00008000) /*!< Write protection of page 60 to 63 */
<> 144:ef7eb2e8f9f7 358 #define OB_WRP_PAGES64TO67 ((uint32_t)0x00010000) /*!< Write protection of page 64 to 67 */
<> 144:ef7eb2e8f9f7 359 #define OB_WRP_PAGES68TO71 ((uint32_t)0x00020000) /*!< Write protection of page 68 to 71 */
<> 144:ef7eb2e8f9f7 360 #define OB_WRP_PAGES72TO75 ((uint32_t)0x00040000) /*!< Write protection of page 72 to 75 */
<> 144:ef7eb2e8f9f7 361 #define OB_WRP_PAGES76TO79 ((uint32_t)0x00080000) /*!< Write protection of page 76 to 79 */
<> 144:ef7eb2e8f9f7 362 #define OB_WRP_PAGES80TO83 ((uint32_t)0x00100000) /*!< Write protection of page 80 to 83 */
<> 144:ef7eb2e8f9f7 363 #define OB_WRP_PAGES84TO87 ((uint32_t)0x00200000) /*!< Write protection of page 84 to 87 */
<> 144:ef7eb2e8f9f7 364 #define OB_WRP_PAGES88TO91 ((uint32_t)0x00400000) /*!< Write protection of page 88 to 91 */
<> 144:ef7eb2e8f9f7 365 #define OB_WRP_PAGES92TO95 ((uint32_t)0x00800000) /*!< Write protection of page 92 to 95 */
<> 144:ef7eb2e8f9f7 366 #define OB_WRP_PAGES96TO99 ((uint32_t)0x01000000) /*!< Write protection of page 96 to 99 */
<> 144:ef7eb2e8f9f7 367 #define OB_WRP_PAGES100TO103 ((uint32_t)0x02000000) /*!< Write protection of page 100 to 103 */
<> 144:ef7eb2e8f9f7 368 #define OB_WRP_PAGES104TO107 ((uint32_t)0x04000000) /*!< Write protection of page 104 to 107 */
<> 144:ef7eb2e8f9f7 369 #define OB_WRP_PAGES108TO111 ((uint32_t)0x08000000) /*!< Write protection of page 108 to 111 */
<> 144:ef7eb2e8f9f7 370 #define OB_WRP_PAGES112TO115 ((uint32_t)0x10000000) /*!< Write protection of page 112 to 115 */
<> 144:ef7eb2e8f9f7 371 #define OB_WRP_PAGES116TO119 ((uint32_t)0x20000000) /*!< Write protection of page 115 to 119 */
<> 144:ef7eb2e8f9f7 372 #define OB_WRP_PAGES120TO123 ((uint32_t)0x40000000) /*!< Write protection of page 120 to 123 */
<> 144:ef7eb2e8f9f7 373 #define OB_WRP_PAGES124TO127 ((uint32_t)0x80000000) /*!< Write protection of page 124 to 127 */
<> 144:ef7eb2e8f9f7 374 #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 /* STM32 High-density, XL-density and Connectivity line devices */
<> 144:ef7eb2e8f9f7 378 #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) \
<> 144:ef7eb2e8f9f7 379 || defined(STM32F101xG) || defined(STM32F103xG) \
<> 144:ef7eb2e8f9f7 380 || defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 381 #define OB_WRP_PAGES0TO1 ((uint32_t)0x00000001) /*!< Write protection of page 0 TO 1 */
<> 144:ef7eb2e8f9f7 382 #define OB_WRP_PAGES2TO3 ((uint32_t)0x00000002) /*!< Write protection of page 2 TO 3 */
<> 144:ef7eb2e8f9f7 383 #define OB_WRP_PAGES4TO5 ((uint32_t)0x00000004) /*!< Write protection of page 4 TO 5 */
<> 144:ef7eb2e8f9f7 384 #define OB_WRP_PAGES6TO7 ((uint32_t)0x00000008) /*!< Write protection of page 6 TO 7 */
<> 144:ef7eb2e8f9f7 385 #define OB_WRP_PAGES8TO9 ((uint32_t)0x00000010) /*!< Write protection of page 8 TO 9 */
<> 144:ef7eb2e8f9f7 386 #define OB_WRP_PAGES10TO11 ((uint32_t)0x00000020) /*!< Write protection of page 10 TO 11 */
<> 144:ef7eb2e8f9f7 387 #define OB_WRP_PAGES12TO13 ((uint32_t)0x00000040) /*!< Write protection of page 12 TO 13 */
<> 144:ef7eb2e8f9f7 388 #define OB_WRP_PAGES14TO15 ((uint32_t)0x00000080) /*!< Write protection of page 14 TO 15 */
<> 144:ef7eb2e8f9f7 389 #define OB_WRP_PAGES16TO17 ((uint32_t)0x00000100) /*!< Write protection of page 16 TO 17 */
<> 144:ef7eb2e8f9f7 390 #define OB_WRP_PAGES18TO19 ((uint32_t)0x00000200) /*!< Write protection of page 18 TO 19 */
<> 144:ef7eb2e8f9f7 391 #define OB_WRP_PAGES20TO21 ((uint32_t)0x00000400) /*!< Write protection of page 20 TO 21 */
<> 144:ef7eb2e8f9f7 392 #define OB_WRP_PAGES22TO23 ((uint32_t)0x00000800) /*!< Write protection of page 22 TO 23 */
<> 144:ef7eb2e8f9f7 393 #define OB_WRP_PAGES24TO25 ((uint32_t)0x00001000) /*!< Write protection of page 24 TO 25 */
<> 144:ef7eb2e8f9f7 394 #define OB_WRP_PAGES26TO27 ((uint32_t)0x00002000) /*!< Write protection of page 26 TO 27 */
<> 144:ef7eb2e8f9f7 395 #define OB_WRP_PAGES28TO29 ((uint32_t)0x00004000) /*!< Write protection of page 28 TO 29 */
<> 144:ef7eb2e8f9f7 396 #define OB_WRP_PAGES30TO31 ((uint32_t)0x00008000) /*!< Write protection of page 30 TO 31 */
<> 144:ef7eb2e8f9f7 397 #define OB_WRP_PAGES32TO33 ((uint32_t)0x00010000) /*!< Write protection of page 32 TO 33 */
<> 144:ef7eb2e8f9f7 398 #define OB_WRP_PAGES34TO35 ((uint32_t)0x00020000) /*!< Write protection of page 34 TO 35 */
<> 144:ef7eb2e8f9f7 399 #define OB_WRP_PAGES36TO37 ((uint32_t)0x00040000) /*!< Write protection of page 36 TO 37 */
<> 144:ef7eb2e8f9f7 400 #define OB_WRP_PAGES38TO39 ((uint32_t)0x00080000) /*!< Write protection of page 38 TO 39 */
<> 144:ef7eb2e8f9f7 401 #define OB_WRP_PAGES40TO41 ((uint32_t)0x00100000) /*!< Write protection of page 40 TO 41 */
<> 144:ef7eb2e8f9f7 402 #define OB_WRP_PAGES42TO43 ((uint32_t)0x00200000) /*!< Write protection of page 42 TO 43 */
<> 144:ef7eb2e8f9f7 403 #define OB_WRP_PAGES44TO45 ((uint32_t)0x00400000) /*!< Write protection of page 44 TO 45 */
<> 144:ef7eb2e8f9f7 404 #define OB_WRP_PAGES46TO47 ((uint32_t)0x00800000) /*!< Write protection of page 46 TO 47 */
<> 144:ef7eb2e8f9f7 405 #define OB_WRP_PAGES48TO49 ((uint32_t)0x01000000) /*!< Write protection of page 48 TO 49 */
<> 144:ef7eb2e8f9f7 406 #define OB_WRP_PAGES50TO51 ((uint32_t)0x02000000) /*!< Write protection of page 50 TO 51 */
<> 144:ef7eb2e8f9f7 407 #define OB_WRP_PAGES52TO53 ((uint32_t)0x04000000) /*!< Write protection of page 52 TO 53 */
<> 144:ef7eb2e8f9f7 408 #define OB_WRP_PAGES54TO55 ((uint32_t)0x08000000) /*!< Write protection of page 54 TO 55 */
<> 144:ef7eb2e8f9f7 409 #define OB_WRP_PAGES56TO57 ((uint32_t)0x10000000) /*!< Write protection of page 56 TO 57 */
<> 144:ef7eb2e8f9f7 410 #define OB_WRP_PAGES58TO59 ((uint32_t)0x20000000) /*!< Write protection of page 58 TO 59 */
<> 144:ef7eb2e8f9f7 411 #define OB_WRP_PAGES60TO61 ((uint32_t)0x40000000) /*!< Write protection of page 60 TO 61 */
<> 144:ef7eb2e8f9f7 412 #define OB_WRP_PAGES62TO127 ((uint32_t)0x80000000) /*!< Write protection of page 62 TO 127 */
<> 144:ef7eb2e8f9f7 413 #define OB_WRP_PAGES62TO255 ((uint32_t)0x80000000) /*!< Write protection of page 62 TO 255 */
<> 144:ef7eb2e8f9f7 414 #define OB_WRP_PAGES62TO511 ((uint32_t)0x80000000) /*!< Write protection of page 62 TO 511 */
<> 144:ef7eb2e8f9f7 415 #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
<> 144:ef7eb2e8f9f7 416 /* STM32F101xG || STM32F103xG */
<> 144:ef7eb2e8f9f7 417 /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 #define OB_WRP_ALLPAGES ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 /* Low Density */
<> 144:ef7eb2e8f9f7 422 #if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)
<> 144:ef7eb2e8f9f7 423 #define OB_WRP_PAGES0TO31MASK ((uint32_t)0x000000FF)
<> 144:ef7eb2e8f9f7 424 #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 /* Medium Density */
<> 144:ef7eb2e8f9f7 427 #if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
<> 144:ef7eb2e8f9f7 428 #define OB_WRP_PAGES0TO31MASK ((uint32_t)0x000000FF)
<> 144:ef7eb2e8f9f7 429 #define OB_WRP_PAGES32TO63MASK ((uint32_t)0x0000FF00)
<> 144:ef7eb2e8f9f7 430 #define OB_WRP_PAGES64TO95MASK ((uint32_t)0x00FF0000)
<> 144:ef7eb2e8f9f7 431 #define OB_WRP_PAGES96TO127MASK ((uint32_t)0xFF000000)
<> 144:ef7eb2e8f9f7 432 #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 /* High Density */
<> 144:ef7eb2e8f9f7 435 #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)
<> 144:ef7eb2e8f9f7 436 #define OB_WRP_PAGES0TO15MASK ((uint32_t)0x000000FF)
<> 144:ef7eb2e8f9f7 437 #define OB_WRP_PAGES16TO31MASK ((uint32_t)0x0000FF00)
<> 144:ef7eb2e8f9f7 438 #define OB_WRP_PAGES32TO47MASK ((uint32_t)0x00FF0000)
<> 144:ef7eb2e8f9f7 439 #define OB_WRP_PAGES48TO255MASK ((uint32_t)0xFF000000)
<> 144:ef7eb2e8f9f7 440 #endif /* STM32F100xE || STM32F101xE || STM32F103xE */
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442 /* XL Density */
<> 144:ef7eb2e8f9f7 443 #if defined(STM32F101xG) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 444 #define OB_WRP_PAGES0TO15MASK ((uint32_t)0x000000FF)
<> 144:ef7eb2e8f9f7 445 #define OB_WRP_PAGES16TO31MASK ((uint32_t)0x0000FF00)
<> 144:ef7eb2e8f9f7 446 #define OB_WRP_PAGES32TO47MASK ((uint32_t)0x00FF0000)
<> 144:ef7eb2e8f9f7 447 #define OB_WRP_PAGES48TO511MASK ((uint32_t)0xFF000000)
<> 144:ef7eb2e8f9f7 448 #endif /* STM32F101xG || STM32F103xG */
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 /* Connectivity line devices */
<> 144:ef7eb2e8f9f7 451 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 452 #define OB_WRP_PAGES0TO15MASK ((uint32_t)0x000000FF)
<> 144:ef7eb2e8f9f7 453 #define OB_WRP_PAGES16TO31MASK ((uint32_t)0x0000FF00)
<> 144:ef7eb2e8f9f7 454 #define OB_WRP_PAGES32TO47MASK ((uint32_t)0x00FF0000)
<> 144:ef7eb2e8f9f7 455 #define OB_WRP_PAGES48TO127MASK ((uint32_t)0xFF000000)
<> 144:ef7eb2e8f9f7 456 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 /**
<> 144:ef7eb2e8f9f7 459 * @}
<> 144:ef7eb2e8f9f7 460 */
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 /** @defgroup FLASHEx_OB_Read_Protection Option Byte Read Protection
<> 144:ef7eb2e8f9f7 463 * @{
<> 144:ef7eb2e8f9f7 464 */
<> 144:ef7eb2e8f9f7 465 #define OB_RDP_LEVEL_0 ((uint8_t)0xA5)
<> 144:ef7eb2e8f9f7 466 #define OB_RDP_LEVEL_1 ((uint8_t)0x00)
<> 144:ef7eb2e8f9f7 467 /**
<> 144:ef7eb2e8f9f7 468 * @}
<> 144:ef7eb2e8f9f7 469 */
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 /** @defgroup FLASHEx_OB_IWatchdog Option Byte IWatchdog
<> 144:ef7eb2e8f9f7 472 * @{
<> 144:ef7eb2e8f9f7 473 */
<> 144:ef7eb2e8f9f7 474 #define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */
<> 144:ef7eb2e8f9f7 475 #define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */
<> 144:ef7eb2e8f9f7 476 /**
<> 144:ef7eb2e8f9f7 477 * @}
<> 144:ef7eb2e8f9f7 478 */
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 /** @defgroup FLASHEx_OB_nRST_STOP Option Byte nRST STOP
<> 144:ef7eb2e8f9f7 481 * @{
<> 144:ef7eb2e8f9f7 482 */
<> 144:ef7eb2e8f9f7 483 #define OB_STOP_NO_RST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
<> 144:ef7eb2e8f9f7 484 #define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
<> 144:ef7eb2e8f9f7 485 /**
<> 144:ef7eb2e8f9f7 486 * @}
<> 144:ef7eb2e8f9f7 487 */
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 /** @defgroup FLASHEx_OB_nRST_STDBY Option Byte nRST STDBY
<> 144:ef7eb2e8f9f7 490 * @{
<> 144:ef7eb2e8f9f7 491 */
<> 144:ef7eb2e8f9f7 492 #define OB_STDBY_NO_RST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
<> 144:ef7eb2e8f9f7 493 #define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
<> 144:ef7eb2e8f9f7 494 /**
<> 144:ef7eb2e8f9f7 495 * @}
<> 144:ef7eb2e8f9f7 496 */
<> 144:ef7eb2e8f9f7 497
<> 144:ef7eb2e8f9f7 498 #if defined(FLASH_BANK2_END)
<> 144:ef7eb2e8f9f7 499 /** @defgroup FLASHEx_OB_BOOT1 Option Byte BOOT1
<> 144:ef7eb2e8f9f7 500 * @{
<> 144:ef7eb2e8f9f7 501 */
<> 144:ef7eb2e8f9f7 502 #define OB_BOOT1_RESET ((uint16_t)0x0000) /*!< BOOT1 Reset */
<> 144:ef7eb2e8f9f7 503 #define OB_BOOT1_SET ((uint16_t)0x0008) /*!< BOOT1 Set */
<> 144:ef7eb2e8f9f7 504 /**
<> 144:ef7eb2e8f9f7 505 * @}
<> 144:ef7eb2e8f9f7 506 */
<> 144:ef7eb2e8f9f7 507 #endif /* FLASH_BANK2_END */
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 /** @defgroup FLASHEx_OB_Data_Address Option Byte Data Address
<> 144:ef7eb2e8f9f7 510 * @{
<> 144:ef7eb2e8f9f7 511 */
<> 144:ef7eb2e8f9f7 512 #define OB_DATA_ADDRESS_DATA0 ((uint32_t)0x1FFFF804)
<> 144:ef7eb2e8f9f7 513 #define OB_DATA_ADDRESS_DATA1 ((uint32_t)0x1FFFF806)
<> 144:ef7eb2e8f9f7 514 /**
<> 144:ef7eb2e8f9f7 515 * @}
<> 144:ef7eb2e8f9f7 516 */
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 /**
<> 144:ef7eb2e8f9f7 519 * @}
<> 144:ef7eb2e8f9f7 520 */
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 /** @addtogroup FLASHEx_Constants
<> 144:ef7eb2e8f9f7 523 * @{
<> 144:ef7eb2e8f9f7 524 */
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 /** @defgroup FLASH_Flag_definition Flag definition
<> 144:ef7eb2e8f9f7 527 * @brief Flag definition
<> 144:ef7eb2e8f9f7 528 * @{
<> 144:ef7eb2e8f9f7 529 */
<> 144:ef7eb2e8f9f7 530 #if defined(FLASH_BANK2_END)
<> 144:ef7eb2e8f9f7 531 #define FLASH_FLAG_BSY FLASH_FLAG_BSY_BANK1 /*!< FLASH Bank1 Busy flag */
<> 144:ef7eb2e8f9f7 532 #define FLASH_FLAG_PGERR FLASH_FLAG_PGERR_BANK1 /*!< FLASH Bank1 Programming error flag */
<> 144:ef7eb2e8f9f7 533 #define FLASH_FLAG_WRPERR FLASH_FLAG_WRPERR_BANK1 /*!< FLASH Bank1 Write protected error flag */
<> 144:ef7eb2e8f9f7 534 #define FLASH_FLAG_EOP FLASH_FLAG_EOP_BANK1 /*!< FLASH Bank1 End of Operation flag */
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 #define FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY /*!< FLASH Bank1 Busy flag */
<> 144:ef7eb2e8f9f7 537 #define FLASH_FLAG_PGERR_BANK1 FLASH_SR_PGERR /*!< FLASH Bank1 Programming error flag */
<> 144:ef7eb2e8f9f7 538 #define FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPRTERR /*!< FLASH Bank1 Write protected error flag */
<> 144:ef7eb2e8f9f7 539 #define FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP /*!< FLASH Bank1 End of Operation flag */
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541 #define FLASH_FLAG_BSY_BANK2 (FLASH_SR2_BSY << 16) /*!< FLASH Bank2 Busy flag */
<> 144:ef7eb2e8f9f7 542 #define FLASH_FLAG_PGERR_BANK2 (FLASH_SR2_PGERR << 16) /*!< FLASH Bank2 Programming error flag */
<> 144:ef7eb2e8f9f7 543 #define FLASH_FLAG_WRPERR_BANK2 (FLASH_SR2_WRPRTERR << 16) /*!< FLASH Bank2 Write protected error flag */
<> 144:ef7eb2e8f9f7 544 #define FLASH_FLAG_EOP_BANK2 (FLASH_SR2_EOP << 16) /*!< FLASH Bank2 End of Operation flag */
<> 144:ef7eb2e8f9f7 545
<> 144:ef7eb2e8f9f7 546 #else
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548 #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
<> 144:ef7eb2e8f9f7 549 #define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */
<> 144:ef7eb2e8f9f7 550 #define FLASH_FLAG_WRPERR FLASH_SR_WRPRTERR /*!< FLASH Write protected error flag */
<> 144:ef7eb2e8f9f7 551 #define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 #endif
<> 144:ef7eb2e8f9f7 554 #define FLASH_FLAG_OPTVERR ((OBR_REG_INDEX << 8 | FLASH_OBR_OPTERR)) /*!< Option Byte Error */
<> 144:ef7eb2e8f9f7 555 /**
<> 144:ef7eb2e8f9f7 556 * @}
<> 144:ef7eb2e8f9f7 557 */
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559 /** @defgroup FLASH_Interrupt_definition Interrupt definition
<> 144:ef7eb2e8f9f7 560 * @brief FLASH Interrupt definition
<> 144:ef7eb2e8f9f7 561 * @{
<> 144:ef7eb2e8f9f7 562 */
<> 144:ef7eb2e8f9f7 563 #if defined(FLASH_BANK2_END)
<> 144:ef7eb2e8f9f7 564 #define FLASH_IT_EOP FLASH_IT_EOP_BANK1 /*!< End of FLASH Operation Interrupt source Bank1 */
<> 144:ef7eb2e8f9f7 565 #define FLASH_IT_ERR FLASH_IT_ERR_BANK1 /*!< Error Interrupt source Bank1 */
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 #define FLASH_IT_EOP_BANK1 FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source Bank1 */
<> 144:ef7eb2e8f9f7 568 #define FLASH_IT_ERR_BANK1 FLASH_CR_ERRIE /*!< Error Interrupt source Bank1 */
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 #define FLASH_IT_EOP_BANK2 (FLASH_CR2_EOPIE << 16) /*!< End of FLASH Operation Interrupt source Bank2 */
<> 144:ef7eb2e8f9f7 571 #define FLASH_IT_ERR_BANK2 (FLASH_CR2_ERRIE << 16) /*!< Error Interrupt source Bank2 */
<> 144:ef7eb2e8f9f7 572
<> 144:ef7eb2e8f9f7 573 #else
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 #define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
<> 144:ef7eb2e8f9f7 576 #define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error Interrupt source */
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 #endif
<> 144:ef7eb2e8f9f7 579 /**
<> 144:ef7eb2e8f9f7 580 * @}
<> 144:ef7eb2e8f9f7 581 */
<> 144:ef7eb2e8f9f7 582
<> 144:ef7eb2e8f9f7 583 /**
<> 144:ef7eb2e8f9f7 584 * @}
<> 144:ef7eb2e8f9f7 585 */
<> 144:ef7eb2e8f9f7 586
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 /**
<> 144:ef7eb2e8f9f7 589 * @}
<> 144:ef7eb2e8f9f7 590 */
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 593 /** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros
<> 144:ef7eb2e8f9f7 594 * @{
<> 144:ef7eb2e8f9f7 595 */
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 /** @defgroup FLASH_Interrupt Interrupt
<> 144:ef7eb2e8f9f7 598 * @brief macros to handle FLASH interrupts
<> 144:ef7eb2e8f9f7 599 * @{
<> 144:ef7eb2e8f9f7 600 */
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 #if defined(FLASH_BANK2_END)
<> 144:ef7eb2e8f9f7 603 /**
<> 144:ef7eb2e8f9f7 604 * @brief Enable the specified FLASH interrupt.
<> 144:ef7eb2e8f9f7 605 * @param __INTERRUPT__ FLASH interrupt
<> 144:ef7eb2e8f9f7 606 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 607 * @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1
<> 144:ef7eb2e8f9f7 608 * @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1
<> 144:ef7eb2e8f9f7 609 * @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2
<> 144:ef7eb2e8f9f7 610 * @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2
<> 144:ef7eb2e8f9f7 611 * @retval none
<> 144:ef7eb2e8f9f7 612 */
<> 144:ef7eb2e8f9f7 613 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { \
<> 144:ef7eb2e8f9f7 614 /* Enable Bank1 IT */ \
<> 144:ef7eb2e8f9f7 615 SET_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFF)); \
<> 144:ef7eb2e8f9f7 616 /* Enable Bank2 IT */ \
<> 144:ef7eb2e8f9f7 617 SET_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16)); \
<> 144:ef7eb2e8f9f7 618 } while(0)
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 /**
<> 144:ef7eb2e8f9f7 621 * @brief Disable the specified FLASH interrupt.
<> 144:ef7eb2e8f9f7 622 * @param __INTERRUPT__ FLASH interrupt
<> 144:ef7eb2e8f9f7 623 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 624 * @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1
<> 144:ef7eb2e8f9f7 625 * @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1
<> 144:ef7eb2e8f9f7 626 * @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2
<> 144:ef7eb2e8f9f7 627 * @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2
<> 144:ef7eb2e8f9f7 628 * @retval none
<> 144:ef7eb2e8f9f7 629 */
<> 144:ef7eb2e8f9f7 630 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { \
<> 144:ef7eb2e8f9f7 631 /* Disable Bank1 IT */ \
<> 144:ef7eb2e8f9f7 632 CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFF)); \
<> 144:ef7eb2e8f9f7 633 /* Disable Bank2 IT */ \
<> 144:ef7eb2e8f9f7 634 CLEAR_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16)); \
<> 144:ef7eb2e8f9f7 635 } while(0)
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 /**
<> 144:ef7eb2e8f9f7 638 * @brief Get the specified FLASH flag status.
<> 144:ef7eb2e8f9f7 639 * @param __FLAG__ specifies the FLASH flag to check.
<> 144:ef7eb2e8f9f7 640 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 641 * @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1
<> 144:ef7eb2e8f9f7 642 * @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1
<> 144:ef7eb2e8f9f7 643 * @arg @ref FLASH_FLAG_PGERR_BANK1 FLASH Programming error flag on bank1
<> 144:ef7eb2e8f9f7 644 * @arg @ref FLASH_FLAG_BSY_BANK1 FLASH Busy flag on bank1
<> 144:ef7eb2e8f9f7 645 * @arg @ref FLASH_FLAG_EOP_BANK2 FLASH End of Operation flag on bank2
<> 144:ef7eb2e8f9f7 646 * @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2
<> 144:ef7eb2e8f9f7 647 * @arg @ref FLASH_FLAG_PGERR_BANK2 FLASH Programming error flag on bank2
<> 144:ef7eb2e8f9f7 648 * @arg @ref FLASH_FLAG_BSY_BANK2 FLASH Busy flag on bank2
<> 144:ef7eb2e8f9f7 649 * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
<> 144:ef7eb2e8f9f7 650 * @retval The new state of __FLAG__ (SET or RESET).
<> 144:ef7eb2e8f9f7 651 */
<> 144:ef7eb2e8f9f7 652 #define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \
<> 144:ef7eb2e8f9f7 653 (FLASH->OBR & FLASH_OBR_OPTERR) : \
<> 144:ef7eb2e8f9f7 654 ((((__FLAG__) & SR_FLAG_MASK) != RESET)? \
<> 144:ef7eb2e8f9f7 655 (FLASH->SR & ((__FLAG__) & SR_FLAG_MASK)) : \
<> 144:ef7eb2e8f9f7 656 (FLASH->SR2 & ((__FLAG__) >> 16))))
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 /**
<> 144:ef7eb2e8f9f7 659 * @brief Clear the specified FLASH flag.
<> 144:ef7eb2e8f9f7 660 * @param __FLAG__ specifies the FLASH flags to clear.
<> 144:ef7eb2e8f9f7 661 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 662 * @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1
<> 144:ef7eb2e8f9f7 663 * @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1
<> 144:ef7eb2e8f9f7 664 * @arg @ref FLASH_FLAG_PGERR_BANK1 FLASH Programming error flag on bank1
<> 144:ef7eb2e8f9f7 665 * @arg @ref FLASH_FLAG_BSY_BANK1 FLASH Busy flag on bank1
<> 144:ef7eb2e8f9f7 666 * @arg @ref FLASH_FLAG_EOP_BANK2 FLASH End of Operation flag on bank2
<> 144:ef7eb2e8f9f7 667 * @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2
<> 144:ef7eb2e8f9f7 668 * @arg @ref FLASH_FLAG_PGERR_BANK2 FLASH Programming error flag on bank2
<> 144:ef7eb2e8f9f7 669 * @arg @ref FLASH_FLAG_BSY_BANK2 FLASH Busy flag on bank2
<> 144:ef7eb2e8f9f7 670 * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
<> 144:ef7eb2e8f9f7 671 * @retval none
<> 144:ef7eb2e8f9f7 672 */
<> 144:ef7eb2e8f9f7 673 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \
<> 144:ef7eb2e8f9f7 674 /* Clear FLASH_FLAG_OPTVERR flag */ \
<> 144:ef7eb2e8f9f7 675 if ((__FLAG__) == FLASH_FLAG_OPTVERR) \
<> 144:ef7eb2e8f9f7 676 { \
<> 144:ef7eb2e8f9f7 677 CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
<> 144:ef7eb2e8f9f7 678 } \
<> 144:ef7eb2e8f9f7 679 else { \
<> 144:ef7eb2e8f9f7 680 /* Clear Flag in Bank1 */ \
<> 144:ef7eb2e8f9f7 681 if (((__FLAG__) & SR_FLAG_MASK) != RESET) \
<> 144:ef7eb2e8f9f7 682 { \
<> 144:ef7eb2e8f9f7 683 FLASH->SR = ((__FLAG__) & SR_FLAG_MASK); \
<> 144:ef7eb2e8f9f7 684 } \
<> 144:ef7eb2e8f9f7 685 /* Clear Flag in Bank2 */ \
<> 144:ef7eb2e8f9f7 686 if (((__FLAG__) >> 16) != RESET) \
<> 144:ef7eb2e8f9f7 687 { \
<> 144:ef7eb2e8f9f7 688 FLASH->SR2 = ((__FLAG__) >> 16); \
<> 144:ef7eb2e8f9f7 689 } \
<> 144:ef7eb2e8f9f7 690 } \
<> 144:ef7eb2e8f9f7 691 } while(0)
<> 144:ef7eb2e8f9f7 692 #else
<> 144:ef7eb2e8f9f7 693 /**
<> 144:ef7eb2e8f9f7 694 * @brief Enable the specified FLASH interrupt.
<> 144:ef7eb2e8f9f7 695 * @param __INTERRUPT__ FLASH interrupt
<> 144:ef7eb2e8f9f7 696 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 697 * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
<> 144:ef7eb2e8f9f7 698 * @arg @ref FLASH_IT_ERR Error Interrupt
<> 144:ef7eb2e8f9f7 699 * @retval none
<> 144:ef7eb2e8f9f7 700 */
<> 144:ef7eb2e8f9f7 701 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 /**
<> 144:ef7eb2e8f9f7 704 * @brief Disable the specified FLASH interrupt.
<> 144:ef7eb2e8f9f7 705 * @param __INTERRUPT__ FLASH interrupt
<> 144:ef7eb2e8f9f7 706 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 707 * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
<> 144:ef7eb2e8f9f7 708 * @arg @ref FLASH_IT_ERR Error Interrupt
<> 144:ef7eb2e8f9f7 709 * @retval none
<> 144:ef7eb2e8f9f7 710 */
<> 144:ef7eb2e8f9f7 711 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 712
<> 144:ef7eb2e8f9f7 713 /**
<> 144:ef7eb2e8f9f7 714 * @brief Get the specified FLASH flag status.
<> 144:ef7eb2e8f9f7 715 * @param __FLAG__ specifies the FLASH flag to check.
<> 144:ef7eb2e8f9f7 716 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 717 * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
<> 144:ef7eb2e8f9f7 718 * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
<> 144:ef7eb2e8f9f7 719 * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag
<> 144:ef7eb2e8f9f7 720 * @arg @ref FLASH_FLAG_BSY FLASH Busy flag
<> 144:ef7eb2e8f9f7 721 * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
<> 144:ef7eb2e8f9f7 722 * @retval The new state of __FLAG__ (SET or RESET).
<> 144:ef7eb2e8f9f7 723 */
<> 144:ef7eb2e8f9f7 724 #define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \
<> 144:ef7eb2e8f9f7 725 (FLASH->OBR & FLASH_OBR_OPTERR) : \
<> 144:ef7eb2e8f9f7 726 (FLASH->SR & (__FLAG__)))
<> 144:ef7eb2e8f9f7 727 /**
<> 144:ef7eb2e8f9f7 728 * @brief Clear the specified FLASH flag.
<> 144:ef7eb2e8f9f7 729 * @param __FLAG__ specifies the FLASH flags to clear.
<> 144:ef7eb2e8f9f7 730 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 731 * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
<> 144:ef7eb2e8f9f7 732 * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
<> 144:ef7eb2e8f9f7 733 * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag
<> 144:ef7eb2e8f9f7 734 * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
<> 144:ef7eb2e8f9f7 735 * @retval none
<> 144:ef7eb2e8f9f7 736 */
<> 144:ef7eb2e8f9f7 737 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \
<> 144:ef7eb2e8f9f7 738 /* Clear FLASH_FLAG_OPTVERR flag */ \
<> 144:ef7eb2e8f9f7 739 if ((__FLAG__) == FLASH_FLAG_OPTVERR) \
<> 144:ef7eb2e8f9f7 740 { \
<> 144:ef7eb2e8f9f7 741 CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
<> 144:ef7eb2e8f9f7 742 } \
<> 144:ef7eb2e8f9f7 743 else { \
<> 144:ef7eb2e8f9f7 744 /* Clear Flag in Bank1 */ \
<> 144:ef7eb2e8f9f7 745 FLASH->SR = (__FLAG__); \
<> 144:ef7eb2e8f9f7 746 } \
<> 144:ef7eb2e8f9f7 747 } while(0)
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749 #endif
<> 144:ef7eb2e8f9f7 750
<> 144:ef7eb2e8f9f7 751 /**
<> 144:ef7eb2e8f9f7 752 * @}
<> 144:ef7eb2e8f9f7 753 */
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 /**
<> 144:ef7eb2e8f9f7 756 * @}
<> 144:ef7eb2e8f9f7 757 */
<> 144:ef7eb2e8f9f7 758
<> 144:ef7eb2e8f9f7 759 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 760 /** @addtogroup FLASHEx_Exported_Functions
<> 144:ef7eb2e8f9f7 761 * @{
<> 144:ef7eb2e8f9f7 762 */
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764 /** @addtogroup FLASHEx_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 765 * @{
<> 144:ef7eb2e8f9f7 766 */
<> 144:ef7eb2e8f9f7 767 /* IO operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 768 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
<> 144:ef7eb2e8f9f7 769 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
<> 144:ef7eb2e8f9f7 770
<> 144:ef7eb2e8f9f7 771 /**
<> 144:ef7eb2e8f9f7 772 * @}
<> 144:ef7eb2e8f9f7 773 */
<> 144:ef7eb2e8f9f7 774
<> 144:ef7eb2e8f9f7 775 /** @addtogroup FLASHEx_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 776 * @{
<> 144:ef7eb2e8f9f7 777 */
<> 144:ef7eb2e8f9f7 778 /* Peripheral Control functions ***********************************************/
<> 144:ef7eb2e8f9f7 779 HAL_StatusTypeDef HAL_FLASHEx_OBErase(void);
<> 144:ef7eb2e8f9f7 780 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
<> 144:ef7eb2e8f9f7 781 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
<> 144:ef7eb2e8f9f7 782 uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress);
<> 144:ef7eb2e8f9f7 783 /**
<> 144:ef7eb2e8f9f7 784 * @}
<> 144:ef7eb2e8f9f7 785 */
<> 144:ef7eb2e8f9f7 786
<> 144:ef7eb2e8f9f7 787 /**
<> 144:ef7eb2e8f9f7 788 * @}
<> 144:ef7eb2e8f9f7 789 */
<> 144:ef7eb2e8f9f7 790
<> 144:ef7eb2e8f9f7 791 /**
<> 144:ef7eb2e8f9f7 792 * @}
<> 144:ef7eb2e8f9f7 793 */
<> 144:ef7eb2e8f9f7 794
<> 144:ef7eb2e8f9f7 795 /**
<> 144:ef7eb2e8f9f7 796 * @}
<> 144:ef7eb2e8f9f7 797 */
<> 144:ef7eb2e8f9f7 798 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 799 }
<> 144:ef7eb2e8f9f7 800 #endif
<> 144:ef7eb2e8f9f7 801
<> 144:ef7eb2e8f9f7 802 #endif /* __STM32F1xx_HAL_FLASH_EX_H */
<> 144:ef7eb2e8f9f7 803
<> 144:ef7eb2e8f9f7 804 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/