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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_can.h@150:cd63f849362a, 2016-11-03 (annotated)

Committer:
ptpaterson
Date:
Thu Nov 03 16:21:53 2016 +0000
Revision:
150:cd63f849362a
Parent:
149:156823d33999 
targets LPC11Cxx, LPC15xx:  can_api can_filter function properly returns 0 if handle argument is out of bounds (handle > 32).

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_can.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.0.4
<> 144:ef7eb2e8f9f7 6 * @date 29-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of CAN HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __stm32f1xx_CAN_H
<> 144:ef7eb2e8f9f7 40 #define __stm32f1xx_CAN_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
<> 144:ef7eb2e8f9f7 47 defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 50 #include "stm32f1xx_hal_def.h"
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 53 * @{
<> 144:ef7eb2e8f9f7 54 */
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /** @addtogroup CAN
<> 144:ef7eb2e8f9f7 57 * @{
<> 144:ef7eb2e8f9f7 58 */
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 61 /** @defgroup CAN_Exported_Types CAN Exported Types
<> 144:ef7eb2e8f9f7 62 * @{
<> 144:ef7eb2e8f9f7 63 */
<> 144:ef7eb2e8f9f7 64 /**
<> 144:ef7eb2e8f9f7 65 * @brief HAL State structures definition
<> 144:ef7eb2e8f9f7 66 */
<> 144:ef7eb2e8f9f7 67 typedef enum
<> 144:ef7eb2e8f9f7 68 {
<> 144:ef7eb2e8f9f7 69 HAL_CAN_STATE_RESET = 0x00, /*!< CAN not yet initialized or disabled */
<> 144:ef7eb2e8f9f7 70 HAL_CAN_STATE_READY = 0x01, /*!< CAN initialized and ready for use */
<> 144:ef7eb2e8f9f7 71 HAL_CAN_STATE_BUSY = 0x02, /*!< CAN process is ongoing */
<> 144:ef7eb2e8f9f7 72 HAL_CAN_STATE_BUSY_TX = 0x12, /*!< CAN process is ongoing */
<> 144:ef7eb2e8f9f7 73 HAL_CAN_STATE_BUSY_RX = 0x22, /*!< CAN process is ongoing */
<> 144:ef7eb2e8f9f7 74 HAL_CAN_STATE_BUSY_TX_RX = 0x32, /*!< CAN process is ongoing */
<> 144:ef7eb2e8f9f7 75 HAL_CAN_STATE_TIMEOUT = 0x03, /*!< CAN in Timeout state */
<> 144:ef7eb2e8f9f7 76 HAL_CAN_STATE_ERROR = 0x04 /*!< CAN error state */
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 }HAL_CAN_StateTypeDef;
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 /**
<> 144:ef7eb2e8f9f7 82 * @brief CAN init structure definition
<> 144:ef7eb2e8f9f7 83 */
<> 144:ef7eb2e8f9f7 84 typedef struct
<> 144:ef7eb2e8f9f7 85 {
<> 144:ef7eb2e8f9f7 86 uint32_t Prescaler; /*!< Specifies the length of a time quantum.
<> 144:ef7eb2e8f9f7 87 This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 uint32_t Mode; /*!< Specifies the CAN operating mode.
<> 144:ef7eb2e8f9f7 90 This parameter can be a value of @ref CAN_operating_mode */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 uint32_t SJW; /*!< Specifies the maximum number of time quanta
<> 144:ef7eb2e8f9f7 93 the CAN hardware is allowed to lengthen or
<> 144:ef7eb2e8f9f7 94 shorten a bit to perform resynchronization.
<> 144:ef7eb2e8f9f7 95 This parameter can be a value of @ref CAN_synchronisation_jump_width */
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
<> 144:ef7eb2e8f9f7 98 This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
<> 144:ef7eb2e8f9f7 101 This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
<> 144:ef7eb2e8f9f7 104 This parameter can be set to ENABLE or DISABLE. */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
<> 144:ef7eb2e8f9f7 107 This parameter can be set to ENABLE or DISABLE. */
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
<> 144:ef7eb2e8f9f7 110 This parameter can be set to ENABLE or DISABLE. */
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
<> 144:ef7eb2e8f9f7 113 This parameter can be set to ENABLE or DISABLE. */
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 uint32_t RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
<> 144:ef7eb2e8f9f7 116 This parameter can be set to ENABLE or DISABLE. */
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
<> 144:ef7eb2e8f9f7 119 This parameter can be set to ENABLE or DISABLE. */
<> 144:ef7eb2e8f9f7 120 }CAN_InitTypeDef;
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 /**
<> 144:ef7eb2e8f9f7 123 * @brief CAN Tx message structure definition
<> 144:ef7eb2e8f9f7 124 */
<> 144:ef7eb2e8f9f7 125 typedef struct
<> 144:ef7eb2e8f9f7 126 {
<> 144:ef7eb2e8f9f7 127 uint32_t StdId; /*!< Specifies the standard identifier.
<> 144:ef7eb2e8f9f7 128 This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 uint32_t ExtId; /*!< Specifies the extended identifier.
<> 144:ef7eb2e8f9f7 131 This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
<> 144:ef7eb2e8f9f7 134 This parameter can be a value of @ref CAN_identifier_type */
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
<> 144:ef7eb2e8f9f7 137 This parameter can be a value of @ref CAN_remote_transmission_request */
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
<> 144:ef7eb2e8f9f7 140 This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 uint8_t Data[8]; /*!< Contains the data to be transmitted.
<> 144:ef7eb2e8f9f7 143 This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 }CanTxMsgTypeDef;
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 /**
<> 144:ef7eb2e8f9f7 148 * @brief CAN Rx message structure definition
<> 144:ef7eb2e8f9f7 149 */
<> 144:ef7eb2e8f9f7 150 typedef struct
<> 144:ef7eb2e8f9f7 151 {
<> 144:ef7eb2e8f9f7 152 uint32_t StdId; /*!< Specifies the standard identifier.
<> 144:ef7eb2e8f9f7 153 This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 uint32_t ExtId; /*!< Specifies the extended identifier.
<> 144:ef7eb2e8f9f7 156 This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
<> 144:ef7eb2e8f9f7 159 This parameter can be a value of @ref CAN_identifier_type */
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 uint32_t RTR; /*!< Specifies the type of frame for the received message.
<> 144:ef7eb2e8f9f7 162 This parameter can be a value of @ref CAN_remote_transmission_request */
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 uint32_t DLC; /*!< Specifies the length of the frame that will be received.
<> 144:ef7eb2e8f9f7 165 This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 uint8_t Data[8]; /*!< Contains the data to be received.
<> 144:ef7eb2e8f9f7 168 This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
<> 144:ef7eb2e8f9f7 171 This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
<> 144:ef7eb2e8f9f7 174 This parameter can be a value of @ref CAN_receive_FIFO_number_constants */
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 }CanRxMsgTypeDef;
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 /**
<> 144:ef7eb2e8f9f7 179 * @brief CAN handle Structure definition
<> 144:ef7eb2e8f9f7 180 */
<> 144:ef7eb2e8f9f7 181 typedef struct
<> 144:ef7eb2e8f9f7 182 {
<> 144:ef7eb2e8f9f7 183 CAN_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 CAN_InitTypeDef Init; /*!< CAN required parameters */
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure */
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 HAL_LockTypeDef Lock; /*!< CAN locking object */
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 __IO uint32_t ErrorCode; /*!< CAN Error code */
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 }CAN_HandleTypeDef;
<> 144:ef7eb2e8f9f7 198 /**
<> 144:ef7eb2e8f9f7 199 * @}
<> 144:ef7eb2e8f9f7 200 */
<> 144:ef7eb2e8f9f7 201 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /** @defgroup CAN_Exported_Constants CAN Exported Constants
<> 144:ef7eb2e8f9f7 204 * @{
<> 144:ef7eb2e8f9f7 205 */
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /** @defgroup CAN_Error_Code CAN Error Code
<> 144:ef7eb2e8f9f7 208 * @{
<> 144:ef7eb2e8f9f7 209 */
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 #define HAL_CAN_ERROR_NONE ((uint32_t)0x00) /*!< No error */
<> 144:ef7eb2e8f9f7 213 #define HAL_CAN_ERROR_EWG ((uint32_t)0x01) /*!< EWG error */
<> 144:ef7eb2e8f9f7 214 #define HAL_CAN_ERROR_EPV ((uint32_t)0x02) /*!< EPV error */
<> 144:ef7eb2e8f9f7 215 #define HAL_CAN_ERROR_BOF ((uint32_t)0x04) /*!< BOF error */
<> 144:ef7eb2e8f9f7 216 #define HAL_CAN_ERROR_STF ((uint32_t)0x08) /*!< Stuff error */
<> 144:ef7eb2e8f9f7 217 #define HAL_CAN_ERROR_FOR ((uint32_t)0x10) /*!< Form error */
<> 144:ef7eb2e8f9f7 218 #define HAL_CAN_ERROR_ACK ((uint32_t)0x20) /*!< Acknowledgment error */
<> 144:ef7eb2e8f9f7 219 #define HAL_CAN_ERROR_BR ((uint32_t)0x40) /*!< Bit recessive */
<> 144:ef7eb2e8f9f7 220 #define HAL_CAN_ERROR_BD ((uint32_t)0x80) /*!< LEC dominant */
<> 144:ef7eb2e8f9f7 221 #define HAL_CAN_ERROR_CRC ((uint32_t)0x100) /*!< LEC transfer error */
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 /**
<> 144:ef7eb2e8f9f7 225 * @}
<> 144:ef7eb2e8f9f7 226 */
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /** @defgroup CAN_InitStatus CAN initialization Status
<> 144:ef7eb2e8f9f7 230 * @{
<> 144:ef7eb2e8f9f7 231 */
<> 144:ef7eb2e8f9f7 232 #define CAN_INITSTATUS_FAILED ((uint32_t)0x00000000) /*!< CAN initialization failed */
<> 144:ef7eb2e8f9f7 233 #define CAN_INITSTATUS_SUCCESS ((uint32_t)0x00000001) /*!< CAN initialization OK */
<> 144:ef7eb2e8f9f7 234 /**
<> 144:ef7eb2e8f9f7 235 * @}
<> 144:ef7eb2e8f9f7 236 */
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 /** @defgroup CAN_operating_mode CAN Operating Mode
<> 144:ef7eb2e8f9f7 239 * @{
<> 144:ef7eb2e8f9f7 240 */
<> 144:ef7eb2e8f9f7 241 #define CAN_MODE_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
<> 144:ef7eb2e8f9f7 242 #define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
<> 144:ef7eb2e8f9f7 243 #define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
<> 144:ef7eb2e8f9f7 244 #define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /**
<> 144:ef7eb2e8f9f7 247 * @}
<> 144:ef7eb2e8f9f7 248 */
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
<> 144:ef7eb2e8f9f7 252 * @{
<> 144:ef7eb2e8f9f7 253 */
<> 144:ef7eb2e8f9f7 254 #define CAN_SJW_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
<> 144:ef7eb2e8f9f7 255 #define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
<> 144:ef7eb2e8f9f7 256 #define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
<> 144:ef7eb2e8f9f7 257 #define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /**
<> 144:ef7eb2e8f9f7 260 * @}
<> 144:ef7eb2e8f9f7 261 */
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
<> 144:ef7eb2e8f9f7 264 * @{
<> 144:ef7eb2e8f9f7 265 */
<> 144:ef7eb2e8f9f7 266 #define CAN_BS1_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
<> 144:ef7eb2e8f9f7 267 #define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
<> 144:ef7eb2e8f9f7 268 #define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
<> 144:ef7eb2e8f9f7 269 #define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
<> 144:ef7eb2e8f9f7 270 #define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
<> 144:ef7eb2e8f9f7 271 #define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
<> 144:ef7eb2e8f9f7 272 #define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
<> 144:ef7eb2e8f9f7 273 #define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
<> 144:ef7eb2e8f9f7 274 #define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
<> 144:ef7eb2e8f9f7 275 #define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
<> 144:ef7eb2e8f9f7 276 #define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
<> 144:ef7eb2e8f9f7 277 #define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
<> 144:ef7eb2e8f9f7 278 #define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
<> 144:ef7eb2e8f9f7 279 #define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
<> 144:ef7eb2e8f9f7 280 #define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
<> 144:ef7eb2e8f9f7 281 #define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /**
<> 144:ef7eb2e8f9f7 284 * @}
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 /** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
<> 144:ef7eb2e8f9f7 288 * @{
<> 144:ef7eb2e8f9f7 289 */
<> 144:ef7eb2e8f9f7 290 #define CAN_BS2_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
<> 144:ef7eb2e8f9f7 291 #define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
<> 144:ef7eb2e8f9f7 292 #define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
<> 144:ef7eb2e8f9f7 293 #define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
<> 144:ef7eb2e8f9f7 294 #define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
<> 144:ef7eb2e8f9f7 295 #define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
<> 144:ef7eb2e8f9f7 296 #define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
<> 144:ef7eb2e8f9f7 297 #define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 /**
<> 144:ef7eb2e8f9f7 300 * @}
<> 144:ef7eb2e8f9f7 301 */
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /** @defgroup CAN_filter_mode CAN Filter Mode
<> 144:ef7eb2e8f9f7 304 * @{
<> 144:ef7eb2e8f9f7 305 */
<> 144:ef7eb2e8f9f7 306 #define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */
<> 144:ef7eb2e8f9f7 307 #define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /**
<> 144:ef7eb2e8f9f7 310 * @}
<> 144:ef7eb2e8f9f7 311 */
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 /** @defgroup CAN_filter_scale CAN Filter Scale
<> 144:ef7eb2e8f9f7 314 * @{
<> 144:ef7eb2e8f9f7 315 */
<> 144:ef7eb2e8f9f7 316 #define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
<> 144:ef7eb2e8f9f7 317 #define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /**
<> 144:ef7eb2e8f9f7 320 * @}
<> 144:ef7eb2e8f9f7 321 */
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 /** @defgroup CAN_filter_FIFO CAN Filter FIFO
<> 144:ef7eb2e8f9f7 324 * @{
<> 144:ef7eb2e8f9f7 325 */
<> 144:ef7eb2e8f9f7 326 #define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
<> 144:ef7eb2e8f9f7 327 #define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /**
<> 144:ef7eb2e8f9f7 331 * @}
<> 144:ef7eb2e8f9f7 332 */
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /** @defgroup CAN_identifier_type CAN Identifier Type
<> 144:ef7eb2e8f9f7 335 * @{
<> 144:ef7eb2e8f9f7 336 */
<> 144:ef7eb2e8f9f7 337 #define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */
<> 144:ef7eb2e8f9f7 338 #define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 /**
<> 144:ef7eb2e8f9f7 341 * @}
<> 144:ef7eb2e8f9f7 342 */
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 /** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
<> 144:ef7eb2e8f9f7 345 * @{
<> 144:ef7eb2e8f9f7 346 */
<> 144:ef7eb2e8f9f7 347 #define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */
<> 144:ef7eb2e8f9f7 348 #define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 /**
<> 144:ef7eb2e8f9f7 351 * @}
<> 144:ef7eb2e8f9f7 352 */
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 /** @defgroup CAN_transmit_constants CAN Transmit Constants
<> 144:ef7eb2e8f9f7 355 * @{
<> 144:ef7eb2e8f9f7 356 */
<> 144:ef7eb2e8f9f7 357 #define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 /**
<> 144:ef7eb2e8f9f7 360 * @}
<> 144:ef7eb2e8f9f7 361 */
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number
<> 144:ef7eb2e8f9f7 364 * @{
<> 144:ef7eb2e8f9f7 365 */
<> 144:ef7eb2e8f9f7 366 #define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
<> 144:ef7eb2e8f9f7 367 #define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 /**
<> 144:ef7eb2e8f9f7 370 * @}
<> 144:ef7eb2e8f9f7 371 */
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 /** @defgroup CAN_flags CAN Flags
<> 144:ef7eb2e8f9f7 374 * @{
<> 144:ef7eb2e8f9f7 375 */
<> 144:ef7eb2e8f9f7 376 /* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
<> 144:ef7eb2e8f9f7 377 and CAN_ClearFlag() functions. */
<> 144:ef7eb2e8f9f7 378 /* If the flag is 0x1XXXXXXX, it means that it can only be used with
<> 144:ef7eb2e8f9f7 379 CAN_GetFlagStatus() function. */
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 /* Transmit Flags */
<> 144:ef7eb2e8f9f7 382 #define CAN_FLAG_RQCP0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP0_BIT_POSITION)) /*!< Request MailBox0 flag */
<> 144:ef7eb2e8f9f7 383 #define CAN_FLAG_RQCP1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP1_BIT_POSITION)) /*!< Request MailBox1 flag */
<> 144:ef7eb2e8f9f7 384 #define CAN_FLAG_RQCP2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP2_BIT_POSITION)) /*!< Request MailBox2 flag */
<> 144:ef7eb2e8f9f7 385 #define CAN_FLAG_TXOK0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK0_BIT_POSITION)) /*!< Transmission OK MailBox0 flag */
<> 144:ef7eb2e8f9f7 386 #define CAN_FLAG_TXOK1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK1_BIT_POSITION)) /*!< Transmission OK MailBox1 flag */
<> 144:ef7eb2e8f9f7 387 #define CAN_FLAG_TXOK2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP0_BIT_POSITION)) /*!< Transmission OK MailBox2 flag */
<> 144:ef7eb2e8f9f7 388 #define CAN_FLAG_TME0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME0_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */
<> 144:ef7eb2e8f9f7 389 #define CAN_FLAG_TME1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME1_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */
<> 144:ef7eb2e8f9f7 390 #define CAN_FLAG_TME2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME2_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 /* Receive Flags */
<> 144:ef7eb2e8f9f7 393 #define CAN_FLAG_FF0 ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FF0_BIT_POSITION)) /*!< FIFO 0 Full flag */
<> 144:ef7eb2e8f9f7 394 #define CAN_FLAG_FOV0 ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FOV0_BIT_POSITION)) /*!< FIFO 0 Overrun flag */
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 #define CAN_FLAG_FF1 ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FF1_BIT_POSITION)) /*!< FIFO 1 Full flag */
<> 144:ef7eb2e8f9f7 397 #define CAN_FLAG_FOV1 ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FOV1_BIT_POSITION)) /*!< FIFO 1 Overrun flag */
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 /* Operating Mode Flags */
<> 144:ef7eb2e8f9f7 400 #define CAN_FLAG_WKU ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_WKU_BIT_POSITION)) /*!< Wake up flag */
<> 144:ef7eb2e8f9f7 401 #define CAN_FLAG_SLAK ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAK_BIT_POSITION)) /*!< Sleep acknowledge flag */
<> 144:ef7eb2e8f9f7 402 #define CAN_FLAG_SLAKI ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAKI_BIT_POSITION)) /*!< Sleep acknowledge flag */
<> 144:ef7eb2e8f9f7 403 /* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
<> 144:ef7eb2e8f9f7 404 In this case the SLAK bit can be polled.*/
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 /* Error Flags */
<> 144:ef7eb2e8f9f7 407 #define CAN_FLAG_EWG ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EWG_BIT_POSITION)) /*!< Error warning flag */
<> 144:ef7eb2e8f9f7 408 #define CAN_FLAG_EPV ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EPV_BIT_POSITION)) /*!< Error passive flag */
<> 144:ef7eb2e8f9f7 409 #define CAN_FLAG_BOF ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_BOF_BIT_POSITION)) /*!< Bus-Off flag */
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 /**
<> 144:ef7eb2e8f9f7 412 * @}
<> 144:ef7eb2e8f9f7 413 */
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 /** @defgroup CAN_interrupts CAN Interrupts
<> 144:ef7eb2e8f9f7 417 * @{
<> 144:ef7eb2e8f9f7 418 */
<> 144:ef7eb2e8f9f7 419 #define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 /* Receive Interrupts */
<> 144:ef7eb2e8f9f7 422 #define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
<> 144:ef7eb2e8f9f7 423 #define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
<> 144:ef7eb2e8f9f7 424 #define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
<> 144:ef7eb2e8f9f7 425 #define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
<> 144:ef7eb2e8f9f7 426 #define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
<> 144:ef7eb2e8f9f7 427 #define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /* Operating Mode Interrupts */
<> 144:ef7eb2e8f9f7 430 #define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
<> 144:ef7eb2e8f9f7 431 #define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 /* Error Interrupts */
<> 144:ef7eb2e8f9f7 434 #define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
<> 144:ef7eb2e8f9f7 435 #define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
<> 144:ef7eb2e8f9f7 436 #define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
<> 144:ef7eb2e8f9f7 437 #define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
<> 144:ef7eb2e8f9f7 438 #define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 /**
<> 144:ef7eb2e8f9f7 442 * @}
<> 144:ef7eb2e8f9f7 443 */
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 /**
<> 144:ef7eb2e8f9f7 448 * @}
<> 144:ef7eb2e8f9f7 449 */
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 /** @defgroup CAN_Private_Constants CAN Private Constants
<> 144:ef7eb2e8f9f7 452 * @{
<> 144:ef7eb2e8f9f7 453 */
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 /* CAN intermediate shift values used for CAN flags */
<> 144:ef7eb2e8f9f7 456 #define TSR_REGISTER_INDEX ((uint32_t)0x5)
<> 144:ef7eb2e8f9f7 457 #define RF0R_REGISTER_INDEX ((uint32_t)0x2)
<> 144:ef7eb2e8f9f7 458 #define RF1R_REGISTER_INDEX ((uint32_t)0x4)
<> 144:ef7eb2e8f9f7 459 #define MSR_REGISTER_INDEX ((uint32_t)0x1)
<> 144:ef7eb2e8f9f7 460 #define ESR_REGISTER_INDEX ((uint32_t)0x3)
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 /* CAN flags bits position into their respective register (TSR, RF0R, RF1R or MSR regsiters) */
<> 144:ef7eb2e8f9f7 463 /* Transmit Flags */
<> 144:ef7eb2e8f9f7 464 #define CAN_TSR_RQCP0_BIT_POSITION ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 465 #define CAN_TSR_RQCP1_BIT_POSITION ((uint32_t)0x00000008)
<> 144:ef7eb2e8f9f7 466 #define CAN_TSR_RQCP2_BIT_POSITION ((uint32_t)0x00000010)
<> 144:ef7eb2e8f9f7 467 #define CAN_TSR_TXOK0_BIT_POSITION ((uint32_t)0x00000001)
<> 144:ef7eb2e8f9f7 468 #define CAN_TSR_TXOK1_BIT_POSITION ((uint32_t)0x00000009)
<> 144:ef7eb2e8f9f7 469 #define CAN_TSR_TXOK2_BIT_POSITION ((uint32_t)0x00000011)
<> 144:ef7eb2e8f9f7 470 #define CAN_TSR_TME0_BIT_POSITION ((uint32_t)0x0000001A)
<> 144:ef7eb2e8f9f7 471 #define CAN_TSR_TME1_BIT_POSITION ((uint32_t)0x0000001B)
<> 144:ef7eb2e8f9f7 472 #define CAN_TSR_TME2_BIT_POSITION ((uint32_t)0x0000001C)
<> 144:ef7eb2e8f9f7 473
<> 144:ef7eb2e8f9f7 474 /* Receive Flags */
<> 144:ef7eb2e8f9f7 475 #define CAN_RF0R_FF0_BIT_POSITION ((uint32_t)0x00000003)
<> 144:ef7eb2e8f9f7 476 #define CAN_RF0R_FOV0_BIT_POSITION ((uint32_t)0x00000004)
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 #define CAN_RF1R_FF1_BIT_POSITION ((uint32_t)0x00000003)
<> 144:ef7eb2e8f9f7 479 #define CAN_RF1R_FOV1_BIT_POSITION ((uint32_t)0x00000004)
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 /* Operating Mode Flags */
<> 144:ef7eb2e8f9f7 482 #define CAN_MSR_WKU_BIT_POSITION ((uint32_t)0x00000003)
<> 144:ef7eb2e8f9f7 483 #define CAN_MSR_SLAK_BIT_POSITION ((uint32_t)0x00000001)
<> 144:ef7eb2e8f9f7 484 #define CAN_MSR_SLAKI_BIT_POSITION ((uint32_t)0x00000004)
<> 144:ef7eb2e8f9f7 485
<> 144:ef7eb2e8f9f7 486 /* Error Flags */
<> 144:ef7eb2e8f9f7 487 #define CAN_ESR_EWG_BIT_POSITION ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 488 #define CAN_ESR_EPV_BIT_POSITION ((uint32_t)0x00000001)
<> 144:ef7eb2e8f9f7 489 #define CAN_ESR_BOF_BIT_POSITION ((uint32_t)0x00000002)
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 /* Mask used by macro to get/clear CAN flags*/
<> 144:ef7eb2e8f9f7 492 #define CAN_FLAG_MASK ((uint32_t)0x000000FF)
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 /* Mailboxes definition */
<> 144:ef7eb2e8f9f7 495 #define CAN_TXMAILBOX_0 ((uint8_t)0x00)
<> 144:ef7eb2e8f9f7 496 #define CAN_TXMAILBOX_1 ((uint8_t)0x01)
<> 144:ef7eb2e8f9f7 497 #define CAN_TXMAILBOX_2 ((uint8_t)0x02)
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 /**
<> 144:ef7eb2e8f9f7 501 * @}
<> 144:ef7eb2e8f9f7 502 */
<> 144:ef7eb2e8f9f7 503
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 506 /** @defgroup CAN_Exported_Macro CAN Exported Macros
<> 144:ef7eb2e8f9f7 507 * @{
<> 144:ef7eb2e8f9f7 508 */
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 /** @brief Reset CAN handle state
<> 144:ef7eb2e8f9f7 511 * @param __HANDLE__: CAN handle.
<> 144:ef7eb2e8f9f7 512 * @retval None
<> 144:ef7eb2e8f9f7 513 */
<> 144:ef7eb2e8f9f7 514 #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
<> 144:ef7eb2e8f9f7 515
<> 144:ef7eb2e8f9f7 516 /**
<> 144:ef7eb2e8f9f7 517 * @brief Enable the specified CAN interrupts
<> 144:ef7eb2e8f9f7 518 * @param __HANDLE__: CAN handle.
<> 144:ef7eb2e8f9f7 519 * @param __INTERRUPT__: CAN Interrupt.
<> 144:ef7eb2e8f9f7 520 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 521 * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
<> 144:ef7eb2e8f9f7 522 * @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
<> 144:ef7eb2e8f9f7 523 * @arg CAN_IT_FF0 : FIFO 0 full interrupt
<> 144:ef7eb2e8f9f7 524 * @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
<> 144:ef7eb2e8f9f7 525 * @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
<> 144:ef7eb2e8f9f7 526 * @arg CAN_IT_FF1 : FIFO 1 full interrupt
<> 144:ef7eb2e8f9f7 527 * @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
<> 144:ef7eb2e8f9f7 528 * @arg CAN_IT_WKU : Wake-up interrupt
<> 144:ef7eb2e8f9f7 529 * @arg CAN_IT_SLK : Sleep acknowledge interrupt
<> 144:ef7eb2e8f9f7 530 * @arg CAN_IT_EWG : Error warning interrupt
<> 144:ef7eb2e8f9f7 531 * @arg CAN_IT_EPV : Error passive interrupt
<> 144:ef7eb2e8f9f7 532 * @arg CAN_IT_BOF : Bus-off interrupt
<> 144:ef7eb2e8f9f7 533 * @arg CAN_IT_LEC : Last error code interrupt
<> 144:ef7eb2e8f9f7 534 * @arg CAN_IT_ERR : Error Interrupt
<> 144:ef7eb2e8f9f7 535 * @retval None.
<> 144:ef7eb2e8f9f7 536 */
<> 144:ef7eb2e8f9f7 537 #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 /**
<> 144:ef7eb2e8f9f7 540 * @brief Disable the specified CAN interrupts
<> 144:ef7eb2e8f9f7 541 * @param __HANDLE__: CAN handle.
<> 144:ef7eb2e8f9f7 542 * @param __INTERRUPT__: CAN Interrupt.
<> 144:ef7eb2e8f9f7 543 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 544 * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
<> 144:ef7eb2e8f9f7 545 * @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
<> 144:ef7eb2e8f9f7 546 * @arg CAN_IT_FF0 : FIFO 0 full interrupt
<> 144:ef7eb2e8f9f7 547 * @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
<> 144:ef7eb2e8f9f7 548 * @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
<> 144:ef7eb2e8f9f7 549 * @arg CAN_IT_FF1 : FIFO 1 full interrupt
<> 144:ef7eb2e8f9f7 550 * @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
<> 144:ef7eb2e8f9f7 551 * @arg CAN_IT_WKU : Wake-up interrupt
<> 144:ef7eb2e8f9f7 552 * @arg CAN_IT_SLK : Sleep acknowledge interrupt
<> 144:ef7eb2e8f9f7 553 * @arg CAN_IT_EWG : Error warning interrupt
<> 144:ef7eb2e8f9f7 554 * @arg CAN_IT_EPV : Error passive interrupt
<> 144:ef7eb2e8f9f7 555 * @arg CAN_IT_BOF : Bus-off interrupt
<> 144:ef7eb2e8f9f7 556 * @arg CAN_IT_LEC : Last error code interrupt
<> 144:ef7eb2e8f9f7 557 * @arg CAN_IT_ERR : Error Interrupt
<> 144:ef7eb2e8f9f7 558 * @retval None.
<> 144:ef7eb2e8f9f7 559 */
<> 144:ef7eb2e8f9f7 560 #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 /**
<> 144:ef7eb2e8f9f7 563 * @brief Return the number of pending received messages.
<> 144:ef7eb2e8f9f7 564 * @param __HANDLE__: CAN handle.
<> 144:ef7eb2e8f9f7 565 * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
<> 144:ef7eb2e8f9f7 566 * @retval The number of pending message.
<> 144:ef7eb2e8f9f7 567 */
<> 144:ef7eb2e8f9f7 568 #define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
<> 144:ef7eb2e8f9f7 569 ((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03)))
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 /** @brief Check whether the specified CAN flag is set or not.
<> 144:ef7eb2e8f9f7 572 * @param __HANDLE__: specifies the CAN Handle.
<> 144:ef7eb2e8f9f7 573 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 574 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 575 * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
<> 144:ef7eb2e8f9f7 576 * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
<> 144:ef7eb2e8f9f7 577 * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
<> 144:ef7eb2e8f9f7 578 * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
<> 144:ef7eb2e8f9f7 579 * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
<> 144:ef7eb2e8f9f7 580 * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
<> 144:ef7eb2e8f9f7 581 * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
<> 144:ef7eb2e8f9f7 582 * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
<> 144:ef7eb2e8f9f7 583 * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
<> 144:ef7eb2e8f9f7 584 * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
<> 144:ef7eb2e8f9f7 585 * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
<> 144:ef7eb2e8f9f7 586 * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
<> 144:ef7eb2e8f9f7 587 * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
<> 144:ef7eb2e8f9f7 588 * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
<> 144:ef7eb2e8f9f7 589 * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
<> 144:ef7eb2e8f9f7 590 * @arg CAN_FLAG_WKU: Wake up Flag
<> 144:ef7eb2e8f9f7 591 * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
<> 144:ef7eb2e8f9f7 592 * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
<> 144:ef7eb2e8f9f7 593 * @arg CAN_FLAG_EWG: Error Warning Flag
<> 144:ef7eb2e8f9f7 594 * @arg CAN_FLAG_EPV: Error Passive Flag
<> 144:ef7eb2e8f9f7 595 * @arg CAN_FLAG_BOF: Bus-Off Flag
<> 144:ef7eb2e8f9f7 596 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 597 */
<> 144:ef7eb2e8f9f7 598 #define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
<> 144:ef7eb2e8f9f7 599 ((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
<> 144:ef7eb2e8f9f7 600 (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
<> 144:ef7eb2e8f9f7 601 (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
<> 144:ef7eb2e8f9f7 602 (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
<> 144:ef7eb2e8f9f7 603 ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
<> 144:ef7eb2e8f9f7 604
<> 144:ef7eb2e8f9f7 605 /** @brief Clear the specified CAN pending flag.
<> 144:ef7eb2e8f9f7 606 * @param __HANDLE__: specifies the CAN Handle.
<> 144:ef7eb2e8f9f7 607 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 608 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 609 * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
<> 144:ef7eb2e8f9f7 610 * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
<> 144:ef7eb2e8f9f7 611 * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
<> 144:ef7eb2e8f9f7 612 * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
<> 144:ef7eb2e8f9f7 613 * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
<> 144:ef7eb2e8f9f7 614 * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
<> 144:ef7eb2e8f9f7 615 * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
<> 144:ef7eb2e8f9f7 616 * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
<> 144:ef7eb2e8f9f7 617 * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
<> 144:ef7eb2e8f9f7 618 * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
<> 144:ef7eb2e8f9f7 619 * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
<> 144:ef7eb2e8f9f7 620 * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
<> 144:ef7eb2e8f9f7 621 * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
<> 144:ef7eb2e8f9f7 622 * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
<> 144:ef7eb2e8f9f7 623 * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
<> 144:ef7eb2e8f9f7 624 * @arg CAN_FLAG_WKU: Wake up Flag
<> 144:ef7eb2e8f9f7 625 * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
<> 144:ef7eb2e8f9f7 626 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 627 */
<> 144:ef7eb2e8f9f7 628 #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
<> 144:ef7eb2e8f9f7 629 ((((__FLAG__) >> 8U) == TSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
<> 144:ef7eb2e8f9f7 630 (((__FLAG__) >> 8U) == RF0R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
<> 144:ef7eb2e8f9f7 631 (((__FLAG__) >> 8U) == RF1R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
<> 144:ef7eb2e8f9f7 632 (((__FLAG__) >> 8U) == MSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0)
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 /** @brief Check if the specified CAN interrupt source is enabled or disabled.
<> 144:ef7eb2e8f9f7 636 * @param __HANDLE__: specifies the CAN Handle.
<> 144:ef7eb2e8f9f7 637 * @param __INTERRUPT__: specifies the CAN interrupt source to check.
<> 144:ef7eb2e8f9f7 638 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 639 * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
<> 144:ef7eb2e8f9f7 640 * @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
<> 144:ef7eb2e8f9f7 641 * @arg CAN_IT_FF0 : FIFO 0 full interrupt
<> 144:ef7eb2e8f9f7 642 * @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
<> 144:ef7eb2e8f9f7 643 * @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
<> 144:ef7eb2e8f9f7 644 * @arg CAN_IT_FF1 : FIFO 1 full interrupt
<> 144:ef7eb2e8f9f7 645 * @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
<> 144:ef7eb2e8f9f7 646 * @arg CAN_IT_WKU : Wake-up interrupt
<> 144:ef7eb2e8f9f7 647 * @arg CAN_IT_SLK : Sleep acknowledge interrupt
<> 144:ef7eb2e8f9f7 648 * @arg CAN_IT_EWG : Error warning interrupt
<> 144:ef7eb2e8f9f7 649 * @arg CAN_IT_EPV : Error passive interrupt
<> 144:ef7eb2e8f9f7 650 * @arg CAN_IT_BOF : Bus-off interrupt
<> 144:ef7eb2e8f9f7 651 * @arg CAN_IT_LEC : Last error code interrupt
<> 144:ef7eb2e8f9f7 652 * @arg CAN_IT_ERR : Error Interrupt
<> 144:ef7eb2e8f9f7 653 * @retval The new state of __IT__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 654 */
<> 144:ef7eb2e8f9f7 655 #define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 144:ef7eb2e8f9f7 656
<> 144:ef7eb2e8f9f7 657 /**
<> 144:ef7eb2e8f9f7 658 * @brief Check the transmission status of a CAN Frame.
<> 144:ef7eb2e8f9f7 659 * @param __HANDLE__: specifies the CAN Handle.
<> 144:ef7eb2e8f9f7 660 * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
<> 144:ef7eb2e8f9f7 661 * @retval The new status of transmission (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 662 */
<> 144:ef7eb2e8f9f7 663 #define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
<> 144:ef7eb2e8f9f7 664 (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
<> 144:ef7eb2e8f9f7 665 ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
<> 144:ef7eb2e8f9f7 666 ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668 /**
<> 144:ef7eb2e8f9f7 669 * @brief Release the specified receive FIFO.
<> 144:ef7eb2e8f9f7 670 * @param __HANDLE__: CAN handle.
<> 144:ef7eb2e8f9f7 671 * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
<> 144:ef7eb2e8f9f7 672 * @retval None.
<> 144:ef7eb2e8f9f7 673 */
<> 144:ef7eb2e8f9f7 674 #define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
<> 144:ef7eb2e8f9f7 675 ((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 /**
<> 144:ef7eb2e8f9f7 678 * @brief Cancel a transmit request.
<> 144:ef7eb2e8f9f7 679 * @param __HANDLE__: specifies the CAN Handle.
<> 144:ef7eb2e8f9f7 680 * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
<> 144:ef7eb2e8f9f7 681 * @retval None.
<> 144:ef7eb2e8f9f7 682 */
<> 144:ef7eb2e8f9f7 683 #define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
<> 144:ef7eb2e8f9f7 684 (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
<> 144:ef7eb2e8f9f7 685 ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
<> 144:ef7eb2e8f9f7 686 ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))
<> 144:ef7eb2e8f9f7 687
<> 144:ef7eb2e8f9f7 688 /**
<> 144:ef7eb2e8f9f7 689 * @brief Enable or disables the DBG Freeze for CAN.
<> 144:ef7eb2e8f9f7 690 * @param __HANDLE__: specifies the CAN Handle.
<> 144:ef7eb2e8f9f7 691 * @param __NEWSTATE__: new state of the CAN peripheral.
<> 144:ef7eb2e8f9f7 692 * This parameter can be: ENABLE (CAN reception/transmission is frozen
<> 144:ef7eb2e8f9f7 693 * during debug. Reception FIFOs can still be accessed/controlled normally)
<> 144:ef7eb2e8f9f7 694 * or DISABLE (CAN is working during debug).
<> 144:ef7eb2e8f9f7 695 * @retval None
<> 144:ef7eb2e8f9f7 696 */
<> 144:ef7eb2e8f9f7 697 #define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
<> 144:ef7eb2e8f9f7 698 ((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 /**
<> 144:ef7eb2e8f9f7 701 * @}
<> 144:ef7eb2e8f9f7 702 */
<> 144:ef7eb2e8f9f7 703
<> 144:ef7eb2e8f9f7 704 /* Private macros --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 705 /** @defgroup CAN_Private_Macros CAN Private Macros
<> 144:ef7eb2e8f9f7 706 * @{
<> 144:ef7eb2e8f9f7 707 */
<> 144:ef7eb2e8f9f7 708
<> 144:ef7eb2e8f9f7 709 #define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
<> 144:ef7eb2e8f9f7 710 ((MODE) == CAN_MODE_LOOPBACK)|| \
<> 144:ef7eb2e8f9f7 711 ((MODE) == CAN_MODE_SILENT) || \
<> 144:ef7eb2e8f9f7 712 ((MODE) == CAN_MODE_SILENT_LOOPBACK))
<> 144:ef7eb2e8f9f7 713
<> 144:ef7eb2e8f9f7 714 #define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
<> 144:ef7eb2e8f9f7 715 ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
<> 144:ef7eb2e8f9f7 716
<> 144:ef7eb2e8f9f7 717 #define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
<> 144:ef7eb2e8f9f7 718
<> 144:ef7eb2e8f9f7 719 #define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
<> 144:ef7eb2e8f9f7 722 ((MODE) == CAN_FILTERMODE_IDLIST))
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
<> 144:ef7eb2e8f9f7 725 ((SCALE) == CAN_FILTERSCALE_32BIT))
<> 144:ef7eb2e8f9f7 726
<> 144:ef7eb2e8f9f7 727
<> 144:ef7eb2e8f9f7 728 #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
<> 144:ef7eb2e8f9f7 729 ((FIFO) == CAN_FILTER_FIFO1))
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 #define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
<> 144:ef7eb2e8f9f7 732 ((IDTYPE) == CAN_ID_EXT))
<> 144:ef7eb2e8f9f7 733
<> 144:ef7eb2e8f9f7 734 #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736 #define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
<> 144:ef7eb2e8f9f7 737
<> 144:ef7eb2e8f9f7 738 #define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
<> 144:ef7eb2e8f9f7 739
<> 144:ef7eb2e8f9f7 740 #define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
<> 144:ef7eb2e8f9f7 741 #define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
<> 144:ef7eb2e8f9f7 742 #define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
<> 144:ef7eb2e8f9f7 743 #define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 #define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
<> 144:ef7eb2e8f9f7 746
<> 144:ef7eb2e8f9f7 747 /**
<> 144:ef7eb2e8f9f7 748 * @}
<> 144:ef7eb2e8f9f7 749 */
<> 144:ef7eb2e8f9f7 750
<> 144:ef7eb2e8f9f7 751 /* Include CAN HAL Extension module */
<> 144:ef7eb2e8f9f7 752 #include "stm32f1xx_hal_can_ex.h"
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 755 /** @addtogroup CAN_Exported_Functions
<> 144:ef7eb2e8f9f7 756 * @{
<> 144:ef7eb2e8f9f7 757 */
<> 144:ef7eb2e8f9f7 758
<> 144:ef7eb2e8f9f7 759 /** @addtogroup CAN_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 760 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 761 * @{
<> 144:ef7eb2e8f9f7 762 */
<> 144:ef7eb2e8f9f7 763 /* Initialization and de-initialization functions *****************************/
<> 144:ef7eb2e8f9f7 764 HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
<> 144:ef7eb2e8f9f7 765 HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
<> 144:ef7eb2e8f9f7 766 HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
<> 144:ef7eb2e8f9f7 767 void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
<> 144:ef7eb2e8f9f7 768 void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
<> 144:ef7eb2e8f9f7 769 /**
<> 144:ef7eb2e8f9f7 770 * @}
<> 144:ef7eb2e8f9f7 771 */
<> 144:ef7eb2e8f9f7 772
<> 144:ef7eb2e8f9f7 773 /** @addtogroup CAN_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 774 * @brief I/O operation functions
<> 144:ef7eb2e8f9f7 775 * @{
<> 144:ef7eb2e8f9f7 776 */
<> 144:ef7eb2e8f9f7 777 /* IO operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 778 HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 779 HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
<> 144:ef7eb2e8f9f7 780 HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 781 HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
<> 144:ef7eb2e8f9f7 782 HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
<> 144:ef7eb2e8f9f7 783 HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
<> 144:ef7eb2e8f9f7 784 void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
<> 144:ef7eb2e8f9f7 785 void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
<> 144:ef7eb2e8f9f7 786 void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
<> 144:ef7eb2e8f9f7 787 void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
<> 144:ef7eb2e8f9f7 788 /**
<> 144:ef7eb2e8f9f7 789 * @}
<> 144:ef7eb2e8f9f7 790 */
<> 144:ef7eb2e8f9f7 791
<> 144:ef7eb2e8f9f7 792 /** @addtogroup CAN_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 793 * @brief CAN Peripheral State functions
<> 144:ef7eb2e8f9f7 794 * @{
<> 144:ef7eb2e8f9f7 795 */
<> 144:ef7eb2e8f9f7 796 /* Peripheral State and Error functions ***************************************/
<> 144:ef7eb2e8f9f7 797 uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
<> 144:ef7eb2e8f9f7 798 HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
<> 144:ef7eb2e8f9f7 799 /**
<> 144:ef7eb2e8f9f7 800 * @}
<> 144:ef7eb2e8f9f7 801 */
<> 144:ef7eb2e8f9f7 802
<> 144:ef7eb2e8f9f7 803 /**
<> 144:ef7eb2e8f9f7 804 * @}
<> 144:ef7eb2e8f9f7 805 */
<> 144:ef7eb2e8f9f7 806
<> 144:ef7eb2e8f9f7 807 /**
<> 144:ef7eb2e8f9f7 808 * @}
<> 144:ef7eb2e8f9f7 809 */
<> 144:ef7eb2e8f9f7 810
<> 144:ef7eb2e8f9f7 811 /**
<> 144:ef7eb2e8f9f7 812 * @}
<> 144:ef7eb2e8f9f7 813 */
<> 144:ef7eb2e8f9f7 814
<> 144:ef7eb2e8f9f7 815 #endif /* STM32F103x6) || STM32F103xB || STM32F103xE || */
<> 144:ef7eb2e8f9f7 816 /* STM32F103xG) || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 817
<> 144:ef7eb2e8f9f7 818 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 819 }
<> 144:ef7eb2e8f9f7 820 #endif
<> 144:ef7eb2e8f9f7 821
<> 144:ef7eb2e8f9f7 822 #endif /* __stm32f1xx_CAN_H */
<> 144:ef7eb2e8f9f7 823
<> 144:ef7eb2e8f9f7 824
<> 144:ef7eb2e8f9f7 825 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/