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targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_ll_utils.c@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_ll_utils.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.5.1
<> 144:ef7eb2e8f9f7 6 * @date 31-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief UTILS LL module driver.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 38 #include "stm32l4xx_ll_utils.h"
<> 144:ef7eb2e8f9f7 39 #include "stm32l4xx_ll_rcc.h"
<> 144:ef7eb2e8f9f7 40 #include "stm32l4xx_ll_system.h"
<> 144:ef7eb2e8f9f7 41 #include "stm32l4xx_ll_pwr.h"
<> 144:ef7eb2e8f9f7 42 #ifdef USE_FULL_ASSERT
<> 144:ef7eb2e8f9f7 43 #include "stm32_assert.h"
<> 144:ef7eb2e8f9f7 44 #else
<> 144:ef7eb2e8f9f7 45 #define assert_param(expr) ((void)0U)
<> 144:ef7eb2e8f9f7 46 #endif
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 /** @addtogroup STM32L4xx_LL_Driver
<> 144:ef7eb2e8f9f7 49 * @{
<> 144:ef7eb2e8f9f7 50 */
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /** @addtogroup UTILS_LL
<> 144:ef7eb2e8f9f7 53 * @{
<> 144:ef7eb2e8f9f7 54 */
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 57 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59 /** @addtogroup UTILS_LL_Private_Constants
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62 #define UTILS_MAX_FREQUENCY_SCALE1 ((uint32_t)80000000) /*!< Maximum frequency for system clock at power scale1, in Hz */
<> 144:ef7eb2e8f9f7 63 #define UTILS_MAX_FREQUENCY_SCALE2 ((uint32_t)26000000) /*!< Maximum frequency for system clock at power scale2, in Hz */
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 /* Defines used for PLL range */
<> 144:ef7eb2e8f9f7 66 #define UTILS_PLLVCO_INPUT_MIN ((uint32_t)4000000) /*!< Frequency min for PLLVCO input, in Hz */
<> 144:ef7eb2e8f9f7 67 #define UTILS_PLLVCO_INPUT_MAX ((uint32_t)16000000) /*!< Frequency max for PLLVCO input, in Hz */
<> 144:ef7eb2e8f9f7 68 #define UTILS_PLLVCO_OUTPUT_MIN ((uint32_t)64000000) /*!< Frequency min for PLLVCO output, in Hz */
<> 144:ef7eb2e8f9f7 69 #define UTILS_PLLVCO_OUTPUT_MAX ((uint32_t)344000000) /*!< Frequency max for PLLVCO output, in Hz */
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 /* Defines used for HSE range */
<> 144:ef7eb2e8f9f7 72 #define UTILS_HSE_FREQUENCY_MIN ((uint32_t)4000000) /*!< Frequency min for HSE frequency, in Hz */
<> 144:ef7eb2e8f9f7 73 #define UTILS_HSE_FREQUENCY_MAX ((uint32_t)48000000) /*!< Frequency max for HSE frequency, in Hz */
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 /* Defines used for FLASH latency according to HCLK Frequency */
<> 144:ef7eb2e8f9f7 76 #define UTILS_SCALE1_LATENCY1_FREQ ((uint32_t)16000000) /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
<> 144:ef7eb2e8f9f7 77 #define UTILS_SCALE1_LATENCY2_FREQ ((uint32_t)32000000) /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
<> 144:ef7eb2e8f9f7 78 #define UTILS_SCALE1_LATENCY3_FREQ ((uint32_t)48000000) /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
<> 144:ef7eb2e8f9f7 79 #define UTILS_SCALE1_LATENCY4_FREQ ((uint32_t)64000000) /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
<> 144:ef7eb2e8f9f7 80 #define UTILS_SCALE2_LATENCY1_FREQ ((uint32_t)6000000) /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
<> 144:ef7eb2e8f9f7 81 #define UTILS_SCALE2_LATENCY2_FREQ ((uint32_t)12000000) /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
<> 144:ef7eb2e8f9f7 82 #define UTILS_SCALE2_LATENCY3_FREQ ((uint32_t)18000000) /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
<> 144:ef7eb2e8f9f7 83 /**
<> 144:ef7eb2e8f9f7 84 * @}
<> 144:ef7eb2e8f9f7 85 */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 88 /** @addtogroup UTILS_LL_Private_Macros
<> 144:ef7eb2e8f9f7 89 * @{
<> 144:ef7eb2e8f9f7 90 */
<> 144:ef7eb2e8f9f7 91 #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
<> 144:ef7eb2e8f9f7 92 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
<> 144:ef7eb2e8f9f7 93 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
<> 144:ef7eb2e8f9f7 94 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
<> 144:ef7eb2e8f9f7 95 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
<> 144:ef7eb2e8f9f7 96 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
<> 144:ef7eb2e8f9f7 97 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
<> 144:ef7eb2e8f9f7 98 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
<> 144:ef7eb2e8f9f7 99 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
<> 144:ef7eb2e8f9f7 102 || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
<> 144:ef7eb2e8f9f7 103 || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
<> 144:ef7eb2e8f9f7 104 || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
<> 144:ef7eb2e8f9f7 105 || ((__VALUE__) == LL_RCC_APB1_DIV_16))
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
<> 144:ef7eb2e8f9f7 108 || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
<> 144:ef7eb2e8f9f7 109 || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
<> 144:ef7eb2e8f9f7 110 || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
<> 144:ef7eb2e8f9f7 111 || ((__VALUE__) == LL_RCC_APB2_DIV_16))
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_1) \
<> 144:ef7eb2e8f9f7 114 || ((__VALUE__) == LL_RCC_PLLM_DIV_2) \
<> 144:ef7eb2e8f9f7 115 || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
<> 144:ef7eb2e8f9f7 116 || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
<> 144:ef7eb2e8f9f7 117 || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
<> 144:ef7eb2e8f9f7 118 || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
<> 144:ef7eb2e8f9f7 119 || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
<> 144:ef7eb2e8f9f7 120 || ((__VALUE__) == LL_RCC_PLLM_DIV_8))
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8 <= (__VALUE__)) && ((__VALUE__) <= 86))
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 #define IS_LL_UTILS_PLLR_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLR_DIV_2) \
<> 144:ef7eb2e8f9f7 125 || ((__VALUE__) == LL_RCC_PLLR_DIV_4) \
<> 144:ef7eb2e8f9f7 126 || ((__VALUE__) == LL_RCC_PLLR_DIV_6) \
<> 144:ef7eb2e8f9f7 127 || ((__VALUE__) == LL_RCC_PLLR_DIV_8))
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
<> 144:ef7eb2e8f9f7 134 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2))
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
<> 144:ef7eb2e8f9f7 137 || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
<> 144:ef7eb2e8f9f7 140 /**
<> 144:ef7eb2e8f9f7 141 * @}
<> 144:ef7eb2e8f9f7 142 */
<> 144:ef7eb2e8f9f7 143 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 144 /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
<> 144:ef7eb2e8f9f7 145 * @{
<> 144:ef7eb2e8f9f7 146 */
<> 144:ef7eb2e8f9f7 147 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
<> 144:ef7eb2e8f9f7 148 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
<> 144:ef7eb2e8f9f7 149 static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency);
<> 144:ef7eb2e8f9f7 150 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
<> 144:ef7eb2e8f9f7 151 static ErrorStatus UTILS_PLL_IsBusy(void);
<> 144:ef7eb2e8f9f7 152 /**
<> 144:ef7eb2e8f9f7 153 * @}
<> 144:ef7eb2e8f9f7 154 */
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 157 /** @addtogroup UTILS_LL_Exported_Functions
<> 144:ef7eb2e8f9f7 158 * @{
<> 144:ef7eb2e8f9f7 159 */
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /** @addtogroup UTILS_LL_EF_DELAY
<> 144:ef7eb2e8f9f7 162 * @{
<> 144:ef7eb2e8f9f7 163 */
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 /**
<> 144:ef7eb2e8f9f7 166 * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
<> 144:ef7eb2e8f9f7 167 * @note When a RTOS is used, it is recommended to avoid changing the Systick
<> 144:ef7eb2e8f9f7 168 * configuration by calling this function, for a delay use rather osDelay RTOS service.
<> 144:ef7eb2e8f9f7 169 * @param HCLKFrequency HCLK frequency in Hz
<> 144:ef7eb2e8f9f7 170 * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
<> 144:ef7eb2e8f9f7 171 * @retval None
<> 144:ef7eb2e8f9f7 172 */
<> 144:ef7eb2e8f9f7 173 void LL_Init1msTick(uint32_t HCLKFrequency)
<> 144:ef7eb2e8f9f7 174 {
<> 144:ef7eb2e8f9f7 175 /* Use frequency provided in argument */
<> 144:ef7eb2e8f9f7 176 LL_InitTick(HCLKFrequency, 1000);
<> 144:ef7eb2e8f9f7 177 }
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /**
<> 144:ef7eb2e8f9f7 180 * @brief This function provides accurate delay (in milliseconds) based
<> 144:ef7eb2e8f9f7 181 * on SysTick counter flag
<> 144:ef7eb2e8f9f7 182 * @note When a RTOS is used, it is recommended to avoid using blocking delay
<> 144:ef7eb2e8f9f7 183 * and use rather osDelay service.
<> 144:ef7eb2e8f9f7 184 * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
<> 144:ef7eb2e8f9f7 185 * will configure Systick to 1ms
<> 144:ef7eb2e8f9f7 186 * @param Delay specifies the delay time length, in milliseconds.
<> 144:ef7eb2e8f9f7 187 * @retval None
<> 144:ef7eb2e8f9f7 188 */
<> 144:ef7eb2e8f9f7 189 void LL_mDelay(uint32_t Delay)
<> 144:ef7eb2e8f9f7 190 {
<> 144:ef7eb2e8f9f7 191 __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
<> 144:ef7eb2e8f9f7 192 /* Add this code to indicate that local variable is not used */
<> 144:ef7eb2e8f9f7 193 ((void)tmp);
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 /* Add a period to guaranty minimum wait */
<> 144:ef7eb2e8f9f7 196 if (Delay < LL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 197 {
<> 144:ef7eb2e8f9f7 198 Delay++;
<> 144:ef7eb2e8f9f7 199 }
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 while (Delay)
<> 144:ef7eb2e8f9f7 202 {
<> 144:ef7eb2e8f9f7 203 if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0)
<> 144:ef7eb2e8f9f7 204 {
<> 144:ef7eb2e8f9f7 205 Delay--;
<> 144:ef7eb2e8f9f7 206 }
<> 144:ef7eb2e8f9f7 207 }
<> 144:ef7eb2e8f9f7 208 }
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 /**
<> 144:ef7eb2e8f9f7 211 * @}
<> 144:ef7eb2e8f9f7 212 */
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /** @addtogroup UTILS_EF_SYSTEM
<> 144:ef7eb2e8f9f7 215 * @brief System Configuration functions
<> 144:ef7eb2e8f9f7 216 *
<> 144:ef7eb2e8f9f7 217 @verbatim
<> 144:ef7eb2e8f9f7 218 ===============================================================================
<> 144:ef7eb2e8f9f7 219 ##### System Configuration functions #####
<> 144:ef7eb2e8f9f7 220 ===============================================================================
<> 144:ef7eb2e8f9f7 221 [..]
<> 144:ef7eb2e8f9f7 222 System, AHB and APB buses clocks configuration
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 80000000 Hz.
<> 144:ef7eb2e8f9f7 225 @endverbatim
<> 144:ef7eb2e8f9f7 226 @internal
<> 144:ef7eb2e8f9f7 227 Depending on the device voltage range, the maximum frequency should be
<> 144:ef7eb2e8f9f7 228 adapted accordingly:
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 (++) Table 1. HCLK clock frequency.
<> 144:ef7eb2e8f9f7 231 (++) +-------------------------------------------------------+
<> 144:ef7eb2e8f9f7 232 (++) | Latency | HCLK clock frequency (MHz) |
<> 144:ef7eb2e8f9f7 233 (++) | |-------------------------------------|
<> 144:ef7eb2e8f9f7 234 (++) | | voltage range 1 | voltage range 2 |
<> 144:ef7eb2e8f9f7 235 (++) | | 1.2 V | 1.0 V |
<> 144:ef7eb2e8f9f7 236 (++) |-----------------|------------------|------------------|
<> 144:ef7eb2e8f9f7 237 (++) |0WS(1 CPU cycles)| 0 < HCLK <= 16 | 0 < HCLK <= 6 |
<> 144:ef7eb2e8f9f7 238 (++) |-----------------|------------------|------------------|
<> 144:ef7eb2e8f9f7 239 (++) |1WS(2 CPU cycles)| 16 < HCLK <= 32 | 6 < HCLK <= 12 |
<> 144:ef7eb2e8f9f7 240 (++) |-----------------|------------------|------------------|
<> 144:ef7eb2e8f9f7 241 (++) |2WS(3 CPU cycles)| 32 < HCLK <= 48 | 12 < HCLK <= 18 |
<> 144:ef7eb2e8f9f7 242 (++) |-----------------|------------------|------------------|
<> 144:ef7eb2e8f9f7 243 (++) |3WS(4 CPU cycles)| 48 < HCLK <= 64 | 18 < HCLK <= 26 |
<> 144:ef7eb2e8f9f7 244 (++) |-----------------|------------------|------------------|
<> 144:ef7eb2e8f9f7 245 (++) |4WS(5 CPU cycles)| 64 < HCLK <= 80 | 18 < HCLK <= 26 |
<> 144:ef7eb2e8f9f7 246 (++) +-------------------------------------------------------+
<> 144:ef7eb2e8f9f7 247 @endinternal
<> 144:ef7eb2e8f9f7 248 * @{
<> 144:ef7eb2e8f9f7 249 */
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /**
<> 144:ef7eb2e8f9f7 252 * @brief This function sets directly SystemCoreClock CMSIS variable.
<> 144:ef7eb2e8f9f7 253 * @note Variable can be calculated also through SystemCoreClockUpdate function.
<> 144:ef7eb2e8f9f7 254 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
<> 144:ef7eb2e8f9f7 255 * @retval None
<> 144:ef7eb2e8f9f7 256 */
<> 144:ef7eb2e8f9f7 257 void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
<> 144:ef7eb2e8f9f7 258 {
<> 144:ef7eb2e8f9f7 259 /* HCLK clock frequency */
<> 144:ef7eb2e8f9f7 260 SystemCoreClock = HCLKFrequency;
<> 144:ef7eb2e8f9f7 261 }
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /**
<> 144:ef7eb2e8f9f7 264 * @brief This function configures system clock with MSI as clock source of the PLL
<> 144:ef7eb2e8f9f7 265 * @note The application needs to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled.
<> 144:ef7eb2e8f9f7 266 * @note Function is based on the following formula:
<> 144:ef7eb2e8f9f7 267 * - PLL output frequency = (((MSI frequency / PLLM) * PLLN) / PLLR)
<> 144:ef7eb2e8f9f7 268 * - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = MSI frequency / PLLM)
<> 144:ef7eb2e8f9f7 269 * - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
<> 144:ef7eb2e8f9f7 270 * - PLLR: ensure that max frequency at 80 MHz is reach (PLLVCO_output / PLLR)
<> 144:ef7eb2e8f9f7 271 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
<> 144:ef7eb2e8f9f7 272 * the configuration information for the PLL.
<> 144:ef7eb2e8f9f7 273 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
<> 144:ef7eb2e8f9f7 274 * the configuration information for the BUS prescalers.
<> 144:ef7eb2e8f9f7 275 * @retval An ErrorStatus enumeration value:
<> 144:ef7eb2e8f9f7 276 * - SUCCESS: Max frequency configuration done
<> 144:ef7eb2e8f9f7 277 * - ERROR: Max frequency configuration not done
<> 144:ef7eb2e8f9f7 278 */
<> 144:ef7eb2e8f9f7 279 ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
<> 144:ef7eb2e8f9f7 280 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
<> 144:ef7eb2e8f9f7 281 {
<> 144:ef7eb2e8f9f7 282 ErrorStatus status = SUCCESS;
<> 144:ef7eb2e8f9f7 283 uint32_t pllfreq = 0, msi_range = 0;
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /* Check if one of the PLL is enabled */
<> 144:ef7eb2e8f9f7 286 if (UTILS_PLL_IsBusy() == SUCCESS)
<> 144:ef7eb2e8f9f7 287 {
<> 144:ef7eb2e8f9f7 288 /* Get the current MSI range */
<> 144:ef7eb2e8f9f7 289 if (LL_RCC_MSI_IsEnabledRangeSelect())
<> 144:ef7eb2e8f9f7 290 {
<> 144:ef7eb2e8f9f7 291 msi_range = LL_RCC_MSI_GetRange();
<> 144:ef7eb2e8f9f7 292 switch (msi_range)
<> 144:ef7eb2e8f9f7 293 {
<> 144:ef7eb2e8f9f7 294 case LL_RCC_MSIRANGE_0: /* MSI = 100 KHz */
<> 144:ef7eb2e8f9f7 295 case LL_RCC_MSIRANGE_1: /* MSI = 200 KHz */
<> 144:ef7eb2e8f9f7 296 case LL_RCC_MSIRANGE_2: /* MSI = 400 KHz */
<> 144:ef7eb2e8f9f7 297 case LL_RCC_MSIRANGE_3: /* MSI = 800 KHz */
<> 144:ef7eb2e8f9f7 298 case LL_RCC_MSIRANGE_4: /* MSI = 1 MHz */
<> 144:ef7eb2e8f9f7 299 case LL_RCC_MSIRANGE_5: /* MSI = 2 MHz */
<> 144:ef7eb2e8f9f7 300 /* PLLVCO input frequency can not in the range from 4 to 16 MHz*/
<> 144:ef7eb2e8f9f7 301 status = ERROR;
<> 144:ef7eb2e8f9f7 302 break;
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 case LL_RCC_MSIRANGE_6: /* MSI = 4 MHz */
<> 144:ef7eb2e8f9f7 305 case LL_RCC_MSIRANGE_7: /* MSI = 8 MHz */
<> 144:ef7eb2e8f9f7 306 case LL_RCC_MSIRANGE_8: /* MSI = 16 MHz */
<> 144:ef7eb2e8f9f7 307 case LL_RCC_MSIRANGE_9: /* MSI = 24 MHz */
<> 144:ef7eb2e8f9f7 308 case LL_RCC_MSIRANGE_10: /* MSI = 32 MHz */
<> 144:ef7eb2e8f9f7 309 case LL_RCC_MSIRANGE_11: /* MSI = 48 MHz */
<> 144:ef7eb2e8f9f7 310 default:
<> 144:ef7eb2e8f9f7 311 break;
<> 144:ef7eb2e8f9f7 312 }
<> 144:ef7eb2e8f9f7 313 }
<> 144:ef7eb2e8f9f7 314 else
<> 144:ef7eb2e8f9f7 315 {
<> 144:ef7eb2e8f9f7 316 msi_range = LL_RCC_MSI_GetRangeAfterStandby();
<> 144:ef7eb2e8f9f7 317 switch (msi_range)
<> 144:ef7eb2e8f9f7 318 {
<> 144:ef7eb2e8f9f7 319 case LL_RCC_MSISRANGE_4: /* MSI = 1 MHz */
<> 144:ef7eb2e8f9f7 320 case LL_RCC_MSISRANGE_5: /* MSI = 2 MHz */
<> 144:ef7eb2e8f9f7 321 /* PLLVCO input frequency is not in the range from 4 to 16 MHz*/
<> 144:ef7eb2e8f9f7 322 status = ERROR;
<> 144:ef7eb2e8f9f7 323 break;
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 case LL_RCC_MSISRANGE_7: /* MSI = 8 MHz */
<> 144:ef7eb2e8f9f7 326 case LL_RCC_MSISRANGE_6: /* MSI = 4 MHz */
<> 144:ef7eb2e8f9f7 327 default:
<> 144:ef7eb2e8f9f7 328 break;
<> 144:ef7eb2e8f9f7 329 }
<> 144:ef7eb2e8f9f7 330 }
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 /* Main PLL configuration and activation */
<> 144:ef7eb2e8f9f7 333 if (status != ERROR)
<> 144:ef7eb2e8f9f7 334 {
<> 144:ef7eb2e8f9f7 335 /* Calculate the new PLL output frequency */
<> 144:ef7eb2e8f9f7 336 pllfreq = UTILS_GetPLLOutputFrequency(__LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), msi_range),
<> 144:ef7eb2e8f9f7 337 UTILS_PLLInitStruct);
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 /* Enable MSI if not enabled */
<> 144:ef7eb2e8f9f7 340 if (LL_RCC_MSI_IsReady() != 1)
<> 144:ef7eb2e8f9f7 341 {
<> 144:ef7eb2e8f9f7 342 LL_RCC_MSI_Enable();
<> 144:ef7eb2e8f9f7 343 while ((LL_RCC_MSI_IsReady() != 1))
<> 144:ef7eb2e8f9f7 344 {
<> 144:ef7eb2e8f9f7 345 /* Wait for MSI ready */
<> 144:ef7eb2e8f9f7 346 }
<> 144:ef7eb2e8f9f7 347 }
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /* Configure PLL */
<> 144:ef7eb2e8f9f7 350 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
<> 144:ef7eb2e8f9f7 351 UTILS_PLLInitStruct->PLLR);
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 /* Enable PLL and switch system clock to PLL */
<> 144:ef7eb2e8f9f7 354 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
<> 144:ef7eb2e8f9f7 355 }
<> 144:ef7eb2e8f9f7 356 }
<> 144:ef7eb2e8f9f7 357 else
<> 144:ef7eb2e8f9f7 358 {
<> 144:ef7eb2e8f9f7 359 /* Current PLL configuration cannot be modified */
<> 144:ef7eb2e8f9f7 360 status = ERROR;
<> 144:ef7eb2e8f9f7 361 }
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 return status;
<> 144:ef7eb2e8f9f7 364 }
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 /**
<> 144:ef7eb2e8f9f7 367 * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL
<> 144:ef7eb2e8f9f7 368 * @note The application need to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled.
<> 144:ef7eb2e8f9f7 369 * @note Function is based on the following formula:
<> 144:ef7eb2e8f9f7 370 * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLR)
<> 144:ef7eb2e8f9f7 371 * - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSI frequency / PLLM)
<> 144:ef7eb2e8f9f7 372 * - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
<> 144:ef7eb2e8f9f7 373 * - PLLR: ensure that max frequency at 80 MHz is reach (PLLVCO_output / PLLR)
<> 144:ef7eb2e8f9f7 374 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
<> 144:ef7eb2e8f9f7 375 * the configuration information for the PLL.
<> 144:ef7eb2e8f9f7 376 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
<> 144:ef7eb2e8f9f7 377 * the configuration information for the BUS prescalers.
<> 144:ef7eb2e8f9f7 378 * @retval An ErrorStatus enumeration value:
<> 144:ef7eb2e8f9f7 379 * - SUCCESS: Max frequency configuration done
<> 144:ef7eb2e8f9f7 380 * - ERROR: Max frequency configuration not done
<> 144:ef7eb2e8f9f7 381 */
<> 144:ef7eb2e8f9f7 382 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
<> 144:ef7eb2e8f9f7 383 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
<> 144:ef7eb2e8f9f7 384 {
<> 144:ef7eb2e8f9f7 385 ErrorStatus status = SUCCESS;
<> 144:ef7eb2e8f9f7 386 uint32_t pllfreq = 0;
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /* Check if one of the PLL is enabled */
<> 144:ef7eb2e8f9f7 389 if (UTILS_PLL_IsBusy() == SUCCESS)
<> 144:ef7eb2e8f9f7 390 {
<> 144:ef7eb2e8f9f7 391 /* Calculate the new PLL output frequency */
<> 144:ef7eb2e8f9f7 392 pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 /* Enable HSI if not enabled */
<> 144:ef7eb2e8f9f7 395 if (LL_RCC_HSI_IsReady() != 1)
<> 144:ef7eb2e8f9f7 396 {
<> 144:ef7eb2e8f9f7 397 LL_RCC_HSI_Enable();
<> 144:ef7eb2e8f9f7 398 while (LL_RCC_HSI_IsReady() != 1)
<> 144:ef7eb2e8f9f7 399 {
<> 144:ef7eb2e8f9f7 400 /* Wait for HSI ready */
<> 144:ef7eb2e8f9f7 401 }
<> 144:ef7eb2e8f9f7 402 }
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 /* Configure PLL */
<> 144:ef7eb2e8f9f7 405 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
<> 144:ef7eb2e8f9f7 406 UTILS_PLLInitStruct->PLLR);
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 /* Enable PLL and switch system clock to PLL */
<> 144:ef7eb2e8f9f7 409 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
<> 144:ef7eb2e8f9f7 410 }
<> 144:ef7eb2e8f9f7 411 else
<> 144:ef7eb2e8f9f7 412 {
<> 144:ef7eb2e8f9f7 413 /* Current PLL configuration cannot be modified */
<> 144:ef7eb2e8f9f7 414 status = ERROR;
<> 144:ef7eb2e8f9f7 415 }
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 return status;
<> 144:ef7eb2e8f9f7 418 }
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 /**
<> 144:ef7eb2e8f9f7 421 * @brief This function configures system clock with HSE as clock source of the PLL
<> 144:ef7eb2e8f9f7 422 * @note The application need to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled.
<> 144:ef7eb2e8f9f7 423 * @note Function is based on the following formula:
<> 144:ef7eb2e8f9f7 424 * - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLR)
<> 144:ef7eb2e8f9f7 425 * - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSE frequency / PLLM)
<> 144:ef7eb2e8f9f7 426 * - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
<> 144:ef7eb2e8f9f7 427 * - PLLR: ensure that max frequency at 80 MHz is reach (PLLVCO_output / PLLR)
<> 144:ef7eb2e8f9f7 428 * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 48000000
<> 144:ef7eb2e8f9f7 429 * @param HSEBypass This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 430 * @arg @ref LL_UTILS_HSEBYPASS_ON
<> 144:ef7eb2e8f9f7 431 * @arg @ref LL_UTILS_HSEBYPASS_OFF
<> 144:ef7eb2e8f9f7 432 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
<> 144:ef7eb2e8f9f7 433 * the configuration information for the PLL.
<> 144:ef7eb2e8f9f7 434 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
<> 144:ef7eb2e8f9f7 435 * the configuration information for the BUS prescalers.
<> 144:ef7eb2e8f9f7 436 * @retval An ErrorStatus enumeration value:
<> 144:ef7eb2e8f9f7 437 * - SUCCESS: Max frequency configuration done
<> 144:ef7eb2e8f9f7 438 * - ERROR: Max frequency configuration not done
<> 144:ef7eb2e8f9f7 439 */
<> 144:ef7eb2e8f9f7 440 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
<> 144:ef7eb2e8f9f7 441 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
<> 144:ef7eb2e8f9f7 442 {
<> 144:ef7eb2e8f9f7 443 ErrorStatus status = SUCCESS;
<> 144:ef7eb2e8f9f7 444 uint32_t pllfreq = 0;
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 /* Check the parameters */
<> 144:ef7eb2e8f9f7 447 assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
<> 144:ef7eb2e8f9f7 448 assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 /* Check if one of the PLL is enabled */
<> 144:ef7eb2e8f9f7 451 if (UTILS_PLL_IsBusy() == SUCCESS)
<> 144:ef7eb2e8f9f7 452 {
<> 144:ef7eb2e8f9f7 453 /* Calculate the new PLL output frequency */
<> 144:ef7eb2e8f9f7 454 pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /* Enable HSE if not enabled */
<> 144:ef7eb2e8f9f7 457 if (LL_RCC_HSE_IsReady() != 1)
<> 144:ef7eb2e8f9f7 458 {
<> 144:ef7eb2e8f9f7 459 /* Check if need to enable HSE bypass feature or not */
<> 144:ef7eb2e8f9f7 460 if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
<> 144:ef7eb2e8f9f7 461 {
<> 144:ef7eb2e8f9f7 462 LL_RCC_HSE_EnableBypass();
<> 144:ef7eb2e8f9f7 463 }
<> 144:ef7eb2e8f9f7 464 else
<> 144:ef7eb2e8f9f7 465 {
<> 144:ef7eb2e8f9f7 466 LL_RCC_HSE_DisableBypass();
<> 144:ef7eb2e8f9f7 467 }
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /* Enable HSE */
<> 144:ef7eb2e8f9f7 470 LL_RCC_HSE_Enable();
<> 144:ef7eb2e8f9f7 471 while (LL_RCC_HSE_IsReady() != 1)
<> 144:ef7eb2e8f9f7 472 {
<> 144:ef7eb2e8f9f7 473 /* Wait for HSE ready */
<> 144:ef7eb2e8f9f7 474 }
<> 144:ef7eb2e8f9f7 475 }
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 /* Configure PLL */
<> 144:ef7eb2e8f9f7 478 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
<> 144:ef7eb2e8f9f7 479 UTILS_PLLInitStruct->PLLR);
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 /* Enable PLL and switch system clock to PLL */
<> 144:ef7eb2e8f9f7 482 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
<> 144:ef7eb2e8f9f7 483 }
<> 144:ef7eb2e8f9f7 484 else
<> 144:ef7eb2e8f9f7 485 {
<> 144:ef7eb2e8f9f7 486 /* Current PLL configuration cannot be modified */
<> 144:ef7eb2e8f9f7 487 status = ERROR;
<> 144:ef7eb2e8f9f7 488 }
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 return status;
<> 144:ef7eb2e8f9f7 491 }
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 /**
<> 144:ef7eb2e8f9f7 494 * @}
<> 144:ef7eb2e8f9f7 495 */
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 /**
<> 144:ef7eb2e8f9f7 498 * @}
<> 144:ef7eb2e8f9f7 499 */
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 /** @addtogroup UTILS_LL_Private_Functions
<> 144:ef7eb2e8f9f7 502 * @{
<> 144:ef7eb2e8f9f7 503 */
<> 144:ef7eb2e8f9f7 504 /**
<> 144:ef7eb2e8f9f7 505 * @brief Update number of Flash wait states in line with new frequency and current
<> 144:ef7eb2e8f9f7 506 voltage range.
<> 144:ef7eb2e8f9f7 507 * @param HCLK_Frequency HCLK frequency
<> 144:ef7eb2e8f9f7 508 * @retval An ErrorStatus enumeration value:
<> 144:ef7eb2e8f9f7 509 * - SUCCESS: Latency has been modified
<> 144:ef7eb2e8f9f7 510 * - ERROR: Latency cannot be modified
<> 144:ef7eb2e8f9f7 511 */
<> 144:ef7eb2e8f9f7 512 static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency)
<> 144:ef7eb2e8f9f7 513 {
<> 144:ef7eb2e8f9f7 514 ErrorStatus status = SUCCESS;
<> 144:ef7eb2e8f9f7 515
<> 144:ef7eb2e8f9f7 516 uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 /* Frequency cannot be equal to 0 */
<> 144:ef7eb2e8f9f7 519 if (HCLK_Frequency == 0)
<> 144:ef7eb2e8f9f7 520 {
<> 144:ef7eb2e8f9f7 521 status = ERROR;
<> 144:ef7eb2e8f9f7 522 }
<> 144:ef7eb2e8f9f7 523 else
<> 144:ef7eb2e8f9f7 524 {
<> 144:ef7eb2e8f9f7 525 if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
<> 144:ef7eb2e8f9f7 526 {
<> 144:ef7eb2e8f9f7 527 if (HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ)
<> 144:ef7eb2e8f9f7 528 {
<> 144:ef7eb2e8f9f7 529 /* 64 < HCLK <= 80 => 4WS (5 CPU cycles) */
<> 144:ef7eb2e8f9f7 530 latency = LL_FLASH_LATENCY_4;
<> 144:ef7eb2e8f9f7 531 }
<> 144:ef7eb2e8f9f7 532 else if (HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ)
<> 144:ef7eb2e8f9f7 533 {
<> 144:ef7eb2e8f9f7 534 /* 48 < HCLK <= 64 => 3WS (4 CPU cycles) */
<> 144:ef7eb2e8f9f7 535 latency = LL_FLASH_LATENCY_3;
<> 144:ef7eb2e8f9f7 536 }
<> 144:ef7eb2e8f9f7 537 else if (HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ)
<> 144:ef7eb2e8f9f7 538 {
<> 144:ef7eb2e8f9f7 539 /* 32 < HCLK <= 48 => 2WS (3 CPU cycles) */
<> 144:ef7eb2e8f9f7 540 latency = LL_FLASH_LATENCY_2;
<> 144:ef7eb2e8f9f7 541 }
<> 144:ef7eb2e8f9f7 542 else
<> 144:ef7eb2e8f9f7 543 {
<> 144:ef7eb2e8f9f7 544 if (HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ)
<> 144:ef7eb2e8f9f7 545 {
<> 144:ef7eb2e8f9f7 546 /* 16 < HCLK <= 32 => 1WS (2 CPU cycles) */
<> 144:ef7eb2e8f9f7 547 latency = LL_FLASH_LATENCY_1;
<> 144:ef7eb2e8f9f7 548 }
<> 144:ef7eb2e8f9f7 549 /* else HCLK_Frequency < 16MHz default LL_FLASH_LATENCY_0 0WS */
<> 144:ef7eb2e8f9f7 550 }
<> 144:ef7eb2e8f9f7 551 }
<> 144:ef7eb2e8f9f7 552 else
<> 144:ef7eb2e8f9f7 553 {
<> 144:ef7eb2e8f9f7 554 if (HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ)
<> 144:ef7eb2e8f9f7 555 {
<> 144:ef7eb2e8f9f7 556 /* 18 < HCLK <= 26 => 3WS (4 CPU cycles) */
<> 144:ef7eb2e8f9f7 557 latency = LL_FLASH_LATENCY_3;
<> 144:ef7eb2e8f9f7 558 }
<> 144:ef7eb2e8f9f7 559 else if (HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)
<> 144:ef7eb2e8f9f7 560 {
<> 144:ef7eb2e8f9f7 561 /* 12 < HCLK <= 18 => 2WS (3 CPU cycles) */
<> 144:ef7eb2e8f9f7 562 latency = LL_FLASH_LATENCY_2;
<> 144:ef7eb2e8f9f7 563 }
<> 144:ef7eb2e8f9f7 564 else
<> 144:ef7eb2e8f9f7 565 {
<> 144:ef7eb2e8f9f7 566 if (HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)
<> 144:ef7eb2e8f9f7 567 {
<> 144:ef7eb2e8f9f7 568 /* 6 < HCLK <= 12 => 1WS (2 CPU cycles) */
<> 144:ef7eb2e8f9f7 569 latency = LL_FLASH_LATENCY_1;
<> 144:ef7eb2e8f9f7 570 }
<> 144:ef7eb2e8f9f7 571 /* else HCLK_Frequency < 6MHz default LL_FLASH_LATENCY_0 0WS */
<> 144:ef7eb2e8f9f7 572 }
<> 144:ef7eb2e8f9f7 573 }
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 LL_FLASH_SetLatency(latency);
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 /* Check that the new number of wait states is taken into account to access the Flash
<> 144:ef7eb2e8f9f7 578 memory by reading the FLASH_ACR register */
<> 144:ef7eb2e8f9f7 579 if (LL_FLASH_GetLatency() != latency)
<> 144:ef7eb2e8f9f7 580 {
<> 144:ef7eb2e8f9f7 581 status = ERROR;
<> 144:ef7eb2e8f9f7 582 }
<> 144:ef7eb2e8f9f7 583 }
<> 144:ef7eb2e8f9f7 584 return status;
<> 144:ef7eb2e8f9f7 585 }
<> 144:ef7eb2e8f9f7 586
<> 144:ef7eb2e8f9f7 587 /**
<> 144:ef7eb2e8f9f7 588 * @brief Function to check that PLL can be modified
<> 144:ef7eb2e8f9f7 589 * @param PLL_InputFrequency PLL input frequency (in Hz)
<> 144:ef7eb2e8f9f7 590 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
<> 144:ef7eb2e8f9f7 591 * the configuration information for the PLL.
<> 144:ef7eb2e8f9f7 592 * @retval PLL output frequency (in Hz)
<> 144:ef7eb2e8f9f7 593 */
<> 144:ef7eb2e8f9f7 594 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
<> 144:ef7eb2e8f9f7 595 {
<> 144:ef7eb2e8f9f7 596 uint32_t pllfreq = 0;
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 /* Check the parameters */
<> 144:ef7eb2e8f9f7 599 assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
<> 144:ef7eb2e8f9f7 600 assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
<> 144:ef7eb2e8f9f7 601 assert_param(IS_LL_UTILS_PLLR_VALUE(UTILS_PLLInitStruct->PLLR));
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 /* Check different PLL parameters according to RM */
<> 144:ef7eb2e8f9f7 604 /* - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz. */
<> 144:ef7eb2e8f9f7 605 pllfreq = PLL_InputFrequency / (((UTILS_PLLInitStruct->PLLM >> RCC_POSITION_PLLM) + 1));
<> 144:ef7eb2e8f9f7 606 assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 /* - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz.*/
<> 144:ef7eb2e8f9f7 609 pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_POSITION_PLLN));
<> 144:ef7eb2e8f9f7 610 assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 /* - PLLR: ensure that max frequency at 80 MHz is reach */
<> 144:ef7eb2e8f9f7 613 pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLR >> RCC_POSITION_PLLR) + 1) * 2);
<> 144:ef7eb2e8f9f7 614 assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 return pllfreq;
<> 144:ef7eb2e8f9f7 617 }
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 /**
<> 144:ef7eb2e8f9f7 620 * @brief Function to check that PLL can be modified
<> 144:ef7eb2e8f9f7 621 * @retval An ErrorStatus enumeration value:
<> 144:ef7eb2e8f9f7 622 * - SUCCESS: PLL modification can be done
<> 144:ef7eb2e8f9f7 623 * - ERROR: PLL is busy
<> 144:ef7eb2e8f9f7 624 */
<> 144:ef7eb2e8f9f7 625 static ErrorStatus UTILS_PLL_IsBusy(void)
<> 144:ef7eb2e8f9f7 626 {
<> 144:ef7eb2e8f9f7 627 ErrorStatus status = SUCCESS;
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 /* Check if PLL is busy*/
<> 144:ef7eb2e8f9f7 630 if (LL_RCC_PLL_IsReady() != 0)
<> 144:ef7eb2e8f9f7 631 {
<> 144:ef7eb2e8f9f7 632 /* PLL configuration cannot be modified */
<> 144:ef7eb2e8f9f7 633 status = ERROR;
<> 144:ef7eb2e8f9f7 634 }
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636 /* Check if PLLSAI1 is busy*/
<> 144:ef7eb2e8f9f7 637 if (LL_RCC_PLLSAI1_IsReady() != 0)
<> 144:ef7eb2e8f9f7 638 {
<> 144:ef7eb2e8f9f7 639 /* PLLSAI1 configuration cannot be modified */
<> 144:ef7eb2e8f9f7 640 status = ERROR;
<> 144:ef7eb2e8f9f7 641 }
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 #if defined(RCC_PLLSAI2_SUPPORT)
<> 144:ef7eb2e8f9f7 644 /* Check if PLLSAI2 is busy*/
<> 144:ef7eb2e8f9f7 645 if (LL_RCC_PLLSAI2_IsReady() != 0)
<> 144:ef7eb2e8f9f7 646 {
<> 144:ef7eb2e8f9f7 647 /* PLLSAI2 configuration cannot be modified */
<> 144:ef7eb2e8f9f7 648 status = ERROR;
<> 144:ef7eb2e8f9f7 649 }
<> 144:ef7eb2e8f9f7 650 #endif /*RCC_PLLSAI2_SUPPORT*/
<> 144:ef7eb2e8f9f7 651
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 return status;
<> 144:ef7eb2e8f9f7 654 }
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 /**
<> 144:ef7eb2e8f9f7 657 * @brief Function to enable PLL and switch system clock to PLL
<> 144:ef7eb2e8f9f7 658 * @param SYSCLK_Frequency SYSCLK frequency
<> 144:ef7eb2e8f9f7 659 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
<> 144:ef7eb2e8f9f7 660 * the configuration information for the BUS prescalers.
<> 144:ef7eb2e8f9f7 661 * @retval An ErrorStatus enumeration value:
<> 144:ef7eb2e8f9f7 662 * - SUCCESS: No problem to switch system to PLL
<> 144:ef7eb2e8f9f7 663 * - ERROR: Problem to switch system to PLL
<> 144:ef7eb2e8f9f7 664 */
<> 144:ef7eb2e8f9f7 665 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
<> 144:ef7eb2e8f9f7 666 {
<> 144:ef7eb2e8f9f7 667 ErrorStatus status = SUCCESS;
<> 144:ef7eb2e8f9f7 668 uint32_t hclk_frequency = 0;
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
<> 144:ef7eb2e8f9f7 671 assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
<> 144:ef7eb2e8f9f7 672 assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
<> 144:ef7eb2e8f9f7 673
<> 144:ef7eb2e8f9f7 674 /* Calculate HCLK frequency */
<> 144:ef7eb2e8f9f7 675 hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 /* Increasing the number of wait states because of higher CPU frequency */
<> 144:ef7eb2e8f9f7 678 if (SystemCoreClock < hclk_frequency)
<> 144:ef7eb2e8f9f7 679 {
<> 144:ef7eb2e8f9f7 680 /* Set FLASH latency to highest latency */
<> 144:ef7eb2e8f9f7 681 status = UTILS_SetFlashLatency(hclk_frequency);
<> 144:ef7eb2e8f9f7 682 }
<> 144:ef7eb2e8f9f7 683
<> 144:ef7eb2e8f9f7 684 /* Update system clock configuration */
<> 144:ef7eb2e8f9f7 685 if (status == SUCCESS)
<> 144:ef7eb2e8f9f7 686 {
<> 144:ef7eb2e8f9f7 687 /* Enable PLL */
<> 144:ef7eb2e8f9f7 688 LL_RCC_PLL_Enable();
<> 144:ef7eb2e8f9f7 689 LL_RCC_PLL_EnableDomain_SYS();
<> 144:ef7eb2e8f9f7 690 while (LL_RCC_PLL_IsReady() != 1)
<> 144:ef7eb2e8f9f7 691 {
<> 144:ef7eb2e8f9f7 692 /* Wait for PLL ready */
<> 144:ef7eb2e8f9f7 693 }
<> 144:ef7eb2e8f9f7 694
<> 144:ef7eb2e8f9f7 695 /* Sysclk activation on the main PLL */
<> 144:ef7eb2e8f9f7 696 LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
<> 144:ef7eb2e8f9f7 697 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
<> 144:ef7eb2e8f9f7 698 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
<> 144:ef7eb2e8f9f7 699 {
<> 144:ef7eb2e8f9f7 700 /* Wait for system clock switch to PLL */
<> 144:ef7eb2e8f9f7 701 }
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 /* Set APB1 & APB2 prescaler*/
<> 144:ef7eb2e8f9f7 704 LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
<> 144:ef7eb2e8f9f7 705 LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
<> 144:ef7eb2e8f9f7 706 }
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 /* Decreasing the number of wait states because of lower CPU frequency */
<> 144:ef7eb2e8f9f7 709 if (SystemCoreClock > hclk_frequency)
<> 144:ef7eb2e8f9f7 710 {
<> 144:ef7eb2e8f9f7 711 /* Set FLASH latency to lowest latency */
<> 144:ef7eb2e8f9f7 712 status = UTILS_SetFlashLatency(hclk_frequency);
<> 144:ef7eb2e8f9f7 713 }
<> 144:ef7eb2e8f9f7 714
<> 144:ef7eb2e8f9f7 715 /* Update SystemCoreClock variable */
<> 144:ef7eb2e8f9f7 716 if (status == SUCCESS)
<> 144:ef7eb2e8f9f7 717 {
<> 144:ef7eb2e8f9f7 718 LL_SetSystemCoreClock(hclk_frequency);
<> 144:ef7eb2e8f9f7 719 }
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 return status;
<> 144:ef7eb2e8f9f7 722 }
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 /**
<> 144:ef7eb2e8f9f7 725 * @}
<> 144:ef7eb2e8f9f7 726 */
<> 144:ef7eb2e8f9f7 727
<> 144:ef7eb2e8f9f7 728 /**
<> 144:ef7eb2e8f9f7 729 * @}
<> 144:ef7eb2e8f9f7 730 */
<> 144:ef7eb2e8f9f7 731
<> 144:ef7eb2e8f9f7 732 /**
<> 144:ef7eb2e8f9f7 733 * @}
<> 144:ef7eb2e8f9f7 734 */
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/