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targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_tim.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_STM/TARGET_STM32F2/stm32f2xx_hal_tim.c@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_hal_tim.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.3
<> 144:ef7eb2e8f9f7 6 * @date 29-June-2016
<> 144:ef7eb2e8f9f7 7 * @brief TIM HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Timer (TIM) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Time Base Initialization
<> 144:ef7eb2e8f9f7 11 * + Time Base Start
<> 144:ef7eb2e8f9f7 12 * + Time Base Start Interruption
<> 144:ef7eb2e8f9f7 13 * + Time Base Start DMA
<> 144:ef7eb2e8f9f7 14 * + Time Output Compare/PWM Initialization
<> 144:ef7eb2e8f9f7 15 * + Time Output Compare/PWM Channel Configuration
<> 144:ef7eb2e8f9f7 16 * + Time Output Compare/PWM Start
<> 144:ef7eb2e8f9f7 17 * + Time Output Compare/PWM Start Interruption
<> 144:ef7eb2e8f9f7 18 * + Time Output Compare/PWM Start DMA
<> 144:ef7eb2e8f9f7 19 * + Time Input Capture Initialization
<> 144:ef7eb2e8f9f7 20 * + Time Input Capture Channel Configuration
<> 144:ef7eb2e8f9f7 21 * + Time Input Capture Start
<> 144:ef7eb2e8f9f7 22 * + Time Input Capture Start Interruption
<> 144:ef7eb2e8f9f7 23 * + Time Input Capture Start DMA
<> 144:ef7eb2e8f9f7 24 * + Time One Pulse Initialization
<> 144:ef7eb2e8f9f7 25 * + Time One Pulse Channel Configuration
<> 144:ef7eb2e8f9f7 26 * + Time One Pulse Start
<> 144:ef7eb2e8f9f7 27 * + Time Encoder Interface Initialization
<> 144:ef7eb2e8f9f7 28 * + Time Encoder Interface Start
<> 144:ef7eb2e8f9f7 29 * + Time Encoder Interface Start Interruption
<> 144:ef7eb2e8f9f7 30 * + Time Encoder Interface Start DMA
<> 144:ef7eb2e8f9f7 31 * + Commutation Event configuration with Interruption and DMA
<> 144:ef7eb2e8f9f7 32 * + Time OCRef clear configuration
<> 144:ef7eb2e8f9f7 33 * + Time External Clock configuration
<> 144:ef7eb2e8f9f7 34 @verbatim
<> 144:ef7eb2e8f9f7 35 ==============================================================================
<> 144:ef7eb2e8f9f7 36 ##### TIMER Generic features #####
<> 144:ef7eb2e8f9f7 37 ==============================================================================
<> 144:ef7eb2e8f9f7 38 [..] The Timer features include:
<> 144:ef7eb2e8f9f7 39 (#) 16-bit up, down, up/down auto-reload counter.
<> 144:ef7eb2e8f9f7 40 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
<> 144:ef7eb2e8f9f7 41 counter clock frequency either by any factor between 1 and 65536.
<> 144:ef7eb2e8f9f7 42 (#) Up to 4 independent channels for:
<> 144:ef7eb2e8f9f7 43 (++) Input Capture
<> 144:ef7eb2e8f9f7 44 (++) Output Compare
<> 144:ef7eb2e8f9f7 45 (++) PWM generation (Edge and Center-aligned Mode)
<> 144:ef7eb2e8f9f7 46 (++) One-pulse mode output
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 49 ==============================================================================
<> 144:ef7eb2e8f9f7 50 [..]
<> 144:ef7eb2e8f9f7 51 (#) Initialize the TIM low level resources by implementing the following functions
<> 144:ef7eb2e8f9f7 52 depending from feature used :
<> 144:ef7eb2e8f9f7 53 (++) Time Base : HAL_TIM_Base_MspInit()
<> 144:ef7eb2e8f9f7 54 (++) Input Capture : HAL_TIM_IC_MspInit()
<> 144:ef7eb2e8f9f7 55 (++) Output Compare : HAL_TIM_OC_MspInit()
<> 144:ef7eb2e8f9f7 56 (++) PWM generation : HAL_TIM_PWM_MspInit()
<> 144:ef7eb2e8f9f7 57 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
<> 144:ef7eb2e8f9f7 58 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 (#) Initialize the TIM low level resources :
<> 144:ef7eb2e8f9f7 61 (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 62 (##) TIM pins configuration
<> 144:ef7eb2e8f9f7 63 (+++) Enable the clock for the TIM GPIOs using the following function:
<> 144:ef7eb2e8f9f7 64 __GPIOx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 65 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 (#) The external Clock can be configured, if needed (the default clock is the
<> 144:ef7eb2e8f9f7 68 internal clock from the APBx), using the following function:
<> 144:ef7eb2e8f9f7 69 HAL_TIM_ConfigClockSource, the clock configuration should be done before
<> 144:ef7eb2e8f9f7 70 any start function.
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 (#) Configure the TIM in the desired functioning mode using one of the
<> 144:ef7eb2e8f9f7 73 initialization function of this driver:
<> 144:ef7eb2e8f9f7 74 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
<> 144:ef7eb2e8f9f7 75 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
<> 144:ef7eb2e8f9f7 76 Output Compare signal.
<> 144:ef7eb2e8f9f7 77 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
<> 144:ef7eb2e8f9f7 78 PWM signal.
<> 144:ef7eb2e8f9f7 79 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
<> 144:ef7eb2e8f9f7 80 external signal.
<> 144:ef7eb2e8f9f7 81 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
<> 144:ef7eb2e8f9f7 82 in One Pulse Mode.
<> 144:ef7eb2e8f9f7 83 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
<> 144:ef7eb2e8f9f7 86 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
<> 144:ef7eb2e8f9f7 87 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
<> 144:ef7eb2e8f9f7 88 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
<> 144:ef7eb2e8f9f7 89 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
<> 144:ef7eb2e8f9f7 90 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
<> 144:ef7eb2e8f9f7 91 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 (#) The DMA Burst is managed with the two following functions:
<> 144:ef7eb2e8f9f7 94 HAL_TIM_DMABurst_WriteStart()
<> 144:ef7eb2e8f9f7 95 HAL_TIM_DMABurst_ReadStart()
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 @endverbatim
<> 144:ef7eb2e8f9f7 98 ******************************************************************************
<> 144:ef7eb2e8f9f7 99 * @attention
<> 144:ef7eb2e8f9f7 100 *
<> 144:ef7eb2e8f9f7 101 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 102 *
<> 144:ef7eb2e8f9f7 103 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 104 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 105 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 106 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 107 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 108 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 109 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 110 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 111 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 112 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 113 *
<> 144:ef7eb2e8f9f7 114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 124 *
<> 144:ef7eb2e8f9f7 125 ******************************************************************************
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 129 #include "stm32f2xx_hal.h"
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 132 * @{
<> 144:ef7eb2e8f9f7 133 */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /** @defgroup TIM TIM
<> 144:ef7eb2e8f9f7 136 * @brief TIM HAL module driver
<> 144:ef7eb2e8f9f7 137 * @{
<> 144:ef7eb2e8f9f7 138 */
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 #ifdef HAL_TIM_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 143 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 144 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 145 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 146 /** @addtogroup TIM_Private_Functions
<> 144:ef7eb2e8f9f7 147 * @{
<> 144:ef7eb2e8f9f7 148 */
<> 144:ef7eb2e8f9f7 149 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 150 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
<> 144:ef7eb2e8f9f7 151 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
<> 144:ef7eb2e8f9f7 152 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 155 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 156 uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 157 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 158 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 159 uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 160 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 161 uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
<> 144:ef7eb2e8f9f7 164 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);
<> 144:ef7eb2e8f9f7 167 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 168 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 169 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 170 TIM_SlaveConfigTypeDef * sSlaveConfig);
<> 144:ef7eb2e8f9f7 171 /**
<> 144:ef7eb2e8f9f7 172 * @}
<> 144:ef7eb2e8f9f7 173 */
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 176 /** @defgroup TIM_Exported_Functions TIM Exported Functions
<> 144:ef7eb2e8f9f7 177 * @{
<> 144:ef7eb2e8f9f7 178 */
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions
<> 144:ef7eb2e8f9f7 181 * @brief Time Base functions
<> 144:ef7eb2e8f9f7 182 *
<> 144:ef7eb2e8f9f7 183 @verbatim
<> 144:ef7eb2e8f9f7 184 ==============================================================================
<> 144:ef7eb2e8f9f7 185 ##### Time Base functions #####
<> 144:ef7eb2e8f9f7 186 ==============================================================================
<> 144:ef7eb2e8f9f7 187 [..]
<> 144:ef7eb2e8f9f7 188 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 189 (+) Initialize and configure the TIM base.
<> 144:ef7eb2e8f9f7 190 (+) De-initialize the TIM base.
<> 144:ef7eb2e8f9f7 191 (+) Start the Time Base.
<> 144:ef7eb2e8f9f7 192 (+) Stop the Time Base.
<> 144:ef7eb2e8f9f7 193 (+) Start the Time Base and enable interrupt.
<> 144:ef7eb2e8f9f7 194 (+) Stop the Time Base and disable interrupt.
<> 144:ef7eb2e8f9f7 195 (+) Start the Time Base and enable DMA transfer.
<> 144:ef7eb2e8f9f7 196 (+) Stop the Time Base and disable DMA transfer.
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 @endverbatim
<> 144:ef7eb2e8f9f7 199 * @{
<> 144:ef7eb2e8f9f7 200 */
<> 144:ef7eb2e8f9f7 201 /**
<> 144:ef7eb2e8f9f7 202 * @brief Initializes the TIM Time base Unit according to the specified
<> 144:ef7eb2e8f9f7 203 * parameters in the TIM_HandleTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 204 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 205 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 206 * @retval HAL status
<> 144:ef7eb2e8f9f7 207 */
<> 144:ef7eb2e8f9f7 208 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 209 {
<> 144:ef7eb2e8f9f7 210 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 211 if(htim == NULL)
<> 144:ef7eb2e8f9f7 212 {
<> 144:ef7eb2e8f9f7 213 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 214 }
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /* Check the parameters */
<> 144:ef7eb2e8f9f7 217 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 218 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 219 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 222 {
<> 144:ef7eb2e8f9f7 223 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 224 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 225 /* Init the low level hardware : GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 226 HAL_TIM_Base_MspInit(htim);
<> 144:ef7eb2e8f9f7 227 }
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 230 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /* Set the Time Base configuration */
<> 144:ef7eb2e8f9f7 233 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 236 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 return HAL_OK;
<> 144:ef7eb2e8f9f7 239 }
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 /**
<> 144:ef7eb2e8f9f7 242 * @brief DeInitializes the TIM Base peripheral
<> 144:ef7eb2e8f9f7 243 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 244 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 245 * @retval HAL status
<> 144:ef7eb2e8f9f7 246 */
<> 144:ef7eb2e8f9f7 247 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 248 {
<> 144:ef7eb2e8f9f7 249 /* Check the parameters */
<> 144:ef7eb2e8f9f7 250 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 255 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 258 HAL_TIM_Base_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /* Change TIM state */
<> 144:ef7eb2e8f9f7 261 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /* Release Lock */
<> 144:ef7eb2e8f9f7 264 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 return HAL_OK;
<> 144:ef7eb2e8f9f7 267 }
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 /**
<> 144:ef7eb2e8f9f7 270 * @brief Initializes the TIM Base MSP.
<> 144:ef7eb2e8f9f7 271 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 272 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 273 * @retval None
<> 144:ef7eb2e8f9f7 274 */
<> 144:ef7eb2e8f9f7 275 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 276 {
<> 144:ef7eb2e8f9f7 277 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 278 UNUSED(htim);
<> 144:ef7eb2e8f9f7 279 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 280 the HAL_TIM_Base_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 281 */
<> 144:ef7eb2e8f9f7 282 }
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /**
<> 144:ef7eb2e8f9f7 285 * @brief DeInitializes TIM Base MSP.
<> 144:ef7eb2e8f9f7 286 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 287 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 288 * @retval None
<> 144:ef7eb2e8f9f7 289 */
<> 144:ef7eb2e8f9f7 290 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 291 {
<> 144:ef7eb2e8f9f7 292 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 293 UNUSED(htim);
<> 144:ef7eb2e8f9f7 294 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 295 the HAL_TIM_Base_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 296 */
<> 144:ef7eb2e8f9f7 297 }
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 /**
<> 144:ef7eb2e8f9f7 300 * @brief Starts the TIM Base generation.
<> 144:ef7eb2e8f9f7 301 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 302 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 303 * @retval HAL status
<> 144:ef7eb2e8f9f7 304 */
<> 144:ef7eb2e8f9f7 305 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 306 {
<> 144:ef7eb2e8f9f7 307 /* Check the parameters */
<> 144:ef7eb2e8f9f7 308 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 311 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 314 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 317 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /* Return function status */
<> 144:ef7eb2e8f9f7 320 return HAL_OK;
<> 144:ef7eb2e8f9f7 321 }
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 /**
<> 144:ef7eb2e8f9f7 324 * @brief Stops the TIM Base generation.
<> 144:ef7eb2e8f9f7 325 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 326 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 327 * @retval HAL status
<> 144:ef7eb2e8f9f7 328 */
<> 144:ef7eb2e8f9f7 329 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 330 {
<> 144:ef7eb2e8f9f7 331 /* Check the parameters */
<> 144:ef7eb2e8f9f7 332 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 335 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 338 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 341 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 /* Return function status */
<> 144:ef7eb2e8f9f7 344 return HAL_OK;
<> 144:ef7eb2e8f9f7 345 }
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 /**
<> 144:ef7eb2e8f9f7 348 * @brief Starts the TIM Base generation in interrupt mode.
<> 144:ef7eb2e8f9f7 349 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 350 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 351 * @retval HAL status
<> 144:ef7eb2e8f9f7 352 */
<> 144:ef7eb2e8f9f7 353 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 354 {
<> 144:ef7eb2e8f9f7 355 /* Check the parameters */
<> 144:ef7eb2e8f9f7 356 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 /* Enable the TIM Update interrupt */
<> 144:ef7eb2e8f9f7 359 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 362 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /* Return function status */
<> 144:ef7eb2e8f9f7 365 return HAL_OK;
<> 144:ef7eb2e8f9f7 366 }
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 /**
<> 144:ef7eb2e8f9f7 369 * @brief Stops the TIM Base generation in interrupt mode.
<> 144:ef7eb2e8f9f7 370 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 371 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 372 * @retval HAL status
<> 144:ef7eb2e8f9f7 373 */
<> 144:ef7eb2e8f9f7 374 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 375 {
<> 144:ef7eb2e8f9f7 376 /* Check the parameters */
<> 144:ef7eb2e8f9f7 377 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 378 /* Disable the TIM Update interrupt */
<> 144:ef7eb2e8f9f7 379 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 382 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 /* Return function status */
<> 144:ef7eb2e8f9f7 385 return HAL_OK;
<> 144:ef7eb2e8f9f7 386 }
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /**
<> 144:ef7eb2e8f9f7 389 * @brief Starts the TIM Base generation in DMA mode.
<> 144:ef7eb2e8f9f7 390 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 391 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 392 * @param pData: The source Buffer address.
<> 144:ef7eb2e8f9f7 393 * @param Length: The length of data to be transferred from memory to peripheral.
<> 144:ef7eb2e8f9f7 394 * @retval HAL status
<> 144:ef7eb2e8f9f7 395 */
<> 144:ef7eb2e8f9f7 396 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 397 {
<> 144:ef7eb2e8f9f7 398 /* Check the parameters */
<> 144:ef7eb2e8f9f7 399 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 402 {
<> 144:ef7eb2e8f9f7 403 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 404 }
<> 144:ef7eb2e8f9f7 405 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 406 {
<> 144:ef7eb2e8f9f7 407 if((pData == 0 ) && (Length > 0))
<> 144:ef7eb2e8f9f7 408 {
<> 144:ef7eb2e8f9f7 409 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 410 }
<> 144:ef7eb2e8f9f7 411 else
<> 144:ef7eb2e8f9f7 412 {
<> 144:ef7eb2e8f9f7 413 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 414 }
<> 144:ef7eb2e8f9f7 415 }
<> 144:ef7eb2e8f9f7 416 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 417 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 420 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 423 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 /* Enable the TIM Update DMA request */
<> 144:ef7eb2e8f9f7 426 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 429 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 /* Return function status */
<> 144:ef7eb2e8f9f7 432 return HAL_OK;
<> 144:ef7eb2e8f9f7 433 }
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 /**
<> 144:ef7eb2e8f9f7 436 * @brief Stops the TIM Base generation in DMA mode.
<> 144:ef7eb2e8f9f7 437 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 438 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 439 * @retval HAL status
<> 144:ef7eb2e8f9f7 440 */
<> 144:ef7eb2e8f9f7 441 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 442 {
<> 144:ef7eb2e8f9f7 443 /* Check the parameters */
<> 144:ef7eb2e8f9f7 444 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 /* Disable the TIM Update DMA request */
<> 144:ef7eb2e8f9f7 447 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 450 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 /* Change the htim state */
<> 144:ef7eb2e8f9f7 453 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 /* Return function status */
<> 144:ef7eb2e8f9f7 456 return HAL_OK;
<> 144:ef7eb2e8f9f7 457 }
<> 144:ef7eb2e8f9f7 458 /**
<> 144:ef7eb2e8f9f7 459 * @}
<> 144:ef7eb2e8f9f7 460 */
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
<> 144:ef7eb2e8f9f7 463 * @brief Time Output Compare functions
<> 144:ef7eb2e8f9f7 464 *
<> 144:ef7eb2e8f9f7 465 @verbatim
<> 144:ef7eb2e8f9f7 466 ==============================================================================
<> 144:ef7eb2e8f9f7 467 ##### Time Output Compare functions #####
<> 144:ef7eb2e8f9f7 468 ==============================================================================
<> 144:ef7eb2e8f9f7 469 [..]
<> 144:ef7eb2e8f9f7 470 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 471 (+) Initialize and configure the TIM Output Compare.
<> 144:ef7eb2e8f9f7 472 (+) De-initialize the TIM Output Compare.
<> 144:ef7eb2e8f9f7 473 (+) Start the Time Output Compare.
<> 144:ef7eb2e8f9f7 474 (+) Stop the Time Output Compare.
<> 144:ef7eb2e8f9f7 475 (+) Start the Time Output Compare and enable interrupt.
<> 144:ef7eb2e8f9f7 476 (+) Stop the Time Output Compare and disable interrupt.
<> 144:ef7eb2e8f9f7 477 (+) Start the Time Output Compare and enable DMA transfer.
<> 144:ef7eb2e8f9f7 478 (+) Stop the Time Output Compare and disable DMA transfer.
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 @endverbatim
<> 144:ef7eb2e8f9f7 481 * @{
<> 144:ef7eb2e8f9f7 482 */
<> 144:ef7eb2e8f9f7 483 /**
<> 144:ef7eb2e8f9f7 484 * @brief Initializes the TIM Output Compare according to the specified
<> 144:ef7eb2e8f9f7 485 * parameters in the TIM_HandleTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 486 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 487 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 488 * @retval HAL status
<> 144:ef7eb2e8f9f7 489 */
<> 144:ef7eb2e8f9f7 490 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
<> 144:ef7eb2e8f9f7 491 {
<> 144:ef7eb2e8f9f7 492 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 493 if(htim == NULL)
<> 144:ef7eb2e8f9f7 494 {
<> 144:ef7eb2e8f9f7 495 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 496 }
<> 144:ef7eb2e8f9f7 497
<> 144:ef7eb2e8f9f7 498 /* Check the parameters */
<> 144:ef7eb2e8f9f7 499 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 500 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 501 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 504 {
<> 144:ef7eb2e8f9f7 505 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 506 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 507 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 508 HAL_TIM_OC_MspInit(htim);
<> 144:ef7eb2e8f9f7 509 }
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 512 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 /* Init the base time for the Output Compare */
<> 144:ef7eb2e8f9f7 515 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 518 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 return HAL_OK;
<> 144:ef7eb2e8f9f7 521 }
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 /**
<> 144:ef7eb2e8f9f7 524 * @brief DeInitializes the TIM peripheral
<> 144:ef7eb2e8f9f7 525 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 526 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 527 * @retval HAL status
<> 144:ef7eb2e8f9f7 528 */
<> 144:ef7eb2e8f9f7 529 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 530 {
<> 144:ef7eb2e8f9f7 531 /* Check the parameters */
<> 144:ef7eb2e8f9f7 532 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 533
<> 144:ef7eb2e8f9f7 534 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 537 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 540 HAL_TIM_OC_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 /* Change TIM state */
<> 144:ef7eb2e8f9f7 543 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 /* Release Lock */
<> 144:ef7eb2e8f9f7 546 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548 return HAL_OK;
<> 144:ef7eb2e8f9f7 549 }
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 /**
<> 144:ef7eb2e8f9f7 552 * @brief Initializes the TIM Output Compare MSP.
<> 144:ef7eb2e8f9f7 553 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 554 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 555 * @retval None
<> 144:ef7eb2e8f9f7 556 */
<> 144:ef7eb2e8f9f7 557 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 558 {
<> 144:ef7eb2e8f9f7 559 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 560 UNUSED(htim);
<> 144:ef7eb2e8f9f7 561 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 562 the HAL_TIM_OC_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 563 */
<> 144:ef7eb2e8f9f7 564 }
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 /**
<> 144:ef7eb2e8f9f7 567 * @brief DeInitializes TIM Output Compare MSP.
<> 144:ef7eb2e8f9f7 568 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 569 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 570 * @retval None
<> 144:ef7eb2e8f9f7 571 */
<> 144:ef7eb2e8f9f7 572 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 573 {
<> 144:ef7eb2e8f9f7 574 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 575 UNUSED(htim);
<> 144:ef7eb2e8f9f7 576 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 577 the HAL_TIM_OC_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 578 */
<> 144:ef7eb2e8f9f7 579 }
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 /**
<> 144:ef7eb2e8f9f7 582 * @brief Starts the TIM Output Compare signal generation.
<> 144:ef7eb2e8f9f7 583 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 584 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 585 * @param Channel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 586 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 587 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 588 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 589 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 590 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 591 * @retval HAL status
<> 144:ef7eb2e8f9f7 592 */
<> 144:ef7eb2e8f9f7 593 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 594 {
<> 144:ef7eb2e8f9f7 595 /* Check the parameters */
<> 144:ef7eb2e8f9f7 596 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 /* Enable the Output compare channel */
<> 144:ef7eb2e8f9f7 599 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 602 {
<> 144:ef7eb2e8f9f7 603 /* Enable the main output */
<> 144:ef7eb2e8f9f7 604 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 605 }
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 608 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610 /* Return function status */
<> 144:ef7eb2e8f9f7 611 return HAL_OK;
<> 144:ef7eb2e8f9f7 612 }
<> 144:ef7eb2e8f9f7 613
<> 144:ef7eb2e8f9f7 614 /**
<> 144:ef7eb2e8f9f7 615 * @brief Stops the TIM Output Compare signal generation.
<> 144:ef7eb2e8f9f7 616 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 617 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 618 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 619 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 620 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 621 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 622 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 623 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 624 * @retval HAL status
<> 144:ef7eb2e8f9f7 625 */
<> 144:ef7eb2e8f9f7 626 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 627 {
<> 144:ef7eb2e8f9f7 628 /* Check the parameters */
<> 144:ef7eb2e8f9f7 629 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 630
<> 144:ef7eb2e8f9f7 631 /* Disable the Output compare channel */
<> 144:ef7eb2e8f9f7 632 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 635 {
<> 144:ef7eb2e8f9f7 636 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 637 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 638 }
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 641 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 /* Return function status */
<> 144:ef7eb2e8f9f7 644 return HAL_OK;
<> 144:ef7eb2e8f9f7 645 }
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 /**
<> 144:ef7eb2e8f9f7 648 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
<> 144:ef7eb2e8f9f7 649 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 650 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 651 * @param Channel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 652 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 653 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 654 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 655 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 656 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 657 * @retval HAL status
<> 144:ef7eb2e8f9f7 658 */
<> 144:ef7eb2e8f9f7 659 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 660 {
<> 144:ef7eb2e8f9f7 661 /* Check the parameters */
<> 144:ef7eb2e8f9f7 662 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 switch (Channel)
<> 144:ef7eb2e8f9f7 665 {
<> 144:ef7eb2e8f9f7 666 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 667 {
<> 144:ef7eb2e8f9f7 668 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 669 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 670 }
<> 144:ef7eb2e8f9f7 671 break;
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 674 {
<> 144:ef7eb2e8f9f7 675 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 676 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 677 }
<> 144:ef7eb2e8f9f7 678 break;
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 681 {
<> 144:ef7eb2e8f9f7 682 /* Enable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 683 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 684 }
<> 144:ef7eb2e8f9f7 685 break;
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 688 {
<> 144:ef7eb2e8f9f7 689 /* Enable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 690 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 691 }
<> 144:ef7eb2e8f9f7 692 break;
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 default:
<> 144:ef7eb2e8f9f7 695 break;
<> 144:ef7eb2e8f9f7 696 }
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 /* Enable the Output compare channel */
<> 144:ef7eb2e8f9f7 699 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 700
<> 144:ef7eb2e8f9f7 701 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 702 {
<> 144:ef7eb2e8f9f7 703 /* Enable the main output */
<> 144:ef7eb2e8f9f7 704 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 705 }
<> 144:ef7eb2e8f9f7 706
<> 144:ef7eb2e8f9f7 707 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 708 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 709
<> 144:ef7eb2e8f9f7 710 /* Return function status */
<> 144:ef7eb2e8f9f7 711 return HAL_OK;
<> 144:ef7eb2e8f9f7 712 }
<> 144:ef7eb2e8f9f7 713
<> 144:ef7eb2e8f9f7 714 /**
<> 144:ef7eb2e8f9f7 715 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
<> 144:ef7eb2e8f9f7 716 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 717 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 718 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 719 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 720 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 721 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 722 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 723 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 724 * @retval HAL status
<> 144:ef7eb2e8f9f7 725 */
<> 144:ef7eb2e8f9f7 726 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 727 {
<> 144:ef7eb2e8f9f7 728 /* Check the parameters */
<> 144:ef7eb2e8f9f7 729 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 switch (Channel)
<> 144:ef7eb2e8f9f7 732 {
<> 144:ef7eb2e8f9f7 733 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 734 {
<> 144:ef7eb2e8f9f7 735 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 736 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 737 }
<> 144:ef7eb2e8f9f7 738 break;
<> 144:ef7eb2e8f9f7 739
<> 144:ef7eb2e8f9f7 740 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 741 {
<> 144:ef7eb2e8f9f7 742 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 743 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 744 }
<> 144:ef7eb2e8f9f7 745 break;
<> 144:ef7eb2e8f9f7 746
<> 144:ef7eb2e8f9f7 747 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 748 {
<> 144:ef7eb2e8f9f7 749 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 750 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 751 }
<> 144:ef7eb2e8f9f7 752 break;
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 755 {
<> 144:ef7eb2e8f9f7 756 /* Disable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 757 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 758 }
<> 144:ef7eb2e8f9f7 759 break;
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761 default:
<> 144:ef7eb2e8f9f7 762 break;
<> 144:ef7eb2e8f9f7 763 }
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765 /* Disable the Output compare channel */
<> 144:ef7eb2e8f9f7 766 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 767
<> 144:ef7eb2e8f9f7 768 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 769 {
<> 144:ef7eb2e8f9f7 770 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 771 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 772 }
<> 144:ef7eb2e8f9f7 773
<> 144:ef7eb2e8f9f7 774 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 775 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 776
<> 144:ef7eb2e8f9f7 777 /* Return function status */
<> 144:ef7eb2e8f9f7 778 return HAL_OK;
<> 144:ef7eb2e8f9f7 779 }
<> 144:ef7eb2e8f9f7 780
<> 144:ef7eb2e8f9f7 781 /**
<> 144:ef7eb2e8f9f7 782 * @brief Starts the TIM Output Compare signal generation in DMA mode.
<> 144:ef7eb2e8f9f7 783 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 784 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 785 * @param Channel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 786 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 787 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 788 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 789 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 790 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 791 * @param pData: The source Buffer address.
<> 144:ef7eb2e8f9f7 792 * @param Length: The length of data to be transferred from memory to TIM peripheral
<> 144:ef7eb2e8f9f7 793 * @retval HAL status
<> 144:ef7eb2e8f9f7 794 */
<> 144:ef7eb2e8f9f7 795 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 796 {
<> 144:ef7eb2e8f9f7 797 /* Check the parameters */
<> 144:ef7eb2e8f9f7 798 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 801 {
<> 144:ef7eb2e8f9f7 802 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 803 }
<> 144:ef7eb2e8f9f7 804 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 805 {
<> 144:ef7eb2e8f9f7 806 if(((uint32_t)pData == 0U ) && (Length > 0U))
<> 144:ef7eb2e8f9f7 807 {
<> 144:ef7eb2e8f9f7 808 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 809 }
<> 144:ef7eb2e8f9f7 810 else
<> 144:ef7eb2e8f9f7 811 {
<> 144:ef7eb2e8f9f7 812 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 813 }
<> 144:ef7eb2e8f9f7 814 }
<> 144:ef7eb2e8f9f7 815 switch (Channel)
<> 144:ef7eb2e8f9f7 816 {
<> 144:ef7eb2e8f9f7 817 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 818 {
<> 144:ef7eb2e8f9f7 819 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 820 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 821
<> 144:ef7eb2e8f9f7 822 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 823 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 824
<> 144:ef7eb2e8f9f7 825 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 826 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<> 144:ef7eb2e8f9f7 827
<> 144:ef7eb2e8f9f7 828 /* Enable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 829 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 830 }
<> 144:ef7eb2e8f9f7 831 break;
<> 144:ef7eb2e8f9f7 832
<> 144:ef7eb2e8f9f7 833 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 834 {
<> 144:ef7eb2e8f9f7 835 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 836 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 837
<> 144:ef7eb2e8f9f7 838 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 839 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 840
<> 144:ef7eb2e8f9f7 841 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 842 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<> 144:ef7eb2e8f9f7 843
<> 144:ef7eb2e8f9f7 844 /* Enable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 845 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 846 }
<> 144:ef7eb2e8f9f7 847 break;
<> 144:ef7eb2e8f9f7 848
<> 144:ef7eb2e8f9f7 849 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 850 {
<> 144:ef7eb2e8f9f7 851 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 852 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 853
<> 144:ef7eb2e8f9f7 854 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 855 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 856
<> 144:ef7eb2e8f9f7 857 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 858 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<> 144:ef7eb2e8f9f7 859
<> 144:ef7eb2e8f9f7 860 /* Enable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 861 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 862 }
<> 144:ef7eb2e8f9f7 863 break;
<> 144:ef7eb2e8f9f7 864
<> 144:ef7eb2e8f9f7 865 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 866 {
<> 144:ef7eb2e8f9f7 867 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 868 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 869
<> 144:ef7eb2e8f9f7 870 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 871 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 872
<> 144:ef7eb2e8f9f7 873 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 874 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<> 144:ef7eb2e8f9f7 875
<> 144:ef7eb2e8f9f7 876 /* Enable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 877 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 878 }
<> 144:ef7eb2e8f9f7 879 break;
<> 144:ef7eb2e8f9f7 880
<> 144:ef7eb2e8f9f7 881 default:
<> 144:ef7eb2e8f9f7 882 break;
<> 144:ef7eb2e8f9f7 883 }
<> 144:ef7eb2e8f9f7 884
<> 144:ef7eb2e8f9f7 885 /* Enable the Output compare channel */
<> 144:ef7eb2e8f9f7 886 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 887
<> 144:ef7eb2e8f9f7 888 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 889 {
<> 144:ef7eb2e8f9f7 890 /* Enable the main output */
<> 144:ef7eb2e8f9f7 891 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 892 }
<> 144:ef7eb2e8f9f7 893
<> 144:ef7eb2e8f9f7 894 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 895 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 /* Return function status */
<> 144:ef7eb2e8f9f7 898 return HAL_OK;
<> 144:ef7eb2e8f9f7 899 }
<> 144:ef7eb2e8f9f7 900
<> 144:ef7eb2e8f9f7 901 /**
<> 144:ef7eb2e8f9f7 902 * @brief Stops the TIM Output Compare signal generation in DMA mode.
<> 144:ef7eb2e8f9f7 903 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 904 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 905 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 906 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 907 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 908 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 909 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 910 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 911 * @retval HAL status
<> 144:ef7eb2e8f9f7 912 */
<> 144:ef7eb2e8f9f7 913 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 914 {
<> 144:ef7eb2e8f9f7 915 /* Check the parameters */
<> 144:ef7eb2e8f9f7 916 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 917
<> 144:ef7eb2e8f9f7 918 switch (Channel)
<> 144:ef7eb2e8f9f7 919 {
<> 144:ef7eb2e8f9f7 920 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 921 {
<> 144:ef7eb2e8f9f7 922 /* Disable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 923 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 924 }
<> 144:ef7eb2e8f9f7 925 break;
<> 144:ef7eb2e8f9f7 926
<> 144:ef7eb2e8f9f7 927 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 928 {
<> 144:ef7eb2e8f9f7 929 /* Disable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 930 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 931 }
<> 144:ef7eb2e8f9f7 932 break;
<> 144:ef7eb2e8f9f7 933
<> 144:ef7eb2e8f9f7 934 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 935 {
<> 144:ef7eb2e8f9f7 936 /* Disable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 937 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 938 }
<> 144:ef7eb2e8f9f7 939 break;
<> 144:ef7eb2e8f9f7 940
<> 144:ef7eb2e8f9f7 941 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 942 {
<> 144:ef7eb2e8f9f7 943 /* Disable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 944 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 945 }
<> 144:ef7eb2e8f9f7 946 break;
<> 144:ef7eb2e8f9f7 947
<> 144:ef7eb2e8f9f7 948 default:
<> 144:ef7eb2e8f9f7 949 break;
<> 144:ef7eb2e8f9f7 950 }
<> 144:ef7eb2e8f9f7 951
<> 144:ef7eb2e8f9f7 952 /* Disable the Output compare channel */
<> 144:ef7eb2e8f9f7 953 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 954
<> 144:ef7eb2e8f9f7 955 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 956 {
<> 144:ef7eb2e8f9f7 957 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 958 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 959 }
<> 144:ef7eb2e8f9f7 960
<> 144:ef7eb2e8f9f7 961 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 962 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 963
<> 144:ef7eb2e8f9f7 964 /* Change the htim state */
<> 144:ef7eb2e8f9f7 965 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 966
<> 144:ef7eb2e8f9f7 967 /* Return function status */
<> 144:ef7eb2e8f9f7 968 return HAL_OK;
<> 144:ef7eb2e8f9f7 969 }
<> 144:ef7eb2e8f9f7 970 /**
<> 144:ef7eb2e8f9f7 971 * @}
<> 144:ef7eb2e8f9f7 972 */
<> 144:ef7eb2e8f9f7 973
<> 144:ef7eb2e8f9f7 974 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
<> 144:ef7eb2e8f9f7 975 * @brief Time PWM functions
<> 144:ef7eb2e8f9f7 976 *
<> 144:ef7eb2e8f9f7 977 @verbatim
<> 144:ef7eb2e8f9f7 978 ==============================================================================
<> 144:ef7eb2e8f9f7 979 ##### Time PWM functions #####
<> 144:ef7eb2e8f9f7 980 ==============================================================================
<> 144:ef7eb2e8f9f7 981 [..]
<> 144:ef7eb2e8f9f7 982 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 983 (+) Initialize and configure the TIM OPWM.
<> 144:ef7eb2e8f9f7 984 (+) De-initialize the TIM PWM.
<> 144:ef7eb2e8f9f7 985 (+) Start the Time PWM.
<> 144:ef7eb2e8f9f7 986 (+) Stop the Time PWM.
<> 144:ef7eb2e8f9f7 987 (+) Start the Time PWM and enable interrupt.
<> 144:ef7eb2e8f9f7 988 (+) Stop the Time PWM and disable interrupt.
<> 144:ef7eb2e8f9f7 989 (+) Start the Time PWM and enable DMA transfer.
<> 144:ef7eb2e8f9f7 990 (+) Stop the Time PWM and disable DMA transfer.
<> 144:ef7eb2e8f9f7 991
<> 144:ef7eb2e8f9f7 992 @endverbatim
<> 144:ef7eb2e8f9f7 993 * @{
<> 144:ef7eb2e8f9f7 994 */
<> 144:ef7eb2e8f9f7 995 /**
<> 144:ef7eb2e8f9f7 996 * @brief Initializes the TIM PWM Time Base according to the specified
<> 144:ef7eb2e8f9f7 997 * parameters in the TIM_HandleTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 998 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 999 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1000 * @retval HAL status
<> 144:ef7eb2e8f9f7 1001 */
<> 144:ef7eb2e8f9f7 1002 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1003 {
<> 144:ef7eb2e8f9f7 1004 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 1005 if(htim == NULL)
<> 144:ef7eb2e8f9f7 1006 {
<> 144:ef7eb2e8f9f7 1007 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1008 }
<> 144:ef7eb2e8f9f7 1009
<> 144:ef7eb2e8f9f7 1010 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1011 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1012 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 1013 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 144:ef7eb2e8f9f7 1014
<> 144:ef7eb2e8f9f7 1015 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 1016 {
<> 144:ef7eb2e8f9f7 1017 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 1018 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 1019 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 1020 HAL_TIM_PWM_MspInit(htim);
<> 144:ef7eb2e8f9f7 1021 }
<> 144:ef7eb2e8f9f7 1022
<> 144:ef7eb2e8f9f7 1023 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 1024 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1025
<> 144:ef7eb2e8f9f7 1026 /* Init the base time for the PWM */
<> 144:ef7eb2e8f9f7 1027 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 1028
<> 144:ef7eb2e8f9f7 1029 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 1030 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1031
<> 144:ef7eb2e8f9f7 1032 return HAL_OK;
<> 144:ef7eb2e8f9f7 1033 }
<> 144:ef7eb2e8f9f7 1034
<> 144:ef7eb2e8f9f7 1035 /**
<> 144:ef7eb2e8f9f7 1036 * @brief DeInitializes the TIM peripheral
<> 144:ef7eb2e8f9f7 1037 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1038 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1039 * @retval HAL status
<> 144:ef7eb2e8f9f7 1040 */
<> 144:ef7eb2e8f9f7 1041 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1042 {
<> 144:ef7eb2e8f9f7 1043 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1044 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1045
<> 144:ef7eb2e8f9f7 1046 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1047
<> 144:ef7eb2e8f9f7 1048 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 1049 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1050
<> 144:ef7eb2e8f9f7 1051 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 1052 HAL_TIM_PWM_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 1053
<> 144:ef7eb2e8f9f7 1054 /* Change TIM state */
<> 144:ef7eb2e8f9f7 1055 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 1056
<> 144:ef7eb2e8f9f7 1057 /* Release Lock */
<> 144:ef7eb2e8f9f7 1058 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1059
<> 144:ef7eb2e8f9f7 1060 return HAL_OK;
<> 144:ef7eb2e8f9f7 1061 }
<> 144:ef7eb2e8f9f7 1062
<> 144:ef7eb2e8f9f7 1063 /**
<> 144:ef7eb2e8f9f7 1064 * @brief Initializes the TIM PWM MSP.
<> 144:ef7eb2e8f9f7 1065 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1066 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1067 * @retval None
<> 144:ef7eb2e8f9f7 1068 */
<> 144:ef7eb2e8f9f7 1069 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1070 {
<> 144:ef7eb2e8f9f7 1071 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1072 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1073 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1074 the HAL_TIM_PWM_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 1075 */
<> 144:ef7eb2e8f9f7 1076 }
<> 144:ef7eb2e8f9f7 1077
<> 144:ef7eb2e8f9f7 1078 /**
<> 144:ef7eb2e8f9f7 1079 * @brief DeInitializes TIM PWM MSP.
<> 144:ef7eb2e8f9f7 1080 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1081 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1082 * @retval None
<> 144:ef7eb2e8f9f7 1083 */
<> 144:ef7eb2e8f9f7 1084 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1085 {
<> 144:ef7eb2e8f9f7 1086 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1087 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1088 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1089 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 1090 */
<> 144:ef7eb2e8f9f7 1091 }
<> 144:ef7eb2e8f9f7 1092
<> 144:ef7eb2e8f9f7 1093 /**
<> 144:ef7eb2e8f9f7 1094 * @brief Starts the PWM signal generation.
<> 144:ef7eb2e8f9f7 1095 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1096 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1097 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 1098 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1099 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1100 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1101 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1102 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1103 * @retval HAL status
<> 144:ef7eb2e8f9f7 1104 */
<> 144:ef7eb2e8f9f7 1105 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1106 {
<> 144:ef7eb2e8f9f7 1107 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1108 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1109
<> 144:ef7eb2e8f9f7 1110 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1111 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1112
<> 144:ef7eb2e8f9f7 1113 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 1114 {
<> 144:ef7eb2e8f9f7 1115 /* Enable the main output */
<> 144:ef7eb2e8f9f7 1116 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1117 }
<> 144:ef7eb2e8f9f7 1118
<> 144:ef7eb2e8f9f7 1119 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1120 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1121
<> 144:ef7eb2e8f9f7 1122 /* Return function status */
<> 144:ef7eb2e8f9f7 1123 return HAL_OK;
<> 144:ef7eb2e8f9f7 1124 }
<> 144:ef7eb2e8f9f7 1125
<> 144:ef7eb2e8f9f7 1126 /**
<> 144:ef7eb2e8f9f7 1127 * @brief Stops the PWM signal generation.
<> 144:ef7eb2e8f9f7 1128 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1129 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1130 * @param Channel: TIM Channels to be disabled.
<> 144:ef7eb2e8f9f7 1131 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1132 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1133 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1134 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1135 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1136 * @retval HAL status
<> 144:ef7eb2e8f9f7 1137 */
<> 144:ef7eb2e8f9f7 1138 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1139 {
<> 144:ef7eb2e8f9f7 1140 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1141 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1142
<> 144:ef7eb2e8f9f7 1143 /* Disable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1144 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1145
<> 144:ef7eb2e8f9f7 1146 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 1147 {
<> 144:ef7eb2e8f9f7 1148 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 1149 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1150 }
<> 144:ef7eb2e8f9f7 1151
<> 144:ef7eb2e8f9f7 1152 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1153 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1154
<> 144:ef7eb2e8f9f7 1155 /* Change the htim state */
<> 144:ef7eb2e8f9f7 1156 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1157
<> 144:ef7eb2e8f9f7 1158 /* Return function status */
<> 144:ef7eb2e8f9f7 1159 return HAL_OK;
<> 144:ef7eb2e8f9f7 1160 }
<> 144:ef7eb2e8f9f7 1161
<> 144:ef7eb2e8f9f7 1162 /**
<> 144:ef7eb2e8f9f7 1163 * @brief Starts the PWM signal generation in interrupt mode.
<> 144:ef7eb2e8f9f7 1164 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1165 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1166 * @param Channel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 1167 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1168 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1169 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1170 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1171 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1172 * @retval HAL status
<> 144:ef7eb2e8f9f7 1173 */
<> 144:ef7eb2e8f9f7 1174 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1175 {
<> 144:ef7eb2e8f9f7 1176 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1177 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1178
<> 144:ef7eb2e8f9f7 1179 switch (Channel)
<> 144:ef7eb2e8f9f7 1180 {
<> 144:ef7eb2e8f9f7 1181 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1182 {
<> 144:ef7eb2e8f9f7 1183 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1184 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1185 }
<> 144:ef7eb2e8f9f7 1186 break;
<> 144:ef7eb2e8f9f7 1187
<> 144:ef7eb2e8f9f7 1188 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1189 {
<> 144:ef7eb2e8f9f7 1190 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1191 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1192 }
<> 144:ef7eb2e8f9f7 1193 break;
<> 144:ef7eb2e8f9f7 1194
<> 144:ef7eb2e8f9f7 1195 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1196 {
<> 144:ef7eb2e8f9f7 1197 /* Enable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1198 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1199 }
<> 144:ef7eb2e8f9f7 1200 break;
<> 144:ef7eb2e8f9f7 1201
<> 144:ef7eb2e8f9f7 1202 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1203 {
<> 144:ef7eb2e8f9f7 1204 /* Enable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1205 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1206 }
<> 144:ef7eb2e8f9f7 1207 break;
<> 144:ef7eb2e8f9f7 1208
<> 144:ef7eb2e8f9f7 1209 default:
<> 144:ef7eb2e8f9f7 1210 break;
<> 144:ef7eb2e8f9f7 1211 }
<> 144:ef7eb2e8f9f7 1212
<> 144:ef7eb2e8f9f7 1213 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1214 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1215
<> 144:ef7eb2e8f9f7 1216 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 1217 {
<> 144:ef7eb2e8f9f7 1218 /* Enable the main output */
<> 144:ef7eb2e8f9f7 1219 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1220 }
<> 144:ef7eb2e8f9f7 1221
<> 144:ef7eb2e8f9f7 1222 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1223 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1224
<> 144:ef7eb2e8f9f7 1225 /* Return function status */
<> 144:ef7eb2e8f9f7 1226 return HAL_OK;
<> 144:ef7eb2e8f9f7 1227 }
<> 144:ef7eb2e8f9f7 1228
<> 144:ef7eb2e8f9f7 1229 /**
<> 144:ef7eb2e8f9f7 1230 * @brief Stops the PWM signal generation in interrupt mode.
<> 144:ef7eb2e8f9f7 1231 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1232 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1233 * @param Channel: TIM Channels to be disabled.
<> 144:ef7eb2e8f9f7 1234 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1235 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1236 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1237 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1238 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1239 * @retval HAL status
<> 144:ef7eb2e8f9f7 1240 */
<> 144:ef7eb2e8f9f7 1241 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1242 {
<> 144:ef7eb2e8f9f7 1243 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1244 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1245
<> 144:ef7eb2e8f9f7 1246 switch (Channel)
<> 144:ef7eb2e8f9f7 1247 {
<> 144:ef7eb2e8f9f7 1248 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1249 {
<> 144:ef7eb2e8f9f7 1250 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1251 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1252 }
<> 144:ef7eb2e8f9f7 1253 break;
<> 144:ef7eb2e8f9f7 1254
<> 144:ef7eb2e8f9f7 1255 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1256 {
<> 144:ef7eb2e8f9f7 1257 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1258 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1259 }
<> 144:ef7eb2e8f9f7 1260 break;
<> 144:ef7eb2e8f9f7 1261
<> 144:ef7eb2e8f9f7 1262 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1263 {
<> 144:ef7eb2e8f9f7 1264 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1265 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1266 }
<> 144:ef7eb2e8f9f7 1267 break;
<> 144:ef7eb2e8f9f7 1268
<> 144:ef7eb2e8f9f7 1269 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1270 {
<> 144:ef7eb2e8f9f7 1271 /* Disable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1272 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1273 }
<> 144:ef7eb2e8f9f7 1274 break;
<> 144:ef7eb2e8f9f7 1275
<> 144:ef7eb2e8f9f7 1276 default:
<> 144:ef7eb2e8f9f7 1277 break;
<> 144:ef7eb2e8f9f7 1278 }
<> 144:ef7eb2e8f9f7 1279
<> 144:ef7eb2e8f9f7 1280 /* Disable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1281 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1282
<> 144:ef7eb2e8f9f7 1283 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 1284 {
<> 144:ef7eb2e8f9f7 1285 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 1286 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1287 }
<> 144:ef7eb2e8f9f7 1288
<> 144:ef7eb2e8f9f7 1289 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1290 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1291
<> 144:ef7eb2e8f9f7 1292 /* Return function status */
<> 144:ef7eb2e8f9f7 1293 return HAL_OK;
<> 144:ef7eb2e8f9f7 1294 }
<> 144:ef7eb2e8f9f7 1295
<> 144:ef7eb2e8f9f7 1296 /**
<> 144:ef7eb2e8f9f7 1297 * @brief Starts the TIM PWM signal generation in DMA mode.
<> 144:ef7eb2e8f9f7 1298 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1299 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1300 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 1301 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1302 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1303 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1304 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1305 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1306 * @param pData: The source Buffer address.
<> 144:ef7eb2e8f9f7 1307 * @param Length: The length of data to be transferred from memory to TIM peripheral
<> 144:ef7eb2e8f9f7 1308 * @retval HAL status
<> 144:ef7eb2e8f9f7 1309 */
<> 144:ef7eb2e8f9f7 1310 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 1311 {
<> 144:ef7eb2e8f9f7 1312 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1313 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1314
<> 144:ef7eb2e8f9f7 1315 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 1316 {
<> 144:ef7eb2e8f9f7 1317 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1318 }
<> 144:ef7eb2e8f9f7 1319 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 1320 {
<> 144:ef7eb2e8f9f7 1321 if(((uint32_t)pData == 0U ) && (Length > 0U))
<> 144:ef7eb2e8f9f7 1322 {
<> 144:ef7eb2e8f9f7 1323 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1324 }
<> 144:ef7eb2e8f9f7 1325 else
<> 144:ef7eb2e8f9f7 1326 {
<> 144:ef7eb2e8f9f7 1327 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1328 }
<> 144:ef7eb2e8f9f7 1329 }
<> 144:ef7eb2e8f9f7 1330 switch (Channel)
<> 144:ef7eb2e8f9f7 1331 {
<> 144:ef7eb2e8f9f7 1332 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1333 {
<> 144:ef7eb2e8f9f7 1334 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1335 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1336
<> 144:ef7eb2e8f9f7 1337 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1338 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1339
<> 144:ef7eb2e8f9f7 1340 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1341 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<> 144:ef7eb2e8f9f7 1342
<> 144:ef7eb2e8f9f7 1343 /* Enable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1344 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1345 }
<> 144:ef7eb2e8f9f7 1346 break;
<> 144:ef7eb2e8f9f7 1347
<> 144:ef7eb2e8f9f7 1348 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1349 {
<> 144:ef7eb2e8f9f7 1350 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1351 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1352
<> 144:ef7eb2e8f9f7 1353 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1354 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1355
<> 144:ef7eb2e8f9f7 1356 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1357 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<> 144:ef7eb2e8f9f7 1358
<> 144:ef7eb2e8f9f7 1359 /* Enable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1360 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1361 }
<> 144:ef7eb2e8f9f7 1362 break;
<> 144:ef7eb2e8f9f7 1363
<> 144:ef7eb2e8f9f7 1364 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1365 {
<> 144:ef7eb2e8f9f7 1366 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1367 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1368
<> 144:ef7eb2e8f9f7 1369 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1370 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1371
<> 144:ef7eb2e8f9f7 1372 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1373 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<> 144:ef7eb2e8f9f7 1374
<> 144:ef7eb2e8f9f7 1375 /* Enable the TIM Output Capture/Compare 3 request */
<> 144:ef7eb2e8f9f7 1376 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1377 }
<> 144:ef7eb2e8f9f7 1378 break;
<> 144:ef7eb2e8f9f7 1379
<> 144:ef7eb2e8f9f7 1380 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1381 {
<> 144:ef7eb2e8f9f7 1382 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1383 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1384
<> 144:ef7eb2e8f9f7 1385 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1386 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1387
<> 144:ef7eb2e8f9f7 1388 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1389 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<> 144:ef7eb2e8f9f7 1390
<> 144:ef7eb2e8f9f7 1391 /* Enable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1392 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1393 }
<> 144:ef7eb2e8f9f7 1394 break;
<> 144:ef7eb2e8f9f7 1395
<> 144:ef7eb2e8f9f7 1396 default:
<> 144:ef7eb2e8f9f7 1397 break;
<> 144:ef7eb2e8f9f7 1398 }
<> 144:ef7eb2e8f9f7 1399
<> 144:ef7eb2e8f9f7 1400 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1401 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1402
<> 144:ef7eb2e8f9f7 1403 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 1404 {
<> 144:ef7eb2e8f9f7 1405 /* Enable the main output */
<> 144:ef7eb2e8f9f7 1406 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1407 }
<> 144:ef7eb2e8f9f7 1408
<> 144:ef7eb2e8f9f7 1409 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1410 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1411
<> 144:ef7eb2e8f9f7 1412 /* Return function status */
<> 144:ef7eb2e8f9f7 1413 return HAL_OK;
<> 144:ef7eb2e8f9f7 1414 }
<> 144:ef7eb2e8f9f7 1415
<> 144:ef7eb2e8f9f7 1416 /**
<> 144:ef7eb2e8f9f7 1417 * @brief Stops the TIM PWM signal generation in DMA mode.
<> 144:ef7eb2e8f9f7 1418 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1419 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1420 * @param Channel: TIM Channels to be disabled.
<> 144:ef7eb2e8f9f7 1421 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1422 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1423 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1424 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1425 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1426 * @retval HAL status
<> 144:ef7eb2e8f9f7 1427 */
<> 144:ef7eb2e8f9f7 1428 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1429 {
<> 144:ef7eb2e8f9f7 1430 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1431 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1432
<> 144:ef7eb2e8f9f7 1433 switch (Channel)
<> 144:ef7eb2e8f9f7 1434 {
<> 144:ef7eb2e8f9f7 1435 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1436 {
<> 144:ef7eb2e8f9f7 1437 /* Disable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1438 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1439 }
<> 144:ef7eb2e8f9f7 1440 break;
<> 144:ef7eb2e8f9f7 1441
<> 144:ef7eb2e8f9f7 1442 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1443 {
<> 144:ef7eb2e8f9f7 1444 /* Disable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1445 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1446 }
<> 144:ef7eb2e8f9f7 1447 break;
<> 144:ef7eb2e8f9f7 1448
<> 144:ef7eb2e8f9f7 1449 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1450 {
<> 144:ef7eb2e8f9f7 1451 /* Disable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1452 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1453 }
<> 144:ef7eb2e8f9f7 1454 break;
<> 144:ef7eb2e8f9f7 1455
<> 144:ef7eb2e8f9f7 1456 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1457 {
<> 144:ef7eb2e8f9f7 1458 /* Disable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1459 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1460 }
<> 144:ef7eb2e8f9f7 1461 break;
<> 144:ef7eb2e8f9f7 1462
<> 144:ef7eb2e8f9f7 1463 default:
<> 144:ef7eb2e8f9f7 1464 break;
<> 144:ef7eb2e8f9f7 1465 }
<> 144:ef7eb2e8f9f7 1466
<> 144:ef7eb2e8f9f7 1467 /* Disable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1468 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1469
<> 144:ef7eb2e8f9f7 1470 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 1471 {
<> 144:ef7eb2e8f9f7 1472 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 1473 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1474 }
<> 144:ef7eb2e8f9f7 1475
<> 144:ef7eb2e8f9f7 1476 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1477 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1478
<> 144:ef7eb2e8f9f7 1479 /* Change the htim state */
<> 144:ef7eb2e8f9f7 1480 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1481
<> 144:ef7eb2e8f9f7 1482 /* Return function status */
<> 144:ef7eb2e8f9f7 1483 return HAL_OK;
<> 144:ef7eb2e8f9f7 1484 }
<> 144:ef7eb2e8f9f7 1485 /**
<> 144:ef7eb2e8f9f7 1486 * @}
<> 144:ef7eb2e8f9f7 1487 */
<> 144:ef7eb2e8f9f7 1488
<> 144:ef7eb2e8f9f7 1489 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
<> 144:ef7eb2e8f9f7 1490 * @brief Time Input Capture functions
<> 144:ef7eb2e8f9f7 1491 *
<> 144:ef7eb2e8f9f7 1492 @verbatim
<> 144:ef7eb2e8f9f7 1493 ==============================================================================
<> 144:ef7eb2e8f9f7 1494 ##### Time Input Capture functions #####
<> 144:ef7eb2e8f9f7 1495 ==============================================================================
<> 144:ef7eb2e8f9f7 1496 [..]
<> 144:ef7eb2e8f9f7 1497 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1498 (+) Initialize and configure the TIM Input Capture.
<> 144:ef7eb2e8f9f7 1499 (+) De-initialize the TIM Input Capture.
<> 144:ef7eb2e8f9f7 1500 (+) Start the Time Input Capture.
<> 144:ef7eb2e8f9f7 1501 (+) Stop the Time Input Capture.
<> 144:ef7eb2e8f9f7 1502 (+) Start the Time Input Capture and enable interrupt.
<> 144:ef7eb2e8f9f7 1503 (+) Stop the Time Input Capture and disable interrupt.
<> 144:ef7eb2e8f9f7 1504 (+) Start the Time Input Capture and enable DMA transfer.
<> 144:ef7eb2e8f9f7 1505 (+) Stop the Time Input Capture and disable DMA transfer.
<> 144:ef7eb2e8f9f7 1506
<> 144:ef7eb2e8f9f7 1507 @endverbatim
<> 144:ef7eb2e8f9f7 1508 * @{
<> 144:ef7eb2e8f9f7 1509 */
<> 144:ef7eb2e8f9f7 1510 /**
<> 144:ef7eb2e8f9f7 1511 * @brief Initializes the TIM Input Capture Time base according to the specified
<> 144:ef7eb2e8f9f7 1512 * parameters in the TIM_HandleTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 1513 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1514 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1515 * @retval HAL status
<> 144:ef7eb2e8f9f7 1516 */
<> 144:ef7eb2e8f9f7 1517 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1518 {
<> 144:ef7eb2e8f9f7 1519 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 1520 if(htim == NULL)
<> 144:ef7eb2e8f9f7 1521 {
<> 144:ef7eb2e8f9f7 1522 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1523 }
<> 144:ef7eb2e8f9f7 1524
<> 144:ef7eb2e8f9f7 1525 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1526 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1527 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 1528 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 144:ef7eb2e8f9f7 1529
<> 144:ef7eb2e8f9f7 1530 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 1531 {
<> 144:ef7eb2e8f9f7 1532 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 1533 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 1534 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 1535 HAL_TIM_IC_MspInit(htim);
<> 144:ef7eb2e8f9f7 1536 }
<> 144:ef7eb2e8f9f7 1537
<> 144:ef7eb2e8f9f7 1538 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 1539 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1540
<> 144:ef7eb2e8f9f7 1541 /* Init the base time for the input capture */
<> 144:ef7eb2e8f9f7 1542 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 1543
<> 144:ef7eb2e8f9f7 1544 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 1545 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1546
<> 144:ef7eb2e8f9f7 1547 return HAL_OK;
<> 144:ef7eb2e8f9f7 1548 }
<> 144:ef7eb2e8f9f7 1549
<> 144:ef7eb2e8f9f7 1550 /**
<> 144:ef7eb2e8f9f7 1551 * @brief DeInitializes the TIM peripheral
<> 144:ef7eb2e8f9f7 1552 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1553 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1554 * @retval HAL status
<> 144:ef7eb2e8f9f7 1555 */
<> 144:ef7eb2e8f9f7 1556 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1557 {
<> 144:ef7eb2e8f9f7 1558 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1559 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1560
<> 144:ef7eb2e8f9f7 1561 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1562
<> 144:ef7eb2e8f9f7 1563 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 1564 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1565
<> 144:ef7eb2e8f9f7 1566 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 1567 HAL_TIM_IC_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 1568
<> 144:ef7eb2e8f9f7 1569 /* Change TIM state */
<> 144:ef7eb2e8f9f7 1570 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 1571
<> 144:ef7eb2e8f9f7 1572 /* Release Lock */
<> 144:ef7eb2e8f9f7 1573 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1574
<> 144:ef7eb2e8f9f7 1575 return HAL_OK;
<> 144:ef7eb2e8f9f7 1576 }
<> 144:ef7eb2e8f9f7 1577
<> 144:ef7eb2e8f9f7 1578 /**
<> 144:ef7eb2e8f9f7 1579 * @brief Initializes the TIM INput Capture MSP.
<> 144:ef7eb2e8f9f7 1580 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1581 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1582 * @retval None
<> 144:ef7eb2e8f9f7 1583 */
<> 144:ef7eb2e8f9f7 1584 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1585 {
<> 144:ef7eb2e8f9f7 1586 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1587 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1588 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1589 the HAL_TIM_IC_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 1590 */
<> 144:ef7eb2e8f9f7 1591 }
<> 144:ef7eb2e8f9f7 1592
<> 144:ef7eb2e8f9f7 1593 /**
<> 144:ef7eb2e8f9f7 1594 * @brief DeInitializes TIM Input Capture MSP.
<> 144:ef7eb2e8f9f7 1595 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1596 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1597 * @retval None
<> 144:ef7eb2e8f9f7 1598 */
<> 144:ef7eb2e8f9f7 1599 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1600 {
<> 144:ef7eb2e8f9f7 1601 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1602 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1603 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1604 the HAL_TIM_IC_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 1605 */
<> 144:ef7eb2e8f9f7 1606 }
<> 144:ef7eb2e8f9f7 1607
<> 144:ef7eb2e8f9f7 1608 /**
<> 144:ef7eb2e8f9f7 1609 * @brief Starts the TIM Input Capture measurement.
<> 144:ef7eb2e8f9f7 1610 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1611 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1612 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 1613 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1614 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1615 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1616 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1617 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1618 * @retval HAL status
<> 144:ef7eb2e8f9f7 1619 */
<> 144:ef7eb2e8f9f7 1620 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1621 {
<> 144:ef7eb2e8f9f7 1622 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1623 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1624
<> 144:ef7eb2e8f9f7 1625 /* Enable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1626 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1627
<> 144:ef7eb2e8f9f7 1628 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1629 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1630
<> 144:ef7eb2e8f9f7 1631 /* Return function status */
<> 144:ef7eb2e8f9f7 1632 return HAL_OK;
<> 144:ef7eb2e8f9f7 1633 }
<> 144:ef7eb2e8f9f7 1634
<> 144:ef7eb2e8f9f7 1635 /**
<> 144:ef7eb2e8f9f7 1636 * @brief Stops the TIM Input Capture measurement.
<> 144:ef7eb2e8f9f7 1637 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1638 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1639 * @param Channel: TIM Channels to be disabled.
<> 144:ef7eb2e8f9f7 1640 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1641 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1642 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1643 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1644 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1645 * @retval HAL status
<> 144:ef7eb2e8f9f7 1646 */
<> 144:ef7eb2e8f9f7 1647 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1648 {
<> 144:ef7eb2e8f9f7 1649 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1650 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1651
<> 144:ef7eb2e8f9f7 1652 /* Disable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1653 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1654
<> 144:ef7eb2e8f9f7 1655 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1656 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1657
<> 144:ef7eb2e8f9f7 1658 /* Return function status */
<> 144:ef7eb2e8f9f7 1659 return HAL_OK;
<> 144:ef7eb2e8f9f7 1660 }
<> 144:ef7eb2e8f9f7 1661
<> 144:ef7eb2e8f9f7 1662 /**
<> 144:ef7eb2e8f9f7 1663 * @brief Starts the TIM Input Capture measurement in interrupt mode.
<> 144:ef7eb2e8f9f7 1664 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1665 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1666 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 1667 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1668 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1669 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1670 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1671 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1672 * @retval HAL status
<> 144:ef7eb2e8f9f7 1673 */
<> 144:ef7eb2e8f9f7 1674 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1675 {
<> 144:ef7eb2e8f9f7 1676 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1677 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1678
<> 144:ef7eb2e8f9f7 1679 switch (Channel)
<> 144:ef7eb2e8f9f7 1680 {
<> 144:ef7eb2e8f9f7 1681 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1682 {
<> 144:ef7eb2e8f9f7 1683 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1684 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1685 }
<> 144:ef7eb2e8f9f7 1686 break;
<> 144:ef7eb2e8f9f7 1687
<> 144:ef7eb2e8f9f7 1688 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1689 {
<> 144:ef7eb2e8f9f7 1690 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1691 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1692 }
<> 144:ef7eb2e8f9f7 1693 break;
<> 144:ef7eb2e8f9f7 1694
<> 144:ef7eb2e8f9f7 1695 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1696 {
<> 144:ef7eb2e8f9f7 1697 /* Enable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1698 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1699 }
<> 144:ef7eb2e8f9f7 1700 break;
<> 144:ef7eb2e8f9f7 1701
<> 144:ef7eb2e8f9f7 1702 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1703 {
<> 144:ef7eb2e8f9f7 1704 /* Enable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1705 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1706 }
<> 144:ef7eb2e8f9f7 1707 break;
<> 144:ef7eb2e8f9f7 1708
<> 144:ef7eb2e8f9f7 1709 default:
<> 144:ef7eb2e8f9f7 1710 break;
<> 144:ef7eb2e8f9f7 1711 }
<> 144:ef7eb2e8f9f7 1712 /* Enable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1713 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1714
<> 144:ef7eb2e8f9f7 1715 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1716 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1717
<> 144:ef7eb2e8f9f7 1718 /* Return function status */
<> 144:ef7eb2e8f9f7 1719 return HAL_OK;
<> 144:ef7eb2e8f9f7 1720 }
<> 144:ef7eb2e8f9f7 1721
<> 144:ef7eb2e8f9f7 1722 /**
<> 144:ef7eb2e8f9f7 1723 * @brief Stops the TIM Input Capture measurement in interrupt mode.
<> 144:ef7eb2e8f9f7 1724 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1725 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1726 * @param Channel: TIM Channels to be disabled.
<> 144:ef7eb2e8f9f7 1727 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1728 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1729 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1730 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1731 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1732 * @retval HAL status
<> 144:ef7eb2e8f9f7 1733 */
<> 144:ef7eb2e8f9f7 1734 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1735 {
<> 144:ef7eb2e8f9f7 1736 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1737 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1738
<> 144:ef7eb2e8f9f7 1739 switch (Channel)
<> 144:ef7eb2e8f9f7 1740 {
<> 144:ef7eb2e8f9f7 1741 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1742 {
<> 144:ef7eb2e8f9f7 1743 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1744 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1745 }
<> 144:ef7eb2e8f9f7 1746 break;
<> 144:ef7eb2e8f9f7 1747
<> 144:ef7eb2e8f9f7 1748 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1749 {
<> 144:ef7eb2e8f9f7 1750 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1751 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1752 }
<> 144:ef7eb2e8f9f7 1753 break;
<> 144:ef7eb2e8f9f7 1754
<> 144:ef7eb2e8f9f7 1755 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1756 {
<> 144:ef7eb2e8f9f7 1757 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1758 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1759 }
<> 144:ef7eb2e8f9f7 1760 break;
<> 144:ef7eb2e8f9f7 1761
<> 144:ef7eb2e8f9f7 1762 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1763 {
<> 144:ef7eb2e8f9f7 1764 /* Disable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1765 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1766 }
<> 144:ef7eb2e8f9f7 1767 break;
<> 144:ef7eb2e8f9f7 1768
<> 144:ef7eb2e8f9f7 1769 default:
<> 144:ef7eb2e8f9f7 1770 break;
<> 144:ef7eb2e8f9f7 1771 }
<> 144:ef7eb2e8f9f7 1772
<> 144:ef7eb2e8f9f7 1773 /* Disable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1774 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1775
<> 144:ef7eb2e8f9f7 1776 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1777 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1778
<> 144:ef7eb2e8f9f7 1779 /* Return function status */
<> 144:ef7eb2e8f9f7 1780 return HAL_OK;
<> 144:ef7eb2e8f9f7 1781 }
<> 144:ef7eb2e8f9f7 1782
<> 144:ef7eb2e8f9f7 1783 /**
<> 144:ef7eb2e8f9f7 1784 * @brief Starts the TIM Input Capture measurement on in DMA mode.
<> 144:ef7eb2e8f9f7 1785 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1786 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1787 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 1788 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1789 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1790 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1791 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1792 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1793 * @param pData: The destination Buffer address.
<> 144:ef7eb2e8f9f7 1794 * @param Length: The length of data to be transferred from TIM peripheral to memory.
<> 144:ef7eb2e8f9f7 1795 * @retval HAL status
<> 144:ef7eb2e8f9f7 1796 */
<> 144:ef7eb2e8f9f7 1797 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 1798 {
<> 144:ef7eb2e8f9f7 1799 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1800 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1801 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1802
<> 144:ef7eb2e8f9f7 1803 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 1804 {
<> 144:ef7eb2e8f9f7 1805 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1806 }
<> 144:ef7eb2e8f9f7 1807 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 1808 {
<> 144:ef7eb2e8f9f7 1809 if((pData == 0U ) && (Length > 0U))
<> 144:ef7eb2e8f9f7 1810 {
<> 144:ef7eb2e8f9f7 1811 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1812 }
<> 144:ef7eb2e8f9f7 1813 else
<> 144:ef7eb2e8f9f7 1814 {
<> 144:ef7eb2e8f9f7 1815 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1816 }
<> 144:ef7eb2e8f9f7 1817 }
<> 144:ef7eb2e8f9f7 1818
<> 144:ef7eb2e8f9f7 1819 switch (Channel)
<> 144:ef7eb2e8f9f7 1820 {
<> 144:ef7eb2e8f9f7 1821 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1822 {
<> 144:ef7eb2e8f9f7 1823 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1824 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 1825
<> 144:ef7eb2e8f9f7 1826 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1827 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1828
<> 144:ef7eb2e8f9f7 1829 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1830 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 1831
<> 144:ef7eb2e8f9f7 1832 /* Enable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1833 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1834 }
<> 144:ef7eb2e8f9f7 1835 break;
<> 144:ef7eb2e8f9f7 1836
<> 144:ef7eb2e8f9f7 1837 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1838 {
<> 144:ef7eb2e8f9f7 1839 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1840 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 1841
<> 144:ef7eb2e8f9f7 1842 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1843 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1844
<> 144:ef7eb2e8f9f7 1845 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1846 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 1847
<> 144:ef7eb2e8f9f7 1848 /* Enable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1849 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1850 }
<> 144:ef7eb2e8f9f7 1851 break;
<> 144:ef7eb2e8f9f7 1852
<> 144:ef7eb2e8f9f7 1853 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1854 {
<> 144:ef7eb2e8f9f7 1855 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1856 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 1857
<> 144:ef7eb2e8f9f7 1858 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1859 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1860
<> 144:ef7eb2e8f9f7 1861 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1862 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 1863
<> 144:ef7eb2e8f9f7 1864 /* Enable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1865 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1866 }
<> 144:ef7eb2e8f9f7 1867 break;
<> 144:ef7eb2e8f9f7 1868
<> 144:ef7eb2e8f9f7 1869 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1870 {
<> 144:ef7eb2e8f9f7 1871 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1872 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 1873
<> 144:ef7eb2e8f9f7 1874 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1875 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1876
<> 144:ef7eb2e8f9f7 1877 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1878 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 1879
<> 144:ef7eb2e8f9f7 1880 /* Enable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1881 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1882 }
<> 144:ef7eb2e8f9f7 1883 break;
<> 144:ef7eb2e8f9f7 1884
<> 144:ef7eb2e8f9f7 1885 default:
<> 144:ef7eb2e8f9f7 1886 break;
<> 144:ef7eb2e8f9f7 1887 }
<> 144:ef7eb2e8f9f7 1888
<> 144:ef7eb2e8f9f7 1889 /* Enable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1890 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1891
<> 144:ef7eb2e8f9f7 1892 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1893 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1894
<> 144:ef7eb2e8f9f7 1895 /* Return function status */
<> 144:ef7eb2e8f9f7 1896 return HAL_OK;
<> 144:ef7eb2e8f9f7 1897 }
<> 144:ef7eb2e8f9f7 1898
<> 144:ef7eb2e8f9f7 1899 /**
<> 144:ef7eb2e8f9f7 1900 * @brief Stops the TIM Input Capture measurement on in DMA mode.
<> 144:ef7eb2e8f9f7 1901 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1902 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1903 * @param Channel: TIM Channels to be disabled.
<> 144:ef7eb2e8f9f7 1904 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1905 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1906 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1907 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1908 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1909 * @retval HAL status
<> 144:ef7eb2e8f9f7 1910 */
<> 144:ef7eb2e8f9f7 1911 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1912 {
<> 144:ef7eb2e8f9f7 1913 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1914 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1915 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1916
<> 144:ef7eb2e8f9f7 1917 switch (Channel)
<> 144:ef7eb2e8f9f7 1918 {
<> 144:ef7eb2e8f9f7 1919 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1920 {
<> 144:ef7eb2e8f9f7 1921 /* Disable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1922 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1923 }
<> 144:ef7eb2e8f9f7 1924 break;
<> 144:ef7eb2e8f9f7 1925
<> 144:ef7eb2e8f9f7 1926 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1927 {
<> 144:ef7eb2e8f9f7 1928 /* Disable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1929 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1930 }
<> 144:ef7eb2e8f9f7 1931 break;
<> 144:ef7eb2e8f9f7 1932
<> 144:ef7eb2e8f9f7 1933 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1934 {
<> 144:ef7eb2e8f9f7 1935 /* Disable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1936 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1937 }
<> 144:ef7eb2e8f9f7 1938 break;
<> 144:ef7eb2e8f9f7 1939
<> 144:ef7eb2e8f9f7 1940 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1941 {
<> 144:ef7eb2e8f9f7 1942 /* Disable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1943 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1944 }
<> 144:ef7eb2e8f9f7 1945 break;
<> 144:ef7eb2e8f9f7 1946
<> 144:ef7eb2e8f9f7 1947 default:
<> 144:ef7eb2e8f9f7 1948 break;
<> 144:ef7eb2e8f9f7 1949 }
<> 144:ef7eb2e8f9f7 1950
<> 144:ef7eb2e8f9f7 1951 /* Disable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1952 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1953
<> 144:ef7eb2e8f9f7 1954 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1955 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1956
<> 144:ef7eb2e8f9f7 1957 /* Change the htim state */
<> 144:ef7eb2e8f9f7 1958 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1959
<> 144:ef7eb2e8f9f7 1960 /* Return function status */
<> 144:ef7eb2e8f9f7 1961 return HAL_OK;
<> 144:ef7eb2e8f9f7 1962 }
<> 144:ef7eb2e8f9f7 1963 /**
<> 144:ef7eb2e8f9f7 1964 * @}
<> 144:ef7eb2e8f9f7 1965 */
<> 144:ef7eb2e8f9f7 1966
<> 144:ef7eb2e8f9f7 1967 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
<> 144:ef7eb2e8f9f7 1968 * @brief Time One Pulse functions
<> 144:ef7eb2e8f9f7 1969 *
<> 144:ef7eb2e8f9f7 1970 @verbatim
<> 144:ef7eb2e8f9f7 1971 ==============================================================================
<> 144:ef7eb2e8f9f7 1972 ##### Time One Pulse functions #####
<> 144:ef7eb2e8f9f7 1973 ==============================================================================
<> 144:ef7eb2e8f9f7 1974 [..]
<> 144:ef7eb2e8f9f7 1975 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1976 (+) Initialize and configure the TIM One Pulse.
<> 144:ef7eb2e8f9f7 1977 (+) De-initialize the TIM One Pulse.
<> 144:ef7eb2e8f9f7 1978 (+) Start the Time One Pulse.
<> 144:ef7eb2e8f9f7 1979 (+) Stop the Time One Pulse.
<> 144:ef7eb2e8f9f7 1980 (+) Start the Time One Pulse and enable interrupt.
<> 144:ef7eb2e8f9f7 1981 (+) Stop the Time One Pulse and disable interrupt.
<> 144:ef7eb2e8f9f7 1982 (+) Start the Time One Pulse and enable DMA transfer.
<> 144:ef7eb2e8f9f7 1983 (+) Stop the Time One Pulse and disable DMA transfer.
<> 144:ef7eb2e8f9f7 1984
<> 144:ef7eb2e8f9f7 1985 @endverbatim
<> 144:ef7eb2e8f9f7 1986 * @{
<> 144:ef7eb2e8f9f7 1987 */
<> 144:ef7eb2e8f9f7 1988 /**
<> 144:ef7eb2e8f9f7 1989 * @brief Initializes the TIM One Pulse Time Base according to the specified
<> 144:ef7eb2e8f9f7 1990 * parameters in the TIM_HandleTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 1991 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1992 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1993 * @param OnePulseMode: Select the One pulse mode.
<> 144:ef7eb2e8f9f7 1994 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1995 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
<> 144:ef7eb2e8f9f7 1996 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
<> 144:ef7eb2e8f9f7 1997 * @retval HAL status
<> 144:ef7eb2e8f9f7 1998 */
<> 144:ef7eb2e8f9f7 1999 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
<> 144:ef7eb2e8f9f7 2000 {
<> 144:ef7eb2e8f9f7 2001 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 2002 if(htim == NULL)
<> 144:ef7eb2e8f9f7 2003 {
<> 144:ef7eb2e8f9f7 2004 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2005 }
<> 144:ef7eb2e8f9f7 2006
<> 144:ef7eb2e8f9f7 2007 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2008 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2009 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 2010 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 144:ef7eb2e8f9f7 2011 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
<> 144:ef7eb2e8f9f7 2012
<> 144:ef7eb2e8f9f7 2013 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 2014 {
<> 144:ef7eb2e8f9f7 2015 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 2016 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 2017 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 2018 HAL_TIM_OnePulse_MspInit(htim);
<> 144:ef7eb2e8f9f7 2019 }
<> 144:ef7eb2e8f9f7 2020
<> 144:ef7eb2e8f9f7 2021 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 2022 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2023
<> 144:ef7eb2e8f9f7 2024 /* Configure the Time base in the One Pulse Mode */
<> 144:ef7eb2e8f9f7 2025 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 2026
<> 144:ef7eb2e8f9f7 2027 /* Reset the OPM Bit */
<> 144:ef7eb2e8f9f7 2028 htim->Instance->CR1 &= ~TIM_CR1_OPM;
<> 144:ef7eb2e8f9f7 2029
<> 144:ef7eb2e8f9f7 2030 /* Configure the OPM Mode */
<> 144:ef7eb2e8f9f7 2031 htim->Instance->CR1 |= OnePulseMode;
<> 144:ef7eb2e8f9f7 2032
<> 144:ef7eb2e8f9f7 2033 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 2034 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2035
<> 144:ef7eb2e8f9f7 2036 return HAL_OK;
<> 144:ef7eb2e8f9f7 2037 }
<> 144:ef7eb2e8f9f7 2038
<> 144:ef7eb2e8f9f7 2039 /**
<> 144:ef7eb2e8f9f7 2040 * @brief DeInitializes the TIM One Pulse
<> 144:ef7eb2e8f9f7 2041 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2042 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2043 * @retval HAL status
<> 144:ef7eb2e8f9f7 2044 */
<> 144:ef7eb2e8f9f7 2045 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2046 {
<> 144:ef7eb2e8f9f7 2047 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2048 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2049
<> 144:ef7eb2e8f9f7 2050 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2051
<> 144:ef7eb2e8f9f7 2052 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 2053 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2054
<> 144:ef7eb2e8f9f7 2055 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 2056 HAL_TIM_OnePulse_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 2057
<> 144:ef7eb2e8f9f7 2058 /* Change TIM state */
<> 144:ef7eb2e8f9f7 2059 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 2060
<> 144:ef7eb2e8f9f7 2061 /* Release Lock */
<> 144:ef7eb2e8f9f7 2062 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 2063
<> 144:ef7eb2e8f9f7 2064 return HAL_OK;
<> 144:ef7eb2e8f9f7 2065 }
<> 144:ef7eb2e8f9f7 2066
<> 144:ef7eb2e8f9f7 2067 /**
<> 144:ef7eb2e8f9f7 2068 * @brief Initializes the TIM One Pulse MSP.
<> 144:ef7eb2e8f9f7 2069 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2070 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2071 * @retval None
<> 144:ef7eb2e8f9f7 2072 */
<> 144:ef7eb2e8f9f7 2073 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2074 {
<> 144:ef7eb2e8f9f7 2075 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2076 UNUSED(htim);
<> 144:ef7eb2e8f9f7 2077 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2078 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 2079 */
<> 144:ef7eb2e8f9f7 2080 }
<> 144:ef7eb2e8f9f7 2081
<> 144:ef7eb2e8f9f7 2082 /**
<> 144:ef7eb2e8f9f7 2083 * @brief DeInitializes TIM One Pulse MSP.
<> 144:ef7eb2e8f9f7 2084 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2085 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2086 * @retval None
<> 144:ef7eb2e8f9f7 2087 */
<> 144:ef7eb2e8f9f7 2088 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2089 {
<> 144:ef7eb2e8f9f7 2090 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2091 UNUSED(htim);
<> 144:ef7eb2e8f9f7 2092 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2093 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 2094 */
<> 144:ef7eb2e8f9f7 2095 }
<> 144:ef7eb2e8f9f7 2096
<> 144:ef7eb2e8f9f7 2097 /**
<> 144:ef7eb2e8f9f7 2098 * @brief Starts the TIM One Pulse signal generation.
<> 144:ef7eb2e8f9f7 2099 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2100 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2101 * @param OutputChannel : TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 2102 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2103 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2104 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2105 * @retval HAL status
<> 144:ef7eb2e8f9f7 2106 */
<> 144:ef7eb2e8f9f7 2107 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 2108 {
<> 144:ef7eb2e8f9f7 2109 /* Enable the Capture compare and the Input Capture channels
<> 144:ef7eb2e8f9f7 2110 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2111 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<> 144:ef7eb2e8f9f7 2112 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<> 144:ef7eb2e8f9f7 2113 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
<> 144:ef7eb2e8f9f7 2114
<> 144:ef7eb2e8f9f7 2115 No need to enable the counter, it's enabled automatically by hardware
<> 144:ef7eb2e8f9f7 2116 (the counter starts in response to a stimulus and generate a pulse */
<> 144:ef7eb2e8f9f7 2117
<> 144:ef7eb2e8f9f7 2118 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2119 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2120
<> 144:ef7eb2e8f9f7 2121 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 2122 {
<> 144:ef7eb2e8f9f7 2123 /* Enable the main output */
<> 144:ef7eb2e8f9f7 2124 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2125 }
<> 144:ef7eb2e8f9f7 2126
<> 144:ef7eb2e8f9f7 2127 /* Return function status */
<> 144:ef7eb2e8f9f7 2128 return HAL_OK;
<> 144:ef7eb2e8f9f7 2129 }
<> 144:ef7eb2e8f9f7 2130
<> 144:ef7eb2e8f9f7 2131 /**
<> 144:ef7eb2e8f9f7 2132 * @brief Stops the TIM One Pulse signal generation.
<> 144:ef7eb2e8f9f7 2133 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2134 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2135 * @param OutputChannel : TIM Channels to be disable.
<> 144:ef7eb2e8f9f7 2136 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2137 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2138 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2139 * @retval HAL status
<> 144:ef7eb2e8f9f7 2140 */
<> 144:ef7eb2e8f9f7 2141 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 2142 {
<> 144:ef7eb2e8f9f7 2143 /* Disable the Capture compare and the Input Capture channels
<> 144:ef7eb2e8f9f7 2144 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2145 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<> 144:ef7eb2e8f9f7 2146 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<> 144:ef7eb2e8f9f7 2147 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
<> 144:ef7eb2e8f9f7 2148
<> 144:ef7eb2e8f9f7 2149 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2150 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2151
<> 144:ef7eb2e8f9f7 2152 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 2153 {
<> 144:ef7eb2e8f9f7 2154 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 2155 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2156 }
<> 144:ef7eb2e8f9f7 2157
<> 144:ef7eb2e8f9f7 2158 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 2159 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2160
<> 144:ef7eb2e8f9f7 2161 /* Return function status */
<> 144:ef7eb2e8f9f7 2162 return HAL_OK;
<> 144:ef7eb2e8f9f7 2163 }
<> 144:ef7eb2e8f9f7 2164
<> 144:ef7eb2e8f9f7 2165 /**
<> 144:ef7eb2e8f9f7 2166 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
<> 144:ef7eb2e8f9f7 2167 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2168 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2169 * @param OutputChannel : TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 2170 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2171 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2172 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2173 * @retval HAL status
<> 144:ef7eb2e8f9f7 2174 */
<> 144:ef7eb2e8f9f7 2175 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 2176 {
<> 144:ef7eb2e8f9f7 2177 /* Enable the Capture compare and the Input Capture channels
<> 144:ef7eb2e8f9f7 2178 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2179 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<> 144:ef7eb2e8f9f7 2180 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<> 144:ef7eb2e8f9f7 2181 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
<> 144:ef7eb2e8f9f7 2182
<> 144:ef7eb2e8f9f7 2183 No need to enable the counter, it's enabled automatically by hardware
<> 144:ef7eb2e8f9f7 2184 (the counter starts in response to a stimulus and generate a pulse */
<> 144:ef7eb2e8f9f7 2185
<> 144:ef7eb2e8f9f7 2186 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 2187 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2188
<> 144:ef7eb2e8f9f7 2189 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 2190 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2191
<> 144:ef7eb2e8f9f7 2192 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2193 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2194
<> 144:ef7eb2e8f9f7 2195 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 2196 {
<> 144:ef7eb2e8f9f7 2197 /* Enable the main output */
<> 144:ef7eb2e8f9f7 2198 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2199 }
<> 144:ef7eb2e8f9f7 2200
<> 144:ef7eb2e8f9f7 2201 /* Return function status */
<> 144:ef7eb2e8f9f7 2202 return HAL_OK;
<> 144:ef7eb2e8f9f7 2203 }
<> 144:ef7eb2e8f9f7 2204
<> 144:ef7eb2e8f9f7 2205 /**
<> 144:ef7eb2e8f9f7 2206 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
<> 144:ef7eb2e8f9f7 2207 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2208 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2209 * @param OutputChannel : TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 2210 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2211 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2212 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2213 * @retval HAL status
<> 144:ef7eb2e8f9f7 2214 */
<> 144:ef7eb2e8f9f7 2215 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 2216 {
<> 144:ef7eb2e8f9f7 2217 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 2218 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2219
<> 144:ef7eb2e8f9f7 2220 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 2221 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2222
<> 144:ef7eb2e8f9f7 2223 /* Disable the Capture compare and the Input Capture channels
<> 144:ef7eb2e8f9f7 2224 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2225 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<> 144:ef7eb2e8f9f7 2226 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<> 144:ef7eb2e8f9f7 2227 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
<> 144:ef7eb2e8f9f7 2228 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2229 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2230
<> 144:ef7eb2e8f9f7 2231 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 2232 {
<> 144:ef7eb2e8f9f7 2233 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 2234 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2235 }
<> 144:ef7eb2e8f9f7 2236
<> 144:ef7eb2e8f9f7 2237 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 2238 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2239
<> 144:ef7eb2e8f9f7 2240 /* Return function status */
<> 144:ef7eb2e8f9f7 2241 return HAL_OK;
<> 144:ef7eb2e8f9f7 2242 }
<> 144:ef7eb2e8f9f7 2243 /**
<> 144:ef7eb2e8f9f7 2244 * @}
<> 144:ef7eb2e8f9f7 2245 */
<> 144:ef7eb2e8f9f7 2246
<> 144:ef7eb2e8f9f7 2247 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
<> 144:ef7eb2e8f9f7 2248 * @brief Time Encoder functions
<> 144:ef7eb2e8f9f7 2249 *
<> 144:ef7eb2e8f9f7 2250 @verbatim
<> 144:ef7eb2e8f9f7 2251 ==============================================================================
<> 144:ef7eb2e8f9f7 2252 ##### Time Encoder functions #####
<> 144:ef7eb2e8f9f7 2253 ==============================================================================
<> 144:ef7eb2e8f9f7 2254 [..]
<> 144:ef7eb2e8f9f7 2255 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 2256 (+) Initialize and configure the TIM Encoder.
<> 144:ef7eb2e8f9f7 2257 (+) De-initialize the TIM Encoder.
<> 144:ef7eb2e8f9f7 2258 (+) Start the Time Encoder.
<> 144:ef7eb2e8f9f7 2259 (+) Stop the Time Encoder.
<> 144:ef7eb2e8f9f7 2260 (+) Start the Time Encoder and enable interrupt.
<> 144:ef7eb2e8f9f7 2261 (+) Stop the Time Encoder and disable interrupt.
<> 144:ef7eb2e8f9f7 2262 (+) Start the Time Encoder and enable DMA transfer.
<> 144:ef7eb2e8f9f7 2263 (+) Stop the Time Encoder and disable DMA transfer.
<> 144:ef7eb2e8f9f7 2264
<> 144:ef7eb2e8f9f7 2265 @endverbatim
<> 144:ef7eb2e8f9f7 2266 * @{
<> 144:ef7eb2e8f9f7 2267 */
<> 144:ef7eb2e8f9f7 2268 /**
<> 144:ef7eb2e8f9f7 2269 * @brief Initializes the TIM Encoder Interface and create the associated handle.
<> 144:ef7eb2e8f9f7 2270 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2271 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2272 * @param sConfig: TIM Encoder Interface configuration structure
<> 144:ef7eb2e8f9f7 2273 * @retval HAL status
<> 144:ef7eb2e8f9f7 2274 */
<> 144:ef7eb2e8f9f7 2275 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
<> 144:ef7eb2e8f9f7 2276 {
<> 144:ef7eb2e8f9f7 2277 uint32_t tmpsmcr = 0U;
<> 144:ef7eb2e8f9f7 2278 uint32_t tmpccmr1 = 0U;
<> 144:ef7eb2e8f9f7 2279 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 2280
<> 144:ef7eb2e8f9f7 2281 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 2282 if(htim == NULL)
<> 144:ef7eb2e8f9f7 2283 {
<> 144:ef7eb2e8f9f7 2284 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2285 }
<> 144:ef7eb2e8f9f7 2286
<> 144:ef7eb2e8f9f7 2287 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2288 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2289 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
<> 144:ef7eb2e8f9f7 2290 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
<> 144:ef7eb2e8f9f7 2291 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
<> 144:ef7eb2e8f9f7 2292 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
<> 144:ef7eb2e8f9f7 2293 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
<> 144:ef7eb2e8f9f7 2294 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
<> 144:ef7eb2e8f9f7 2295 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
<> 144:ef7eb2e8f9f7 2296 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
<> 144:ef7eb2e8f9f7 2297 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
<> 144:ef7eb2e8f9f7 2298
<> 144:ef7eb2e8f9f7 2299 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 2300 {
<> 144:ef7eb2e8f9f7 2301 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 2302 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 2303 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 2304 HAL_TIM_Encoder_MspInit(htim);
<> 144:ef7eb2e8f9f7 2305 }
<> 144:ef7eb2e8f9f7 2306
<> 144:ef7eb2e8f9f7 2307 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 2308 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2309
<> 144:ef7eb2e8f9f7 2310 /* Reset the SMS bits */
<> 144:ef7eb2e8f9f7 2311 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 2312
<> 144:ef7eb2e8f9f7 2313 /* Configure the Time base in the Encoder Mode */
<> 144:ef7eb2e8f9f7 2314 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 2315
<> 144:ef7eb2e8f9f7 2316 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 2317 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 2318
<> 144:ef7eb2e8f9f7 2319 /* Get the TIMx CCMR1 register value */
<> 144:ef7eb2e8f9f7 2320 tmpccmr1 = htim->Instance->CCMR1;
<> 144:ef7eb2e8f9f7 2321
<> 144:ef7eb2e8f9f7 2322 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 2323 tmpccer = htim->Instance->CCER;
<> 144:ef7eb2e8f9f7 2324
<> 144:ef7eb2e8f9f7 2325 /* Set the encoder Mode */
<> 144:ef7eb2e8f9f7 2326 tmpsmcr |= sConfig->EncoderMode;
<> 144:ef7eb2e8f9f7 2327
<> 144:ef7eb2e8f9f7 2328 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
<> 144:ef7eb2e8f9f7 2329 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
<> 144:ef7eb2e8f9f7 2330 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
<> 144:ef7eb2e8f9f7 2331
<> 144:ef7eb2e8f9f7 2332 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
<> 144:ef7eb2e8f9f7 2333 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
<> 144:ef7eb2e8f9f7 2334 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
<> 144:ef7eb2e8f9f7 2335 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
<> 144:ef7eb2e8f9f7 2336 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
<> 144:ef7eb2e8f9f7 2337
<> 144:ef7eb2e8f9f7 2338 /* Set the TI1 and the TI2 Polarities */
<> 144:ef7eb2e8f9f7 2339 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
<> 144:ef7eb2e8f9f7 2340 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
<> 144:ef7eb2e8f9f7 2341 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
<> 144:ef7eb2e8f9f7 2342
<> 144:ef7eb2e8f9f7 2343 /* Write to TIMx SMCR */
<> 144:ef7eb2e8f9f7 2344 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 2345
<> 144:ef7eb2e8f9f7 2346 /* Write to TIMx CCMR1 */
<> 144:ef7eb2e8f9f7 2347 htim->Instance->CCMR1 = tmpccmr1;
<> 144:ef7eb2e8f9f7 2348
<> 144:ef7eb2e8f9f7 2349 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 2350 htim->Instance->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 2351
<> 144:ef7eb2e8f9f7 2352 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 2353 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2354
<> 144:ef7eb2e8f9f7 2355 return HAL_OK;
<> 144:ef7eb2e8f9f7 2356 }
<> 144:ef7eb2e8f9f7 2357
<> 144:ef7eb2e8f9f7 2358 /**
<> 144:ef7eb2e8f9f7 2359 * @brief DeInitializes the TIM Encoder interface
<> 144:ef7eb2e8f9f7 2360 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2361 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2362 * @retval HAL status
<> 144:ef7eb2e8f9f7 2363 */
<> 144:ef7eb2e8f9f7 2364 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2365 {
<> 144:ef7eb2e8f9f7 2366 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2367 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2368
<> 144:ef7eb2e8f9f7 2369 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2370
<> 144:ef7eb2e8f9f7 2371 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 2372 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2373
<> 144:ef7eb2e8f9f7 2374 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 2375 HAL_TIM_Encoder_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 2376
<> 144:ef7eb2e8f9f7 2377 /* Change TIM state */
<> 144:ef7eb2e8f9f7 2378 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 2379
<> 144:ef7eb2e8f9f7 2380 /* Release Lock */
<> 144:ef7eb2e8f9f7 2381 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 2382
<> 144:ef7eb2e8f9f7 2383 return HAL_OK;
<> 144:ef7eb2e8f9f7 2384 }
<> 144:ef7eb2e8f9f7 2385
<> 144:ef7eb2e8f9f7 2386 /**
<> 144:ef7eb2e8f9f7 2387 * @brief Initializes the TIM Encoder Interface MSP.
<> 144:ef7eb2e8f9f7 2388 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2389 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2390 * @retval None
<> 144:ef7eb2e8f9f7 2391 */
<> 144:ef7eb2e8f9f7 2392 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2393 {
<> 144:ef7eb2e8f9f7 2394 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2395 UNUSED(htim);
<> 144:ef7eb2e8f9f7 2396 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2397 the HAL_TIM_Encoder_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 2398 */
<> 144:ef7eb2e8f9f7 2399 }
<> 144:ef7eb2e8f9f7 2400
<> 144:ef7eb2e8f9f7 2401 /**
<> 144:ef7eb2e8f9f7 2402 * @brief DeInitializes TIM Encoder Interface MSP.
<> 144:ef7eb2e8f9f7 2403 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2404 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2405 * @retval None
<> 144:ef7eb2e8f9f7 2406 */
<> 144:ef7eb2e8f9f7 2407 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2408 {
<> 144:ef7eb2e8f9f7 2409 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2410 UNUSED(htim);
<> 144:ef7eb2e8f9f7 2411 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2412 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 2413 */
<> 144:ef7eb2e8f9f7 2414 }
<> 144:ef7eb2e8f9f7 2415
<> 144:ef7eb2e8f9f7 2416 /**
<> 144:ef7eb2e8f9f7 2417 * @brief Starts the TIM Encoder Interface.
<> 144:ef7eb2e8f9f7 2418 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2419 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2420 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 2421 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2422 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2423 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2424 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2425 * @retval HAL status
<> 144:ef7eb2e8f9f7 2426 */
<> 144:ef7eb2e8f9f7 2427 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2428 {
<> 144:ef7eb2e8f9f7 2429 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2430 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2431
<> 144:ef7eb2e8f9f7 2432 /* Enable the encoder interface channels */
<> 144:ef7eb2e8f9f7 2433 switch (Channel)
<> 144:ef7eb2e8f9f7 2434 {
<> 144:ef7eb2e8f9f7 2435 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 2436 {
<> 144:ef7eb2e8f9f7 2437 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2438 break;
<> 144:ef7eb2e8f9f7 2439 }
<> 144:ef7eb2e8f9f7 2440 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 2441 {
<> 144:ef7eb2e8f9f7 2442 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2443 break;
<> 144:ef7eb2e8f9f7 2444 }
<> 144:ef7eb2e8f9f7 2445 default :
<> 144:ef7eb2e8f9f7 2446 {
<> 144:ef7eb2e8f9f7 2447 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2448 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2449 break;
<> 144:ef7eb2e8f9f7 2450 }
<> 144:ef7eb2e8f9f7 2451 }
<> 144:ef7eb2e8f9f7 2452 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 2453 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2454
<> 144:ef7eb2e8f9f7 2455 /* Return function status */
<> 144:ef7eb2e8f9f7 2456 return HAL_OK;
<> 144:ef7eb2e8f9f7 2457 }
<> 144:ef7eb2e8f9f7 2458
<> 144:ef7eb2e8f9f7 2459 /**
<> 144:ef7eb2e8f9f7 2460 * @brief Stops the TIM Encoder Interface.
<> 144:ef7eb2e8f9f7 2461 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2462 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2463 * @param Channel: TIM Channels to be disabled.
<> 144:ef7eb2e8f9f7 2464 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2465 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2466 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2467 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2468 * @retval HAL status
<> 144:ef7eb2e8f9f7 2469 */
<> 144:ef7eb2e8f9f7 2470 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2471 {
<> 144:ef7eb2e8f9f7 2472 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2473 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2474
<> 144:ef7eb2e8f9f7 2475 /* Disable the Input Capture channels 1 and 2
<> 144:ef7eb2e8f9f7 2476 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<> 144:ef7eb2e8f9f7 2477 switch (Channel)
<> 144:ef7eb2e8f9f7 2478 {
<> 144:ef7eb2e8f9f7 2479 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 2480 {
<> 144:ef7eb2e8f9f7 2481 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2482 break;
<> 144:ef7eb2e8f9f7 2483 }
<> 144:ef7eb2e8f9f7 2484 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 2485 {
<> 144:ef7eb2e8f9f7 2486 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2487 break;
<> 144:ef7eb2e8f9f7 2488 }
<> 144:ef7eb2e8f9f7 2489 default :
<> 144:ef7eb2e8f9f7 2490 {
<> 144:ef7eb2e8f9f7 2491 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2492 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2493 break;
<> 144:ef7eb2e8f9f7 2494 }
<> 144:ef7eb2e8f9f7 2495 }
<> 144:ef7eb2e8f9f7 2496 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 2497 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2498
<> 144:ef7eb2e8f9f7 2499 /* Return function status */
<> 144:ef7eb2e8f9f7 2500 return HAL_OK;
<> 144:ef7eb2e8f9f7 2501 }
<> 144:ef7eb2e8f9f7 2502
<> 144:ef7eb2e8f9f7 2503 /**
<> 144:ef7eb2e8f9f7 2504 * @brief Starts the TIM Encoder Interface in interrupt mode.
<> 144:ef7eb2e8f9f7 2505 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2506 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2507 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 2508 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2509 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2510 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2511 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2512 * @retval HAL status
<> 144:ef7eb2e8f9f7 2513 */
<> 144:ef7eb2e8f9f7 2514 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2515 {
<> 144:ef7eb2e8f9f7 2516 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2517 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2518
<> 144:ef7eb2e8f9f7 2519 /* Enable the encoder interface channels */
<> 144:ef7eb2e8f9f7 2520 /* Enable the capture compare Interrupts 1 and/or 2 */
<> 144:ef7eb2e8f9f7 2521 switch (Channel)
<> 144:ef7eb2e8f9f7 2522 {
<> 144:ef7eb2e8f9f7 2523 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 2524 {
<> 144:ef7eb2e8f9f7 2525 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2526 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2527 break;
<> 144:ef7eb2e8f9f7 2528 }
<> 144:ef7eb2e8f9f7 2529 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 2530 {
<> 144:ef7eb2e8f9f7 2531 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2532 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2533 break;
<> 144:ef7eb2e8f9f7 2534 }
<> 144:ef7eb2e8f9f7 2535 default :
<> 144:ef7eb2e8f9f7 2536 {
<> 144:ef7eb2e8f9f7 2537 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2538 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2539 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2540 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2541 break;
<> 144:ef7eb2e8f9f7 2542 }
<> 144:ef7eb2e8f9f7 2543 }
<> 144:ef7eb2e8f9f7 2544
<> 144:ef7eb2e8f9f7 2545 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 2546 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2547
<> 144:ef7eb2e8f9f7 2548 /* Return function status */
<> 144:ef7eb2e8f9f7 2549 return HAL_OK;
<> 144:ef7eb2e8f9f7 2550 }
<> 144:ef7eb2e8f9f7 2551
<> 144:ef7eb2e8f9f7 2552 /**
<> 144:ef7eb2e8f9f7 2553 * @brief Stops the TIM Encoder Interface in interrupt mode.
<> 144:ef7eb2e8f9f7 2554 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2555 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2556 * @param Channel: TIM Channels to be disabled.
<> 144:ef7eb2e8f9f7 2557 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2558 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2559 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2560 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2561 * @retval HAL status
<> 144:ef7eb2e8f9f7 2562 */
<> 144:ef7eb2e8f9f7 2563 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2564 {
<> 144:ef7eb2e8f9f7 2565 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2566 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2567
<> 144:ef7eb2e8f9f7 2568 /* Disable the Input Capture channels 1 and 2
<> 144:ef7eb2e8f9f7 2569 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<> 144:ef7eb2e8f9f7 2570 if(Channel == TIM_CHANNEL_1)
<> 144:ef7eb2e8f9f7 2571 {
<> 144:ef7eb2e8f9f7 2572 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2573
<> 144:ef7eb2e8f9f7 2574 /* Disable the capture compare Interrupts 1 */
<> 144:ef7eb2e8f9f7 2575 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2576 }
<> 144:ef7eb2e8f9f7 2577 else if(Channel == TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2578 {
<> 144:ef7eb2e8f9f7 2579 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2580
<> 144:ef7eb2e8f9f7 2581 /* Disable the capture compare Interrupts 2 */
<> 144:ef7eb2e8f9f7 2582 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2583 }
<> 144:ef7eb2e8f9f7 2584 else
<> 144:ef7eb2e8f9f7 2585 {
<> 144:ef7eb2e8f9f7 2586 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2587 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2588
<> 144:ef7eb2e8f9f7 2589 /* Disable the capture compare Interrupts 1 and 2 */
<> 144:ef7eb2e8f9f7 2590 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2591 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2592 }
<> 144:ef7eb2e8f9f7 2593
<> 144:ef7eb2e8f9f7 2594 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 2595 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2596
<> 144:ef7eb2e8f9f7 2597 /* Change the htim state */
<> 144:ef7eb2e8f9f7 2598 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2599
<> 144:ef7eb2e8f9f7 2600 /* Return function status */
<> 144:ef7eb2e8f9f7 2601 return HAL_OK;
<> 144:ef7eb2e8f9f7 2602 }
<> 144:ef7eb2e8f9f7 2603
<> 144:ef7eb2e8f9f7 2604 /**
<> 144:ef7eb2e8f9f7 2605 * @brief Starts the TIM Encoder Interface in DMA mode.
<> 144:ef7eb2e8f9f7 2606 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2607 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2608 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 2609 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2610 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2611 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2612 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2613 * @param pData1: The destination Buffer address for IC1.
<> 144:ef7eb2e8f9f7 2614 * @param pData2: The destination Buffer address for IC2.
<> 144:ef7eb2e8f9f7 2615 * @param Length: The length of data to be transferred from TIM peripheral to memory.
<> 144:ef7eb2e8f9f7 2616 * @retval HAL status
<> 144:ef7eb2e8f9f7 2617 */
<> 144:ef7eb2e8f9f7 2618 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
<> 144:ef7eb2e8f9f7 2619 {
<> 144:ef7eb2e8f9f7 2620 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2621 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2622
<> 144:ef7eb2e8f9f7 2623 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 2624 {
<> 144:ef7eb2e8f9f7 2625 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 2626 }
<> 144:ef7eb2e8f9f7 2627 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 2628 {
<> 144:ef7eb2e8f9f7 2629 if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0U))
<> 144:ef7eb2e8f9f7 2630 {
<> 144:ef7eb2e8f9f7 2631 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2632 }
<> 144:ef7eb2e8f9f7 2633 else
<> 144:ef7eb2e8f9f7 2634 {
<> 144:ef7eb2e8f9f7 2635 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2636 }
<> 144:ef7eb2e8f9f7 2637 }
<> 144:ef7eb2e8f9f7 2638
<> 144:ef7eb2e8f9f7 2639 switch (Channel)
<> 144:ef7eb2e8f9f7 2640 {
<> 144:ef7eb2e8f9f7 2641 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 2642 {
<> 144:ef7eb2e8f9f7 2643 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 2644 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 2645
<> 144:ef7eb2e8f9f7 2646 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 2647 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 2648
<> 144:ef7eb2e8f9f7 2649 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 2650 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
<> 144:ef7eb2e8f9f7 2651
<> 144:ef7eb2e8f9f7 2652 /* Enable the TIM Input Capture DMA request */
<> 144:ef7eb2e8f9f7 2653 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 2654
<> 144:ef7eb2e8f9f7 2655 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 2656 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2657
<> 144:ef7eb2e8f9f7 2658 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 2659 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2660 }
<> 144:ef7eb2e8f9f7 2661 break;
<> 144:ef7eb2e8f9f7 2662
<> 144:ef7eb2e8f9f7 2663 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 2664 {
<> 144:ef7eb2e8f9f7 2665 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 2666 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 2667
<> 144:ef7eb2e8f9f7 2668 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 2669 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
<> 144:ef7eb2e8f9f7 2670 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 2671 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
<> 144:ef7eb2e8f9f7 2672
<> 144:ef7eb2e8f9f7 2673 /* Enable the TIM Input Capture DMA request */
<> 144:ef7eb2e8f9f7 2674 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 2675
<> 144:ef7eb2e8f9f7 2676 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 2677 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2678
<> 144:ef7eb2e8f9f7 2679 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 2680 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2681 }
<> 144:ef7eb2e8f9f7 2682 break;
<> 144:ef7eb2e8f9f7 2683
<> 144:ef7eb2e8f9f7 2684 case TIM_CHANNEL_ALL:
<> 144:ef7eb2e8f9f7 2685 {
<> 144:ef7eb2e8f9f7 2686 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 2687 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 2688
<> 144:ef7eb2e8f9f7 2689 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 2690 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 2691
<> 144:ef7eb2e8f9f7 2692 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 2693 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
<> 144:ef7eb2e8f9f7 2694
<> 144:ef7eb2e8f9f7 2695 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 2696 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 2697
<> 144:ef7eb2e8f9f7 2698 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 2699 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 2700
<> 144:ef7eb2e8f9f7 2701 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 2702 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
<> 144:ef7eb2e8f9f7 2703
<> 144:ef7eb2e8f9f7 2704 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 2705 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2706
<> 144:ef7eb2e8f9f7 2707 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 2708 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2709 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2710
<> 144:ef7eb2e8f9f7 2711 /* Enable the TIM Input Capture DMA request */
<> 144:ef7eb2e8f9f7 2712 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 2713 /* Enable the TIM Input Capture DMA request */
<> 144:ef7eb2e8f9f7 2714 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 2715 }
<> 144:ef7eb2e8f9f7 2716 break;
<> 144:ef7eb2e8f9f7 2717
<> 144:ef7eb2e8f9f7 2718 default:
<> 144:ef7eb2e8f9f7 2719 break;
<> 144:ef7eb2e8f9f7 2720 }
<> 144:ef7eb2e8f9f7 2721 /* Return function status */
<> 144:ef7eb2e8f9f7 2722 return HAL_OK;
<> 144:ef7eb2e8f9f7 2723 }
<> 144:ef7eb2e8f9f7 2724
<> 144:ef7eb2e8f9f7 2725 /**
<> 144:ef7eb2e8f9f7 2726 * @brief Stops the TIM Encoder Interface in DMA mode.
<> 144:ef7eb2e8f9f7 2727 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2728 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2729 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 2730 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2731 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2732 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2733 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2734 * @retval HAL status
<> 144:ef7eb2e8f9f7 2735 */
<> 144:ef7eb2e8f9f7 2736 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2737 {
<> 144:ef7eb2e8f9f7 2738 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2739 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2740
<> 144:ef7eb2e8f9f7 2741 /* Disable the Input Capture channels 1 and 2
<> 144:ef7eb2e8f9f7 2742 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<> 144:ef7eb2e8f9f7 2743 if(Channel == TIM_CHANNEL_1)
<> 144:ef7eb2e8f9f7 2744 {
<> 144:ef7eb2e8f9f7 2745 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2746
<> 144:ef7eb2e8f9f7 2747 /* Disable the capture compare DMA Request 1 */
<> 144:ef7eb2e8f9f7 2748 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 2749 }
<> 144:ef7eb2e8f9f7 2750 else if(Channel == TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2751 {
<> 144:ef7eb2e8f9f7 2752 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2753
<> 144:ef7eb2e8f9f7 2754 /* Disable the capture compare DMA Request 2 */
<> 144:ef7eb2e8f9f7 2755 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 2756 }
<> 144:ef7eb2e8f9f7 2757 else
<> 144:ef7eb2e8f9f7 2758 {
<> 144:ef7eb2e8f9f7 2759 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2760 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2761
<> 144:ef7eb2e8f9f7 2762 /* Disable the capture compare DMA Request 1 and 2 */
<> 144:ef7eb2e8f9f7 2763 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 2764 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 2765 }
<> 144:ef7eb2e8f9f7 2766
<> 144:ef7eb2e8f9f7 2767 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 2768 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2769
<> 144:ef7eb2e8f9f7 2770 /* Change the htim state */
<> 144:ef7eb2e8f9f7 2771 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2772
<> 144:ef7eb2e8f9f7 2773 /* Return function status */
<> 144:ef7eb2e8f9f7 2774 return HAL_OK;
<> 144:ef7eb2e8f9f7 2775 }
<> 144:ef7eb2e8f9f7 2776 /**
<> 144:ef7eb2e8f9f7 2777 * @}
<> 144:ef7eb2e8f9f7 2778 */
<> 144:ef7eb2e8f9f7 2779
<> 144:ef7eb2e8f9f7 2780 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
<> 144:ef7eb2e8f9f7 2781 * @brief IRQ handler management
<> 144:ef7eb2e8f9f7 2782 *
<> 144:ef7eb2e8f9f7 2783 @verbatim
<> 144:ef7eb2e8f9f7 2784 ==============================================================================
<> 144:ef7eb2e8f9f7 2785 ##### IRQ handler management #####
<> 144:ef7eb2e8f9f7 2786 ==============================================================================
<> 144:ef7eb2e8f9f7 2787 [..]
<> 144:ef7eb2e8f9f7 2788 This section provides Timer IRQ handler function.
<> 144:ef7eb2e8f9f7 2789
<> 144:ef7eb2e8f9f7 2790 @endverbatim
<> 144:ef7eb2e8f9f7 2791 * @{
<> 144:ef7eb2e8f9f7 2792 */
<> 144:ef7eb2e8f9f7 2793 /**
<> 144:ef7eb2e8f9f7 2794 * @brief This function handles TIM interrupts requests.
<> 144:ef7eb2e8f9f7 2795 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2796 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2797 * @retval None
<> 144:ef7eb2e8f9f7 2798 */
<> 144:ef7eb2e8f9f7 2799 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2800 {
<> 144:ef7eb2e8f9f7 2801 /* Capture compare 1 event */
<> 144:ef7eb2e8f9f7 2802 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
<> 144:ef7eb2e8f9f7 2803 {
<> 144:ef7eb2e8f9f7 2804 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
<> 144:ef7eb2e8f9f7 2805 {
<> 144:ef7eb2e8f9f7 2806 {
<> 144:ef7eb2e8f9f7 2807 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2808 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<> 144:ef7eb2e8f9f7 2809
<> 144:ef7eb2e8f9f7 2810 /* Input capture event */
<> 144:ef7eb2e8f9f7 2811 if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
<> 144:ef7eb2e8f9f7 2812 {
<> 144:ef7eb2e8f9f7 2813 HAL_TIM_IC_CaptureCallback(htim);
<> 144:ef7eb2e8f9f7 2814 }
<> 144:ef7eb2e8f9f7 2815 /* Output compare event */
<> 144:ef7eb2e8f9f7 2816 else
<> 144:ef7eb2e8f9f7 2817 {
<> 144:ef7eb2e8f9f7 2818 HAL_TIM_OC_DelayElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 2819 HAL_TIM_PWM_PulseFinishedCallback(htim);
<> 144:ef7eb2e8f9f7 2820 }
<> 144:ef7eb2e8f9f7 2821 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 2822 }
<> 144:ef7eb2e8f9f7 2823 }
<> 144:ef7eb2e8f9f7 2824 }
<> 144:ef7eb2e8f9f7 2825 /* Capture compare 2 event */
<> 144:ef7eb2e8f9f7 2826 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
<> 144:ef7eb2e8f9f7 2827 {
<> 144:ef7eb2e8f9f7 2828 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
<> 144:ef7eb2e8f9f7 2829 {
<> 144:ef7eb2e8f9f7 2830 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2831 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<> 144:ef7eb2e8f9f7 2832 /* Input capture event */
<> 144:ef7eb2e8f9f7 2833 if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
<> 144:ef7eb2e8f9f7 2834 {
<> 144:ef7eb2e8f9f7 2835 HAL_TIM_IC_CaptureCallback(htim);
<> 144:ef7eb2e8f9f7 2836 }
<> 144:ef7eb2e8f9f7 2837 /* Output compare event */
<> 144:ef7eb2e8f9f7 2838 else
<> 144:ef7eb2e8f9f7 2839 {
<> 144:ef7eb2e8f9f7 2840 HAL_TIM_OC_DelayElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 2841 HAL_TIM_PWM_PulseFinishedCallback(htim);
<> 144:ef7eb2e8f9f7 2842 }
<> 144:ef7eb2e8f9f7 2843 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 2844 }
<> 144:ef7eb2e8f9f7 2845 }
<> 144:ef7eb2e8f9f7 2846 /* Capture compare 3 event */
<> 144:ef7eb2e8f9f7 2847 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
<> 144:ef7eb2e8f9f7 2848 {
<> 144:ef7eb2e8f9f7 2849 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
<> 144:ef7eb2e8f9f7 2850 {
<> 144:ef7eb2e8f9f7 2851 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 2852 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<> 144:ef7eb2e8f9f7 2853 /* Input capture event */
<> 144:ef7eb2e8f9f7 2854 if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
<> 144:ef7eb2e8f9f7 2855 {
<> 144:ef7eb2e8f9f7 2856 HAL_TIM_IC_CaptureCallback(htim);
<> 144:ef7eb2e8f9f7 2857 }
<> 144:ef7eb2e8f9f7 2858 /* Output compare event */
<> 144:ef7eb2e8f9f7 2859 else
<> 144:ef7eb2e8f9f7 2860 {
<> 144:ef7eb2e8f9f7 2861 HAL_TIM_OC_DelayElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 2862 HAL_TIM_PWM_PulseFinishedCallback(htim);
<> 144:ef7eb2e8f9f7 2863 }
<> 144:ef7eb2e8f9f7 2864 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 2865 }
<> 144:ef7eb2e8f9f7 2866 }
<> 144:ef7eb2e8f9f7 2867 /* Capture compare 4 event */
<> 144:ef7eb2e8f9f7 2868 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
<> 144:ef7eb2e8f9f7 2869 {
<> 144:ef7eb2e8f9f7 2870 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
<> 144:ef7eb2e8f9f7 2871 {
<> 144:ef7eb2e8f9f7 2872 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 2873 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<> 144:ef7eb2e8f9f7 2874 /* Input capture event */
<> 144:ef7eb2e8f9f7 2875 if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
<> 144:ef7eb2e8f9f7 2876 {
<> 144:ef7eb2e8f9f7 2877 HAL_TIM_IC_CaptureCallback(htim);
<> 144:ef7eb2e8f9f7 2878 }
<> 144:ef7eb2e8f9f7 2879 /* Output compare event */
<> 144:ef7eb2e8f9f7 2880 else
<> 144:ef7eb2e8f9f7 2881 {
<> 144:ef7eb2e8f9f7 2882 HAL_TIM_OC_DelayElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 2883 HAL_TIM_PWM_PulseFinishedCallback(htim);
<> 144:ef7eb2e8f9f7 2884 }
<> 144:ef7eb2e8f9f7 2885 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 2886 }
<> 144:ef7eb2e8f9f7 2887 }
<> 144:ef7eb2e8f9f7 2888 /* TIM Update event */
<> 144:ef7eb2e8f9f7 2889 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
<> 144:ef7eb2e8f9f7 2890 {
<> 144:ef7eb2e8f9f7 2891 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
<> 144:ef7eb2e8f9f7 2892 {
<> 144:ef7eb2e8f9f7 2893 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
<> 144:ef7eb2e8f9f7 2894 HAL_TIM_PeriodElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 2895 }
<> 144:ef7eb2e8f9f7 2896 }
<> 144:ef7eb2e8f9f7 2897 /* TIM Break input event */
<> 144:ef7eb2e8f9f7 2898 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
<> 144:ef7eb2e8f9f7 2899 {
<> 144:ef7eb2e8f9f7 2900 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
<> 144:ef7eb2e8f9f7 2901 {
<> 144:ef7eb2e8f9f7 2902 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 2903 HAL_TIMEx_BreakCallback(htim);
<> 144:ef7eb2e8f9f7 2904 }
<> 144:ef7eb2e8f9f7 2905 }
<> 144:ef7eb2e8f9f7 2906 /* TIM Trigger detection event */
<> 144:ef7eb2e8f9f7 2907 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
<> 144:ef7eb2e8f9f7 2908 {
<> 144:ef7eb2e8f9f7 2909 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
<> 144:ef7eb2e8f9f7 2910 {
<> 144:ef7eb2e8f9f7 2911 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
<> 144:ef7eb2e8f9f7 2912 HAL_TIM_TriggerCallback(htim);
<> 144:ef7eb2e8f9f7 2913 }
<> 144:ef7eb2e8f9f7 2914 }
<> 144:ef7eb2e8f9f7 2915 /* TIM commutation event */
<> 144:ef7eb2e8f9f7 2916 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
<> 144:ef7eb2e8f9f7 2917 {
<> 144:ef7eb2e8f9f7 2918 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
<> 144:ef7eb2e8f9f7 2919 {
<> 144:ef7eb2e8f9f7 2920 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
<> 144:ef7eb2e8f9f7 2921 HAL_TIMEx_CommutationCallback(htim);
<> 144:ef7eb2e8f9f7 2922 }
<> 144:ef7eb2e8f9f7 2923 }
<> 144:ef7eb2e8f9f7 2924 }
<> 144:ef7eb2e8f9f7 2925 /**
<> 144:ef7eb2e8f9f7 2926 * @}
<> 144:ef7eb2e8f9f7 2927 */
<> 144:ef7eb2e8f9f7 2928
<> 144:ef7eb2e8f9f7 2929 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
<> 144:ef7eb2e8f9f7 2930 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 2931 *
<> 144:ef7eb2e8f9f7 2932 @verbatim
<> 144:ef7eb2e8f9f7 2933 ==============================================================================
<> 144:ef7eb2e8f9f7 2934 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 2935 ==============================================================================
<> 144:ef7eb2e8f9f7 2936 [..]
<> 144:ef7eb2e8f9f7 2937 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 2938 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
<> 144:ef7eb2e8f9f7 2939 (+) Configure External Clock source.
<> 144:ef7eb2e8f9f7 2940 (+) Configure Complementary channels, break features and dead time.
<> 144:ef7eb2e8f9f7 2941 (+) Configure Master and the Slave synchronization.
<> 144:ef7eb2e8f9f7 2942 (+) Configure the DMA Burst Mode.
<> 144:ef7eb2e8f9f7 2943
<> 144:ef7eb2e8f9f7 2944 @endverbatim
<> 144:ef7eb2e8f9f7 2945 * @{
<> 144:ef7eb2e8f9f7 2946 */
<> 144:ef7eb2e8f9f7 2947
<> 144:ef7eb2e8f9f7 2948 /**
<> 144:ef7eb2e8f9f7 2949 * @brief Initializes the TIM Output Compare Channels according to the specified
<> 144:ef7eb2e8f9f7 2950 * parameters in the TIM_OC_InitTypeDef.
<> 144:ef7eb2e8f9f7 2951 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2952 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2953 * @param sConfig: TIM Output Compare configuration structure
<> 144:ef7eb2e8f9f7 2954 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 2955 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2956 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2957 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2958 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 2959 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 2960 * @retval HAL status
<> 144:ef7eb2e8f9f7 2961 */
<> 144:ef7eb2e8f9f7 2962 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2963 {
<> 144:ef7eb2e8f9f7 2964 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2965 assert_param(IS_TIM_CHANNELS(Channel));
<> 144:ef7eb2e8f9f7 2966 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
<> 144:ef7eb2e8f9f7 2967 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
<> 144:ef7eb2e8f9f7 2968
<> 144:ef7eb2e8f9f7 2969 /* Check input state */
<> 144:ef7eb2e8f9f7 2970 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 2971
<> 144:ef7eb2e8f9f7 2972 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2973
<> 144:ef7eb2e8f9f7 2974 switch (Channel)
<> 144:ef7eb2e8f9f7 2975 {
<> 144:ef7eb2e8f9f7 2976 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 2977 {
<> 144:ef7eb2e8f9f7 2978 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2979 /* Configure the TIM Channel 1 in Output Compare */
<> 144:ef7eb2e8f9f7 2980 TIM_OC1_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 2981 }
<> 144:ef7eb2e8f9f7 2982 break;
<> 144:ef7eb2e8f9f7 2983
<> 144:ef7eb2e8f9f7 2984 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 2985 {
<> 144:ef7eb2e8f9f7 2986 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2987 /* Configure the TIM Channel 2 in Output Compare */
<> 144:ef7eb2e8f9f7 2988 TIM_OC2_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 2989 }
<> 144:ef7eb2e8f9f7 2990 break;
<> 144:ef7eb2e8f9f7 2991
<> 144:ef7eb2e8f9f7 2992 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 2993 {
<> 144:ef7eb2e8f9f7 2994 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2995 /* Configure the TIM Channel 3 in Output Compare */
<> 144:ef7eb2e8f9f7 2996 TIM_OC3_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 2997 }
<> 144:ef7eb2e8f9f7 2998 break;
<> 144:ef7eb2e8f9f7 2999
<> 144:ef7eb2e8f9f7 3000 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 3001 {
<> 144:ef7eb2e8f9f7 3002 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3003 /* Configure the TIM Channel 4 in Output Compare */
<> 144:ef7eb2e8f9f7 3004 TIM_OC4_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 3005 }
<> 144:ef7eb2e8f9f7 3006 break;
<> 144:ef7eb2e8f9f7 3007
<> 144:ef7eb2e8f9f7 3008 default:
<> 144:ef7eb2e8f9f7 3009 break;
<> 144:ef7eb2e8f9f7 3010 }
<> 144:ef7eb2e8f9f7 3011 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3012
<> 144:ef7eb2e8f9f7 3013 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3014
<> 144:ef7eb2e8f9f7 3015 return HAL_OK;
<> 144:ef7eb2e8f9f7 3016 }
<> 144:ef7eb2e8f9f7 3017
<> 144:ef7eb2e8f9f7 3018 /**
<> 144:ef7eb2e8f9f7 3019 * @brief Initializes the TIM Input Capture Channels according to the specified
<> 144:ef7eb2e8f9f7 3020 * parameters in the TIM_IC_InitTypeDef.
<> 144:ef7eb2e8f9f7 3021 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3022 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 3023 * @param sConfig: TIM Input Capture configuration structure
<> 144:ef7eb2e8f9f7 3024 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 3025 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3026 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 3027 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 3028 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 3029 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 3030 * @retval HAL status
<> 144:ef7eb2e8f9f7 3031 */
<> 144:ef7eb2e8f9f7 3032 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 3033 {
<> 144:ef7eb2e8f9f7 3034 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3035 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3036 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
<> 144:ef7eb2e8f9f7 3037 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
<> 144:ef7eb2e8f9f7 3038 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
<> 144:ef7eb2e8f9f7 3039 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
<> 144:ef7eb2e8f9f7 3040
<> 144:ef7eb2e8f9f7 3041 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3042
<> 144:ef7eb2e8f9f7 3043 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3044
<> 144:ef7eb2e8f9f7 3045 if (Channel == TIM_CHANNEL_1)
<> 144:ef7eb2e8f9f7 3046 {
<> 144:ef7eb2e8f9f7 3047 /* TI1 Configuration */
<> 144:ef7eb2e8f9f7 3048 TIM_TI1_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3049 sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 3050 sConfig->ICSelection,
<> 144:ef7eb2e8f9f7 3051 sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 3052
<> 144:ef7eb2e8f9f7 3053 /* Reset the IC1PSC Bits */
<> 144:ef7eb2e8f9f7 3054 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<> 144:ef7eb2e8f9f7 3055
<> 144:ef7eb2e8f9f7 3056 /* Set the IC1PSC value */
<> 144:ef7eb2e8f9f7 3057 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
<> 144:ef7eb2e8f9f7 3058 }
<> 144:ef7eb2e8f9f7 3059 else if (Channel == TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 3060 {
<> 144:ef7eb2e8f9f7 3061 /* TI2 Configuration */
<> 144:ef7eb2e8f9f7 3062 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3063
<> 144:ef7eb2e8f9f7 3064 TIM_TI2_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3065 sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 3066 sConfig->ICSelection,
<> 144:ef7eb2e8f9f7 3067 sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 3068
<> 144:ef7eb2e8f9f7 3069 /* Reset the IC2PSC Bits */
<> 144:ef7eb2e8f9f7 3070 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
<> 144:ef7eb2e8f9f7 3071
<> 144:ef7eb2e8f9f7 3072 /* Set the IC2PSC value */
<> 144:ef7eb2e8f9f7 3073 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
<> 144:ef7eb2e8f9f7 3074 }
<> 144:ef7eb2e8f9f7 3075 else if (Channel == TIM_CHANNEL_3)
<> 144:ef7eb2e8f9f7 3076 {
<> 144:ef7eb2e8f9f7 3077 /* TI3 Configuration */
<> 144:ef7eb2e8f9f7 3078 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3079
<> 144:ef7eb2e8f9f7 3080 TIM_TI3_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3081 sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 3082 sConfig->ICSelection,
<> 144:ef7eb2e8f9f7 3083 sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 3084
<> 144:ef7eb2e8f9f7 3085 /* Reset the IC3PSC Bits */
<> 144:ef7eb2e8f9f7 3086 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
<> 144:ef7eb2e8f9f7 3087
<> 144:ef7eb2e8f9f7 3088 /* Set the IC3PSC value */
<> 144:ef7eb2e8f9f7 3089 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
<> 144:ef7eb2e8f9f7 3090 }
<> 144:ef7eb2e8f9f7 3091 else
<> 144:ef7eb2e8f9f7 3092 {
<> 144:ef7eb2e8f9f7 3093 /* TI4 Configuration */
<> 144:ef7eb2e8f9f7 3094 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3095
<> 144:ef7eb2e8f9f7 3096 TIM_TI4_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3097 sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 3098 sConfig->ICSelection,
<> 144:ef7eb2e8f9f7 3099 sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 3100
<> 144:ef7eb2e8f9f7 3101 /* Reset the IC4PSC Bits */
<> 144:ef7eb2e8f9f7 3102 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
<> 144:ef7eb2e8f9f7 3103
<> 144:ef7eb2e8f9f7 3104 /* Set the IC4PSC value */
<> 144:ef7eb2e8f9f7 3105 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
<> 144:ef7eb2e8f9f7 3106 }
<> 144:ef7eb2e8f9f7 3107
<> 144:ef7eb2e8f9f7 3108 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3109
<> 144:ef7eb2e8f9f7 3110 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3111
<> 144:ef7eb2e8f9f7 3112 return HAL_OK;
<> 144:ef7eb2e8f9f7 3113 }
<> 144:ef7eb2e8f9f7 3114
<> 144:ef7eb2e8f9f7 3115 /**
<> 144:ef7eb2e8f9f7 3116 * @brief Initializes the TIM PWM channels according to the specified
<> 144:ef7eb2e8f9f7 3117 * parameters in the TIM_OC_InitTypeDef.
<> 144:ef7eb2e8f9f7 3118 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3119 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 3120 * @param sConfig: TIM PWM configuration structure
<> 144:ef7eb2e8f9f7 3121 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 3122 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3123 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 3124 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 3125 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 3126 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 3127 * @retval HAL status
<> 144:ef7eb2e8f9f7 3128 */
<> 144:ef7eb2e8f9f7 3129 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 3130 {
<> 144:ef7eb2e8f9f7 3131 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3132
<> 144:ef7eb2e8f9f7 3133 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3134 assert_param(IS_TIM_CHANNELS(Channel));
<> 144:ef7eb2e8f9f7 3135 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
<> 144:ef7eb2e8f9f7 3136 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
<> 144:ef7eb2e8f9f7 3137 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
<> 144:ef7eb2e8f9f7 3138
<> 144:ef7eb2e8f9f7 3139 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3140
<> 144:ef7eb2e8f9f7 3141 switch (Channel)
<> 144:ef7eb2e8f9f7 3142 {
<> 144:ef7eb2e8f9f7 3143 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 3144 {
<> 144:ef7eb2e8f9f7 3145 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3146 /* Configure the Channel 1 in PWM mode */
<> 144:ef7eb2e8f9f7 3147 TIM_OC1_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 3148
<> 144:ef7eb2e8f9f7 3149 /* Set the Preload enable bit for channel1 */
<> 144:ef7eb2e8f9f7 3150 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
<> 144:ef7eb2e8f9f7 3151
<> 144:ef7eb2e8f9f7 3152 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 3153 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
<> 144:ef7eb2e8f9f7 3154 htim->Instance->CCMR1 |= sConfig->OCFastMode;
<> 144:ef7eb2e8f9f7 3155 }
<> 144:ef7eb2e8f9f7 3156 break;
<> 144:ef7eb2e8f9f7 3157
<> 144:ef7eb2e8f9f7 3158 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 3159 {
<> 144:ef7eb2e8f9f7 3160 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3161 /* Configure the Channel 2 in PWM mode */
<> 144:ef7eb2e8f9f7 3162 TIM_OC2_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 3163
<> 144:ef7eb2e8f9f7 3164 /* Set the Preload enable bit for channel2 */
<> 144:ef7eb2e8f9f7 3165 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
<> 144:ef7eb2e8f9f7 3166
<> 144:ef7eb2e8f9f7 3167 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 3168 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
<> 144:ef7eb2e8f9f7 3169 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
<> 144:ef7eb2e8f9f7 3170 }
<> 144:ef7eb2e8f9f7 3171 break;
<> 144:ef7eb2e8f9f7 3172
<> 144:ef7eb2e8f9f7 3173 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 3174 {
<> 144:ef7eb2e8f9f7 3175 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3176 /* Configure the Channel 3 in PWM mode */
<> 144:ef7eb2e8f9f7 3177 TIM_OC3_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 3178
<> 144:ef7eb2e8f9f7 3179 /* Set the Preload enable bit for channel3 */
<> 144:ef7eb2e8f9f7 3180 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
<> 144:ef7eb2e8f9f7 3181
<> 144:ef7eb2e8f9f7 3182 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 3183 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
<> 144:ef7eb2e8f9f7 3184 htim->Instance->CCMR2 |= sConfig->OCFastMode;
<> 144:ef7eb2e8f9f7 3185 }
<> 144:ef7eb2e8f9f7 3186 break;
<> 144:ef7eb2e8f9f7 3187
<> 144:ef7eb2e8f9f7 3188 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 3189 {
<> 144:ef7eb2e8f9f7 3190 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3191 /* Configure the Channel 4 in PWM mode */
<> 144:ef7eb2e8f9f7 3192 TIM_OC4_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 3193
<> 144:ef7eb2e8f9f7 3194 /* Set the Preload enable bit for channel4 */
<> 144:ef7eb2e8f9f7 3195 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
<> 144:ef7eb2e8f9f7 3196
<> 144:ef7eb2e8f9f7 3197 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 3198 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
<> 144:ef7eb2e8f9f7 3199 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
<> 144:ef7eb2e8f9f7 3200 }
<> 144:ef7eb2e8f9f7 3201 break;
<> 144:ef7eb2e8f9f7 3202
<> 144:ef7eb2e8f9f7 3203 default:
<> 144:ef7eb2e8f9f7 3204 break;
<> 144:ef7eb2e8f9f7 3205 }
<> 144:ef7eb2e8f9f7 3206
<> 144:ef7eb2e8f9f7 3207 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3208
<> 144:ef7eb2e8f9f7 3209 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3210
<> 144:ef7eb2e8f9f7 3211 return HAL_OK;
<> 144:ef7eb2e8f9f7 3212 }
<> 144:ef7eb2e8f9f7 3213
<> 144:ef7eb2e8f9f7 3214 /**
<> 144:ef7eb2e8f9f7 3215 * @brief Initializes the TIM One Pulse Channels according to the specified
<> 144:ef7eb2e8f9f7 3216 * parameters in the TIM_OnePulse_InitTypeDef.
<> 144:ef7eb2e8f9f7 3217 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3218 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 3219 * @param sConfig: TIM One Pulse configuration structure
<> 144:ef7eb2e8f9f7 3220 * @param OutputChannel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 3221 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3222 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 3223 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 3224 * @param InputChannel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 3225 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3226 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 3227 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 3228 * @retval HAL status
<> 144:ef7eb2e8f9f7 3229 */
<> 144:ef7eb2e8f9f7 3230 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
<> 144:ef7eb2e8f9f7 3231 {
<> 144:ef7eb2e8f9f7 3232 TIM_OC_InitTypeDef temp1;
<> 144:ef7eb2e8f9f7 3233
<> 144:ef7eb2e8f9f7 3234 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3235 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
<> 144:ef7eb2e8f9f7 3236 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
<> 144:ef7eb2e8f9f7 3237
<> 144:ef7eb2e8f9f7 3238 if(OutputChannel != InputChannel)
<> 144:ef7eb2e8f9f7 3239 {
<> 144:ef7eb2e8f9f7 3240 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3241
<> 144:ef7eb2e8f9f7 3242 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3243
<> 144:ef7eb2e8f9f7 3244 /* Extract the Output compare configuration from sConfig structure */
<> 144:ef7eb2e8f9f7 3245 temp1.OCMode = sConfig->OCMode;
<> 144:ef7eb2e8f9f7 3246 temp1.Pulse = sConfig->Pulse;
<> 144:ef7eb2e8f9f7 3247 temp1.OCPolarity = sConfig->OCPolarity;
<> 144:ef7eb2e8f9f7 3248 temp1.OCNPolarity = sConfig->OCNPolarity;
<> 144:ef7eb2e8f9f7 3249 temp1.OCIdleState = sConfig->OCIdleState;
<> 144:ef7eb2e8f9f7 3250 temp1.OCNIdleState = sConfig->OCNIdleState;
<> 144:ef7eb2e8f9f7 3251
<> 144:ef7eb2e8f9f7 3252 switch (OutputChannel)
<> 144:ef7eb2e8f9f7 3253 {
<> 144:ef7eb2e8f9f7 3254 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 3255 {
<> 144:ef7eb2e8f9f7 3256 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3257
<> 144:ef7eb2e8f9f7 3258 TIM_OC1_SetConfig(htim->Instance, &temp1);
<> 144:ef7eb2e8f9f7 3259 }
<> 144:ef7eb2e8f9f7 3260 break;
<> 144:ef7eb2e8f9f7 3261 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 3262 {
<> 144:ef7eb2e8f9f7 3263 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3264
<> 144:ef7eb2e8f9f7 3265 TIM_OC2_SetConfig(htim->Instance, &temp1);
<> 144:ef7eb2e8f9f7 3266 }
<> 144:ef7eb2e8f9f7 3267 break;
<> 144:ef7eb2e8f9f7 3268 default:
<> 144:ef7eb2e8f9f7 3269 break;
<> 144:ef7eb2e8f9f7 3270 }
<> 144:ef7eb2e8f9f7 3271 switch (InputChannel)
<> 144:ef7eb2e8f9f7 3272 {
<> 144:ef7eb2e8f9f7 3273 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 3274 {
<> 144:ef7eb2e8f9f7 3275 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3276
<> 144:ef7eb2e8f9f7 3277 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 3278 sConfig->ICSelection, sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 3279
<> 144:ef7eb2e8f9f7 3280 /* Reset the IC1PSC Bits */
<> 144:ef7eb2e8f9f7 3281 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<> 144:ef7eb2e8f9f7 3282
<> 144:ef7eb2e8f9f7 3283 /* Select the Trigger source */
<> 144:ef7eb2e8f9f7 3284 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 3285 htim->Instance->SMCR |= TIM_TS_TI1FP1;
<> 144:ef7eb2e8f9f7 3286
<> 144:ef7eb2e8f9f7 3287 /* Select the Slave Mode */
<> 144:ef7eb2e8f9f7 3288 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 3289 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
<> 144:ef7eb2e8f9f7 3290 }
<> 144:ef7eb2e8f9f7 3291 break;
<> 144:ef7eb2e8f9f7 3292 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 3293 {
<> 144:ef7eb2e8f9f7 3294 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3295
<> 144:ef7eb2e8f9f7 3296 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 3297 sConfig->ICSelection, sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 3298
<> 144:ef7eb2e8f9f7 3299 /* Reset the IC2PSC Bits */
<> 144:ef7eb2e8f9f7 3300 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
<> 144:ef7eb2e8f9f7 3301
<> 144:ef7eb2e8f9f7 3302 /* Select the Trigger source */
<> 144:ef7eb2e8f9f7 3303 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 3304 htim->Instance->SMCR |= TIM_TS_TI2FP2;
<> 144:ef7eb2e8f9f7 3305
<> 144:ef7eb2e8f9f7 3306 /* Select the Slave Mode */
<> 144:ef7eb2e8f9f7 3307 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 3308 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
<> 144:ef7eb2e8f9f7 3309 }
<> 144:ef7eb2e8f9f7 3310 break;
<> 144:ef7eb2e8f9f7 3311
<> 144:ef7eb2e8f9f7 3312 default:
<> 144:ef7eb2e8f9f7 3313 break;
<> 144:ef7eb2e8f9f7 3314 }
<> 144:ef7eb2e8f9f7 3315
<> 144:ef7eb2e8f9f7 3316 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3317
<> 144:ef7eb2e8f9f7 3318 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3319
<> 144:ef7eb2e8f9f7 3320 return HAL_OK;
<> 144:ef7eb2e8f9f7 3321 }
<> 144:ef7eb2e8f9f7 3322 else
<> 144:ef7eb2e8f9f7 3323 {
<> 144:ef7eb2e8f9f7 3324 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 3325 }
<> 144:ef7eb2e8f9f7 3326 }
<> 144:ef7eb2e8f9f7 3327
<> 144:ef7eb2e8f9f7 3328 /**
<> 144:ef7eb2e8f9f7 3329 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
<> 144:ef7eb2e8f9f7 3330 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3331 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 3332 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
<> 144:ef7eb2e8f9f7 3333 * This parameters can be on of the following values:
<> 144:ef7eb2e8f9f7 3334 * @arg TIM_DMABASE_CR1
<> 144:ef7eb2e8f9f7 3335 * @arg TIM_DMABASE_CR2
<> 144:ef7eb2e8f9f7 3336 * @arg TIM_DMABASE_SMCR
<> 144:ef7eb2e8f9f7 3337 * @arg TIM_DMABASE_DIER
<> 144:ef7eb2e8f9f7 3338 * @arg TIM_DMABASE_SR
<> 144:ef7eb2e8f9f7 3339 * @arg TIM_DMABASE_EGR
<> 144:ef7eb2e8f9f7 3340 * @arg TIM_DMABASE_CCMR1
<> 144:ef7eb2e8f9f7 3341 * @arg TIM_DMABASE_CCMR2
<> 144:ef7eb2e8f9f7 3342 * @arg TIM_DMABASE_CCER
<> 144:ef7eb2e8f9f7 3343 * @arg TIM_DMABASE_CNT
<> 144:ef7eb2e8f9f7 3344 * @arg TIM_DMABASE_PSC
<> 144:ef7eb2e8f9f7 3345 * @arg TIM_DMABASE_ARR
<> 144:ef7eb2e8f9f7 3346 * @arg TIM_DMABASE_RCR
<> 144:ef7eb2e8f9f7 3347 * @arg TIM_DMABASE_CCR1
<> 144:ef7eb2e8f9f7 3348 * @arg TIM_DMABASE_CCR2
<> 144:ef7eb2e8f9f7 3349 * @arg TIM_DMABASE_CCR3
<> 144:ef7eb2e8f9f7 3350 * @arg TIM_DMABASE_CCR4
<> 144:ef7eb2e8f9f7 3351 * @arg TIM_DMABASE_BDTR
<> 144:ef7eb2e8f9f7 3352 * @arg TIM_DMABASE_DCR
<> 144:ef7eb2e8f9f7 3353 * @param BurstRequestSrc: TIM DMA Request sources.
<> 144:ef7eb2e8f9f7 3354 * This parameters can be on of the following values:
<> 144:ef7eb2e8f9f7 3355 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
<> 144:ef7eb2e8f9f7 3356 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
<> 144:ef7eb2e8f9f7 3357 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
<> 144:ef7eb2e8f9f7 3358 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
<> 144:ef7eb2e8f9f7 3359 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
<> 144:ef7eb2e8f9f7 3360 * @arg TIM_DMA_COM: TIM Commutation DMA source
<> 144:ef7eb2e8f9f7 3361 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
<> 144:ef7eb2e8f9f7 3362 * @param BurstBuffer: The Buffer address.
<> 144:ef7eb2e8f9f7 3363 * @param BurstLength: DMA Burst length. This parameter can be one value
<> 144:ef7eb2e8f9f7 3364 * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
<> 144:ef7eb2e8f9f7 3365 * @retval HAL status
<> 144:ef7eb2e8f9f7 3366 */
<> 144:ef7eb2e8f9f7 3367 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
<> 144:ef7eb2e8f9f7 3368 uint32_t* BurstBuffer, uint32_t BurstLength)
<> 144:ef7eb2e8f9f7 3369 {
<> 144:ef7eb2e8f9f7 3370 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3371 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3372 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
<> 144:ef7eb2e8f9f7 3373 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<> 144:ef7eb2e8f9f7 3374 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
<> 144:ef7eb2e8f9f7 3375
<> 144:ef7eb2e8f9f7 3376 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 3377 {
<> 144:ef7eb2e8f9f7 3378 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 3379 }
<> 144:ef7eb2e8f9f7 3380 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 3381 {
<> 144:ef7eb2e8f9f7 3382 if((BurstBuffer == 0U ) && (BurstLength > 0U))
<> 144:ef7eb2e8f9f7 3383 {
<> 144:ef7eb2e8f9f7 3384 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 3385 }
<> 144:ef7eb2e8f9f7 3386 else
<> 144:ef7eb2e8f9f7 3387 {
<> 144:ef7eb2e8f9f7 3388 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3389 }
<> 144:ef7eb2e8f9f7 3390 }
<> 144:ef7eb2e8f9f7 3391 switch(BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3392 {
<> 144:ef7eb2e8f9f7 3393 case TIM_DMA_UPDATE:
<> 144:ef7eb2e8f9f7 3394 {
<> 144:ef7eb2e8f9f7 3395 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3396 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<> 144:ef7eb2e8f9f7 3397
<> 144:ef7eb2e8f9f7 3398 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3399 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3400
<> 144:ef7eb2e8f9f7 3401 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 3402 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
<> 144:ef7eb2e8f9f7 3403 }
<> 144:ef7eb2e8f9f7 3404 break;
<> 144:ef7eb2e8f9f7 3405 case TIM_DMA_CC1:
<> 144:ef7eb2e8f9f7 3406 {
<> 144:ef7eb2e8f9f7 3407 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3408 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 3409
<> 144:ef7eb2e8f9f7 3410 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3411 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3412
<> 144:ef7eb2e8f9f7 3413 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 3414 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
<> 144:ef7eb2e8f9f7 3415 }
<> 144:ef7eb2e8f9f7 3416 break;
<> 144:ef7eb2e8f9f7 3417 case TIM_DMA_CC2:
<> 144:ef7eb2e8f9f7 3418 {
<> 144:ef7eb2e8f9f7 3419 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3420 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 3421
<> 144:ef7eb2e8f9f7 3422 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3423 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3424
<> 144:ef7eb2e8f9f7 3425 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 3426 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
<> 144:ef7eb2e8f9f7 3427 }
<> 144:ef7eb2e8f9f7 3428 break;
<> 144:ef7eb2e8f9f7 3429 case TIM_DMA_CC3:
<> 144:ef7eb2e8f9f7 3430 {
<> 144:ef7eb2e8f9f7 3431 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3432 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 3433
<> 144:ef7eb2e8f9f7 3434 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3435 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3436
<> 144:ef7eb2e8f9f7 3437 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 3438 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
<> 144:ef7eb2e8f9f7 3439 }
<> 144:ef7eb2e8f9f7 3440 break;
<> 144:ef7eb2e8f9f7 3441 case TIM_DMA_CC4:
<> 144:ef7eb2e8f9f7 3442 {
<> 144:ef7eb2e8f9f7 3443 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3444 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 3445
<> 144:ef7eb2e8f9f7 3446 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3447 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3448
<> 144:ef7eb2e8f9f7 3449 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 3450 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
<> 144:ef7eb2e8f9f7 3451 }
<> 144:ef7eb2e8f9f7 3452 break;
<> 144:ef7eb2e8f9f7 3453 case TIM_DMA_COM:
<> 144:ef7eb2e8f9f7 3454 {
<> 144:ef7eb2e8f9f7 3455 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3456 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
<> 144:ef7eb2e8f9f7 3457
<> 144:ef7eb2e8f9f7 3458 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3459 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3460
<> 144:ef7eb2e8f9f7 3461 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 3462 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
<> 144:ef7eb2e8f9f7 3463 }
<> 144:ef7eb2e8f9f7 3464 break;
<> 144:ef7eb2e8f9f7 3465 case TIM_DMA_TRIGGER:
<> 144:ef7eb2e8f9f7 3466 {
<> 144:ef7eb2e8f9f7 3467 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3468 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
<> 144:ef7eb2e8f9f7 3469
<> 144:ef7eb2e8f9f7 3470 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3471 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3472
<> 144:ef7eb2e8f9f7 3473 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 3474 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
<> 144:ef7eb2e8f9f7 3475 }
<> 144:ef7eb2e8f9f7 3476 break;
<> 144:ef7eb2e8f9f7 3477 default:
<> 144:ef7eb2e8f9f7 3478 break;
<> 144:ef7eb2e8f9f7 3479 }
<> 144:ef7eb2e8f9f7 3480 /* configure the DMA Burst Mode */
<> 144:ef7eb2e8f9f7 3481 htim->Instance->DCR = BurstBaseAddress | BurstLength;
<> 144:ef7eb2e8f9f7 3482
<> 144:ef7eb2e8f9f7 3483 /* Enable the TIM DMA Request */
<> 144:ef7eb2e8f9f7 3484 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
<> 144:ef7eb2e8f9f7 3485
<> 144:ef7eb2e8f9f7 3486 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3487
<> 144:ef7eb2e8f9f7 3488 /* Return function status */
<> 144:ef7eb2e8f9f7 3489 return HAL_OK;
<> 144:ef7eb2e8f9f7 3490 }
<> 144:ef7eb2e8f9f7 3491
<> 144:ef7eb2e8f9f7 3492 /**
<> 144:ef7eb2e8f9f7 3493 * @brief Stops the TIM DMA Burst mode
<> 144:ef7eb2e8f9f7 3494 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3495 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 3496 * @param BurstRequestSrc: TIM DMA Request sources to disable
<> 144:ef7eb2e8f9f7 3497 * @retval HAL status
<> 144:ef7eb2e8f9f7 3498 */
<> 144:ef7eb2e8f9f7 3499 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3500 {
<> 144:ef7eb2e8f9f7 3501 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3502 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<> 144:ef7eb2e8f9f7 3503
<> 144:ef7eb2e8f9f7 3504 /* Abort the DMA transfer (at least disable the DMA channel) */
<> 144:ef7eb2e8f9f7 3505 switch(BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3506 {
<> 144:ef7eb2e8f9f7 3507 case TIM_DMA_UPDATE:
<> 144:ef7eb2e8f9f7 3508 {
<> 144:ef7eb2e8f9f7 3509 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
<> 144:ef7eb2e8f9f7 3510 }
<> 144:ef7eb2e8f9f7 3511 break;
<> 144:ef7eb2e8f9f7 3512 case TIM_DMA_CC1:
<> 144:ef7eb2e8f9f7 3513 {
<> 144:ef7eb2e8f9f7 3514 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
<> 144:ef7eb2e8f9f7 3515 }
<> 144:ef7eb2e8f9f7 3516 break;
<> 144:ef7eb2e8f9f7 3517 case TIM_DMA_CC2:
<> 144:ef7eb2e8f9f7 3518 {
<> 144:ef7eb2e8f9f7 3519 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
<> 144:ef7eb2e8f9f7 3520 }
<> 144:ef7eb2e8f9f7 3521 break;
<> 144:ef7eb2e8f9f7 3522 case TIM_DMA_CC3:
<> 144:ef7eb2e8f9f7 3523 {
<> 144:ef7eb2e8f9f7 3524 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
<> 144:ef7eb2e8f9f7 3525 }
<> 144:ef7eb2e8f9f7 3526 break;
<> 144:ef7eb2e8f9f7 3527 case TIM_DMA_CC4:
<> 144:ef7eb2e8f9f7 3528 {
<> 144:ef7eb2e8f9f7 3529 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
<> 144:ef7eb2e8f9f7 3530 }
<> 144:ef7eb2e8f9f7 3531 break;
<> 144:ef7eb2e8f9f7 3532 case TIM_DMA_COM:
<> 144:ef7eb2e8f9f7 3533 {
<> 144:ef7eb2e8f9f7 3534 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
<> 144:ef7eb2e8f9f7 3535 }
<> 144:ef7eb2e8f9f7 3536 break;
<> 144:ef7eb2e8f9f7 3537 case TIM_DMA_TRIGGER:
<> 144:ef7eb2e8f9f7 3538 {
<> 144:ef7eb2e8f9f7 3539 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
<> 144:ef7eb2e8f9f7 3540 }
<> 144:ef7eb2e8f9f7 3541 break;
<> 144:ef7eb2e8f9f7 3542 default:
<> 144:ef7eb2e8f9f7 3543 break;
<> 144:ef7eb2e8f9f7 3544 }
<> 144:ef7eb2e8f9f7 3545
<> 144:ef7eb2e8f9f7 3546 /* Disable the TIM Update DMA request */
<> 144:ef7eb2e8f9f7 3547 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
<> 144:ef7eb2e8f9f7 3548
<> 144:ef7eb2e8f9f7 3549 /* Return function status */
<> 144:ef7eb2e8f9f7 3550 return HAL_OK;
<> 144:ef7eb2e8f9f7 3551 }
<> 144:ef7eb2e8f9f7 3552
<> 144:ef7eb2e8f9f7 3553 /**
<> 144:ef7eb2e8f9f7 3554 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
<> 144:ef7eb2e8f9f7 3555 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3556 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 3557 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
<> 144:ef7eb2e8f9f7 3558 * This parameters can be on of the following values:
<> 144:ef7eb2e8f9f7 3559 * @arg TIM_DMABASE_CR1
<> 144:ef7eb2e8f9f7 3560 * @arg TIM_DMABASE_CR2
<> 144:ef7eb2e8f9f7 3561 * @arg TIM_DMABASE_SMCR
<> 144:ef7eb2e8f9f7 3562 * @arg TIM_DMABASE_DIER
<> 144:ef7eb2e8f9f7 3563 * @arg TIM_DMABASE_SR
<> 144:ef7eb2e8f9f7 3564 * @arg TIM_DMABASE_EGR
<> 144:ef7eb2e8f9f7 3565 * @arg TIM_DMABASE_CCMR1
<> 144:ef7eb2e8f9f7 3566 * @arg TIM_DMABASE_CCMR2
<> 144:ef7eb2e8f9f7 3567 * @arg TIM_DMABASE_CCER
<> 144:ef7eb2e8f9f7 3568 * @arg TIM_DMABASE_CNT
<> 144:ef7eb2e8f9f7 3569 * @arg TIM_DMABASE_PSC
<> 144:ef7eb2e8f9f7 3570 * @arg TIM_DMABASE_ARR
<> 144:ef7eb2e8f9f7 3571 * @arg TIM_DMABASE_RCR
<> 144:ef7eb2e8f9f7 3572 * @arg TIM_DMABASE_CCR1
<> 144:ef7eb2e8f9f7 3573 * @arg TIM_DMABASE_CCR2
<> 144:ef7eb2e8f9f7 3574 * @arg TIM_DMABASE_CCR3
<> 144:ef7eb2e8f9f7 3575 * @arg TIM_DMABASE_CCR4
<> 144:ef7eb2e8f9f7 3576 * @arg TIM_DMABASE_BDTR
<> 144:ef7eb2e8f9f7 3577 * @arg TIM_DMABASE_DCR
<> 144:ef7eb2e8f9f7 3578 * @param BurstRequestSrc: TIM DMA Request sources.
<> 144:ef7eb2e8f9f7 3579 * This parameters can be on of the following values:
<> 144:ef7eb2e8f9f7 3580 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
<> 144:ef7eb2e8f9f7 3581 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
<> 144:ef7eb2e8f9f7 3582 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
<> 144:ef7eb2e8f9f7 3583 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
<> 144:ef7eb2e8f9f7 3584 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
<> 144:ef7eb2e8f9f7 3585 * @arg TIM_DMA_COM: TIM Commutation DMA source
<> 144:ef7eb2e8f9f7 3586 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
<> 144:ef7eb2e8f9f7 3587 * @param BurstBuffer: The Buffer address.
<> 144:ef7eb2e8f9f7 3588 * @param BurstLength: DMA Burst length. This parameter can be one value
<> 144:ef7eb2e8f9f7 3589 * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
<> 144:ef7eb2e8f9f7 3590 * @retval HAL status
<> 144:ef7eb2e8f9f7 3591 */
<> 144:ef7eb2e8f9f7 3592 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
<> 144:ef7eb2e8f9f7 3593 uint32_t *BurstBuffer, uint32_t BurstLength)
<> 144:ef7eb2e8f9f7 3594 {
<> 144:ef7eb2e8f9f7 3595 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3596 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3597 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
<> 144:ef7eb2e8f9f7 3598 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<> 144:ef7eb2e8f9f7 3599 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
<> 144:ef7eb2e8f9f7 3600
<> 144:ef7eb2e8f9f7 3601 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 3602 {
<> 144:ef7eb2e8f9f7 3603 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 3604 }
<> 144:ef7eb2e8f9f7 3605 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 3606 {
<> 144:ef7eb2e8f9f7 3607 if((BurstBuffer == 0 ) && (BurstLength > 0))
<> 144:ef7eb2e8f9f7 3608 {
<> 144:ef7eb2e8f9f7 3609 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 3610 }
<> 144:ef7eb2e8f9f7 3611 else
<> 144:ef7eb2e8f9f7 3612 {
<> 144:ef7eb2e8f9f7 3613 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3614 }
<> 144:ef7eb2e8f9f7 3615 }
<> 144:ef7eb2e8f9f7 3616 switch(BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3617 {
<> 144:ef7eb2e8f9f7 3618 case TIM_DMA_UPDATE:
<> 144:ef7eb2e8f9f7 3619 {
<> 144:ef7eb2e8f9f7 3620 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3621 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<> 144:ef7eb2e8f9f7 3622
<> 144:ef7eb2e8f9f7 3623 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3624 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3625
<> 144:ef7eb2e8f9f7 3626 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 3627 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<> 144:ef7eb2e8f9f7 3628 }
<> 144:ef7eb2e8f9f7 3629 break;
<> 144:ef7eb2e8f9f7 3630 case TIM_DMA_CC1:
<> 144:ef7eb2e8f9f7 3631 {
<> 144:ef7eb2e8f9f7 3632 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3633 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 3634
<> 144:ef7eb2e8f9f7 3635 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3636 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3637
<> 144:ef7eb2e8f9f7 3638 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 3639 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<> 144:ef7eb2e8f9f7 3640 }
<> 144:ef7eb2e8f9f7 3641 break;
<> 144:ef7eb2e8f9f7 3642 case TIM_DMA_CC2:
<> 144:ef7eb2e8f9f7 3643 {
<> 144:ef7eb2e8f9f7 3644 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3645 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 3646
<> 144:ef7eb2e8f9f7 3647 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3648 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3649
<> 144:ef7eb2e8f9f7 3650 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 3651 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<> 144:ef7eb2e8f9f7 3652 }
<> 144:ef7eb2e8f9f7 3653 break;
<> 144:ef7eb2e8f9f7 3654 case TIM_DMA_CC3:
<> 144:ef7eb2e8f9f7 3655 {
<> 144:ef7eb2e8f9f7 3656 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3657 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 3658
<> 144:ef7eb2e8f9f7 3659 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3660 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3661
<> 144:ef7eb2e8f9f7 3662 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 3663 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<> 144:ef7eb2e8f9f7 3664 }
<> 144:ef7eb2e8f9f7 3665 break;
<> 144:ef7eb2e8f9f7 3666 case TIM_DMA_CC4:
<> 144:ef7eb2e8f9f7 3667 {
<> 144:ef7eb2e8f9f7 3668 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3669 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 3670
<> 144:ef7eb2e8f9f7 3671 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3672 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3673
<> 144:ef7eb2e8f9f7 3674 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 3675 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<> 144:ef7eb2e8f9f7 3676 }
<> 144:ef7eb2e8f9f7 3677 break;
<> 144:ef7eb2e8f9f7 3678 case TIM_DMA_COM:
<> 144:ef7eb2e8f9f7 3679 {
<> 144:ef7eb2e8f9f7 3680 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3681 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
<> 144:ef7eb2e8f9f7 3682
<> 144:ef7eb2e8f9f7 3683 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3684 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3685
<> 144:ef7eb2e8f9f7 3686 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 3687 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<> 144:ef7eb2e8f9f7 3688 }
<> 144:ef7eb2e8f9f7 3689 break;
<> 144:ef7eb2e8f9f7 3690 case TIM_DMA_TRIGGER:
<> 144:ef7eb2e8f9f7 3691 {
<> 144:ef7eb2e8f9f7 3692 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3693 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
<> 144:ef7eb2e8f9f7 3694
<> 144:ef7eb2e8f9f7 3695 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3696 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3697
<> 144:ef7eb2e8f9f7 3698 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 3699 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<> 144:ef7eb2e8f9f7 3700 }
<> 144:ef7eb2e8f9f7 3701 break;
<> 144:ef7eb2e8f9f7 3702 default:
<> 144:ef7eb2e8f9f7 3703 break;
<> 144:ef7eb2e8f9f7 3704 }
<> 144:ef7eb2e8f9f7 3705
<> 144:ef7eb2e8f9f7 3706 /* configure the DMA Burst Mode */
<> 144:ef7eb2e8f9f7 3707 htim->Instance->DCR = BurstBaseAddress | BurstLength;
<> 144:ef7eb2e8f9f7 3708
<> 144:ef7eb2e8f9f7 3709 /* Enable the TIM DMA Request */
<> 144:ef7eb2e8f9f7 3710 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
<> 144:ef7eb2e8f9f7 3711
<> 144:ef7eb2e8f9f7 3712 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3713
<> 144:ef7eb2e8f9f7 3714 /* Return function status */
<> 144:ef7eb2e8f9f7 3715 return HAL_OK;
<> 144:ef7eb2e8f9f7 3716 }
<> 144:ef7eb2e8f9f7 3717
<> 144:ef7eb2e8f9f7 3718 /**
<> 144:ef7eb2e8f9f7 3719 * @brief Stop the DMA burst reading
<> 144:ef7eb2e8f9f7 3720 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3721 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 3722 * @param BurstRequestSrc: TIM DMA Request sources to disable.
<> 144:ef7eb2e8f9f7 3723 * @retval HAL status
<> 144:ef7eb2e8f9f7 3724 */
<> 144:ef7eb2e8f9f7 3725 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3726 {
<> 144:ef7eb2e8f9f7 3727 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3728 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<> 144:ef7eb2e8f9f7 3729
<> 144:ef7eb2e8f9f7 3730 /* Abort the DMA transfer (at least disable the DMA channel) */
<> 144:ef7eb2e8f9f7 3731 switch(BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3732 {
<> 144:ef7eb2e8f9f7 3733 case TIM_DMA_UPDATE:
<> 144:ef7eb2e8f9f7 3734 {
<> 144:ef7eb2e8f9f7 3735 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
<> 144:ef7eb2e8f9f7 3736 }
<> 144:ef7eb2e8f9f7 3737 break;
<> 144:ef7eb2e8f9f7 3738 case TIM_DMA_CC1:
<> 144:ef7eb2e8f9f7 3739 {
<> 144:ef7eb2e8f9f7 3740 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
<> 144:ef7eb2e8f9f7 3741 }
<> 144:ef7eb2e8f9f7 3742 break;
<> 144:ef7eb2e8f9f7 3743 case TIM_DMA_CC2:
<> 144:ef7eb2e8f9f7 3744 {
<> 144:ef7eb2e8f9f7 3745 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
<> 144:ef7eb2e8f9f7 3746 }
<> 144:ef7eb2e8f9f7 3747 break;
<> 144:ef7eb2e8f9f7 3748 case TIM_DMA_CC3:
<> 144:ef7eb2e8f9f7 3749 {
<> 144:ef7eb2e8f9f7 3750 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
<> 144:ef7eb2e8f9f7 3751 }
<> 144:ef7eb2e8f9f7 3752 break;
<> 144:ef7eb2e8f9f7 3753 case TIM_DMA_CC4:
<> 144:ef7eb2e8f9f7 3754 {
<> 144:ef7eb2e8f9f7 3755 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
<> 144:ef7eb2e8f9f7 3756 }
<> 144:ef7eb2e8f9f7 3757 break;
<> 144:ef7eb2e8f9f7 3758 case TIM_DMA_COM:
<> 144:ef7eb2e8f9f7 3759 {
<> 144:ef7eb2e8f9f7 3760 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
<> 144:ef7eb2e8f9f7 3761 }
<> 144:ef7eb2e8f9f7 3762 break;
<> 144:ef7eb2e8f9f7 3763 case TIM_DMA_TRIGGER:
<> 144:ef7eb2e8f9f7 3764 {
<> 144:ef7eb2e8f9f7 3765 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
<> 144:ef7eb2e8f9f7 3766 }
<> 144:ef7eb2e8f9f7 3767 break;
<> 144:ef7eb2e8f9f7 3768 default:
<> 144:ef7eb2e8f9f7 3769 break;
<> 144:ef7eb2e8f9f7 3770 }
<> 144:ef7eb2e8f9f7 3771
<> 144:ef7eb2e8f9f7 3772 /* Disable the TIM Update DMA request */
<> 144:ef7eb2e8f9f7 3773 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
<> 144:ef7eb2e8f9f7 3774
<> 144:ef7eb2e8f9f7 3775 /* Return function status */
<> 144:ef7eb2e8f9f7 3776 return HAL_OK;
<> 144:ef7eb2e8f9f7 3777 }
<> 144:ef7eb2e8f9f7 3778
<> 144:ef7eb2e8f9f7 3779 /**
<> 144:ef7eb2e8f9f7 3780 * @brief Generate a software event
<> 144:ef7eb2e8f9f7 3781 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3782 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 3783 * @param EventSource: specifies the event source.
<> 144:ef7eb2e8f9f7 3784 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3785 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
<> 144:ef7eb2e8f9f7 3786 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
<> 144:ef7eb2e8f9f7 3787 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
<> 144:ef7eb2e8f9f7 3788 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
<> 144:ef7eb2e8f9f7 3789 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
<> 144:ef7eb2e8f9f7 3790 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
<> 144:ef7eb2e8f9f7 3791 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
<> 144:ef7eb2e8f9f7 3792 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
<> 144:ef7eb2e8f9f7 3793 * @note TIM6 and TIM7 can only generate an update event.
<> 144:ef7eb2e8f9f7 3794 * @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1 and TIM8.
<> 144:ef7eb2e8f9f7 3795 * @retval HAL status
<> 144:ef7eb2e8f9f7 3796 */
<> 144:ef7eb2e8f9f7 3797
<> 144:ef7eb2e8f9f7 3798 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
<> 144:ef7eb2e8f9f7 3799 {
<> 144:ef7eb2e8f9f7 3800 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3801 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3802 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
<> 144:ef7eb2e8f9f7 3803
<> 144:ef7eb2e8f9f7 3804 /* Process Locked */
<> 144:ef7eb2e8f9f7 3805 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3806
<> 144:ef7eb2e8f9f7 3807 /* Change the TIM state */
<> 144:ef7eb2e8f9f7 3808 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3809
<> 144:ef7eb2e8f9f7 3810 /* Set the event sources */
<> 144:ef7eb2e8f9f7 3811 htim->Instance->EGR = EventSource;
<> 144:ef7eb2e8f9f7 3812
<> 144:ef7eb2e8f9f7 3813 /* Change the TIM state */
<> 144:ef7eb2e8f9f7 3814 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3815
<> 144:ef7eb2e8f9f7 3816 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3817
<> 144:ef7eb2e8f9f7 3818 /* Return function status */
<> 144:ef7eb2e8f9f7 3819 return HAL_OK;
<> 144:ef7eb2e8f9f7 3820 }
<> 144:ef7eb2e8f9f7 3821
<> 144:ef7eb2e8f9f7 3822 /**
<> 144:ef7eb2e8f9f7 3823 * @brief Configures the OCRef clear feature
<> 144:ef7eb2e8f9f7 3824 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3825 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 3826 * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 3827 * contains the OCREF clear feature and parameters for the TIM peripheral.
<> 144:ef7eb2e8f9f7 3828 * @param Channel: specifies the TIM Channel.
<> 144:ef7eb2e8f9f7 3829 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3830 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 3831 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 3832 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 3833 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 3834 * @retval HAL status
<> 144:ef7eb2e8f9f7 3835 */
<> 144:ef7eb2e8f9f7 3836 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 3837 {
<> 144:ef7eb2e8f9f7 3838 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3839 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3840 assert_param(IS_TIM_CHANNELS(Channel));
<> 144:ef7eb2e8f9f7 3841 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
<> 144:ef7eb2e8f9f7 3842 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
<> 144:ef7eb2e8f9f7 3843 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
<> 144:ef7eb2e8f9f7 3844 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
<> 144:ef7eb2e8f9f7 3845
<> 144:ef7eb2e8f9f7 3846 /* Process Locked */
<> 144:ef7eb2e8f9f7 3847 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3848
<> 144:ef7eb2e8f9f7 3849 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3850
<> 144:ef7eb2e8f9f7 3851 if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
<> 144:ef7eb2e8f9f7 3852 {
<> 144:ef7eb2e8f9f7 3853 TIM_ETR_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3854 sClearInputConfig->ClearInputPrescaler,
<> 144:ef7eb2e8f9f7 3855 sClearInputConfig->ClearInputPolarity,
<> 144:ef7eb2e8f9f7 3856 sClearInputConfig->ClearInputFilter);
<> 144:ef7eb2e8f9f7 3857 }
<> 144:ef7eb2e8f9f7 3858
<> 144:ef7eb2e8f9f7 3859 switch (Channel)
<> 144:ef7eb2e8f9f7 3860 {
<> 144:ef7eb2e8f9f7 3861 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 3862 {
<> 144:ef7eb2e8f9f7 3863 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 3864 {
<> 144:ef7eb2e8f9f7 3865 /* Enable the Ocref clear feature for Channel 1 */
<> 144:ef7eb2e8f9f7 3866 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
<> 144:ef7eb2e8f9f7 3867 }
<> 144:ef7eb2e8f9f7 3868 else
<> 144:ef7eb2e8f9f7 3869 {
<> 144:ef7eb2e8f9f7 3870 /* Disable the Ocref clear feature for Channel 1 */
<> 144:ef7eb2e8f9f7 3871 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
<> 144:ef7eb2e8f9f7 3872 }
<> 144:ef7eb2e8f9f7 3873 }
<> 144:ef7eb2e8f9f7 3874 break;
<> 144:ef7eb2e8f9f7 3875 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 3876 {
<> 144:ef7eb2e8f9f7 3877 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3878 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 3879 {
<> 144:ef7eb2e8f9f7 3880 /* Enable the Ocref clear feature for Channel 2 */
<> 144:ef7eb2e8f9f7 3881 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
<> 144:ef7eb2e8f9f7 3882 }
<> 144:ef7eb2e8f9f7 3883 else
<> 144:ef7eb2e8f9f7 3884 {
<> 144:ef7eb2e8f9f7 3885 /* Disable the Ocref clear feature for Channel 2 */
<> 144:ef7eb2e8f9f7 3886 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
<> 144:ef7eb2e8f9f7 3887 }
<> 144:ef7eb2e8f9f7 3888 }
<> 144:ef7eb2e8f9f7 3889 break;
<> 144:ef7eb2e8f9f7 3890 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 3891 {
<> 144:ef7eb2e8f9f7 3892 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3893 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 3894 {
<> 144:ef7eb2e8f9f7 3895 /* Enable the Ocref clear feature for Channel 3 */
<> 144:ef7eb2e8f9f7 3896 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
<> 144:ef7eb2e8f9f7 3897 }
<> 144:ef7eb2e8f9f7 3898 else
<> 144:ef7eb2e8f9f7 3899 {
<> 144:ef7eb2e8f9f7 3900 /* Disable the Ocref clear feature for Channel 3 */
<> 144:ef7eb2e8f9f7 3901 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
<> 144:ef7eb2e8f9f7 3902 }
<> 144:ef7eb2e8f9f7 3903 }
<> 144:ef7eb2e8f9f7 3904 break;
<> 144:ef7eb2e8f9f7 3905 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 3906 {
<> 144:ef7eb2e8f9f7 3907 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3908 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 3909 {
<> 144:ef7eb2e8f9f7 3910 /* Enable the Ocref clear feature for Channel 4 */
<> 144:ef7eb2e8f9f7 3911 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
<> 144:ef7eb2e8f9f7 3912 }
<> 144:ef7eb2e8f9f7 3913 else
<> 144:ef7eb2e8f9f7 3914 {
<> 144:ef7eb2e8f9f7 3915 /* Disable the Ocref clear feature for Channel 4 */
<> 144:ef7eb2e8f9f7 3916 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
<> 144:ef7eb2e8f9f7 3917 }
<> 144:ef7eb2e8f9f7 3918 }
<> 144:ef7eb2e8f9f7 3919 break;
<> 144:ef7eb2e8f9f7 3920 default:
<> 144:ef7eb2e8f9f7 3921 break;
<> 144:ef7eb2e8f9f7 3922 }
<> 144:ef7eb2e8f9f7 3923
<> 144:ef7eb2e8f9f7 3924 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3925
<> 144:ef7eb2e8f9f7 3926 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3927
<> 144:ef7eb2e8f9f7 3928 return HAL_OK;
<> 144:ef7eb2e8f9f7 3929 }
<> 144:ef7eb2e8f9f7 3930
<> 144:ef7eb2e8f9f7 3931 /**
<> 144:ef7eb2e8f9f7 3932 * @brief Configures the clock source to be used
<> 144:ef7eb2e8f9f7 3933 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3934 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 3935 * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 3936 * contains the clock source information for the TIM peripheral.
<> 144:ef7eb2e8f9f7 3937 * @retval HAL status
<> 144:ef7eb2e8f9f7 3938 */
<> 144:ef7eb2e8f9f7 3939 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
<> 144:ef7eb2e8f9f7 3940 {
<> 144:ef7eb2e8f9f7 3941 uint32_t tmpsmcr = 0U;
<> 144:ef7eb2e8f9f7 3942
<> 144:ef7eb2e8f9f7 3943 /* Process Locked */
<> 144:ef7eb2e8f9f7 3944 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3945
<> 144:ef7eb2e8f9f7 3946 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3947
<> 144:ef7eb2e8f9f7 3948 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3949 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
<> 144:ef7eb2e8f9f7 3950
<> 144:ef7eb2e8f9f7 3951 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
<> 144:ef7eb2e8f9f7 3952 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 3953 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
<> 144:ef7eb2e8f9f7 3954 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
<> 144:ef7eb2e8f9f7 3955 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 3956
<> 144:ef7eb2e8f9f7 3957 switch (sClockSourceConfig->ClockSource)
<> 144:ef7eb2e8f9f7 3958 {
<> 144:ef7eb2e8f9f7 3959 case TIM_CLOCKSOURCE_INTERNAL:
<> 144:ef7eb2e8f9f7 3960 {
<> 144:ef7eb2e8f9f7 3961 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3962
<> 144:ef7eb2e8f9f7 3963 /* Disable slave mode to clock the prescaler directly with the internal clock */
<> 144:ef7eb2e8f9f7 3964 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 3965 }
<> 144:ef7eb2e8f9f7 3966 break;
<> 144:ef7eb2e8f9f7 3967
<> 144:ef7eb2e8f9f7 3968 case TIM_CLOCKSOURCE_ETRMODE1:
<> 144:ef7eb2e8f9f7 3969 {
<> 144:ef7eb2e8f9f7 3970 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3971
<> 144:ef7eb2e8f9f7 3972 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<> 144:ef7eb2e8f9f7 3973 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
<> 144:ef7eb2e8f9f7 3974 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<> 144:ef7eb2e8f9f7 3975
<> 144:ef7eb2e8f9f7 3976 /* Configure the ETR Clock source */
<> 144:ef7eb2e8f9f7 3977 TIM_ETR_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3978 sClockSourceConfig->ClockPrescaler,
<> 144:ef7eb2e8f9f7 3979 sClockSourceConfig->ClockPolarity,
<> 144:ef7eb2e8f9f7 3980 sClockSourceConfig->ClockFilter);
<> 144:ef7eb2e8f9f7 3981 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 3982 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 3983 /* Reset the SMS and TS Bits */
<> 144:ef7eb2e8f9f7 3984 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
<> 144:ef7eb2e8f9f7 3985 /* Select the External clock mode1 and the ETRF trigger */
<> 144:ef7eb2e8f9f7 3986 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
<> 144:ef7eb2e8f9f7 3987 /* Write to TIMx SMCR */
<> 144:ef7eb2e8f9f7 3988 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 3989 }
<> 144:ef7eb2e8f9f7 3990 break;
<> 144:ef7eb2e8f9f7 3991
<> 144:ef7eb2e8f9f7 3992 case TIM_CLOCKSOURCE_ETRMODE2:
<> 144:ef7eb2e8f9f7 3993 {
<> 144:ef7eb2e8f9f7 3994 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3995
<> 144:ef7eb2e8f9f7 3996 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<> 144:ef7eb2e8f9f7 3997 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
<> 144:ef7eb2e8f9f7 3998 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<> 144:ef7eb2e8f9f7 3999
<> 144:ef7eb2e8f9f7 4000 /* Configure the ETR Clock source */
<> 144:ef7eb2e8f9f7 4001 TIM_ETR_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 4002 sClockSourceConfig->ClockPrescaler,
<> 144:ef7eb2e8f9f7 4003 sClockSourceConfig->ClockPolarity,
<> 144:ef7eb2e8f9f7 4004 sClockSourceConfig->ClockFilter);
<> 144:ef7eb2e8f9f7 4005 /* Enable the External clock mode2 */
<> 144:ef7eb2e8f9f7 4006 htim->Instance->SMCR |= TIM_SMCR_ECE;
<> 144:ef7eb2e8f9f7 4007 }
<> 144:ef7eb2e8f9f7 4008 break;
<> 144:ef7eb2e8f9f7 4009
<> 144:ef7eb2e8f9f7 4010 case TIM_CLOCKSOURCE_TI1:
<> 144:ef7eb2e8f9f7 4011 {
<> 144:ef7eb2e8f9f7 4012 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4013
<> 144:ef7eb2e8f9f7 4014 /* Check TI1 input conditioning related parameters */
<> 144:ef7eb2e8f9f7 4015 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<> 144:ef7eb2e8f9f7 4016 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<> 144:ef7eb2e8f9f7 4017
<> 144:ef7eb2e8f9f7 4018 TIM_TI1_ConfigInputStage(htim->Instance,
<> 144:ef7eb2e8f9f7 4019 sClockSourceConfig->ClockPolarity,
<> 144:ef7eb2e8f9f7 4020 sClockSourceConfig->ClockFilter);
<> 144:ef7eb2e8f9f7 4021 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
<> 144:ef7eb2e8f9f7 4022 }
<> 144:ef7eb2e8f9f7 4023 break;
<> 144:ef7eb2e8f9f7 4024 case TIM_CLOCKSOURCE_TI2:
<> 144:ef7eb2e8f9f7 4025 {
<> 144:ef7eb2e8f9f7 4026 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4027
<> 144:ef7eb2e8f9f7 4028 /* Check TI1 input conditioning related parameters */
<> 144:ef7eb2e8f9f7 4029 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<> 144:ef7eb2e8f9f7 4030 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<> 144:ef7eb2e8f9f7 4031
<> 144:ef7eb2e8f9f7 4032 TIM_TI2_ConfigInputStage(htim->Instance,
<> 144:ef7eb2e8f9f7 4033 sClockSourceConfig->ClockPolarity,
<> 144:ef7eb2e8f9f7 4034 sClockSourceConfig->ClockFilter);
<> 144:ef7eb2e8f9f7 4035 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
<> 144:ef7eb2e8f9f7 4036 }
<> 144:ef7eb2e8f9f7 4037 break;
<> 144:ef7eb2e8f9f7 4038 case TIM_CLOCKSOURCE_TI1ED:
<> 144:ef7eb2e8f9f7 4039 {
<> 144:ef7eb2e8f9f7 4040 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4041
<> 144:ef7eb2e8f9f7 4042 /* Check TI1 input conditioning related parameters */
<> 144:ef7eb2e8f9f7 4043 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<> 144:ef7eb2e8f9f7 4044 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<> 144:ef7eb2e8f9f7 4045
<> 144:ef7eb2e8f9f7 4046 TIM_TI1_ConfigInputStage(htim->Instance,
<> 144:ef7eb2e8f9f7 4047 sClockSourceConfig->ClockPolarity,
<> 144:ef7eb2e8f9f7 4048 sClockSourceConfig->ClockFilter);
<> 144:ef7eb2e8f9f7 4049 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
<> 144:ef7eb2e8f9f7 4050 }
<> 144:ef7eb2e8f9f7 4051 break;
<> 144:ef7eb2e8f9f7 4052 case TIM_CLOCKSOURCE_ITR0:
<> 144:ef7eb2e8f9f7 4053 {
<> 144:ef7eb2e8f9f7 4054 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4055 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
<> 144:ef7eb2e8f9f7 4056 }
<> 144:ef7eb2e8f9f7 4057 break;
<> 144:ef7eb2e8f9f7 4058 case TIM_CLOCKSOURCE_ITR1:
<> 144:ef7eb2e8f9f7 4059 {
<> 144:ef7eb2e8f9f7 4060 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4061 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
<> 144:ef7eb2e8f9f7 4062 }
<> 144:ef7eb2e8f9f7 4063 break;
<> 144:ef7eb2e8f9f7 4064 case TIM_CLOCKSOURCE_ITR2:
<> 144:ef7eb2e8f9f7 4065 {
<> 144:ef7eb2e8f9f7 4066 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4067 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
<> 144:ef7eb2e8f9f7 4068 }
<> 144:ef7eb2e8f9f7 4069 break;
<> 144:ef7eb2e8f9f7 4070 case TIM_CLOCKSOURCE_ITR3:
<> 144:ef7eb2e8f9f7 4071 {
<> 144:ef7eb2e8f9f7 4072 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4073 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
<> 144:ef7eb2e8f9f7 4074 }
<> 144:ef7eb2e8f9f7 4075 break;
<> 144:ef7eb2e8f9f7 4076
<> 144:ef7eb2e8f9f7 4077 default:
<> 144:ef7eb2e8f9f7 4078 break;
<> 144:ef7eb2e8f9f7 4079 }
<> 144:ef7eb2e8f9f7 4080 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4081
<> 144:ef7eb2e8f9f7 4082 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 4083
<> 144:ef7eb2e8f9f7 4084 return HAL_OK;
<> 144:ef7eb2e8f9f7 4085 }
<> 144:ef7eb2e8f9f7 4086
<> 144:ef7eb2e8f9f7 4087 /**
<> 144:ef7eb2e8f9f7 4088 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
<> 144:ef7eb2e8f9f7 4089 * or a XOR combination between CH1_input, CH2_input & CH3_input
<> 144:ef7eb2e8f9f7 4090 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4091 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 4092 * @param TI1_Selection: Indicate whether or not channel 1 is connected to the
<> 144:ef7eb2e8f9f7 4093 * output of a XOR gate.
<> 144:ef7eb2e8f9f7 4094 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 4095 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
<> 144:ef7eb2e8f9f7 4096 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
<> 144:ef7eb2e8f9f7 4097 * pins are connected to the TI1 input (XOR combination)
<> 144:ef7eb2e8f9f7 4098 * @retval HAL status
<> 144:ef7eb2e8f9f7 4099 */
<> 144:ef7eb2e8f9f7 4100 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
<> 144:ef7eb2e8f9f7 4101 {
<> 144:ef7eb2e8f9f7 4102 uint32_t tmpcr2 = 0U;
<> 144:ef7eb2e8f9f7 4103
<> 144:ef7eb2e8f9f7 4104 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4105 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4106 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
<> 144:ef7eb2e8f9f7 4107
<> 144:ef7eb2e8f9f7 4108 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 4109 tmpcr2 = htim->Instance->CR2;
<> 144:ef7eb2e8f9f7 4110
<> 144:ef7eb2e8f9f7 4111 /* Reset the TI1 selection */
<> 144:ef7eb2e8f9f7 4112 tmpcr2 &= ~TIM_CR2_TI1S;
<> 144:ef7eb2e8f9f7 4113
<> 144:ef7eb2e8f9f7 4114 /* Set the TI1 selection */
<> 144:ef7eb2e8f9f7 4115 tmpcr2 |= TI1_Selection;
<> 144:ef7eb2e8f9f7 4116
<> 144:ef7eb2e8f9f7 4117 /* Write to TIMxCR2 */
<> 144:ef7eb2e8f9f7 4118 htim->Instance->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 4119
<> 144:ef7eb2e8f9f7 4120 return HAL_OK;
<> 144:ef7eb2e8f9f7 4121 }
<> 144:ef7eb2e8f9f7 4122
<> 144:ef7eb2e8f9f7 4123 /**
<> 144:ef7eb2e8f9f7 4124 * @brief Configures the TIM in Slave mode
<> 144:ef7eb2e8f9f7 4125 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4126 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 4127 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 4128 * contains the selected trigger (internal trigger input, filtered
<> 144:ef7eb2e8f9f7 4129 * timer input or external trigger input) and the ) and the Slave
<> 144:ef7eb2e8f9f7 4130 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
<> 144:ef7eb2e8f9f7 4131 * @retval HAL status
<> 144:ef7eb2e8f9f7 4132 */
<> 144:ef7eb2e8f9f7 4133 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
<> 144:ef7eb2e8f9f7 4134 {
<> 144:ef7eb2e8f9f7 4135 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4136 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4137 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
<> 144:ef7eb2e8f9f7 4138 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
<> 144:ef7eb2e8f9f7 4139
<> 144:ef7eb2e8f9f7 4140 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 4141
<> 144:ef7eb2e8f9f7 4142 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 4143
<> 144:ef7eb2e8f9f7 4144 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
<> 144:ef7eb2e8f9f7 4145
<> 144:ef7eb2e8f9f7 4146 /* Disable Trigger Interrupt */
<> 144:ef7eb2e8f9f7 4147 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
<> 144:ef7eb2e8f9f7 4148
<> 144:ef7eb2e8f9f7 4149 /* Disable Trigger DMA request */
<> 144:ef7eb2e8f9f7 4150 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
<> 144:ef7eb2e8f9f7 4151
<> 144:ef7eb2e8f9f7 4152 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4153
<> 144:ef7eb2e8f9f7 4154 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 4155
<> 144:ef7eb2e8f9f7 4156 return HAL_OK;
<> 144:ef7eb2e8f9f7 4157 }
<> 144:ef7eb2e8f9f7 4158
<> 144:ef7eb2e8f9f7 4159 /**
<> 144:ef7eb2e8f9f7 4160 * @brief Configures the TIM in Slave mode in interrupt mode
<> 144:ef7eb2e8f9f7 4161 * @param htim: TIM handle.
<> 144:ef7eb2e8f9f7 4162 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 4163 * contains the selected trigger (internal trigger input, filtered
<> 144:ef7eb2e8f9f7 4164 * timer input or external trigger input) and the ) and the Slave
<> 144:ef7eb2e8f9f7 4165 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
<> 144:ef7eb2e8f9f7 4166 * @retval HAL status
<> 144:ef7eb2e8f9f7 4167 */
<> 144:ef7eb2e8f9f7 4168 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 4169 TIM_SlaveConfigTypeDef * sSlaveConfig)
<> 144:ef7eb2e8f9f7 4170 {
<> 144:ef7eb2e8f9f7 4171 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4172 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4173 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
<> 144:ef7eb2e8f9f7 4174 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
<> 144:ef7eb2e8f9f7 4175
<> 144:ef7eb2e8f9f7 4176 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 4177
<> 144:ef7eb2e8f9f7 4178 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 4179
<> 144:ef7eb2e8f9f7 4180 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
<> 144:ef7eb2e8f9f7 4181
<> 144:ef7eb2e8f9f7 4182 /* Enable Trigger Interrupt */
<> 144:ef7eb2e8f9f7 4183 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
<> 144:ef7eb2e8f9f7 4184
<> 144:ef7eb2e8f9f7 4185 /* Disable Trigger DMA request */
<> 144:ef7eb2e8f9f7 4186 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
<> 144:ef7eb2e8f9f7 4187
<> 144:ef7eb2e8f9f7 4188 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4189
<> 144:ef7eb2e8f9f7 4190 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 4191
<> 144:ef7eb2e8f9f7 4192 return HAL_OK;
<> 144:ef7eb2e8f9f7 4193 }
<> 144:ef7eb2e8f9f7 4194
<> 144:ef7eb2e8f9f7 4195 /**
<> 144:ef7eb2e8f9f7 4196 * @brief Read the captured value from Capture Compare unit
<> 144:ef7eb2e8f9f7 4197 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4198 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 4199 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 4200 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 4201 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 4202 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 4203 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 4204 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 4205 * @retval Captured value
<> 144:ef7eb2e8f9f7 4206 */
<> 144:ef7eb2e8f9f7 4207 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 4208 {
<> 144:ef7eb2e8f9f7 4209 uint32_t tmpreg = 0U;
<> 144:ef7eb2e8f9f7 4210
<> 144:ef7eb2e8f9f7 4211 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 4212
<> 144:ef7eb2e8f9f7 4213 switch (Channel)
<> 144:ef7eb2e8f9f7 4214 {
<> 144:ef7eb2e8f9f7 4215 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 4216 {
<> 144:ef7eb2e8f9f7 4217 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4218 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4219
<> 144:ef7eb2e8f9f7 4220 /* Return the capture 1 value */
<> 144:ef7eb2e8f9f7 4221 tmpreg = htim->Instance->CCR1;
<> 144:ef7eb2e8f9f7 4222
<> 144:ef7eb2e8f9f7 4223 break;
<> 144:ef7eb2e8f9f7 4224 }
<> 144:ef7eb2e8f9f7 4225 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 4226 {
<> 144:ef7eb2e8f9f7 4227 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4228 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4229
<> 144:ef7eb2e8f9f7 4230 /* Return the capture 2 value */
<> 144:ef7eb2e8f9f7 4231 tmpreg = htim->Instance->CCR2;
<> 144:ef7eb2e8f9f7 4232
<> 144:ef7eb2e8f9f7 4233 break;
<> 144:ef7eb2e8f9f7 4234 }
<> 144:ef7eb2e8f9f7 4235
<> 144:ef7eb2e8f9f7 4236 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 4237 {
<> 144:ef7eb2e8f9f7 4238 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4239 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4240
<> 144:ef7eb2e8f9f7 4241 /* Return the capture 3 value */
<> 144:ef7eb2e8f9f7 4242 tmpreg = htim->Instance->CCR3;
<> 144:ef7eb2e8f9f7 4243
<> 144:ef7eb2e8f9f7 4244 break;
<> 144:ef7eb2e8f9f7 4245 }
<> 144:ef7eb2e8f9f7 4246
<> 144:ef7eb2e8f9f7 4247 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 4248 {
<> 144:ef7eb2e8f9f7 4249 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4250 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4251
<> 144:ef7eb2e8f9f7 4252 /* Return the capture 4 value */
<> 144:ef7eb2e8f9f7 4253 tmpreg = htim->Instance->CCR4;
<> 144:ef7eb2e8f9f7 4254
<> 144:ef7eb2e8f9f7 4255 break;
<> 144:ef7eb2e8f9f7 4256 }
<> 144:ef7eb2e8f9f7 4257
<> 144:ef7eb2e8f9f7 4258 default:
<> 144:ef7eb2e8f9f7 4259 break;
<> 144:ef7eb2e8f9f7 4260 }
<> 144:ef7eb2e8f9f7 4261
<> 144:ef7eb2e8f9f7 4262 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 4263 return tmpreg;
<> 144:ef7eb2e8f9f7 4264 }
<> 144:ef7eb2e8f9f7 4265 /**
<> 144:ef7eb2e8f9f7 4266 * @}
<> 144:ef7eb2e8f9f7 4267 */
<> 144:ef7eb2e8f9f7 4268
<> 144:ef7eb2e8f9f7 4269 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
<> 144:ef7eb2e8f9f7 4270 * @brief TIM Callbacks functions
<> 144:ef7eb2e8f9f7 4271 *
<> 144:ef7eb2e8f9f7 4272 @verbatim
<> 144:ef7eb2e8f9f7 4273 ==============================================================================
<> 144:ef7eb2e8f9f7 4274 ##### TIM Callbacks functions #####
<> 144:ef7eb2e8f9f7 4275 ==============================================================================
<> 144:ef7eb2e8f9f7 4276 [..]
<> 144:ef7eb2e8f9f7 4277 This section provides TIM callback functions:
<> 144:ef7eb2e8f9f7 4278 (+) Timer Period elapsed callback
<> 144:ef7eb2e8f9f7 4279 (+) Timer Output Compare callback
<> 144:ef7eb2e8f9f7 4280 (+) Timer Input capture callback
<> 144:ef7eb2e8f9f7 4281 (+) Timer Trigger callback
<> 144:ef7eb2e8f9f7 4282 (+) Timer Error callback
<> 144:ef7eb2e8f9f7 4283
<> 144:ef7eb2e8f9f7 4284 @endverbatim
<> 144:ef7eb2e8f9f7 4285 * @{
<> 144:ef7eb2e8f9f7 4286 */
<> 144:ef7eb2e8f9f7 4287
<> 144:ef7eb2e8f9f7 4288 /**
<> 144:ef7eb2e8f9f7 4289 * @brief Period elapsed callback in non blocking mode
<> 144:ef7eb2e8f9f7 4290 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4291 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 4292 * @retval None
<> 144:ef7eb2e8f9f7 4293 */
<> 144:ef7eb2e8f9f7 4294 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4295 {
<> 144:ef7eb2e8f9f7 4296 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4297 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4298 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4299 the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4300 */
<> 144:ef7eb2e8f9f7 4301 }
<> 144:ef7eb2e8f9f7 4302
<> 144:ef7eb2e8f9f7 4303 /**
<> 144:ef7eb2e8f9f7 4304 * @brief Output Compare callback in non blocking mode
<> 144:ef7eb2e8f9f7 4305 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4306 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 4307 * @retval None
<> 144:ef7eb2e8f9f7 4308 */
<> 144:ef7eb2e8f9f7 4309 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4310 {
<> 144:ef7eb2e8f9f7 4311 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4312 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4313 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4314 the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4315 */
<> 144:ef7eb2e8f9f7 4316 }
<> 144:ef7eb2e8f9f7 4317
<> 144:ef7eb2e8f9f7 4318 /**
<> 144:ef7eb2e8f9f7 4319 * @brief Input Capture callback in non blocking mode
<> 144:ef7eb2e8f9f7 4320 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4321 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 4322 * @retval None
<> 144:ef7eb2e8f9f7 4323 */
<> 144:ef7eb2e8f9f7 4324 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4325 {
<> 144:ef7eb2e8f9f7 4326 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4327 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4328 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4329 the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4330 */
<> 144:ef7eb2e8f9f7 4331 }
<> 144:ef7eb2e8f9f7 4332
<> 144:ef7eb2e8f9f7 4333 /**
<> 144:ef7eb2e8f9f7 4334 * @brief PWM Pulse finished callback in non blocking mode
<> 144:ef7eb2e8f9f7 4335 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4336 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 4337 * @retval None
<> 144:ef7eb2e8f9f7 4338 */
<> 144:ef7eb2e8f9f7 4339 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4340 {
<> 144:ef7eb2e8f9f7 4341 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4342 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4343 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4344 the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4345 */
<> 144:ef7eb2e8f9f7 4346 }
<> 144:ef7eb2e8f9f7 4347
<> 144:ef7eb2e8f9f7 4348 /**
<> 144:ef7eb2e8f9f7 4349 * @brief Hall Trigger detection callback in non blocking mode
<> 144:ef7eb2e8f9f7 4350 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4351 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 4352 * @retval None
<> 144:ef7eb2e8f9f7 4353 */
<> 144:ef7eb2e8f9f7 4354 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4355 {
<> 144:ef7eb2e8f9f7 4356 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4357 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4358 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4359 the HAL_TIM_TriggerCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4360 */
<> 144:ef7eb2e8f9f7 4361 }
<> 144:ef7eb2e8f9f7 4362
<> 144:ef7eb2e8f9f7 4363 /**
<> 144:ef7eb2e8f9f7 4364 * @brief Timer error callback in non blocking mode
<> 144:ef7eb2e8f9f7 4365 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4366 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 4367 * @retval None
<> 144:ef7eb2e8f9f7 4368 */
<> 144:ef7eb2e8f9f7 4369 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4370 {
<> 144:ef7eb2e8f9f7 4371 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4372 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4373 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4374 the HAL_TIM_ErrorCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4375 */
<> 144:ef7eb2e8f9f7 4376 }
<> 144:ef7eb2e8f9f7 4377 /**
<> 144:ef7eb2e8f9f7 4378 * @}
<> 144:ef7eb2e8f9f7 4379 */
<> 144:ef7eb2e8f9f7 4380
<> 144:ef7eb2e8f9f7 4381 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
<> 144:ef7eb2e8f9f7 4382 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 4383 *
<> 144:ef7eb2e8f9f7 4384 @verbatim
<> 144:ef7eb2e8f9f7 4385 ==============================================================================
<> 144:ef7eb2e8f9f7 4386 ##### Peripheral State functions #####
<> 144:ef7eb2e8f9f7 4387 ==============================================================================
<> 144:ef7eb2e8f9f7 4388 [..]
<> 144:ef7eb2e8f9f7 4389 This subsection permits to get in run-time the status of the peripheral
<> 144:ef7eb2e8f9f7 4390 and the data flow.
<> 144:ef7eb2e8f9f7 4391
<> 144:ef7eb2e8f9f7 4392 @endverbatim
<> 144:ef7eb2e8f9f7 4393 * @{
<> 144:ef7eb2e8f9f7 4394 */
<> 144:ef7eb2e8f9f7 4395
<> 144:ef7eb2e8f9f7 4396 /**
<> 144:ef7eb2e8f9f7 4397 * @brief Return the TIM Base state
<> 144:ef7eb2e8f9f7 4398 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4399 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 4400 * @retval HAL state
<> 144:ef7eb2e8f9f7 4401 */
<> 144:ef7eb2e8f9f7 4402 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4403 {
<> 144:ef7eb2e8f9f7 4404 return htim->State;
<> 144:ef7eb2e8f9f7 4405 }
<> 144:ef7eb2e8f9f7 4406
<> 144:ef7eb2e8f9f7 4407 /**
<> 144:ef7eb2e8f9f7 4408 * @brief Return the TIM OC state
<> 144:ef7eb2e8f9f7 4409 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4410 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 4411 * @retval HAL state
<> 144:ef7eb2e8f9f7 4412 */
<> 144:ef7eb2e8f9f7 4413 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4414 {
<> 144:ef7eb2e8f9f7 4415 return htim->State;
<> 144:ef7eb2e8f9f7 4416 }
<> 144:ef7eb2e8f9f7 4417
<> 144:ef7eb2e8f9f7 4418 /**
<> 144:ef7eb2e8f9f7 4419 * @brief Return the TIM PWM state
<> 144:ef7eb2e8f9f7 4420 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4421 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 4422 * @retval HAL state
<> 144:ef7eb2e8f9f7 4423 */
<> 144:ef7eb2e8f9f7 4424 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4425 {
<> 144:ef7eb2e8f9f7 4426 return htim->State;
<> 144:ef7eb2e8f9f7 4427 }
<> 144:ef7eb2e8f9f7 4428
<> 144:ef7eb2e8f9f7 4429 /**
<> 144:ef7eb2e8f9f7 4430 * @brief Return the TIM Input Capture state
<> 144:ef7eb2e8f9f7 4431 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4432 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 4433 * @retval HAL state
<> 144:ef7eb2e8f9f7 4434 */
<> 144:ef7eb2e8f9f7 4435 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4436 {
<> 144:ef7eb2e8f9f7 4437 return htim->State;
<> 144:ef7eb2e8f9f7 4438 }
<> 144:ef7eb2e8f9f7 4439
<> 144:ef7eb2e8f9f7 4440 /**
<> 144:ef7eb2e8f9f7 4441 * @brief Return the TIM One Pulse Mode state
<> 144:ef7eb2e8f9f7 4442 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4443 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 4444 * @retval HAL state
<> 144:ef7eb2e8f9f7 4445 */
<> 144:ef7eb2e8f9f7 4446 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4447 {
<> 144:ef7eb2e8f9f7 4448 return htim->State;
<> 144:ef7eb2e8f9f7 4449 }
<> 144:ef7eb2e8f9f7 4450
<> 144:ef7eb2e8f9f7 4451 /**
<> 144:ef7eb2e8f9f7 4452 * @brief Return the TIM Encoder Mode state
<> 144:ef7eb2e8f9f7 4453 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4454 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 4455 * @retval HAL state
<> 144:ef7eb2e8f9f7 4456 */
<> 144:ef7eb2e8f9f7 4457 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4458 {
<> 144:ef7eb2e8f9f7 4459 return htim->State;
<> 144:ef7eb2e8f9f7 4460 }
<> 144:ef7eb2e8f9f7 4461 /**
<> 144:ef7eb2e8f9f7 4462 * @}
<> 144:ef7eb2e8f9f7 4463 */
<> 144:ef7eb2e8f9f7 4464
<> 144:ef7eb2e8f9f7 4465 /**
<> 144:ef7eb2e8f9f7 4466 * @brief Time Base configuration
<> 144:ef7eb2e8f9f7 4467 * @param TIMx: TIM peripheral
<> 144:ef7eb2e8f9f7 4468 * @param Structure: pointer on TIM Time Base required parameters
<> 144:ef7eb2e8f9f7 4469 * @retval None
<> 144:ef7eb2e8f9f7 4470 */
<> 144:ef7eb2e8f9f7 4471 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
<> 144:ef7eb2e8f9f7 4472 {
<> 144:ef7eb2e8f9f7 4473 uint32_t tmpcr1 = 0U;
<> 144:ef7eb2e8f9f7 4474 tmpcr1 = TIMx->CR1;
<> 144:ef7eb2e8f9f7 4475
<> 144:ef7eb2e8f9f7 4476 /* Set TIM Time Base Unit parameters ---------------------------------------*/
<> 144:ef7eb2e8f9f7 4477 if(IS_TIM_CC3_INSTANCE(TIMx) != RESET)
<> 144:ef7eb2e8f9f7 4478 {
<> 144:ef7eb2e8f9f7 4479 /* Select the Counter Mode */
<> 144:ef7eb2e8f9f7 4480 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
<> 144:ef7eb2e8f9f7 4481 tmpcr1 |= Structure->CounterMode;
<> 144:ef7eb2e8f9f7 4482 }
<> 144:ef7eb2e8f9f7 4483
<> 144:ef7eb2e8f9f7 4484 if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
<> 144:ef7eb2e8f9f7 4485 {
<> 144:ef7eb2e8f9f7 4486 /* Set the clock division */
<> 144:ef7eb2e8f9f7 4487 tmpcr1 &= ~TIM_CR1_CKD;
<> 144:ef7eb2e8f9f7 4488 tmpcr1 |= (uint32_t)Structure->ClockDivision;
<> 144:ef7eb2e8f9f7 4489 }
<> 144:ef7eb2e8f9f7 4490
<> 144:ef7eb2e8f9f7 4491 TIMx->CR1 = tmpcr1;
<> 144:ef7eb2e8f9f7 4492
<> 144:ef7eb2e8f9f7 4493 /* Set the Auto-reload value */
<> 144:ef7eb2e8f9f7 4494 TIMx->ARR = (uint32_t)Structure->Period ;
<> 144:ef7eb2e8f9f7 4495
<> 144:ef7eb2e8f9f7 4496 /* Set the Prescaler value */
<> 144:ef7eb2e8f9f7 4497 TIMx->PSC = (uint32_t)Structure->Prescaler;
<> 144:ef7eb2e8f9f7 4498
<> 144:ef7eb2e8f9f7 4499 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
<> 144:ef7eb2e8f9f7 4500 {
<> 144:ef7eb2e8f9f7 4501 /* Set the Repetition Counter value */
<> 144:ef7eb2e8f9f7 4502 TIMx->RCR = Structure->RepetitionCounter;
<> 144:ef7eb2e8f9f7 4503 }
<> 144:ef7eb2e8f9f7 4504
<> 144:ef7eb2e8f9f7 4505 /* Generate an update event to reload the Prescaler
<> 144:ef7eb2e8f9f7 4506 and the repetition counter(only for TIM1 and TIM8) value immediately */
<> 144:ef7eb2e8f9f7 4507 TIMx->EGR = TIM_EGR_UG;
<> 144:ef7eb2e8f9f7 4508 }
<> 144:ef7eb2e8f9f7 4509
<> 144:ef7eb2e8f9f7 4510 /**
<> 144:ef7eb2e8f9f7 4511 * @brief Configure the TI1 as Input.
<> 144:ef7eb2e8f9f7 4512 * @param TIMx to select the TIM peripheral.
<> 144:ef7eb2e8f9f7 4513 * @param TIM_ICPolarity : The Input Polarity.
<> 144:ef7eb2e8f9f7 4514 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 4515 * @arg TIM_ICPolarity_Rising
<> 144:ef7eb2e8f9f7 4516 * @arg TIM_ICPolarity_Falling
<> 144:ef7eb2e8f9f7 4517 * @arg TIM_ICPolarity_BothEdge
<> 144:ef7eb2e8f9f7 4518 * @param TIM_ICSelection: specifies the input to be used.
<> 144:ef7eb2e8f9f7 4519 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 4520 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
<> 144:ef7eb2e8f9f7 4521 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
<> 144:ef7eb2e8f9f7 4522 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
<> 144:ef7eb2e8f9f7 4523 * @param TIM_ICFilter: Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 4524 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 4525 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
<> 144:ef7eb2e8f9f7 4526 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
<> 144:ef7eb2e8f9f7 4527 * protected against un-initialized filter and polarity values.
<> 144:ef7eb2e8f9f7 4528 * @retval None
<> 144:ef7eb2e8f9f7 4529 */
<> 144:ef7eb2e8f9f7 4530 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 4531 uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 4532 {
<> 144:ef7eb2e8f9f7 4533 uint32_t tmpccmr1 = 0U;
<> 144:ef7eb2e8f9f7 4534 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 4535
<> 144:ef7eb2e8f9f7 4536 /* Disable the Channel 1: Reset the CC1E Bit */
<> 144:ef7eb2e8f9f7 4537 TIMx->CCER &= ~TIM_CCER_CC1E;
<> 144:ef7eb2e8f9f7 4538 tmpccmr1 = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 4539 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 4540
<> 144:ef7eb2e8f9f7 4541 /* Select the Input */
<> 144:ef7eb2e8f9f7 4542 if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
<> 144:ef7eb2e8f9f7 4543 {
<> 144:ef7eb2e8f9f7 4544 tmpccmr1 &= ~TIM_CCMR1_CC1S;
<> 144:ef7eb2e8f9f7 4545 tmpccmr1 |= TIM_ICSelection;
<> 144:ef7eb2e8f9f7 4546 }
<> 144:ef7eb2e8f9f7 4547 else
<> 144:ef7eb2e8f9f7 4548 {
<> 144:ef7eb2e8f9f7 4549 tmpccmr1 &= ~TIM_CCMR1_CC1S;
<> 144:ef7eb2e8f9f7 4550 tmpccmr1 |= TIM_CCMR1_CC1S_0;
<> 144:ef7eb2e8f9f7 4551 }
<> 144:ef7eb2e8f9f7 4552
<> 144:ef7eb2e8f9f7 4553 /* Set the filter */
<> 144:ef7eb2e8f9f7 4554 tmpccmr1 &= ~TIM_CCMR1_IC1F;
<> 144:ef7eb2e8f9f7 4555 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
<> 144:ef7eb2e8f9f7 4556
<> 144:ef7eb2e8f9f7 4557 /* Select the Polarity and set the CC1E Bit */
<> 144:ef7eb2e8f9f7 4558 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
<> 144:ef7eb2e8f9f7 4559 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
<> 144:ef7eb2e8f9f7 4560
<> 144:ef7eb2e8f9f7 4561 /* Write to TIMx CCMR1 and CCER registers */
<> 144:ef7eb2e8f9f7 4562 TIMx->CCMR1 = tmpccmr1;
<> 144:ef7eb2e8f9f7 4563 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 4564 }
<> 144:ef7eb2e8f9f7 4565
<> 144:ef7eb2e8f9f7 4566 /**
<> 144:ef7eb2e8f9f7 4567 * @brief Time Output Compare 2 configuration
<> 144:ef7eb2e8f9f7 4568 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 4569 * @param OC_Config: The output configuration structure
<> 144:ef7eb2e8f9f7 4570 * @retval None
<> 144:ef7eb2e8f9f7 4571 */
<> 144:ef7eb2e8f9f7 4572 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
<> 144:ef7eb2e8f9f7 4573 {
<> 144:ef7eb2e8f9f7 4574 uint32_t tmpccmrx = 0U;
<> 144:ef7eb2e8f9f7 4575 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 4576 uint32_t tmpcr2 = 0U;
<> 144:ef7eb2e8f9f7 4577
<> 144:ef7eb2e8f9f7 4578 /* Disable the Channel 2: Reset the CC2E Bit */
<> 144:ef7eb2e8f9f7 4579 TIMx->CCER &= ~TIM_CCER_CC2E;
<> 144:ef7eb2e8f9f7 4580
<> 144:ef7eb2e8f9f7 4581 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 4582 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 4583 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 4584 tmpcr2 = TIMx->CR2;
<> 144:ef7eb2e8f9f7 4585
<> 144:ef7eb2e8f9f7 4586 /* Get the TIMx CCMR1 register value */
<> 144:ef7eb2e8f9f7 4587 tmpccmrx = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 4588
<> 144:ef7eb2e8f9f7 4589 /* Reset the Output Compare mode and Capture/Compare selection Bits */
<> 144:ef7eb2e8f9f7 4590 tmpccmrx &= ~TIM_CCMR1_OC2M;
<> 144:ef7eb2e8f9f7 4591 tmpccmrx &= ~TIM_CCMR1_CC2S;
<> 144:ef7eb2e8f9f7 4592
<> 144:ef7eb2e8f9f7 4593 /* Select the Output Compare Mode */
<> 144:ef7eb2e8f9f7 4594 tmpccmrx |= (OC_Config->OCMode << 8U);
<> 144:ef7eb2e8f9f7 4595
<> 144:ef7eb2e8f9f7 4596 /* Reset the Output Polarity level */
<> 144:ef7eb2e8f9f7 4597 tmpccer &= ~TIM_CCER_CC2P;
<> 144:ef7eb2e8f9f7 4598 /* Set the Output Compare Polarity */
<> 144:ef7eb2e8f9f7 4599 tmpccer |= (OC_Config->OCPolarity << 4U);
<> 144:ef7eb2e8f9f7 4600
<> 144:ef7eb2e8f9f7 4601 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
<> 144:ef7eb2e8f9f7 4602 {
<> 144:ef7eb2e8f9f7 4603 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
<> 144:ef7eb2e8f9f7 4604
<> 144:ef7eb2e8f9f7 4605 /* Reset the Output N Polarity level */
<> 144:ef7eb2e8f9f7 4606 tmpccer &= ~TIM_CCER_CC2NP;
<> 144:ef7eb2e8f9f7 4607 /* Set the Output N Polarity */
<> 144:ef7eb2e8f9f7 4608 tmpccer |= (OC_Config->OCNPolarity << 4U);
<> 144:ef7eb2e8f9f7 4609 /* Reset the Output N State */
<> 144:ef7eb2e8f9f7 4610 tmpccer &= ~TIM_CCER_CC2NE;
<> 144:ef7eb2e8f9f7 4611
<> 144:ef7eb2e8f9f7 4612 /* Reset the Output Compare and Output Compare N IDLE State */
<> 144:ef7eb2e8f9f7 4613 tmpcr2 &= ~TIM_CR2_OIS2;
<> 144:ef7eb2e8f9f7 4614 tmpcr2 &= ~TIM_CR2_OIS2N;
<> 144:ef7eb2e8f9f7 4615 /* Set the Output Idle state */
<> 144:ef7eb2e8f9f7 4616 tmpcr2 |= (OC_Config->OCIdleState << 2U);
<> 144:ef7eb2e8f9f7 4617 /* Set the Output N Idle state */
<> 144:ef7eb2e8f9f7 4618 tmpcr2 |= (OC_Config->OCNIdleState << 2U);
<> 144:ef7eb2e8f9f7 4619 }
<> 144:ef7eb2e8f9f7 4620 /* Write to TIMx CR2 */
<> 144:ef7eb2e8f9f7 4621 TIMx->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 4622
<> 144:ef7eb2e8f9f7 4623 /* Write to TIMx CCMR1 */
<> 144:ef7eb2e8f9f7 4624 TIMx->CCMR1 = tmpccmrx;
<> 144:ef7eb2e8f9f7 4625
<> 144:ef7eb2e8f9f7 4626 /* Set the Capture Compare Register value */
<> 144:ef7eb2e8f9f7 4627 TIMx->CCR2 = OC_Config->Pulse;
<> 144:ef7eb2e8f9f7 4628
<> 144:ef7eb2e8f9f7 4629 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 4630 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 4631 }
<> 144:ef7eb2e8f9f7 4632
<> 144:ef7eb2e8f9f7 4633 /**
<> 144:ef7eb2e8f9f7 4634 * @brief TIM DMA Delay Pulse complete callback.
<> 144:ef7eb2e8f9f7 4635 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4636 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 4637 * @retval None
<> 144:ef7eb2e8f9f7 4638 */
<> 144:ef7eb2e8f9f7 4639 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4640 {
<> 144:ef7eb2e8f9f7 4641 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 4642
<> 144:ef7eb2e8f9f7 4643 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4644
<> 144:ef7eb2e8f9f7 4645 if(hdma == htim->hdma[TIM_DMA_ID_CC1])
<> 144:ef7eb2e8f9f7 4646 {
<> 144:ef7eb2e8f9f7 4647 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<> 144:ef7eb2e8f9f7 4648 }
<> 144:ef7eb2e8f9f7 4649 else if(hdma == htim->hdma[TIM_DMA_ID_CC2])
<> 144:ef7eb2e8f9f7 4650 {
<> 144:ef7eb2e8f9f7 4651 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<> 144:ef7eb2e8f9f7 4652 }
<> 144:ef7eb2e8f9f7 4653 else if(hdma == htim->hdma[TIM_DMA_ID_CC3])
<> 144:ef7eb2e8f9f7 4654 {
<> 144:ef7eb2e8f9f7 4655 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<> 144:ef7eb2e8f9f7 4656 }
<> 144:ef7eb2e8f9f7 4657 else if(hdma == htim->hdma[TIM_DMA_ID_CC4])
<> 144:ef7eb2e8f9f7 4658 {
<> 144:ef7eb2e8f9f7 4659 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<> 144:ef7eb2e8f9f7 4660 }
<> 144:ef7eb2e8f9f7 4661
<> 144:ef7eb2e8f9f7 4662 HAL_TIM_PWM_PulseFinishedCallback(htim);
<> 144:ef7eb2e8f9f7 4663
<> 144:ef7eb2e8f9f7 4664 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 4665 }
<> 144:ef7eb2e8f9f7 4666
<> 144:ef7eb2e8f9f7 4667 /**
<> 144:ef7eb2e8f9f7 4668 * @brief TIM DMA error callback
<> 144:ef7eb2e8f9f7 4669 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4670 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 4671 * @retval None
<> 144:ef7eb2e8f9f7 4672 */
<> 144:ef7eb2e8f9f7 4673 void TIM_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4674 {
<> 144:ef7eb2e8f9f7 4675 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 4676
<> 144:ef7eb2e8f9f7 4677 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4678
<> 144:ef7eb2e8f9f7 4679 HAL_TIM_ErrorCallback(htim);
<> 144:ef7eb2e8f9f7 4680 }
<> 144:ef7eb2e8f9f7 4681
<> 144:ef7eb2e8f9f7 4682 /**
<> 144:ef7eb2e8f9f7 4683 * @brief TIM DMA Capture complete callback.
<> 144:ef7eb2e8f9f7 4684 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4685 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 4686 * @retval None
<> 144:ef7eb2e8f9f7 4687 */
<> 144:ef7eb2e8f9f7 4688 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4689 {
<> 144:ef7eb2e8f9f7 4690 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 4691
<> 144:ef7eb2e8f9f7 4692 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4693
<> 144:ef7eb2e8f9f7 4694 if(hdma == htim->hdma[TIM_DMA_ID_CC1])
<> 144:ef7eb2e8f9f7 4695 {
<> 144:ef7eb2e8f9f7 4696 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<> 144:ef7eb2e8f9f7 4697 }
<> 144:ef7eb2e8f9f7 4698 else if(hdma == htim->hdma[TIM_DMA_ID_CC2])
<> 144:ef7eb2e8f9f7 4699 {
<> 144:ef7eb2e8f9f7 4700 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<> 144:ef7eb2e8f9f7 4701 }
<> 144:ef7eb2e8f9f7 4702 else if(hdma == htim->hdma[TIM_DMA_ID_CC3])
<> 144:ef7eb2e8f9f7 4703 {
<> 144:ef7eb2e8f9f7 4704 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<> 144:ef7eb2e8f9f7 4705 }
<> 144:ef7eb2e8f9f7 4706 else if(hdma == htim->hdma[TIM_DMA_ID_CC4])
<> 144:ef7eb2e8f9f7 4707 {
<> 144:ef7eb2e8f9f7 4708 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<> 144:ef7eb2e8f9f7 4709 }
<> 144:ef7eb2e8f9f7 4710
<> 144:ef7eb2e8f9f7 4711 HAL_TIM_IC_CaptureCallback(htim);
<> 144:ef7eb2e8f9f7 4712
<> 144:ef7eb2e8f9f7 4713 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 4714 }
<> 144:ef7eb2e8f9f7 4715
<> 144:ef7eb2e8f9f7 4716 /**
<> 144:ef7eb2e8f9f7 4717 * @brief Enables or disables the TIM Capture Compare Channel x.
<> 144:ef7eb2e8f9f7 4718 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 4719 * @param Channel: specifies the TIM Channel
<> 144:ef7eb2e8f9f7 4720 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 4721 * @arg TIM_Channel_1: TIM Channel 1
<> 144:ef7eb2e8f9f7 4722 * @arg TIM_Channel_2: TIM Channel 2
<> 144:ef7eb2e8f9f7 4723 * @arg TIM_Channel_3: TIM Channel 3
<> 144:ef7eb2e8f9f7 4724 * @arg TIM_Channel_4: TIM Channel 4
<> 144:ef7eb2e8f9f7 4725 * @param ChannelState: specifies the TIM Channel CCxE bit new state.
<> 144:ef7eb2e8f9f7 4726 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
<> 144:ef7eb2e8f9f7 4727 * @retval None
<> 144:ef7eb2e8f9f7 4728 */
<> 144:ef7eb2e8f9f7 4729 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
<> 144:ef7eb2e8f9f7 4730 {
<> 144:ef7eb2e8f9f7 4731 uint32_t tmp = 0;
<> 144:ef7eb2e8f9f7 4732
<> 144:ef7eb2e8f9f7 4733 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4734 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
<> 144:ef7eb2e8f9f7 4735 assert_param(IS_TIM_CHANNELS(Channel));
<> 144:ef7eb2e8f9f7 4736
<> 144:ef7eb2e8f9f7 4737 tmp = TIM_CCER_CC1E << Channel;
<> 144:ef7eb2e8f9f7 4738
<> 144:ef7eb2e8f9f7 4739 /* Reset the CCxE Bit */
<> 144:ef7eb2e8f9f7 4740 TIMx->CCER &= ~tmp;
<> 144:ef7eb2e8f9f7 4741
<> 144:ef7eb2e8f9f7 4742 /* Set or reset the CCxE Bit */
<> 144:ef7eb2e8f9f7 4743 TIMx->CCER |= (uint32_t)(ChannelState << Channel);
<> 144:ef7eb2e8f9f7 4744 }
<> 144:ef7eb2e8f9f7 4745
<> 144:ef7eb2e8f9f7 4746 /**
<> 144:ef7eb2e8f9f7 4747 * @brief TIM DMA Period Elapse complete callback.
<> 144:ef7eb2e8f9f7 4748 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4749 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 4750 * @retval None
<> 144:ef7eb2e8f9f7 4751 */
<> 144:ef7eb2e8f9f7 4752 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4753 {
<> 144:ef7eb2e8f9f7 4754 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 4755
<> 144:ef7eb2e8f9f7 4756 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4757
<> 144:ef7eb2e8f9f7 4758 HAL_TIM_PeriodElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 4759 }
<> 144:ef7eb2e8f9f7 4760
<> 144:ef7eb2e8f9f7 4761 /**
<> 144:ef7eb2e8f9f7 4762 * @brief TIM DMA Trigger callback.
<> 144:ef7eb2e8f9f7 4763 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4764 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 4765 * @retval None
<> 144:ef7eb2e8f9f7 4766 */
<> 144:ef7eb2e8f9f7 4767 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4768 {
<> 144:ef7eb2e8f9f7 4769 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 4770
<> 144:ef7eb2e8f9f7 4771 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4772
<> 144:ef7eb2e8f9f7 4773 HAL_TIM_TriggerCallback(htim);
<> 144:ef7eb2e8f9f7 4774 }
<> 144:ef7eb2e8f9f7 4775
<> 144:ef7eb2e8f9f7 4776 /**
<> 144:ef7eb2e8f9f7 4777 * @brief Time Output Compare 1 configuration
<> 144:ef7eb2e8f9f7 4778 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 4779 * @param OC_Config: The output configuration structure
<> 144:ef7eb2e8f9f7 4780 * @retval None
<> 144:ef7eb2e8f9f7 4781 */
<> 144:ef7eb2e8f9f7 4782 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
<> 144:ef7eb2e8f9f7 4783 {
<> 144:ef7eb2e8f9f7 4784 uint32_t tmpccmrx = 0U;
<> 144:ef7eb2e8f9f7 4785 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 4786 uint32_t tmpcr2 = 0U;
<> 144:ef7eb2e8f9f7 4787
<> 144:ef7eb2e8f9f7 4788 /* Disable the Channel 1: Reset the CC1E Bit */
<> 144:ef7eb2e8f9f7 4789 TIMx->CCER &= ~TIM_CCER_CC1E;
<> 144:ef7eb2e8f9f7 4790
<> 144:ef7eb2e8f9f7 4791 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 4792 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 4793 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 4794 tmpcr2 = TIMx->CR2;
<> 144:ef7eb2e8f9f7 4795
<> 144:ef7eb2e8f9f7 4796 /* Get the TIMx CCMR1 register value */
<> 144:ef7eb2e8f9f7 4797 tmpccmrx = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 4798
<> 144:ef7eb2e8f9f7 4799 /* Reset the Output Compare Mode Bits */
<> 144:ef7eb2e8f9f7 4800 tmpccmrx &= ~TIM_CCMR1_OC1M;
<> 144:ef7eb2e8f9f7 4801 tmpccmrx &= ~TIM_CCMR1_CC1S;
<> 144:ef7eb2e8f9f7 4802 /* Select the Output Compare Mode */
<> 144:ef7eb2e8f9f7 4803 tmpccmrx |= OC_Config->OCMode;
<> 144:ef7eb2e8f9f7 4804
<> 144:ef7eb2e8f9f7 4805 /* Reset the Output Polarity level */
<> 144:ef7eb2e8f9f7 4806 tmpccer &= ~TIM_CCER_CC1P;
<> 144:ef7eb2e8f9f7 4807 /* Set the Output Compare Polarity */
<> 144:ef7eb2e8f9f7 4808 tmpccer |= OC_Config->OCPolarity;
<> 144:ef7eb2e8f9f7 4809
<> 144:ef7eb2e8f9f7 4810
<> 144:ef7eb2e8f9f7 4811 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
<> 144:ef7eb2e8f9f7 4812 {
<> 144:ef7eb2e8f9f7 4813 /* Reset the Output N Polarity level */
<> 144:ef7eb2e8f9f7 4814 tmpccer &= ~TIM_CCER_CC1NP;
<> 144:ef7eb2e8f9f7 4815 /* Set the Output N Polarity */
<> 144:ef7eb2e8f9f7 4816 tmpccer |= OC_Config->OCNPolarity;
<> 144:ef7eb2e8f9f7 4817 /* Reset the Output N State */
<> 144:ef7eb2e8f9f7 4818 tmpccer &= ~TIM_CCER_CC1NE;
<> 144:ef7eb2e8f9f7 4819
<> 144:ef7eb2e8f9f7 4820 /* Reset the Output Compare and Output Compare N IDLE State */
<> 144:ef7eb2e8f9f7 4821 tmpcr2 &= ~TIM_CR2_OIS1;
<> 144:ef7eb2e8f9f7 4822 tmpcr2 &= ~TIM_CR2_OIS1N;
<> 144:ef7eb2e8f9f7 4823 /* Set the Output Idle state */
<> 144:ef7eb2e8f9f7 4824 tmpcr2 |= OC_Config->OCIdleState;
<> 144:ef7eb2e8f9f7 4825 /* Set the Output N Idle state */
<> 144:ef7eb2e8f9f7 4826 tmpcr2 |= OC_Config->OCNIdleState;
<> 144:ef7eb2e8f9f7 4827 }
<> 144:ef7eb2e8f9f7 4828 /* Write to TIMx CR2 */
<> 144:ef7eb2e8f9f7 4829 TIMx->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 4830
<> 144:ef7eb2e8f9f7 4831 /* Write to TIMx CCMR1 */
<> 144:ef7eb2e8f9f7 4832 TIMx->CCMR1 = tmpccmrx;
<> 144:ef7eb2e8f9f7 4833
<> 144:ef7eb2e8f9f7 4834 /* Set the Capture Compare Register value */
<> 144:ef7eb2e8f9f7 4835 TIMx->CCR1 = OC_Config->Pulse;
<> 144:ef7eb2e8f9f7 4836
<> 144:ef7eb2e8f9f7 4837 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 4838 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 4839 }
<> 144:ef7eb2e8f9f7 4840
<> 144:ef7eb2e8f9f7 4841 /**
<> 144:ef7eb2e8f9f7 4842 * @brief Time Output Compare 3 configuration
<> 144:ef7eb2e8f9f7 4843 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 4844 * @param OC_Config: The output configuration structure
<> 144:ef7eb2e8f9f7 4845 * @retval None
<> 144:ef7eb2e8f9f7 4846 */
<> 144:ef7eb2e8f9f7 4847 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
<> 144:ef7eb2e8f9f7 4848 {
<> 144:ef7eb2e8f9f7 4849 uint32_t tmpccmrx = 0U;
<> 144:ef7eb2e8f9f7 4850 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 4851 uint32_t tmpcr2 = 0U;
<> 144:ef7eb2e8f9f7 4852
<> 144:ef7eb2e8f9f7 4853 /* Disable the Channel 3: Reset the CC2E Bit */
<> 144:ef7eb2e8f9f7 4854 TIMx->CCER &= ~TIM_CCER_CC3E;
<> 144:ef7eb2e8f9f7 4855
<> 144:ef7eb2e8f9f7 4856 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 4857 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 4858 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 4859 tmpcr2 = TIMx->CR2;
<> 144:ef7eb2e8f9f7 4860
<> 144:ef7eb2e8f9f7 4861 /* Get the TIMx CCMR2 register value */
<> 144:ef7eb2e8f9f7 4862 tmpccmrx = TIMx->CCMR2;
<> 144:ef7eb2e8f9f7 4863
<> 144:ef7eb2e8f9f7 4864 /* Reset the Output Compare mode and Capture/Compare selection Bits */
<> 144:ef7eb2e8f9f7 4865 tmpccmrx &= ~TIM_CCMR2_OC3M;
<> 144:ef7eb2e8f9f7 4866 tmpccmrx &= ~TIM_CCMR2_CC3S;
<> 144:ef7eb2e8f9f7 4867 /* Select the Output Compare Mode */
<> 144:ef7eb2e8f9f7 4868 tmpccmrx |= OC_Config->OCMode;
<> 144:ef7eb2e8f9f7 4869
<> 144:ef7eb2e8f9f7 4870 /* Reset the Output Polarity level */
<> 144:ef7eb2e8f9f7 4871 tmpccer &= ~TIM_CCER_CC3P;
<> 144:ef7eb2e8f9f7 4872 /* Set the Output Compare Polarity */
<> 144:ef7eb2e8f9f7 4873 tmpccer |= (OC_Config->OCPolarity << 8U);
<> 144:ef7eb2e8f9f7 4874
<> 144:ef7eb2e8f9f7 4875 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
<> 144:ef7eb2e8f9f7 4876 {
<> 144:ef7eb2e8f9f7 4877 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
<> 144:ef7eb2e8f9f7 4878 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
<> 144:ef7eb2e8f9f7 4879 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
<> 144:ef7eb2e8f9f7 4880
<> 144:ef7eb2e8f9f7 4881 /* Reset the Output N Polarity level */
<> 144:ef7eb2e8f9f7 4882 tmpccer &= ~TIM_CCER_CC3NP;
<> 144:ef7eb2e8f9f7 4883 /* Set the Output N Polarity */
<> 144:ef7eb2e8f9f7 4884 tmpccer |= (OC_Config->OCNPolarity << 8U);
<> 144:ef7eb2e8f9f7 4885 /* Reset the Output N State */
<> 144:ef7eb2e8f9f7 4886 tmpccer &= ~TIM_CCER_CC3NE;
<> 144:ef7eb2e8f9f7 4887
<> 144:ef7eb2e8f9f7 4888 /* Reset the Output Compare and Output Compare N IDLE State */
<> 144:ef7eb2e8f9f7 4889 tmpcr2 &= ~TIM_CR2_OIS3;
<> 144:ef7eb2e8f9f7 4890 tmpcr2 &= ~TIM_CR2_OIS3N;
<> 144:ef7eb2e8f9f7 4891 /* Set the Output Idle state */
<> 144:ef7eb2e8f9f7 4892 tmpcr2 |= (OC_Config->OCIdleState << 4U);
<> 144:ef7eb2e8f9f7 4893 /* Set the Output N Idle state */
<> 144:ef7eb2e8f9f7 4894 tmpcr2 |= (OC_Config->OCNIdleState << 4U);
<> 144:ef7eb2e8f9f7 4895 }
<> 144:ef7eb2e8f9f7 4896 /* Write to TIMx CR2 */
<> 144:ef7eb2e8f9f7 4897 TIMx->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 4898
<> 144:ef7eb2e8f9f7 4899 /* Write to TIMx CCMR2 */
<> 144:ef7eb2e8f9f7 4900 TIMx->CCMR2 = tmpccmrx;
<> 144:ef7eb2e8f9f7 4901
<> 144:ef7eb2e8f9f7 4902 /* Set the Capture Compare Register value */
<> 144:ef7eb2e8f9f7 4903 TIMx->CCR3 = OC_Config->Pulse;
<> 144:ef7eb2e8f9f7 4904
<> 144:ef7eb2e8f9f7 4905 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 4906 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 4907 }
<> 144:ef7eb2e8f9f7 4908
<> 144:ef7eb2e8f9f7 4909 /**
<> 144:ef7eb2e8f9f7 4910 * @brief Time Output Compare 4 configuration
<> 144:ef7eb2e8f9f7 4911 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 4912 * @param OC_Config: The output configuration structure
<> 144:ef7eb2e8f9f7 4913 * @retval None
<> 144:ef7eb2e8f9f7 4914 */
<> 144:ef7eb2e8f9f7 4915 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
<> 144:ef7eb2e8f9f7 4916 {
<> 144:ef7eb2e8f9f7 4917 uint32_t tmpccmrx = 0U;
<> 144:ef7eb2e8f9f7 4918 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 4919 uint32_t tmpcr2 = 0U;
<> 144:ef7eb2e8f9f7 4920
<> 144:ef7eb2e8f9f7 4921 /* Disable the Channel 4: Reset the CC4E Bit */
<> 144:ef7eb2e8f9f7 4922 TIMx->CCER &= ~TIM_CCER_CC4E;
<> 144:ef7eb2e8f9f7 4923
<> 144:ef7eb2e8f9f7 4924 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 4925 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 4926 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 4927 tmpcr2 = TIMx->CR2;
<> 144:ef7eb2e8f9f7 4928
<> 144:ef7eb2e8f9f7 4929 /* Get the TIMx CCMR2 register value */
<> 144:ef7eb2e8f9f7 4930 tmpccmrx = TIMx->CCMR2;
<> 144:ef7eb2e8f9f7 4931
<> 144:ef7eb2e8f9f7 4932 /* Reset the Output Compare mode and Capture/Compare selection Bits */
<> 144:ef7eb2e8f9f7 4933 tmpccmrx &= ~TIM_CCMR2_OC4M;
<> 144:ef7eb2e8f9f7 4934 tmpccmrx &= ~TIM_CCMR2_CC4S;
<> 144:ef7eb2e8f9f7 4935
<> 144:ef7eb2e8f9f7 4936 /* Select the Output Compare Mode */
<> 144:ef7eb2e8f9f7 4937 tmpccmrx |= (OC_Config->OCMode << 8U);
<> 144:ef7eb2e8f9f7 4938
<> 144:ef7eb2e8f9f7 4939 /* Reset the Output Polarity level */
<> 144:ef7eb2e8f9f7 4940 tmpccer &= ~TIM_CCER_CC4P;
<> 144:ef7eb2e8f9f7 4941 /* Set the Output Compare Polarity */
<> 144:ef7eb2e8f9f7 4942 tmpccer |= (OC_Config->OCPolarity << 12U);
<> 144:ef7eb2e8f9f7 4943
<> 144:ef7eb2e8f9f7 4944 /*if((TIMx == TIM1) || (TIMx == TIM8))*/
<> 144:ef7eb2e8f9f7 4945 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
<> 144:ef7eb2e8f9f7 4946 {
<> 144:ef7eb2e8f9f7 4947 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
<> 144:ef7eb2e8f9f7 4948 /* Reset the Output Compare IDLE State */
<> 144:ef7eb2e8f9f7 4949 tmpcr2 &= ~TIM_CR2_OIS4;
<> 144:ef7eb2e8f9f7 4950 /* Set the Output Idle state */
<> 144:ef7eb2e8f9f7 4951 tmpcr2 |= (OC_Config->OCIdleState << 6U);
<> 144:ef7eb2e8f9f7 4952 }
<> 144:ef7eb2e8f9f7 4953 /* Write to TIMx CR2 */
<> 144:ef7eb2e8f9f7 4954 TIMx->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 4955
<> 144:ef7eb2e8f9f7 4956 /* Write to TIMx CCMR2 */
<> 144:ef7eb2e8f9f7 4957 TIMx->CCMR2 = tmpccmrx;
<> 144:ef7eb2e8f9f7 4958
<> 144:ef7eb2e8f9f7 4959 /* Set the Capture Compare Register value */
<> 144:ef7eb2e8f9f7 4960 TIMx->CCR4 = OC_Config->Pulse;
<> 144:ef7eb2e8f9f7 4961
<> 144:ef7eb2e8f9f7 4962 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 4963 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 4964 }
<> 144:ef7eb2e8f9f7 4965
<> 144:ef7eb2e8f9f7 4966 /**
<> 144:ef7eb2e8f9f7 4967 * @brief Time Output Compare 4 configuration
<> 144:ef7eb2e8f9f7 4968 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4969 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 4970 * @param sSlaveConfig: The slave configuration structure
<> 144:ef7eb2e8f9f7 4971 * @retval None
<> 144:ef7eb2e8f9f7 4972 */
<> 144:ef7eb2e8f9f7 4973 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 4974 TIM_SlaveConfigTypeDef * sSlaveConfig)
<> 144:ef7eb2e8f9f7 4975 {
<> 144:ef7eb2e8f9f7 4976 uint32_t tmpsmcr = 0U;
<> 144:ef7eb2e8f9f7 4977 uint32_t tmpccmr1 = 0U;
<> 144:ef7eb2e8f9f7 4978 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 4979
<> 144:ef7eb2e8f9f7 4980 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 4981 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 4982
<> 144:ef7eb2e8f9f7 4983 /* Reset the Trigger Selection Bits */
<> 144:ef7eb2e8f9f7 4984 tmpsmcr &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 4985 /* Set the Input Trigger source */
<> 144:ef7eb2e8f9f7 4986 tmpsmcr |= sSlaveConfig->InputTrigger;
<> 144:ef7eb2e8f9f7 4987
<> 144:ef7eb2e8f9f7 4988 /* Reset the slave mode Bits */
<> 144:ef7eb2e8f9f7 4989 tmpsmcr &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 4990 /* Set the slave mode */
<> 144:ef7eb2e8f9f7 4991 tmpsmcr |= sSlaveConfig->SlaveMode;
<> 144:ef7eb2e8f9f7 4992
<> 144:ef7eb2e8f9f7 4993 /* Write to TIMx SMCR */
<> 144:ef7eb2e8f9f7 4994 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 4995
<> 144:ef7eb2e8f9f7 4996 /* Configure the trigger prescaler, filter, and polarity */
<> 144:ef7eb2e8f9f7 4997 switch (sSlaveConfig->InputTrigger)
<> 144:ef7eb2e8f9f7 4998 {
<> 144:ef7eb2e8f9f7 4999 case TIM_TS_ETRF:
<> 144:ef7eb2e8f9f7 5000 {
<> 144:ef7eb2e8f9f7 5001 /* Check the parameters */
<> 144:ef7eb2e8f9f7 5002 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5003 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
<> 144:ef7eb2e8f9f7 5004 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<> 144:ef7eb2e8f9f7 5005 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<> 144:ef7eb2e8f9f7 5006 /* Configure the ETR Trigger source */
<> 144:ef7eb2e8f9f7 5007 TIM_ETR_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 5008 sSlaveConfig->TriggerPrescaler,
<> 144:ef7eb2e8f9f7 5009 sSlaveConfig->TriggerPolarity,
<> 144:ef7eb2e8f9f7 5010 sSlaveConfig->TriggerFilter);
<> 144:ef7eb2e8f9f7 5011 }
<> 144:ef7eb2e8f9f7 5012 break;
<> 144:ef7eb2e8f9f7 5013
<> 144:ef7eb2e8f9f7 5014 case TIM_TS_TI1F_ED:
<> 144:ef7eb2e8f9f7 5015 {
<> 144:ef7eb2e8f9f7 5016 /* Check the parameters */
<> 144:ef7eb2e8f9f7 5017 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5018 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<> 144:ef7eb2e8f9f7 5019
<> 144:ef7eb2e8f9f7 5020 /* Disable the Channel 1: Reset the CC1E Bit */
<> 144:ef7eb2e8f9f7 5021 tmpccer = htim->Instance->CCER;
<> 144:ef7eb2e8f9f7 5022 htim->Instance->CCER &= ~TIM_CCER_CC1E;
<> 144:ef7eb2e8f9f7 5023 tmpccmr1 = htim->Instance->CCMR1;
<> 144:ef7eb2e8f9f7 5024
<> 144:ef7eb2e8f9f7 5025 /* Set the filter */
<> 144:ef7eb2e8f9f7 5026 tmpccmr1 &= ~TIM_CCMR1_IC1F;
<> 144:ef7eb2e8f9f7 5027 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
<> 144:ef7eb2e8f9f7 5028
<> 144:ef7eb2e8f9f7 5029 /* Write to TIMx CCMR1 and CCER registers */
<> 144:ef7eb2e8f9f7 5030 htim->Instance->CCMR1 = tmpccmr1;
<> 144:ef7eb2e8f9f7 5031 htim->Instance->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 5032
<> 144:ef7eb2e8f9f7 5033 }
<> 144:ef7eb2e8f9f7 5034 break;
<> 144:ef7eb2e8f9f7 5035
<> 144:ef7eb2e8f9f7 5036 case TIM_TS_TI1FP1:
<> 144:ef7eb2e8f9f7 5037 {
<> 144:ef7eb2e8f9f7 5038 /* Check the parameters */
<> 144:ef7eb2e8f9f7 5039 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5040 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<> 144:ef7eb2e8f9f7 5041 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<> 144:ef7eb2e8f9f7 5042
<> 144:ef7eb2e8f9f7 5043 /* Configure TI1 Filter and Polarity */
<> 144:ef7eb2e8f9f7 5044 TIM_TI1_ConfigInputStage(htim->Instance,
<> 144:ef7eb2e8f9f7 5045 sSlaveConfig->TriggerPolarity,
<> 144:ef7eb2e8f9f7 5046 sSlaveConfig->TriggerFilter);
<> 144:ef7eb2e8f9f7 5047 }
<> 144:ef7eb2e8f9f7 5048 break;
<> 144:ef7eb2e8f9f7 5049
<> 144:ef7eb2e8f9f7 5050 case TIM_TS_TI2FP2:
<> 144:ef7eb2e8f9f7 5051 {
<> 144:ef7eb2e8f9f7 5052 /* Check the parameters */
<> 144:ef7eb2e8f9f7 5053 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5054 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<> 144:ef7eb2e8f9f7 5055 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<> 144:ef7eb2e8f9f7 5056
<> 144:ef7eb2e8f9f7 5057 /* Configure TI2 Filter and Polarity */
<> 144:ef7eb2e8f9f7 5058 TIM_TI2_ConfigInputStage(htim->Instance,
<> 144:ef7eb2e8f9f7 5059 sSlaveConfig->TriggerPolarity,
<> 144:ef7eb2e8f9f7 5060 sSlaveConfig->TriggerFilter);
<> 144:ef7eb2e8f9f7 5061 }
<> 144:ef7eb2e8f9f7 5062 break;
<> 144:ef7eb2e8f9f7 5063
<> 144:ef7eb2e8f9f7 5064 case TIM_TS_ITR0:
<> 144:ef7eb2e8f9f7 5065 {
<> 144:ef7eb2e8f9f7 5066 /* Check the parameter */
<> 144:ef7eb2e8f9f7 5067 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5068 }
<> 144:ef7eb2e8f9f7 5069 break;
<> 144:ef7eb2e8f9f7 5070
<> 144:ef7eb2e8f9f7 5071 case TIM_TS_ITR1:
<> 144:ef7eb2e8f9f7 5072 {
<> 144:ef7eb2e8f9f7 5073 /* Check the parameter */
<> 144:ef7eb2e8f9f7 5074 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5075 }
<> 144:ef7eb2e8f9f7 5076 break;
<> 144:ef7eb2e8f9f7 5077
<> 144:ef7eb2e8f9f7 5078 case TIM_TS_ITR2:
<> 144:ef7eb2e8f9f7 5079 {
<> 144:ef7eb2e8f9f7 5080 /* Check the parameter */
<> 144:ef7eb2e8f9f7 5081 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5082 }
<> 144:ef7eb2e8f9f7 5083 break;
<> 144:ef7eb2e8f9f7 5084
<> 144:ef7eb2e8f9f7 5085 case TIM_TS_ITR3:
<> 144:ef7eb2e8f9f7 5086 {
<> 144:ef7eb2e8f9f7 5087 /* Check the parameter */
<> 144:ef7eb2e8f9f7 5088 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5089 }
<> 144:ef7eb2e8f9f7 5090 break;
<> 144:ef7eb2e8f9f7 5091
<> 144:ef7eb2e8f9f7 5092 default:
<> 144:ef7eb2e8f9f7 5093 break;
<> 144:ef7eb2e8f9f7 5094 }
<> 144:ef7eb2e8f9f7 5095 }
<> 144:ef7eb2e8f9f7 5096
<> 144:ef7eb2e8f9f7 5097
<> 144:ef7eb2e8f9f7 5098 /**
<> 144:ef7eb2e8f9f7 5099 * @brief Configure the Polarity and Filter for TI1.
<> 144:ef7eb2e8f9f7 5100 * @param TIMx to select the TIM peripheral.
<> 144:ef7eb2e8f9f7 5101 * @param TIM_ICPolarity : The Input Polarity.
<> 144:ef7eb2e8f9f7 5102 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5103 * @arg TIM_ICPolarity_Rising
<> 144:ef7eb2e8f9f7 5104 * @arg TIM_ICPolarity_Falling
<> 144:ef7eb2e8f9f7 5105 * @arg TIM_ICPolarity_BothEdge
<> 144:ef7eb2e8f9f7 5106 * @param TIM_ICFilter: Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 5107 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 5108 * @retval None
<> 144:ef7eb2e8f9f7 5109 */
<> 144:ef7eb2e8f9f7 5110 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 5111 {
<> 144:ef7eb2e8f9f7 5112 uint32_t tmpccmr1 = 0U;
<> 144:ef7eb2e8f9f7 5113 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 5114
<> 144:ef7eb2e8f9f7 5115 /* Disable the Channel 1: Reset the CC1E Bit */
<> 144:ef7eb2e8f9f7 5116 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 5117 TIMx->CCER &= ~TIM_CCER_CC1E;
<> 144:ef7eb2e8f9f7 5118 tmpccmr1 = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 5119
<> 144:ef7eb2e8f9f7 5120 /* Set the filter */
<> 144:ef7eb2e8f9f7 5121 tmpccmr1 &= ~TIM_CCMR1_IC1F;
<> 144:ef7eb2e8f9f7 5122 tmpccmr1 |= (TIM_ICFilter << 4U);
<> 144:ef7eb2e8f9f7 5123
<> 144:ef7eb2e8f9f7 5124 /* Select the Polarity and set the CC1E Bit */
<> 144:ef7eb2e8f9f7 5125 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
<> 144:ef7eb2e8f9f7 5126 tmpccer |= TIM_ICPolarity;
<> 144:ef7eb2e8f9f7 5127
<> 144:ef7eb2e8f9f7 5128 /* Write to TIMx CCMR1 and CCER registers */
<> 144:ef7eb2e8f9f7 5129 TIMx->CCMR1 = tmpccmr1;
<> 144:ef7eb2e8f9f7 5130 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 5131 }
<> 144:ef7eb2e8f9f7 5132
<> 144:ef7eb2e8f9f7 5133 /**
<> 144:ef7eb2e8f9f7 5134 * @brief Configure the TI2 as Input.
<> 144:ef7eb2e8f9f7 5135 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 5136 * @param TIM_ICPolarity : The Input Polarity.
<> 144:ef7eb2e8f9f7 5137 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5138 * @arg TIM_ICPolarity_Rising
<> 144:ef7eb2e8f9f7 5139 * @arg TIM_ICPolarity_Falling
<> 144:ef7eb2e8f9f7 5140 * @arg TIM_ICPolarity_BothEdge
<> 144:ef7eb2e8f9f7 5141 * @param TIM_ICSelection: specifies the input to be used.
<> 144:ef7eb2e8f9f7 5142 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5143 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
<> 144:ef7eb2e8f9f7 5144 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
<> 144:ef7eb2e8f9f7 5145 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
<> 144:ef7eb2e8f9f7 5146 * @param TIM_ICFilter: Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 5147 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 5148 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
<> 144:ef7eb2e8f9f7 5149 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
<> 144:ef7eb2e8f9f7 5150 * protected against un-initialized filter and polarity values.
<> 144:ef7eb2e8f9f7 5151 * @retval None
<> 144:ef7eb2e8f9f7 5152 */
<> 144:ef7eb2e8f9f7 5153 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 5154 uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 5155 {
<> 144:ef7eb2e8f9f7 5156 uint32_t tmpccmr1 = 0U;
<> 144:ef7eb2e8f9f7 5157 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 5158
<> 144:ef7eb2e8f9f7 5159 /* Disable the Channel 2: Reset the CC2E Bit */
<> 144:ef7eb2e8f9f7 5160 TIMx->CCER &= ~TIM_CCER_CC2E;
<> 144:ef7eb2e8f9f7 5161 tmpccmr1 = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 5162 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 5163
<> 144:ef7eb2e8f9f7 5164 /* Select the Input */
<> 144:ef7eb2e8f9f7 5165 tmpccmr1 &= ~TIM_CCMR1_CC2S;
<> 144:ef7eb2e8f9f7 5166 tmpccmr1 |= (TIM_ICSelection << 8U);
<> 144:ef7eb2e8f9f7 5167
<> 144:ef7eb2e8f9f7 5168 /* Set the filter */
<> 144:ef7eb2e8f9f7 5169 tmpccmr1 &= ~TIM_CCMR1_IC2F;
<> 144:ef7eb2e8f9f7 5170 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
<> 144:ef7eb2e8f9f7 5171
<> 144:ef7eb2e8f9f7 5172 /* Select the Polarity and set the CC2E Bit */
<> 144:ef7eb2e8f9f7 5173 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
<> 144:ef7eb2e8f9f7 5174 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
<> 144:ef7eb2e8f9f7 5175
<> 144:ef7eb2e8f9f7 5176 /* Write to TIMx CCMR1 and CCER registers */
<> 144:ef7eb2e8f9f7 5177 TIMx->CCMR1 = tmpccmr1 ;
<> 144:ef7eb2e8f9f7 5178 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 5179 }
<> 144:ef7eb2e8f9f7 5180
<> 144:ef7eb2e8f9f7 5181 /**
<> 144:ef7eb2e8f9f7 5182 * @brief Configure the Polarity and Filter for TI2.
<> 144:ef7eb2e8f9f7 5183 * @param TIMx to select the TIM peripheral.
<> 144:ef7eb2e8f9f7 5184 * @param TIM_ICPolarity : The Input Polarity.
<> 144:ef7eb2e8f9f7 5185 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5186 * @arg TIM_ICPolarity_Rising
<> 144:ef7eb2e8f9f7 5187 * @arg TIM_ICPolarity_Falling
<> 144:ef7eb2e8f9f7 5188 * @arg TIM_ICPolarity_BothEdge
<> 144:ef7eb2e8f9f7 5189 * @param TIM_ICFilter: Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 5190 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 5191 * @retval None
<> 144:ef7eb2e8f9f7 5192 */
<> 144:ef7eb2e8f9f7 5193 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 5194 {
<> 144:ef7eb2e8f9f7 5195 uint32_t tmpccmr1 = 0U;
<> 144:ef7eb2e8f9f7 5196 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 5197
<> 144:ef7eb2e8f9f7 5198 /* Disable the Channel 2: Reset the CC2E Bit */
<> 144:ef7eb2e8f9f7 5199 TIMx->CCER &= ~TIM_CCER_CC2E;
<> 144:ef7eb2e8f9f7 5200 tmpccmr1 = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 5201 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 5202
<> 144:ef7eb2e8f9f7 5203 /* Set the filter */
<> 144:ef7eb2e8f9f7 5204 tmpccmr1 &= ~TIM_CCMR1_IC2F;
<> 144:ef7eb2e8f9f7 5205 tmpccmr1 |= (TIM_ICFilter << 12U);
<> 144:ef7eb2e8f9f7 5206
<> 144:ef7eb2e8f9f7 5207 /* Select the Polarity and set the CC2E Bit */
<> 144:ef7eb2e8f9f7 5208 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
<> 144:ef7eb2e8f9f7 5209 tmpccer |= (TIM_ICPolarity << 4U);
<> 144:ef7eb2e8f9f7 5210
<> 144:ef7eb2e8f9f7 5211 /* Write to TIMx CCMR1 and CCER registers */
<> 144:ef7eb2e8f9f7 5212 TIMx->CCMR1 = tmpccmr1 ;
<> 144:ef7eb2e8f9f7 5213 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 5214 }
<> 144:ef7eb2e8f9f7 5215
<> 144:ef7eb2e8f9f7 5216 /**
<> 144:ef7eb2e8f9f7 5217 * @brief Configure the TI3 as Input.
<> 144:ef7eb2e8f9f7 5218 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 5219 * @param TIM_ICPolarity : The Input Polarity.
<> 144:ef7eb2e8f9f7 5220 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5221 * @arg TIM_ICPolarity_Rising
<> 144:ef7eb2e8f9f7 5222 * @arg TIM_ICPolarity_Falling
<> 144:ef7eb2e8f9f7 5223 * @arg TIM_ICPolarity_BothEdge
<> 144:ef7eb2e8f9f7 5224 * @param TIM_ICSelection: specifies the input to be used.
<> 144:ef7eb2e8f9f7 5225 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5226 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
<> 144:ef7eb2e8f9f7 5227 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
<> 144:ef7eb2e8f9f7 5228 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
<> 144:ef7eb2e8f9f7 5229 * @param TIM_ICFilter: Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 5230 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 5231 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
<> 144:ef7eb2e8f9f7 5232 * (on channel4 path) is used as the input signal. Therefore CCMR2 must be
<> 144:ef7eb2e8f9f7 5233 * protected against un-initialized filter and polarity values.
<> 144:ef7eb2e8f9f7 5234 * @retval None
<> 144:ef7eb2e8f9f7 5235 */
<> 144:ef7eb2e8f9f7 5236 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 5237 uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 5238 {
<> 144:ef7eb2e8f9f7 5239 uint32_t tmpccmr2 = 0U;
<> 144:ef7eb2e8f9f7 5240 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 5241
<> 144:ef7eb2e8f9f7 5242 /* Disable the Channel 3: Reset the CC3E Bit */
<> 144:ef7eb2e8f9f7 5243 TIMx->CCER &= ~TIM_CCER_CC3E;
<> 144:ef7eb2e8f9f7 5244 tmpccmr2 = TIMx->CCMR2;
<> 144:ef7eb2e8f9f7 5245 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 5246
<> 144:ef7eb2e8f9f7 5247 /* Select the Input */
<> 144:ef7eb2e8f9f7 5248 tmpccmr2 &= ~TIM_CCMR2_CC3S;
<> 144:ef7eb2e8f9f7 5249 tmpccmr2 |= TIM_ICSelection;
<> 144:ef7eb2e8f9f7 5250
<> 144:ef7eb2e8f9f7 5251 /* Set the filter */
<> 144:ef7eb2e8f9f7 5252 tmpccmr2 &= ~TIM_CCMR2_IC3F;
<> 144:ef7eb2e8f9f7 5253 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
<> 144:ef7eb2e8f9f7 5254
<> 144:ef7eb2e8f9f7 5255 /* Select the Polarity and set the CC3E Bit */
<> 144:ef7eb2e8f9f7 5256 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
<> 144:ef7eb2e8f9f7 5257 tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
<> 144:ef7eb2e8f9f7 5258
<> 144:ef7eb2e8f9f7 5259 /* Write to TIMx CCMR2 and CCER registers */
<> 144:ef7eb2e8f9f7 5260 TIMx->CCMR2 = tmpccmr2;
<> 144:ef7eb2e8f9f7 5261 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 5262 }
<> 144:ef7eb2e8f9f7 5263
<> 144:ef7eb2e8f9f7 5264 /**
<> 144:ef7eb2e8f9f7 5265 * @brief Configure the TI4 as Input.
<> 144:ef7eb2e8f9f7 5266 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 5267 * @param TIM_ICPolarity : The Input Polarity.
<> 144:ef7eb2e8f9f7 5268 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5269 * @arg TIM_ICPolarity_Rising
<> 144:ef7eb2e8f9f7 5270 * @arg TIM_ICPolarity_Falling
<> 144:ef7eb2e8f9f7 5271 * @arg TIM_ICPolarity_BothEdge
<> 144:ef7eb2e8f9f7 5272 * @param TIM_ICSelection: specifies the input to be used.
<> 144:ef7eb2e8f9f7 5273 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5274 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
<> 144:ef7eb2e8f9f7 5275 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
<> 144:ef7eb2e8f9f7 5276 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
<> 144:ef7eb2e8f9f7 5277 * @param TIM_ICFilter: Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 5278 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 5279 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
<> 144:ef7eb2e8f9f7 5280 * (on channel3 path) is used as the input signal. Therefore CCMR2 must be
<> 144:ef7eb2e8f9f7 5281 * protected against un-initialized filter and polarity values.
<> 144:ef7eb2e8f9f7 5282 * @retval None
<> 144:ef7eb2e8f9f7 5283 */
<> 144:ef7eb2e8f9f7 5284 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 5285 uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 5286 {
<> 144:ef7eb2e8f9f7 5287 uint32_t tmpccmr2 = 0U;
<> 144:ef7eb2e8f9f7 5288 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 5289
<> 144:ef7eb2e8f9f7 5290 /* Disable the Channel 4: Reset the CC4E Bit */
<> 144:ef7eb2e8f9f7 5291 TIMx->CCER &= ~TIM_CCER_CC4E;
<> 144:ef7eb2e8f9f7 5292 tmpccmr2 = TIMx->CCMR2;
<> 144:ef7eb2e8f9f7 5293 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 5294
<> 144:ef7eb2e8f9f7 5295 /* Select the Input */
<> 144:ef7eb2e8f9f7 5296 tmpccmr2 &= ~TIM_CCMR2_CC4S;
<> 144:ef7eb2e8f9f7 5297 tmpccmr2 |= (TIM_ICSelection << 8U);
<> 144:ef7eb2e8f9f7 5298
<> 144:ef7eb2e8f9f7 5299 /* Set the filter */
<> 144:ef7eb2e8f9f7 5300 tmpccmr2 &= ~TIM_CCMR2_IC4F;
<> 144:ef7eb2e8f9f7 5301 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
<> 144:ef7eb2e8f9f7 5302
<> 144:ef7eb2e8f9f7 5303 /* Select the Polarity and set the CC4E Bit */
<> 144:ef7eb2e8f9f7 5304 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
<> 144:ef7eb2e8f9f7 5305 tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
<> 144:ef7eb2e8f9f7 5306
<> 144:ef7eb2e8f9f7 5307 /* Write to TIMx CCMR2 and CCER registers */
<> 144:ef7eb2e8f9f7 5308 TIMx->CCMR2 = tmpccmr2;
<> 144:ef7eb2e8f9f7 5309 TIMx->CCER = tmpccer ;
<> 144:ef7eb2e8f9f7 5310 }
<> 144:ef7eb2e8f9f7 5311
<> 144:ef7eb2e8f9f7 5312 /**
<> 144:ef7eb2e8f9f7 5313 * @brief Selects the Input Trigger source
<> 144:ef7eb2e8f9f7 5314 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 5315 * @param TIM_ITRx: The Input Trigger source.
<> 144:ef7eb2e8f9f7 5316 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5317 * @arg TIM_TS_ITR0: Internal Trigger 0
<> 144:ef7eb2e8f9f7 5318 * @arg TIM_TS_ITR1: Internal Trigger 1
<> 144:ef7eb2e8f9f7 5319 * @arg TIM_TS_ITR2: Internal Trigger 2
<> 144:ef7eb2e8f9f7 5320 * @arg TIM_TS_ITR3: Internal Trigger 3
<> 144:ef7eb2e8f9f7 5321 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
<> 144:ef7eb2e8f9f7 5322 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
<> 144:ef7eb2e8f9f7 5323 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
<> 144:ef7eb2e8f9f7 5324 * @arg TIM_TS_ETRF: External Trigger input
<> 144:ef7eb2e8f9f7 5325 * @retval None
<> 144:ef7eb2e8f9f7 5326 */
<> 144:ef7eb2e8f9f7 5327 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
<> 144:ef7eb2e8f9f7 5328 {
<> 144:ef7eb2e8f9f7 5329 uint32_t tmpsmcr = 0U;
<> 144:ef7eb2e8f9f7 5330
<> 144:ef7eb2e8f9f7 5331 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 5332 tmpsmcr = TIMx->SMCR;
<> 144:ef7eb2e8f9f7 5333 /* Reset the TS Bits */
<> 144:ef7eb2e8f9f7 5334 tmpsmcr &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 5335 /* Set the Input Trigger source and the slave mode*/
<> 144:ef7eb2e8f9f7 5336 tmpsmcr |= TIM_ITRx | TIM_SLAVEMODE_EXTERNAL1;
<> 144:ef7eb2e8f9f7 5337 /* Write to TIMx SMCR */
<> 144:ef7eb2e8f9f7 5338 TIMx->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 5339 }
<> 144:ef7eb2e8f9f7 5340
<> 144:ef7eb2e8f9f7 5341 /**
<> 144:ef7eb2e8f9f7 5342 * @brief Configures the TIMx External Trigger (ETR).
<> 144:ef7eb2e8f9f7 5343 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 5344 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
<> 144:ef7eb2e8f9f7 5345 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5346 * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
<> 144:ef7eb2e8f9f7 5347 * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
<> 144:ef7eb2e8f9f7 5348 * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
<> 144:ef7eb2e8f9f7 5349 * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
<> 144:ef7eb2e8f9f7 5350 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
<> 144:ef7eb2e8f9f7 5351 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5352 * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
<> 144:ef7eb2e8f9f7 5353 * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
<> 144:ef7eb2e8f9f7 5354 * @param ExtTRGFilter: External Trigger Filter.
<> 144:ef7eb2e8f9f7 5355 * This parameter must be a value between 0x00 and 0x0F
<> 144:ef7eb2e8f9f7 5356 * @retval None
<> 144:ef7eb2e8f9f7 5357 */
<> 144:ef7eb2e8f9f7 5358 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
<> 144:ef7eb2e8f9f7 5359 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
<> 144:ef7eb2e8f9f7 5360 {
<> 144:ef7eb2e8f9f7 5361 uint32_t tmpsmcr = 0U;
<> 144:ef7eb2e8f9f7 5362
<> 144:ef7eb2e8f9f7 5363 tmpsmcr = TIMx->SMCR;
<> 144:ef7eb2e8f9f7 5364
<> 144:ef7eb2e8f9f7 5365 /* Reset the ETR Bits */
<> 144:ef7eb2e8f9f7 5366 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
<> 144:ef7eb2e8f9f7 5367
<> 144:ef7eb2e8f9f7 5368 /* Set the Prescaler, the Filter value and the Polarity */
<> 144:ef7eb2e8f9f7 5369 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
<> 144:ef7eb2e8f9f7 5370
<> 144:ef7eb2e8f9f7 5371 /* Write to TIMx SMCR */
<> 144:ef7eb2e8f9f7 5372 TIMx->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 5373 }
<> 144:ef7eb2e8f9f7 5374
<> 144:ef7eb2e8f9f7 5375 /**
<> 144:ef7eb2e8f9f7 5376 * @}
<> 144:ef7eb2e8f9f7 5377 */
<> 144:ef7eb2e8f9f7 5378
<> 144:ef7eb2e8f9f7 5379 #endif /* HAL_TIM_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 5380 /**
<> 144:ef7eb2e8f9f7 5381 * @}
<> 144:ef7eb2e8f9f7 5382 */
<> 144:ef7eb2e8f9f7 5383
<> 144:ef7eb2e8f9f7 5384 /**
<> 144:ef7eb2e8f9f7 5385 * @}
<> 144:ef7eb2e8f9f7 5386 */
<> 144:ef7eb2e8f9f7 5387 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/