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targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_i2s.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_NUVOTON/TARGET_NUC472/StdDriver/nuc472_i2s.c@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /******************************************************************************
<> 144:ef7eb2e8f9f7 2 * @file i2s.c
<> 144:ef7eb2e8f9f7 3 * @version V0.10
<> 144:ef7eb2e8f9f7 4 * $Revision: 14 $
<> 144:ef7eb2e8f9f7 5 * $Date: 14/09/30 1:10p $
<> 144:ef7eb2e8f9f7 6 * @brief NUC472/NUC442 I2S driver source file
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * @note
<> 144:ef7eb2e8f9f7 9 * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
<> 144:ef7eb2e8f9f7 10 *****************************************************************************/
<> 144:ef7eb2e8f9f7 11
<> 144:ef7eb2e8f9f7 12 #include <stdio.h>
<> 144:ef7eb2e8f9f7 13 #include "NUC472_442.h"
<> 144:ef7eb2e8f9f7 14
<> 144:ef7eb2e8f9f7 15 /** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
<> 144:ef7eb2e8f9f7 16 @{
<> 144:ef7eb2e8f9f7 17 */
<> 144:ef7eb2e8f9f7 18
<> 144:ef7eb2e8f9f7 19 /** @addtogroup NUC472_442_I2S_Driver I2S Driver
<> 144:ef7eb2e8f9f7 20 @{
<> 144:ef7eb2e8f9f7 21 */
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 /** @addtogroup NUC472_442_I2S_EXPORTED_FUNCTIONS I2S Exported Functions
<> 144:ef7eb2e8f9f7 24 @{
<> 144:ef7eb2e8f9f7 25 */
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 /**
<> 144:ef7eb2e8f9f7 28 * @brief This function is used to get I2S source clock frequency.
<> 144:ef7eb2e8f9f7 29 * @param[in] i2s is the base address of I2S module.
<> 144:ef7eb2e8f9f7 30 * @return I2S source clock frequency (Hz).
<> 144:ef7eb2e8f9f7 31 */
<> 144:ef7eb2e8f9f7 32 static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s)
<> 144:ef7eb2e8f9f7 33 {
<> 144:ef7eb2e8f9f7 34 uint32_t u32Freq, u32ClkSrcSel;
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 // get I2S selection clock source
<> 144:ef7eb2e8f9f7 37 if((uint32_t)i2s == I2S0_BASE)
<> 144:ef7eb2e8f9f7 38 u32ClkSrcSel = CLK->CLKSEL3 & CLK_CLKSEL3_I2S0SEL_Msk;
<> 144:ef7eb2e8f9f7 39 else
<> 144:ef7eb2e8f9f7 40 u32ClkSrcSel = CLK->CLKSEL3 & CLK_CLKSEL3_I2S1SEL_Msk;
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 switch (u32ClkSrcSel) {
<> 144:ef7eb2e8f9f7 43 case CLK_CLKSEL3_I2S0SEL_HXT:
<> 144:ef7eb2e8f9f7 44 u32Freq = __HXT;
<> 144:ef7eb2e8f9f7 45 break;
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 case CLK_CLKSEL3_I2S0SEL_PLL:
<> 144:ef7eb2e8f9f7 48 case CLK_CLKSEL3_I2S1SEL_PLL:
<> 144:ef7eb2e8f9f7 49 u32Freq = CLK_GetPLLClockFreq();
<> 144:ef7eb2e8f9f7 50 break;
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 case CLK_CLKSEL3_I2S0SEL_HIRC:
<> 144:ef7eb2e8f9f7 53 case CLK_CLKSEL3_I2S1SEL_HIRC:
<> 144:ef7eb2e8f9f7 54 u32Freq = __HIRC;
<> 144:ef7eb2e8f9f7 55 break;
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 case CLK_CLKSEL3_I2S0SEL_PCLK:
<> 144:ef7eb2e8f9f7 58 case CLK_CLKSEL3_I2S1SEL_PCLK:
<> 144:ef7eb2e8f9f7 59 u32Freq = SystemCoreClock;
<> 144:ef7eb2e8f9f7 60 break;
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 default:
<> 144:ef7eb2e8f9f7 63 u32Freq = __HIRC;
<> 144:ef7eb2e8f9f7 64 break;
<> 144:ef7eb2e8f9f7 65 }
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 return u32Freq;
<> 144:ef7eb2e8f9f7 68 }
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 /**
<> 144:ef7eb2e8f9f7 71 * @brief This function configures some parameters of I2S interface for general purpose use.
<> 144:ef7eb2e8f9f7 72 * The sample rate may not be used from the parameter, it depends on system's clock settings,
<> 144:ef7eb2e8f9f7 73 * but real sample rate used by system will be returned for reference.
<> 144:ef7eb2e8f9f7 74 * @param[in] i2s is the base address of I2S module.
<> 144:ef7eb2e8f9f7 75 * @param[in] u32MasterSlave I2S operation mode. Valid values are:
<> 144:ef7eb2e8f9f7 76 * - \ref I2S_MODE_MASTER
<> 144:ef7eb2e8f9f7 77 * - \ref I2S_MODE_SLAVE
<> 144:ef7eb2e8f9f7 78 * @param[in] u32SampleRate Sample rate
<> 144:ef7eb2e8f9f7 79 * @param[in] u32WordWidth Data length. Valid values are:
<> 144:ef7eb2e8f9f7 80 * - \ref I2S_DATABIT_8
<> 144:ef7eb2e8f9f7 81 * - \ref I2S_DATABIT_16
<> 144:ef7eb2e8f9f7 82 * - \ref I2S_DATABIT_24
<> 144:ef7eb2e8f9f7 83 * - \ref I2S_DATABIT_32
<> 144:ef7eb2e8f9f7 84 * @param[in] u32Channels: Audio format. Valid values are:
<> 144:ef7eb2e8f9f7 85 * - \ref I2S_MONO
<> 144:ef7eb2e8f9f7 86 * - \ref I2S_STEREO
<> 144:ef7eb2e8f9f7 87 * @param[in] u32DataFormat: Data format. Valid values are:
<> 144:ef7eb2e8f9f7 88 * - \ref I2S_FORMAT_I2S
<> 144:ef7eb2e8f9f7 89 * - \ref I2S_FORMAT_MSB
<> 144:ef7eb2e8f9f7 90 * - \ref I2S_FORMAT_PCMA
<> 144:ef7eb2e8f9f7 91 * - \ref I2S_FORMAT_PCMB
<> 144:ef7eb2e8f9f7 92 * @param[in] u32AudioInterface: Audio interface. Valid values are:
<> 144:ef7eb2e8f9f7 93 * - \ref I2S_I2S
<> 144:ef7eb2e8f9f7 94 * - \ref I2S_PCM
<> 144:ef7eb2e8f9f7 95 * @return Real sample rate.
<> 144:ef7eb2e8f9f7 96 */
<> 144:ef7eb2e8f9f7 97 uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat, uint32_t u32AudioInterface)
<> 144:ef7eb2e8f9f7 98 {
<> 144:ef7eb2e8f9f7 99 uint16_t u16Divider;
<> 144:ef7eb2e8f9f7 100 uint32_t u32BitRate, u32SrcClk;
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 if((uint32_t)i2s == I2S0_BASE) {
<> 144:ef7eb2e8f9f7 103 SYS->IPRST1 |= SYS_IPRST1_I2S0RST_Msk;
<> 144:ef7eb2e8f9f7 104 SYS->IPRST1 &= ~SYS_IPRST1_I2S0RST_Msk;
<> 144:ef7eb2e8f9f7 105 } else {
<> 144:ef7eb2e8f9f7 106 SYS->IPRST1 |= SYS_IPRST1_I2S1RST_Msk;
<> 144:ef7eb2e8f9f7 107 SYS->IPRST1 &= ~SYS_IPRST1_I2S1RST_Msk;
<> 144:ef7eb2e8f9f7 108 }
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 i2s->CTL = u32MasterSlave | u32WordWidth | u32Channels | u32DataFormat | u32AudioInterface | I2S_FIFO_TX_LEVEL_WORD_4 | I2S_FIFO_RX_LEVEL_WORD_4;
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 u32SrcClk = I2S_GetSourceClockFreq(i2s);
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 u32BitRate = u32SampleRate * (((u32WordWidth>>4) & 0x3) + 1) * 16;
<> 144:ef7eb2e8f9f7 115 u16Divider = ((u32SrcClk/u32BitRate) >> 1) - 1;
<> 144:ef7eb2e8f9f7 116 i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_BCLKDIV_Msk) | (u16Divider << 8);
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 //calculate real sample rate
<> 144:ef7eb2e8f9f7 119 u32BitRate = u32SrcClk / (2*(u16Divider+1));
<> 144:ef7eb2e8f9f7 120 u32SampleRate = u32BitRate / ((((u32WordWidth>>4) & 0x3) + 1) * 16);
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 i2s->CTL |= I2S_CTL_I2SEN_Msk;
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 return u32SampleRate;
<> 144:ef7eb2e8f9f7 125 }
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /**
<> 144:ef7eb2e8f9f7 128 * @brief Disable I2S function and I2S clock.
<> 144:ef7eb2e8f9f7 129 * @param[in] i2s is the base address of I2S module.
<> 144:ef7eb2e8f9f7 130 * @return none
<> 144:ef7eb2e8f9f7 131 */
<> 144:ef7eb2e8f9f7 132 void I2S_Close(I2S_T *i2s)
<> 144:ef7eb2e8f9f7 133 {
<> 144:ef7eb2e8f9f7 134 i2s->CTL &= ~I2S_CTL_I2SEN_Msk;
<> 144:ef7eb2e8f9f7 135 }
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 /**
<> 144:ef7eb2e8f9f7 138 * @brief This function enables the interrupt according to the mask parameter.
<> 144:ef7eb2e8f9f7 139 * @param[in] i2s is the base address of I2S module.
<> 144:ef7eb2e8f9f7 140 * @param[in] u32Mask is the combination of all related interrupt enable bits.
<> 144:ef7eb2e8f9f7 141 * Each bit corresponds to a interrupt bit.
<> 144:ef7eb2e8f9f7 142 * @return none
<> 144:ef7eb2e8f9f7 143 */
<> 144:ef7eb2e8f9f7 144 void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask)
<> 144:ef7eb2e8f9f7 145 {
<> 144:ef7eb2e8f9f7 146 i2s->IEN |= u32Mask;
<> 144:ef7eb2e8f9f7 147 }
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /**
<> 144:ef7eb2e8f9f7 150 * @brief This function disables the interrupt according to the mask parameter.
<> 144:ef7eb2e8f9f7 151 * @param[in] i2s is the base address of I2S module.
<> 144:ef7eb2e8f9f7 152 * @param[in] u32Mask is the combination of all related interrupt enable bits.
<> 144:ef7eb2e8f9f7 153 * Each bit corresponds to a interrupt bit.
<> 144:ef7eb2e8f9f7 154 * @return none
<> 144:ef7eb2e8f9f7 155 */
<> 144:ef7eb2e8f9f7 156 void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask)
<> 144:ef7eb2e8f9f7 157 {
<> 144:ef7eb2e8f9f7 158 i2s->IEN &= ~u32Mask;
<> 144:ef7eb2e8f9f7 159 }
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /**
<> 144:ef7eb2e8f9f7 162 * @brief Enable MCLK .
<> 144:ef7eb2e8f9f7 163 * @param[in] i2s is the base address of I2S module.
<> 144:ef7eb2e8f9f7 164 * @param[in] u32BusClock is the target MCLK clock
<> 144:ef7eb2e8f9f7 165 * @return Actual MCLK clock
<> 144:ef7eb2e8f9f7 166 */
<> 144:ef7eb2e8f9f7 167 uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock)
<> 144:ef7eb2e8f9f7 168 {
<> 144:ef7eb2e8f9f7 169 uint8_t u8Divider;
<> 144:ef7eb2e8f9f7 170 uint32_t u32SrcClk, u32Reg;
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 u32SrcClk = I2S_GetSourceClockFreq(i2s);
<> 144:ef7eb2e8f9f7 173 if (u32BusClock == u32SrcClk)
<> 144:ef7eb2e8f9f7 174 u8Divider = 0;
<> 144:ef7eb2e8f9f7 175 else
<> 144:ef7eb2e8f9f7 176 u8Divider = (u32SrcClk/u32BusClock) >> 1;
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_MCLKDIV_Msk) | u8Divider;
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 i2s->CTL |= I2S_CTL_MCLKEN_Msk;
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 u32Reg = i2s->CLKDIV & I2S_CLKDIV_MCLKDIV_Msk;
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 if (u32Reg == 0)
<> 144:ef7eb2e8f9f7 185 return u32SrcClk;
<> 144:ef7eb2e8f9f7 186 else
<> 144:ef7eb2e8f9f7 187 return ((u32SrcClk >> 1) / u32Reg);
<> 144:ef7eb2e8f9f7 188 }
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 /**
<> 144:ef7eb2e8f9f7 191 * @brief Disable MCLK .
<> 144:ef7eb2e8f9f7 192 * @param[in] i2s is the base address of I2S module.
<> 144:ef7eb2e8f9f7 193 * @return none
<> 144:ef7eb2e8f9f7 194 */
<> 144:ef7eb2e8f9f7 195 void I2S_DisableMCLK(I2S_T *i2s)
<> 144:ef7eb2e8f9f7 196 {
<> 144:ef7eb2e8f9f7 197 i2s->CTL &= ~I2S_CTL_MCLKEN_Msk;
<> 144:ef7eb2e8f9f7 198 }
<> 144:ef7eb2e8f9f7 199 /*@}*/ /* end of group NUC472_442_I2S_EXPORTED_FUNCTIONS */
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /*@}*/ /* end of group NUC472_442_I2S_Driver */
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /*@}*/ /* end of group NUC472_442_Device_Driver */
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/