Pedro Correia / mbed-dev

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targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_STD/startup_LPC17xx.S@187:fa51feb62426, 2018-10-09 (annotated)

Committer:
pmcorreia
Date:
Tue Oct 09 14:42:37 2018 +0000
Revision:
187:fa51feb62426
Parent:
176:447f873cad2f 
Updated version to work with F446RE

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 ;/*****************************************************************************
<> 144:ef7eb2e8f9f7 2 ; * @file: startup_LPC17xx.s
<> 144:ef7eb2e8f9f7 3 ; * @purpose: CMSIS Cortex-M3 Core Device Startup File
<> 144:ef7eb2e8f9f7 4 ; * for the NXP LPC17xx Device Series
<> 144:ef7eb2e8f9f7 5 ; * @version: V1.02, modified for mbed
<> 144:ef7eb2e8f9f7 6 ; * @date: 27. July 2009, modified 3rd Aug 2009
<> 144:ef7eb2e8f9f7 7 ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
<> 144:ef7eb2e8f9f7 8 ; *
<> 144:ef7eb2e8f9f7 9 ; * Copyright (C) 2009 ARM Limited. All rights reserved.
<> 144:ef7eb2e8f9f7 10 ; * ARM Limited (ARM) is supplying this software for use with Cortex-M3
<> 144:ef7eb2e8f9f7 11 ; * processor based microcontrollers. This file can be freely distributed
<> 144:ef7eb2e8f9f7 12 ; * within development tools that are supporting such ARM based processors.
<> 144:ef7eb2e8f9f7 13 ; *
<> 144:ef7eb2e8f9f7 14 ; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 15 ; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 ; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 17 ; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
<> 144:ef7eb2e8f9f7 18 ; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 19 ; *
<> 144:ef7eb2e8f9f7 20 ; *****************************************************************************/
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 __initial_sp EQU 0x10008000 ; Top of RAM from LPC1768
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 PRESERVE8
<> 144:ef7eb2e8f9f7 25 THUMB
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 ; Vector Table Mapped to Address 0 at Reset
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 AREA RESET, DATA, READONLY
<> 144:ef7eb2e8f9f7 30 EXPORT __Vectors
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 __Vectors DCD __initial_sp ; Top of Stack
<> 144:ef7eb2e8f9f7 33 DCD Reset_Handler ; Reset Handler
<> 144:ef7eb2e8f9f7 34 DCD NMI_Handler ; NMI Handler
<> 144:ef7eb2e8f9f7 35 DCD HardFault_Handler ; Hard Fault Handler
<> 144:ef7eb2e8f9f7 36 DCD MemManage_Handler ; MPU Fault Handler
<> 144:ef7eb2e8f9f7 37 DCD BusFault_Handler ; Bus Fault Handler
<> 144:ef7eb2e8f9f7 38 DCD UsageFault_Handler ; Usage Fault Handler
<> 144:ef7eb2e8f9f7 39 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 40 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 41 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 42 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 43 DCD SVC_Handler ; SVCall Handler
<> 144:ef7eb2e8f9f7 44 DCD DebugMon_Handler ; Debug Monitor Handler
<> 144:ef7eb2e8f9f7 45 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 46 DCD PendSV_Handler ; PendSV Handler
<> 144:ef7eb2e8f9f7 47 DCD SysTick_Handler ; SysTick Handler
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 ; External Interrupts
<> 144:ef7eb2e8f9f7 50 DCD WDT_IRQHandler ; 16: Watchdog Timer
<> 144:ef7eb2e8f9f7 51 DCD TIMER0_IRQHandler ; 17: Timer0
<> 144:ef7eb2e8f9f7 52 DCD TIMER1_IRQHandler ; 18: Timer1
<> 144:ef7eb2e8f9f7 53 DCD TIMER2_IRQHandler ; 19: Timer2
<> 144:ef7eb2e8f9f7 54 DCD TIMER3_IRQHandler ; 20: Timer3
<> 144:ef7eb2e8f9f7 55 DCD UART0_IRQHandler ; 21: UART0
<> 144:ef7eb2e8f9f7 56 DCD UART1_IRQHandler ; 22: UART1
<> 144:ef7eb2e8f9f7 57 DCD UART2_IRQHandler ; 23: UART2
<> 144:ef7eb2e8f9f7 58 DCD UART3_IRQHandler ; 24: UART3
<> 144:ef7eb2e8f9f7 59 DCD PWM1_IRQHandler ; 25: PWM1
<> 144:ef7eb2e8f9f7 60 DCD I2C0_IRQHandler ; 26: I2C0
<> 144:ef7eb2e8f9f7 61 DCD I2C1_IRQHandler ; 27: I2C1
<> 144:ef7eb2e8f9f7 62 DCD I2C2_IRQHandler ; 28: I2C2
<> 144:ef7eb2e8f9f7 63 DCD SPI_IRQHandler ; 29: SPI
<> 144:ef7eb2e8f9f7 64 DCD SSP0_IRQHandler ; 30: SSP0
<> 144:ef7eb2e8f9f7 65 DCD SSP1_IRQHandler ; 31: SSP1
<> 144:ef7eb2e8f9f7 66 DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
<> 144:ef7eb2e8f9f7 67 DCD RTC_IRQHandler ; 33: Real Time Clock
<> 144:ef7eb2e8f9f7 68 DCD EINT0_IRQHandler ; 34: External Interrupt 0
<> 144:ef7eb2e8f9f7 69 DCD EINT1_IRQHandler ; 35: External Interrupt 1
<> 144:ef7eb2e8f9f7 70 DCD EINT2_IRQHandler ; 36: External Interrupt 2
<> 144:ef7eb2e8f9f7 71 DCD EINT3_IRQHandler ; 37: External Interrupt 3
<> 144:ef7eb2e8f9f7 72 DCD ADC_IRQHandler ; 38: A/D Converter
<> 144:ef7eb2e8f9f7 73 DCD BOD_IRQHandler ; 39: Brown-Out Detect
<> 144:ef7eb2e8f9f7 74 DCD USB_IRQHandler ; 40: USB
<> 144:ef7eb2e8f9f7 75 DCD CAN_IRQHandler ; 41: CAN
<> 144:ef7eb2e8f9f7 76 DCD DMA_IRQHandler ; 42: General Purpose DMA
<> 144:ef7eb2e8f9f7 77 DCD I2S_IRQHandler ; 43: I2S
<> 144:ef7eb2e8f9f7 78 DCD ENET_IRQHandler ; 44: Ethernet
<> 144:ef7eb2e8f9f7 79 DCD RIT_IRQHandler ; 45: Repetitive Interrupt Timer
<> 144:ef7eb2e8f9f7 80 DCD MCPWM_IRQHandler ; 46: Motor Control PWM
<> 144:ef7eb2e8f9f7 81 DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
<> 144:ef7eb2e8f9f7 82 DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 AREA |.text|, CODE, READONLY
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 ; Reset Handler
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 Reset_Handler PROC
<> 144:ef7eb2e8f9f7 91 EXPORT Reset_Handler [WEAK]
<> 144:ef7eb2e8f9f7 92 IMPORT SystemInit
<> 144:ef7eb2e8f9f7 93 IMPORT __main
<> 144:ef7eb2e8f9f7 94 LDR R0, =SystemInit
<> 144:ef7eb2e8f9f7 95 BLX R0
<> 144:ef7eb2e8f9f7 96 LDR R0, =__main
<> 144:ef7eb2e8f9f7 97 BX R0
<> 144:ef7eb2e8f9f7 98 ENDP
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 ; Dummy Exception Handlers (infinite loops which can be modified)
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 NMI_Handler PROC
<> 144:ef7eb2e8f9f7 104 EXPORT NMI_Handler [WEAK]
<> 144:ef7eb2e8f9f7 105 B .
<> 144:ef7eb2e8f9f7 106 ENDP
<> 144:ef7eb2e8f9f7 107 HardFault_Handler\
<> 144:ef7eb2e8f9f7 108 PROC
<> 144:ef7eb2e8f9f7 109 EXPORT HardFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 110 B .
<> 144:ef7eb2e8f9f7 111 ENDP
<> 144:ef7eb2e8f9f7 112 MemManage_Handler\
<> 144:ef7eb2e8f9f7 113 PROC
<> 144:ef7eb2e8f9f7 114 EXPORT MemManage_Handler [WEAK]
<> 144:ef7eb2e8f9f7 115 B .
<> 144:ef7eb2e8f9f7 116 ENDP
<> 144:ef7eb2e8f9f7 117 BusFault_Handler\
<> 144:ef7eb2e8f9f7 118 PROC
<> 144:ef7eb2e8f9f7 119 EXPORT BusFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 120 B .
<> 144:ef7eb2e8f9f7 121 ENDP
<> 144:ef7eb2e8f9f7 122 UsageFault_Handler\
<> 144:ef7eb2e8f9f7 123 PROC
<> 144:ef7eb2e8f9f7 124 EXPORT UsageFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 125 B .
<> 144:ef7eb2e8f9f7 126 ENDP
<> 144:ef7eb2e8f9f7 127 SVC_Handler PROC
<> 144:ef7eb2e8f9f7 128 EXPORT SVC_Handler [WEAK]
<> 144:ef7eb2e8f9f7 129 B .
<> 144:ef7eb2e8f9f7 130 ENDP
<> 144:ef7eb2e8f9f7 131 DebugMon_Handler\
<> 144:ef7eb2e8f9f7 132 PROC
<> 144:ef7eb2e8f9f7 133 EXPORT DebugMon_Handler [WEAK]
<> 144:ef7eb2e8f9f7 134 B .
<> 144:ef7eb2e8f9f7 135 ENDP
<> 144:ef7eb2e8f9f7 136 PendSV_Handler PROC
<> 144:ef7eb2e8f9f7 137 EXPORT PendSV_Handler [WEAK]
<> 144:ef7eb2e8f9f7 138 B .
<> 144:ef7eb2e8f9f7 139 ENDP
<> 144:ef7eb2e8f9f7 140 SysTick_Handler PROC
<> 144:ef7eb2e8f9f7 141 EXPORT SysTick_Handler [WEAK]
<> 144:ef7eb2e8f9f7 142 B .
<> 144:ef7eb2e8f9f7 143 ENDP
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 Default_Handler PROC
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 EXPORT WDT_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 148 EXPORT TIMER0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 149 EXPORT TIMER1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 150 EXPORT TIMER2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 151 EXPORT TIMER3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 152 EXPORT UART0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 153 EXPORT UART1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 154 EXPORT UART2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 155 EXPORT UART3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 156 EXPORT PWM1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 157 EXPORT I2C0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 158 EXPORT I2C1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 159 EXPORT I2C2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 160 EXPORT SPI_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 161 EXPORT SSP0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 162 EXPORT SSP1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 163 EXPORT PLL0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 164 EXPORT RTC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 165 EXPORT EINT0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 166 EXPORT EINT1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 167 EXPORT EINT2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 168 EXPORT EINT3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 169 EXPORT ADC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 170 EXPORT BOD_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 171 EXPORT USB_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 172 EXPORT CAN_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 173 EXPORT DMA_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 174 EXPORT I2S_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 175 EXPORT ENET_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 176 EXPORT RIT_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 177 EXPORT MCPWM_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 178 EXPORT QEI_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 179 EXPORT PLL1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 WDT_IRQHandler
<> 144:ef7eb2e8f9f7 182 TIMER0_IRQHandler
<> 144:ef7eb2e8f9f7 183 TIMER1_IRQHandler
<> 144:ef7eb2e8f9f7 184 TIMER2_IRQHandler
<> 144:ef7eb2e8f9f7 185 TIMER3_IRQHandler
<> 144:ef7eb2e8f9f7 186 UART0_IRQHandler
<> 144:ef7eb2e8f9f7 187 UART1_IRQHandler
<> 144:ef7eb2e8f9f7 188 UART2_IRQHandler
<> 144:ef7eb2e8f9f7 189 UART3_IRQHandler
<> 144:ef7eb2e8f9f7 190 PWM1_IRQHandler
<> 144:ef7eb2e8f9f7 191 I2C0_IRQHandler
<> 144:ef7eb2e8f9f7 192 I2C1_IRQHandler
<> 144:ef7eb2e8f9f7 193 I2C2_IRQHandler
<> 144:ef7eb2e8f9f7 194 SPI_IRQHandler
<> 144:ef7eb2e8f9f7 195 SSP0_IRQHandler
<> 144:ef7eb2e8f9f7 196 SSP1_IRQHandler
<> 144:ef7eb2e8f9f7 197 PLL0_IRQHandler
<> 144:ef7eb2e8f9f7 198 RTC_IRQHandler
<> 144:ef7eb2e8f9f7 199 EINT0_IRQHandler
<> 144:ef7eb2e8f9f7 200 EINT1_IRQHandler
<> 144:ef7eb2e8f9f7 201 EINT2_IRQHandler
<> 144:ef7eb2e8f9f7 202 EINT3_IRQHandler
<> 144:ef7eb2e8f9f7 203 ADC_IRQHandler
<> 144:ef7eb2e8f9f7 204 BOD_IRQHandler
<> 144:ef7eb2e8f9f7 205 USB_IRQHandler
<> 144:ef7eb2e8f9f7 206 CAN_IRQHandler
<> 144:ef7eb2e8f9f7 207 DMA_IRQHandler
<> 144:ef7eb2e8f9f7 208 I2S_IRQHandler
<> 144:ef7eb2e8f9f7 209 ENET_IRQHandler
<> 144:ef7eb2e8f9f7 210 RIT_IRQHandler
<> 144:ef7eb2e8f9f7 211 MCPWM_IRQHandler
<> 144:ef7eb2e8f9f7 212 QEI_IRQHandler
<> 144:ef7eb2e8f9f7 213 PLL1_IRQHandler
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 B .
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 ENDP
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 ALIGN
<> 144:ef7eb2e8f9f7 220 END