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Revision 246:15713155d815, committed 2014-07-01
- Comitter:
- piyamate
- Date:
- Tue Jul 01 00:03:52 2014 +0000
- Parent:
- 245:b4dea936db71
- Commit message:
- Overclock K64F to 128.125MHz
Changed in this revision
targets/cmsis/TARGET_Freescale/TARGET_K64F/system_MK64F12.c | Show annotated file Show diff for this revision Revisions of this file |
--- a/targets/cmsis/TARGET_Freescale/TARGET_K64F/system_MK64F12.c Mon Jun 30 08:00:09 2014 +0100 +++ b/targets/cmsis/TARGET_Freescale/TARGET_K64F/system_MK64F12.c Tue Jul 01 00:03:52 2014 +0000 @@ -115,6 +115,9 @@ #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */ #endif /* (CLOCK_SETUP == 4) */ +#define OVERCLOCK 1 +#define PRDIV0 0x0F //Device Factor = 16 +#define VDIV0 0x11 //Multiply Factor = 41 /* ---------------------------------------------------------------------------- -- Core clock @@ -213,16 +216,28 @@ /* MCG->C4: DMX32=0,DRST_DRS=0 */ MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03))); /* MCG->C5: ?=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */ +#if (!OVERCLOCK) MCG->C5 = MCG_C5_PRDIV0(0x13); +#else + MCG->C5 = MCG_C5_PRDIV0(PRDIV0); +#endif /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0x18 */ +#if (!OVERCLOCK) MCG->C6 = MCG_C6_VDIV0(0x18); +#else + MCG->C6 = MCG_C6_VDIV0(VDIV0); +#endif while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */ } while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ } /* Switch to PBE Mode */ /* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */ +#if (!OVERCLOCK) MCG->C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x18)); +#else + MCG->C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(VDIV0)); +#endif while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ } while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */