p igmon / Mbed 2 deprecated DMA_I2S_Test

Simple Exmple

Dependencies:   ST_401_84MHZ mbed

http://www.geocities.jp/micro_diys/

main.cpp@1:530d6fb59a93, 2014-05-24 (annotated)

Committer:
p_igmon
Date:
Sat May 24 12:07:17 2014 +0000
Revision:
1:530d6fb59a93
Parent:
0:0093b4cc5297 
Nucleo F401RE I2S Transfer Example.

; DMA Dubble buffer mode.

; IRQ not yet.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
p_igmon 1:530d6fb59a93 1 /*
p_igmon 1:530d6fb59a93 2 Nucleo F401RE Board
p_igmon 1:530d6fb59a93 3 DMA Transmit sample
p_igmon 1:530d6fb59a93 4
p_igmon 1:530d6fb59a93 5 I2S Master Transmit (Enable MCK out)
p_igmon 1:530d6fb59a93 6 Phillips Format 16bit
p_igmon 1:530d6fb59a93 7 Dubble DMA Buffer
p_igmon 1:530d6fb59a93 8
p_igmon 1:530d6fb59a93 9
p_igmon 1:530d6fb59a93 10
p_igmon 1:530d6fb59a93 11
p_igmon 1:530d6fb59a93 12 */
p_igmon 1:530d6fb59a93 13
p_igmon 0:0093b4cc5297 14 #include "mbed.h"
p_igmon 0:0093b4cc5297 15 #include <math.h>
p_igmon 0:0093b4cc5297 16 #include "cmsis.h"
p_igmon 0:0093b4cc5297 17 #include "pinmap.h"
p_igmon 0:0093b4cc5297 18 #include "PinNames.h"
p_igmon 0:0093b4cc5297 19 #include "error.h"
p_igmon 1:530d6fb59a93 20 #include "stm32f401xe.h"
p_igmon 0:0093b4cc5297 21 #include "stm32f4xx.h"
p_igmon 0:0093b4cc5297 22 #include "stm32f4xx_hal.h"
p_igmon 0:0093b4cc5297 23 #include "stm32f4xx_hal_dma_ex.h"
p_igmon 1:530d6fb59a93 24 #include "stm32f4xx_hal_dma.h"
p_igmon 0:0093b4cc5297 25 #include "stm32f4xx_hal_i2s.h"
p_igmon 0:0093b4cc5297 26 #include "sine_wave.h"
p_igmon 0:0093b4cc5297 27 #include "saw_wave.h"
p_igmon 1:530d6fb59a93 28 #include "ST_F401_84MHZ.h"
p_igmon 0:0093b4cc5297 29
p_igmon 0:0093b4cc5297 30 Serial pc(SERIAL_TX, SERIAL_RX);
p_igmon 0:0093b4cc5297 31 DigitalOut myled(LED1);
p_igmon 0:0093b4cc5297 32
p_igmon 1:530d6fb59a93 33 #define I2S_BUFFERSIZE 256
p_igmon 1:530d6fb59a93 34 #define DMA_TRANSFERCOUNT (I2S_BUFFERSIZE<<1)
p_igmon 1:530d6fb59a93 35 int16_t dmabuffer[2][DMA_TRANSFERCOUNT];//DMA Double Buffer
p_igmon 0:0093b4cc5297 36
p_igmon 0:0093b4cc5297 37 static const PinMap PinMap_I2S_MCK[] = {
p_igmon 0:0093b4cc5297 38 {PC_6, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
p_igmon 1:530d6fb59a93 39 // {PC_7, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
p_igmon 0:0093b4cc5297 40 {NC, NC, 0}
p_igmon 0:0093b4cc5297 41 };
p_igmon 0:0093b4cc5297 42
p_igmon 0:0093b4cc5297 43 static const PinMap PinMap_I2S_CK[] = {
p_igmon 0:0093b4cc5297 44 {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
p_igmon 0:0093b4cc5297 45 {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
p_igmon 1:530d6fb59a93 46 // {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
p_igmon 1:530d6fb59a93 47 // {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
p_igmon 0:0093b4cc5297 48 {NC, NC, 0}
p_igmon 0:0093b4cc5297 49 };
p_igmon 0:0093b4cc5297 50
p_igmon 0:0093b4cc5297 51 static const PinMap PinMap_I2S_WS[] = {
p_igmon 0:0093b4cc5297 52 {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
p_igmon 0:0093b4cc5297 53 {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
p_igmon 1:530d6fb59a93 54 // {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
p_igmon 0:0093b4cc5297 55 {NC, NC, 0}
p_igmon 0:0093b4cc5297 56 };
p_igmon 0:0093b4cc5297 57
p_igmon 0:0093b4cc5297 58 static const PinMap PinMap_I2S_SD[] = {
p_igmon 0:0093b4cc5297 59 {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
p_igmon 0:0093b4cc5297 60 {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
p_igmon 1:530d6fb59a93 61 // {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
p_igmon 1:530d6fb59a93 62 // {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)},
p_igmon 0:0093b4cc5297 63 {NC, NC, 0}
p_igmon 0:0093b4cc5297 64 };
p_igmon 0:0093b4cc5297 65
p_igmon 0:0093b4cc5297 66
p_igmon 0:0093b4cc5297 67 DMA_InitTypeDef DMA_InitType ={
p_igmon 0:0093b4cc5297 68 DMA_CHANNEL_0,
p_igmon 0:0093b4cc5297 69 DMA_MEMORY_TO_PERIPH,
p_igmon 0:0093b4cc5297 70 DMA_PINC_DISABLE,
p_igmon 0:0093b4cc5297 71 DMA_MINC_ENABLE,
p_igmon 1:530d6fb59a93 72 DMA_PDATAALIGN_HALFWORD,
p_igmon 0:0093b4cc5297 73 DMA_MDATAALIGN_WORD,
p_igmon 1:530d6fb59a93 74 DMA_CIRCULAR,//DMA_PFCTRL,//
p_igmon 0:0093b4cc5297 75 DMA_PRIORITY_HIGH,
p_igmon 1:530d6fb59a93 76 DMA_FIFOMODE_DISABLE,//DMA_FIFOMODE_ENABLE,
p_igmon 0:0093b4cc5297 77 DMA_FIFO_THRESHOLD_HALFFULL,
p_igmon 0:0093b4cc5297 78 DMA_MBURST_SINGLE,
p_igmon 0:0093b4cc5297 79 DMA_PBURST_SINGLE
p_igmon 0:0093b4cc5297 80 };
p_igmon 0:0093b4cc5297 81
p_igmon 0:0093b4cc5297 82 DMA_HandleTypeDef DMA_HandleType ={
p_igmon 0:0093b4cc5297 83 DMA1_Stream4,
p_igmon 0:0093b4cc5297 84 DMA_InitType,
p_igmon 0:0093b4cc5297 85 HAL_UNLOCKED,
p_igmon 1:530d6fb59a93 86 HAL_DMA_STATE_RESET,//HAL_DMA_STATE_READY
p_igmon 0:0093b4cc5297 87 NULL,
p_igmon 0:0093b4cc5297 88 NULL,
p_igmon 0:0093b4cc5297 89 NULL,
p_igmon 0:0093b4cc5297 90 NULL,
p_igmon 0:0093b4cc5297 91 NULL,
p_igmon 0:0093b4cc5297 92 NULL
p_igmon 0:0093b4cc5297 93 };
p_igmon 0:0093b4cc5297 94
p_igmon 0:0093b4cc5297 95 I2S_InitTypeDef my_I2S_InitType ={
p_igmon 0:0093b4cc5297 96 I2S_MODE_MASTER_TX,
p_igmon 1:530d6fb59a93 97 I2S_STANDARD_PHILLIPS,
p_igmon 0:0093b4cc5297 98 I2S_DATAFORMAT_16B,
p_igmon 0:0093b4cc5297 99 I2S_MCLKOUTPUT_ENABLE,
p_igmon 0:0093b4cc5297 100 I2S_AUDIOFREQ_44K,
p_igmon 0:0093b4cc5297 101 I2S_CPOL_LOW,
p_igmon 0:0093b4cc5297 102 I2S_CLOCK_PLL,
p_igmon 0:0093b4cc5297 103 I2S_FULLDUPLEXMODE_DISABLE
p_igmon 0:0093b4cc5297 104 };
p_igmon 0:0093b4cc5297 105
p_igmon 0:0093b4cc5297 106 HAL_I2S_StateTypeDef my_I2S_StateTypeDef={
p_igmon 0:0093b4cc5297 107 HAL_I2S_STATE_RESET
p_igmon 0:0093b4cc5297 108 };
p_igmon 0:0093b4cc5297 109
p_igmon 0:0093b4cc5297 110 HAL_I2S_ErrorTypeDef my_I2S_ErorTypeDef={
p_igmon 0:0093b4cc5297 111 HAL_I2S_ERROR_NONE
p_igmon 0:0093b4cc5297 112 };
p_igmon 0:0093b4cc5297 113
p_igmon 0:0093b4cc5297 114 I2S_HandleTypeDef my_I2S_HandleTypeDef = {
p_igmon 0:0093b4cc5297 115 SPI2,
p_igmon 0:0093b4cc5297 116 my_I2S_InitType,
p_igmon 1:530d6fb59a93 117 (uint16_t*)&dmabuffer[0][0],
p_igmon 0:0093b4cc5297 118 I2S_BUFFERSIZE,
p_igmon 0:0093b4cc5297 119 NULL,
p_igmon 0:0093b4cc5297 120 NULL,
p_igmon 0:0093b4cc5297 121 NULL,
p_igmon 0:0093b4cc5297 122 NULL,
p_igmon 0:0093b4cc5297 123 &DMA_HandleType,//&my_DMA_HamdleType,
p_igmon 0:0093b4cc5297 124 NULL,
p_igmon 0:0093b4cc5297 125 HAL_UNLOCKED,
p_igmon 0:0093b4cc5297 126 my_I2S_StateTypeDef,
p_igmon 0:0093b4cc5297 127 my_I2S_ErorTypeDef
p_igmon 0:0093b4cc5297 128 };
p_igmon 0:0093b4cc5297 129
p_igmon 0:0093b4cc5297 130 void init_dmabuffer(void){
p_igmon 1:530d6fb59a93 131 for (int i =0;i < I2S_BUFFERSIZE;i++){
p_igmon 1:530d6fb59a93 132 dmabuffer[0][i*2] = sine_wave[i];// 1st Buffer Lch
p_igmon 1:530d6fb59a93 133 dmabuffer[0][i*2+1] = saw_wave[i];// 1nd Buffer Rch
p_igmon 1:530d6fb59a93 134 dmabuffer[1][i*2] = sine_wave[i];// 2nd Buffer Lch
p_igmon 1:530d6fb59a93 135 dmabuffer[1][i*2+1] = saw_wave[i];// 2nd Buffer Rch
p_igmon 0:0093b4cc5297 136 }
p_igmon 0:0093b4cc5297 137 }
p_igmon 1:530d6fb59a93 138
p_igmon 1:530d6fb59a93 139 #define PLLI2S_N 271
p_igmon 1:530d6fb59a93 140 #define PLLI2S_R 2
p_igmon 0:0093b4cc5297 141
p_igmon 0:0093b4cc5297 142 int main() {
p_igmon 1:530d6fb59a93 143 F401_init84 myinit(0);
p_igmon 1:530d6fb59a93 144 pc.baud(9600);
p_igmon 1:530d6fb59a93 145 pc.printf("CPU SystemCoreClock is %d Hz\r\n", SystemCoreClock);
p_igmon 0:0093b4cc5297 146 init_dmabuffer();
p_igmon 1:530d6fb59a93 147
p_igmon 1:530d6fb59a93 148 /* Configure the I2S PLL */
p_igmon 1:530d6fb59a93 149 RCC->PLLI2SCFGR = (PLLI2S_N << 6) | (PLLI2S_R << 28);
p_igmon 1:530d6fb59a93 150 /* Enable the I2S PLL */
p_igmon 1:530d6fb59a93 151 RCC->CR |= RCC_CR_PLLI2SON;
p_igmon 1:530d6fb59a93 152 /* Wait until the I2S PLL is ready */
p_igmon 1:530d6fb59a93 153 while (!(RCC->CR & RCC_CR_PLLI2SRDY));
p_igmon 1:530d6fb59a93 154
p_igmon 1:530d6fb59a93 155 __SPI2_CLK_ENABLE();
p_igmon 1:530d6fb59a93 156 __DMA1_CLK_ENABLE();
p_igmon 1:530d6fb59a93 157
p_igmon 1:530d6fb59a93 158 pinmap_pinout(PC_6, PinMap_I2S_MCK);
p_igmon 1:530d6fb59a93 159 pinmap_pinout(PB_13, PinMap_I2S_CK);
p_igmon 1:530d6fb59a93 160 pinmap_pinout(PB_12, PinMap_I2S_WS);
p_igmon 1:530d6fb59a93 161 pinmap_pinout(PB_15, PinMap_I2S_SD);
p_igmon 1:530d6fb59a93 162
p_igmon 0:0093b4cc5297 163 pin_mode(PC_6, PullUp);
p_igmon 1:530d6fb59a93 164 pin_mode(PB_13, PullUp);
p_igmon 0:0093b4cc5297 165 pin_mode(PB_12, PullUp);
p_igmon 1:530d6fb59a93 166 pin_mode(PB_15, PullUp);
p_igmon 1:530d6fb59a93 167
p_igmon 1:530d6fb59a93 168 if(HAL_DMA_Init(&DMA_HandleType)!= HAL_OK) pc.printf("Eror in HAL_DMA_Init \n\r");
p_igmon 1:530d6fb59a93 169
p_igmon 1:530d6fb59a93 170 if (HAL_I2S_Init(&my_I2S_HandleTypeDef)!= HAL_OK) pc.printf("Eror in HAL_I2S_Init \n\r");
p_igmon 1:530d6fb59a93 171
p_igmon 1:530d6fb59a93 172 volatile uint32_t *I2S_DR = &SPI2->DR;
p_igmon 1:530d6fb59a93 173 if(HAL_DMAEx_MultiBufferStart_IT(&DMA_HandleType ,(uint32_t)&dmabuffer[0][0] ,(uint32_t )I2S_DR ,(uint32_t)&dmabuffer[1][0] ,DMA_TRANSFERCOUNT)!=HAL_OK) pc.printf("Eror in HAL_DMAEx_MultiBufferStart_IT \n\r");
p_igmon 0:0093b4cc5297 174
p_igmon 1:530d6fb59a93 175 SPI2->I2SCFGR |= SPI_I2SCFGR_I2SE;
p_igmon 1:530d6fb59a93 176 /* Enable Tx DMA Request */
p_igmon 1:530d6fb59a93 177 SPI2->CR2 |= SPI_CR2_TXDMAEN;
p_igmon 0:0093b4cc5297 178
p_igmon 1:530d6fb59a93 179 pc.printf("DMA M0AR =%4x M1AR =%4x PAR = %4x \n\r" ,DMA1_Stream4->M0AR ,DMA1_Stream4->M1AR ,DMA1_Stream4->PAR);
p_igmon 1:530d6fb59a93 180 pc.printf("I2S CR2 = %4x \n\r" ,SPI2->CR2);
p_igmon 1:530d6fb59a93 181 pc.printf("I2S SR = %4x \n\r" ,SPI2->SR);
p_igmon 1:530d6fb59a93 182 pc.printf("I2S I2SCFGR = %4x \n\r" ,SPI2->I2SCFGR);
p_igmon 1:530d6fb59a93 183 pc.printf("I2S I2SPR = %4x \n\r" ,SPI2->I2SPR);
p_igmon 1:530d6fb59a93 184 pc.printf("RCC->PLLI2SCFGR = %4x \n\r" ,RCC->PLLI2SCFGR);
p_igmon 1:530d6fb59a93 185
p_igmon 1:530d6fb59a93 186 HAL_RCC_MCOConfig(uint32_t RCC_MCO2, RCC_MCO2SOURCE_PLLI2SCLK, RCC_MCODIV_5);
p_igmon 1:530d6fb59a93 187
p_igmon 0:0093b4cc5297 188 while(1) {
p_igmon 1:530d6fb59a93 189 wait_ms(500);
p_igmon 0:0093b4cc5297 190 }
p_igmon 0:0093b4cc5297 191 }
p_igmon 0:0093b4cc5297 192