Chau Vo / mbed-dev

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targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/startup_MK20D5.S@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* File: startup_MK20D5.s
<> 144:ef7eb2e8f9f7 2 * Purpose: startup file for Cortex-M4 devices. Should use with
<> 144:ef7eb2e8f9f7 3 * GCC for ARM Embedded Processors
<> 144:ef7eb2e8f9f7 4 * Version: V1.3
<> 144:ef7eb2e8f9f7 5 * Date: 08 Feb 2012
<> 144:ef7eb2e8f9f7 6 *
<> 144:ef7eb2e8f9f7 7 * Copyright (c) 2015, ARM Limited
<> 144:ef7eb2e8f9f7 8 * All rights reserved.
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Redistribution and use in source and binary forms, with or without
<> 144:ef7eb2e8f9f7 11 * modification, are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 12 * Redistributions of source code must retain the above copyright
<> 144:ef7eb2e8f9f7 13 notice, this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 14 * Redistributions in binary form must reproduce the above copyright
<> 144:ef7eb2e8f9f7 15 notice, this list of conditions and the following disclaimer in the
<> 144:ef7eb2e8f9f7 16 documentation and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 17 * Neither the name of the ARM Limited nor the
<> 144:ef7eb2e8f9f7 18 names of its contributors may be used to endorse or promote products
<> 144:ef7eb2e8f9f7 19 derived from this software without specific prior written permission.
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 24 * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
<> 144:ef7eb2e8f9f7 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
<> 144:ef7eb2e8f9f7 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 31 */
<> 144:ef7eb2e8f9f7 32 .syntax unified
<> 144:ef7eb2e8f9f7 33 .arch armv7-m
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 .section .stack
<> 144:ef7eb2e8f9f7 36 .align 3
<> 144:ef7eb2e8f9f7 37 #ifdef __STACK_SIZE
<> 144:ef7eb2e8f9f7 38 .equ Stack_Size, __STACK_SIZE
<> 144:ef7eb2e8f9f7 39 #else
<> 144:ef7eb2e8f9f7 40 .equ Stack_Size, 0x400
<> 144:ef7eb2e8f9f7 41 #endif
<> 144:ef7eb2e8f9f7 42 .globl __StackTop
<> 144:ef7eb2e8f9f7 43 .globl __StackLimit
<> 144:ef7eb2e8f9f7 44 __StackLimit:
<> 144:ef7eb2e8f9f7 45 .space Stack_Size
<> 144:ef7eb2e8f9f7 46 .size __StackLimit, . - __StackLimit
<> 144:ef7eb2e8f9f7 47 __StackTop:
<> 144:ef7eb2e8f9f7 48 .size __StackTop, . - __StackTop
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 .section .heap
<> 144:ef7eb2e8f9f7 51 .align 3
<> 144:ef7eb2e8f9f7 52 #ifdef __HEAP_SIZE
<> 144:ef7eb2e8f9f7 53 .equ Heap_Size, __HEAP_SIZE
<> 144:ef7eb2e8f9f7 54 #else
<> 144:ef7eb2e8f9f7 55 .equ Heap_Size, 0xC00
<> 144:ef7eb2e8f9f7 56 #endif
<> 144:ef7eb2e8f9f7 57 .globl __HeapBase
<> 144:ef7eb2e8f9f7 58 .globl __HeapLimit
<> 144:ef7eb2e8f9f7 59 __HeapBase:
<> 144:ef7eb2e8f9f7 60 .if Heap_Size
<> 144:ef7eb2e8f9f7 61 .space Heap_Size
<> 144:ef7eb2e8f9f7 62 .endif
<> 144:ef7eb2e8f9f7 63 .size __HeapBase, . - __HeapBase
<> 144:ef7eb2e8f9f7 64 __HeapLimit:
<> 144:ef7eb2e8f9f7 65 .size __HeapLimit, . - __HeapLimit
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 .section .isr_vector
<> 144:ef7eb2e8f9f7 68 .align 2
<> 144:ef7eb2e8f9f7 69 .globl __isr_vector
<> 144:ef7eb2e8f9f7 70 __isr_vector:
<> 144:ef7eb2e8f9f7 71 .long __StackTop /* Top of Stack */
<> 144:ef7eb2e8f9f7 72 .long Reset_Handler /* Reset Handler */
<> 144:ef7eb2e8f9f7 73 .long NMI_Handler /* NMI Handler */
<> 144:ef7eb2e8f9f7 74 .long HardFault_Handler /* Hard Fault Handler */
<> 144:ef7eb2e8f9f7 75 .long MemManage_Handler /* MPU Fault Handler */
<> 144:ef7eb2e8f9f7 76 .long BusFault_Handler /* Bus Fault Handler */
<> 144:ef7eb2e8f9f7 77 .long UsageFault_Handler /* Usage Fault Handler */
<> 144:ef7eb2e8f9f7 78 .long 0 /* Reserved */
<> 144:ef7eb2e8f9f7 79 .long 0 /* Reserved */
<> 144:ef7eb2e8f9f7 80 .long 0 /* Reserved */
<> 144:ef7eb2e8f9f7 81 .long 0 /* Reserved */
<> 144:ef7eb2e8f9f7 82 .long SVC_Handler /* SVCall Handler */
<> 144:ef7eb2e8f9f7 83 .long DebugMon_Handler /* Debug Monitor Handler */
<> 144:ef7eb2e8f9f7 84 .long 0 /* Reserved */
<> 144:ef7eb2e8f9f7 85 .long PendSV_Handler /* PendSV Handler */
<> 144:ef7eb2e8f9f7 86 .long SysTick_Handler /* SysTick Handler */
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 /* External interrupts */
<> 144:ef7eb2e8f9f7 89 .long DMA0_IRQHandler /* 0: Watchdog Timer */
<> 144:ef7eb2e8f9f7 90 .long DMA1_IRQHandler /* 1: Real Time Clock */
<> 144:ef7eb2e8f9f7 91 .long DMA2_IRQHandler /* 2: Timer0 / Timer1 */
<> 144:ef7eb2e8f9f7 92 .long DMA3_IRQHandler /* 3: Timer2 / Timer3 */
<> 144:ef7eb2e8f9f7 93 .long DMA_Error_IRQHandler /* 4: MCIa */
<> 144:ef7eb2e8f9f7 94 .long 0 /* 5: MCIb */
<> 144:ef7eb2e8f9f7 95 .long FTFL_IRQHandler /* 6: UART0 - DUT FPGA */
<> 144:ef7eb2e8f9f7 96 .long Read_Collision_IRQHandler /* 7: UART1 - DUT FPGA */
<> 144:ef7eb2e8f9f7 97 .long LVD_LVW_IRQHandler /* 8: UART2 - DUT FPGA */
<> 144:ef7eb2e8f9f7 98 .long LLW_IRQHandler /* 9: UART4 - not connected */
<> 144:ef7eb2e8f9f7 99 .long Watchdog_IRQHandler /* 10: AACI / AC97 */
<> 144:ef7eb2e8f9f7 100 .long I2C0_IRQHandler /* 11: CLCD Combined Interrupt */
<> 144:ef7eb2e8f9f7 101 .long SPI0_IRQHandler /* 12: Ethernet */
<> 144:ef7eb2e8f9f7 102 .long I2S0_Tx_IRQHandler /* 13: USB Device */
<> 144:ef7eb2e8f9f7 103 .long I2S0_Rx_IRQHandler /* 14: USB Host Controller */
<> 144:ef7eb2e8f9f7 104 .long UART0_LON_IRQHandler /* 15: Character LCD */
<> 144:ef7eb2e8f9f7 105 .long UART0_RX_TX_IRQHandler /* 16: Flexray */
<> 144:ef7eb2e8f9f7 106 .long UART0_ERR_IRQHandler /* 17: CAN */
<> 144:ef7eb2e8f9f7 107 .long UART1_RX_TX_IRQHandler /* 18: LIN */
<> 144:ef7eb2e8f9f7 108 .long UART1_ERR_IRQHandler /* 19: I2C ADC/DAC */
<> 144:ef7eb2e8f9f7 109 .long UART2_RX_TX_IRQHandler /* 20: Reserved */
<> 144:ef7eb2e8f9f7 110 .long UART2_ERR_IRQHandler /* 21: Reserved */
<> 144:ef7eb2e8f9f7 111 .long ADC0_IRQHandler /* 22: Reserved */
<> 144:ef7eb2e8f9f7 112 .long CMP0_IRQHandler /* 23: Reserved */
<> 144:ef7eb2e8f9f7 113 .long CMP1_IRQHandler /* 24: Reserved */
<> 144:ef7eb2e8f9f7 114 .long FTM0_IRQHandler /* 25: Reserved */
<> 144:ef7eb2e8f9f7 115 .long FTM1_IRQHandler /* 26: Reserved */
<> 144:ef7eb2e8f9f7 116 .long CMT_IRQHandler /* 27: Reserved */
<> 144:ef7eb2e8f9f7 117 .long RTC_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
<> 144:ef7eb2e8f9f7 118 .long RTC_Seconds_IRQHandler /* 29: Reserved - CPU FPGA */
<> 144:ef7eb2e8f9f7 119 .long PIT0_IRQHandler /* 30: UART3 - CPU FPGA */
<> 144:ef7eb2e8f9f7 120 .long PIT1_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
<> 144:ef7eb2e8f9f7 121 .long PIT2_IRQHandler
<> 144:ef7eb2e8f9f7 122 .long PIT3_IRQHandler
<> 144:ef7eb2e8f9f7 123 .long PDB0_IRQHandler
<> 144:ef7eb2e8f9f7 124 .long USB0_IRQHandler
<> 144:ef7eb2e8f9f7 125 .long USBDCD_IRQHandler
<> 144:ef7eb2e8f9f7 126 .long TSI0_IRQHandler
<> 144:ef7eb2e8f9f7 127 .long MCG_IRQHandler
<> 144:ef7eb2e8f9f7 128 .long LPTimer_IRQHandler
<> 144:ef7eb2e8f9f7 129 .long PORTA_IRQHandler
<> 144:ef7eb2e8f9f7 130 .long PORTB_IRQHandler
<> 144:ef7eb2e8f9f7 131 .long PORTC_IRQHandler
<> 144:ef7eb2e8f9f7 132 .long PORTD_IRQHandler
<> 144:ef7eb2e8f9f7 133 .long PORTE_IRQHandler
<> 144:ef7eb2e8f9f7 134 .long SWI_IRQHandler
<> 144:ef7eb2e8f9f7 135 .size __isr_vector, . - __isr_vector
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 .section .text.Reset_Handler
<> 144:ef7eb2e8f9f7 138 .thumb
<> 144:ef7eb2e8f9f7 139 .thumb_func
<> 144:ef7eb2e8f9f7 140 .align 2
<> 144:ef7eb2e8f9f7 141 .globl Reset_Handler
<> 144:ef7eb2e8f9f7 142 .type Reset_Handler, %function
<> 144:ef7eb2e8f9f7 143 Reset_Handler:
<> 144:ef7eb2e8f9f7 144 /* Loop to copy data from read only memory to RAM. The ranges
<> 144:ef7eb2e8f9f7 145 * of copy from/to are specified by following symbols evaluated in
<> 144:ef7eb2e8f9f7 146 * linker script.
<> 144:ef7eb2e8f9f7 147 * __etext: End of code section, i.e., begin of data sections to copy from.
<> 144:ef7eb2e8f9f7 148 * __data_start__/__data_end__: RAM address range that data should be
<> 144:ef7eb2e8f9f7 149 * copied to. Both must be aligned to 4 bytes boundary. */
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 ldr r1, =__etext
<> 144:ef7eb2e8f9f7 152 ldr r2, =__data_start__
<> 144:ef7eb2e8f9f7 153 ldr r3, =__data_end__
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 .Lflash_to_ram_loop:
<> 144:ef7eb2e8f9f7 156 cmp r2, r3
<> 144:ef7eb2e8f9f7 157 ittt lt
<> 144:ef7eb2e8f9f7 158 ldrlt r0, [r1], #4
<> 144:ef7eb2e8f9f7 159 strlt r0, [r2], #4
<> 144:ef7eb2e8f9f7 160 blt .Lflash_to_ram_loop
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 .Lflash_to_ram_loop_end:
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 ldr r0, =SystemInit
<> 144:ef7eb2e8f9f7 165 blx r0
<> 144:ef7eb2e8f9f7 166 ldr r0, =_start
<> 144:ef7eb2e8f9f7 167 bx r0
<> 144:ef7eb2e8f9f7 168 .pool
<> 144:ef7eb2e8f9f7 169 .size Reset_Handler, . - Reset_Handler
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 .text
<> 144:ef7eb2e8f9f7 172 /* Macro to define default handlers. Default handler
<> 144:ef7eb2e8f9f7 173 * will be weak symbol and just dead loops. They can be
<> 144:ef7eb2e8f9f7 174 * overwritten by other handlers */
<> 144:ef7eb2e8f9f7 175 .macro def_default_handler handler_name
<> 144:ef7eb2e8f9f7 176 .align 1
<> 144:ef7eb2e8f9f7 177 .thumb_func
<> 144:ef7eb2e8f9f7 178 .weak \handler_name
<> 144:ef7eb2e8f9f7 179 .type \handler_name, %function
<> 144:ef7eb2e8f9f7 180 \handler_name :
<> 144:ef7eb2e8f9f7 181 b .
<> 144:ef7eb2e8f9f7 182 .size \handler_name, . - \handler_name
<> 144:ef7eb2e8f9f7 183 .endm
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 def_default_handler NMI_Handler
<> 144:ef7eb2e8f9f7 186 def_default_handler HardFault_Handler
<> 144:ef7eb2e8f9f7 187 def_default_handler MemManage_Handler
<> 144:ef7eb2e8f9f7 188 def_default_handler BusFault_Handler
<> 144:ef7eb2e8f9f7 189 def_default_handler UsageFault_Handler
<> 144:ef7eb2e8f9f7 190 def_default_handler SVC_Handler
<> 144:ef7eb2e8f9f7 191 def_default_handler DebugMon_Handler
<> 144:ef7eb2e8f9f7 192 def_default_handler PendSV_Handler
<> 144:ef7eb2e8f9f7 193 def_default_handler SysTick_Handler
<> 144:ef7eb2e8f9f7 194 def_default_handler Default_Handler
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 .macro def_irq_default_handler handler_name
<> 144:ef7eb2e8f9f7 197 .weak \handler_name
<> 144:ef7eb2e8f9f7 198 .set \handler_name, Default_Handler
<> 144:ef7eb2e8f9f7 199 .endm
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 def_irq_default_handler DMA0_IRQHandler
<> 144:ef7eb2e8f9f7 202 def_irq_default_handler DMA1_IRQHandler
<> 144:ef7eb2e8f9f7 203 def_irq_default_handler DMA2_IRQHandler
<> 144:ef7eb2e8f9f7 204 def_irq_default_handler DMA3_IRQHandler
<> 144:ef7eb2e8f9f7 205 def_irq_default_handler DMA_Error_IRQHandler
<> 144:ef7eb2e8f9f7 206 def_irq_default_handler FTFL_IRQHandler
<> 144:ef7eb2e8f9f7 207 def_irq_default_handler Read_Collision_IRQHandler
<> 144:ef7eb2e8f9f7 208 def_irq_default_handler LVD_LVW_IRQHandler
<> 144:ef7eb2e8f9f7 209 def_irq_default_handler LLW_IRQHandler
<> 144:ef7eb2e8f9f7 210 def_irq_default_handler Watchdog_IRQHandler
<> 144:ef7eb2e8f9f7 211 def_irq_default_handler I2C0_IRQHandler
<> 144:ef7eb2e8f9f7 212 def_irq_default_handler SPI0_IRQHandler
<> 144:ef7eb2e8f9f7 213 def_irq_default_handler I2S0_Tx_IRQHandler
<> 144:ef7eb2e8f9f7 214 def_irq_default_handler I2S0_Rx_IRQHandler
<> 144:ef7eb2e8f9f7 215 def_irq_default_handler UART0_LON_IRQHandler
<> 144:ef7eb2e8f9f7 216 def_irq_default_handler UART0_RX_TX_IRQHandler
<> 144:ef7eb2e8f9f7 217 def_irq_default_handler UART0_ERR_IRQHandler
<> 144:ef7eb2e8f9f7 218 def_irq_default_handler UART1_RX_TX_IRQHandler
<> 144:ef7eb2e8f9f7 219 def_irq_default_handler UART1_ERR_IRQHandler
<> 144:ef7eb2e8f9f7 220 def_irq_default_handler UART2_RX_TX_IRQHandler
<> 144:ef7eb2e8f9f7 221 def_irq_default_handler UART2_ERR_IRQHandler
<> 144:ef7eb2e8f9f7 222 def_irq_default_handler ADC0_IRQHandler
<> 144:ef7eb2e8f9f7 223 def_irq_default_handler CMP0_IRQHandler
<> 144:ef7eb2e8f9f7 224 def_irq_default_handler CMP1_IRQHandler
<> 144:ef7eb2e8f9f7 225 def_irq_default_handler FTM0_IRQHandler
<> 144:ef7eb2e8f9f7 226 def_irq_default_handler FTM1_IRQHandler
<> 144:ef7eb2e8f9f7 227 def_irq_default_handler CMT_IRQHandler
<> 144:ef7eb2e8f9f7 228 def_irq_default_handler RTC_IRQHandler
<> 144:ef7eb2e8f9f7 229 def_irq_default_handler RTC_Seconds_IRQHandler
<> 144:ef7eb2e8f9f7 230 def_irq_default_handler PIT0_IRQHandler
<> 144:ef7eb2e8f9f7 231 def_irq_default_handler PIT1_IRQHandler
<> 144:ef7eb2e8f9f7 232 def_irq_default_handler PIT2_IRQHandler
<> 144:ef7eb2e8f9f7 233 def_irq_default_handler PIT3_IRQHandler
<> 144:ef7eb2e8f9f7 234 def_irq_default_handler PDB0_IRQHandler
<> 144:ef7eb2e8f9f7 235 def_irq_default_handler USB0_IRQHandler
<> 144:ef7eb2e8f9f7 236 def_irq_default_handler USBDCD_IRQHandler
<> 144:ef7eb2e8f9f7 237 def_irq_default_handler TSI0_IRQHandler
<> 144:ef7eb2e8f9f7 238 def_irq_default_handler MCG_IRQHandler
<> 144:ef7eb2e8f9f7 239 def_irq_default_handler LPTimer_IRQHandler
<> 144:ef7eb2e8f9f7 240 def_irq_default_handler PORTA_IRQHandler
<> 144:ef7eb2e8f9f7 241 def_irq_default_handler PORTB_IRQHandler
<> 144:ef7eb2e8f9f7 242 def_irq_default_handler PORTC_IRQHandler
<> 144:ef7eb2e8f9f7 243 def_irq_default_handler PORTD_IRQHandler
<> 144:ef7eb2e8f9f7 244 def_irq_default_handler PORTE_IRQHandler
<> 144:ef7eb2e8f9f7 245 def_irq_default_handler SWI_IRQHandler
<> 144:ef7eb2e8f9f7 246 def_irq_default_handler DEF_IRQHandler
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /* Flash protection region, placed at 0x400 */
<> 144:ef7eb2e8f9f7 249 .text
<> 144:ef7eb2e8f9f7 250 .thumb
<> 144:ef7eb2e8f9f7 251 .align 2
<> 144:ef7eb2e8f9f7 252 .section .kinetis_flash_config_field,"a",%progbits
<> 144:ef7eb2e8f9f7 253 kinetis_flash_config:
<> 144:ef7eb2e8f9f7 254 .long 0xffffffff
<> 144:ef7eb2e8f9f7 255 .long 0xffffffff
<> 144:ef7eb2e8f9f7 256 .long 0xffffffff
<> 144:ef7eb2e8f9f7 257 .long 0xfffffffe
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 .end