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targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l1xx_hal_adc.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.3
<> 144:ef7eb2e8f9f7 6 * @date 04-March-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file containing functions prototypes of ADC HAL library.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32L1xx_HAL_ADC_H
<> 144:ef7eb2e8f9f7 40 #define __STM32L1xx_HAL_ADC_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32l1xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32L1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup ADC
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /** @defgroup ADC_Exported_Types ADC Exported Types
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /**
<> 144:ef7eb2e8f9f7 63 * @brief Structure definition of ADC and regular group initialization
<> 144:ef7eb2e8f9f7 64 * @note Parameters of this structure are shared within 2 scopes:
<> 144:ef7eb2e8f9f7 65 * - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
<> 144:ef7eb2e8f9f7 66 * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
<> 144:ef7eb2e8f9f7 67 * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
<> 144:ef7eb2e8f9f7 68 * ADC state can be either:
<> 144:ef7eb2e8f9f7 69 * - For all parameters: ADC disabled
<> 144:ef7eb2e8f9f7 70 * - For all parameters except 'Resolution', 'ScanConvMode', 'LowPowerAutoWait', 'LowPowerAutoPowerOff', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
<> 144:ef7eb2e8f9f7 71 * - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
<> 144:ef7eb2e8f9f7 72 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
<> 144:ef7eb2e8f9f7 73 * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly).
<> 144:ef7eb2e8f9f7 74 */
<> 144:ef7eb2e8f9f7 75 typedef struct
<> 144:ef7eb2e8f9f7 76 {
<> 144:ef7eb2e8f9f7 77 uint32_t ClockPrescaler; /*!< Select ADC clock source (asynchronous clock derived from HSI RC oscillator) and clock prescaler.
<> 144:ef7eb2e8f9f7 78 This parameter can be a value of @ref ADC_ClockPrescaler
<> 144:ef7eb2e8f9f7 79 Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits,
<> 144:ef7eb2e8f9f7 80 AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
<> 144:ef7eb2e8f9f7 81 Note: HSI RC oscillator must be preliminarily enabled at RCC top level. */
<> 144:ef7eb2e8f9f7 82 uint32_t Resolution; /*!< Configures the ADC resolution.
<> 144:ef7eb2e8f9f7 83 This parameter can be a value of @ref ADC_Resolution */
<> 144:ef7eb2e8f9f7 84 uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
<> 144:ef7eb2e8f9f7 85 or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
<> 144:ef7eb2e8f9f7 86 This parameter can be a value of @ref ADC_Data_align */
<> 144:ef7eb2e8f9f7 87 uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
<> 144:ef7eb2e8f9f7 88 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
<> 144:ef7eb2e8f9f7 89 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
<> 144:ef7eb2e8f9f7 90 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
<> 144:ef7eb2e8f9f7 91 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
<> 144:ef7eb2e8f9f7 92 Scan direction is upward: from rank1 to rank 'n'.
<> 144:ef7eb2e8f9f7 93 This parameter can be a value of @ref ADC_Scan_mode */
<> 144:ef7eb2e8f9f7 94 uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
<> 144:ef7eb2e8f9f7 95 This parameter can be a value of @ref ADC_EOCSelection.
<> 144:ef7eb2e8f9f7 96 Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
<> 144:ef7eb2e8f9f7 97 Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
<> 144:ef7eb2e8f9f7 98 or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
<> 144:ef7eb2e8f9f7 99 Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
<> 144:ef7eb2e8f9f7 100 If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
<> 144:ef7eb2e8f9f7 101 uint32_t LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous
<> 144:ef7eb2e8f9f7 102 conversion (for regular group) or previous sequence (for injected group) has been treated by user software, using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue().
<> 144:ef7eb2e8f9f7 103 This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications.
<> 144:ef7eb2e8f9f7 104 This parameter can be a value of @ref ADC_LowPowerAutoWait.
<> 144:ef7eb2e8f9f7 105 Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer.
<> 144:ef7eb2e8f9f7 106 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed
<> 144:ef7eb2e8f9f7 107 and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...).
<> 144:ef7eb2e8f9f7 108 Note: ADC clock latency and some timing constraints depending on clock prescaler have to be taken into account: refer to reference manual (register ADC_CR2 bit DELS description). */
<> 144:ef7eb2e8f9f7 109 uint32_t LowPowerAutoPowerOff; /*!< Selects the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
<> 144:ef7eb2e8f9f7 110 This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait').
<> 144:ef7eb2e8f9f7 111 This parameter can be a value of @ref ADC_LowPowerAutoPowerOff. */
<> 144:ef7eb2e8f9f7 112 uint32_t ChannelsBank; /*!< Selects the ADC channels bank.
<> 144:ef7eb2e8f9f7 113 This parameter can be a value of @ref ADC_ChannelsBank.
<> 144:ef7eb2e8f9f7 114 Note: Banks availability depends on devices categories.
<> 144:ef7eb2e8f9f7 115 Note: To change bank selection on the fly, without going through execution of 'HAL_ADC_Init()', macro '__HAL_ADC_CHANNELS_BANK()' can be used directly. */
<> 144:ef7eb2e8f9f7 116 uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
<> 144:ef7eb2e8f9f7 117 after the selected trigger occurred (software start or external trigger).
<> 144:ef7eb2e8f9f7 118 This parameter can be set to ENABLE or DISABLE. */
<> 144:ef7eb2e8f9f7 119 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 144:ef7eb2e8f9f7 120 uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
<> 144:ef7eb2e8f9f7 121 To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
<> 144:ef7eb2e8f9f7 122 This parameter must be a number between Min_Data = 1 and Max_Data = 28. */
<> 144:ef7eb2e8f9f7 123 #else
<> 144:ef7eb2e8f9f7 124 uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
<> 144:ef7eb2e8f9f7 125 To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
<> 144:ef7eb2e8f9f7 126 This parameter must be a number between Min_Data = 1 and Max_Data = 27. */
<> 144:ef7eb2e8f9f7 127 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
<> 144:ef7eb2e8f9f7 128 uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
<> 144:ef7eb2e8f9f7 129 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
<> 144:ef7eb2e8f9f7 130 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
<> 144:ef7eb2e8f9f7 131 This parameter can be set to ENABLE or DISABLE. */
<> 144:ef7eb2e8f9f7 132 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
<> 144:ef7eb2e8f9f7 133 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
<> 144:ef7eb2e8f9f7 134 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
<> 144:ef7eb2e8f9f7 135 uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
<> 144:ef7eb2e8f9f7 136 If set to ADC_SOFTWARE_START, external triggers are disabled.
<> 144:ef7eb2e8f9f7 137 If set to external trigger source, triggering is on event rising edge by default.
<> 144:ef7eb2e8f9f7 138 This parameter can be a value of @ref ADC_External_trigger_source_Regular */
<> 144:ef7eb2e8f9f7 139 uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
<> 144:ef7eb2e8f9f7 140 If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
<> 144:ef7eb2e8f9f7 141 This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
<> 144:ef7eb2e8f9f7 142 uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
<> 144:ef7eb2e8f9f7 143 or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
<> 144:ef7eb2e8f9f7 144 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
<> 144:ef7eb2e8f9f7 145 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
<> 144:ef7eb2e8f9f7 146 This parameter can be set to ENABLE or DISABLE. */
<> 144:ef7eb2e8f9f7 147 }ADC_InitTypeDef;
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /**
<> 144:ef7eb2e8f9f7 150 * @brief Structure definition of ADC channel for regular group
<> 144:ef7eb2e8f9f7 151 * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
<> 144:ef7eb2e8f9f7 152 * ADC can be either disabled or enabled without conversion on going on regular group.
<> 144:ef7eb2e8f9f7 153 */
<> 144:ef7eb2e8f9f7 154 typedef struct
<> 144:ef7eb2e8f9f7 155 {
<> 144:ef7eb2e8f9f7 156 uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
<> 144:ef7eb2e8f9f7 157 This parameter can be a value of @ref ADC_channels
<> 144:ef7eb2e8f9f7 158 Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
<> 144:ef7eb2e8f9f7 159 Maximum number of channels by device category (without taking in account each device package constraints):
<> 144:ef7eb2e8f9f7 160 STM32L1 category 1, 2: 24 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 26.
<> 144:ef7eb2e8f9f7 161 STM32L1 category 3: 25 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 26, 1 additional channel in bank B. Note: OPAMP1 and OPAMP2 are connected internally but not increasing internal channels number: they are sharing ADC input with external channels ADC_IN3 and ADC_IN8.
<> 144:ef7eb2e8f9f7 162 STM32L1 category 4, 5: 40 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 31, 11 additional channels in bank B. Note: OPAMP1 and OPAMP2 are connected internally but not increasing internal channels number: they are sharing ADC input with external channels ADC_IN3 and ADC_IN8.
<> 144:ef7eb2e8f9f7 163 Note: In case of peripherals OPAMPx not used: 3 channels (3, 8, 13) can be configured as direct channels (fast channels). Refer to macro ' __HAL_ADC_CHANNEL_SPEED_FAST() '.
<> 144:ef7eb2e8f9f7 164 Note: In case of peripheral OPAMP3 and ADC channel OPAMP3 used (OPAMP3 available on STM32L1 devices Cat.4 only): the analog switch COMP1_SW1 must be closed. Refer to macro: ' __HAL_OPAMP_OPAMP3OUT_CONNECT_ADC_COMP1() '. */
<> 144:ef7eb2e8f9f7 165 uint32_t Rank; /*!< Specifies the rank in the regular group sequencer.
<> 144:ef7eb2e8f9f7 166 This parameter can be a value of @ref ADC_regular_rank
<> 144:ef7eb2e8f9f7 167 Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
<> 144:ef7eb2e8f9f7 168 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
<> 144:ef7eb2e8f9f7 169 Unit: ADC clock cycles
<> 144:ef7eb2e8f9f7 170 Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
<> 144:ef7eb2e8f9f7 171 This parameter can be a value of @ref ADC_sampling_times
<> 144:ef7eb2e8f9f7 172 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
<> 144:ef7eb2e8f9f7 173 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
<> 144:ef7eb2e8f9f7 174 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
<> 144:ef7eb2e8f9f7 175 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
<> 144:ef7eb2e8f9f7 176 Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
<> 144:ef7eb2e8f9f7 177 }ADC_ChannelConfTypeDef;
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /**
<> 144:ef7eb2e8f9f7 180 * @brief ADC Configuration analog watchdog definition
<> 144:ef7eb2e8f9f7 181 * @note The setting of these parameters with function is conditioned to ADC state.
<> 144:ef7eb2e8f9f7 182 * ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
<> 144:ef7eb2e8f9f7 183 */
<> 144:ef7eb2e8f9f7 184 typedef struct
<> 144:ef7eb2e8f9f7 185 {
<> 144:ef7eb2e8f9f7 186 uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
<> 144:ef7eb2e8f9f7 187 This parameter can be a value of @ref ADC_analog_watchdog_mode. */
<> 144:ef7eb2e8f9f7 188 uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
<> 144:ef7eb2e8f9f7 189 This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
<> 144:ef7eb2e8f9f7 190 This parameter can be a value of @ref ADC_channels. */
<> 144:ef7eb2e8f9f7 191 uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
<> 144:ef7eb2e8f9f7 192 This parameter can be set to ENABLE or DISABLE */
<> 144:ef7eb2e8f9f7 193 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
<> 144:ef7eb2e8f9f7 194 This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
<> 144:ef7eb2e8f9f7 195 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
<> 144:ef7eb2e8f9f7 196 This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
<> 144:ef7eb2e8f9f7 197 uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
<> 144:ef7eb2e8f9f7 198 }ADC_AnalogWDGConfTypeDef;
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 /**
<> 144:ef7eb2e8f9f7 201 * @brief HAL ADC state machine: ADC states definition (bitfields)
<> 144:ef7eb2e8f9f7 202 */
<> 144:ef7eb2e8f9f7 203 /* States of ADC global scope */
<> 144:ef7eb2e8f9f7 204 #define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */
<> 144:ef7eb2e8f9f7 205 #define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */
<> 144:ef7eb2e8f9f7 206 #define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy to internal process (initialization, calibration) */
<> 144:ef7eb2e8f9f7 207 #define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 /* States of ADC errors */
<> 144:ef7eb2e8f9f7 210 #define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */
<> 144:ef7eb2e8f9f7 211 #define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */
<> 144:ef7eb2e8f9f7 212 #define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /* States of ADC group regular */
<> 144:ef7eb2e8f9f7 215 #define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
<> 144:ef7eb2e8f9f7 216 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
<> 144:ef7eb2e8f9f7 217 #define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */
<> 144:ef7eb2e8f9f7 218 #define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Overrun occurrence */
<> 144:ef7eb2e8f9f7 219 #define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /*!< Not available on STM32L1 device: End Of Sampling flag raised */
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /* States of ADC group injected */
<> 144:ef7eb2e8f9f7 222 #define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
<> 144:ef7eb2e8f9f7 223 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
<> 144:ef7eb2e8f9f7 224 #define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Conversion data available on group injected */
<> 144:ef7eb2e8f9f7 225 #define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /*!< Not available on STM32L1 device: Injected queue overflow occurrence */
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /* States of ADC analog watchdogs */
<> 144:ef7eb2e8f9f7 228 #define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of analog watchdog 1 */
<> 144:ef7eb2e8f9f7 229 #define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Not available on STM32L1 device: Out-of-window occurrence of analog watchdog 2 */
<> 144:ef7eb2e8f9f7 230 #define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Not available on STM32L1 device: Out-of-window occurrence of analog watchdog 3 */
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /* States of ADC multi-mode */
<> 144:ef7eb2e8f9f7 233 #define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< Not available on STM32L1 device: ADC in multimode slave state, controlled by another ADC master ( */
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 /**
<> 144:ef7eb2e8f9f7 237 * @brief ADC handle Structure definition
<> 144:ef7eb2e8f9f7 238 */
<> 144:ef7eb2e8f9f7 239 typedef struct
<> 144:ef7eb2e8f9f7 240 {
<> 144:ef7eb2e8f9f7 241 ADC_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 ADC_InitTypeDef Init; /*!< ADC required parameters */
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 __IO uint32_t NbrOfConversionRank ; /*!< ADC conversion rank counter */
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 HAL_LockTypeDef Lock; /*!< ADC locking object */
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 __IO uint32_t ErrorCode; /*!< ADC Error code */
<> 144:ef7eb2e8f9f7 254 }ADC_HandleTypeDef;
<> 144:ef7eb2e8f9f7 255 /**
<> 144:ef7eb2e8f9f7 256 * @}
<> 144:ef7eb2e8f9f7 257 */
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /** @defgroup ADC_Exported_Constants ADC Exported Constants
<> 144:ef7eb2e8f9f7 264 * @{
<> 144:ef7eb2e8f9f7 265 */
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /** @defgroup ADC_Error_Code ADC Error Code
<> 144:ef7eb2e8f9f7 268 * @{
<> 144:ef7eb2e8f9f7 269 */
<> 144:ef7eb2e8f9f7 270 #define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */
<> 144:ef7eb2e8f9f7 271 #define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking,
<> 144:ef7eb2e8f9f7 272 enable/disable, erroneous state */
<> 144:ef7eb2e8f9f7 273 #define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< Overrun error */
<> 144:ef7eb2e8f9f7 274 #define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */
<> 144:ef7eb2e8f9f7 275 /**
<> 144:ef7eb2e8f9f7 276 * @}
<> 144:ef7eb2e8f9f7 277 */
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 /** @defgroup ADC_ClockPrescaler ADC ClockPrescaler
<> 144:ef7eb2e8f9f7 280 * @{
<> 144:ef7eb2e8f9f7 281 */
<> 144:ef7eb2e8f9f7 282 #define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /*!< ADC asynchronous clock derived from ADC dedicated HSI without prescaler */
<> 144:ef7eb2e8f9f7 283 #define ADC_CLOCK_ASYNC_DIV2 ((uint32_t)ADC_CCR_ADCPRE_0) /*!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 2 */
<> 144:ef7eb2e8f9f7 284 #define ADC_CLOCK_ASYNC_DIV4 ((uint32_t)ADC_CCR_ADCPRE_1) /*!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 4 */
<> 144:ef7eb2e8f9f7 285 /**
<> 144:ef7eb2e8f9f7 286 * @}
<> 144:ef7eb2e8f9f7 287 */
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /** @defgroup ADC_Resolution ADC Resolution
<> 144:ef7eb2e8f9f7 290 * @{
<> 144:ef7eb2e8f9f7 291 */
<> 144:ef7eb2e8f9f7 292 #define ADC_RESOLUTION_12B ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */
<> 144:ef7eb2e8f9f7 293 #define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0) /*!< ADC 10-bit resolution */
<> 144:ef7eb2e8f9f7 294 #define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1) /*!< ADC 8-bit resolution */
<> 144:ef7eb2e8f9f7 295 #define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES) /*!< ADC 6-bit resolution */
<> 144:ef7eb2e8f9f7 296 /**
<> 144:ef7eb2e8f9f7 297 * @}
<> 144:ef7eb2e8f9f7 298 */
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /** @defgroup ADC_Data_align ADC Data_align
<> 144:ef7eb2e8f9f7 301 * @{
<> 144:ef7eb2e8f9f7 302 */
<> 144:ef7eb2e8f9f7 303 #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 304 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
<> 144:ef7eb2e8f9f7 305 /**
<> 144:ef7eb2e8f9f7 306 * @}
<> 144:ef7eb2e8f9f7 307 */
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /** @defgroup ADC_Scan_mode ADC Scan mode
<> 144:ef7eb2e8f9f7 310 * @{
<> 144:ef7eb2e8f9f7 311 */
<> 144:ef7eb2e8f9f7 312 #define ADC_SCAN_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 313 #define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)
<> 144:ef7eb2e8f9f7 314 /**
<> 144:ef7eb2e8f9f7 315 * @}
<> 144:ef7eb2e8f9f7 316 */
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 /** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group
<> 144:ef7eb2e8f9f7 319 * @{
<> 144:ef7eb2e8f9f7 320 */
<> 144:ef7eb2e8f9f7 321 #define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 322 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
<> 144:ef7eb2e8f9f7 323 #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
<> 144:ef7eb2e8f9f7 324 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
<> 144:ef7eb2e8f9f7 325 /**
<> 144:ef7eb2e8f9f7 326 * @}
<> 144:ef7eb2e8f9f7 327 */
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /** @defgroup ADC_External_trigger_source_Regular ADC External trigger source Regular
<> 144:ef7eb2e8f9f7 330 * @{
<> 144:ef7eb2e8f9f7 331 */
<> 144:ef7eb2e8f9f7 332 /* List of external triggers with generic trigger name, sorted by trigger */
<> 144:ef7eb2e8f9f7 333 /* name: */
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 /* External triggers of regular group for ADC1 */
<> 144:ef7eb2e8f9f7 336 #define ADC_EXTERNALTRIGCONV_T2_CC3 ADC_EXTERNALTRIG_T2_CC3
<> 144:ef7eb2e8f9f7 337 #define ADC_EXTERNALTRIGCONV_T2_CC2 ADC_EXTERNALTRIG_T2_CC2
<> 144:ef7eb2e8f9f7 338 #define ADC_EXTERNALTRIGCONV_T2_TRGO ADC_EXTERNALTRIG_T2_TRGO
<> 144:ef7eb2e8f9f7 339 #define ADC_EXTERNALTRIGCONV_T3_CC1 ADC_EXTERNALTRIG_T3_CC1
<> 144:ef7eb2e8f9f7 340 #define ADC_EXTERNALTRIGCONV_T3_CC3 ADC_EXTERNALTRIG_T3_CC3
<> 144:ef7eb2e8f9f7 341 #define ADC_EXTERNALTRIGCONV_T3_TRGO ADC_EXTERNALTRIG_T3_TRGO
<> 144:ef7eb2e8f9f7 342 #define ADC_EXTERNALTRIGCONV_T4_CC4 ADC_EXTERNALTRIG_T4_CC4
<> 144:ef7eb2e8f9f7 343 #define ADC_EXTERNALTRIGCONV_T4_TRGO ADC_EXTERNALTRIG_T4_TRGO
<> 144:ef7eb2e8f9f7 344 #define ADC_EXTERNALTRIGCONV_T6_TRGO ADC_EXTERNALTRIG_T6_TRGO
<> 144:ef7eb2e8f9f7 345 #define ADC_EXTERNALTRIGCONV_T9_CC2 ADC_EXTERNALTRIG_T9_CC2
<> 144:ef7eb2e8f9f7 346 #define ADC_EXTERNALTRIGCONV_T9_TRGO ADC_EXTERNALTRIG_T9_TRGO
<> 144:ef7eb2e8f9f7 347 #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC_EXTERNALTRIG_EXT_IT11
<> 144:ef7eb2e8f9f7 348 #define ADC_SOFTWARE_START ((uint32_t)0x00000010)
<> 144:ef7eb2e8f9f7 349 /**
<> 144:ef7eb2e8f9f7 350 * @}
<> 144:ef7eb2e8f9f7 351 */
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 /** @defgroup ADC_EOCSelection ADC EOCSelection
<> 144:ef7eb2e8f9f7 354 * @{
<> 144:ef7eb2e8f9f7 355 */
<> 144:ef7eb2e8f9f7 356 #define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 357 #define ADC_EOC_SINGLE_CONV ((uint32_t)ADC_CR2_EOCS)
<> 144:ef7eb2e8f9f7 358 /**
<> 144:ef7eb2e8f9f7 359 * @}
<> 144:ef7eb2e8f9f7 360 */
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 /** @defgroup ADC_LowPowerAutoWait ADC LowPowerAutoWait
<> 144:ef7eb2e8f9f7 363 * @{
<> 144:ef7eb2e8f9f7 364 */
<> 144:ef7eb2e8f9f7 365 /*!< Note : For compatibility with other STM32 devices with ADC autowait */
<> 144:ef7eb2e8f9f7 366 /* feature limited to enable or disable settings: */
<> 144:ef7eb2e8f9f7 367 /* Setting "ADC_AUTOWAIT_UNTIL_DATA_READ" is equivalent to "ENABLE". */
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 #define ADC_AUTOWAIT_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 370 #define ADC_AUTOWAIT_UNTIL_DATA_READ ((uint32_t)( ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: infinite delay, until the result of previous conversion is read */
<> 144:ef7eb2e8f9f7 371 #define ADC_AUTOWAIT_7_APBCLOCKCYCLES ((uint32_t)( ADC_CR2_DELS_1 )) /*!< Insert a delay between ADC conversions: 7 APB clock cycles */
<> 144:ef7eb2e8f9f7 372 #define ADC_AUTOWAIT_15_APBCLOCKCYCLES ((uint32_t)( ADC_CR2_DELS_1 | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 15 APB clock cycles */
<> 144:ef7eb2e8f9f7 373 #define ADC_AUTOWAIT_31_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 )) /*!< Insert a delay between ADC conversions: 31 APB clock cycles */
<> 144:ef7eb2e8f9f7 374 #define ADC_AUTOWAIT_63_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 63 APB clock cycles */
<> 144:ef7eb2e8f9f7 375 #define ADC_AUTOWAIT_127_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 | ADC_CR2_DELS_1 )) /*!< Insert a delay between ADC conversions: 127 APB clock cycles */
<> 144:ef7eb2e8f9f7 376 #define ADC_AUTOWAIT_255_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 | ADC_CR2_DELS_1 | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 255 APB clock cycles */
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /**
<> 144:ef7eb2e8f9f7 379 * @}
<> 144:ef7eb2e8f9f7 380 */
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 /** @defgroup ADC_LowPowerAutoPowerOff ADC LowPowerAutoPowerOff
<> 144:ef7eb2e8f9f7 383 * @{
<> 144:ef7eb2e8f9f7 384 */
<> 144:ef7eb2e8f9f7 385 #define ADC_AUTOPOWEROFF_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 386 #define ADC_AUTOPOWEROFF_IDLE_PHASE ((uint32_t)ADC_CR1_PDI) /*!< ADC power off when ADC is not converting (idle phase) */
<> 144:ef7eb2e8f9f7 387 #define ADC_AUTOPOWEROFF_DELAY_PHASE ((uint32_t)ADC_CR1_PDD) /*!< ADC power off when a delay is inserted between conversions (see parameter ADC_LowPowerAutoWait) */
<> 144:ef7eb2e8f9f7 388 #define ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES ((uint32_t)(ADC_CR1_PDI | ADC_CR1_PDD)) /*!< ADC power off when ADC is not converting (idle phase) and when a delay is inserted between conversions */
<> 144:ef7eb2e8f9f7 389 /**
<> 144:ef7eb2e8f9f7 390 * @}
<> 144:ef7eb2e8f9f7 391 */
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 /** @defgroup ADC_ChannelsBank ADC ChannelsBank
<> 144:ef7eb2e8f9f7 395 * @{
<> 144:ef7eb2e8f9f7 396 */
<> 144:ef7eb2e8f9f7 397 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 144:ef7eb2e8f9f7 398 #define ADC_CHANNELS_BANK_A ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 399 #define ADC_CHANNELS_BANK_B ((uint32_t)ADC_CR2_CFG)
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 #define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A) || \
<> 144:ef7eb2e8f9f7 402 ((BANK) == ADC_CHANNELS_BANK_B) )
<> 144:ef7eb2e8f9f7 403 #else
<> 144:ef7eb2e8f9f7 404 #define ADC_CHANNELS_BANK_A ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 #define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A))
<> 144:ef7eb2e8f9f7 407 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
<> 144:ef7eb2e8f9f7 408 /**
<> 144:ef7eb2e8f9f7 409 * @}
<> 144:ef7eb2e8f9f7 410 */
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 /** @defgroup ADC_channels ADC channels
<> 144:ef7eb2e8f9f7 413 * @{
<> 144:ef7eb2e8f9f7 414 */
<> 144:ef7eb2e8f9f7 415 /* Note: Depending on devices, some channels may not be available on package */
<> 144:ef7eb2e8f9f7 416 /* pins. Refer to device datasheet for channels availability. */
<> 144:ef7eb2e8f9f7 417 #define ADC_CHANNEL_0 ((uint32_t)0x00000000) /* Channel different in bank A and bank B */
<> 144:ef7eb2e8f9f7 418 #define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
<> 144:ef7eb2e8f9f7 419 #define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */
<> 144:ef7eb2e8f9f7 420 #define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
<> 144:ef7eb2e8f9f7 421 #define ADC_CHANNEL_4 ((uint32_t)( ADC_SQR5_SQ1_2 )) /* Direct (fast) channel */
<> 144:ef7eb2e8f9f7 422 #define ADC_CHANNEL_5 ((uint32_t)( ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Direct (fast) channel */
<> 144:ef7eb2e8f9f7 423 #define ADC_CHANNEL_6 ((uint32_t)( ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */
<> 144:ef7eb2e8f9f7 424 #define ADC_CHANNEL_7 ((uint32_t)( ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
<> 144:ef7eb2e8f9f7 425 #define ADC_CHANNEL_8 ((uint32_t)( ADC_SQR5_SQ1_3 )) /* Channel different in bank A and bank B */
<> 144:ef7eb2e8f9f7 426 #define ADC_CHANNEL_9 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
<> 144:ef7eb2e8f9f7 427 #define ADC_CHANNEL_10 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */
<> 144:ef7eb2e8f9f7 428 #define ADC_CHANNEL_11 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
<> 144:ef7eb2e8f9f7 429 #define ADC_CHANNEL_12 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 )) /* Channel different in bank A and bank B */
<> 144:ef7eb2e8f9f7 430 #define ADC_CHANNEL_13 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
<> 144:ef7eb2e8f9f7 431 #define ADC_CHANNEL_14 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */
<> 144:ef7eb2e8f9f7 432 #define ADC_CHANNEL_15 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
<> 144:ef7eb2e8f9f7 433 #define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR5_SQ1_4 )) /* Channel common to both bank A and bank B */
<> 144:ef7eb2e8f9f7 434 #define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
<> 144:ef7eb2e8f9f7 435 #define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */
<> 144:ef7eb2e8f9f7 436 #define ADC_CHANNEL_19 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
<> 144:ef7eb2e8f9f7 437 #define ADC_CHANNEL_20 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_2 )) /* Channel common to both bank A and bank B */
<> 144:ef7eb2e8f9f7 438 #define ADC_CHANNEL_21 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
<> 144:ef7eb2e8f9f7 439 #define ADC_CHANNEL_22 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Direct (fast) channel */
<> 144:ef7eb2e8f9f7 440 #define ADC_CHANNEL_23 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Direct (fast) channel */
<> 144:ef7eb2e8f9f7 441 #define ADC_CHANNEL_24 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 )) /* Direct (fast) channel */
<> 144:ef7eb2e8f9f7 442 #define ADC_CHANNEL_25 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_0)) /* Direct (fast) channel */
<> 144:ef7eb2e8f9f7 443 #define ADC_CHANNEL_26 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */
<> 144:ef7eb2e8f9f7 444 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 144:ef7eb2e8f9f7 445 #define ADC_CHANNEL_27 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
<> 144:ef7eb2e8f9f7 446 #define ADC_CHANNEL_28 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 )) /* Channel common to both bank A and bank B */
<> 144:ef7eb2e8f9f7 447 #define ADC_CHANNEL_29 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
<> 144:ef7eb2e8f9f7 448 #define ADC_CHANNEL_30 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */
<> 144:ef7eb2e8f9f7 449 #define ADC_CHANNEL_31 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
<> 144:ef7eb2e8f9f7 450 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */
<> 144:ef7eb2e8f9f7 453 #define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */
<> 144:ef7eb2e8f9f7 454 #define ADC_CHANNEL_VCOMP ADC_CHANNEL_26 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 144:ef7eb2e8f9f7 457 #define ADC_CHANNEL_VOPAMP1 ADC_CHANNEL_3 /* Internal connection from OPAMP1 output to ADC switch matrix */
<> 144:ef7eb2e8f9f7 458 #define ADC_CHANNEL_VOPAMP2 ADC_CHANNEL_8 /* Internal connection from OPAMP2 output to ADC switch matrix */
<> 144:ef7eb2e8f9f7 459 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD)
<> 144:ef7eb2e8f9f7 460 #define ADC_CHANNEL_VOPAMP3 ADC_CHANNEL_13 /* Internal connection from OPAMP3 output to ADC switch matrix */
<> 144:ef7eb2e8f9f7 461 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD */
<> 144:ef7eb2e8f9f7 462 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
<> 144:ef7eb2e8f9f7 463 /**
<> 144:ef7eb2e8f9f7 464 * @}
<> 144:ef7eb2e8f9f7 465 */
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 /** @defgroup ADC_sampling_times ADC sampling times
<> 144:ef7eb2e8f9f7 468 * @{
<> 144:ef7eb2e8f9f7 469 */
<> 144:ef7eb2e8f9f7 470 #define ADC_SAMPLETIME_4CYCLES ((uint32_t)0x00000000) /*!< Sampling time 4 ADC clock cycles */
<> 144:ef7eb2e8f9f7 471 #define ADC_SAMPLETIME_9CYCLES ((uint32_t) ADC_SMPR3_SMP0_0) /*!< Sampling time 9 ADC clock cycles */
<> 144:ef7eb2e8f9f7 472 #define ADC_SAMPLETIME_16CYCLES ((uint32_t) ADC_SMPR3_SMP0_1) /*!< Sampling time 16 ADC clock cycles */
<> 144:ef7eb2e8f9f7 473 #define ADC_SAMPLETIME_24CYCLES ((uint32_t)(ADC_SMPR3_SMP0_1 | ADC_SMPR3_SMP0_0)) /*!< Sampling time 24 ADC clock cycles */
<> 144:ef7eb2e8f9f7 474 #define ADC_SAMPLETIME_48CYCLES ((uint32_t) ADC_SMPR3_SMP0_2) /*!< Sampling time 48 ADC clock cycles */
<> 144:ef7eb2e8f9f7 475 #define ADC_SAMPLETIME_96CYCLES ((uint32_t)(ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_0)) /*!< Sampling time 96 ADC clock cycles */
<> 144:ef7eb2e8f9f7 476 #define ADC_SAMPLETIME_192CYCLES ((uint32_t)(ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_1)) /*!< Sampling time 192 ADC clock cycles */
<> 144:ef7eb2e8f9f7 477 #define ADC_SAMPLETIME_384CYCLES ((uint32_t) ADC_SMPR3_SMP0) /*!< Sampling time 384 ADC clock cycles */
<> 144:ef7eb2e8f9f7 478 /**
<> 144:ef7eb2e8f9f7 479 * @}
<> 144:ef7eb2e8f9f7 480 */
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 /** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels
<> 144:ef7eb2e8f9f7 483 * @{
<> 144:ef7eb2e8f9f7 484 */
<> 144:ef7eb2e8f9f7 485 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2 \
<> 144:ef7eb2e8f9f7 486 (ADC_SMPR3_SMP9_2 | ADC_SMPR3_SMP8_2 | ADC_SMPR3_SMP7_2 | ADC_SMPR3_SMP6_2 | \
<> 144:ef7eb2e8f9f7 487 ADC_SMPR3_SMP5_2 | ADC_SMPR3_SMP4_2 | ADC_SMPR3_SMP3_2 | ADC_SMPR3_SMP2_2 | \
<> 144:ef7eb2e8f9f7 488 ADC_SMPR3_SMP1_2 | ADC_SMPR3_SMP0_2)
<> 144:ef7eb2e8f9f7 489 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \
<> 144:ef7eb2e8f9f7 490 (ADC_SMPR2_SMP19_2 | ADC_SMPR2_SMP18_2 | ADC_SMPR2_SMP17_2 | ADC_SMPR2_SMP16_2 | \
<> 144:ef7eb2e8f9f7 491 ADC_SMPR2_SMP15_2 | ADC_SMPR2_SMP14_2 | ADC_SMPR2_SMP13_2 | ADC_SMPR2_SMP12_2 | \
<> 144:ef7eb2e8f9f7 492 ADC_SMPR2_SMP11_2 | ADC_SMPR2_SMP10_2)
<> 144:ef7eb2e8f9f7 493 #if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
<> 144:ef7eb2e8f9f7 494 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
<> 144:ef7eb2e8f9f7 495 (ADC_SMPR1_SMP26_2 | ADC_SMPR1_SMP25_2 | ADC_SMPR1_SMP24_2 | ADC_SMPR1_SMP23_2 | \
<> 144:ef7eb2e8f9f7 496 ADC_SMPR1_SMP22_2 | ADC_SMPR1_SMP21_2 | ADC_SMPR1_SMP20_2)
<> 144:ef7eb2e8f9f7 497 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */
<> 144:ef7eb2e8f9f7 498 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 144:ef7eb2e8f9f7 499 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
<> 144:ef7eb2e8f9f7 500 (ADC_SMPR1_SMP29_2 | ADC_SMPR1_SMP28_2 | ADC_SMPR1_SMP27_2 | ADC_SMPR1_SMP26_2 | \
<> 144:ef7eb2e8f9f7 501 ADC_SMPR1_SMP25_2 | ADC_SMPR1_SMP24_2 | ADC_SMPR1_SMP23_2 | ADC_SMPR1_SMP22_2 | \
<> 144:ef7eb2e8f9f7 502 ADC_SMPR1_SMP21_2 | ADC_SMPR1_SMP20_2)
<> 144:ef7eb2e8f9f7 503 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT2 \
<> 144:ef7eb2e8f9f7 504 (ADC_SMPR0_SMP31_2 | ADC_SMPR0_SMP30_2 )
<> 144:ef7eb2e8f9f7 505 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT1 \
<> 144:ef7eb2e8f9f7 508 (ADC_SMPR3_SMP9_1 | ADC_SMPR3_SMP8_1 | ADC_SMPR3_SMP7_1 | ADC_SMPR3_SMP6_1 | \
<> 144:ef7eb2e8f9f7 509 ADC_SMPR3_SMP5_1 | ADC_SMPR3_SMP4_1 | ADC_SMPR3_SMP3_1 | ADC_SMPR3_SMP2_1 | \
<> 144:ef7eb2e8f9f7 510 ADC_SMPR3_SMP1_1 | ADC_SMPR3_SMP0_1)
<> 144:ef7eb2e8f9f7 511 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \
<> 144:ef7eb2e8f9f7 512 (ADC_SMPR2_SMP19_1 | ADC_SMPR2_SMP18_1 | ADC_SMPR2_SMP17_1 | ADC_SMPR2_SMP16_1 | \
<> 144:ef7eb2e8f9f7 513 ADC_SMPR2_SMP15_1 | ADC_SMPR2_SMP14_1 | ADC_SMPR2_SMP13_1 | ADC_SMPR2_SMP12_1 | \
<> 144:ef7eb2e8f9f7 514 ADC_SMPR2_SMP11_1 | ADC_SMPR2_SMP10_1)
<> 144:ef7eb2e8f9f7 515 #if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
<> 144:ef7eb2e8f9f7 516 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
<> 144:ef7eb2e8f9f7 517 (ADC_SMPR1_SMP26_1 | ADC_SMPR1_SMP25_1 | ADC_SMPR1_SMP24_1 | ADC_SMPR1_SMP23_1 | \
<> 144:ef7eb2e8f9f7 518 ADC_SMPR1_SMP22_1 | ADC_SMPR1_SMP21_1 | ADC_SMPR1_SMP20_1)
<> 144:ef7eb2e8f9f7 519 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */
<> 144:ef7eb2e8f9f7 520 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 144:ef7eb2e8f9f7 521 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
<> 144:ef7eb2e8f9f7 522 (ADC_SMPR1_SMP29_1 | ADC_SMPR1_SMP28_1 | ADC_SMPR1_SMP27_1 | ADC_SMPR1_SMP26_1 | \
<> 144:ef7eb2e8f9f7 523 ADC_SMPR1_SMP25_1 | ADC_SMPR1_SMP24_1 | ADC_SMPR1_SMP23_1 | ADC_SMPR1_SMP22_1 | \
<> 144:ef7eb2e8f9f7 524 ADC_SMPR1_SMP21_1 | ADC_SMPR1_SMP20_1)
<> 144:ef7eb2e8f9f7 525 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT1 \
<> 144:ef7eb2e8f9f7 526 (ADC_SMPR0_SMP31_1 | ADC_SMPR0_SMP30_1 )
<> 144:ef7eb2e8f9f7 527 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT0 \
<> 144:ef7eb2e8f9f7 530 (ADC_SMPR3_SMP9_0 | ADC_SMPR3_SMP8_0 | ADC_SMPR3_SMP7_0 | ADC_SMPR3_SMP6_0 | \
<> 144:ef7eb2e8f9f7 531 ADC_SMPR3_SMP5_0 | ADC_SMPR3_SMP4_0 | ADC_SMPR3_SMP3_0 | ADC_SMPR3_SMP2_0 | \
<> 144:ef7eb2e8f9f7 532 ADC_SMPR3_SMP1_0 | ADC_SMPR3_SMP0_0)
<> 144:ef7eb2e8f9f7 533 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \
<> 144:ef7eb2e8f9f7 534 (ADC_SMPR2_SMP19_0 | ADC_SMPR2_SMP18_0 | ADC_SMPR2_SMP17_0 | ADC_SMPR2_SMP16_0 | \
<> 144:ef7eb2e8f9f7 535 ADC_SMPR2_SMP15_0 | ADC_SMPR2_SMP14_0 | ADC_SMPR2_SMP13_0 | ADC_SMPR2_SMP12_0 | \
<> 144:ef7eb2e8f9f7 536 ADC_SMPR2_SMP11_0 | ADC_SMPR2_SMP10_0)
<> 144:ef7eb2e8f9f7 537 #if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
<> 144:ef7eb2e8f9f7 538 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
<> 144:ef7eb2e8f9f7 539 (ADC_SMPR1_SMP26_0 | ADC_SMPR1_SMP25_0 | ADC_SMPR1_SMP24_0 | ADC_SMPR1_SMP23_0 | \
<> 144:ef7eb2e8f9f7 540 ADC_SMPR1_SMP22_0 | ADC_SMPR1_SMP21_0 | ADC_SMPR1_SMP20_0)
<> 144:ef7eb2e8f9f7 541 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */
<> 144:ef7eb2e8f9f7 542 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 144:ef7eb2e8f9f7 543 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
<> 144:ef7eb2e8f9f7 544 (ADC_SMPR1_SMP29_0 | ADC_SMPR1_SMP28_0 | ADC_SMPR1_SMP27_0 | ADC_SMPR1_SMP26_0 | \
<> 144:ef7eb2e8f9f7 545 ADC_SMPR1_SMP25_0 | ADC_SMPR1_SMP24_0 | ADC_SMPR1_SMP23_0 | ADC_SMPR1_SMP22_0 | \
<> 144:ef7eb2e8f9f7 546 ADC_SMPR1_SMP21_0 | ADC_SMPR1_SMP20_0)
<> 144:ef7eb2e8f9f7 547 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT0 \
<> 144:ef7eb2e8f9f7 548 (ADC_SMPR0_SMP31_0 | ADC_SMPR0_SMP30_0 )
<> 144:ef7eb2e8f9f7 549 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
<> 144:ef7eb2e8f9f7 550 /**
<> 144:ef7eb2e8f9f7 551 * @}
<> 144:ef7eb2e8f9f7 552 */
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 /** @defgroup ADC_regular_rank ADC rank into regular group
<> 144:ef7eb2e8f9f7 555 * @{
<> 144:ef7eb2e8f9f7 556 */
<> 144:ef7eb2e8f9f7 557 #define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001)
<> 144:ef7eb2e8f9f7 558 #define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002)
<> 144:ef7eb2e8f9f7 559 #define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003)
<> 144:ef7eb2e8f9f7 560 #define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004)
<> 144:ef7eb2e8f9f7 561 #define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005)
<> 144:ef7eb2e8f9f7 562 #define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006)
<> 144:ef7eb2e8f9f7 563 #define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007)
<> 144:ef7eb2e8f9f7 564 #define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008)
<> 144:ef7eb2e8f9f7 565 #define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009)
<> 144:ef7eb2e8f9f7 566 #define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A)
<> 144:ef7eb2e8f9f7 567 #define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B)
<> 144:ef7eb2e8f9f7 568 #define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C)
<> 144:ef7eb2e8f9f7 569 #define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D)
<> 144:ef7eb2e8f9f7 570 #define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E)
<> 144:ef7eb2e8f9f7 571 #define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F)
<> 144:ef7eb2e8f9f7 572 #define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010)
<> 144:ef7eb2e8f9f7 573 #define ADC_REGULAR_RANK_17 ((uint32_t)0x00000011)
<> 144:ef7eb2e8f9f7 574 #define ADC_REGULAR_RANK_18 ((uint32_t)0x00000012)
<> 144:ef7eb2e8f9f7 575 #define ADC_REGULAR_RANK_19 ((uint32_t)0x00000013)
<> 144:ef7eb2e8f9f7 576 #define ADC_REGULAR_RANK_20 ((uint32_t)0x00000014)
<> 144:ef7eb2e8f9f7 577 #define ADC_REGULAR_RANK_21 ((uint32_t)0x00000015)
<> 144:ef7eb2e8f9f7 578 #define ADC_REGULAR_RANK_22 ((uint32_t)0x00000016)
<> 144:ef7eb2e8f9f7 579 #define ADC_REGULAR_RANK_23 ((uint32_t)0x00000017)
<> 144:ef7eb2e8f9f7 580 #define ADC_REGULAR_RANK_24 ((uint32_t)0x00000018)
<> 144:ef7eb2e8f9f7 581 #define ADC_REGULAR_RANK_25 ((uint32_t)0x00000019)
<> 144:ef7eb2e8f9f7 582 #define ADC_REGULAR_RANK_26 ((uint32_t)0x0000001A)
<> 144:ef7eb2e8f9f7 583 #define ADC_REGULAR_RANK_27 ((uint32_t)0x0000001B)
<> 144:ef7eb2e8f9f7 584 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 144:ef7eb2e8f9f7 585 #define ADC_REGULAR_RANK_28 ((uint32_t)0x0000001C)
<> 144:ef7eb2e8f9f7 586 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
<> 144:ef7eb2e8f9f7 587 /**
<> 144:ef7eb2e8f9f7 588 * @}
<> 144:ef7eb2e8f9f7 589 */
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
<> 144:ef7eb2e8f9f7 592 * @{
<> 144:ef7eb2e8f9f7 593 */
<> 144:ef7eb2e8f9f7 594 #define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 595 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
<> 144:ef7eb2e8f9f7 596 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
<> 144:ef7eb2e8f9f7 597 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
<> 144:ef7eb2e8f9f7 598 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CR1_AWDEN)
<> 144:ef7eb2e8f9f7 599 #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CR1_JAWDEN)
<> 144:ef7eb2e8f9f7 600 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
<> 144:ef7eb2e8f9f7 601 /**
<> 144:ef7eb2e8f9f7 602 * @}
<> 144:ef7eb2e8f9f7 603 */
<> 144:ef7eb2e8f9f7 604
<> 144:ef7eb2e8f9f7 605 /** @defgroup ADC_conversion_group ADC conversion group
<> 144:ef7eb2e8f9f7 606 * @{
<> 144:ef7eb2e8f9f7 607 */
<> 144:ef7eb2e8f9f7 608 #define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC))
<> 144:ef7eb2e8f9f7 609 #define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC))
<> 144:ef7eb2e8f9f7 610 #define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC))
<> 144:ef7eb2e8f9f7 611 /**
<> 144:ef7eb2e8f9f7 612 * @}
<> 144:ef7eb2e8f9f7 613 */
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615 /** @defgroup ADC_Event_type ADC Event type
<> 144:ef7eb2e8f9f7 616 * @{
<> 144:ef7eb2e8f9f7 617 */
<> 144:ef7eb2e8f9f7 618 #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */
<> 144:ef7eb2e8f9f7 619 #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */
<> 144:ef7eb2e8f9f7 620 /**
<> 144:ef7eb2e8f9f7 621 * @}
<> 144:ef7eb2e8f9f7 622 */
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 /** @defgroup ADC_interrupts_definition ADC interrupts definition
<> 144:ef7eb2e8f9f7 625 * @{
<> 144:ef7eb2e8f9f7 626 */
<> 144:ef7eb2e8f9f7 627 #define ADC_IT_EOC ADC_CR1_EOCIE /*!< ADC End of Regular Conversion interrupt source */
<> 144:ef7eb2e8f9f7 628 #define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */
<> 144:ef7eb2e8f9f7 629 #define ADC_IT_AWD ADC_CR1_AWDIE /*!< ADC Analog watchdog interrupt source */
<> 144:ef7eb2e8f9f7 630 #define ADC_IT_OVR ADC_CR1_OVRIE /*!< ADC overrun interrupt source */
<> 144:ef7eb2e8f9f7 631 /**
<> 144:ef7eb2e8f9f7 632 * @}
<> 144:ef7eb2e8f9f7 633 */
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 /** @defgroup ADC_flags_definition ADC flags definition
<> 144:ef7eb2e8f9f7 636 * @{
<> 144:ef7eb2e8f9f7 637 */
<> 144:ef7eb2e8f9f7 638 #define ADC_FLAG_AWD ADC_SR_AWD /*!< ADC Analog watchdog flag */
<> 144:ef7eb2e8f9f7 639 #define ADC_FLAG_EOC ADC_SR_EOC /*!< ADC End of Regular conversion flag */
<> 144:ef7eb2e8f9f7 640 #define ADC_FLAG_JEOC ADC_SR_JEOC /*!< ADC End of Injected conversion flag */
<> 144:ef7eb2e8f9f7 641 #define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */
<> 144:ef7eb2e8f9f7 642 #define ADC_FLAG_STRT ADC_SR_STRT /*!< ADC Regular group start flag */
<> 144:ef7eb2e8f9f7 643 #define ADC_FLAG_OVR ADC_SR_OVR /*!< ADC overrun flag */
<> 144:ef7eb2e8f9f7 644 #define ADC_FLAG_ADONS ADC_SR_ADONS /*!< ADC ready status flag */
<> 144:ef7eb2e8f9f7 645 #define ADC_FLAG_RCNR ADC_SR_RCNR /*!< ADC Regular group ready status flag */
<> 144:ef7eb2e8f9f7 646 #define ADC_FLAG_JCNR ADC_SR_JCNR /*!< ADC Injected group ready status flag */
<> 144:ef7eb2e8f9f7 647 /**
<> 144:ef7eb2e8f9f7 648 * @}
<> 144:ef7eb2e8f9f7 649 */
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651 /**
<> 144:ef7eb2e8f9f7 652 * @}
<> 144:ef7eb2e8f9f7 653 */
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 /** @addtogroup ADC_Private_Constants ADC Private Constants
<> 144:ef7eb2e8f9f7 659 * @{
<> 144:ef7eb2e8f9f7 660 */
<> 144:ef7eb2e8f9f7 661
<> 144:ef7eb2e8f9f7 662 /* List of external triggers of regular group for ADC1: */
<> 144:ef7eb2e8f9f7 663 /* (used internally by HAL driver. To not use into HAL structure parameters) */
<> 144:ef7eb2e8f9f7 664
<> 144:ef7eb2e8f9f7 665 /* External triggers of regular group for ADC1 */
<> 144:ef7eb2e8f9f7 666 #define ADC_EXTERNALTRIG_T9_CC2 ((uint32_t) 0x00000000)
<> 144:ef7eb2e8f9f7 667 #define ADC_EXTERNALTRIG_T9_TRGO ((uint32_t)( ADC_CR2_EXTSEL_0))
<> 144:ef7eb2e8f9f7 668 #define ADC_EXTERNALTRIG_T2_CC3 ((uint32_t)( ADC_CR2_EXTSEL_1 ))
<> 144:ef7eb2e8f9f7 669 #define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)( ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
<> 144:ef7eb2e8f9f7 670 #define ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)( ADC_CR2_EXTSEL_2 ))
<> 144:ef7eb2e8f9f7 671 #define ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)( ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
<> 144:ef7eb2e8f9f7 672 #define ADC_EXTERNALTRIG_T2_TRGO ((uint32_t)( ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 ))
<> 144:ef7eb2e8f9f7 673 #define ADC_EXTERNALTRIG_T3_CC1 ((uint32_t)( ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
<> 144:ef7eb2e8f9f7 674 #define ADC_EXTERNALTRIG_T3_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 ))
<> 144:ef7eb2e8f9f7 675 #define ADC_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
<> 144:ef7eb2e8f9f7 676 #define ADC_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 ))
<> 144:ef7eb2e8f9f7 677 #define ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
<> 144:ef7eb2e8f9f7 678
<> 144:ef7eb2e8f9f7 679 /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
<> 144:ef7eb2e8f9f7 680 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD | \
<> 144:ef7eb2e8f9f7 681 ADC_FLAG_OVR)
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683 /**
<> 144:ef7eb2e8f9f7 684 * @}
<> 144:ef7eb2e8f9f7 685 */
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687
<> 144:ef7eb2e8f9f7 688 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 /** @defgroup ADC_Exported_Macros ADC Exported Macros
<> 144:ef7eb2e8f9f7 691 * @{
<> 144:ef7eb2e8f9f7 692 */
<> 144:ef7eb2e8f9f7 693 /* Macro for internal HAL driver usage, and possibly can be used into code of */
<> 144:ef7eb2e8f9f7 694 /* final user. */
<> 144:ef7eb2e8f9f7 695
<> 144:ef7eb2e8f9f7 696 /**
<> 144:ef7eb2e8f9f7 697 * @brief Enable the ADC peripheral
<> 144:ef7eb2e8f9f7 698 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 699 * @retval None
<> 144:ef7eb2e8f9f7 700 */
<> 144:ef7eb2e8f9f7 701 #define __HAL_ADC_ENABLE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 702 (__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON
<> 144:ef7eb2e8f9f7 703
<> 144:ef7eb2e8f9f7 704 /**
<> 144:ef7eb2e8f9f7 705 * @brief Disable the ADC peripheral
<> 144:ef7eb2e8f9f7 706 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 707 * @retval None
<> 144:ef7eb2e8f9f7 708 */
<> 144:ef7eb2e8f9f7 709 #define __HAL_ADC_DISABLE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 710 (__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON
<> 144:ef7eb2e8f9f7 711
<> 144:ef7eb2e8f9f7 712 /**
<> 144:ef7eb2e8f9f7 713 * @brief Enable the ADC end of conversion interrupt.
<> 144:ef7eb2e8f9f7 714 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 715 * @param __INTERRUPT__: ADC Interrupt
<> 144:ef7eb2e8f9f7 716 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 717 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
<> 144:ef7eb2e8f9f7 718 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
<> 144:ef7eb2e8f9f7 719 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
<> 144:ef7eb2e8f9f7 720 * @arg ADC_IT_OVR: ADC overrun interrupt source
<> 144:ef7eb2e8f9f7 721 * @retval None
<> 144:ef7eb2e8f9f7 722 */
<> 144:ef7eb2e8f9f7 723 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
<> 144:ef7eb2e8f9f7 724 (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 725
<> 144:ef7eb2e8f9f7 726 /**
<> 144:ef7eb2e8f9f7 727 * @brief Disable the ADC end of conversion interrupt.
<> 144:ef7eb2e8f9f7 728 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 729 * @param __INTERRUPT__: ADC Interrupt
<> 144:ef7eb2e8f9f7 730 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 731 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
<> 144:ef7eb2e8f9f7 732 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
<> 144:ef7eb2e8f9f7 733 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
<> 144:ef7eb2e8f9f7 734 * @arg ADC_IT_OVR: ADC overrun interrupt source
<> 144:ef7eb2e8f9f7 735 * @retval None
<> 144:ef7eb2e8f9f7 736 */
<> 144:ef7eb2e8f9f7 737 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
<> 144:ef7eb2e8f9f7 738 (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 739
<> 144:ef7eb2e8f9f7 740 /** @brief Checks if the specified ADC interrupt source is enabled or disabled.
<> 144:ef7eb2e8f9f7 741 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 742 * @param __INTERRUPT__: ADC interrupt source to check
<> 144:ef7eb2e8f9f7 743 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 744 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
<> 144:ef7eb2e8f9f7 745 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
<> 144:ef7eb2e8f9f7 746 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
<> 144:ef7eb2e8f9f7 747 * @arg ADC_IT_OVR: ADC overrun interrupt source
<> 144:ef7eb2e8f9f7 748 * @retval State of interruption (SET or RESET)
<> 144:ef7eb2e8f9f7 749 */
<> 144:ef7eb2e8f9f7 750 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
<> 144:ef7eb2e8f9f7 751 (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753 /**
<> 144:ef7eb2e8f9f7 754 * @brief Get the selected ADC's flag status.
<> 144:ef7eb2e8f9f7 755 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 756 * @param __FLAG__: ADC flag
<> 144:ef7eb2e8f9f7 757 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 758 * @arg ADC_FLAG_STRT: ADC Regular group start flag
<> 144:ef7eb2e8f9f7 759 * @arg ADC_FLAG_JSTRT: ADC Injected group start flag
<> 144:ef7eb2e8f9f7 760 * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
<> 144:ef7eb2e8f9f7 761 * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
<> 144:ef7eb2e8f9f7 762 * @arg ADC_FLAG_AWD: ADC Analog watchdog flag
<> 144:ef7eb2e8f9f7 763 * @arg ADC_FLAG_OVR: ADC overrun flag
<> 144:ef7eb2e8f9f7 764 * @arg ADC_FLAG_ADONS: ADC ready status flag
<> 144:ef7eb2e8f9f7 765 * @arg ADC_FLAG_RCNR: ADC Regular group ready status flag
<> 144:ef7eb2e8f9f7 766 * @arg ADC_FLAG_JCNR: ADC Injected group ready status flag
<> 144:ef7eb2e8f9f7 767 * @retval None
<> 144:ef7eb2e8f9f7 768 */
<> 144:ef7eb2e8f9f7 769 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
<> 144:ef7eb2e8f9f7 770 ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 771
<> 144:ef7eb2e8f9f7 772 /**
<> 144:ef7eb2e8f9f7 773 * @brief Clear the ADC's pending flags
<> 144:ef7eb2e8f9f7 774 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 775 * @param __FLAG__: ADC flag
<> 144:ef7eb2e8f9f7 776 * @arg ADC_FLAG_STRT: ADC Regular group start flag
<> 144:ef7eb2e8f9f7 777 * @arg ADC_FLAG_JSTRT: ADC Injected group start flag
<> 144:ef7eb2e8f9f7 778 * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
<> 144:ef7eb2e8f9f7 779 * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
<> 144:ef7eb2e8f9f7 780 * @arg ADC_FLAG_AWD: ADC Analog watchdog flag
<> 144:ef7eb2e8f9f7 781 * @arg ADC_FLAG_OVR: ADC overrun flag
<> 144:ef7eb2e8f9f7 782 * @arg ADC_FLAG_ADONS: ADC ready status flag
<> 144:ef7eb2e8f9f7 783 * @arg ADC_FLAG_RCNR: ADC Regular group ready status flag
<> 144:ef7eb2e8f9f7 784 * @arg ADC_FLAG_JCNR: ADC Injected group ready status flag
<> 144:ef7eb2e8f9f7 785 * @retval None
<> 144:ef7eb2e8f9f7 786 */
<> 144:ef7eb2e8f9f7 787 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
<> 144:ef7eb2e8f9f7 788 (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
<> 144:ef7eb2e8f9f7 789
<> 144:ef7eb2e8f9f7 790 /** @brief Reset ADC handle state
<> 144:ef7eb2e8f9f7 791 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 792 * @retval None
<> 144:ef7eb2e8f9f7 793 */
<> 144:ef7eb2e8f9f7 794 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 795 ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
<> 144:ef7eb2e8f9f7 796
<> 144:ef7eb2e8f9f7 797 /**
<> 144:ef7eb2e8f9f7 798 * @}
<> 144:ef7eb2e8f9f7 799 */
<> 144:ef7eb2e8f9f7 800
<> 144:ef7eb2e8f9f7 801 /* Private macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 802
<> 144:ef7eb2e8f9f7 803 /** @defgroup ADC_Private_Macros ADC Private Macros
<> 144:ef7eb2e8f9f7 804 * @{
<> 144:ef7eb2e8f9f7 805 */
<> 144:ef7eb2e8f9f7 806 /* Macro reserved for internal HAL driver usage, not intended to be used in */
<> 144:ef7eb2e8f9f7 807 /* code of final user. */
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809 /**
<> 144:ef7eb2e8f9f7 810 * @brief Verification of ADC state: enabled or disabled
<> 144:ef7eb2e8f9f7 811 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 812 * @retval SET (ADC enabled) or RESET (ADC disabled)
<> 144:ef7eb2e8f9f7 813 */
<> 144:ef7eb2e8f9f7 814 #define ADC_IS_ENABLE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 815 ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \
<> 144:ef7eb2e8f9f7 816 ) ? SET : RESET)
<> 144:ef7eb2e8f9f7 817
<> 144:ef7eb2e8f9f7 818 /**
<> 144:ef7eb2e8f9f7 819 * @brief Test if conversion trigger of regular group is software start
<> 144:ef7eb2e8f9f7 820 * or external trigger.
<> 144:ef7eb2e8f9f7 821 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 822 * @retval SET (software start) or RESET (external trigger)
<> 144:ef7eb2e8f9f7 823 */
<> 144:ef7eb2e8f9f7 824 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
<> 144:ef7eb2e8f9f7 825 (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
<> 144:ef7eb2e8f9f7 826
<> 144:ef7eb2e8f9f7 827 /**
<> 144:ef7eb2e8f9f7 828 * @brief Test if conversion trigger of injected group is software start
<> 144:ef7eb2e8f9f7 829 * or external trigger.
<> 144:ef7eb2e8f9f7 830 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 831 * @retval SET (software start) or RESET (external trigger)
<> 144:ef7eb2e8f9f7 832 */
<> 144:ef7eb2e8f9f7 833 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
<> 144:ef7eb2e8f9f7 834 (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 /**
<> 144:ef7eb2e8f9f7 837 * @brief Simultaneously clears and sets specific bits of the handle State
<> 144:ef7eb2e8f9f7 838 * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
<> 144:ef7eb2e8f9f7 839 * the first parameter is the ADC handle State, the second parameter is the
<> 144:ef7eb2e8f9f7 840 * bit field to clear, the third and last parameter is the bit field to set.
<> 144:ef7eb2e8f9f7 841 * @retval None
<> 144:ef7eb2e8f9f7 842 */
<> 144:ef7eb2e8f9f7 843 #define ADC_STATE_CLR_SET MODIFY_REG
<> 144:ef7eb2e8f9f7 844
<> 144:ef7eb2e8f9f7 845 /**
<> 144:ef7eb2e8f9f7 846 * @brief Clear ADC error code (set it to error code: "no error")
<> 144:ef7eb2e8f9f7 847 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 848 * @retval None
<> 144:ef7eb2e8f9f7 849 */
<> 144:ef7eb2e8f9f7 850 #define ADC_CLEAR_ERRORCODE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 851 ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
<> 144:ef7eb2e8f9f7 852
<> 144:ef7eb2e8f9f7 853 /**
<> 144:ef7eb2e8f9f7 854 * @brief Set ADC number of ranks into regular channel sequence length.
<> 144:ef7eb2e8f9f7 855 * @param _NbrOfConversion_: Regular channel sequence length
<> 144:ef7eb2e8f9f7 856 * @retval None
<> 144:ef7eb2e8f9f7 857 */
<> 144:ef7eb2e8f9f7 858 #define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \
<> 144:ef7eb2e8f9f7 859 (((_NbrOfConversion_) - (uint8_t)1) << POSITION_VAL(ADC_SQR1_L))
<> 144:ef7eb2e8f9f7 860
<> 144:ef7eb2e8f9f7 861 /**
<> 144:ef7eb2e8f9f7 862 * @brief Set the ADC's sample time for channel numbers between 10 and 18.
<> 144:ef7eb2e8f9f7 863 * @param _SAMPLETIME_: Sample time parameter.
<> 144:ef7eb2e8f9f7 864 * @param _CHANNELNB_: Channel number.
<> 144:ef7eb2e8f9f7 865 * @retval None
<> 144:ef7eb2e8f9f7 866 */
<> 144:ef7eb2e8f9f7 867 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \
<> 144:ef7eb2e8f9f7 868 ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10)))
<> 144:ef7eb2e8f9f7 869
<> 144:ef7eb2e8f9f7 870 /**
<> 144:ef7eb2e8f9f7 871 * @brief Set the ADC's sample time for channel numbers between 0 and 9.
<> 144:ef7eb2e8f9f7 872 * @param _SAMPLETIME_: Sample time parameter.
<> 144:ef7eb2e8f9f7 873 * @param _CHANNELNB_: Channel number.
<> 144:ef7eb2e8f9f7 874 * @retval None
<> 144:ef7eb2e8f9f7 875 */
<> 144:ef7eb2e8f9f7 876 #define ADC_SMPR3(_SAMPLETIME_, _CHANNELNB_) \
<> 144:ef7eb2e8f9f7 877 ((_SAMPLETIME_) << (3 * (_CHANNELNB_)))
<> 144:ef7eb2e8f9f7 878
<> 144:ef7eb2e8f9f7 879 /**
<> 144:ef7eb2e8f9f7 880 * @brief Set the selected regular channel rank for rank between 1 and 6.
<> 144:ef7eb2e8f9f7 881 * @param _CHANNELNB_: Channel number.
<> 144:ef7eb2e8f9f7 882 * @param _RANKNB_: Rank number.
<> 144:ef7eb2e8f9f7 883 * @retval None
<> 144:ef7eb2e8f9f7 884 */
<> 144:ef7eb2e8f9f7 885 #define ADC_SQR5_RK(_CHANNELNB_, _RANKNB_) \
<> 144:ef7eb2e8f9f7 886 ((_CHANNELNB_) << (5 * ((_RANKNB_) - 1)))
<> 144:ef7eb2e8f9f7 887
<> 144:ef7eb2e8f9f7 888 /**
<> 144:ef7eb2e8f9f7 889 * @brief Set the selected regular channel rank for rank between 7 and 12.
<> 144:ef7eb2e8f9f7 890 * @param _CHANNELNB_: Channel number.
<> 144:ef7eb2e8f9f7 891 * @param _RANKNB_: Rank number.
<> 144:ef7eb2e8f9f7 892 * @retval None
<> 144:ef7eb2e8f9f7 893 */
<> 144:ef7eb2e8f9f7 894 #define ADC_SQR4_RK(_CHANNELNB_, _RANKNB_) \
<> 144:ef7eb2e8f9f7 895 ((_CHANNELNB_) << (5 * ((_RANKNB_) - 7)))
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 /**
<> 144:ef7eb2e8f9f7 898 * @brief Set the selected regular channel rank for rank between 13 and 18.
<> 144:ef7eb2e8f9f7 899 * @param _CHANNELNB_: Channel number.
<> 144:ef7eb2e8f9f7 900 * @param _RANKNB_: Rank number.
<> 144:ef7eb2e8f9f7 901 * @retval None
<> 144:ef7eb2e8f9f7 902 */
<> 144:ef7eb2e8f9f7 903 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \
<> 144:ef7eb2e8f9f7 904 ((_CHANNELNB_) << (5 * ((_RANKNB_) - 13)))
<> 144:ef7eb2e8f9f7 905
<> 144:ef7eb2e8f9f7 906 /**
<> 144:ef7eb2e8f9f7 907 * @brief Set the selected regular channel rank for rank between 19 and 24.
<> 144:ef7eb2e8f9f7 908 * @param _CHANNELNB_: Channel number.
<> 144:ef7eb2e8f9f7 909 * @param _RANKNB_: Rank number.
<> 144:ef7eb2e8f9f7 910 * @retval None
<> 144:ef7eb2e8f9f7 911 */
<> 144:ef7eb2e8f9f7 912 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \
<> 144:ef7eb2e8f9f7 913 ((_CHANNELNB_) << (5 * ((_RANKNB_) - 19)))
<> 144:ef7eb2e8f9f7 914
<> 144:ef7eb2e8f9f7 915 /**
<> 144:ef7eb2e8f9f7 916 * @brief Set the selected regular channel rank for rank between 25 and 28.
<> 144:ef7eb2e8f9f7 917 * @param _CHANNELNB_: Channel number.
<> 144:ef7eb2e8f9f7 918 * @param _RANKNB_: Rank number.
<> 144:ef7eb2e8f9f7 919 * @retval None
<> 144:ef7eb2e8f9f7 920 */
<> 144:ef7eb2e8f9f7 921 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \
<> 144:ef7eb2e8f9f7 922 ((_CHANNELNB_) << (5 * ((_RANKNB_) - 25)))
<> 144:ef7eb2e8f9f7 923
<> 144:ef7eb2e8f9f7 924 /**
<> 144:ef7eb2e8f9f7 925 * @brief Set the injected sequence length.
<> 144:ef7eb2e8f9f7 926 * @param _JSQR_JL_: Sequence length.
<> 144:ef7eb2e8f9f7 927 * @retval None
<> 144:ef7eb2e8f9f7 928 */
<> 144:ef7eb2e8f9f7 929 #define ADC_JSQR_JL_SHIFT(_JSQR_JL_) (((_JSQR_JL_) -1) << 20)
<> 144:ef7eb2e8f9f7 930
<> 144:ef7eb2e8f9f7 931 /**
<> 144:ef7eb2e8f9f7 932 * @brief Set the selected injected channel rank
<> 144:ef7eb2e8f9f7 933 * Note: on STM32L1 devices, channel rank position in JSQR register
<> 144:ef7eb2e8f9f7 934 * is depending on total number of ranks selected into
<> 144:ef7eb2e8f9f7 935 * injected sequencer (ranks sequence starting from 4-JL)
<> 144:ef7eb2e8f9f7 936 * @param _CHANNELNB_: Channel number.
<> 144:ef7eb2e8f9f7 937 * @param _RANKNB_: Rank number.
<> 144:ef7eb2e8f9f7 938 * @param _JSQR_JL_: Sequence length.
<> 144:ef7eb2e8f9f7 939 * @retval None
<> 144:ef7eb2e8f9f7 940 */
<> 144:ef7eb2e8f9f7 941 #define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \
<> 144:ef7eb2e8f9f7 942 ((_CHANNELNB_) << (5 * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
<> 144:ef7eb2e8f9f7 943
<> 144:ef7eb2e8f9f7 944 /**
<> 144:ef7eb2e8f9f7 945 * @brief Enable the ADC DMA continuous request.
<> 144:ef7eb2e8f9f7 946 * @param _DMACONTREQ_MODE_: DMA continuous request mode.
<> 144:ef7eb2e8f9f7 947 * @retval None
<> 144:ef7eb2e8f9f7 948 */
<> 144:ef7eb2e8f9f7 949 #define ADC_CR2_DMACONTREQ(_DMACONTREQ_MODE_) \
<> 144:ef7eb2e8f9f7 950 ((_DMACONTREQ_MODE_) << POSITION_VAL(ADC_CR2_DDS))
<> 144:ef7eb2e8f9f7 951
<> 144:ef7eb2e8f9f7 952 /**
<> 144:ef7eb2e8f9f7 953 * @brief Enable ADC continuous conversion mode.
<> 144:ef7eb2e8f9f7 954 * @param _CONTINUOUS_MODE_: Continuous mode.
<> 144:ef7eb2e8f9f7 955 * @retval None
<> 144:ef7eb2e8f9f7 956 */
<> 144:ef7eb2e8f9f7 957 #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \
<> 144:ef7eb2e8f9f7 958 ((_CONTINUOUS_MODE_) << POSITION_VAL(ADC_CR2_CONT))
<> 144:ef7eb2e8f9f7 959
<> 144:ef7eb2e8f9f7 960 /**
<> 144:ef7eb2e8f9f7 961 * @brief Configures the number of discontinuous conversions for the regular group channels.
<> 144:ef7eb2e8f9f7 962 * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
<> 144:ef7eb2e8f9f7 963 * @retval None
<> 144:ef7eb2e8f9f7 964 */
<> 144:ef7eb2e8f9f7 965 #define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \
<> 144:ef7eb2e8f9f7 966 (((_NBR_DISCONTINUOUS_CONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM))
<> 144:ef7eb2e8f9f7 967
<> 144:ef7eb2e8f9f7 968 /**
<> 144:ef7eb2e8f9f7 969 * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
<> 144:ef7eb2e8f9f7 970 * @param _SCAN_MODE_: Scan conversion mode.
<> 144:ef7eb2e8f9f7 971 * @retval None
<> 144:ef7eb2e8f9f7 972 */
<> 144:ef7eb2e8f9f7 973 /* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */
<> 144:ef7eb2e8f9f7 974 /* is equivalent to ADC_SCAN_ENABLE. */
<> 144:ef7eb2e8f9f7 975 #define ADC_CR1_SCAN_SET(_SCAN_MODE_) \
<> 144:ef7eb2e8f9f7 976 (( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE) \
<> 144:ef7eb2e8f9f7 977 )? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \
<> 144:ef7eb2e8f9f7 978 )
<> 144:ef7eb2e8f9f7 979
<> 144:ef7eb2e8f9f7 980
<> 144:ef7eb2e8f9f7 981 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || \
<> 144:ef7eb2e8f9f7 982 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2) || \
<> 144:ef7eb2e8f9f7 983 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4) )
<> 144:ef7eb2e8f9f7 984
<> 144:ef7eb2e8f9f7 985 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
<> 144:ef7eb2e8f9f7 986 ((RESOLUTION) == ADC_RESOLUTION_10B) || \
<> 144:ef7eb2e8f9f7 987 ((RESOLUTION) == ADC_RESOLUTION_8B) || \
<> 144:ef7eb2e8f9f7 988 ((RESOLUTION) == ADC_RESOLUTION_6B) )
<> 144:ef7eb2e8f9f7 989
<> 144:ef7eb2e8f9f7 990 #define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) || \
<> 144:ef7eb2e8f9f7 991 ((RESOLUTION) == ADC_RESOLUTION_6B) )
<> 144:ef7eb2e8f9f7 992
<> 144:ef7eb2e8f9f7 993 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
<> 144:ef7eb2e8f9f7 994 ((ALIGN) == ADC_DATAALIGN_LEFT) )
<> 144:ef7eb2e8f9f7 995
<> 144:ef7eb2e8f9f7 996 #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \
<> 144:ef7eb2e8f9f7 997 ((SCAN_MODE) == ADC_SCAN_ENABLE) )
<> 144:ef7eb2e8f9f7 998
<> 144:ef7eb2e8f9f7 999 #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
<> 144:ef7eb2e8f9f7 1000 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
<> 144:ef7eb2e8f9f7 1001 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
<> 144:ef7eb2e8f9f7 1002 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
<> 144:ef7eb2e8f9f7 1003
<> 144:ef7eb2e8f9f7 1004 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
<> 144:ef7eb2e8f9f7 1005 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
<> 144:ef7eb2e8f9f7 1006 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
<> 144:ef7eb2e8f9f7 1007 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
<> 144:ef7eb2e8f9f7 1008 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC3) || \
<> 144:ef7eb2e8f9f7 1009 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
<> 144:ef7eb2e8f9f7 1010 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
<> 144:ef7eb2e8f9f7 1011 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \
<> 144:ef7eb2e8f9f7 1012 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
<> 144:ef7eb2e8f9f7 1013 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T9_CC2) || \
<> 144:ef7eb2e8f9f7 1014 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T9_TRGO) || \
<> 144:ef7eb2e8f9f7 1015 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
<> 144:ef7eb2e8f9f7 1016 ((REGTRIG) == ADC_SOFTWARE_START) )
<> 144:ef7eb2e8f9f7 1017
<> 144:ef7eb2e8f9f7 1018 #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \
<> 144:ef7eb2e8f9f7 1019 ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) )
<> 144:ef7eb2e8f9f7 1020
<> 144:ef7eb2e8f9f7 1021 #define IS_ADC_AUTOWAIT(AUTOWAIT) (((AUTOWAIT) == ADC_AUTOWAIT_DISABLE) || \
<> 144:ef7eb2e8f9f7 1022 ((AUTOWAIT) == ADC_AUTOWAIT_UNTIL_DATA_READ) || \
<> 144:ef7eb2e8f9f7 1023 ((AUTOWAIT) == ADC_AUTOWAIT_7_APBCLOCKCYCLES) || \
<> 144:ef7eb2e8f9f7 1024 ((AUTOWAIT) == ADC_AUTOWAIT_15_APBCLOCKCYCLES) || \
<> 144:ef7eb2e8f9f7 1025 ((AUTOWAIT) == ADC_AUTOWAIT_31_APBCLOCKCYCLES) || \
<> 144:ef7eb2e8f9f7 1026 ((AUTOWAIT) == ADC_AUTOWAIT_63_APBCLOCKCYCLES) || \
<> 144:ef7eb2e8f9f7 1027 ((AUTOWAIT) == ADC_AUTOWAIT_127_APBCLOCKCYCLES) || \
<> 144:ef7eb2e8f9f7 1028 ((AUTOWAIT) == ADC_AUTOWAIT_255_APBCLOCKCYCLES) )
<> 144:ef7eb2e8f9f7 1029
<> 144:ef7eb2e8f9f7 1030 #define IS_ADC_AUTOPOWEROFF(AUTOPOWEROFF) (((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_DISABLE) || \
<> 144:ef7eb2e8f9f7 1031 ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_IDLE_PHASE) || \
<> 144:ef7eb2e8f9f7 1032 ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_DELAY_PHASE) || \
<> 144:ef7eb2e8f9f7 1033 ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES) )
<> 144:ef7eb2e8f9f7 1034
<> 144:ef7eb2e8f9f7 1035 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 144:ef7eb2e8f9f7 1036
<> 144:ef7eb2e8f9f7 1037 #define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A) || \
<> 144:ef7eb2e8f9f7 1038 ((BANK) == ADC_CHANNELS_BANK_B) )
<> 144:ef7eb2e8f9f7 1039 #else
<> 144:ef7eb2e8f9f7 1040
<> 144:ef7eb2e8f9f7 1041 #define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A))
<> 144:ef7eb2e8f9f7 1042 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
<> 144:ef7eb2e8f9f7 1043
<> 144:ef7eb2e8f9f7 1044 #if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
<> 144:ef7eb2e8f9f7 1045 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
<> 144:ef7eb2e8f9f7 1046 ((CHANNEL) == ADC_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 1047 ((CHANNEL) == ADC_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 1048 ((CHANNEL) == ADC_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 1049 ((CHANNEL) == ADC_CHANNEL_4) || \
<> 144:ef7eb2e8f9f7 1050 ((CHANNEL) == ADC_CHANNEL_5) || \
<> 144:ef7eb2e8f9f7 1051 ((CHANNEL) == ADC_CHANNEL_6) || \
<> 144:ef7eb2e8f9f7 1052 ((CHANNEL) == ADC_CHANNEL_7) || \
<> 144:ef7eb2e8f9f7 1053 ((CHANNEL) == ADC_CHANNEL_8) || \
<> 144:ef7eb2e8f9f7 1054 ((CHANNEL) == ADC_CHANNEL_9) || \
<> 144:ef7eb2e8f9f7 1055 ((CHANNEL) == ADC_CHANNEL_10) || \
<> 144:ef7eb2e8f9f7 1056 ((CHANNEL) == ADC_CHANNEL_11) || \
<> 144:ef7eb2e8f9f7 1057 ((CHANNEL) == ADC_CHANNEL_12) || \
<> 144:ef7eb2e8f9f7 1058 ((CHANNEL) == ADC_CHANNEL_13) || \
<> 144:ef7eb2e8f9f7 1059 ((CHANNEL) == ADC_CHANNEL_14) || \
<> 144:ef7eb2e8f9f7 1060 ((CHANNEL) == ADC_CHANNEL_15) || \
<> 144:ef7eb2e8f9f7 1061 ((CHANNEL) == ADC_CHANNEL_16) || \
<> 144:ef7eb2e8f9f7 1062 ((CHANNEL) == ADC_CHANNEL_17) || \
<> 144:ef7eb2e8f9f7 1063 ((CHANNEL) == ADC_CHANNEL_18) || \
<> 144:ef7eb2e8f9f7 1064 ((CHANNEL) == ADC_CHANNEL_19) || \
<> 144:ef7eb2e8f9f7 1065 ((CHANNEL) == ADC_CHANNEL_20) || \
<> 144:ef7eb2e8f9f7 1066 ((CHANNEL) == ADC_CHANNEL_21) || \
<> 144:ef7eb2e8f9f7 1067 ((CHANNEL) == ADC_CHANNEL_22) || \
<> 144:ef7eb2e8f9f7 1068 ((CHANNEL) == ADC_CHANNEL_23) || \
<> 144:ef7eb2e8f9f7 1069 ((CHANNEL) == ADC_CHANNEL_24) || \
<> 144:ef7eb2e8f9f7 1070 ((CHANNEL) == ADC_CHANNEL_25) || \
<> 144:ef7eb2e8f9f7 1071 ((CHANNEL) == ADC_CHANNEL_26) )
<> 144:ef7eb2e8f9f7 1072 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */
<> 144:ef7eb2e8f9f7 1073 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 144:ef7eb2e8f9f7 1074 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
<> 144:ef7eb2e8f9f7 1075 ((CHANNEL) == ADC_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 1076 ((CHANNEL) == ADC_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 1077 ((CHANNEL) == ADC_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 1078 ((CHANNEL) == ADC_CHANNEL_4) || \
<> 144:ef7eb2e8f9f7 1079 ((CHANNEL) == ADC_CHANNEL_5) || \
<> 144:ef7eb2e8f9f7 1080 ((CHANNEL) == ADC_CHANNEL_6) || \
<> 144:ef7eb2e8f9f7 1081 ((CHANNEL) == ADC_CHANNEL_7) || \
<> 144:ef7eb2e8f9f7 1082 ((CHANNEL) == ADC_CHANNEL_8) || \
<> 144:ef7eb2e8f9f7 1083 ((CHANNEL) == ADC_CHANNEL_9) || \
<> 144:ef7eb2e8f9f7 1084 ((CHANNEL) == ADC_CHANNEL_10) || \
<> 144:ef7eb2e8f9f7 1085 ((CHANNEL) == ADC_CHANNEL_11) || \
<> 144:ef7eb2e8f9f7 1086 ((CHANNEL) == ADC_CHANNEL_12) || \
<> 144:ef7eb2e8f9f7 1087 ((CHANNEL) == ADC_CHANNEL_13) || \
<> 144:ef7eb2e8f9f7 1088 ((CHANNEL) == ADC_CHANNEL_14) || \
<> 144:ef7eb2e8f9f7 1089 ((CHANNEL) == ADC_CHANNEL_15) || \
<> 144:ef7eb2e8f9f7 1090 ((CHANNEL) == ADC_CHANNEL_16) || \
<> 144:ef7eb2e8f9f7 1091 ((CHANNEL) == ADC_CHANNEL_17) || \
<> 144:ef7eb2e8f9f7 1092 ((CHANNEL) == ADC_CHANNEL_18) || \
<> 144:ef7eb2e8f9f7 1093 ((CHANNEL) == ADC_CHANNEL_19) || \
<> 144:ef7eb2e8f9f7 1094 ((CHANNEL) == ADC_CHANNEL_20) || \
<> 144:ef7eb2e8f9f7 1095 ((CHANNEL) == ADC_CHANNEL_21) || \
<> 144:ef7eb2e8f9f7 1096 ((CHANNEL) == ADC_CHANNEL_22) || \
<> 144:ef7eb2e8f9f7 1097 ((CHANNEL) == ADC_CHANNEL_23) || \
<> 144:ef7eb2e8f9f7 1098 ((CHANNEL) == ADC_CHANNEL_24) || \
<> 144:ef7eb2e8f9f7 1099 ((CHANNEL) == ADC_CHANNEL_25) || \
<> 144:ef7eb2e8f9f7 1100 ((CHANNEL) == ADC_CHANNEL_26) || \
<> 144:ef7eb2e8f9f7 1101 ((CHANNEL) == ADC_CHANNEL_27) || \
<> 144:ef7eb2e8f9f7 1102 ((CHANNEL) == ADC_CHANNEL_28) || \
<> 144:ef7eb2e8f9f7 1103 ((CHANNEL) == ADC_CHANNEL_29) || \
<> 144:ef7eb2e8f9f7 1104 ((CHANNEL) == ADC_CHANNEL_30) || \
<> 144:ef7eb2e8f9f7 1105 ((CHANNEL) == ADC_CHANNEL_31) )
<> 144:ef7eb2e8f9f7 1106 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
<> 144:ef7eb2e8f9f7 1107
<> 144:ef7eb2e8f9f7 1108 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_4CYCLES) || \
<> 144:ef7eb2e8f9f7 1109 ((TIME) == ADC_SAMPLETIME_9CYCLES) || \
<> 144:ef7eb2e8f9f7 1110 ((TIME) == ADC_SAMPLETIME_16CYCLES) || \
<> 144:ef7eb2e8f9f7 1111 ((TIME) == ADC_SAMPLETIME_24CYCLES) || \
<> 144:ef7eb2e8f9f7 1112 ((TIME) == ADC_SAMPLETIME_48CYCLES) || \
<> 144:ef7eb2e8f9f7 1113 ((TIME) == ADC_SAMPLETIME_96CYCLES) || \
<> 144:ef7eb2e8f9f7 1114 ((TIME) == ADC_SAMPLETIME_192CYCLES) || \
<> 144:ef7eb2e8f9f7 1115 ((TIME) == ADC_SAMPLETIME_384CYCLES) )
<> 144:ef7eb2e8f9f7 1116
<> 144:ef7eb2e8f9f7 1117 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 144:ef7eb2e8f9f7 1118
<> 144:ef7eb2e8f9f7 1119 #define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \
<> 144:ef7eb2e8f9f7 1120 ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \
<> 144:ef7eb2e8f9f7 1121 ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \
<> 144:ef7eb2e8f9f7 1122 ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \
<> 144:ef7eb2e8f9f7 1123 ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \
<> 144:ef7eb2e8f9f7 1124 ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
<> 144:ef7eb2e8f9f7 1125 ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
<> 144:ef7eb2e8f9f7 1126 ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
<> 144:ef7eb2e8f9f7 1127 ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
<> 144:ef7eb2e8f9f7 1128 ((CHANNEL) == ADC_REGULAR_RANK_10) || \
<> 144:ef7eb2e8f9f7 1129 ((CHANNEL) == ADC_REGULAR_RANK_11) || \
<> 144:ef7eb2e8f9f7 1130 ((CHANNEL) == ADC_REGULAR_RANK_12) || \
<> 144:ef7eb2e8f9f7 1131 ((CHANNEL) == ADC_REGULAR_RANK_13) || \
<> 144:ef7eb2e8f9f7 1132 ((CHANNEL) == ADC_REGULAR_RANK_14) || \
<> 144:ef7eb2e8f9f7 1133 ((CHANNEL) == ADC_REGULAR_RANK_15) || \
<> 144:ef7eb2e8f9f7 1134 ((CHANNEL) == ADC_REGULAR_RANK_16) || \
<> 144:ef7eb2e8f9f7 1135 ((CHANNEL) == ADC_REGULAR_RANK_17) || \
<> 144:ef7eb2e8f9f7 1136 ((CHANNEL) == ADC_REGULAR_RANK_18) || \
<> 144:ef7eb2e8f9f7 1137 ((CHANNEL) == ADC_REGULAR_RANK_19) || \
<> 144:ef7eb2e8f9f7 1138 ((CHANNEL) == ADC_REGULAR_RANK_20) || \
<> 144:ef7eb2e8f9f7 1139 ((CHANNEL) == ADC_REGULAR_RANK_21) || \
<> 144:ef7eb2e8f9f7 1140 ((CHANNEL) == ADC_REGULAR_RANK_22) || \
<> 144:ef7eb2e8f9f7 1141 ((CHANNEL) == ADC_REGULAR_RANK_23) || \
<> 144:ef7eb2e8f9f7 1142 ((CHANNEL) == ADC_REGULAR_RANK_24) || \
<> 144:ef7eb2e8f9f7 1143 ((CHANNEL) == ADC_REGULAR_RANK_25) || \
<> 144:ef7eb2e8f9f7 1144 ((CHANNEL) == ADC_REGULAR_RANK_26) || \
<> 144:ef7eb2e8f9f7 1145 ((CHANNEL) == ADC_REGULAR_RANK_27) || \
<> 144:ef7eb2e8f9f7 1146 ((CHANNEL) == ADC_REGULAR_RANK_28) )
<> 144:ef7eb2e8f9f7 1147 #else
<> 144:ef7eb2e8f9f7 1148
<> 144:ef7eb2e8f9f7 1149 #define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \
<> 144:ef7eb2e8f9f7 1150 ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \
<> 144:ef7eb2e8f9f7 1151 ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \
<> 144:ef7eb2e8f9f7 1152 ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \
<> 144:ef7eb2e8f9f7 1153 ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \
<> 144:ef7eb2e8f9f7 1154 ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
<> 144:ef7eb2e8f9f7 1155 ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
<> 144:ef7eb2e8f9f7 1156 ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
<> 144:ef7eb2e8f9f7 1157 ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
<> 144:ef7eb2e8f9f7 1158 ((CHANNEL) == ADC_REGULAR_RANK_10) || \
<> 144:ef7eb2e8f9f7 1159 ((CHANNEL) == ADC_REGULAR_RANK_11) || \
<> 144:ef7eb2e8f9f7 1160 ((CHANNEL) == ADC_REGULAR_RANK_12) || \
<> 144:ef7eb2e8f9f7 1161 ((CHANNEL) == ADC_REGULAR_RANK_13) || \
<> 144:ef7eb2e8f9f7 1162 ((CHANNEL) == ADC_REGULAR_RANK_14) || \
<> 144:ef7eb2e8f9f7 1163 ((CHANNEL) == ADC_REGULAR_RANK_15) || \
<> 144:ef7eb2e8f9f7 1164 ((CHANNEL) == ADC_REGULAR_RANK_16) || \
<> 144:ef7eb2e8f9f7 1165 ((CHANNEL) == ADC_REGULAR_RANK_17) || \
<> 144:ef7eb2e8f9f7 1166 ((CHANNEL) == ADC_REGULAR_RANK_18) || \
<> 144:ef7eb2e8f9f7 1167 ((CHANNEL) == ADC_REGULAR_RANK_19) || \
<> 144:ef7eb2e8f9f7 1168 ((CHANNEL) == ADC_REGULAR_RANK_20) || \
<> 144:ef7eb2e8f9f7 1169 ((CHANNEL) == ADC_REGULAR_RANK_21) || \
<> 144:ef7eb2e8f9f7 1170 ((CHANNEL) == ADC_REGULAR_RANK_22) || \
<> 144:ef7eb2e8f9f7 1171 ((CHANNEL) == ADC_REGULAR_RANK_23) || \
<> 144:ef7eb2e8f9f7 1172 ((CHANNEL) == ADC_REGULAR_RANK_24) || \
<> 144:ef7eb2e8f9f7 1173 ((CHANNEL) == ADC_REGULAR_RANK_25) || \
<> 144:ef7eb2e8f9f7 1174 ((CHANNEL) == ADC_REGULAR_RANK_26) || \
<> 144:ef7eb2e8f9f7 1175 ((CHANNEL) == ADC_REGULAR_RANK_27) )
<> 144:ef7eb2e8f9f7 1176 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
<> 144:ef7eb2e8f9f7 1177
<> 144:ef7eb2e8f9f7 1178 #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \
<> 144:ef7eb2e8f9f7 1179 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
<> 144:ef7eb2e8f9f7 1180 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
<> 144:ef7eb2e8f9f7 1181 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
<> 144:ef7eb2e8f9f7 1182 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
<> 144:ef7eb2e8f9f7 1183 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
<> 144:ef7eb2e8f9f7 1184 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
<> 144:ef7eb2e8f9f7 1185
<> 144:ef7eb2e8f9f7 1186 #define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \
<> 144:ef7eb2e8f9f7 1187 ((CONVERSION) == ADC_INJECTED_GROUP) || \
<> 144:ef7eb2e8f9f7 1188 ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) )
<> 144:ef7eb2e8f9f7 1189
<> 144:ef7eb2e8f9f7 1190 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \
<> 144:ef7eb2e8f9f7 1191 ((EVENT) == ADC_FLAG_OVR) )
<> 144:ef7eb2e8f9f7 1192
<> 144:ef7eb2e8f9f7 1193 /**
<> 144:ef7eb2e8f9f7 1194 * @brief Verify that a ADC data is within range corresponding to
<> 144:ef7eb2e8f9f7 1195 * ADC resolution.
<> 144:ef7eb2e8f9f7 1196 * @param __RESOLUTION__: ADC resolution (12, 10, 8 or 6 bits).
<> 144:ef7eb2e8f9f7 1197 * @param __ADC_DATA__: value checked against the resolution.
<> 144:ef7eb2e8f9f7 1198 * @retval SET: ADC data is within range corresponding to ADC resolution
<> 144:ef7eb2e8f9f7 1199 * RESET: ADC data is not within range corresponding to ADC resolution
<> 144:ef7eb2e8f9f7 1200 *
<> 144:ef7eb2e8f9f7 1201 */
<> 144:ef7eb2e8f9f7 1202 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_DATA__) \
<> 144:ef7eb2e8f9f7 1203 ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_DATA__) <= ((uint32_t)0x0FFF))) || \
<> 144:ef7eb2e8f9f7 1204 (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_DATA__) <= ((uint32_t)0x03FF))) || \
<> 144:ef7eb2e8f9f7 1205 (((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_DATA__) <= ((uint32_t)0x00FF))) || \
<> 144:ef7eb2e8f9f7 1206 (((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_DATA__) <= ((uint32_t)0x003F))) )
<> 144:ef7eb2e8f9f7 1207
<> 144:ef7eb2e8f9f7 1208
<> 144:ef7eb2e8f9f7 1209 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 144:ef7eb2e8f9f7 1210 #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)28)))
<> 144:ef7eb2e8f9f7 1211 #else
<> 144:ef7eb2e8f9f7 1212 #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)27)))
<> 144:ef7eb2e8f9f7 1213 #endif
<> 144:ef7eb2e8f9f7 1214
<> 144:ef7eb2e8f9f7 1215 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
<> 144:ef7eb2e8f9f7 1216
<> 144:ef7eb2e8f9f7 1217 /**
<> 144:ef7eb2e8f9f7 1218 * @}
<> 144:ef7eb2e8f9f7 1219 */
<> 144:ef7eb2e8f9f7 1220
<> 144:ef7eb2e8f9f7 1221
<> 144:ef7eb2e8f9f7 1222 /* Include ADC HAL Extension module */
<> 144:ef7eb2e8f9f7 1223 #include "stm32l1xx_hal_adc_ex.h"
<> 144:ef7eb2e8f9f7 1224
<> 144:ef7eb2e8f9f7 1225 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1226 /** @addtogroup ADC_Exported_Functions
<> 144:ef7eb2e8f9f7 1227 * @{
<> 144:ef7eb2e8f9f7 1228 */
<> 144:ef7eb2e8f9f7 1229
<> 144:ef7eb2e8f9f7 1230 /** @addtogroup ADC_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 1231 * @{
<> 144:ef7eb2e8f9f7 1232 */
<> 144:ef7eb2e8f9f7 1233
<> 144:ef7eb2e8f9f7 1234
<> 144:ef7eb2e8f9f7 1235 /* Initialization and de-initialization functions **********************************/
<> 144:ef7eb2e8f9f7 1236 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 1237 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
<> 144:ef7eb2e8f9f7 1238 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 1239 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 1240 /**
<> 144:ef7eb2e8f9f7 1241 * @}
<> 144:ef7eb2e8f9f7 1242 */
<> 144:ef7eb2e8f9f7 1243
<> 144:ef7eb2e8f9f7 1244 /* IO operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 1245
<> 144:ef7eb2e8f9f7 1246 /** @addtogroup ADC_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 1247 * @{
<> 144:ef7eb2e8f9f7 1248 */
<> 144:ef7eb2e8f9f7 1249
<> 144:ef7eb2e8f9f7 1250
<> 144:ef7eb2e8f9f7 1251 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 1252 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 1253 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 1254 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 1255 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 1256
<> 144:ef7eb2e8f9f7 1257 /* Non-blocking mode: Interruption */
<> 144:ef7eb2e8f9f7 1258 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 1259 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 1260
<> 144:ef7eb2e8f9f7 1261 /* Non-blocking mode: DMA */
<> 144:ef7eb2e8f9f7 1262 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
<> 144:ef7eb2e8f9f7 1263 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 1264
<> 144:ef7eb2e8f9f7 1265 /* ADC retrieve conversion value intended to be used with polling or interruption */
<> 144:ef7eb2e8f9f7 1266 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 1267
<> 144:ef7eb2e8f9f7 1268 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
<> 144:ef7eb2e8f9f7 1269 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 1270 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 1271 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 1272 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 1273 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
<> 144:ef7eb2e8f9f7 1274 /**
<> 144:ef7eb2e8f9f7 1275 * @}
<> 144:ef7eb2e8f9f7 1276 */
<> 144:ef7eb2e8f9f7 1277
<> 144:ef7eb2e8f9f7 1278
<> 144:ef7eb2e8f9f7 1279 /* Peripheral Control functions ***********************************************/
<> 144:ef7eb2e8f9f7 1280 /** @addtogroup ADC_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 1281 * @{
<> 144:ef7eb2e8f9f7 1282 */
<> 144:ef7eb2e8f9f7 1283 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
<> 144:ef7eb2e8f9f7 1284 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
<> 144:ef7eb2e8f9f7 1285 /**
<> 144:ef7eb2e8f9f7 1286 * @}
<> 144:ef7eb2e8f9f7 1287 */
<> 144:ef7eb2e8f9f7 1288
<> 144:ef7eb2e8f9f7 1289
<> 144:ef7eb2e8f9f7 1290 /* Peripheral State functions *************************************************/
<> 144:ef7eb2e8f9f7 1291 /** @addtogroup ADC_Exported_Functions_Group4
<> 144:ef7eb2e8f9f7 1292 * @{
<> 144:ef7eb2e8f9f7 1293 */
<> 144:ef7eb2e8f9f7 1294 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 1295 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
<> 144:ef7eb2e8f9f7 1296 /**
<> 144:ef7eb2e8f9f7 1297 * @}
<> 144:ef7eb2e8f9f7 1298 */
<> 144:ef7eb2e8f9f7 1299
<> 144:ef7eb2e8f9f7 1300
<> 144:ef7eb2e8f9f7 1301 /**
<> 144:ef7eb2e8f9f7 1302 * @}
<> 144:ef7eb2e8f9f7 1303 */
<> 144:ef7eb2e8f9f7 1304
<> 144:ef7eb2e8f9f7 1305
<> 144:ef7eb2e8f9f7 1306 /* Internal HAL driver functions **********************************************/
<> 144:ef7eb2e8f9f7 1307 /** @addtogroup ADC_Private_Functions
<> 144:ef7eb2e8f9f7 1308 * @{
<> 144:ef7eb2e8f9f7 1309 */
<> 144:ef7eb2e8f9f7 1310
<> 144:ef7eb2e8f9f7 1311 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 1312 HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 1313 /**
<> 144:ef7eb2e8f9f7 1314 * @}
<> 144:ef7eb2e8f9f7 1315 */
<> 144:ef7eb2e8f9f7 1316
<> 144:ef7eb2e8f9f7 1317
<> 144:ef7eb2e8f9f7 1318 /**
<> 144:ef7eb2e8f9f7 1319 * @}
<> 144:ef7eb2e8f9f7 1320 */
<> 144:ef7eb2e8f9f7 1321
<> 144:ef7eb2e8f9f7 1322 /**
<> 144:ef7eb2e8f9f7 1323 * @}
<> 144:ef7eb2e8f9f7 1324 */
<> 144:ef7eb2e8f9f7 1325
<> 144:ef7eb2e8f9f7 1326 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 1327 }
<> 144:ef7eb2e8f9f7 1328 #endif
<> 144:ef7eb2e8f9f7 1329
<> 144:ef7eb2e8f9f7 1330
<> 144:ef7eb2e8f9f7 1331 #endif /* __STM32L1xx_HAL_ADC_H */
<> 144:ef7eb2e8f9f7 1332
<> 144:ef7eb2e8f9f7 1333 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/