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targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_tim.h@148:161ebc35dc3a, 2016-09-28 (annotated)

Committer:
olympux
Date:
Wed Sep 28 20:59:47 2016 +0000
Revision:
148:161ebc35dc3a
Parent:
144:ef7eb2e8f9f7 
RTC working

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_hal_tim.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.5.1
<> 144:ef7eb2e8f9f7 6 * @date 31-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of TIM HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32L4xx_HAL_TIM_H
<> 144:ef7eb2e8f9f7 40 #define __STM32L4xx_HAL_TIM_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32l4xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32L4xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup TIM
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /** @defgroup TIM_Exported_Types TIM Exported Types
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /**
<> 144:ef7eb2e8f9f7 63 * @brief TIM Time base Configuration Structure definition
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65 typedef struct
<> 144:ef7eb2e8f9f7 66 {
<> 144:ef7eb2e8f9f7 67 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
<> 144:ef7eb2e8f9f7 68 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 uint32_t CounterMode; /*!< Specifies the counter mode.
<> 144:ef7eb2e8f9f7 71 This parameter can be a value of @ref TIM_Counter_Mode */
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 uint32_t Period; /*!< Specifies the period value to be loaded into the active
<> 144:ef7eb2e8f9f7 74 Auto-Reload Register at the next update event.
<> 144:ef7eb2e8f9f7 75 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 uint32_t ClockDivision; /*!< Specifies the clock division.
<> 144:ef7eb2e8f9f7 78 This parameter can be a value of @ref TIM_ClockDivision */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
<> 144:ef7eb2e8f9f7 81 reaches zero, an update event is generated and counting restarts
<> 144:ef7eb2e8f9f7 82 from the RCR value (N).
<> 144:ef7eb2e8f9f7 83 This means in PWM mode that (N+1) corresponds to:
<> 144:ef7eb2e8f9f7 84 - the number of PWM periods in edge-aligned mode
<> 144:ef7eb2e8f9f7 85 - the number of half PWM period in center-aligned mode
<> 144:ef7eb2e8f9f7 86 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
<> 144:ef7eb2e8f9f7 87 @note This parameter is valid only for TIM1 and TIM8. */
<> 144:ef7eb2e8f9f7 88 } TIM_Base_InitTypeDef;
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 /**
<> 144:ef7eb2e8f9f7 91 * @brief TIM Output Compare Configuration Structure definition
<> 144:ef7eb2e8f9f7 92 */
<> 144:ef7eb2e8f9f7 93 typedef struct
<> 144:ef7eb2e8f9f7 94 {
<> 144:ef7eb2e8f9f7 95 uint32_t OCMode; /*!< Specifies the TIM mode.
<> 144:ef7eb2e8f9f7 96 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
<> 144:ef7eb2e8f9f7 99 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 uint32_t OCPolarity; /*!< Specifies the output polarity.
<> 144:ef7eb2e8f9f7 102 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
<> 144:ef7eb2e8f9f7 105 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
<> 144:ef7eb2e8f9f7 106 @note This parameter is valid only for TIM1 and TIM8. */
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
<> 144:ef7eb2e8f9f7 109 This parameter can be a value of @ref TIM_Output_Fast_State
<> 144:ef7eb2e8f9f7 110 @note This parameter is valid only in PWM1 and PWM2 mode. */
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
<> 144:ef7eb2e8f9f7 114 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
<> 144:ef7eb2e8f9f7 115 @note This parameter is valid only for TIM1 and TIM8. */
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
<> 144:ef7eb2e8f9f7 118 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
<> 144:ef7eb2e8f9f7 119 @note This parameter is valid only for TIM1 and TIM8. */
<> 144:ef7eb2e8f9f7 120 } TIM_OC_InitTypeDef;
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 /**
<> 144:ef7eb2e8f9f7 123 * @brief TIM One Pulse Mode Configuration Structure definition
<> 144:ef7eb2e8f9f7 124 */
<> 144:ef7eb2e8f9f7 125 typedef struct
<> 144:ef7eb2e8f9f7 126 {
<> 144:ef7eb2e8f9f7 127 uint32_t OCMode; /*!< Specifies the TIM mode.
<> 144:ef7eb2e8f9f7 128 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
<> 144:ef7eb2e8f9f7 131 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 uint32_t OCPolarity; /*!< Specifies the output polarity.
<> 144:ef7eb2e8f9f7 134 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
<> 144:ef7eb2e8f9f7 137 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
<> 144:ef7eb2e8f9f7 138 @note This parameter is valid only for TIM1 and TIM8. */
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
<> 144:ef7eb2e8f9f7 141 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
<> 144:ef7eb2e8f9f7 142 @note This parameter is valid only for TIM1 and TIM8. */
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
<> 144:ef7eb2e8f9f7 145 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
<> 144:ef7eb2e8f9f7 146 @note This parameter is valid only for TIM1 and TIM8. */
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
<> 144:ef7eb2e8f9f7 149 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 uint32_t ICSelection; /*!< Specifies the input.
<> 144:ef7eb2e8f9f7 152 This parameter can be a value of @ref TIM_Input_Capture_Selection */
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 uint32_t ICFilter; /*!< Specifies the input capture filter.
<> 144:ef7eb2e8f9f7 155 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<> 144:ef7eb2e8f9f7 156 } TIM_OnePulse_InitTypeDef;
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 /**
<> 144:ef7eb2e8f9f7 160 * @brief TIM Input Capture Configuration Structure definition
<> 144:ef7eb2e8f9f7 161 */
<> 144:ef7eb2e8f9f7 162 typedef struct
<> 144:ef7eb2e8f9f7 163 {
<> 144:ef7eb2e8f9f7 164 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
<> 144:ef7eb2e8f9f7 165 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 uint32_t ICSelection; /*!< Specifies the input.
<> 144:ef7eb2e8f9f7 168 This parameter can be a value of @ref TIM_Input_Capture_Selection */
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
<> 144:ef7eb2e8f9f7 171 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 uint32_t ICFilter; /*!< Specifies the input capture filter.
<> 144:ef7eb2e8f9f7 174 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<> 144:ef7eb2e8f9f7 175 } TIM_IC_InitTypeDef;
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 /**
<> 144:ef7eb2e8f9f7 178 * @brief TIM Encoder Configuration Structure definition
<> 144:ef7eb2e8f9f7 179 */
<> 144:ef7eb2e8f9f7 180 typedef struct
<> 144:ef7eb2e8f9f7 181 {
<> 144:ef7eb2e8f9f7 182 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
<> 144:ef7eb2e8f9f7 183 This parameter can be a value of @ref TIM_Encoder_Mode */
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
<> 144:ef7eb2e8f9f7 186 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 uint32_t IC1Selection; /*!< Specifies the input.
<> 144:ef7eb2e8f9f7 189 This parameter can be a value of @ref TIM_Input_Capture_Selection */
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
<> 144:ef7eb2e8f9f7 192 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 uint32_t IC1Filter; /*!< Specifies the input capture filter.
<> 144:ef7eb2e8f9f7 195 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
<> 144:ef7eb2e8f9f7 198 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 uint32_t IC2Selection; /*!< Specifies the input.
<> 144:ef7eb2e8f9f7 201 This parameter can be a value of @ref TIM_Input_Capture_Selection */
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
<> 144:ef7eb2e8f9f7 204 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 uint32_t IC2Filter; /*!< Specifies the input capture filter.
<> 144:ef7eb2e8f9f7 207 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<> 144:ef7eb2e8f9f7 208 } TIM_Encoder_InitTypeDef;
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /**
<> 144:ef7eb2e8f9f7 212 * @brief Clock Configuration Handle Structure definition
<> 144:ef7eb2e8f9f7 213 */
<> 144:ef7eb2e8f9f7 214 typedef struct
<> 144:ef7eb2e8f9f7 215 {
<> 144:ef7eb2e8f9f7 216 uint32_t ClockSource; /*!< TIM clock sources
<> 144:ef7eb2e8f9f7 217 This parameter can be a value of @ref TIM_Clock_Source */
<> 144:ef7eb2e8f9f7 218 uint32_t ClockPolarity; /*!< TIM clock polarity
<> 144:ef7eb2e8f9f7 219 This parameter can be a value of @ref TIM_Clock_Polarity */
<> 144:ef7eb2e8f9f7 220 uint32_t ClockPrescaler; /*!< TIM clock prescaler
<> 144:ef7eb2e8f9f7 221 This parameter can be a value of @ref TIM_Clock_Prescaler */
<> 144:ef7eb2e8f9f7 222 uint32_t ClockFilter; /*!< TIM clock filter
<> 144:ef7eb2e8f9f7 223 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<> 144:ef7eb2e8f9f7 224 }TIM_ClockConfigTypeDef;
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /**
<> 144:ef7eb2e8f9f7 227 * @brief Clear Input Configuration Handle Structure definition
<> 144:ef7eb2e8f9f7 228 */
<> 144:ef7eb2e8f9f7 229 typedef struct
<> 144:ef7eb2e8f9f7 230 {
<> 144:ef7eb2e8f9f7 231 uint32_t ClearInputState; /*!< TIM clear Input state
<> 144:ef7eb2e8f9f7 232 This parameter can be ENABLE or DISABLE */
<> 144:ef7eb2e8f9f7 233 uint32_t ClearInputSource; /*!< TIM clear Input sources
<> 144:ef7eb2e8f9f7 234 This parameter can be a value of @ref TIM_ClearInput_Source */
<> 144:ef7eb2e8f9f7 235 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
<> 144:ef7eb2e8f9f7 236 This parameter can be a value of @ref TIM_ClearInput_Polarity */
<> 144:ef7eb2e8f9f7 237 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
<> 144:ef7eb2e8f9f7 238 This parameter can be a value of @ref TIM_ClearInput_Prescaler */
<> 144:ef7eb2e8f9f7 239 uint32_t ClearInputFilter; /*!< TIM Clear Input filter
<> 144:ef7eb2e8f9f7 240 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<> 144:ef7eb2e8f9f7 241 }TIM_ClearInputConfigTypeDef;
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 /**
<> 144:ef7eb2e8f9f7 244 * @brief TIM Master configuration Structure definition
<> 144:ef7eb2e8f9f7 245 * @note Advanced timers provide TRGO2 internal line which is redirected
<> 144:ef7eb2e8f9f7 246 * to the ADC
<> 144:ef7eb2e8f9f7 247 */
<> 144:ef7eb2e8f9f7 248 typedef struct {
<> 144:ef7eb2e8f9f7 249 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
<> 144:ef7eb2e8f9f7 250 This parameter can be a value of @ref TIM_Master_Mode_Selection */
<> 144:ef7eb2e8f9f7 251 uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
<> 144:ef7eb2e8f9f7 252 This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
<> 144:ef7eb2e8f9f7 253 uint32_t MasterSlaveMode; /*!< Master/slave mode selection
<> 144:ef7eb2e8f9f7 254 This parameter can be a value of @ref TIM_Master_Slave_Mode */
<> 144:ef7eb2e8f9f7 255 }TIM_MasterConfigTypeDef;
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /**
<> 144:ef7eb2e8f9f7 258 * @brief TIM Slave configuration Structure definition
<> 144:ef7eb2e8f9f7 259 */
<> 144:ef7eb2e8f9f7 260 typedef struct {
<> 144:ef7eb2e8f9f7 261 uint32_t SlaveMode; /*!< Slave mode selection
<> 144:ef7eb2e8f9f7 262 This parameter can be a value of @ref TIM_Slave_Mode */
<> 144:ef7eb2e8f9f7 263 uint32_t InputTrigger; /*!< Input Trigger source
<> 144:ef7eb2e8f9f7 264 This parameter can be a value of @ref TIM_Trigger_Selection */
<> 144:ef7eb2e8f9f7 265 uint32_t TriggerPolarity; /*!< Input Trigger polarity
<> 144:ef7eb2e8f9f7 266 This parameter can be a value of @ref TIM_Trigger_Polarity */
<> 144:ef7eb2e8f9f7 267 uint32_t TriggerPrescaler; /*!< Input trigger prescaler
<> 144:ef7eb2e8f9f7 268 This parameter can be a value of @ref TIM_Trigger_Prescaler */
<> 144:ef7eb2e8f9f7 269 uint32_t TriggerFilter; /*!< Input trigger filter
<> 144:ef7eb2e8f9f7 270 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 }TIM_SlaveConfigTypeDef;
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /**
<> 144:ef7eb2e8f9f7 275 * @brief TIM Break input(s) and Dead time configuration Structure definition
<> 144:ef7eb2e8f9f7 276 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
<> 144:ef7eb2e8f9f7 277 * filter and polarity.
<> 144:ef7eb2e8f9f7 278 */
<> 144:ef7eb2e8f9f7 279 typedef struct
<> 144:ef7eb2e8f9f7 280 {
<> 144:ef7eb2e8f9f7 281 uint32_t OffStateRunMode; /*!< TIM off state in run mode
<> 144:ef7eb2e8f9f7 282 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
<> 144:ef7eb2e8f9f7 283 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
<> 144:ef7eb2e8f9f7 284 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
<> 144:ef7eb2e8f9f7 285 uint32_t LockLevel; /*!< TIM Lock level
<> 144:ef7eb2e8f9f7 286 This parameter can be a value of @ref TIM_Lock_level */
<> 144:ef7eb2e8f9f7 287 uint32_t DeadTime; /*!< TIM dead Time
<> 144:ef7eb2e8f9f7 288 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
<> 144:ef7eb2e8f9f7 289 uint32_t BreakState; /*!< TIM Break State
<> 144:ef7eb2e8f9f7 290 This parameter can be a value of @ref TIM_Break_Input_enable_disable */
<> 144:ef7eb2e8f9f7 291 uint32_t BreakPolarity; /*!< TIM Break input polarity
<> 144:ef7eb2e8f9f7 292 This parameter can be a value of @ref TIM_Break_Polarity */
<> 144:ef7eb2e8f9f7 293 uint32_t BreakFilter; /*!< Specifies the break input filter.
<> 144:ef7eb2e8f9f7 294 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<> 144:ef7eb2e8f9f7 295 uint32_t Break2State; /*!< TIM Break2 State
<> 144:ef7eb2e8f9f7 296 This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
<> 144:ef7eb2e8f9f7 297 uint32_t Break2Polarity; /*!< TIM Break2 input polarity
<> 144:ef7eb2e8f9f7 298 This parameter can be a value of @ref TIM_Break2_Polarity */
<> 144:ef7eb2e8f9f7 299 uint32_t Break2Filter; /*!< TIM break2 input filter.
<> 144:ef7eb2e8f9f7 300 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<> 144:ef7eb2e8f9f7 301 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
<> 144:ef7eb2e8f9f7 302 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
<> 144:ef7eb2e8f9f7 303 } TIM_BreakDeadTimeConfigTypeDef;
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /**
<> 144:ef7eb2e8f9f7 306 * @brief HAL State structures definition
<> 144:ef7eb2e8f9f7 307 */
<> 144:ef7eb2e8f9f7 308 typedef enum
<> 144:ef7eb2e8f9f7 309 {
<> 144:ef7eb2e8f9f7 310 HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */
<> 144:ef7eb2e8f9f7 311 HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
<> 144:ef7eb2e8f9f7 312 HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
<> 144:ef7eb2e8f9f7 313 HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
<> 144:ef7eb2e8f9f7 314 HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
<> 144:ef7eb2e8f9f7 315 }HAL_TIM_StateTypeDef;
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /**
<> 144:ef7eb2e8f9f7 318 * @brief HAL Active channel structures definition
<> 144:ef7eb2e8f9f7 319 */
<> 144:ef7eb2e8f9f7 320 typedef enum
<> 144:ef7eb2e8f9f7 321 {
<> 144:ef7eb2e8f9f7 322 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */
<> 144:ef7eb2e8f9f7 323 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */
<> 144:ef7eb2e8f9f7 324 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */
<> 144:ef7eb2e8f9f7 325 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */
<> 144:ef7eb2e8f9f7 326 HAL_TIM_ACTIVE_CHANNEL_5 = 0x10, /*!< The active channel is 5 */
<> 144:ef7eb2e8f9f7 327 HAL_TIM_ACTIVE_CHANNEL_6 = 0x20, /*!< The active channel is 6 */
<> 144:ef7eb2e8f9f7 328 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
<> 144:ef7eb2e8f9f7 329 }HAL_TIM_ActiveChannel;
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /**
<> 144:ef7eb2e8f9f7 332 * @brief TIM Time Base Handle Structure definition
<> 144:ef7eb2e8f9f7 333 */
<> 144:ef7eb2e8f9f7 334 typedef struct
<> 144:ef7eb2e8f9f7 335 {
<> 144:ef7eb2e8f9f7 336 TIM_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 337 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
<> 144:ef7eb2e8f9f7 338 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
<> 144:ef7eb2e8f9f7 339 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
<> 144:ef7eb2e8f9f7 340 This array is accessed by a @ref DMA_Handle_index */
<> 144:ef7eb2e8f9f7 341 HAL_LockTypeDef Lock; /*!< Locking object */
<> 144:ef7eb2e8f9f7 342 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
<> 144:ef7eb2e8f9f7 343 }TIM_HandleTypeDef;
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /**
<> 144:ef7eb2e8f9f7 346 * @}
<> 144:ef7eb2e8f9f7 347 */
<> 144:ef7eb2e8f9f7 348 /* End of exported types -----------------------------------------------------*/
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 351 /** @defgroup TIM_Exported_Constants TIM Exported Constants
<> 144:ef7eb2e8f9f7 352 * @{
<> 144:ef7eb2e8f9f7 353 */
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source
<> 144:ef7eb2e8f9f7 356 * @{
<> 144:ef7eb2e8f9f7 357 */
<> 144:ef7eb2e8f9f7 358 #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
<> 144:ef7eb2e8f9f7 359 #define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002)
<> 144:ef7eb2e8f9f7 360 #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 361 /**
<> 144:ef7eb2e8f9f7 362 * @}
<> 144:ef7eb2e8f9f7 363 */
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address
<> 144:ef7eb2e8f9f7 366 * @{
<> 144:ef7eb2e8f9f7 367 */
<> 144:ef7eb2e8f9f7 368 #define TIM_DMABASE_CR1 (0x00000000)
<> 144:ef7eb2e8f9f7 369 #define TIM_DMABASE_CR2 (0x00000001)
<> 144:ef7eb2e8f9f7 370 #define TIM_DMABASE_SMCR (0x00000002)
<> 144:ef7eb2e8f9f7 371 #define TIM_DMABASE_DIER (0x00000003)
<> 144:ef7eb2e8f9f7 372 #define TIM_DMABASE_SR (0x00000004)
<> 144:ef7eb2e8f9f7 373 #define TIM_DMABASE_EGR (0x00000005)
<> 144:ef7eb2e8f9f7 374 #define TIM_DMABASE_CCMR1 (0x00000006)
<> 144:ef7eb2e8f9f7 375 #define TIM_DMABASE_CCMR2 (0x00000007)
<> 144:ef7eb2e8f9f7 376 #define TIM_DMABASE_CCER (0x00000008)
<> 144:ef7eb2e8f9f7 377 #define TIM_DMABASE_CNT (0x00000009)
<> 144:ef7eb2e8f9f7 378 #define TIM_DMABASE_PSC (0x0000000A)
<> 144:ef7eb2e8f9f7 379 #define TIM_DMABASE_ARR (0x0000000B)
<> 144:ef7eb2e8f9f7 380 #define TIM_DMABASE_RCR (0x0000000C)
<> 144:ef7eb2e8f9f7 381 #define TIM_DMABASE_CCR1 (0x0000000D)
<> 144:ef7eb2e8f9f7 382 #define TIM_DMABASE_CCR2 (0x0000000E)
<> 144:ef7eb2e8f9f7 383 #define TIM_DMABASE_CCR3 (0x0000000F)
<> 144:ef7eb2e8f9f7 384 #define TIM_DMABASE_CCR4 (0x00000010)
<> 144:ef7eb2e8f9f7 385 #define TIM_DMABASE_BDTR (0x00000011)
<> 144:ef7eb2e8f9f7 386 #define TIM_DMABASE_DCR (0x00000012)
<> 144:ef7eb2e8f9f7 387 #define TIM_DMABASE_DMAR (0x00000013)
<> 144:ef7eb2e8f9f7 388 #define TIM_DMABASE_OR1 (0x00000014)
<> 144:ef7eb2e8f9f7 389 #define TIM_DMABASE_CCMR3 (0x00000015)
<> 144:ef7eb2e8f9f7 390 #define TIM_DMABASE_CCR5 (0x00000016)
<> 144:ef7eb2e8f9f7 391 #define TIM_DMABASE_CCR6 (0x00000017)
<> 144:ef7eb2e8f9f7 392 #define TIM_DMABASE_OR2 (0x00000018)
<> 144:ef7eb2e8f9f7 393 #define TIM_DMABASE_OR3 (0x00000019)
<> 144:ef7eb2e8f9f7 394 /**
<> 144:ef7eb2e8f9f7 395 * @}
<> 144:ef7eb2e8f9f7 396 */
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 /** @defgroup TIM_Event_Source TIM Extended Event Source
<> 144:ef7eb2e8f9f7 399 * @{
<> 144:ef7eb2e8f9f7 400 */
<> 144:ef7eb2e8f9f7 401 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
<> 144:ef7eb2e8f9f7 402 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
<> 144:ef7eb2e8f9f7 403 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
<> 144:ef7eb2e8f9f7 404 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
<> 144:ef7eb2e8f9f7 405 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
<> 144:ef7eb2e8f9f7 406 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
<> 144:ef7eb2e8f9f7 407 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
<> 144:ef7eb2e8f9f7 408 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
<> 144:ef7eb2e8f9f7 409 #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */
<> 144:ef7eb2e8f9f7 410 /**
<> 144:ef7eb2e8f9f7 411 * @}
<> 144:ef7eb2e8f9f7 412 */
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
<> 144:ef7eb2e8f9f7 415 * @{
<> 144:ef7eb2e8f9f7 416 */
<> 144:ef7eb2e8f9f7 417 #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */
<> 144:ef7eb2e8f9f7 418 #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
<> 144:ef7eb2e8f9f7 419 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
<> 144:ef7eb2e8f9f7 420 /**
<> 144:ef7eb2e8f9f7 421 * @}
<> 144:ef7eb2e8f9f7 422 */
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
<> 144:ef7eb2e8f9f7 425 * @{
<> 144:ef7eb2e8f9f7 426 */
<> 144:ef7eb2e8f9f7 427 #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
<> 144:ef7eb2e8f9f7 428 #define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */
<> 144:ef7eb2e8f9f7 429 /**
<> 144:ef7eb2e8f9f7 430 * @}
<> 144:ef7eb2e8f9f7 431 */
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
<> 144:ef7eb2e8f9f7 434 * @{
<> 144:ef7eb2e8f9f7 435 */
<> 144:ef7eb2e8f9f7 436 #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */
<> 144:ef7eb2e8f9f7 437 #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
<> 144:ef7eb2e8f9f7 438 #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
<> 144:ef7eb2e8f9f7 439 #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
<> 144:ef7eb2e8f9f7 440 /**
<> 144:ef7eb2e8f9f7 441 * @}
<> 144:ef7eb2e8f9f7 442 */
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 /** @defgroup TIM_Counter_Mode TIM Counter Mode
<> 144:ef7eb2e8f9f7 445 * @{
<> 144:ef7eb2e8f9f7 446 */
<> 144:ef7eb2e8f9f7 447 #define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 448 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
<> 144:ef7eb2e8f9f7 449 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
<> 144:ef7eb2e8f9f7 450 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
<> 144:ef7eb2e8f9f7 451 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
<> 144:ef7eb2e8f9f7 452 /**
<> 144:ef7eb2e8f9f7 453 * @}
<> 144:ef7eb2e8f9f7 454 */
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /** @defgroup TIM_ClockDivision TIM Clock Division
<> 144:ef7eb2e8f9f7 457 * @{
<> 144:ef7eb2e8f9f7 458 */
<> 144:ef7eb2e8f9f7 459 #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 460 #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
<> 144:ef7eb2e8f9f7 461 #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
<> 144:ef7eb2e8f9f7 462 /**
<> 144:ef7eb2e8f9f7 463 * @}
<> 144:ef7eb2e8f9f7 464 */
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /** @defgroup TIM_Output_Compare_State TIM Output Compare State
<> 144:ef7eb2e8f9f7 467 * @{
<> 144:ef7eb2e8f9f7 468 */
<> 144:ef7eb2e8f9f7 469 #define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 470 #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
<> 144:ef7eb2e8f9f7 471 /**
<> 144:ef7eb2e8f9f7 472 * @}
<> 144:ef7eb2e8f9f7 473 */
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
<> 144:ef7eb2e8f9f7 476 * @{
<> 144:ef7eb2e8f9f7 477 */
<> 144:ef7eb2e8f9f7 478 #define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 479 #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
<> 144:ef7eb2e8f9f7 480 /**
<> 144:ef7eb2e8f9f7 481 * @}
<> 144:ef7eb2e8f9f7 482 */
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
<> 144:ef7eb2e8f9f7 485 * @{
<> 144:ef7eb2e8f9f7 486 */
<> 144:ef7eb2e8f9f7 487 #define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 488 #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
<> 144:ef7eb2e8f9f7 489 /**
<> 144:ef7eb2e8f9f7 490 * @}
<> 144:ef7eb2e8f9f7 491 */
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
<> 144:ef7eb2e8f9f7 494 * @{
<> 144:ef7eb2e8f9f7 495 */
<> 144:ef7eb2e8f9f7 496 #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 497 #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
<> 144:ef7eb2e8f9f7 498 /**
<> 144:ef7eb2e8f9f7 499 * @}
<> 144:ef7eb2e8f9f7 500 */
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
<> 144:ef7eb2e8f9f7 503 * @{
<> 144:ef7eb2e8f9f7 504 */
<> 144:ef7eb2e8f9f7 505 #define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 506 #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
<> 144:ef7eb2e8f9f7 507 /**
<> 144:ef7eb2e8f9f7 508 * @}
<> 144:ef7eb2e8f9f7 509 */
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
<> 144:ef7eb2e8f9f7 512 * @{
<> 144:ef7eb2e8f9f7 513 */
<> 144:ef7eb2e8f9f7 514 #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
<> 144:ef7eb2e8f9f7 515 #define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 516 /**
<> 144:ef7eb2e8f9f7 517 * @}
<> 144:ef7eb2e8f9f7 518 */
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
<> 144:ef7eb2e8f9f7 521 * @{
<> 144:ef7eb2e8f9f7 522 */
<> 144:ef7eb2e8f9f7 523 #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
<> 144:ef7eb2e8f9f7 524 #define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 525 /**
<> 144:ef7eb2e8f9f7 526 * @}
<> 144:ef7eb2e8f9f7 527 */
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
<> 144:ef7eb2e8f9f7 530 * @{
<> 144:ef7eb2e8f9f7 531 */
<> 144:ef7eb2e8f9f7 532 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
<> 144:ef7eb2e8f9f7 533 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
<> 144:ef7eb2e8f9f7 534 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
<> 144:ef7eb2e8f9f7 535 /**
<> 144:ef7eb2e8f9f7 536 * @}
<> 144:ef7eb2e8f9f7 537 */
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
<> 144:ef7eb2e8f9f7 540 * @{
<> 144:ef7eb2e8f9f7 541 */
<> 144:ef7eb2e8f9f7 542 #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
<> 144:ef7eb2e8f9f7 543 connected to IC1, IC2, IC3 or IC4, respectively */
<> 144:ef7eb2e8f9f7 544 #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
<> 144:ef7eb2e8f9f7 545 connected to IC2, IC1, IC4 or IC3, respectively */
<> 144:ef7eb2e8f9f7 546 #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
<> 144:ef7eb2e8f9f7 547 /**
<> 144:ef7eb2e8f9f7 548 * @}
<> 144:ef7eb2e8f9f7 549 */
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
<> 144:ef7eb2e8f9f7 552 * @{
<> 144:ef7eb2e8f9f7 553 */
<> 144:ef7eb2e8f9f7 554 #define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */
<> 144:ef7eb2e8f9f7 555 #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
<> 144:ef7eb2e8f9f7 556 #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
<> 144:ef7eb2e8f9f7 557 #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
<> 144:ef7eb2e8f9f7 558 /**
<> 144:ef7eb2e8f9f7 559 * @}
<> 144:ef7eb2e8f9f7 560 */
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
<> 144:ef7eb2e8f9f7 563 * @{
<> 144:ef7eb2e8f9f7 564 */
<> 144:ef7eb2e8f9f7 565 #define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
<> 144:ef7eb2e8f9f7 566 #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 567 /**
<> 144:ef7eb2e8f9f7 568 * @}
<> 144:ef7eb2e8f9f7 569 */
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
<> 144:ef7eb2e8f9f7 572 * @{
<> 144:ef7eb2e8f9f7 573 */
<> 144:ef7eb2e8f9f7 574 #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
<> 144:ef7eb2e8f9f7 575 #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
<> 144:ef7eb2e8f9f7 576 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
<> 144:ef7eb2e8f9f7 577 /**
<> 144:ef7eb2e8f9f7 578 * @}
<> 144:ef7eb2e8f9f7 579 */
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition
<> 144:ef7eb2e8f9f7 582 * @{
<> 144:ef7eb2e8f9f7 583 */
<> 144:ef7eb2e8f9f7 584 #define TIM_IT_UPDATE (TIM_DIER_UIE)
<> 144:ef7eb2e8f9f7 585 #define TIM_IT_CC1 (TIM_DIER_CC1IE)
<> 144:ef7eb2e8f9f7 586 #define TIM_IT_CC2 (TIM_DIER_CC2IE)
<> 144:ef7eb2e8f9f7 587 #define TIM_IT_CC3 (TIM_DIER_CC3IE)
<> 144:ef7eb2e8f9f7 588 #define TIM_IT_CC4 (TIM_DIER_CC4IE)
<> 144:ef7eb2e8f9f7 589 #define TIM_IT_COM (TIM_DIER_COMIE)
<> 144:ef7eb2e8f9f7 590 #define TIM_IT_TRIGGER (TIM_DIER_TIE)
<> 144:ef7eb2e8f9f7 591 #define TIM_IT_BREAK (TIM_DIER_BIE)
<> 144:ef7eb2e8f9f7 592 /**
<> 144:ef7eb2e8f9f7 593 * @}
<> 144:ef7eb2e8f9f7 594 */
<> 144:ef7eb2e8f9f7 595
<> 144:ef7eb2e8f9f7 596 /** @defgroup TIM_Commutation_Source TIM Commutation Source
<> 144:ef7eb2e8f9f7 597 * @{
<> 144:ef7eb2e8f9f7 598 */
<> 144:ef7eb2e8f9f7 599 #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
<> 144:ef7eb2e8f9f7 600 #define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 601 /**
<> 144:ef7eb2e8f9f7 602 * @}
<> 144:ef7eb2e8f9f7 603 */
<> 144:ef7eb2e8f9f7 604
<> 144:ef7eb2e8f9f7 605 /** @defgroup TIM_DMA_sources TIM DMA Sources
<> 144:ef7eb2e8f9f7 606 * @{
<> 144:ef7eb2e8f9f7 607 */
<> 144:ef7eb2e8f9f7 608 #define TIM_DMA_UPDATE (TIM_DIER_UDE)
<> 144:ef7eb2e8f9f7 609 #define TIM_DMA_CC1 (TIM_DIER_CC1DE)
<> 144:ef7eb2e8f9f7 610 #define TIM_DMA_CC2 (TIM_DIER_CC2DE)
<> 144:ef7eb2e8f9f7 611 #define TIM_DMA_CC3 (TIM_DIER_CC3DE)
<> 144:ef7eb2e8f9f7 612 #define TIM_DMA_CC4 (TIM_DIER_CC4DE)
<> 144:ef7eb2e8f9f7 613 #define TIM_DMA_COM (TIM_DIER_COMDE)
<> 144:ef7eb2e8f9f7 614 #define TIM_DMA_TRIGGER (TIM_DIER_TDE)
<> 144:ef7eb2e8f9f7 615 /**
<> 144:ef7eb2e8f9f7 616 * @}
<> 144:ef7eb2e8f9f7 617 */
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 /** @defgroup TIM_Flag_definition TIM Flag Definition
<> 144:ef7eb2e8f9f7 620 * @{
<> 144:ef7eb2e8f9f7 621 */
<> 144:ef7eb2e8f9f7 622 #define TIM_FLAG_UPDATE (TIM_SR_UIF)
<> 144:ef7eb2e8f9f7 623 #define TIM_FLAG_CC1 (TIM_SR_CC1IF)
<> 144:ef7eb2e8f9f7 624 #define TIM_FLAG_CC2 (TIM_SR_CC2IF)
<> 144:ef7eb2e8f9f7 625 #define TIM_FLAG_CC3 (TIM_SR_CC3IF)
<> 144:ef7eb2e8f9f7 626 #define TIM_FLAG_CC4 (TIM_SR_CC4IF)
<> 144:ef7eb2e8f9f7 627 #define TIM_FLAG_CC5 (TIM_SR_CC5IF)
<> 144:ef7eb2e8f9f7 628 #define TIM_FLAG_CC6 (TIM_SR_CC6IF)
<> 144:ef7eb2e8f9f7 629 #define TIM_FLAG_COM (TIM_SR_COMIF)
<> 144:ef7eb2e8f9f7 630 #define TIM_FLAG_TRIGGER (TIM_SR_TIF)
<> 144:ef7eb2e8f9f7 631 #define TIM_FLAG_BREAK (TIM_SR_BIF)
<> 144:ef7eb2e8f9f7 632 #define TIM_FLAG_BREAK2 (TIM_SR_B2IF)
<> 144:ef7eb2e8f9f7 633 #define TIM_FLAG_SYSTEM_BREAK (TIM_SR_SBIF)
<> 144:ef7eb2e8f9f7 634 #define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
<> 144:ef7eb2e8f9f7 635 #define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
<> 144:ef7eb2e8f9f7 636 #define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
<> 144:ef7eb2e8f9f7 637 #define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
<> 144:ef7eb2e8f9f7 638 /**
<> 144:ef7eb2e8f9f7 639 * @}
<> 144:ef7eb2e8f9f7 640 */
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642 /** @defgroup TIM_Channel TIM Channel
<> 144:ef7eb2e8f9f7 643 * @{
<> 144:ef7eb2e8f9f7 644 */
<> 144:ef7eb2e8f9f7 645 #define TIM_CHANNEL_1 ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 646 #define TIM_CHANNEL_2 ((uint32_t)0x0004)
<> 144:ef7eb2e8f9f7 647 #define TIM_CHANNEL_3 ((uint32_t)0x0008)
<> 144:ef7eb2e8f9f7 648 #define TIM_CHANNEL_4 ((uint32_t)0x000C)
<> 144:ef7eb2e8f9f7 649 #define TIM_CHANNEL_5 ((uint32_t)0x0010)
<> 144:ef7eb2e8f9f7 650 #define TIM_CHANNEL_6 ((uint32_t)0x0014)
<> 144:ef7eb2e8f9f7 651 #define TIM_CHANNEL_ALL ((uint32_t)0x003C)
<> 144:ef7eb2e8f9f7 652 /**
<> 144:ef7eb2e8f9f7 653 * @}
<> 144:ef7eb2e8f9f7 654 */
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 /** @defgroup TIM_Clock_Source TIM Clock Source
<> 144:ef7eb2e8f9f7 657 * @{
<> 144:ef7eb2e8f9f7 658 */
<> 144:ef7eb2e8f9f7 659 #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
<> 144:ef7eb2e8f9f7 660 #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
<> 144:ef7eb2e8f9f7 661 #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 662 #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
<> 144:ef7eb2e8f9f7 663 #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
<> 144:ef7eb2e8f9f7 664 #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
<> 144:ef7eb2e8f9f7 665 #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
<> 144:ef7eb2e8f9f7 666 #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
<> 144:ef7eb2e8f9f7 667 #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
<> 144:ef7eb2e8f9f7 668 #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
<> 144:ef7eb2e8f9f7 669 /**
<> 144:ef7eb2e8f9f7 670 * @}
<> 144:ef7eb2e8f9f7 671 */
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
<> 144:ef7eb2e8f9f7 674 * @{
<> 144:ef7eb2e8f9f7 675 */
<> 144:ef7eb2e8f9f7 676 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
<> 144:ef7eb2e8f9f7 677 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
<> 144:ef7eb2e8f9f7 678 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
<> 144:ef7eb2e8f9f7 679 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
<> 144:ef7eb2e8f9f7 680 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
<> 144:ef7eb2e8f9f7 681 /**
<> 144:ef7eb2e8f9f7 682 * @}
<> 144:ef7eb2e8f9f7 683 */
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
<> 144:ef7eb2e8f9f7 686 * @{
<> 144:ef7eb2e8f9f7 687 */
<> 144:ef7eb2e8f9f7 688 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
<> 144:ef7eb2e8f9f7 689 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
<> 144:ef7eb2e8f9f7 690 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
<> 144:ef7eb2e8f9f7 691 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
<> 144:ef7eb2e8f9f7 692 /**
<> 144:ef7eb2e8f9f7 693 * @}
<> 144:ef7eb2e8f9f7 694 */
<> 144:ef7eb2e8f9f7 695
<> 144:ef7eb2e8f9f7 696 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
<> 144:ef7eb2e8f9f7 697 * @{
<> 144:ef7eb2e8f9f7 698 */
<> 144:ef7eb2e8f9f7 699 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
<> 144:ef7eb2e8f9f7 700 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
<> 144:ef7eb2e8f9f7 701 /**
<> 144:ef7eb2e8f9f7 702 * @}
<> 144:ef7eb2e8f9f7 703 */
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
<> 144:ef7eb2e8f9f7 706 * @{
<> 144:ef7eb2e8f9f7 707 */
<> 144:ef7eb2e8f9f7 708 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
<> 144:ef7eb2e8f9f7 709 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
<> 144:ef7eb2e8f9f7 710 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
<> 144:ef7eb2e8f9f7 711 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
<> 144:ef7eb2e8f9f7 712 /**
<> 144:ef7eb2e8f9f7 713 * @}
<> 144:ef7eb2e8f9f7 714 */
<> 144:ef7eb2e8f9f7 715
<> 144:ef7eb2e8f9f7 716 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
<> 144:ef7eb2e8f9f7 717 * @{
<> 144:ef7eb2e8f9f7 718 */
<> 144:ef7eb2e8f9f7 719 #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
<> 144:ef7eb2e8f9f7 720 #define TIM_OSSR_DISABLE ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 721 /**
<> 144:ef7eb2e8f9f7 722 * @}
<> 144:ef7eb2e8f9f7 723 */
<> 144:ef7eb2e8f9f7 724
<> 144:ef7eb2e8f9f7 725 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
<> 144:ef7eb2e8f9f7 726 * @{
<> 144:ef7eb2e8f9f7 727 */
<> 144:ef7eb2e8f9f7 728 #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
<> 144:ef7eb2e8f9f7 729 #define TIM_OSSI_DISABLE ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 730 /**
<> 144:ef7eb2e8f9f7 731 * @}
<> 144:ef7eb2e8f9f7 732 */
<> 144:ef7eb2e8f9f7 733 /** @defgroup TIM_Lock_level TIM Lock level
<> 144:ef7eb2e8f9f7 734 * @{
<> 144:ef7eb2e8f9f7 735 */
<> 144:ef7eb2e8f9f7 736 #define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 737 #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
<> 144:ef7eb2e8f9f7 738 #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
<> 144:ef7eb2e8f9f7 739 #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
<> 144:ef7eb2e8f9f7 740 /**
<> 144:ef7eb2e8f9f7 741 * @}
<> 144:ef7eb2e8f9f7 742 */
<> 144:ef7eb2e8f9f7 743
<> 144:ef7eb2e8f9f7 744 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
<> 144:ef7eb2e8f9f7 745 * @{
<> 144:ef7eb2e8f9f7 746 */
<> 144:ef7eb2e8f9f7 747 #define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
<> 144:ef7eb2e8f9f7 748 #define TIM_BREAK_DISABLE ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 749 /**
<> 144:ef7eb2e8f9f7 750 * @}
<> 144:ef7eb2e8f9f7 751 */
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity
<> 144:ef7eb2e8f9f7 754 * @{
<> 144:ef7eb2e8f9f7 755 */
<> 144:ef7eb2e8f9f7 756 #define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 757 #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
<> 144:ef7eb2e8f9f7 758 /**
<> 144:ef7eb2e8f9f7 759 * @}
<> 144:ef7eb2e8f9f7 760 */
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
<> 144:ef7eb2e8f9f7 763 * @{
<> 144:ef7eb2e8f9f7 764 */
<> 144:ef7eb2e8f9f7 765 #define TIM_BREAK2_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 766 #define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E)
<> 144:ef7eb2e8f9f7 767 /**
<> 144:ef7eb2e8f9f7 768 * @}
<> 144:ef7eb2e8f9f7 769 */
<> 144:ef7eb2e8f9f7 770
<> 144:ef7eb2e8f9f7 771 /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
<> 144:ef7eb2e8f9f7 772 * @{
<> 144:ef7eb2e8f9f7 773 */
<> 144:ef7eb2e8f9f7 774 #define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 775 #define TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P)
<> 144:ef7eb2e8f9f7 776 /**
<> 144:ef7eb2e8f9f7 777 * @}
<> 144:ef7eb2e8f9f7 778 */
<> 144:ef7eb2e8f9f7 779
<> 144:ef7eb2e8f9f7 780 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
<> 144:ef7eb2e8f9f7 781 * @{
<> 144:ef7eb2e8f9f7 782 */
<> 144:ef7eb2e8f9f7 783 #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
<> 144:ef7eb2e8f9f7 784 #define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 785 /**
<> 144:ef7eb2e8f9f7 786 * @}
<> 144:ef7eb2e8f9f7 787 */
<> 144:ef7eb2e8f9f7 788
<> 144:ef7eb2e8f9f7 789 /** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
<> 144:ef7eb2e8f9f7 790 * @{
<> 144:ef7eb2e8f9f7 791 */
<> 144:ef7eb2e8f9f7 792 #define TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
<> 144:ef7eb2e8f9f7 793 #define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
<> 144:ef7eb2e8f9f7 794 #define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
<> 144:ef7eb2e8f9f7 795 #define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
<> 144:ef7eb2e8f9f7 796 /**
<> 144:ef7eb2e8f9f7 797 * @}
<> 144:ef7eb2e8f9f7 798 */
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
<> 144:ef7eb2e8f9f7 801 * @{
<> 144:ef7eb2e8f9f7 802 */
<> 144:ef7eb2e8f9f7 803 #define TIM_TRGO_RESET ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 804 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
<> 144:ef7eb2e8f9f7 805 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
<> 144:ef7eb2e8f9f7 806 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
<> 144:ef7eb2e8f9f7 807 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
<> 144:ef7eb2e8f9f7 808 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
<> 144:ef7eb2e8f9f7 809 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
<> 144:ef7eb2e8f9f7 810 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
<> 144:ef7eb2e8f9f7 811 /**
<> 144:ef7eb2e8f9f7 812 * @}
<> 144:ef7eb2e8f9f7 813 */
<> 144:ef7eb2e8f9f7 814
<> 144:ef7eb2e8f9f7 815 /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
<> 144:ef7eb2e8f9f7 816 * @{
<> 144:ef7eb2e8f9f7 817 */
<> 144:ef7eb2e8f9f7 818 #define TIM_TRGO2_RESET ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 819 #define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0))
<> 144:ef7eb2e8f9f7 820 #define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1))
<> 144:ef7eb2e8f9f7 821 #define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
<> 144:ef7eb2e8f9f7 822 #define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2))
<> 144:ef7eb2e8f9f7 823 #define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
<> 144:ef7eb2e8f9f7 824 #define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))
<> 144:ef7eb2e8f9f7 825 #define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
<> 144:ef7eb2e8f9f7 826 #define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3))
<> 144:ef7eb2e8f9f7 827 #define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))
<> 144:ef7eb2e8f9f7 828 #define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))
<> 144:ef7eb2e8f9f7 829 #define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
<> 144:ef7eb2e8f9f7 830 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))
<> 144:ef7eb2e8f9f7 831 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
<> 144:ef7eb2e8f9f7 832 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))
<> 144:ef7eb2e8f9f7 833 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
<> 144:ef7eb2e8f9f7 834 /**
<> 144:ef7eb2e8f9f7 835 * @}
<> 144:ef7eb2e8f9f7 836 */
<> 144:ef7eb2e8f9f7 837
<> 144:ef7eb2e8f9f7 838 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
<> 144:ef7eb2e8f9f7 839 * @{
<> 144:ef7eb2e8f9f7 840 */
<> 144:ef7eb2e8f9f7 841 #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
<> 144:ef7eb2e8f9f7 842 #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 843 /**
<> 144:ef7eb2e8f9f7 844 * @}
<> 144:ef7eb2e8f9f7 845 */
<> 144:ef7eb2e8f9f7 846
<> 144:ef7eb2e8f9f7 847 /** @defgroup TIM_Slave_Mode TIM Slave mode
<> 144:ef7eb2e8f9f7 848 * @{
<> 144:ef7eb2e8f9f7 849 */
<> 144:ef7eb2e8f9f7 850 #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 851 #define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
<> 144:ef7eb2e8f9f7 852 #define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
<> 144:ef7eb2e8f9f7 853 #define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
<> 144:ef7eb2e8f9f7 854 #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
<> 144:ef7eb2e8f9f7 855 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3))
<> 144:ef7eb2e8f9f7 856 /**
<> 144:ef7eb2e8f9f7 857 * @}
<> 144:ef7eb2e8f9f7 858 */
<> 144:ef7eb2e8f9f7 859
<> 144:ef7eb2e8f9f7 860 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
<> 144:ef7eb2e8f9f7 861 * @{
<> 144:ef7eb2e8f9f7 862 */
<> 144:ef7eb2e8f9f7 863 #define TIM_OCMODE_TIMING ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 864 #define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
<> 144:ef7eb2e8f9f7 865 #define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
<> 144:ef7eb2e8f9f7 866 #define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
<> 144:ef7eb2e8f9f7 867 #define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
<> 144:ef7eb2e8f9f7 868 #define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
<> 144:ef7eb2e8f9f7 869 #define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
<> 144:ef7eb2e8f9f7 870 #define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
<> 144:ef7eb2e8f9f7 871
<> 144:ef7eb2e8f9f7 872 #define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3)
<> 144:ef7eb2e8f9f7 873 #define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
<> 144:ef7eb2e8f9f7 874 #define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
<> 144:ef7eb2e8f9f7 875 #define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
<> 144:ef7eb2e8f9f7 876 #define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
<> 144:ef7eb2e8f9f7 877 #define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)
<> 144:ef7eb2e8f9f7 878 /**
<> 144:ef7eb2e8f9f7 879 * @}
<> 144:ef7eb2e8f9f7 880 */
<> 144:ef7eb2e8f9f7 881
<> 144:ef7eb2e8f9f7 882 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
<> 144:ef7eb2e8f9f7 883 * @{
<> 144:ef7eb2e8f9f7 884 */
<> 144:ef7eb2e8f9f7 885 #define TIM_TS_ITR0 ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 886 #define TIM_TS_ITR1 ((uint32_t)0x0010)
<> 144:ef7eb2e8f9f7 887 #define TIM_TS_ITR2 ((uint32_t)0x0020)
<> 144:ef7eb2e8f9f7 888 #define TIM_TS_ITR3 ((uint32_t)0x0030)
<> 144:ef7eb2e8f9f7 889 #define TIM_TS_TI1F_ED ((uint32_t)0x0040)
<> 144:ef7eb2e8f9f7 890 #define TIM_TS_TI1FP1 ((uint32_t)0x0050)
<> 144:ef7eb2e8f9f7 891 #define TIM_TS_TI2FP2 ((uint32_t)0x0060)
<> 144:ef7eb2e8f9f7 892 #define TIM_TS_ETRF ((uint32_t)0x0070)
<> 144:ef7eb2e8f9f7 893 #define TIM_TS_NONE ((uint32_t)0xFFFF)
<> 144:ef7eb2e8f9f7 894 /**
<> 144:ef7eb2e8f9f7 895 * @}
<> 144:ef7eb2e8f9f7 896 */
<> 144:ef7eb2e8f9f7 897
<> 144:ef7eb2e8f9f7 898 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
<> 144:ef7eb2e8f9f7 899 * @{
<> 144:ef7eb2e8f9f7 900 */
<> 144:ef7eb2e8f9f7 901 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
<> 144:ef7eb2e8f9f7 902 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
<> 144:ef7eb2e8f9f7 903 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
<> 144:ef7eb2e8f9f7 904 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
<> 144:ef7eb2e8f9f7 905 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
<> 144:ef7eb2e8f9f7 906 /**
<> 144:ef7eb2e8f9f7 907 * @}
<> 144:ef7eb2e8f9f7 908 */
<> 144:ef7eb2e8f9f7 909
<> 144:ef7eb2e8f9f7 910 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
<> 144:ef7eb2e8f9f7 911 * @{
<> 144:ef7eb2e8f9f7 912 */
<> 144:ef7eb2e8f9f7 913 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
<> 144:ef7eb2e8f9f7 914 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
<> 144:ef7eb2e8f9f7 915 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
<> 144:ef7eb2e8f9f7 916 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
<> 144:ef7eb2e8f9f7 917 /**
<> 144:ef7eb2e8f9f7 918 * @}
<> 144:ef7eb2e8f9f7 919 */
<> 144:ef7eb2e8f9f7 920
<> 144:ef7eb2e8f9f7 921 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
<> 144:ef7eb2e8f9f7 922 * @{
<> 144:ef7eb2e8f9f7 923 */
<> 144:ef7eb2e8f9f7 924 #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 925 #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
<> 144:ef7eb2e8f9f7 926 /**
<> 144:ef7eb2e8f9f7 927 * @}
<> 144:ef7eb2e8f9f7 928 */
<> 144:ef7eb2e8f9f7 929
<> 144:ef7eb2e8f9f7 930 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
<> 144:ef7eb2e8f9f7 931 * @{
<> 144:ef7eb2e8f9f7 932 */
<> 144:ef7eb2e8f9f7 933 #define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
<> 144:ef7eb2e8f9f7 934 #define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
<> 144:ef7eb2e8f9f7 935 #define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
<> 144:ef7eb2e8f9f7 936 #define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
<> 144:ef7eb2e8f9f7 937 #define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
<> 144:ef7eb2e8f9f7 938 #define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
<> 144:ef7eb2e8f9f7 939 #define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
<> 144:ef7eb2e8f9f7 940 #define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
<> 144:ef7eb2e8f9f7 941 #define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
<> 144:ef7eb2e8f9f7 942 #define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
<> 144:ef7eb2e8f9f7 943 #define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
<> 144:ef7eb2e8f9f7 944 #define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
<> 144:ef7eb2e8f9f7 945 #define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
<> 144:ef7eb2e8f9f7 946 #define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
<> 144:ef7eb2e8f9f7 947 #define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
<> 144:ef7eb2e8f9f7 948 #define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
<> 144:ef7eb2e8f9f7 949 #define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
<> 144:ef7eb2e8f9f7 950 #define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
<> 144:ef7eb2e8f9f7 951 /**
<> 144:ef7eb2e8f9f7 952 * @}
<> 144:ef7eb2e8f9f7 953 */
<> 144:ef7eb2e8f9f7 954
<> 144:ef7eb2e8f9f7 955 /** @defgroup DMA_Handle_index TIM DMA Handle Index
<> 144:ef7eb2e8f9f7 956 * @{
<> 144:ef7eb2e8f9f7 957 */
<> 144:ef7eb2e8f9f7 958 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */
<> 144:ef7eb2e8f9f7 959 #define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
<> 144:ef7eb2e8f9f7 960 #define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
<> 144:ef7eb2e8f9f7 961 #define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
<> 144:ef7eb2e8f9f7 962 #define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
<> 144:ef7eb2e8f9f7 963 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */
<> 144:ef7eb2e8f9f7 964 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */
<> 144:ef7eb2e8f9f7 965 /**
<> 144:ef7eb2e8f9f7 966 * @}
<> 144:ef7eb2e8f9f7 967 */
<> 144:ef7eb2e8f9f7 968
<> 144:ef7eb2e8f9f7 969 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State
<> 144:ef7eb2e8f9f7 970 * @{
<> 144:ef7eb2e8f9f7 971 */
<> 144:ef7eb2e8f9f7 972 #define TIM_CCx_ENABLE ((uint32_t)0x0001)
<> 144:ef7eb2e8f9f7 973 #define TIM_CCx_DISABLE ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 974 #define TIM_CCxN_ENABLE ((uint32_t)0x0004)
<> 144:ef7eb2e8f9f7 975 #define TIM_CCxN_DISABLE ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 976 /**
<> 144:ef7eb2e8f9f7 977 * @}
<> 144:ef7eb2e8f9f7 978 */
<> 144:ef7eb2e8f9f7 979
<> 144:ef7eb2e8f9f7 980 /** @defgroup TIM_Break_System TIM Break System
<> 144:ef7eb2e8f9f7 981 * @{
<> 144:ef7eb2e8f9f7 982 */
<> 144:ef7eb2e8f9f7 983 #define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */
<> 144:ef7eb2e8f9f7 984 #define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */
<> 144:ef7eb2e8f9f7 985 #define TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal with Break Input of TIM1/8/15/16/17 */
<> 144:ef7eb2e8f9f7 986 #define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/15/16/17 */
<> 144:ef7eb2e8f9f7 987 /**
<> 144:ef7eb2e8f9f7 988 * @}
<> 144:ef7eb2e8f9f7 989 */
<> 144:ef7eb2e8f9f7 990
<> 144:ef7eb2e8f9f7 991 /**
<> 144:ef7eb2e8f9f7 992 * @}
<> 144:ef7eb2e8f9f7 993 */
<> 144:ef7eb2e8f9f7 994 /* End of exported constants -------------------------------------------------*/
<> 144:ef7eb2e8f9f7 995
<> 144:ef7eb2e8f9f7 996 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 997 /** @defgroup TIM_Exported_Macros TIM Exported Macros
<> 144:ef7eb2e8f9f7 998 * @{
<> 144:ef7eb2e8f9f7 999 */
<> 144:ef7eb2e8f9f7 1000
<> 144:ef7eb2e8f9f7 1001 /** @brief Reset TIM handle state.
<> 144:ef7eb2e8f9f7 1002 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 1003 * @retval None
<> 144:ef7eb2e8f9f7 1004 */
<> 144:ef7eb2e8f9f7 1005 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 1006
<> 144:ef7eb2e8f9f7 1007 /**
<> 144:ef7eb2e8f9f7 1008 * @brief Enable the TIM peripheral.
<> 144:ef7eb2e8f9f7 1009 * @param __HANDLE__: TIM handle
<> 144:ef7eb2e8f9f7 1010 * @retval None
<> 144:ef7eb2e8f9f7 1011 */
<> 144:ef7eb2e8f9f7 1012 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
<> 144:ef7eb2e8f9f7 1013
<> 144:ef7eb2e8f9f7 1014 /**
<> 144:ef7eb2e8f9f7 1015 * @brief Enable the TIM main Output.
<> 144:ef7eb2e8f9f7 1016 * @param __HANDLE__: TIM handle
<> 144:ef7eb2e8f9f7 1017 * @retval None
<> 144:ef7eb2e8f9f7 1018 */
<> 144:ef7eb2e8f9f7 1019 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
<> 144:ef7eb2e8f9f7 1020
<> 144:ef7eb2e8f9f7 1021 /**
<> 144:ef7eb2e8f9f7 1022 * @brief Disable the TIM peripheral.
<> 144:ef7eb2e8f9f7 1023 * @param __HANDLE__: TIM handle
<> 144:ef7eb2e8f9f7 1024 * @retval None
<> 144:ef7eb2e8f9f7 1025 */
<> 144:ef7eb2e8f9f7 1026 #define __HAL_TIM_DISABLE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 1027 do { \
<> 144:ef7eb2e8f9f7 1028 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
<> 144:ef7eb2e8f9f7 1029 { \
<> 144:ef7eb2e8f9f7 1030 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
<> 144:ef7eb2e8f9f7 1031 { \
<> 144:ef7eb2e8f9f7 1032 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
<> 144:ef7eb2e8f9f7 1033 } \
<> 144:ef7eb2e8f9f7 1034 } \
<> 144:ef7eb2e8f9f7 1035 } while(0)
<> 144:ef7eb2e8f9f7 1036
<> 144:ef7eb2e8f9f7 1037 /**
<> 144:ef7eb2e8f9f7 1038 * @brief Disable the TIM main Output.
<> 144:ef7eb2e8f9f7 1039 * @param __HANDLE__: TIM handle
<> 144:ef7eb2e8f9f7 1040 * @retval None
<> 144:ef7eb2e8f9f7 1041 * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
<> 144:ef7eb2e8f9f7 1042 */
<> 144:ef7eb2e8f9f7 1043 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 1044 do { \
<> 144:ef7eb2e8f9f7 1045 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
<> 144:ef7eb2e8f9f7 1046 { \
<> 144:ef7eb2e8f9f7 1047 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
<> 144:ef7eb2e8f9f7 1048 { \
<> 144:ef7eb2e8f9f7 1049 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
<> 144:ef7eb2e8f9f7 1050 } \
<> 144:ef7eb2e8f9f7 1051 } \
<> 144:ef7eb2e8f9f7 1052 } while(0)
<> 144:ef7eb2e8f9f7 1053
<> 144:ef7eb2e8f9f7 1054 /** @brief Enable the specified TIM interrupt.
<> 144:ef7eb2e8f9f7 1055 * @param __HANDLE__: specifies the TIM Handle.
<> 144:ef7eb2e8f9f7 1056 * @param __INTERRUPT__: specifies the TIM interrupt source to enable.
<> 144:ef7eb2e8f9f7 1057 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1058 * @arg TIM_IT_UPDATE: Update interrupt
<> 144:ef7eb2e8f9f7 1059 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
<> 144:ef7eb2e8f9f7 1060 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
<> 144:ef7eb2e8f9f7 1061 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
<> 144:ef7eb2e8f9f7 1062 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
<> 144:ef7eb2e8f9f7 1063 * @arg TIM_IT_COM: Commutation interrupt
<> 144:ef7eb2e8f9f7 1064 * @arg TIM_IT_TRIGGER: Trigger interrupt
<> 144:ef7eb2e8f9f7 1065 * @arg TIM_IT_BREAK: Break interrupt
<> 144:ef7eb2e8f9f7 1066 * @retval None
<> 144:ef7eb2e8f9f7 1067 */
<> 144:ef7eb2e8f9f7 1068 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1069
<> 144:ef7eb2e8f9f7 1070
<> 144:ef7eb2e8f9f7 1071 /** @brief Disable the specified TIM interrupt.
<> 144:ef7eb2e8f9f7 1072 * @param __HANDLE__: specifies the TIM Handle.
<> 144:ef7eb2e8f9f7 1073 * @param __INTERRUPT__: specifies the TIM interrupt source to disable.
<> 144:ef7eb2e8f9f7 1074 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1075 * @arg TIM_IT_UPDATE: Update interrupt
<> 144:ef7eb2e8f9f7 1076 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
<> 144:ef7eb2e8f9f7 1077 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
<> 144:ef7eb2e8f9f7 1078 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
<> 144:ef7eb2e8f9f7 1079 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
<> 144:ef7eb2e8f9f7 1080 * @arg TIM_IT_COM: Commutation interrupt
<> 144:ef7eb2e8f9f7 1081 * @arg TIM_IT_TRIGGER: Trigger interrupt
<> 144:ef7eb2e8f9f7 1082 * @arg TIM_IT_BREAK: Break interrupt
<> 144:ef7eb2e8f9f7 1083 * @retval None
<> 144:ef7eb2e8f9f7 1084 */
<> 144:ef7eb2e8f9f7 1085 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1086
<> 144:ef7eb2e8f9f7 1087 /** @brief Enable the specified DMA request.
<> 144:ef7eb2e8f9f7 1088 * @param __HANDLE__: specifies the TIM Handle.
<> 144:ef7eb2e8f9f7 1089 * @param __DMA__: specifies the TIM DMA request to enable.
<> 144:ef7eb2e8f9f7 1090 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1091 * @arg TIM_DMA_UPDATE: Update DMA request
<> 144:ef7eb2e8f9f7 1092 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
<> 144:ef7eb2e8f9f7 1093 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
<> 144:ef7eb2e8f9f7 1094 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
<> 144:ef7eb2e8f9f7 1095 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
<> 144:ef7eb2e8f9f7 1096 * @arg TIM_DMA_COM: Commutation DMA request
<> 144:ef7eb2e8f9f7 1097 * @arg TIM_DMA_TRIGGER: Trigger DMA request
<> 144:ef7eb2e8f9f7 1098 * @arg TIM_DMA_BREAK: Break DMA request
<> 144:ef7eb2e8f9f7 1099 * @retval None
<> 144:ef7eb2e8f9f7 1100 */
<> 144:ef7eb2e8f9f7 1101 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
<> 144:ef7eb2e8f9f7 1102
<> 144:ef7eb2e8f9f7 1103 /** @brief Disable the specified DMA request.
<> 144:ef7eb2e8f9f7 1104 * @param __HANDLE__: specifies the TIM Handle.
<> 144:ef7eb2e8f9f7 1105 * @param __DMA__: specifies the TIM DMA request to disable.
<> 144:ef7eb2e8f9f7 1106 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1107 * @arg TIM_DMA_UPDATE: Update DMA request
<> 144:ef7eb2e8f9f7 1108 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
<> 144:ef7eb2e8f9f7 1109 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
<> 144:ef7eb2e8f9f7 1110 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
<> 144:ef7eb2e8f9f7 1111 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
<> 144:ef7eb2e8f9f7 1112 * @arg TIM_DMA_COM: Commutation DMA request
<> 144:ef7eb2e8f9f7 1113 * @arg TIM_DMA_TRIGGER: Trigger DMA request
<> 144:ef7eb2e8f9f7 1114 * @arg TIM_DMA_BREAK: Break DMA request
<> 144:ef7eb2e8f9f7 1115 * @retval None
<> 144:ef7eb2e8f9f7 1116 */
<> 144:ef7eb2e8f9f7 1117 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
<> 144:ef7eb2e8f9f7 1118
<> 144:ef7eb2e8f9f7 1119 /** @brief Check whether the specified TIM interrupt flag is set or not.
<> 144:ef7eb2e8f9f7 1120 * @param __HANDLE__: specifies the TIM Handle.
<> 144:ef7eb2e8f9f7 1121 * @param __FLAG__: specifies the TIM interrupt flag to check.
<> 144:ef7eb2e8f9f7 1122 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1123 * @arg TIM_FLAG_UPDATE: Update interrupt flag
<> 144:ef7eb2e8f9f7 1124 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
<> 144:ef7eb2e8f9f7 1125 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
<> 144:ef7eb2e8f9f7 1126 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
<> 144:ef7eb2e8f9f7 1127 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
<> 144:ef7eb2e8f9f7 1128 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
<> 144:ef7eb2e8f9f7 1129 * @arg TIM_FLAG_CC6: Compare 5 interrupt flag
<> 144:ef7eb2e8f9f7 1130 * @arg TIM_FLAG_COM: Commutation interrupt flag
<> 144:ef7eb2e8f9f7 1131 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
<> 144:ef7eb2e8f9f7 1132 * @arg TIM_FLAG_BREAK: Break interrupt flag
<> 144:ef7eb2e8f9f7 1133 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
<> 144:ef7eb2e8f9f7 1134 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
<> 144:ef7eb2e8f9f7 1135 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
<> 144:ef7eb2e8f9f7 1136 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
<> 144:ef7eb2e8f9f7 1137 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
<> 144:ef7eb2e8f9f7 1138 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
<> 144:ef7eb2e8f9f7 1139 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 1140 */
<> 144:ef7eb2e8f9f7 1141 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 1142
<> 144:ef7eb2e8f9f7 1143 /** @brief Clear the specified TIM interrupt flag.
<> 144:ef7eb2e8f9f7 1144 * @param __HANDLE__: specifies the TIM Handle.
<> 144:ef7eb2e8f9f7 1145 * @param __FLAG__: specifies the TIM interrupt flag to clear.
<> 144:ef7eb2e8f9f7 1146 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1147 * @arg TIM_FLAG_UPDATE: Update interrupt flag
<> 144:ef7eb2e8f9f7 1148 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
<> 144:ef7eb2e8f9f7 1149 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
<> 144:ef7eb2e8f9f7 1150 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
<> 144:ef7eb2e8f9f7 1151 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
<> 144:ef7eb2e8f9f7 1152 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
<> 144:ef7eb2e8f9f7 1153 * @arg TIM_FLAG_CC6: Compare 5 interrupt flag
<> 144:ef7eb2e8f9f7 1154 * @arg TIM_FLAG_COM: Commutation interrupt flag
<> 144:ef7eb2e8f9f7 1155 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
<> 144:ef7eb2e8f9f7 1156 * @arg TIM_FLAG_BREAK: Break interrupt flag
<> 144:ef7eb2e8f9f7 1157 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
<> 144:ef7eb2e8f9f7 1158 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
<> 144:ef7eb2e8f9f7 1159 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
<> 144:ef7eb2e8f9f7 1160 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
<> 144:ef7eb2e8f9f7 1161 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
<> 144:ef7eb2e8f9f7 1162 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
<> 144:ef7eb2e8f9f7 1163 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 1164 */
<> 144:ef7eb2e8f9f7 1165 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
<> 144:ef7eb2e8f9f7 1166
<> 144:ef7eb2e8f9f7 1167 /**
<> 144:ef7eb2e8f9f7 1168 * @brief Check whether the specified TIM interrupt source is enabled or not.
<> 144:ef7eb2e8f9f7 1169 * @param __HANDLE__: TIM handle
<> 144:ef7eb2e8f9f7 1170 * @param __INTERRUPT__: specifies the TIM interrupt source to check.
<> 144:ef7eb2e8f9f7 1171 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1172 * @arg TIM_IT_UPDATE: Update interrupt
<> 144:ef7eb2e8f9f7 1173 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
<> 144:ef7eb2e8f9f7 1174 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
<> 144:ef7eb2e8f9f7 1175 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
<> 144:ef7eb2e8f9f7 1176 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
<> 144:ef7eb2e8f9f7 1177 * @arg TIM_IT_COM: Commutation interrupt
<> 144:ef7eb2e8f9f7 1178 * @arg TIM_IT_TRIGGER: Trigger interrupt
<> 144:ef7eb2e8f9f7 1179 * @arg TIM_IT_BREAK: Break interrupt
<> 144:ef7eb2e8f9f7 1180 * @retval The state of TIM_IT (SET or RESET).
<> 144:ef7eb2e8f9f7 1181 */
<> 144:ef7eb2e8f9f7 1182 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 144:ef7eb2e8f9f7 1183
<> 144:ef7eb2e8f9f7 1184 /** @brief Clear the TIM interrupt pending bits.
<> 144:ef7eb2e8f9f7 1185 * @param __HANDLE__: TIM handle
<> 144:ef7eb2e8f9f7 1186 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
<> 144:ef7eb2e8f9f7 1187 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1188 * @arg TIM_IT_UPDATE: Update interrupt
<> 144:ef7eb2e8f9f7 1189 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
<> 144:ef7eb2e8f9f7 1190 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
<> 144:ef7eb2e8f9f7 1191 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
<> 144:ef7eb2e8f9f7 1192 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
<> 144:ef7eb2e8f9f7 1193 * @arg TIM_IT_COM: Commutation interrupt
<> 144:ef7eb2e8f9f7 1194 * @arg TIM_IT_TRIGGER: Trigger interrupt
<> 144:ef7eb2e8f9f7 1195 * @arg TIM_IT_BREAK: Break interrupt
<> 144:ef7eb2e8f9f7 1196 * @retval None
<> 144:ef7eb2e8f9f7 1197 */
<> 144:ef7eb2e8f9f7 1198 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1199
<> 144:ef7eb2e8f9f7 1200 /**
<> 144:ef7eb2e8f9f7 1201 * @brief Indicates whether or not the TIM Counter is used as downcounter.
<> 144:ef7eb2e8f9f7 1202 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 1203 * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
<> 144:ef7eb2e8f9f7 1204 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
<> 144:ef7eb2e8f9f7 1205 mode.
<> 144:ef7eb2e8f9f7 1206 */
<> 144:ef7eb2e8f9f7 1207 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
<> 144:ef7eb2e8f9f7 1208
<> 144:ef7eb2e8f9f7 1209
<> 144:ef7eb2e8f9f7 1210 /**
<> 144:ef7eb2e8f9f7 1211 * @brief Set the TIM Prescaler on runtime.
<> 144:ef7eb2e8f9f7 1212 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 1213 * @param __PRESC__: specifies the Prescaler new value.
<> 144:ef7eb2e8f9f7 1214 * @retval None
<> 144:ef7eb2e8f9f7 1215 */
<> 144:ef7eb2e8f9f7 1216 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
<> 144:ef7eb2e8f9f7 1217
<> 144:ef7eb2e8f9f7 1218 /**
<> 144:ef7eb2e8f9f7 1219 * @brief Set the TIM Counter Register value on runtime.
<> 144:ef7eb2e8f9f7 1220 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 1221 * @param __COUNTER__: specifies the Counter register new value.
<> 144:ef7eb2e8f9f7 1222 * @retval None
<> 144:ef7eb2e8f9f7 1223 */
<> 144:ef7eb2e8f9f7 1224 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
<> 144:ef7eb2e8f9f7 1225
<> 144:ef7eb2e8f9f7 1226 /**
<> 144:ef7eb2e8f9f7 1227 * @brief Get the TIM Counter Register value on runtime.
<> 144:ef7eb2e8f9f7 1228 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 1229 * @retval None
<> 144:ef7eb2e8f9f7 1230 */
<> 144:ef7eb2e8f9f7 1231 #define __HAL_TIM_GET_COUNTER(__HANDLE__) \
<> 144:ef7eb2e8f9f7 1232 ((__HANDLE__)->Instance->CNT)
<> 144:ef7eb2e8f9f7 1233
<> 144:ef7eb2e8f9f7 1234 /**
<> 144:ef7eb2e8f9f7 1235 * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
<> 144:ef7eb2e8f9f7 1236 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 1237 * @param __AUTORELOAD__: specifies the Counter register new value.
<> 144:ef7eb2e8f9f7 1238 * @retval None
<> 144:ef7eb2e8f9f7 1239 */
<> 144:ef7eb2e8f9f7 1240 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
<> 144:ef7eb2e8f9f7 1241 do{ \
<> 144:ef7eb2e8f9f7 1242 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
<> 144:ef7eb2e8f9f7 1243 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
<> 144:ef7eb2e8f9f7 1244 } while(0)
<> 144:ef7eb2e8f9f7 1245
<> 144:ef7eb2e8f9f7 1246 /**
<> 144:ef7eb2e8f9f7 1247 * @brief Get the TIM Autoreload Register value on runtime.
<> 144:ef7eb2e8f9f7 1248 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 1249 * @retval None
<> 144:ef7eb2e8f9f7 1250 */
<> 144:ef7eb2e8f9f7 1251 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
<> 144:ef7eb2e8f9f7 1252 ((__HANDLE__)->Instance->ARR)
<> 144:ef7eb2e8f9f7 1253
<> 144:ef7eb2e8f9f7 1254 /**
<> 144:ef7eb2e8f9f7 1255 * @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
<> 144:ef7eb2e8f9f7 1256 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 1257 * @param __CKD__: specifies the clock division value.
<> 144:ef7eb2e8f9f7 1258 * This parameter can be one of the following value:
<> 144:ef7eb2e8f9f7 1259 * @arg TIM_CLOCKDIVISION_DIV1
<> 144:ef7eb2e8f9f7 1260 * @arg TIM_CLOCKDIVISION_DIV2
<> 144:ef7eb2e8f9f7 1261 * @arg TIM_CLOCKDIVISION_DIV4
<> 144:ef7eb2e8f9f7 1262 * @retval None
<> 144:ef7eb2e8f9f7 1263 */
<> 144:ef7eb2e8f9f7 1264 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
<> 144:ef7eb2e8f9f7 1265 do{ \
<> 144:ef7eb2e8f9f7 1266 (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
<> 144:ef7eb2e8f9f7 1267 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
<> 144:ef7eb2e8f9f7 1268 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
<> 144:ef7eb2e8f9f7 1269 } while(0)
<> 144:ef7eb2e8f9f7 1270
<> 144:ef7eb2e8f9f7 1271 /**
<> 144:ef7eb2e8f9f7 1272 * @brief Get the TIM Clock Division value on runtime.
<> 144:ef7eb2e8f9f7 1273 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 1274 * @retval None
<> 144:ef7eb2e8f9f7 1275 */
<> 144:ef7eb2e8f9f7 1276 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
<> 144:ef7eb2e8f9f7 1277 ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
<> 144:ef7eb2e8f9f7 1278
<> 144:ef7eb2e8f9f7 1279 /**
<> 144:ef7eb2e8f9f7 1280 * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
<> 144:ef7eb2e8f9f7 1281 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 1282 * @param __CHANNEL__: TIM Channels to be configured.
<> 144:ef7eb2e8f9f7 1283 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1284 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1285 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1286 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1287 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1288 * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
<> 144:ef7eb2e8f9f7 1289 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1290 * @arg TIM_ICPSC_DIV1: no prescaler
<> 144:ef7eb2e8f9f7 1291 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
<> 144:ef7eb2e8f9f7 1292 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
<> 144:ef7eb2e8f9f7 1293 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
<> 144:ef7eb2e8f9f7 1294 * @retval None
<> 144:ef7eb2e8f9f7 1295 */
<> 144:ef7eb2e8f9f7 1296 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
<> 144:ef7eb2e8f9f7 1297 do{ \
<> 144:ef7eb2e8f9f7 1298 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
<> 144:ef7eb2e8f9f7 1299 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
<> 144:ef7eb2e8f9f7 1300 } while(0)
<> 144:ef7eb2e8f9f7 1301
<> 144:ef7eb2e8f9f7 1302 /**
<> 144:ef7eb2e8f9f7 1303 * @brief Get the TIM Input Capture prescaler on runtime.
<> 144:ef7eb2e8f9f7 1304 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 1305 * @param __CHANNEL__: TIM Channels to be configured.
<> 144:ef7eb2e8f9f7 1306 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1307 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
<> 144:ef7eb2e8f9f7 1308 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
<> 144:ef7eb2e8f9f7 1309 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
<> 144:ef7eb2e8f9f7 1310 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
<> 144:ef7eb2e8f9f7 1311 * @retval None
<> 144:ef7eb2e8f9f7 1312 */
<> 144:ef7eb2e8f9f7 1313 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
<> 144:ef7eb2e8f9f7 1314 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
<> 144:ef7eb2e8f9f7 1315 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
<> 144:ef7eb2e8f9f7 1316 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
<> 144:ef7eb2e8f9f7 1317 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
<> 144:ef7eb2e8f9f7 1318
<> 144:ef7eb2e8f9f7 1319 /**
<> 144:ef7eb2e8f9f7 1320 * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
<> 144:ef7eb2e8f9f7 1321 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 1322 * @param __CHANNEL__: TIM Channels to be configured.
<> 144:ef7eb2e8f9f7 1323 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1324 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1325 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1326 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1327 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1328 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
<> 144:ef7eb2e8f9f7 1329 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
<> 144:ef7eb2e8f9f7 1330 * @param __COMPARE__: specifies the Capture Compare register new value.
<> 144:ef7eb2e8f9f7 1331 * @retval None
<> 144:ef7eb2e8f9f7 1332 */
<> 144:ef7eb2e8f9f7 1333 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
<> 144:ef7eb2e8f9f7 1334 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
<> 144:ef7eb2e8f9f7 1335 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
<> 144:ef7eb2e8f9f7 1336 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
<> 144:ef7eb2e8f9f7 1337 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
<> 144:ef7eb2e8f9f7 1338 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
<> 144:ef7eb2e8f9f7 1339 ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
<> 144:ef7eb2e8f9f7 1340
<> 144:ef7eb2e8f9f7 1341 /**
<> 144:ef7eb2e8f9f7 1342 * @brief Get the TIM Capture Compare Register value on runtime.
<> 144:ef7eb2e8f9f7 1343 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 1344 * @param __CHANNEL__: TIM Channel associated with the capture compare register
<> 144:ef7eb2e8f9f7 1345 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1346 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
<> 144:ef7eb2e8f9f7 1347 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
<> 144:ef7eb2e8f9f7 1348 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
<> 144:ef7eb2e8f9f7 1349 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
<> 144:ef7eb2e8f9f7 1350 * @arg TIM_CHANNEL_5: get capture/compare 5 register value
<> 144:ef7eb2e8f9f7 1351 * @arg TIM_CHANNEL_6: get capture/compare 6 register value
<> 144:ef7eb2e8f9f7 1352 * @retval None
<> 144:ef7eb2e8f9f7 1353 */
<> 144:ef7eb2e8f9f7 1354 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
<> 144:ef7eb2e8f9f7 1355 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
<> 144:ef7eb2e8f9f7 1356 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
<> 144:ef7eb2e8f9f7 1357 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
<> 144:ef7eb2e8f9f7 1358 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
<> 144:ef7eb2e8f9f7 1359 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
<> 144:ef7eb2e8f9f7 1360 ((__HANDLE__)->Instance->CCR6))
<> 144:ef7eb2e8f9f7 1361
<> 144:ef7eb2e8f9f7 1362 /**
<> 144:ef7eb2e8f9f7 1363 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
<> 144:ef7eb2e8f9f7 1364 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 1365 * @note When the USR bit of the TIMx_CR1 register is set, only counter
<> 144:ef7eb2e8f9f7 1366 * overflow/underflow generates an update interrupt or DMA request (if
<> 144:ef7eb2e8f9f7 1367 * enabled)
<> 144:ef7eb2e8f9f7 1368 * @retval None
<> 144:ef7eb2e8f9f7 1369 */
<> 144:ef7eb2e8f9f7 1370 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 1371 ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
<> 144:ef7eb2e8f9f7 1372
<> 144:ef7eb2e8f9f7 1373 /**
<> 144:ef7eb2e8f9f7 1374 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
<> 144:ef7eb2e8f9f7 1375 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 1376 * @note When the USR bit of the TIMx_CR1 register is reset, any of the
<> 144:ef7eb2e8f9f7 1377 * following events generate an update interrupt or DMA request (if
<> 144:ef7eb2e8f9f7 1378 * enabled):
<> 144:ef7eb2e8f9f7 1379 * _ Counter overflow underflow
<> 144:ef7eb2e8f9f7 1380 * _ Setting the UG bit
<> 144:ef7eb2e8f9f7 1381 * _ Update generation through the slave mode controller
<> 144:ef7eb2e8f9f7 1382 * @retval None
<> 144:ef7eb2e8f9f7 1383 */
<> 144:ef7eb2e8f9f7 1384 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 1385 ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
<> 144:ef7eb2e8f9f7 1386
<> 144:ef7eb2e8f9f7 1387 /**
<> 144:ef7eb2e8f9f7 1388 * @brief Set the TIM Capture x input polarity on runtime.
<> 144:ef7eb2e8f9f7 1389 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 1390 * @param __CHANNEL__: TIM Channels to be configured.
<> 144:ef7eb2e8f9f7 1391 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1392 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1393 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1394 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1395 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1396 * @param __POLARITY__: Polarity for TIx source
<> 144:ef7eb2e8f9f7 1397 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
<> 144:ef7eb2e8f9f7 1398 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
<> 144:ef7eb2e8f9f7 1399 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
<> 144:ef7eb2e8f9f7 1400 * @retval None
<> 144:ef7eb2e8f9f7 1401 */
<> 144:ef7eb2e8f9f7 1402 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
<> 144:ef7eb2e8f9f7 1403 do{ \
<> 144:ef7eb2e8f9f7 1404 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
<> 144:ef7eb2e8f9f7 1405 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
<> 144:ef7eb2e8f9f7 1406 }while(0)
<> 144:ef7eb2e8f9f7 1407
<> 144:ef7eb2e8f9f7 1408 /**
<> 144:ef7eb2e8f9f7 1409 * @}
<> 144:ef7eb2e8f9f7 1410 */
<> 144:ef7eb2e8f9f7 1411 /* End of exported macros ----------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1412
<> 144:ef7eb2e8f9f7 1413 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1414 /** @defgroup TIM_Private_Constants TIM Private Constants
<> 144:ef7eb2e8f9f7 1415 * @{
<> 144:ef7eb2e8f9f7 1416 */
<> 144:ef7eb2e8f9f7 1417 /* The counter of a timer instance is disabled only if all the CCx and CCxN
<> 144:ef7eb2e8f9f7 1418 channels have been disabled */
<> 144:ef7eb2e8f9f7 1419 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
<> 144:ef7eb2e8f9f7 1420 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
<> 144:ef7eb2e8f9f7 1421 /**
<> 144:ef7eb2e8f9f7 1422 * @}
<> 144:ef7eb2e8f9f7 1423 */
<> 144:ef7eb2e8f9f7 1424 /* End of private constants --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1425
<> 144:ef7eb2e8f9f7 1426 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1427 /** @defgroup TIM_Private_Macros TIM Private Macros
<> 144:ef7eb2e8f9f7 1428 * @{
<> 144:ef7eb2e8f9f7 1429 */
<> 144:ef7eb2e8f9f7 1430
<> 144:ef7eb2e8f9f7 1431 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \
<> 144:ef7eb2e8f9f7 1432 ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
<> 144:ef7eb2e8f9f7 1433 ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
<> 144:ef7eb2e8f9f7 1434
<> 144:ef7eb2e8f9f7 1435 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
<> 144:ef7eb2e8f9f7 1436 ((__BASE__) == TIM_DMABASE_CR2) || \
<> 144:ef7eb2e8f9f7 1437 ((__BASE__) == TIM_DMABASE_SMCR) || \
<> 144:ef7eb2e8f9f7 1438 ((__BASE__) == TIM_DMABASE_DIER) || \
<> 144:ef7eb2e8f9f7 1439 ((__BASE__) == TIM_DMABASE_SR) || \
<> 144:ef7eb2e8f9f7 1440 ((__BASE__) == TIM_DMABASE_EGR) || \
<> 144:ef7eb2e8f9f7 1441 ((__BASE__) == TIM_DMABASE_CCMR1) || \
<> 144:ef7eb2e8f9f7 1442 ((__BASE__) == TIM_DMABASE_CCMR2) || \
<> 144:ef7eb2e8f9f7 1443 ((__BASE__) == TIM_DMABASE_CCER) || \
<> 144:ef7eb2e8f9f7 1444 ((__BASE__) == TIM_DMABASE_CNT) || \
<> 144:ef7eb2e8f9f7 1445 ((__BASE__) == TIM_DMABASE_PSC) || \
<> 144:ef7eb2e8f9f7 1446 ((__BASE__) == TIM_DMABASE_ARR) || \
<> 144:ef7eb2e8f9f7 1447 ((__BASE__) == TIM_DMABASE_RCR) || \
<> 144:ef7eb2e8f9f7 1448 ((__BASE__) == TIM_DMABASE_CCR1) || \
<> 144:ef7eb2e8f9f7 1449 ((__BASE__) == TIM_DMABASE_CCR2) || \
<> 144:ef7eb2e8f9f7 1450 ((__BASE__) == TIM_DMABASE_CCR3) || \
<> 144:ef7eb2e8f9f7 1451 ((__BASE__) == TIM_DMABASE_CCR4) || \
<> 144:ef7eb2e8f9f7 1452 ((__BASE__) == TIM_DMABASE_BDTR) || \
<> 144:ef7eb2e8f9f7 1453 ((__BASE__) == TIM_DMABASE_CCMR3) || \
<> 144:ef7eb2e8f9f7 1454 ((__BASE__) == TIM_DMABASE_CCR5) || \
<> 144:ef7eb2e8f9f7 1455 ((__BASE__) == TIM_DMABASE_CCR6) || \
<> 144:ef7eb2e8f9f7 1456 ((__BASE__) == TIM_DMABASE_OR1) || \
<> 144:ef7eb2e8f9f7 1457 ((__BASE__) == TIM_DMABASE_OR2) || \
<> 144:ef7eb2e8f9f7 1458 ((__BASE__) == TIM_DMABASE_OR3))
<> 144:ef7eb2e8f9f7 1459
<> 144:ef7eb2e8f9f7 1460
<> 144:ef7eb2e8f9f7 1461 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00) == 0x00000000) && ((__SOURCE__) != 0x00000000))
<> 144:ef7eb2e8f9f7 1462
<> 144:ef7eb2e8f9f7 1463
<> 144:ef7eb2e8f9f7 1464 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
<> 144:ef7eb2e8f9f7 1465 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
<> 144:ef7eb2e8f9f7 1466 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
<> 144:ef7eb2e8f9f7 1467 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
<> 144:ef7eb2e8f9f7 1468 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
<> 144:ef7eb2e8f9f7 1469
<> 144:ef7eb2e8f9f7 1470 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
<> 144:ef7eb2e8f9f7 1471 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
<> 144:ef7eb2e8f9f7 1472 ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
<> 144:ef7eb2e8f9f7 1473
<> 144:ef7eb2e8f9f7 1474 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
<> 144:ef7eb2e8f9f7 1475 ((__STATE__) == TIM_OCFAST_ENABLE))
<> 144:ef7eb2e8f9f7 1476
<> 144:ef7eb2e8f9f7 1477 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
<> 144:ef7eb2e8f9f7 1478 ((__POLARITY__) == TIM_OCPOLARITY_LOW))
<> 144:ef7eb2e8f9f7 1479
<> 144:ef7eb2e8f9f7 1480 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
<> 144:ef7eb2e8f9f7 1481 ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
<> 144:ef7eb2e8f9f7 1482
<> 144:ef7eb2e8f9f7 1483 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \
<> 144:ef7eb2e8f9f7 1484 ((__STATE__) == TIM_OCIDLESTATE_RESET))
<> 144:ef7eb2e8f9f7 1485
<> 144:ef7eb2e8f9f7 1486 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
<> 144:ef7eb2e8f9f7 1487 ((__STATE__) == TIM_OCNIDLESTATE_RESET))
<> 144:ef7eb2e8f9f7 1488
<> 144:ef7eb2e8f9f7 1489 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
<> 144:ef7eb2e8f9f7 1490 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
<> 144:ef7eb2e8f9f7 1491 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
<> 144:ef7eb2e8f9f7 1492
<> 144:ef7eb2e8f9f7 1493 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
<> 144:ef7eb2e8f9f7 1494 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
<> 144:ef7eb2e8f9f7 1495 ((__SELECTION__) == TIM_ICSELECTION_TRC))
<> 144:ef7eb2e8f9f7 1496
<> 144:ef7eb2e8f9f7 1497 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
<> 144:ef7eb2e8f9f7 1498 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
<> 144:ef7eb2e8f9f7 1499 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
<> 144:ef7eb2e8f9f7 1500 ((__PRESCALER__) == TIM_ICPSC_DIV8))
<> 144:ef7eb2e8f9f7 1501
<> 144:ef7eb2e8f9f7 1502 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
<> 144:ef7eb2e8f9f7 1503 ((__MODE__) == TIM_OPMODE_REPETITIVE))
<> 144:ef7eb2e8f9f7 1504
<> 144:ef7eb2e8f9f7 1505 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
<> 144:ef7eb2e8f9f7 1506 ((__MODE__) == TIM_ENCODERMODE_TI2) || \
<> 144:ef7eb2e8f9f7 1507 ((__MODE__) == TIM_ENCODERMODE_TI12))
<> 144:ef7eb2e8f9f7 1508
<> 144:ef7eb2e8f9f7 1509 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FF) == 0x00000000) && ((__SOURCE__) != 0x00000000))
<> 144:ef7eb2e8f9f7 1510
<> 144:ef7eb2e8f9f7 1511 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 1512 ((__CHANNEL__) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 1513 ((__CHANNEL__) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 1514 ((__CHANNEL__) == TIM_CHANNEL_4) || \
<> 144:ef7eb2e8f9f7 1515 ((__CHANNEL__) == TIM_CHANNEL_5) || \
<> 144:ef7eb2e8f9f7 1516 ((__CHANNEL__) == TIM_CHANNEL_6) || \
<> 144:ef7eb2e8f9f7 1517 ((__CHANNEL__) == TIM_CHANNEL_ALL))
<> 144:ef7eb2e8f9f7 1518
<> 144:ef7eb2e8f9f7 1519 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 1520 ((__CHANNEL__) == TIM_CHANNEL_2))
<> 144:ef7eb2e8f9f7 1521
<> 144:ef7eb2e8f9f7 1522 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 1523 ((__CHANNEL__) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 1524 ((__CHANNEL__) == TIM_CHANNEL_3))
<> 144:ef7eb2e8f9f7 1525
<> 144:ef7eb2e8f9f7 1526 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
<> 144:ef7eb2e8f9f7 1527 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
<> 144:ef7eb2e8f9f7 1528 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
<> 144:ef7eb2e8f9f7 1529 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
<> 144:ef7eb2e8f9f7 1530 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
<> 144:ef7eb2e8f9f7 1531 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
<> 144:ef7eb2e8f9f7 1532 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
<> 144:ef7eb2e8f9f7 1533 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
<> 144:ef7eb2e8f9f7 1534 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
<> 144:ef7eb2e8f9f7 1535 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
<> 144:ef7eb2e8f9f7 1536
<> 144:ef7eb2e8f9f7 1537 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
<> 144:ef7eb2e8f9f7 1538 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
<> 144:ef7eb2e8f9f7 1539 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
<> 144:ef7eb2e8f9f7 1540 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
<> 144:ef7eb2e8f9f7 1541 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
<> 144:ef7eb2e8f9f7 1542
<> 144:ef7eb2e8f9f7 1543 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
<> 144:ef7eb2e8f9f7 1544 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
<> 144:ef7eb2e8f9f7 1545 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
<> 144:ef7eb2e8f9f7 1546 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
<> 144:ef7eb2e8f9f7 1547
<> 144:ef7eb2e8f9f7 1548 #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
<> 144:ef7eb2e8f9f7 1549
<> 144:ef7eb2e8f9f7 1550 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
<> 144:ef7eb2e8f9f7 1551 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
<> 144:ef7eb2e8f9f7 1552
<> 144:ef7eb2e8f9f7 1553 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
<> 144:ef7eb2e8f9f7 1554 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
<> 144:ef7eb2e8f9f7 1555 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
<> 144:ef7eb2e8f9f7 1556 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
<> 144:ef7eb2e8f9f7 1557
<> 144:ef7eb2e8f9f7 1558 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
<> 144:ef7eb2e8f9f7 1559
<> 144:ef7eb2e8f9f7 1560
<> 144:ef7eb2e8f9f7 1561 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \
<> 144:ef7eb2e8f9f7 1562 ((__STATE__) == TIM_OSSR_DISABLE))
<> 144:ef7eb2e8f9f7 1563
<> 144:ef7eb2e8f9f7 1564 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \
<> 144:ef7eb2e8f9f7 1565 ((__STATE__) == TIM_OSSI_DISABLE))
<> 144:ef7eb2e8f9f7 1566
<> 144:ef7eb2e8f9f7 1567 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
<> 144:ef7eb2e8f9f7 1568 ((__LEVEL__) == TIM_LOCKLEVEL_1) || \
<> 144:ef7eb2e8f9f7 1569 ((__LEVEL__) == TIM_LOCKLEVEL_2) || \
<> 144:ef7eb2e8f9f7 1570 ((__LEVEL__) == TIM_LOCKLEVEL_3))
<> 144:ef7eb2e8f9f7 1571
<> 144:ef7eb2e8f9f7 1572 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xF)
<> 144:ef7eb2e8f9f7 1573
<> 144:ef7eb2e8f9f7 1574
<> 144:ef7eb2e8f9f7 1575 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
<> 144:ef7eb2e8f9f7 1576 ((__STATE__) == TIM_BREAK_DISABLE))
<> 144:ef7eb2e8f9f7 1577
<> 144:ef7eb2e8f9f7 1578 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
<> 144:ef7eb2e8f9f7 1579 ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
<> 144:ef7eb2e8f9f7 1580
<> 144:ef7eb2e8f9f7 1581 #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \
<> 144:ef7eb2e8f9f7 1582 ((__STATE__) == TIM_BREAK2_DISABLE))
<> 144:ef7eb2e8f9f7 1583
<> 144:ef7eb2e8f9f7 1584 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
<> 144:ef7eb2e8f9f7 1585 ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
<> 144:ef7eb2e8f9f7 1586
<> 144:ef7eb2e8f9f7 1587 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
<> 144:ef7eb2e8f9f7 1588 ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
<> 144:ef7eb2e8f9f7 1589
<> 144:ef7eb2e8f9f7 1590 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFF) == 0x00000000))
<> 144:ef7eb2e8f9f7 1591
<> 144:ef7eb2e8f9f7 1592 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
<> 144:ef7eb2e8f9f7 1593 ((__SOURCE__) == TIM_TRGO_ENABLE) || \
<> 144:ef7eb2e8f9f7 1594 ((__SOURCE__) == TIM_TRGO_UPDATE) || \
<> 144:ef7eb2e8f9f7 1595 ((__SOURCE__) == TIM_TRGO_OC1) || \
<> 144:ef7eb2e8f9f7 1596 ((__SOURCE__) == TIM_TRGO_OC1REF) || \
<> 144:ef7eb2e8f9f7 1597 ((__SOURCE__) == TIM_TRGO_OC2REF) || \
<> 144:ef7eb2e8f9f7 1598 ((__SOURCE__) == TIM_TRGO_OC3REF) || \
<> 144:ef7eb2e8f9f7 1599 ((__SOURCE__) == TIM_TRGO_OC4REF))
<> 144:ef7eb2e8f9f7 1600
<> 144:ef7eb2e8f9f7 1601 #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \
<> 144:ef7eb2e8f9f7 1602 ((__SOURCE__) == TIM_TRGO2_ENABLE) || \
<> 144:ef7eb2e8f9f7 1603 ((__SOURCE__) == TIM_TRGO2_UPDATE) || \
<> 144:ef7eb2e8f9f7 1604 ((__SOURCE__) == TIM_TRGO2_OC1) || \
<> 144:ef7eb2e8f9f7 1605 ((__SOURCE__) == TIM_TRGO2_OC1REF) || \
<> 144:ef7eb2e8f9f7 1606 ((__SOURCE__) == TIM_TRGO2_OC2REF) || \
<> 144:ef7eb2e8f9f7 1607 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
<> 144:ef7eb2e8f9f7 1608 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
<> 144:ef7eb2e8f9f7 1609 ((__SOURCE__) == TIM_TRGO2_OC4REF) || \
<> 144:ef7eb2e8f9f7 1610 ((__SOURCE__) == TIM_TRGO2_OC5REF) || \
<> 144:ef7eb2e8f9f7 1611 ((__SOURCE__) == TIM_TRGO2_OC6REF) || \
<> 144:ef7eb2e8f9f7 1612 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
<> 144:ef7eb2e8f9f7 1613 ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
<> 144:ef7eb2e8f9f7 1614 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \
<> 144:ef7eb2e8f9f7 1615 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
<> 144:ef7eb2e8f9f7 1616 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \
<> 144:ef7eb2e8f9f7 1617 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
<> 144:ef7eb2e8f9f7 1618
<> 144:ef7eb2e8f9f7 1619 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
<> 144:ef7eb2e8f9f7 1620 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
<> 144:ef7eb2e8f9f7 1621
<> 144:ef7eb2e8f9f7 1622 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
<> 144:ef7eb2e8f9f7 1623 ((__MODE__) == TIM_SLAVEMODE_RESET) || \
<> 144:ef7eb2e8f9f7 1624 ((__MODE__) == TIM_SLAVEMODE_GATED) || \
<> 144:ef7eb2e8f9f7 1625 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
<> 144:ef7eb2e8f9f7 1626 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
<> 144:ef7eb2e8f9f7 1627 ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
<> 144:ef7eb2e8f9f7 1628
<> 144:ef7eb2e8f9f7 1629 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
<> 144:ef7eb2e8f9f7 1630 ((__MODE__) == TIM_OCMODE_PWM2) || \
<> 144:ef7eb2e8f9f7 1631 ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \
<> 144:ef7eb2e8f9f7 1632 ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \
<> 144:ef7eb2e8f9f7 1633 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
<> 144:ef7eb2e8f9f7 1634 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
<> 144:ef7eb2e8f9f7 1635
<> 144:ef7eb2e8f9f7 1636 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
<> 144:ef7eb2e8f9f7 1637 ((__MODE__) == TIM_OCMODE_ACTIVE) || \
<> 144:ef7eb2e8f9f7 1638 ((__MODE__) == TIM_OCMODE_INACTIVE) || \
<> 144:ef7eb2e8f9f7 1639 ((__MODE__) == TIM_OCMODE_TOGGLE) || \
<> 144:ef7eb2e8f9f7 1640 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
<> 144:ef7eb2e8f9f7 1641 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \
<> 144:ef7eb2e8f9f7 1642 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
<> 144:ef7eb2e8f9f7 1643 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
<> 144:ef7eb2e8f9f7 1644
<> 144:ef7eb2e8f9f7 1645 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
<> 144:ef7eb2e8f9f7 1646 ((__SELECTION__) == TIM_TS_ITR1) || \
<> 144:ef7eb2e8f9f7 1647 ((__SELECTION__) == TIM_TS_ITR2) || \
<> 144:ef7eb2e8f9f7 1648 ((__SELECTION__) == TIM_TS_ITR3) || \
<> 144:ef7eb2e8f9f7 1649 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
<> 144:ef7eb2e8f9f7 1650 ((__SELECTION__) == TIM_TS_TI1FP1) || \
<> 144:ef7eb2e8f9f7 1651 ((__SELECTION__) == TIM_TS_TI2FP2) || \
<> 144:ef7eb2e8f9f7 1652 ((__SELECTION__) == TIM_TS_ETRF))
<> 144:ef7eb2e8f9f7 1653
<> 144:ef7eb2e8f9f7 1654 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
<> 144:ef7eb2e8f9f7 1655 ((__SELECTION__) == TIM_TS_ITR1) || \
<> 144:ef7eb2e8f9f7 1656 ((__SELECTION__) == TIM_TS_ITR2) || \
<> 144:ef7eb2e8f9f7 1657 ((__SELECTION__) == TIM_TS_ITR3) || \
<> 144:ef7eb2e8f9f7 1658 ((__SELECTION__) == TIM_TS_NONE))
<> 144:ef7eb2e8f9f7 1659
<> 144:ef7eb2e8f9f7 1660
<> 144:ef7eb2e8f9f7 1661 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
<> 144:ef7eb2e8f9f7 1662 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
<> 144:ef7eb2e8f9f7 1663 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
<> 144:ef7eb2e8f9f7 1664 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
<> 144:ef7eb2e8f9f7 1665 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
<> 144:ef7eb2e8f9f7 1666
<> 144:ef7eb2e8f9f7 1667 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
<> 144:ef7eb2e8f9f7 1668 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
<> 144:ef7eb2e8f9f7 1669 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
<> 144:ef7eb2e8f9f7 1670 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
<> 144:ef7eb2e8f9f7 1671
<> 144:ef7eb2e8f9f7 1672 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
<> 144:ef7eb2e8f9f7 1673
<> 144:ef7eb2e8f9f7 1674 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
<> 144:ef7eb2e8f9f7 1675 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
<> 144:ef7eb2e8f9f7 1676
<> 144:ef7eb2e8f9f7 1677 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
<> 144:ef7eb2e8f9f7 1678 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
<> 144:ef7eb2e8f9f7 1679 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
<> 144:ef7eb2e8f9f7 1680 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
<> 144:ef7eb2e8f9f7 1681 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
<> 144:ef7eb2e8f9f7 1682 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
<> 144:ef7eb2e8f9f7 1683 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
<> 144:ef7eb2e8f9f7 1684 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
<> 144:ef7eb2e8f9f7 1685 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
<> 144:ef7eb2e8f9f7 1686 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
<> 144:ef7eb2e8f9f7 1687 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
<> 144:ef7eb2e8f9f7 1688 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
<> 144:ef7eb2e8f9f7 1689 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
<> 144:ef7eb2e8f9f7 1690 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
<> 144:ef7eb2e8f9f7 1691 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
<> 144:ef7eb2e8f9f7 1692 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
<> 144:ef7eb2e8f9f7 1693 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
<> 144:ef7eb2e8f9f7 1694 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
<> 144:ef7eb2e8f9f7 1695
<> 144:ef7eb2e8f9f7 1696 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
<> 144:ef7eb2e8f9f7 1697
<> 144:ef7eb2e8f9f7 1698 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFF)
<> 144:ef7eb2e8f9f7 1699
<> 144:ef7eb2e8f9f7 1700 #define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \
<> 144:ef7eb2e8f9f7 1701 ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \
<> 144:ef7eb2e8f9f7 1702 ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR) || \
<> 144:ef7eb2e8f9f7 1703 ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
<> 144:ef7eb2e8f9f7 1704
<> 144:ef7eb2e8f9f7 1705 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
<> 144:ef7eb2e8f9f7 1706 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
<> 144:ef7eb2e8f9f7 1707 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
<> 144:ef7eb2e8f9f7 1708 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
<> 144:ef7eb2e8f9f7 1709 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
<> 144:ef7eb2e8f9f7 1710
<> 144:ef7eb2e8f9f7 1711 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
<> 144:ef7eb2e8f9f7 1712 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
<> 144:ef7eb2e8f9f7 1713 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
<> 144:ef7eb2e8f9f7 1714 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
<> 144:ef7eb2e8f9f7 1715 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
<> 144:ef7eb2e8f9f7 1716
<> 144:ef7eb2e8f9f7 1717 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
<> 144:ef7eb2e8f9f7 1718 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
<> 144:ef7eb2e8f9f7 1719 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
<> 144:ef7eb2e8f9f7 1720 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
<> 144:ef7eb2e8f9f7 1721 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12))))
<> 144:ef7eb2e8f9f7 1722
<> 144:ef7eb2e8f9f7 1723 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
<> 144:ef7eb2e8f9f7 1724 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
<> 144:ef7eb2e8f9f7 1725 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
<> 144:ef7eb2e8f9f7 1726 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
<> 144:ef7eb2e8f9f7 1727 ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
<> 144:ef7eb2e8f9f7 1728
<> 144:ef7eb2e8f9f7 1729 /**
<> 144:ef7eb2e8f9f7 1730 * @}
<> 144:ef7eb2e8f9f7 1731 */
<> 144:ef7eb2e8f9f7 1732 /* End of private macros -----------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1733
<> 144:ef7eb2e8f9f7 1734 /* Include TIM HAL Extended module */
<> 144:ef7eb2e8f9f7 1735 #include "stm32l4xx_hal_tim_ex.h"
<> 144:ef7eb2e8f9f7 1736
<> 144:ef7eb2e8f9f7 1737 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1738 /** @addtogroup TIM_Exported_Functions TIM Exported Functions
<> 144:ef7eb2e8f9f7 1739 * @{
<> 144:ef7eb2e8f9f7 1740 */
<> 144:ef7eb2e8f9f7 1741
<> 144:ef7eb2e8f9f7 1742 /** @addtogroup TIM_Exported_Functions_Group1 Time Base functions
<> 144:ef7eb2e8f9f7 1743 * @brief Time Base functions
<> 144:ef7eb2e8f9f7 1744 * @{
<> 144:ef7eb2e8f9f7 1745 */
<> 144:ef7eb2e8f9f7 1746 /* Time Base functions ********************************************************/
<> 144:ef7eb2e8f9f7 1747 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1748 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1749 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1750 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1751 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 1752 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1753 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1754 /* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 1755 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1756 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1757 /* Non-Blocking mode: DMA */
<> 144:ef7eb2e8f9f7 1758 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
<> 144:ef7eb2e8f9f7 1759 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1760 /**
<> 144:ef7eb2e8f9f7 1761 * @}
<> 144:ef7eb2e8f9f7 1762 */
<> 144:ef7eb2e8f9f7 1763
<> 144:ef7eb2e8f9f7 1764 /** @addtogroup TIM_Exported_Functions_Group2 Time Output Compare functions
<> 144:ef7eb2e8f9f7 1765 * @brief Time Output Compare functions
<> 144:ef7eb2e8f9f7 1766 * @{
<> 144:ef7eb2e8f9f7 1767 */
<> 144:ef7eb2e8f9f7 1768 /* Timer Output Compare functions *********************************************/
<> 144:ef7eb2e8f9f7 1769 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1770 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1771 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1772 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1773 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 1774 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1775 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1776 /* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 1777 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1778 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1779 /* Non-Blocking mode: DMA */
<> 144:ef7eb2e8f9f7 1780 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
<> 144:ef7eb2e8f9f7 1781 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1782 /**
<> 144:ef7eb2e8f9f7 1783 * @}
<> 144:ef7eb2e8f9f7 1784 */
<> 144:ef7eb2e8f9f7 1785
<> 144:ef7eb2e8f9f7 1786 /** @addtogroup TIM_Exported_Functions_Group3 Time PWM functions
<> 144:ef7eb2e8f9f7 1787 * @brief Time PWM functions
<> 144:ef7eb2e8f9f7 1788 * @{
<> 144:ef7eb2e8f9f7 1789 */
<> 144:ef7eb2e8f9f7 1790 /* Timer PWM functions ********************************************************/
<> 144:ef7eb2e8f9f7 1791 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1792 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1793 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1794 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1795 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 1796 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1797 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1798 /* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 1799 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1800 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1801 /* Non-Blocking mode: DMA */
<> 144:ef7eb2e8f9f7 1802 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
<> 144:ef7eb2e8f9f7 1803 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1804 /**
<> 144:ef7eb2e8f9f7 1805 * @}
<> 144:ef7eb2e8f9f7 1806 */
<> 144:ef7eb2e8f9f7 1807
<> 144:ef7eb2e8f9f7 1808 /** @addtogroup TIM_Exported_Functions_Group4 Time Input Capture functions
<> 144:ef7eb2e8f9f7 1809 * @brief Time Input Capture functions
<> 144:ef7eb2e8f9f7 1810 * @{
<> 144:ef7eb2e8f9f7 1811 */
<> 144:ef7eb2e8f9f7 1812 /* Timer Input Capture functions **********************************************/
<> 144:ef7eb2e8f9f7 1813 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1814 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1815 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1816 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1817 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 1818 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1819 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1820 /* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 1821 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1822 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1823 /* Non-Blocking mode: DMA */
<> 144:ef7eb2e8f9f7 1824 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
<> 144:ef7eb2e8f9f7 1825 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1826 /**
<> 144:ef7eb2e8f9f7 1827 * @}
<> 144:ef7eb2e8f9f7 1828 */
<> 144:ef7eb2e8f9f7 1829
<> 144:ef7eb2e8f9f7 1830 /** @addtogroup TIM_Exported_Functions_Group5 Time One Pulse functions
<> 144:ef7eb2e8f9f7 1831 * @brief Time One Pulse functions
<> 144:ef7eb2e8f9f7 1832 * @{
<> 144:ef7eb2e8f9f7 1833 */
<> 144:ef7eb2e8f9f7 1834 /* Timer One Pulse functions **************************************************/
<> 144:ef7eb2e8f9f7 1835 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
<> 144:ef7eb2e8f9f7 1836 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1837 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1838 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1839 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 1840 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<> 144:ef7eb2e8f9f7 1841 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<> 144:ef7eb2e8f9f7 1842 /* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 1843 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<> 144:ef7eb2e8f9f7 1844 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<> 144:ef7eb2e8f9f7 1845 /**
<> 144:ef7eb2e8f9f7 1846 * @}
<> 144:ef7eb2e8f9f7 1847 */
<> 144:ef7eb2e8f9f7 1848
<> 144:ef7eb2e8f9f7 1849 /** @addtogroup TIM_Exported_Functions_Group6 Time Encoder functions
<> 144:ef7eb2e8f9f7 1850 * @brief Time Encoder functions
<> 144:ef7eb2e8f9f7 1851 * @{
<> 144:ef7eb2e8f9f7 1852 */
<> 144:ef7eb2e8f9f7 1853 /* Timer Encoder functions ****************************************************/
<> 144:ef7eb2e8f9f7 1854 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
<> 144:ef7eb2e8f9f7 1855 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1856 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1857 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1858 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 1859 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1860 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1861 /* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 1862 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1863 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1864 /* Non-Blocking mode: DMA */
<> 144:ef7eb2e8f9f7 1865 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
<> 144:ef7eb2e8f9f7 1866 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1867 /**
<> 144:ef7eb2e8f9f7 1868 * @}
<> 144:ef7eb2e8f9f7 1869 */
<> 144:ef7eb2e8f9f7 1870
<> 144:ef7eb2e8f9f7 1871 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
<> 144:ef7eb2e8f9f7 1872 * @brief IRQ handler management
<> 144:ef7eb2e8f9f7 1873 * @{
<> 144:ef7eb2e8f9f7 1874 */
<> 144:ef7eb2e8f9f7 1875 /* Interrupt Handler functions ***********************************************/
<> 144:ef7eb2e8f9f7 1876 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1877 /**
<> 144:ef7eb2e8f9f7 1878 * @}
<> 144:ef7eb2e8f9f7 1879 */
<> 144:ef7eb2e8f9f7 1880
<> 144:ef7eb2e8f9f7 1881 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
<> 144:ef7eb2e8f9f7 1882 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 1883 * @{
<> 144:ef7eb2e8f9f7 1884 */
<> 144:ef7eb2e8f9f7 1885 /* Control functions *********************************************************/
<> 144:ef7eb2e8f9f7 1886 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1887 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1888 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1889 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
<> 144:ef7eb2e8f9f7 1890 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1891 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
<> 144:ef7eb2e8f9f7 1892 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
<> 144:ef7eb2e8f9f7 1893 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
<> 144:ef7eb2e8f9f7 1894 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
<> 144:ef7eb2e8f9f7 1895 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
<> 144:ef7eb2e8f9f7 1896 uint32_t *BurstBuffer, uint32_t BurstLength);
<> 144:ef7eb2e8f9f7 1897 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
<> 144:ef7eb2e8f9f7 1898 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
<> 144:ef7eb2e8f9f7 1899 uint32_t *BurstBuffer, uint32_t BurstLength);
<> 144:ef7eb2e8f9f7 1900 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
<> 144:ef7eb2e8f9f7 1901 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
<> 144:ef7eb2e8f9f7 1902 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1903 /**
<> 144:ef7eb2e8f9f7 1904 * @}
<> 144:ef7eb2e8f9f7 1905 */
<> 144:ef7eb2e8f9f7 1906
<> 144:ef7eb2e8f9f7 1907 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
<> 144:ef7eb2e8f9f7 1908 * @brief TIM Callbacks functions
<> 144:ef7eb2e8f9f7 1909 * @{
<> 144:ef7eb2e8f9f7 1910 */
<> 144:ef7eb2e8f9f7 1911 /* Callback in non blocking modes (Interrupt and DMA) *************************/
<> 144:ef7eb2e8f9f7 1912 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1913 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1914 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1915 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1916 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1917 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1918 /**
<> 144:ef7eb2e8f9f7 1919 * @}
<> 144:ef7eb2e8f9f7 1920 */
<> 144:ef7eb2e8f9f7 1921
<> 144:ef7eb2e8f9f7 1922 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
<> 144:ef7eb2e8f9f7 1923 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 1924 * @{
<> 144:ef7eb2e8f9f7 1925 */
<> 144:ef7eb2e8f9f7 1926 /* Peripheral State functions ************************************************/
<> 144:ef7eb2e8f9f7 1927 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1928 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1929 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1930 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1931 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1932 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1933 /**
<> 144:ef7eb2e8f9f7 1934 * @}
<> 144:ef7eb2e8f9f7 1935 */
<> 144:ef7eb2e8f9f7 1936
<> 144:ef7eb2e8f9f7 1937 /**
<> 144:ef7eb2e8f9f7 1938 * @}
<> 144:ef7eb2e8f9f7 1939 */
<> 144:ef7eb2e8f9f7 1940 /* End of exported functions -------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1941
<> 144:ef7eb2e8f9f7 1942 /* Private functions----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1943 /** @defgroup TIM_Private_Functions TIM Private Functions
<> 144:ef7eb2e8f9f7 1944 * @{
<> 144:ef7eb2e8f9f7 1945 */
<> 144:ef7eb2e8f9f7 1946 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
<> 144:ef7eb2e8f9f7 1947 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 1948 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
<> 144:ef7eb2e8f9f7 1949 void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
<> 144:ef7eb2e8f9f7 1950 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
<> 144:ef7eb2e8f9f7 1951
<> 144:ef7eb2e8f9f7 1952 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 1953 void TIM_DMAError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 1954 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 1955 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
<> 144:ef7eb2e8f9f7 1956 /**
<> 144:ef7eb2e8f9f7 1957 * @}
<> 144:ef7eb2e8f9f7 1958 */
<> 144:ef7eb2e8f9f7 1959 /* End of private functions --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1960
<> 144:ef7eb2e8f9f7 1961 /**
<> 144:ef7eb2e8f9f7 1962 * @}
<> 144:ef7eb2e8f9f7 1963 */
<> 144:ef7eb2e8f9f7 1964
<> 144:ef7eb2e8f9f7 1965 /**
<> 144:ef7eb2e8f9f7 1966 * @}
<> 144:ef7eb2e8f9f7 1967 */
<> 144:ef7eb2e8f9f7 1968
<> 144:ef7eb2e8f9f7 1969 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 1970 }
<> 144:ef7eb2e8f9f7 1971 #endif
<> 144:ef7eb2e8f9f7 1972
<> 144:ef7eb2e8f9f7 1973 #endif /* __STM32L4xx_HAL_TIM_H */
<> 144:ef7eb2e8f9f7 1974
<> 144:ef7eb2e8f9f7 1975 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/