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targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc_ex.c@148:161ebc35dc3a, 2016-09-28 (annotated)

Committer:
olympux
Date:
Wed Sep 28 20:59:47 2016 +0000
Revision:
148:161ebc35dc3a
Parent:
144:ef7eb2e8f9f7 
RTC working

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f3xx_hal_rcc_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.3.0
<> 144:ef7eb2e8f9f7 6 * @date 01-July-2016
<> 144:ef7eb2e8f9f7 7 * @brief Extended RCC HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities RCC extension peripheral:
<> 144:ef7eb2e8f9f7 10 * + Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 ******************************************************************************
<> 144:ef7eb2e8f9f7 13 * @attention
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 16 *
<> 144:ef7eb2e8f9f7 17 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 18 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 19 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 20 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 21 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 22 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 23 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 25 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 26 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 27 *
<> 144:ef7eb2e8f9f7 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 38 *
<> 144:ef7eb2e8f9f7 39 ******************************************************************************
<> 144:ef7eb2e8f9f7 40 */
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 43 #include "stm32f3xx_hal.h"
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 /** @addtogroup STM32F3xx_HAL_Driver
<> 144:ef7eb2e8f9f7 46 * @{
<> 144:ef7eb2e8f9f7 47 */
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 #ifdef HAL_RCC_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /** @defgroup RCCEx RCCEx
<> 144:ef7eb2e8f9f7 52 * @brief RCC Extension HAL module driver.
<> 144:ef7eb2e8f9f7 53 * @{
<> 144:ef7eb2e8f9f7 54 */
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 57 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62 /**
<> 144:ef7eb2e8f9f7 63 * @}
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 67 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 68 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 69 #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) || defined(RCC_CFGR_USBPRE) \
<> 144:ef7eb2e8f9f7 70 || defined(RCC_CFGR3_TIM1SW) || defined(RCC_CFGR3_TIM2SW) || defined(RCC_CFGR3_TIM8SW) || defined(RCC_CFGR3_TIM15SW) \
<> 144:ef7eb2e8f9f7 71 || defined(RCC_CFGR3_TIM16SW) || defined(RCC_CFGR3_TIM17SW) || defined(RCC_CFGR3_TIM20SW) || defined(RCC_CFGR3_TIM34SW) \
<> 144:ef7eb2e8f9f7 72 || defined(RCC_CFGR3_HRTIM1SW)
<> 144:ef7eb2e8f9f7 73 /** @defgroup RCCEx_Private_Functions RCCEx Private Functions
<> 144:ef7eb2e8f9f7 74 * @{
<> 144:ef7eb2e8f9f7 75 */
<> 144:ef7eb2e8f9f7 76 static uint32_t RCC_GetPLLCLKFreq(void);
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 /**
<> 144:ef7eb2e8f9f7 79 * @}
<> 144:ef7eb2e8f9f7 80 */
<> 144:ef7eb2e8f9f7 81 #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRExx || RCC_CFGR3_TIMxSW || RCC_CFGR3_HRTIM1SW || RCC_CFGR_USBPRE */
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
<> 144:ef7eb2e8f9f7 84 * @{
<> 144:ef7eb2e8f9f7 85 */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 88 * @brief Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 89 *
<> 144:ef7eb2e8f9f7 90 @verbatim
<> 144:ef7eb2e8f9f7 91 ===============================================================================
<> 144:ef7eb2e8f9f7 92 ##### Extended Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 93 ===============================================================================
<> 144:ef7eb2e8f9f7 94 [..]
<> 144:ef7eb2e8f9f7 95 This subsection provides a set of functions allowing to control the RCC Clocks
<> 144:ef7eb2e8f9f7 96 frequencies.
<> 144:ef7eb2e8f9f7 97 [..]
<> 144:ef7eb2e8f9f7 98 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
<> 144:ef7eb2e8f9f7 99 select the RTC clock source; in this case the Backup domain will be reset in
<> 144:ef7eb2e8f9f7 100 order to modify the RTC Clock source, as consequence RTC registers (including
<> 144:ef7eb2e8f9f7 101 the backup registers) are set to their reset values.
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 @endverbatim
<> 144:ef7eb2e8f9f7 104 * @{
<> 144:ef7eb2e8f9f7 105 */
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 /**
<> 144:ef7eb2e8f9f7 108 * @brief Initializes the RCC extended peripherals clocks according to the specified
<> 144:ef7eb2e8f9f7 109 * parameters in the RCC_PeriphCLKInitTypeDef.
<> 144:ef7eb2e8f9f7 110 * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
<> 144:ef7eb2e8f9f7 111 * contains the configuration information for the Extended Peripherals clocks
<> 144:ef7eb2e8f9f7 112 * (ADC, CEC, I2C, I2S, SDADC, HRTIM, TIM, USART, RTC and USB).
<> 144:ef7eb2e8f9f7 113 *
<> 144:ef7eb2e8f9f7 114 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
<> 144:ef7eb2e8f9f7 115 * the RTC clock source; in this case the Backup domain will be reset in
<> 144:ef7eb2e8f9f7 116 * order to modify the RTC Clock source, as consequence RTC registers (including
<> 144:ef7eb2e8f9f7 117 * the backup registers) and RCC_BDCR register are set to their reset values.
<> 144:ef7eb2e8f9f7 118 *
<> 144:ef7eb2e8f9f7 119 * @retval HAL status
<> 144:ef7eb2e8f9f7 120 */
<> 144:ef7eb2e8f9f7 121 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
<> 144:ef7eb2e8f9f7 122 {
<> 144:ef7eb2e8f9f7 123 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 124 uint32_t temp_reg = 0;
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /* Check the parameters */
<> 144:ef7eb2e8f9f7 127 assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /*---------------------------- RTC configuration -------------------------------*/
<> 144:ef7eb2e8f9f7 130 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
<> 144:ef7eb2e8f9f7 131 {
<> 144:ef7eb2e8f9f7 132 /* check for RTC Parameters used to output RTCCLK */
<> 144:ef7eb2e8f9f7 133 assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 FlagStatus pwrclkchanged = RESET;
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 /* As soon as function is called to change RTC clock source, activation of the
<> 144:ef7eb2e8f9f7 138 power domain is done. */
<> 144:ef7eb2e8f9f7 139 /* Requires to enable write access to Backup Domain of necessary */
<> 144:ef7eb2e8f9f7 140 if(__HAL_RCC_PWR_IS_CLK_DISABLED())
<> 144:ef7eb2e8f9f7 141 {
<> 144:ef7eb2e8f9f7 142 __HAL_RCC_PWR_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 143 pwrclkchanged = SET;
<> 144:ef7eb2e8f9f7 144 }
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
<> 144:ef7eb2e8f9f7 147 {
<> 144:ef7eb2e8f9f7 148 /* Enable write access to Backup domain */
<> 144:ef7eb2e8f9f7 149 SET_BIT(PWR->CR, PWR_CR_DBP);
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 /* Wait for Backup domain Write protection disable */
<> 144:ef7eb2e8f9f7 152 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
<> 144:ef7eb2e8f9f7 155 {
<> 144:ef7eb2e8f9f7 156 if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 157 {
<> 144:ef7eb2e8f9f7 158 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 159 }
<> 144:ef7eb2e8f9f7 160 }
<> 144:ef7eb2e8f9f7 161 }
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
<> 144:ef7eb2e8f9f7 164 temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
<> 144:ef7eb2e8f9f7 165 if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
<> 144:ef7eb2e8f9f7 166 {
<> 144:ef7eb2e8f9f7 167 /* Store the content of BDCR register before the reset of Backup Domain */
<> 144:ef7eb2e8f9f7 168 temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
<> 144:ef7eb2e8f9f7 169 /* RTC Clock selection can be changed only if the Backup Domain is reset */
<> 144:ef7eb2e8f9f7 170 __HAL_RCC_BACKUPRESET_FORCE();
<> 144:ef7eb2e8f9f7 171 __HAL_RCC_BACKUPRESET_RELEASE();
<> 144:ef7eb2e8f9f7 172 /* Restore the Content of BDCR register */
<> 144:ef7eb2e8f9f7 173 RCC->BDCR = temp_reg;
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 /* Wait for LSERDY if LSE was enabled */
<> 144:ef7eb2e8f9f7 176 if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
<> 144:ef7eb2e8f9f7 177 {
<> 144:ef7eb2e8f9f7 178 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 179 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 /* Wait till LSE is ready */
<> 144:ef7eb2e8f9f7 182 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
<> 144:ef7eb2e8f9f7 183 {
<> 144:ef7eb2e8f9f7 184 if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 185 {
<> 144:ef7eb2e8f9f7 186 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 187 }
<> 144:ef7eb2e8f9f7 188 }
<> 144:ef7eb2e8f9f7 189 }
<> 144:ef7eb2e8f9f7 190 }
<> 144:ef7eb2e8f9f7 191 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /* Require to disable power clock if necessary */
<> 144:ef7eb2e8f9f7 194 if(pwrclkchanged == SET)
<> 144:ef7eb2e8f9f7 195 {
<> 144:ef7eb2e8f9f7 196 __HAL_RCC_PWR_CLK_DISABLE();
<> 144:ef7eb2e8f9f7 197 }
<> 144:ef7eb2e8f9f7 198 }
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 /*------------------------------- USART1 Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 201 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
<> 144:ef7eb2e8f9f7 202 {
<> 144:ef7eb2e8f9f7 203 /* Check the parameters */
<> 144:ef7eb2e8f9f7 204 assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /* Configure the USART1 clock source */
<> 144:ef7eb2e8f9f7 207 __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
<> 144:ef7eb2e8f9f7 208 }
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 #if defined(RCC_CFGR3_USART2SW)
<> 144:ef7eb2e8f9f7 211 /*----------------------------- USART2 Configuration --------------------------*/
<> 144:ef7eb2e8f9f7 212 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
<> 144:ef7eb2e8f9f7 213 {
<> 144:ef7eb2e8f9f7 214 /* Check the parameters */
<> 144:ef7eb2e8f9f7 215 assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /* Configure the USART2 clock source */
<> 144:ef7eb2e8f9f7 218 __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
<> 144:ef7eb2e8f9f7 219 }
<> 144:ef7eb2e8f9f7 220 #endif /* RCC_CFGR3_USART2SW */
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 #if defined(RCC_CFGR3_USART3SW)
<> 144:ef7eb2e8f9f7 223 /*------------------------------ USART3 Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 224 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
<> 144:ef7eb2e8f9f7 225 {
<> 144:ef7eb2e8f9f7 226 /* Check the parameters */
<> 144:ef7eb2e8f9f7 227 assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /* Configure the USART3 clock source */
<> 144:ef7eb2e8f9f7 230 __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
<> 144:ef7eb2e8f9f7 231 }
<> 144:ef7eb2e8f9f7 232 #endif /* RCC_CFGR3_USART3SW */
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 /*------------------------------ I2C1 Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 235 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
<> 144:ef7eb2e8f9f7 236 {
<> 144:ef7eb2e8f9f7 237 /* Check the parameters */
<> 144:ef7eb2e8f9f7 238 assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /* Configure the I2C1 clock source */
<> 144:ef7eb2e8f9f7 241 __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
<> 144:ef7eb2e8f9f7 242 }
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 #if defined(STM32F302xE) || defined(STM32F303xE)\
<> 144:ef7eb2e8f9f7 245 || defined(STM32F302xC) || defined(STM32F303xC)\
<> 144:ef7eb2e8f9f7 246 || defined(STM32F302x8) \
<> 144:ef7eb2e8f9f7 247 || defined(STM32F373xC)
<> 144:ef7eb2e8f9f7 248 /*------------------------------ USB Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 249 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
<> 144:ef7eb2e8f9f7 250 {
<> 144:ef7eb2e8f9f7 251 /* Check the parameters */
<> 144:ef7eb2e8f9f7 252 assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->USBClockSelection));
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /* Configure the USB clock source */
<> 144:ef7eb2e8f9f7 255 __HAL_RCC_USB_CONFIG(PeriphClkInit->USBClockSelection);
<> 144:ef7eb2e8f9f7 256 }
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 #endif /* STM32F302xE || STM32F303xE || */
<> 144:ef7eb2e8f9f7 259 /* STM32F302xC || STM32F303xC || */
<> 144:ef7eb2e8f9f7 260 /* STM32F302x8 || */
<> 144:ef7eb2e8f9f7 261 /* STM32F373xC */
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
<> 144:ef7eb2e8f9f7 264 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
<> 144:ef7eb2e8f9f7 265 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
<> 144:ef7eb2e8f9f7 266 || defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 /*------------------------------ I2C2 Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 269 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
<> 144:ef7eb2e8f9f7 270 {
<> 144:ef7eb2e8f9f7 271 /* Check the parameters */
<> 144:ef7eb2e8f9f7 272 assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /* Configure the I2C2 clock source */
<> 144:ef7eb2e8f9f7 275 __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
<> 144:ef7eb2e8f9f7 276 }
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 279 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 280 /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
<> 144:ef7eb2e8f9f7 281 /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
<> 144:ef7eb2e8f9f7 284 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 /*------------------------------ I2C3 Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 287 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
<> 144:ef7eb2e8f9f7 288 {
<> 144:ef7eb2e8f9f7 289 /* Check the parameters */
<> 144:ef7eb2e8f9f7 290 assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /* Configure the I2C3 clock source */
<> 144:ef7eb2e8f9f7 293 __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
<> 144:ef7eb2e8f9f7 294 }
<> 144:ef7eb2e8f9f7 295 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 296 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
<> 144:ef7eb2e8f9f7 299 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 /*------------------------------ UART4 Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 302 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
<> 144:ef7eb2e8f9f7 303 {
<> 144:ef7eb2e8f9f7 304 /* Check the parameters */
<> 144:ef7eb2e8f9f7 305 assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /* Configure the UART4 clock source */
<> 144:ef7eb2e8f9f7 308 __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
<> 144:ef7eb2e8f9f7 309 }
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 /*------------------------------ UART5 Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 312 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
<> 144:ef7eb2e8f9f7 313 {
<> 144:ef7eb2e8f9f7 314 /* Check the parameters */
<> 144:ef7eb2e8f9f7 315 assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /* Configure the UART5 clock source */
<> 144:ef7eb2e8f9f7 318 __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
<> 144:ef7eb2e8f9f7 319 }
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 322 /* STM32F302xC || STM32F303xC || STM32F358xx */
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
<> 144:ef7eb2e8f9f7 325 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
<> 144:ef7eb2e8f9f7 326 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 327 /*------------------------------ I2S Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 328 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
<> 144:ef7eb2e8f9f7 329 {
<> 144:ef7eb2e8f9f7 330 /* Check the parameters */
<> 144:ef7eb2e8f9f7 331 assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 /* Configure the I2S clock source */
<> 144:ef7eb2e8f9f7 334 __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
<> 144:ef7eb2e8f9f7 335 }
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 338 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 339 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 /*------------------------------ ADC1 clock Configuration ------------------*/
<> 144:ef7eb2e8f9f7 344 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC1) == RCC_PERIPHCLK_ADC1)
<> 144:ef7eb2e8f9f7 345 {
<> 144:ef7eb2e8f9f7 346 /* Check the parameters */
<> 144:ef7eb2e8f9f7 347 assert_param(IS_RCC_ADC1PLLCLK_DIV(PeriphClkInit->Adc1ClockSelection));
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /* Configure the ADC1 clock source */
<> 144:ef7eb2e8f9f7 350 __HAL_RCC_ADC1_CONFIG(PeriphClkInit->Adc1ClockSelection);
<> 144:ef7eb2e8f9f7 351 }
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
<> 144:ef7eb2e8f9f7 356 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
<> 144:ef7eb2e8f9f7 357 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 /*------------------------------ ADC1 & ADC2 clock Configuration -------------*/
<> 144:ef7eb2e8f9f7 360 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12)
<> 144:ef7eb2e8f9f7 361 {
<> 144:ef7eb2e8f9f7 362 /* Check the parameters */
<> 144:ef7eb2e8f9f7 363 assert_param(IS_RCC_ADC12PLLCLK_DIV(PeriphClkInit->Adc12ClockSelection));
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /* Configure the ADC12 clock source */
<> 144:ef7eb2e8f9f7 366 __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection);
<> 144:ef7eb2e8f9f7 367 }
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 370 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 371 /* STM32F303x8 || STM32F334x8 || STM32F328xx */
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 #if defined(STM32F303xE) || defined(STM32F398xx)\
<> 144:ef7eb2e8f9f7 374 || defined(STM32F303xC) || defined(STM32F358xx)
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 /*------------------------------ ADC3 & ADC4 clock Configuration -------------*/
<> 144:ef7eb2e8f9f7 377 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC34) == RCC_PERIPHCLK_ADC34)
<> 144:ef7eb2e8f9f7 378 {
<> 144:ef7eb2e8f9f7 379 /* Check the parameters */
<> 144:ef7eb2e8f9f7 380 assert_param(IS_RCC_ADC34PLLCLK_DIV(PeriphClkInit->Adc34ClockSelection));
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 /* Configure the ADC34 clock source */
<> 144:ef7eb2e8f9f7 383 __HAL_RCC_ADC34_CONFIG(PeriphClkInit->Adc34ClockSelection);
<> 144:ef7eb2e8f9f7 384 }
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 #endif /* STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 387 /* STM32F303xC || STM32F358xx */
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 /*------------------------------ ADC1 clock Configuration ------------------*/
<> 144:ef7eb2e8f9f7 392 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC1) == RCC_PERIPHCLK_ADC1)
<> 144:ef7eb2e8f9f7 393 {
<> 144:ef7eb2e8f9f7 394 /* Check the parameters */
<> 144:ef7eb2e8f9f7 395 assert_param(IS_RCC_ADC1PCLK2_DIV(PeriphClkInit->Adc1ClockSelection));
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 /* Configure the ADC1 clock source */
<> 144:ef7eb2e8f9f7 398 __HAL_RCC_ADC1_CONFIG(PeriphClkInit->Adc1ClockSelection);
<> 144:ef7eb2e8f9f7 399 }
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
<> 144:ef7eb2e8f9f7 404 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
<> 144:ef7eb2e8f9f7 405 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
<> 144:ef7eb2e8f9f7 406 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 /*------------------------------ TIM1 clock Configuration ----------------*/
<> 144:ef7eb2e8f9f7 409 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1)
<> 144:ef7eb2e8f9f7 410 {
<> 144:ef7eb2e8f9f7 411 /* Check the parameters */
<> 144:ef7eb2e8f9f7 412 assert_param(IS_RCC_TIM1CLKSOURCE(PeriphClkInit->Tim1ClockSelection));
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 /* Configure the TIM1 clock source */
<> 144:ef7eb2e8f9f7 415 __HAL_RCC_TIM1_CONFIG(PeriphClkInit->Tim1ClockSelection);
<> 144:ef7eb2e8f9f7 416 }
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 419 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 420 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 421 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 #if defined(STM32F303xE) || defined(STM32F398xx)\
<> 144:ef7eb2e8f9f7 424 || defined(STM32F303xC) || defined(STM32F358xx)
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 /*------------------------------ TIM8 clock Configuration ----------------*/
<> 144:ef7eb2e8f9f7 427 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM8) == RCC_PERIPHCLK_TIM8)
<> 144:ef7eb2e8f9f7 428 {
<> 144:ef7eb2e8f9f7 429 /* Check the parameters */
<> 144:ef7eb2e8f9f7 430 assert_param(IS_RCC_TIM8CLKSOURCE(PeriphClkInit->Tim8ClockSelection));
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 /* Configure the TIM8 clock source */
<> 144:ef7eb2e8f9f7 433 __HAL_RCC_TIM8_CONFIG(PeriphClkInit->Tim8ClockSelection);
<> 144:ef7eb2e8f9f7 434 }
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 #endif /* STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 437 /* STM32F303xC || STM32F358xx */
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 /*------------------------------ TIM15 clock Configuration ----------------*/
<> 144:ef7eb2e8f9f7 442 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)
<> 144:ef7eb2e8f9f7 443 {
<> 144:ef7eb2e8f9f7 444 /* Check the parameters */
<> 144:ef7eb2e8f9f7 445 assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection));
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 /* Configure the TIM15 clock source */
<> 144:ef7eb2e8f9f7 448 __HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection);
<> 144:ef7eb2e8f9f7 449 }
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 /*------------------------------ TIM16 clock Configuration ----------------*/
<> 144:ef7eb2e8f9f7 452 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM16) == RCC_PERIPHCLK_TIM16)
<> 144:ef7eb2e8f9f7 453 {
<> 144:ef7eb2e8f9f7 454 /* Check the parameters */
<> 144:ef7eb2e8f9f7 455 assert_param(IS_RCC_TIM16CLKSOURCE(PeriphClkInit->Tim16ClockSelection));
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 /* Configure the TIM16 clock source */
<> 144:ef7eb2e8f9f7 458 __HAL_RCC_TIM16_CONFIG(PeriphClkInit->Tim16ClockSelection);
<> 144:ef7eb2e8f9f7 459 }
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 /*------------------------------ TIM17 clock Configuration ----------------*/
<> 144:ef7eb2e8f9f7 462 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM17) == RCC_PERIPHCLK_TIM17)
<> 144:ef7eb2e8f9f7 463 {
<> 144:ef7eb2e8f9f7 464 /* Check the parameters */
<> 144:ef7eb2e8f9f7 465 assert_param(IS_RCC_TIM17CLKSOURCE(PeriphClkInit->Tim17ClockSelection));
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 /* Configure the TIM17 clock source */
<> 144:ef7eb2e8f9f7 468 __HAL_RCC_TIM17_CONFIG(PeriphClkInit->Tim17ClockSelection);
<> 144:ef7eb2e8f9f7 469 }
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473 #if defined(STM32F334x8)
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 /*------------------------------ HRTIM1 clock Configuration ----------------*/
<> 144:ef7eb2e8f9f7 476 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1)
<> 144:ef7eb2e8f9f7 477 {
<> 144:ef7eb2e8f9f7 478 /* Check the parameters */
<> 144:ef7eb2e8f9f7 479 assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection));
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 /* Configure the HRTIM1 clock source */
<> 144:ef7eb2e8f9f7 482 __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection);
<> 144:ef7eb2e8f9f7 483 }
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 #endif /* STM32F334x8 */
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 /*------------------------------ SDADC clock Configuration -------------------*/
<> 144:ef7eb2e8f9f7 490 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDADC) == RCC_PERIPHCLK_SDADC)
<> 144:ef7eb2e8f9f7 491 {
<> 144:ef7eb2e8f9f7 492 /* Check the parameters */
<> 144:ef7eb2e8f9f7 493 assert_param(IS_RCC_SDADCSYSCLK_DIV(PeriphClkInit->SdadcClockSelection));
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 /* Configure the SDADC clock prescaler */
<> 144:ef7eb2e8f9f7 496 __HAL_RCC_SDADC_CONFIG(PeriphClkInit->SdadcClockSelection);
<> 144:ef7eb2e8f9f7 497 }
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 /*------------------------------ CEC clock Configuration -------------------*/
<> 144:ef7eb2e8f9f7 500 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
<> 144:ef7eb2e8f9f7 501 {
<> 144:ef7eb2e8f9f7 502 /* Check the parameters */
<> 144:ef7eb2e8f9f7 503 assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 /* Configure the CEC clock source */
<> 144:ef7eb2e8f9f7 506 __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
<> 144:ef7eb2e8f9f7 507 }
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 /*------------------------------ TIM2 clock Configuration -------------------*/
<> 144:ef7eb2e8f9f7 514 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM2) == RCC_PERIPHCLK_TIM2)
<> 144:ef7eb2e8f9f7 515 {
<> 144:ef7eb2e8f9f7 516 /* Check the parameters */
<> 144:ef7eb2e8f9f7 517 assert_param(IS_RCC_TIM2CLKSOURCE(PeriphClkInit->Tim2ClockSelection));
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519 /* Configure the CEC clock source */
<> 144:ef7eb2e8f9f7 520 __HAL_RCC_TIM2_CONFIG(PeriphClkInit->Tim2ClockSelection);
<> 144:ef7eb2e8f9f7 521 }
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 /*------------------------------ TIM3 clock Configuration -------------------*/
<> 144:ef7eb2e8f9f7 524 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM34) == RCC_PERIPHCLK_TIM34)
<> 144:ef7eb2e8f9f7 525 {
<> 144:ef7eb2e8f9f7 526 /* Check the parameters */
<> 144:ef7eb2e8f9f7 527 assert_param(IS_RCC_TIM3CLKSOURCE(PeriphClkInit->Tim34ClockSelection));
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 /* Configure the CEC clock source */
<> 144:ef7eb2e8f9f7 530 __HAL_RCC_TIM34_CONFIG(PeriphClkInit->Tim34ClockSelection);
<> 144:ef7eb2e8f9f7 531 }
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 /*------------------------------ TIM15 clock Configuration ------------------*/
<> 144:ef7eb2e8f9f7 534 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)
<> 144:ef7eb2e8f9f7 535 {
<> 144:ef7eb2e8f9f7 536 /* Check the parameters */
<> 144:ef7eb2e8f9f7 537 assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection));
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 /* Configure the CEC clock source */
<> 144:ef7eb2e8f9f7 540 __HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection);
<> 144:ef7eb2e8f9f7 541 }
<> 144:ef7eb2e8f9f7 542
<> 144:ef7eb2e8f9f7 543 /*------------------------------ TIM16 clock Configuration ------------------*/
<> 144:ef7eb2e8f9f7 544 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM16) == RCC_PERIPHCLK_TIM16)
<> 144:ef7eb2e8f9f7 545 {
<> 144:ef7eb2e8f9f7 546 /* Check the parameters */
<> 144:ef7eb2e8f9f7 547 assert_param(IS_RCC_TIM16CLKSOURCE(PeriphClkInit->Tim16ClockSelection));
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 /* Configure the CEC clock source */
<> 144:ef7eb2e8f9f7 550 __HAL_RCC_TIM16_CONFIG(PeriphClkInit->Tim16ClockSelection);
<> 144:ef7eb2e8f9f7 551 }
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 /*------------------------------ TIM17 clock Configuration ------------------*/
<> 144:ef7eb2e8f9f7 554 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM17) == RCC_PERIPHCLK_TIM17)
<> 144:ef7eb2e8f9f7 555 {
<> 144:ef7eb2e8f9f7 556 /* Check the parameters */
<> 144:ef7eb2e8f9f7 557 assert_param(IS_RCC_TIM17CLKSOURCE(PeriphClkInit->Tim17ClockSelection));
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559 /* Configure the CEC clock source */
<> 144:ef7eb2e8f9f7 560 __HAL_RCC_TIM17_CONFIG(PeriphClkInit->Tim17ClockSelection);
<> 144:ef7eb2e8f9f7 561 }
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 #if defined(STM32F303xE) || defined(STM32F398xx)
<> 144:ef7eb2e8f9f7 566 /*------------------------------ TIM20 clock Configuration ------------------*/
<> 144:ef7eb2e8f9f7 567 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM20) == RCC_PERIPHCLK_TIM20)
<> 144:ef7eb2e8f9f7 568 {
<> 144:ef7eb2e8f9f7 569 /* Check the parameters */
<> 144:ef7eb2e8f9f7 570 assert_param(IS_RCC_TIM20CLKSOURCE(PeriphClkInit->Tim20ClockSelection));
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 /* Configure the CEC clock source */
<> 144:ef7eb2e8f9f7 573 __HAL_RCC_TIM20_CONFIG(PeriphClkInit->Tim20ClockSelection);
<> 144:ef7eb2e8f9f7 574 }
<> 144:ef7eb2e8f9f7 575 #endif /* STM32F303xE || STM32F398xx */
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 return HAL_OK;
<> 144:ef7eb2e8f9f7 579 }
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 /**
<> 144:ef7eb2e8f9f7 582 * @brief Get the RCC_ClkInitStruct according to the internal
<> 144:ef7eb2e8f9f7 583 * RCC configuration registers.
<> 144:ef7eb2e8f9f7 584 * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
<> 144:ef7eb2e8f9f7 585 * returns the configuration information for the Extended Peripherals clocks
<> 144:ef7eb2e8f9f7 586 * (ADC, CEC, I2C, I2S, SDADC, HRTIM, TIM, USART, RTC and USB clocks).
<> 144:ef7eb2e8f9f7 587 * @retval None
<> 144:ef7eb2e8f9f7 588 */
<> 144:ef7eb2e8f9f7 589 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
<> 144:ef7eb2e8f9f7 590 {
<> 144:ef7eb2e8f9f7 591 /* Set all possible values for the extended clock type parameter------------*/
<> 144:ef7eb2e8f9f7 592 /* Common part first */
<> 144:ef7eb2e8f9f7 593 #if defined(RCC_CFGR3_USART2SW) && defined(RCC_CFGR3_USART3SW)
<> 144:ef7eb2e8f9f7 594 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
<> 144:ef7eb2e8f9f7 595 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC;
<> 144:ef7eb2e8f9f7 596 #else
<> 144:ef7eb2e8f9f7 597 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | \
<> 144:ef7eb2e8f9f7 598 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC;
<> 144:ef7eb2e8f9f7 599 #endif /* RCC_CFGR3_USART2SW && RCC_CFGR3_USART3SW */
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 /* Get the RTC configuration --------------------------------------------*/
<> 144:ef7eb2e8f9f7 602 PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
<> 144:ef7eb2e8f9f7 603 /* Get the USART1 clock configuration --------------------------------------------*/
<> 144:ef7eb2e8f9f7 604 PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
<> 144:ef7eb2e8f9f7 605 #if defined(RCC_CFGR3_USART2SW)
<> 144:ef7eb2e8f9f7 606 /* Get the USART2 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 607 PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
<> 144:ef7eb2e8f9f7 608 #endif /* RCC_CFGR3_USART2SW */
<> 144:ef7eb2e8f9f7 609 #if defined(RCC_CFGR3_USART3SW)
<> 144:ef7eb2e8f9f7 610 /* Get the USART3 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 611 PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
<> 144:ef7eb2e8f9f7 612 #endif /* RCC_CFGR3_USART3SW */
<> 144:ef7eb2e8f9f7 613 /* Get the I2C1 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 614 PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 #if defined(STM32F302xE) || defined(STM32F303xE)\
<> 144:ef7eb2e8f9f7 617 || defined(STM32F302xC) || defined(STM32F303xC)\
<> 144:ef7eb2e8f9f7 618 || defined(STM32F302x8) \
<> 144:ef7eb2e8f9f7 619 || defined(STM32F373xC)
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
<> 144:ef7eb2e8f9f7 622 /* Get the USB clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 623 PeriphClkInit->USBClockSelection = __HAL_RCC_GET_USB_SOURCE();
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 #endif /* STM32F302xE || STM32F303xE || */
<> 144:ef7eb2e8f9f7 626 /* STM32F302xC || STM32F303xC || */
<> 144:ef7eb2e8f9f7 627 /* STM32F302x8 || */
<> 144:ef7eb2e8f9f7 628 /* STM32F373xC */
<> 144:ef7eb2e8f9f7 629
<> 144:ef7eb2e8f9f7 630 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
<> 144:ef7eb2e8f9f7 631 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
<> 144:ef7eb2e8f9f7 632 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
<> 144:ef7eb2e8f9f7 633 || defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C2;
<> 144:ef7eb2e8f9f7 636 /* Get the I2C2 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 637 PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 640 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 641 /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
<> 144:ef7eb2e8f9f7 642 /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 643
<> 144:ef7eb2e8f9f7 644 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
<> 144:ef7eb2e8f9f7 645 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C3;
<> 144:ef7eb2e8f9f7 648 /* Get the I2C3 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 649 PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 652 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 653
<> 144:ef7eb2e8f9f7 654 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
<> 144:ef7eb2e8f9f7 655 || defined(STM32F302xC) || defined(STM32F303xC) ||defined(STM32F358xx)
<> 144:ef7eb2e8f9f7 656
<> 144:ef7eb2e8f9f7 657 PeriphClkInit->PeriphClockSelection |= (RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5);
<> 144:ef7eb2e8f9f7 658 /* Get the UART4 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 659 PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
<> 144:ef7eb2e8f9f7 660 /* Get the UART5 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 661 PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
<> 144:ef7eb2e8f9f7 662
<> 144:ef7eb2e8f9f7 663 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 664 /* STM32F302xC || STM32F303xC || STM32F358xx */
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
<> 144:ef7eb2e8f9f7 667 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
<> 144:ef7eb2e8f9f7 668 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S;
<> 144:ef7eb2e8f9f7 671 /* Get the I2S clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 672 PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2S_SOURCE();
<> 144:ef7eb2e8f9f7 673
<> 144:ef7eb2e8f9f7 674 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 675 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 676 /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
<> 144:ef7eb2e8f9f7 679 || defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 680
<> 144:ef7eb2e8f9f7 681 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC1;
<> 144:ef7eb2e8f9f7 682 /* Get the ADC1 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 683 PeriphClkInit->Adc1ClockSelection = __HAL_RCC_GET_ADC1_SOURCE();
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
<> 144:ef7eb2e8f9f7 686 /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 687
<> 144:ef7eb2e8f9f7 688 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
<> 144:ef7eb2e8f9f7 689 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
<> 144:ef7eb2e8f9f7 690 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
<> 144:ef7eb2e8f9f7 691
<> 144:ef7eb2e8f9f7 692 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC12;
<> 144:ef7eb2e8f9f7 693 /* Get the ADC1 & ADC2 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 694 PeriphClkInit->Adc12ClockSelection = __HAL_RCC_GET_ADC12_SOURCE();
<> 144:ef7eb2e8f9f7 695
<> 144:ef7eb2e8f9f7 696 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 697 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 698 /* STM32F303x8 || STM32F334x8 || STM32F328xx */
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 #if defined(STM32F303xE) || defined(STM32F398xx)\
<> 144:ef7eb2e8f9f7 701 || defined(STM32F303xC) || defined(STM32F358xx)
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC34;
<> 144:ef7eb2e8f9f7 704 /* Get the ADC3 & ADC4 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 705 PeriphClkInit->Adc34ClockSelection = __HAL_RCC_GET_ADC34_SOURCE();
<> 144:ef7eb2e8f9f7 706
<> 144:ef7eb2e8f9f7 707 #endif /* STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 708 /* STM32F303xC || STM32F358xx */
<> 144:ef7eb2e8f9f7 709
<> 144:ef7eb2e8f9f7 710 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
<> 144:ef7eb2e8f9f7 711 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
<> 144:ef7eb2e8f9f7 712 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
<> 144:ef7eb2e8f9f7 713 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 714
<> 144:ef7eb2e8f9f7 715 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM1;
<> 144:ef7eb2e8f9f7 716 /* Get the TIM1 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 717 PeriphClkInit->Tim1ClockSelection = __HAL_RCC_GET_TIM1_SOURCE();
<> 144:ef7eb2e8f9f7 718
<> 144:ef7eb2e8f9f7 719 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 720 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 721 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 722 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 #if defined(STM32F303xE) || defined(STM32F398xx)\
<> 144:ef7eb2e8f9f7 725 || defined(STM32F303xC) || defined(STM32F358xx)
<> 144:ef7eb2e8f9f7 726
<> 144:ef7eb2e8f9f7 727 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM8;
<> 144:ef7eb2e8f9f7 728 /* Get the TIM8 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 729 PeriphClkInit->Tim8ClockSelection = __HAL_RCC_GET_TIM8_SOURCE();
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 #endif /* STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 732 /* STM32F303xC || STM32F358xx */
<> 144:ef7eb2e8f9f7 733
<> 144:ef7eb2e8f9f7 734 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736 PeriphClkInit->PeriphClockSelection |= (RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | RCC_PERIPHCLK_TIM17);
<> 144:ef7eb2e8f9f7 737 /* Get the TIM15 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 738 PeriphClkInit->Tim15ClockSelection = __HAL_RCC_GET_TIM15_SOURCE();
<> 144:ef7eb2e8f9f7 739 /* Get the TIM16 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 740 PeriphClkInit->Tim16ClockSelection = __HAL_RCC_GET_TIM16_SOURCE();
<> 144:ef7eb2e8f9f7 741 /* Get the TIM17 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 742 PeriphClkInit->Tim17ClockSelection = __HAL_RCC_GET_TIM17_SOURCE();
<> 144:ef7eb2e8f9f7 743
<> 144:ef7eb2e8f9f7 744 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 745
<> 144:ef7eb2e8f9f7 746 #if defined(STM32F334x8)
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_HRTIM1;
<> 144:ef7eb2e8f9f7 749 /* Get the HRTIM1 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 750 PeriphClkInit->Hrtim1ClockSelection = __HAL_RCC_GET_HRTIM1_SOURCE();
<> 144:ef7eb2e8f9f7 751
<> 144:ef7eb2e8f9f7 752 #endif /* STM32F334x8 */
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 755
<> 144:ef7eb2e8f9f7 756 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SDADC;
<> 144:ef7eb2e8f9f7 757 /* Get the SDADC clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 758 PeriphClkInit->SdadcClockSelection = __HAL_RCC_GET_SDADC_SOURCE();
<> 144:ef7eb2e8f9f7 759
<> 144:ef7eb2e8f9f7 760 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC;
<> 144:ef7eb2e8f9f7 761 /* Get the CEC clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 762 PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 765
<> 144:ef7eb2e8f9f7 766 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
<> 144:ef7eb2e8f9f7 767
<> 144:ef7eb2e8f9f7 768 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM2;
<> 144:ef7eb2e8f9f7 769 /* Get the TIM2 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 770 PeriphClkInit->Tim2ClockSelection = __HAL_RCC_GET_TIM2_SOURCE();
<> 144:ef7eb2e8f9f7 771
<> 144:ef7eb2e8f9f7 772 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM34;
<> 144:ef7eb2e8f9f7 773 /* Get the TIM3 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 774 PeriphClkInit->Tim34ClockSelection = __HAL_RCC_GET_TIM34_SOURCE();
<> 144:ef7eb2e8f9f7 775
<> 144:ef7eb2e8f9f7 776 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM15;
<> 144:ef7eb2e8f9f7 777 /* Get the TIM15 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 778 PeriphClkInit->Tim15ClockSelection = __HAL_RCC_GET_TIM15_SOURCE();
<> 144:ef7eb2e8f9f7 779
<> 144:ef7eb2e8f9f7 780 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM16;
<> 144:ef7eb2e8f9f7 781 /* Get the TIM16 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 782 PeriphClkInit->Tim16ClockSelection = __HAL_RCC_GET_TIM16_SOURCE();
<> 144:ef7eb2e8f9f7 783
<> 144:ef7eb2e8f9f7 784 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM17;
<> 144:ef7eb2e8f9f7 785 /* Get the TIM17 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 786 PeriphClkInit->Tim17ClockSelection = __HAL_RCC_GET_TIM17_SOURCE();
<> 144:ef7eb2e8f9f7 787
<> 144:ef7eb2e8f9f7 788 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
<> 144:ef7eb2e8f9f7 789
<> 144:ef7eb2e8f9f7 790 #if defined (STM32F303xE) || defined(STM32F398xx)
<> 144:ef7eb2e8f9f7 791 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM20;
<> 144:ef7eb2e8f9f7 792 /* Get the TIM20 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 793 PeriphClkInit->Tim20ClockSelection = __HAL_RCC_GET_TIM20_SOURCE();
<> 144:ef7eb2e8f9f7 794 #endif /* STM32F303xE || STM32F398xx */
<> 144:ef7eb2e8f9f7 795 }
<> 144:ef7eb2e8f9f7 796
<> 144:ef7eb2e8f9f7 797 /**
<> 144:ef7eb2e8f9f7 798 * @brief Returns the peripheral clock frequency
<> 144:ef7eb2e8f9f7 799 * @note Returns 0 if peripheral clock is unknown or 0xDEADDEAD if not applicable.
<> 144:ef7eb2e8f9f7 800 * @param PeriphClk Peripheral clock identifier
<> 144:ef7eb2e8f9f7 801 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 802 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
<> 144:ef7eb2e8f9f7 803 * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
<> 144:ef7eb2e8f9f7 804 * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
<> 144:ef7eb2e8f9f7 805 @if STM32F301x8
<> 144:ef7eb2e8f9f7 806 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
<> 144:ef7eb2e8f9f7 807 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
<> 144:ef7eb2e8f9f7 808 * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
<> 144:ef7eb2e8f9f7 809 * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
<> 144:ef7eb2e8f9f7 810 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
<> 144:ef7eb2e8f9f7 811 * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
<> 144:ef7eb2e8f9f7 812 * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
<> 144:ef7eb2e8f9f7 813 * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
<> 144:ef7eb2e8f9f7 814 @endif
<> 144:ef7eb2e8f9f7 815 @if STM32F302x8
<> 144:ef7eb2e8f9f7 816 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
<> 144:ef7eb2e8f9f7 817 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
<> 144:ef7eb2e8f9f7 818 * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
<> 144:ef7eb2e8f9f7 819 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
<> 144:ef7eb2e8f9f7 820 * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
<> 144:ef7eb2e8f9f7 821 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
<> 144:ef7eb2e8f9f7 822 * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
<> 144:ef7eb2e8f9f7 823 * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
<> 144:ef7eb2e8f9f7 824 * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
<> 144:ef7eb2e8f9f7 825 @endif
<> 144:ef7eb2e8f9f7 826 @if STM32F302xC
<> 144:ef7eb2e8f9f7 827 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
<> 144:ef7eb2e8f9f7 828 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
<> 144:ef7eb2e8f9f7 829 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
<> 144:ef7eb2e8f9f7 830 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
<> 144:ef7eb2e8f9f7 831 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
<> 144:ef7eb2e8f9f7 832 * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
<> 144:ef7eb2e8f9f7 833 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
<> 144:ef7eb2e8f9f7 834 * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
<> 144:ef7eb2e8f9f7 835 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
<> 144:ef7eb2e8f9f7 836 @endif
<> 144:ef7eb2e8f9f7 837 @if STM32F302xE
<> 144:ef7eb2e8f9f7 838 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
<> 144:ef7eb2e8f9f7 839 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
<> 144:ef7eb2e8f9f7 840 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
<> 144:ef7eb2e8f9f7 841 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
<> 144:ef7eb2e8f9f7 842 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
<> 144:ef7eb2e8f9f7 843 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
<> 144:ef7eb2e8f9f7 844 * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
<> 144:ef7eb2e8f9f7 845 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
<> 144:ef7eb2e8f9f7 846 * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
<> 144:ef7eb2e8f9f7 847 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
<> 144:ef7eb2e8f9f7 848 * @arg @ref RCC_PERIPHCLK_TIM2 TIM2 peripheral clock
<> 144:ef7eb2e8f9f7 849 * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
<> 144:ef7eb2e8f9f7 850 * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
<> 144:ef7eb2e8f9f7 851 * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
<> 144:ef7eb2e8f9f7 852 * @arg @ref RCC_PERIPHCLK_TIM34 TIM34 peripheral clock
<> 144:ef7eb2e8f9f7 853 @endif
<> 144:ef7eb2e8f9f7 854 @if STM32F303x8
<> 144:ef7eb2e8f9f7 855 * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
<> 144:ef7eb2e8f9f7 856 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
<> 144:ef7eb2e8f9f7 857 @endif
<> 144:ef7eb2e8f9f7 858 @if STM32F303xC
<> 144:ef7eb2e8f9f7 859 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
<> 144:ef7eb2e8f9f7 860 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
<> 144:ef7eb2e8f9f7 861 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
<> 144:ef7eb2e8f9f7 862 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
<> 144:ef7eb2e8f9f7 863 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
<> 144:ef7eb2e8f9f7 864 * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
<> 144:ef7eb2e8f9f7 865 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
<> 144:ef7eb2e8f9f7 866 * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
<> 144:ef7eb2e8f9f7 867 * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock
<> 144:ef7eb2e8f9f7 868 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
<> 144:ef7eb2e8f9f7 869 * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock
<> 144:ef7eb2e8f9f7 870 @endif
<> 144:ef7eb2e8f9f7 871 @if STM32F303xE
<> 144:ef7eb2e8f9f7 872 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
<> 144:ef7eb2e8f9f7 873 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
<> 144:ef7eb2e8f9f7 874 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
<> 144:ef7eb2e8f9f7 875 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
<> 144:ef7eb2e8f9f7 876 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
<> 144:ef7eb2e8f9f7 877 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
<> 144:ef7eb2e8f9f7 878 * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
<> 144:ef7eb2e8f9f7 879 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
<> 144:ef7eb2e8f9f7 880 * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
<> 144:ef7eb2e8f9f7 881 * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock
<> 144:ef7eb2e8f9f7 882 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
<> 144:ef7eb2e8f9f7 883 * @arg @ref RCC_PERIPHCLK_TIM2 TIM2 peripheral clock
<> 144:ef7eb2e8f9f7 884 * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock
<> 144:ef7eb2e8f9f7 885 * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
<> 144:ef7eb2e8f9f7 886 * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
<> 144:ef7eb2e8f9f7 887 * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
<> 144:ef7eb2e8f9f7 888 * @arg @ref RCC_PERIPHCLK_TIM20 TIM20 peripheral clock
<> 144:ef7eb2e8f9f7 889 * @arg @ref RCC_PERIPHCLK_TIM34 TIM34 peripheral clock
<> 144:ef7eb2e8f9f7 890 @endif
<> 144:ef7eb2e8f9f7 891 @if STM32F318xx
<> 144:ef7eb2e8f9f7 892 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
<> 144:ef7eb2e8f9f7 893 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
<> 144:ef7eb2e8f9f7 894 * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
<> 144:ef7eb2e8f9f7 895 * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
<> 144:ef7eb2e8f9f7 896 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
<> 144:ef7eb2e8f9f7 897 * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
<> 144:ef7eb2e8f9f7 898 * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
<> 144:ef7eb2e8f9f7 899 * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
<> 144:ef7eb2e8f9f7 900 @endif
<> 144:ef7eb2e8f9f7 901 @if STM32F328xx
<> 144:ef7eb2e8f9f7 902 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
<> 144:ef7eb2e8f9f7 903 * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
<> 144:ef7eb2e8f9f7 904 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
<> 144:ef7eb2e8f9f7 905 @endif
<> 144:ef7eb2e8f9f7 906 @if STM32F334x8
<> 144:ef7eb2e8f9f7 907 * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
<> 144:ef7eb2e8f9f7 908 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
<> 144:ef7eb2e8f9f7 909 * @arg @ref RCC_PERIPHCLK_HRTIM1 HRTIM1 peripheral clock
<> 144:ef7eb2e8f9f7 910 @endif
<> 144:ef7eb2e8f9f7 911 @if STM32F358xx
<> 144:ef7eb2e8f9f7 912 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
<> 144:ef7eb2e8f9f7 913 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
<> 144:ef7eb2e8f9f7 914 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
<> 144:ef7eb2e8f9f7 915 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
<> 144:ef7eb2e8f9f7 916 * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
<> 144:ef7eb2e8f9f7 917 * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
<> 144:ef7eb2e8f9f7 918 * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock
<> 144:ef7eb2e8f9f7 919 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
<> 144:ef7eb2e8f9f7 920 * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock
<> 144:ef7eb2e8f9f7 921 @endif
<> 144:ef7eb2e8f9f7 922 @if STM32F373xC
<> 144:ef7eb2e8f9f7 923 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
<> 144:ef7eb2e8f9f7 924 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
<> 144:ef7eb2e8f9f7 925 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
<> 144:ef7eb2e8f9f7 926 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
<> 144:ef7eb2e8f9f7 927 * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
<> 144:ef7eb2e8f9f7 928 * @arg @ref RCC_PERIPHCLK_SDADC SDADC peripheral clock
<> 144:ef7eb2e8f9f7 929 * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
<> 144:ef7eb2e8f9f7 930 @endif
<> 144:ef7eb2e8f9f7 931 @if STM32F378xx
<> 144:ef7eb2e8f9f7 932 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
<> 144:ef7eb2e8f9f7 933 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
<> 144:ef7eb2e8f9f7 934 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
<> 144:ef7eb2e8f9f7 935 * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
<> 144:ef7eb2e8f9f7 936 * @arg @ref RCC_PERIPHCLK_SDADC SDADC peripheral clock
<> 144:ef7eb2e8f9f7 937 * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
<> 144:ef7eb2e8f9f7 938 @endif
<> 144:ef7eb2e8f9f7 939 @if STM32F398xx
<> 144:ef7eb2e8f9f7 940 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
<> 144:ef7eb2e8f9f7 941 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
<> 144:ef7eb2e8f9f7 942 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
<> 144:ef7eb2e8f9f7 943 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
<> 144:ef7eb2e8f9f7 944 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
<> 144:ef7eb2e8f9f7 945 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
<> 144:ef7eb2e8f9f7 946 * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
<> 144:ef7eb2e8f9f7 947 * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
<> 144:ef7eb2e8f9f7 948 * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock
<> 144:ef7eb2e8f9f7 949 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
<> 144:ef7eb2e8f9f7 950 * @arg @ref RCC_PERIPHCLK_TIM2 TIM2 peripheral clock
<> 144:ef7eb2e8f9f7 951 * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock
<> 144:ef7eb2e8f9f7 952 * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
<> 144:ef7eb2e8f9f7 953 * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
<> 144:ef7eb2e8f9f7 954 * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
<> 144:ef7eb2e8f9f7 955 * @arg @ref RCC_PERIPHCLK_TIM20 TIM20 peripheral clock
<> 144:ef7eb2e8f9f7 956 * @arg @ref RCC_PERIPHCLK_TIM34 TIM34 peripheral clock
<> 144:ef7eb2e8f9f7 957 @endif
<> 144:ef7eb2e8f9f7 958 * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
<> 144:ef7eb2e8f9f7 959 */
<> 144:ef7eb2e8f9f7 960 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
<> 144:ef7eb2e8f9f7 961 {
<> 144:ef7eb2e8f9f7 962 uint32_t frequency = 0;
<> 144:ef7eb2e8f9f7 963 uint32_t srcclk = 0;
<> 144:ef7eb2e8f9f7 964 #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
<> 144:ef7eb2e8f9f7 965 uint16_t adc_pll_prediv_table[12] = { 1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256};
<> 144:ef7eb2e8f9f7 966 #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
<> 144:ef7eb2e8f9f7 967 #if defined(RCC_CFGR_SDADCPRE)
<> 144:ef7eb2e8f9f7 968 uint8_t sdadc_prescaler_table[16] = { 2, 4, 6, 8, 10, 12, 14, 16, 20, 24, 28, 32, 36, 40, 44, 48};
<> 144:ef7eb2e8f9f7 969 #endif /* RCC_CFGR_SDADCPRE */
<> 144:ef7eb2e8f9f7 970
<> 144:ef7eb2e8f9f7 971 /* Check the parameters */
<> 144:ef7eb2e8f9f7 972 assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
<> 144:ef7eb2e8f9f7 973
<> 144:ef7eb2e8f9f7 974 switch (PeriphClk)
<> 144:ef7eb2e8f9f7 975 {
<> 144:ef7eb2e8f9f7 976 case RCC_PERIPHCLK_RTC:
<> 144:ef7eb2e8f9f7 977 {
<> 144:ef7eb2e8f9f7 978 /* Get the current RTC source */
<> 144:ef7eb2e8f9f7 979 srcclk = __HAL_RCC_GET_RTC_SOURCE();
<> 144:ef7eb2e8f9f7 980
<> 144:ef7eb2e8f9f7 981 /* Check if LSE is ready and if RTC clock selection is LSE */
<> 144:ef7eb2e8f9f7 982 if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
<> 144:ef7eb2e8f9f7 983 {
<> 144:ef7eb2e8f9f7 984 frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 985 }
<> 144:ef7eb2e8f9f7 986 /* Check if LSI is ready and if RTC clock selection is LSI */
<> 144:ef7eb2e8f9f7 987 else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
<> 144:ef7eb2e8f9f7 988 {
<> 144:ef7eb2e8f9f7 989 frequency = LSI_VALUE;
<> 144:ef7eb2e8f9f7 990 }
<> 144:ef7eb2e8f9f7 991 /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/
<> 144:ef7eb2e8f9f7 992 else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
<> 144:ef7eb2e8f9f7 993 {
<> 144:ef7eb2e8f9f7 994 frequency = HSE_VALUE / 32;
<> 144:ef7eb2e8f9f7 995 }
<> 144:ef7eb2e8f9f7 996 /* Clock not enabled for RTC*/
<> 144:ef7eb2e8f9f7 997 else
<> 144:ef7eb2e8f9f7 998 {
<> 144:ef7eb2e8f9f7 999 frequency = 0;
<> 144:ef7eb2e8f9f7 1000 }
<> 144:ef7eb2e8f9f7 1001 break;
<> 144:ef7eb2e8f9f7 1002 }
<> 144:ef7eb2e8f9f7 1003 case RCC_PERIPHCLK_USART1:
<> 144:ef7eb2e8f9f7 1004 {
<> 144:ef7eb2e8f9f7 1005 /* Get the current USART1 source */
<> 144:ef7eb2e8f9f7 1006 srcclk = __HAL_RCC_GET_USART1_SOURCE();
<> 144:ef7eb2e8f9f7 1007
<> 144:ef7eb2e8f9f7 1008 /* Check if USART1 clock selection is PCLK1 */
<> 144:ef7eb2e8f9f7 1009 #if defined(RCC_USART1CLKSOURCE_PCLK2)
<> 144:ef7eb2e8f9f7 1010 if (srcclk == RCC_USART1CLKSOURCE_PCLK2)
<> 144:ef7eb2e8f9f7 1011 {
<> 144:ef7eb2e8f9f7 1012 frequency = HAL_RCC_GetPCLK2Freq();
<> 144:ef7eb2e8f9f7 1013 }
<> 144:ef7eb2e8f9f7 1014 #else
<> 144:ef7eb2e8f9f7 1015 if (srcclk == RCC_USART1CLKSOURCE_PCLK1)
<> 144:ef7eb2e8f9f7 1016 {
<> 144:ef7eb2e8f9f7 1017 frequency = HAL_RCC_GetPCLK1Freq();
<> 144:ef7eb2e8f9f7 1018 }
<> 144:ef7eb2e8f9f7 1019 #endif /* RCC_USART1CLKSOURCE_PCLK2 */
<> 144:ef7eb2e8f9f7 1020 /* Check if HSI is ready and if USART1 clock selection is HSI */
<> 144:ef7eb2e8f9f7 1021 else if ((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
<> 144:ef7eb2e8f9f7 1022 {
<> 144:ef7eb2e8f9f7 1023 frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 1024 }
<> 144:ef7eb2e8f9f7 1025 /* Check if USART1 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1026 else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 1027 {
<> 144:ef7eb2e8f9f7 1028 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 1029 }
<> 144:ef7eb2e8f9f7 1030 /* Check if LSE is ready and if USART1 clock selection is LSE */
<> 144:ef7eb2e8f9f7 1031 else if ((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
<> 144:ef7eb2e8f9f7 1032 {
<> 144:ef7eb2e8f9f7 1033 frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 1034 }
<> 144:ef7eb2e8f9f7 1035 /* Clock not enabled for USART1*/
<> 144:ef7eb2e8f9f7 1036 else
<> 144:ef7eb2e8f9f7 1037 {
<> 144:ef7eb2e8f9f7 1038 frequency = 0;
<> 144:ef7eb2e8f9f7 1039 }
<> 144:ef7eb2e8f9f7 1040 break;
<> 144:ef7eb2e8f9f7 1041 }
<> 144:ef7eb2e8f9f7 1042 #if defined(RCC_CFGR3_USART2SW)
<> 144:ef7eb2e8f9f7 1043 case RCC_PERIPHCLK_USART2:
<> 144:ef7eb2e8f9f7 1044 {
<> 144:ef7eb2e8f9f7 1045 /* Get the current USART2 source */
<> 144:ef7eb2e8f9f7 1046 srcclk = __HAL_RCC_GET_USART2_SOURCE();
<> 144:ef7eb2e8f9f7 1047
<> 144:ef7eb2e8f9f7 1048 /* Check if USART2 clock selection is PCLK1 */
<> 144:ef7eb2e8f9f7 1049 if (srcclk == RCC_USART2CLKSOURCE_PCLK1)
<> 144:ef7eb2e8f9f7 1050 {
<> 144:ef7eb2e8f9f7 1051 frequency = HAL_RCC_GetPCLK1Freq();
<> 144:ef7eb2e8f9f7 1052 }
<> 144:ef7eb2e8f9f7 1053 /* Check if HSI is ready and if USART2 clock selection is HSI */
<> 144:ef7eb2e8f9f7 1054 else if ((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
<> 144:ef7eb2e8f9f7 1055 {
<> 144:ef7eb2e8f9f7 1056 frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 1057 }
<> 144:ef7eb2e8f9f7 1058 /* Check if USART2 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1059 else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 1060 {
<> 144:ef7eb2e8f9f7 1061 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 1062 }
<> 144:ef7eb2e8f9f7 1063 /* Check if LSE is ready and if USART2 clock selection is LSE */
<> 144:ef7eb2e8f9f7 1064 else if ((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
<> 144:ef7eb2e8f9f7 1065 {
<> 144:ef7eb2e8f9f7 1066 frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 1067 }
<> 144:ef7eb2e8f9f7 1068 /* Clock not enabled for USART2*/
<> 144:ef7eb2e8f9f7 1069 else
<> 144:ef7eb2e8f9f7 1070 {
<> 144:ef7eb2e8f9f7 1071 frequency = 0;
<> 144:ef7eb2e8f9f7 1072 }
<> 144:ef7eb2e8f9f7 1073 break;
<> 144:ef7eb2e8f9f7 1074 }
<> 144:ef7eb2e8f9f7 1075 #endif /* RCC_CFGR3_USART2SW */
<> 144:ef7eb2e8f9f7 1076 #if defined(RCC_CFGR3_USART3SW)
<> 144:ef7eb2e8f9f7 1077 case RCC_PERIPHCLK_USART3:
<> 144:ef7eb2e8f9f7 1078 {
<> 144:ef7eb2e8f9f7 1079 /* Get the current USART3 source */
<> 144:ef7eb2e8f9f7 1080 srcclk = __HAL_RCC_GET_USART3_SOURCE();
<> 144:ef7eb2e8f9f7 1081
<> 144:ef7eb2e8f9f7 1082 /* Check if USART3 clock selection is PCLK1 */
<> 144:ef7eb2e8f9f7 1083 if (srcclk == RCC_USART3CLKSOURCE_PCLK1)
<> 144:ef7eb2e8f9f7 1084 {
<> 144:ef7eb2e8f9f7 1085 frequency = HAL_RCC_GetPCLK1Freq();
<> 144:ef7eb2e8f9f7 1086 }
<> 144:ef7eb2e8f9f7 1087 /* Check if HSI is ready and if USART3 clock selection is HSI */
<> 144:ef7eb2e8f9f7 1088 else if ((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
<> 144:ef7eb2e8f9f7 1089 {
<> 144:ef7eb2e8f9f7 1090 frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 1091 }
<> 144:ef7eb2e8f9f7 1092 /* Check if USART3 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1093 else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 1094 {
<> 144:ef7eb2e8f9f7 1095 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 1096 }
<> 144:ef7eb2e8f9f7 1097 /* Check if LSE is ready and if USART3 clock selection is LSE */
<> 144:ef7eb2e8f9f7 1098 else if ((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
<> 144:ef7eb2e8f9f7 1099 {
<> 144:ef7eb2e8f9f7 1100 frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 1101 }
<> 144:ef7eb2e8f9f7 1102 /* Clock not enabled for USART3*/
<> 144:ef7eb2e8f9f7 1103 else
<> 144:ef7eb2e8f9f7 1104 {
<> 144:ef7eb2e8f9f7 1105 frequency = 0;
<> 144:ef7eb2e8f9f7 1106 }
<> 144:ef7eb2e8f9f7 1107 break;
<> 144:ef7eb2e8f9f7 1108 }
<> 144:ef7eb2e8f9f7 1109 #endif /* RCC_CFGR3_USART3SW */
<> 144:ef7eb2e8f9f7 1110 #if defined(RCC_CFGR3_UART4SW)
<> 144:ef7eb2e8f9f7 1111 case RCC_PERIPHCLK_UART4:
<> 144:ef7eb2e8f9f7 1112 {
<> 144:ef7eb2e8f9f7 1113 /* Get the current UART4 source */
<> 144:ef7eb2e8f9f7 1114 srcclk = __HAL_RCC_GET_UART4_SOURCE();
<> 144:ef7eb2e8f9f7 1115
<> 144:ef7eb2e8f9f7 1116 /* Check if UART4 clock selection is PCLK1 */
<> 144:ef7eb2e8f9f7 1117 if (srcclk == RCC_UART4CLKSOURCE_PCLK1)
<> 144:ef7eb2e8f9f7 1118 {
<> 144:ef7eb2e8f9f7 1119 frequency = HAL_RCC_GetPCLK1Freq();
<> 144:ef7eb2e8f9f7 1120 }
<> 144:ef7eb2e8f9f7 1121 /* Check if HSI is ready and if UART4 clock selection is HSI */
<> 144:ef7eb2e8f9f7 1122 else if ((srcclk == RCC_UART4CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
<> 144:ef7eb2e8f9f7 1123 {
<> 144:ef7eb2e8f9f7 1124 frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 1125 }
<> 144:ef7eb2e8f9f7 1126 /* Check if UART4 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1127 else if (srcclk == RCC_UART4CLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 1128 {
<> 144:ef7eb2e8f9f7 1129 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 1130 }
<> 144:ef7eb2e8f9f7 1131 /* Check if LSE is ready and if UART4 clock selection is LSE */
<> 144:ef7eb2e8f9f7 1132 else if ((srcclk == RCC_UART4CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
<> 144:ef7eb2e8f9f7 1133 {
<> 144:ef7eb2e8f9f7 1134 frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 1135 }
<> 144:ef7eb2e8f9f7 1136 /* Clock not enabled for UART4*/
<> 144:ef7eb2e8f9f7 1137 else
<> 144:ef7eb2e8f9f7 1138 {
<> 144:ef7eb2e8f9f7 1139 frequency = 0;
<> 144:ef7eb2e8f9f7 1140 }
<> 144:ef7eb2e8f9f7 1141 break;
<> 144:ef7eb2e8f9f7 1142 }
<> 144:ef7eb2e8f9f7 1143 #endif /* RCC_CFGR3_UART4SW */
<> 144:ef7eb2e8f9f7 1144 #if defined(RCC_CFGR3_UART5SW)
<> 144:ef7eb2e8f9f7 1145 case RCC_PERIPHCLK_UART5:
<> 144:ef7eb2e8f9f7 1146 {
<> 144:ef7eb2e8f9f7 1147 /* Get the current UART5 source */
<> 144:ef7eb2e8f9f7 1148 srcclk = __HAL_RCC_GET_UART5_SOURCE();
<> 144:ef7eb2e8f9f7 1149
<> 144:ef7eb2e8f9f7 1150 /* Check if UART5 clock selection is PCLK1 */
<> 144:ef7eb2e8f9f7 1151 if (srcclk == RCC_UART5CLKSOURCE_PCLK1)
<> 144:ef7eb2e8f9f7 1152 {
<> 144:ef7eb2e8f9f7 1153 frequency = HAL_RCC_GetPCLK1Freq();
<> 144:ef7eb2e8f9f7 1154 }
<> 144:ef7eb2e8f9f7 1155 /* Check if HSI is ready and if UART5 clock selection is HSI */
<> 144:ef7eb2e8f9f7 1156 else if ((srcclk == RCC_UART5CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
<> 144:ef7eb2e8f9f7 1157 {
<> 144:ef7eb2e8f9f7 1158 frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 1159 }
<> 144:ef7eb2e8f9f7 1160 /* Check if UART5 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1161 else if (srcclk == RCC_UART5CLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 1162 {
<> 144:ef7eb2e8f9f7 1163 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 1164 }
<> 144:ef7eb2e8f9f7 1165 /* Check if LSE is ready and if UART5 clock selection is LSE */
<> 144:ef7eb2e8f9f7 1166 else if ((srcclk == RCC_UART5CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
<> 144:ef7eb2e8f9f7 1167 {
<> 144:ef7eb2e8f9f7 1168 frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 1169 }
<> 144:ef7eb2e8f9f7 1170 /* Clock not enabled for UART5*/
<> 144:ef7eb2e8f9f7 1171 else
<> 144:ef7eb2e8f9f7 1172 {
<> 144:ef7eb2e8f9f7 1173 frequency = 0;
<> 144:ef7eb2e8f9f7 1174 }
<> 144:ef7eb2e8f9f7 1175 break;
<> 144:ef7eb2e8f9f7 1176 }
<> 144:ef7eb2e8f9f7 1177 #endif /* RCC_CFGR3_UART5SW */
<> 144:ef7eb2e8f9f7 1178 case RCC_PERIPHCLK_I2C1:
<> 144:ef7eb2e8f9f7 1179 {
<> 144:ef7eb2e8f9f7 1180 /* Get the current I2C1 source */
<> 144:ef7eb2e8f9f7 1181 srcclk = __HAL_RCC_GET_I2C1_SOURCE();
<> 144:ef7eb2e8f9f7 1182
<> 144:ef7eb2e8f9f7 1183 /* Check if HSI is ready and if I2C1 clock selection is HSI */
<> 144:ef7eb2e8f9f7 1184 if ((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
<> 144:ef7eb2e8f9f7 1185 {
<> 144:ef7eb2e8f9f7 1186 frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 1187 }
<> 144:ef7eb2e8f9f7 1188 /* Check if I2C1 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1189 else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 1190 {
<> 144:ef7eb2e8f9f7 1191 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 1192 }
<> 144:ef7eb2e8f9f7 1193 /* Clock not enabled for I2C1*/
<> 144:ef7eb2e8f9f7 1194 else
<> 144:ef7eb2e8f9f7 1195 {
<> 144:ef7eb2e8f9f7 1196 frequency = 0;
<> 144:ef7eb2e8f9f7 1197 }
<> 144:ef7eb2e8f9f7 1198 break;
<> 144:ef7eb2e8f9f7 1199 }
<> 144:ef7eb2e8f9f7 1200 #if defined(RCC_CFGR3_I2C2SW)
<> 144:ef7eb2e8f9f7 1201 case RCC_PERIPHCLK_I2C2:
<> 144:ef7eb2e8f9f7 1202 {
<> 144:ef7eb2e8f9f7 1203 /* Get the current I2C2 source */
<> 144:ef7eb2e8f9f7 1204 srcclk = __HAL_RCC_GET_I2C2_SOURCE();
<> 144:ef7eb2e8f9f7 1205
<> 144:ef7eb2e8f9f7 1206 /* Check if HSI is ready and if I2C2 clock selection is HSI */
<> 144:ef7eb2e8f9f7 1207 if ((srcclk == RCC_I2C2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
<> 144:ef7eb2e8f9f7 1208 {
<> 144:ef7eb2e8f9f7 1209 frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 1210 }
<> 144:ef7eb2e8f9f7 1211 /* Check if I2C2 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1212 else if (srcclk == RCC_I2C2CLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 1213 {
<> 144:ef7eb2e8f9f7 1214 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 1215 }
<> 144:ef7eb2e8f9f7 1216 /* Clock not enabled for I2C2*/
<> 144:ef7eb2e8f9f7 1217 else
<> 144:ef7eb2e8f9f7 1218 {
<> 144:ef7eb2e8f9f7 1219 frequency = 0;
<> 144:ef7eb2e8f9f7 1220 }
<> 144:ef7eb2e8f9f7 1221 break;
<> 144:ef7eb2e8f9f7 1222 }
<> 144:ef7eb2e8f9f7 1223 #endif /* RCC_CFGR3_I2C2SW */
<> 144:ef7eb2e8f9f7 1224 #if defined(RCC_CFGR3_I2C3SW)
<> 144:ef7eb2e8f9f7 1225 case RCC_PERIPHCLK_I2C3:
<> 144:ef7eb2e8f9f7 1226 {
<> 144:ef7eb2e8f9f7 1227 /* Get the current I2C3 source */
<> 144:ef7eb2e8f9f7 1228 srcclk = __HAL_RCC_GET_I2C3_SOURCE();
<> 144:ef7eb2e8f9f7 1229
<> 144:ef7eb2e8f9f7 1230 /* Check if HSI is ready and if I2C3 clock selection is HSI */
<> 144:ef7eb2e8f9f7 1231 if ((srcclk == RCC_I2C3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
<> 144:ef7eb2e8f9f7 1232 {
<> 144:ef7eb2e8f9f7 1233 frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 1234 }
<> 144:ef7eb2e8f9f7 1235 /* Check if I2C3 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1236 else if (srcclk == RCC_I2C3CLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 1237 {
<> 144:ef7eb2e8f9f7 1238 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 1239 }
<> 144:ef7eb2e8f9f7 1240 /* Clock not enabled for I2C3*/
<> 144:ef7eb2e8f9f7 1241 else
<> 144:ef7eb2e8f9f7 1242 {
<> 144:ef7eb2e8f9f7 1243 frequency = 0;
<> 144:ef7eb2e8f9f7 1244 }
<> 144:ef7eb2e8f9f7 1245 break;
<> 144:ef7eb2e8f9f7 1246 }
<> 144:ef7eb2e8f9f7 1247 #endif /* RCC_CFGR3_I2C3SW */
<> 144:ef7eb2e8f9f7 1248 #if defined(RCC_CFGR_I2SSRC)
<> 144:ef7eb2e8f9f7 1249 case RCC_PERIPHCLK_I2S:
<> 144:ef7eb2e8f9f7 1250 {
<> 144:ef7eb2e8f9f7 1251 /* Get the current I2S source */
<> 144:ef7eb2e8f9f7 1252 srcclk = __HAL_RCC_GET_I2S_SOURCE();
<> 144:ef7eb2e8f9f7 1253
<> 144:ef7eb2e8f9f7 1254 /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin */
<> 144:ef7eb2e8f9f7 1255 if (srcclk == RCC_I2SCLKSOURCE_EXT)
<> 144:ef7eb2e8f9f7 1256 {
<> 144:ef7eb2e8f9f7 1257 /* External clock used. Frequency cannot be returned.*/
<> 144:ef7eb2e8f9f7 1258 frequency = 0xDEADDEADU;
<> 144:ef7eb2e8f9f7 1259 }
<> 144:ef7eb2e8f9f7 1260 /* Check if I2S clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1261 else if (srcclk == RCC_I2SCLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 1262 {
<> 144:ef7eb2e8f9f7 1263 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 1264 }
<> 144:ef7eb2e8f9f7 1265 /* Clock not enabled for I2S*/
<> 144:ef7eb2e8f9f7 1266 else
<> 144:ef7eb2e8f9f7 1267 {
<> 144:ef7eb2e8f9f7 1268 frequency = 0;
<> 144:ef7eb2e8f9f7 1269 }
<> 144:ef7eb2e8f9f7 1270 break;
<> 144:ef7eb2e8f9f7 1271 }
<> 144:ef7eb2e8f9f7 1272 #endif /* RCC_CFGR_I2SSRC */
<> 144:ef7eb2e8f9f7 1273 #if defined(RCC_CFGR_USBPRE)
<> 144:ef7eb2e8f9f7 1274 case RCC_PERIPHCLK_USB:
<> 144:ef7eb2e8f9f7 1275 {
<> 144:ef7eb2e8f9f7 1276 /* Check if PLL is ready */
<> 144:ef7eb2e8f9f7 1277 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
<> 144:ef7eb2e8f9f7 1278 {
<> 144:ef7eb2e8f9f7 1279 /* Get the current USB source */
<> 144:ef7eb2e8f9f7 1280 srcclk = __HAL_RCC_GET_USB_SOURCE();
<> 144:ef7eb2e8f9f7 1281
<> 144:ef7eb2e8f9f7 1282 /* Check if USB clock selection is not divided */
<> 144:ef7eb2e8f9f7 1283 if (srcclk == RCC_USBCLKSOURCE_PLL)
<> 144:ef7eb2e8f9f7 1284 {
<> 144:ef7eb2e8f9f7 1285 frequency = RCC_GetPLLCLKFreq();
<> 144:ef7eb2e8f9f7 1286 }
<> 144:ef7eb2e8f9f7 1287 /* Check if USB clock selection is divided by 1.5 */
<> 144:ef7eb2e8f9f7 1288 else /* RCC_USBCLKSOURCE_PLL_DIV1_5 */
<> 144:ef7eb2e8f9f7 1289 {
<> 144:ef7eb2e8f9f7 1290 frequency = (RCC_GetPLLCLKFreq() * 3) / 2;
<> 144:ef7eb2e8f9f7 1291 }
<> 144:ef7eb2e8f9f7 1292 }
<> 144:ef7eb2e8f9f7 1293 /* Clock not enabled for USB*/
<> 144:ef7eb2e8f9f7 1294 else
<> 144:ef7eb2e8f9f7 1295 {
<> 144:ef7eb2e8f9f7 1296 frequency = 0;
<> 144:ef7eb2e8f9f7 1297 }
<> 144:ef7eb2e8f9f7 1298 break;
<> 144:ef7eb2e8f9f7 1299 }
<> 144:ef7eb2e8f9f7 1300 #endif /* RCC_CFGR_USBPRE */
<> 144:ef7eb2e8f9f7 1301 #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR_ADCPRE)
<> 144:ef7eb2e8f9f7 1302 case RCC_PERIPHCLK_ADC1:
<> 144:ef7eb2e8f9f7 1303 {
<> 144:ef7eb2e8f9f7 1304 /* Get the current ADC1 source */
<> 144:ef7eb2e8f9f7 1305 srcclk = __HAL_RCC_GET_ADC1_SOURCE();
<> 144:ef7eb2e8f9f7 1306 #if defined(RCC_CFGR2_ADC1PRES)
<> 144:ef7eb2e8f9f7 1307 /* Check if ADC1 clock selection is AHB */
<> 144:ef7eb2e8f9f7 1308 if (srcclk == RCC_ADC1PLLCLK_OFF)
<> 144:ef7eb2e8f9f7 1309 {
<> 144:ef7eb2e8f9f7 1310 frequency = SystemCoreClock;
<> 144:ef7eb2e8f9f7 1311 }
<> 144:ef7eb2e8f9f7 1312 /* PLL clock has been selected */
<> 144:ef7eb2e8f9f7 1313 else
<> 144:ef7eb2e8f9f7 1314 {
<> 144:ef7eb2e8f9f7 1315 /* Check if PLL is ready */
<> 144:ef7eb2e8f9f7 1316 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
<> 144:ef7eb2e8f9f7 1317 {
<> 144:ef7eb2e8f9f7 1318 /* Frequency is the PLL frequency divided by ADC prescaler (1/2/4/6/8/10/12/16/32/64/128/256) */
<> 144:ef7eb2e8f9f7 1319 frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADC1PRES)) & 0xF];
<> 144:ef7eb2e8f9f7 1320 }
<> 144:ef7eb2e8f9f7 1321 /* Clock not enabled for ADC1*/
<> 144:ef7eb2e8f9f7 1322 else
<> 144:ef7eb2e8f9f7 1323 {
<> 144:ef7eb2e8f9f7 1324 frequency = 0;
<> 144:ef7eb2e8f9f7 1325 }
<> 144:ef7eb2e8f9f7 1326 }
<> 144:ef7eb2e8f9f7 1327 #else /* RCC_CFGR_ADCPRE */
<> 144:ef7eb2e8f9f7 1328 /* ADC1 is set to PLCK2 frequency divided by 2/4/6/8 */
<> 144:ef7eb2e8f9f7 1329 frequency = HAL_RCC_GetPCLK2Freq() / (((srcclk >> POSITION_VAL(RCC_CFGR_ADCPRE)) + 1) * 2);
<> 144:ef7eb2e8f9f7 1330 #endif /* RCC_CFGR2_ADC1PRES */
<> 144:ef7eb2e8f9f7 1331 break;
<> 144:ef7eb2e8f9f7 1332 }
<> 144:ef7eb2e8f9f7 1333 #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR_ADCPRE */
<> 144:ef7eb2e8f9f7 1334 #if defined(RCC_CFGR2_ADCPRE12)
<> 144:ef7eb2e8f9f7 1335 case RCC_PERIPHCLK_ADC12:
<> 144:ef7eb2e8f9f7 1336 {
<> 144:ef7eb2e8f9f7 1337 /* Get the current ADC12 source */
<> 144:ef7eb2e8f9f7 1338 srcclk = __HAL_RCC_GET_ADC12_SOURCE();
<> 144:ef7eb2e8f9f7 1339 /* Check if ADC12 clock selection is AHB */
<> 144:ef7eb2e8f9f7 1340 if (srcclk == RCC_ADC12PLLCLK_OFF)
<> 144:ef7eb2e8f9f7 1341 {
<> 144:ef7eb2e8f9f7 1342 frequency = SystemCoreClock;
<> 144:ef7eb2e8f9f7 1343 }
<> 144:ef7eb2e8f9f7 1344 /* PLL clock has been selected */
<> 144:ef7eb2e8f9f7 1345 else
<> 144:ef7eb2e8f9f7 1346 {
<> 144:ef7eb2e8f9f7 1347 /* Check if PLL is ready */
<> 144:ef7eb2e8f9f7 1348 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
<> 144:ef7eb2e8f9f7 1349 {
<> 144:ef7eb2e8f9f7 1350 /* Frequency is the PLL frequency divided by ADC prescaler (1/2/4/6/8/10/12/16/32/64/128/256) */
<> 144:ef7eb2e8f9f7 1351 frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADCPRE12)) & 0xF];
<> 144:ef7eb2e8f9f7 1352 }
<> 144:ef7eb2e8f9f7 1353 /* Clock not enabled for ADC12*/
<> 144:ef7eb2e8f9f7 1354 else
<> 144:ef7eb2e8f9f7 1355 {
<> 144:ef7eb2e8f9f7 1356 frequency = 0;
<> 144:ef7eb2e8f9f7 1357 }
<> 144:ef7eb2e8f9f7 1358 }
<> 144:ef7eb2e8f9f7 1359 break;
<> 144:ef7eb2e8f9f7 1360 }
<> 144:ef7eb2e8f9f7 1361 #endif /* RCC_CFGR2_ADCPRE12 */
<> 144:ef7eb2e8f9f7 1362 #if defined(RCC_CFGR2_ADCPRE34)
<> 144:ef7eb2e8f9f7 1363 case RCC_PERIPHCLK_ADC34:
<> 144:ef7eb2e8f9f7 1364 {
<> 144:ef7eb2e8f9f7 1365 /* Get the current ADC34 source */
<> 144:ef7eb2e8f9f7 1366 srcclk = __HAL_RCC_GET_ADC34_SOURCE();
<> 144:ef7eb2e8f9f7 1367 /* Check if ADC34 clock selection is AHB */
<> 144:ef7eb2e8f9f7 1368 if (srcclk == RCC_ADC34PLLCLK_OFF)
<> 144:ef7eb2e8f9f7 1369 {
<> 144:ef7eb2e8f9f7 1370 frequency = SystemCoreClock;
<> 144:ef7eb2e8f9f7 1371 }
<> 144:ef7eb2e8f9f7 1372 /* PLL clock has been selected */
<> 144:ef7eb2e8f9f7 1373 else
<> 144:ef7eb2e8f9f7 1374 {
<> 144:ef7eb2e8f9f7 1375 /* Check if PLL is ready */
<> 144:ef7eb2e8f9f7 1376 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
<> 144:ef7eb2e8f9f7 1377 {
<> 144:ef7eb2e8f9f7 1378 /* Frequency is the PLL frequency divided by ADC prescaler (1/2/4/6/8/10/12/16/32/64/128/256) */
<> 144:ef7eb2e8f9f7 1379 frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADCPRE34)) & 0xF];
<> 144:ef7eb2e8f9f7 1380 }
<> 144:ef7eb2e8f9f7 1381 /* Clock not enabled for ADC34*/
<> 144:ef7eb2e8f9f7 1382 else
<> 144:ef7eb2e8f9f7 1383 {
<> 144:ef7eb2e8f9f7 1384 frequency = 0;
<> 144:ef7eb2e8f9f7 1385 }
<> 144:ef7eb2e8f9f7 1386 }
<> 144:ef7eb2e8f9f7 1387 break;
<> 144:ef7eb2e8f9f7 1388 }
<> 144:ef7eb2e8f9f7 1389 #endif /* RCC_CFGR2_ADCPRE34 */
<> 144:ef7eb2e8f9f7 1390 #if defined(RCC_CFGR3_TIM1SW)
<> 144:ef7eb2e8f9f7 1391 case RCC_PERIPHCLK_TIM1:
<> 144:ef7eb2e8f9f7 1392 {
<> 144:ef7eb2e8f9f7 1393 /* Get the current TIM1 source */
<> 144:ef7eb2e8f9f7 1394 srcclk = __HAL_RCC_GET_TIM1_SOURCE();
<> 144:ef7eb2e8f9f7 1395
<> 144:ef7eb2e8f9f7 1396 /* Check if PLL is ready and if TIM1 clock selection is PLL */
<> 144:ef7eb2e8f9f7 1397 if ((srcclk == RCC_TIM1CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
<> 144:ef7eb2e8f9f7 1398 {
<> 144:ef7eb2e8f9f7 1399 frequency = RCC_GetPLLCLKFreq();
<> 144:ef7eb2e8f9f7 1400 }
<> 144:ef7eb2e8f9f7 1401 /* Check if TIM1 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1402 else if (srcclk == RCC_TIM1CLK_HCLK)
<> 144:ef7eb2e8f9f7 1403 {
<> 144:ef7eb2e8f9f7 1404 frequency = SystemCoreClock;
<> 144:ef7eb2e8f9f7 1405 }
<> 144:ef7eb2e8f9f7 1406 /* Clock not enabled for TIM1*/
<> 144:ef7eb2e8f9f7 1407 else
<> 144:ef7eb2e8f9f7 1408 {
<> 144:ef7eb2e8f9f7 1409 frequency = 0;
<> 144:ef7eb2e8f9f7 1410 }
<> 144:ef7eb2e8f9f7 1411 break;
<> 144:ef7eb2e8f9f7 1412 }
<> 144:ef7eb2e8f9f7 1413 #endif /* RCC_CFGR3_TIM1SW */
<> 144:ef7eb2e8f9f7 1414 #if defined(RCC_CFGR3_TIM2SW)
<> 144:ef7eb2e8f9f7 1415 case RCC_PERIPHCLK_TIM2:
<> 144:ef7eb2e8f9f7 1416 {
<> 144:ef7eb2e8f9f7 1417 /* Get the current TIM2 source */
<> 144:ef7eb2e8f9f7 1418 srcclk = __HAL_RCC_GET_TIM2_SOURCE();
<> 144:ef7eb2e8f9f7 1419
<> 144:ef7eb2e8f9f7 1420 /* Check if PLL is ready and if TIM2 clock selection is PLL */
<> 144:ef7eb2e8f9f7 1421 if ((srcclk == RCC_TIM2CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
<> 144:ef7eb2e8f9f7 1422 {
<> 144:ef7eb2e8f9f7 1423 frequency = RCC_GetPLLCLKFreq();
<> 144:ef7eb2e8f9f7 1424 }
<> 144:ef7eb2e8f9f7 1425 /* Check if TIM2 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1426 else if (srcclk == RCC_TIM2CLK_HCLK)
<> 144:ef7eb2e8f9f7 1427 {
<> 144:ef7eb2e8f9f7 1428 frequency = SystemCoreClock;
<> 144:ef7eb2e8f9f7 1429 }
<> 144:ef7eb2e8f9f7 1430 /* Clock not enabled for TIM2*/
<> 144:ef7eb2e8f9f7 1431 else
<> 144:ef7eb2e8f9f7 1432 {
<> 144:ef7eb2e8f9f7 1433 frequency = 0;
<> 144:ef7eb2e8f9f7 1434 }
<> 144:ef7eb2e8f9f7 1435 break;
<> 144:ef7eb2e8f9f7 1436 }
<> 144:ef7eb2e8f9f7 1437 #endif /* RCC_CFGR3_TIM2SW */
<> 144:ef7eb2e8f9f7 1438 #if defined(RCC_CFGR3_TIM8SW)
<> 144:ef7eb2e8f9f7 1439 case RCC_PERIPHCLK_TIM8:
<> 144:ef7eb2e8f9f7 1440 {
<> 144:ef7eb2e8f9f7 1441 /* Get the current TIM8 source */
<> 144:ef7eb2e8f9f7 1442 srcclk = __HAL_RCC_GET_TIM8_SOURCE();
<> 144:ef7eb2e8f9f7 1443
<> 144:ef7eb2e8f9f7 1444 /* Check if PLL is ready and if TIM8 clock selection is PLL */
<> 144:ef7eb2e8f9f7 1445 if ((srcclk == RCC_TIM8CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
<> 144:ef7eb2e8f9f7 1446 {
<> 144:ef7eb2e8f9f7 1447 frequency = RCC_GetPLLCLKFreq();
<> 144:ef7eb2e8f9f7 1448 }
<> 144:ef7eb2e8f9f7 1449 /* Check if TIM8 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1450 else if (srcclk == RCC_TIM8CLK_HCLK)
<> 144:ef7eb2e8f9f7 1451 {
<> 144:ef7eb2e8f9f7 1452 frequency = SystemCoreClock;
<> 144:ef7eb2e8f9f7 1453 }
<> 144:ef7eb2e8f9f7 1454 /* Clock not enabled for TIM8*/
<> 144:ef7eb2e8f9f7 1455 else
<> 144:ef7eb2e8f9f7 1456 {
<> 144:ef7eb2e8f9f7 1457 frequency = 0;
<> 144:ef7eb2e8f9f7 1458 }
<> 144:ef7eb2e8f9f7 1459 break;
<> 144:ef7eb2e8f9f7 1460 }
<> 144:ef7eb2e8f9f7 1461 #endif /* RCC_CFGR3_TIM8SW */
<> 144:ef7eb2e8f9f7 1462 #if defined(RCC_CFGR3_TIM15SW)
<> 144:ef7eb2e8f9f7 1463 case RCC_PERIPHCLK_TIM15:
<> 144:ef7eb2e8f9f7 1464 {
<> 144:ef7eb2e8f9f7 1465 /* Get the current TIM15 source */
<> 144:ef7eb2e8f9f7 1466 srcclk = __HAL_RCC_GET_TIM15_SOURCE();
<> 144:ef7eb2e8f9f7 1467
<> 144:ef7eb2e8f9f7 1468 /* Check if PLL is ready and if TIM15 clock selection is PLL */
<> 144:ef7eb2e8f9f7 1469 if ((srcclk == RCC_TIM15CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
<> 144:ef7eb2e8f9f7 1470 {
<> 144:ef7eb2e8f9f7 1471 frequency = RCC_GetPLLCLKFreq();
<> 144:ef7eb2e8f9f7 1472 }
<> 144:ef7eb2e8f9f7 1473 /* Check if TIM15 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1474 else if (srcclk == RCC_TIM15CLK_HCLK)
<> 144:ef7eb2e8f9f7 1475 {
<> 144:ef7eb2e8f9f7 1476 frequency = SystemCoreClock;
<> 144:ef7eb2e8f9f7 1477 }
<> 144:ef7eb2e8f9f7 1478 /* Clock not enabled for TIM15*/
<> 144:ef7eb2e8f9f7 1479 else
<> 144:ef7eb2e8f9f7 1480 {
<> 144:ef7eb2e8f9f7 1481 frequency = 0;
<> 144:ef7eb2e8f9f7 1482 }
<> 144:ef7eb2e8f9f7 1483 break;
<> 144:ef7eb2e8f9f7 1484 }
<> 144:ef7eb2e8f9f7 1485 #endif /* RCC_CFGR3_TIM15SW */
<> 144:ef7eb2e8f9f7 1486 #if defined(RCC_CFGR3_TIM16SW)
<> 144:ef7eb2e8f9f7 1487 case RCC_PERIPHCLK_TIM16:
<> 144:ef7eb2e8f9f7 1488 {
<> 144:ef7eb2e8f9f7 1489 /* Get the current TIM16 source */
<> 144:ef7eb2e8f9f7 1490 srcclk = __HAL_RCC_GET_TIM16_SOURCE();
<> 144:ef7eb2e8f9f7 1491
<> 144:ef7eb2e8f9f7 1492 /* Check if PLL is ready and if TIM16 clock selection is PLL */
<> 144:ef7eb2e8f9f7 1493 if ((srcclk == RCC_TIM16CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
<> 144:ef7eb2e8f9f7 1494 {
<> 144:ef7eb2e8f9f7 1495 frequency = RCC_GetPLLCLKFreq();
<> 144:ef7eb2e8f9f7 1496 }
<> 144:ef7eb2e8f9f7 1497 /* Check if TIM16 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1498 else if (srcclk == RCC_TIM16CLK_HCLK)
<> 144:ef7eb2e8f9f7 1499 {
<> 144:ef7eb2e8f9f7 1500 frequency = SystemCoreClock;
<> 144:ef7eb2e8f9f7 1501 }
<> 144:ef7eb2e8f9f7 1502 /* Clock not enabled for TIM16*/
<> 144:ef7eb2e8f9f7 1503 else
<> 144:ef7eb2e8f9f7 1504 {
<> 144:ef7eb2e8f9f7 1505 frequency = 0;
<> 144:ef7eb2e8f9f7 1506 }
<> 144:ef7eb2e8f9f7 1507 break;
<> 144:ef7eb2e8f9f7 1508 }
<> 144:ef7eb2e8f9f7 1509 #endif /* RCC_CFGR3_TIM16SW */
<> 144:ef7eb2e8f9f7 1510 #if defined(RCC_CFGR3_TIM17SW)
<> 144:ef7eb2e8f9f7 1511 case RCC_PERIPHCLK_TIM17:
<> 144:ef7eb2e8f9f7 1512 {
<> 144:ef7eb2e8f9f7 1513 /* Get the current TIM17 source */
<> 144:ef7eb2e8f9f7 1514 srcclk = __HAL_RCC_GET_TIM17_SOURCE();
<> 144:ef7eb2e8f9f7 1515
<> 144:ef7eb2e8f9f7 1516 /* Check if PLL is ready and if TIM17 clock selection is PLL */
<> 144:ef7eb2e8f9f7 1517 if ((srcclk == RCC_TIM17CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
<> 144:ef7eb2e8f9f7 1518 {
<> 144:ef7eb2e8f9f7 1519 frequency = RCC_GetPLLCLKFreq();
<> 144:ef7eb2e8f9f7 1520 }
<> 144:ef7eb2e8f9f7 1521 /* Check if TIM17 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1522 else if (srcclk == RCC_TIM17CLK_HCLK)
<> 144:ef7eb2e8f9f7 1523 {
<> 144:ef7eb2e8f9f7 1524 frequency = SystemCoreClock;
<> 144:ef7eb2e8f9f7 1525 }
<> 144:ef7eb2e8f9f7 1526 /* Clock not enabled for TIM17*/
<> 144:ef7eb2e8f9f7 1527 else
<> 144:ef7eb2e8f9f7 1528 {
<> 144:ef7eb2e8f9f7 1529 frequency = 0;
<> 144:ef7eb2e8f9f7 1530 }
<> 144:ef7eb2e8f9f7 1531 break;
<> 144:ef7eb2e8f9f7 1532 }
<> 144:ef7eb2e8f9f7 1533 #endif /* RCC_CFGR3_TIM17SW */
<> 144:ef7eb2e8f9f7 1534 #if defined(RCC_CFGR3_TIM20SW)
<> 144:ef7eb2e8f9f7 1535 case RCC_PERIPHCLK_TIM20:
<> 144:ef7eb2e8f9f7 1536 {
<> 144:ef7eb2e8f9f7 1537 /* Get the current TIM20 source */
<> 144:ef7eb2e8f9f7 1538 srcclk = __HAL_RCC_GET_TIM20_SOURCE();
<> 144:ef7eb2e8f9f7 1539
<> 144:ef7eb2e8f9f7 1540 /* Check if PLL is ready and if TIM20 clock selection is PLL */
<> 144:ef7eb2e8f9f7 1541 if ((srcclk == RCC_TIM20CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
<> 144:ef7eb2e8f9f7 1542 {
<> 144:ef7eb2e8f9f7 1543 frequency = RCC_GetPLLCLKFreq();
<> 144:ef7eb2e8f9f7 1544 }
<> 144:ef7eb2e8f9f7 1545 /* Check if TIM20 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1546 else if (srcclk == RCC_TIM20CLK_HCLK)
<> 144:ef7eb2e8f9f7 1547 {
<> 144:ef7eb2e8f9f7 1548 frequency = SystemCoreClock;
<> 144:ef7eb2e8f9f7 1549 }
<> 144:ef7eb2e8f9f7 1550 /* Clock not enabled for TIM20*/
<> 144:ef7eb2e8f9f7 1551 else
<> 144:ef7eb2e8f9f7 1552 {
<> 144:ef7eb2e8f9f7 1553 frequency = 0;
<> 144:ef7eb2e8f9f7 1554 }
<> 144:ef7eb2e8f9f7 1555 break;
<> 144:ef7eb2e8f9f7 1556 }
<> 144:ef7eb2e8f9f7 1557 #endif /* RCC_CFGR3_TIM20SW */
<> 144:ef7eb2e8f9f7 1558 #if defined(RCC_CFGR3_TIM34SW)
<> 144:ef7eb2e8f9f7 1559 case RCC_PERIPHCLK_TIM34:
<> 144:ef7eb2e8f9f7 1560 {
<> 144:ef7eb2e8f9f7 1561 /* Get the current TIM34 source */
<> 144:ef7eb2e8f9f7 1562 srcclk = __HAL_RCC_GET_TIM34_SOURCE();
<> 144:ef7eb2e8f9f7 1563
<> 144:ef7eb2e8f9f7 1564 /* Check if PLL is ready and if TIM34 clock selection is PLL */
<> 144:ef7eb2e8f9f7 1565 if ((srcclk == RCC_TIM34CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
<> 144:ef7eb2e8f9f7 1566 {
<> 144:ef7eb2e8f9f7 1567 frequency = RCC_GetPLLCLKFreq();
<> 144:ef7eb2e8f9f7 1568 }
<> 144:ef7eb2e8f9f7 1569 /* Check if TIM34 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1570 else if (srcclk == RCC_TIM34CLK_HCLK)
<> 144:ef7eb2e8f9f7 1571 {
<> 144:ef7eb2e8f9f7 1572 frequency = SystemCoreClock;
<> 144:ef7eb2e8f9f7 1573 }
<> 144:ef7eb2e8f9f7 1574 /* Clock not enabled for TIM34*/
<> 144:ef7eb2e8f9f7 1575 else
<> 144:ef7eb2e8f9f7 1576 {
<> 144:ef7eb2e8f9f7 1577 frequency = 0;
<> 144:ef7eb2e8f9f7 1578 }
<> 144:ef7eb2e8f9f7 1579 break;
<> 144:ef7eb2e8f9f7 1580 }
<> 144:ef7eb2e8f9f7 1581 #endif /* RCC_CFGR3_TIM34SW */
<> 144:ef7eb2e8f9f7 1582 #if defined(RCC_CFGR3_HRTIM1SW)
<> 144:ef7eb2e8f9f7 1583 case RCC_PERIPHCLK_HRTIM1:
<> 144:ef7eb2e8f9f7 1584 {
<> 144:ef7eb2e8f9f7 1585 /* Get the current HRTIM1 source */
<> 144:ef7eb2e8f9f7 1586 srcclk = __HAL_RCC_GET_HRTIM1_SOURCE();
<> 144:ef7eb2e8f9f7 1587
<> 144:ef7eb2e8f9f7 1588 /* Check if PLL is ready and if HRTIM1 clock selection is PLL */
<> 144:ef7eb2e8f9f7 1589 if ((srcclk == RCC_HRTIM1CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
<> 144:ef7eb2e8f9f7 1590 {
<> 144:ef7eb2e8f9f7 1591 frequency = RCC_GetPLLCLKFreq();
<> 144:ef7eb2e8f9f7 1592 }
<> 144:ef7eb2e8f9f7 1593 /* Check if HRTIM1 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1594 else if (srcclk == RCC_HRTIM1CLK_HCLK)
<> 144:ef7eb2e8f9f7 1595 {
<> 144:ef7eb2e8f9f7 1596 frequency = SystemCoreClock;
<> 144:ef7eb2e8f9f7 1597 }
<> 144:ef7eb2e8f9f7 1598 /* Clock not enabled for HRTIM1*/
<> 144:ef7eb2e8f9f7 1599 else
<> 144:ef7eb2e8f9f7 1600 {
<> 144:ef7eb2e8f9f7 1601 frequency = 0;
<> 144:ef7eb2e8f9f7 1602 }
<> 144:ef7eb2e8f9f7 1603 break;
<> 144:ef7eb2e8f9f7 1604 }
<> 144:ef7eb2e8f9f7 1605 #endif /* RCC_CFGR3_HRTIM1SW */
<> 144:ef7eb2e8f9f7 1606 #if defined(RCC_CFGR_SDADCPRE)
<> 144:ef7eb2e8f9f7 1607 case RCC_PERIPHCLK_SDADC:
<> 144:ef7eb2e8f9f7 1608 {
<> 144:ef7eb2e8f9f7 1609 /* Get the current SDADC source */
<> 144:ef7eb2e8f9f7 1610 srcclk = __HAL_RCC_GET_SDADC_SOURCE();
<> 144:ef7eb2e8f9f7 1611 /* Frequency is the system frequency divided by SDADC prescaler (2/4/6/8/10/12/14/16/20/24/28/32/36/40/44/48) */
<> 144:ef7eb2e8f9f7 1612 frequency = SystemCoreClock / sdadc_prescaler_table[(srcclk >> POSITION_VAL(RCC_CFGR_SDADCPRE)) & 0xF];
<> 144:ef7eb2e8f9f7 1613 break;
<> 144:ef7eb2e8f9f7 1614 }
<> 144:ef7eb2e8f9f7 1615 #endif /* RCC_CFGR_SDADCPRE */
<> 144:ef7eb2e8f9f7 1616 #if defined(RCC_CFGR3_CECSW)
<> 144:ef7eb2e8f9f7 1617 case RCC_PERIPHCLK_CEC:
<> 144:ef7eb2e8f9f7 1618 {
<> 144:ef7eb2e8f9f7 1619 /* Get the current CEC source */
<> 144:ef7eb2e8f9f7 1620 srcclk = __HAL_RCC_GET_CEC_SOURCE();
<> 144:ef7eb2e8f9f7 1621
<> 144:ef7eb2e8f9f7 1622 /* Check if HSI is ready and if CEC clock selection is HSI */
<> 144:ef7eb2e8f9f7 1623 if ((srcclk == RCC_CECCLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
<> 144:ef7eb2e8f9f7 1624 {
<> 144:ef7eb2e8f9f7 1625 frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 1626 }
<> 144:ef7eb2e8f9f7 1627 /* Check if LSE is ready and if CEC clock selection is LSE */
<> 144:ef7eb2e8f9f7 1628 else if ((srcclk == RCC_CECCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
<> 144:ef7eb2e8f9f7 1629 {
<> 144:ef7eb2e8f9f7 1630 frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 1631 }
<> 144:ef7eb2e8f9f7 1632 /* Clock not enabled for CEC*/
<> 144:ef7eb2e8f9f7 1633 else
<> 144:ef7eb2e8f9f7 1634 {
<> 144:ef7eb2e8f9f7 1635 frequency = 0;
<> 144:ef7eb2e8f9f7 1636 }
<> 144:ef7eb2e8f9f7 1637 break;
<> 144:ef7eb2e8f9f7 1638 }
<> 144:ef7eb2e8f9f7 1639 #endif /* RCC_CFGR3_CECSW */
<> 144:ef7eb2e8f9f7 1640 default:
<> 144:ef7eb2e8f9f7 1641 {
<> 144:ef7eb2e8f9f7 1642 break;
<> 144:ef7eb2e8f9f7 1643 }
<> 144:ef7eb2e8f9f7 1644 }
<> 144:ef7eb2e8f9f7 1645 return(frequency);
<> 144:ef7eb2e8f9f7 1646 }
<> 144:ef7eb2e8f9f7 1647
<> 144:ef7eb2e8f9f7 1648 /**
<> 144:ef7eb2e8f9f7 1649 * @}
<> 144:ef7eb2e8f9f7 1650 */
<> 144:ef7eb2e8f9f7 1651
<> 144:ef7eb2e8f9f7 1652 /**
<> 144:ef7eb2e8f9f7 1653 * @}
<> 144:ef7eb2e8f9f7 1654 */
<> 144:ef7eb2e8f9f7 1655
<> 144:ef7eb2e8f9f7 1656
<> 144:ef7eb2e8f9f7 1657 #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) || defined(RCC_CFGR_USBPRE) \
<> 144:ef7eb2e8f9f7 1658 || defined(RCC_CFGR3_TIM1SW) || defined(RCC_CFGR3_TIM2SW) || defined(RCC_CFGR3_TIM8SW) || defined(RCC_CFGR3_TIM15SW) \
<> 144:ef7eb2e8f9f7 1659 || defined(RCC_CFGR3_TIM16SW) || defined(RCC_CFGR3_TIM17SW) || defined(RCC_CFGR3_TIM20SW) || defined(RCC_CFGR3_TIM34SW) \
<> 144:ef7eb2e8f9f7 1660 || defined(RCC_CFGR3_HRTIM1SW)
<> 144:ef7eb2e8f9f7 1661
<> 144:ef7eb2e8f9f7 1662 /** @addtogroup RCCEx_Private_Functions
<> 144:ef7eb2e8f9f7 1663 * @{
<> 144:ef7eb2e8f9f7 1664 */
<> 144:ef7eb2e8f9f7 1665 static uint32_t RCC_GetPLLCLKFreq(void)
<> 144:ef7eb2e8f9f7 1666 {
<> 144:ef7eb2e8f9f7 1667 uint32_t pllmul = 0, pllsource = 0, prediv = 0, pllclk = 0;
<> 144:ef7eb2e8f9f7 1668
<> 144:ef7eb2e8f9f7 1669 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
<> 144:ef7eb2e8f9f7 1670 pllmul = ( pllmul >> 18) + 2;
<> 144:ef7eb2e8f9f7 1671 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
<> 144:ef7eb2e8f9f7 1672 #if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
<> 144:ef7eb2e8f9f7 1673 if (pllsource != RCC_PLLSOURCE_HSI)
<> 144:ef7eb2e8f9f7 1674 {
<> 144:ef7eb2e8f9f7 1675 prediv = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
<> 144:ef7eb2e8f9f7 1676 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
<> 144:ef7eb2e8f9f7 1677 pllclk = (HSE_VALUE/prediv) * pllmul;
<> 144:ef7eb2e8f9f7 1678 }
<> 144:ef7eb2e8f9f7 1679 else
<> 144:ef7eb2e8f9f7 1680 {
<> 144:ef7eb2e8f9f7 1681 /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
<> 144:ef7eb2e8f9f7 1682 pllclk = (HSI_VALUE >> 1) * pllmul;
<> 144:ef7eb2e8f9f7 1683 }
<> 144:ef7eb2e8f9f7 1684 #else
<> 144:ef7eb2e8f9f7 1685 prediv = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
<> 144:ef7eb2e8f9f7 1686 if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
<> 144:ef7eb2e8f9f7 1687 {
<> 144:ef7eb2e8f9f7 1688 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
<> 144:ef7eb2e8f9f7 1689 pllclk = (HSE_VALUE/prediv) * pllmul;
<> 144:ef7eb2e8f9f7 1690 }
<> 144:ef7eb2e8f9f7 1691 else
<> 144:ef7eb2e8f9f7 1692 {
<> 144:ef7eb2e8f9f7 1693 /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
<> 144:ef7eb2e8f9f7 1694 pllclk = (HSI_VALUE/prediv) * pllmul;
<> 144:ef7eb2e8f9f7 1695 }
<> 144:ef7eb2e8f9f7 1696 #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
<> 144:ef7eb2e8f9f7 1697
<> 144:ef7eb2e8f9f7 1698 return pllclk;
<> 144:ef7eb2e8f9f7 1699 }
<> 144:ef7eb2e8f9f7 1700 /**
<> 144:ef7eb2e8f9f7 1701 * @}
<> 144:ef7eb2e8f9f7 1702 */
<> 144:ef7eb2e8f9f7 1703
<> 144:ef7eb2e8f9f7 1704 #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRExx || RCC_CFGR3_TIMxSW || RCC_CFGR3_HRTIM1SW || RCC_CFGR_USBPRE */
<> 144:ef7eb2e8f9f7 1705
<> 144:ef7eb2e8f9f7 1706 /**
<> 144:ef7eb2e8f9f7 1707 * @}
<> 144:ef7eb2e8f9f7 1708 */
<> 144:ef7eb2e8f9f7 1709
<> 144:ef7eb2e8f9f7 1710 #endif /* HAL_RCC_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1711
<> 144:ef7eb2e8f9f7 1712 /**
<> 144:ef7eb2e8f9f7 1713 * @}
<> 144:ef7eb2e8f9f7 1714 */
<> 144:ef7eb2e8f9f7 1715
<> 144:ef7eb2e8f9f7 1716 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/