Chau Vo / RF24

Maniacbug RF24 on Nucleo STM32

Dependents:   NRF24_master_slave NRF24_master_slave

nRF24L01.h@5:aaff7f374e2b, 2015-02-09 (annotated)

Committer:
olympux
Date:
Mon Feb 09 00:01:47 2015 +0000
Revision:
5:aaff7f374e2b
Parent:
1:8fc901e8846f 
clean code

Who changed what in which revision?

UserRevisionLine numberNew contents of line
olympux 0:707771bf6708 1 /*
olympux 0:707771bf6708 2 Copyright (c) 2007 Stefan Engelke <mbox@stefanengelke.de>
olympux 0:707771bf6708 3
olympux 1:8fc901e8846f 4 Permission is hereby granted, free of charge, to any person
olympux 1:8fc901e8846f 5 obtaining a copy of this software and associated documentation
olympux 1:8fc901e8846f 6 files (the "Software"), to deal in the Software without
olympux 1:8fc901e8846f 7 restriction, including without limitation the rights to use, copy,
olympux 1:8fc901e8846f 8 modify, merge, publish, distribute, sublicense, and/or sell copies
olympux 1:8fc901e8846f 9 of the Software, and to permit persons to whom the Software is
olympux 0:707771bf6708 10 furnished to do so, subject to the following conditions:
olympux 0:707771bf6708 11
olympux 1:8fc901e8846f 12 The above copyright notice and this permission notice shall be
olympux 0:707771bf6708 13 included in all copies or substantial portions of the Software.
olympux 0:707771bf6708 14
olympux 1:8fc901e8846f 15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
olympux 1:8fc901e8846f 16 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
olympux 1:8fc901e8846f 17 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
olympux 1:8fc901e8846f 18 NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
olympux 1:8fc901e8846f 19 HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
olympux 1:8fc901e8846f 20 WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
olympux 1:8fc901e8846f 21 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
olympux 0:707771bf6708 22 DEALINGS IN THE SOFTWARE.
olympux 0:707771bf6708 23 */
olympux 0:707771bf6708 24
olympux 0:707771bf6708 25 /* Memory Map */
olympux 0:707771bf6708 26 #define CONFIG 0x00
olympux 0:707771bf6708 27 #define EN_AA 0x01
olympux 0:707771bf6708 28 #define EN_RXADDR 0x02
olympux 0:707771bf6708 29 #define SETUP_AW 0x03
olympux 0:707771bf6708 30 #define SETUP_RETR 0x04
olympux 0:707771bf6708 31 #define RF_CH 0x05
olympux 0:707771bf6708 32 #define RF_SETUP 0x06
olympux 0:707771bf6708 33 #define STATUS 0x07
olympux 0:707771bf6708 34 #define OBSERVE_TX 0x08
olympux 0:707771bf6708 35 #define CD 0x09
olympux 0:707771bf6708 36 #define RX_ADDR_P0 0x0A
olympux 0:707771bf6708 37 #define RX_ADDR_P1 0x0B
olympux 0:707771bf6708 38 #define RX_ADDR_P2 0x0C
olympux 0:707771bf6708 39 #define RX_ADDR_P3 0x0D
olympux 0:707771bf6708 40 #define RX_ADDR_P4 0x0E
olympux 0:707771bf6708 41 #define RX_ADDR_P5 0x0F
olympux 0:707771bf6708 42 #define TX_ADDR 0x10
olympux 0:707771bf6708 43 #define RX_PW_P0 0x11
olympux 0:707771bf6708 44 #define RX_PW_P1 0x12
olympux 0:707771bf6708 45 #define RX_PW_P2 0x13
olympux 0:707771bf6708 46 #define RX_PW_P3 0x14
olympux 0:707771bf6708 47 #define RX_PW_P4 0x15
olympux 0:707771bf6708 48 #define RX_PW_P5 0x16
olympux 0:707771bf6708 49 #define FIFO_STATUS 0x17
olympux 0:707771bf6708 50 #define DYNPD 0x1C
olympux 0:707771bf6708 51 #define FEATURE 0x1D
olympux 0:707771bf6708 52
olympux 0:707771bf6708 53 /* Bit Mnemonics */
olympux 0:707771bf6708 54 #define MASK_RX_DR 6
olympux 0:707771bf6708 55 #define MASK_TX_DS 5
olympux 0:707771bf6708 56 #define MASK_MAX_RT 4
olympux 0:707771bf6708 57 #define EN_CRC 3
olympux 0:707771bf6708 58 #define CRCO 2
olympux 0:707771bf6708 59 #define PWR_UP 1
olympux 0:707771bf6708 60 #define PRIM_RX 0
olympux 0:707771bf6708 61 #define ENAA_P5 5
olympux 0:707771bf6708 62 #define ENAA_P4 4
olympux 0:707771bf6708 63 #define ENAA_P3 3
olympux 0:707771bf6708 64 #define ENAA_P2 2
olympux 0:707771bf6708 65 #define ENAA_P1 1
olympux 0:707771bf6708 66 #define ENAA_P0 0
olympux 0:707771bf6708 67 #define ERX_P5 5
olympux 0:707771bf6708 68 #define ERX_P4 4
olympux 0:707771bf6708 69 #define ERX_P3 3
olympux 0:707771bf6708 70 #define ERX_P2 2
olympux 0:707771bf6708 71 #define ERX_P1 1
olympux 0:707771bf6708 72 #define ERX_P0 0
olympux 0:707771bf6708 73 #define AW 0
olympux 0:707771bf6708 74 #define ARD 4
olympux 0:707771bf6708 75 #define ARC 0
olympux 0:707771bf6708 76 #define PLL_LOCK 4
olympux 0:707771bf6708 77 #define RF_DR 3
olympux 0:707771bf6708 78 #define RF_PWR 6
olympux 0:707771bf6708 79 #define RX_DR 6
olympux 0:707771bf6708 80 #define TX_DS 5
olympux 0:707771bf6708 81 #define MAX_RT 4
olympux 0:707771bf6708 82 #define RX_P_NO 1
olympux 0:707771bf6708 83 #define TX_FULL 0
olympux 0:707771bf6708 84 #define PLOS_CNT 4
olympux 0:707771bf6708 85 #define ARC_CNT 0
olympux 0:707771bf6708 86 #define TX_REUSE 6
olympux 0:707771bf6708 87 #define FIFO_FULL 5
olympux 0:707771bf6708 88 #define TX_EMPTY 4
olympux 0:707771bf6708 89 #define RX_FULL 1
olympux 0:707771bf6708 90 #define RX_EMPTY 0
olympux 0:707771bf6708 91 #define DPL_P5 5
olympux 0:707771bf6708 92 #define DPL_P4 4
olympux 0:707771bf6708 93 #define DPL_P3 3
olympux 0:707771bf6708 94 #define DPL_P2 2
olympux 0:707771bf6708 95 #define DPL_P1 1
olympux 0:707771bf6708 96 #define DPL_P0 0
olympux 0:707771bf6708 97 #define EN_DPL 2
olympux 0:707771bf6708 98 #define EN_ACK_PAY 1
olympux 0:707771bf6708 99 #define EN_DYN_ACK 0
olympux 0:707771bf6708 100
olympux 0:707771bf6708 101 /* Instruction Mnemonics */
olympux 0:707771bf6708 102 #define R_REGISTER 0x00
olympux 0:707771bf6708 103 #define W_REGISTER 0x20
olympux 0:707771bf6708 104 #define REGISTER_MASK 0x1F
olympux 0:707771bf6708 105 #define ACTIVATE 0x50
olympux 0:707771bf6708 106 #define R_RX_PL_WID 0x60
olympux 0:707771bf6708 107 #define R_RX_PAYLOAD 0x61
olympux 0:707771bf6708 108 #define W_TX_PAYLOAD 0xA0
olympux 0:707771bf6708 109 #define W_ACK_PAYLOAD 0xA8
olympux 0:707771bf6708 110 #define FLUSH_TX 0xE1
olympux 0:707771bf6708 111 #define FLUSH_RX 0xE2
olympux 0:707771bf6708 112 #define REUSE_TX_PL 0xE3
olympux 0:707771bf6708 113 #define NOP 0xFF
olympux 0:707771bf6708 114
olympux 0:707771bf6708 115 /* Non-P omissions */
olympux 0:707771bf6708 116 #define LNA_HCURR 0
olympux 0:707771bf6708 117
olympux 0:707771bf6708 118 /* P model memory Map */
olympux 0:707771bf6708 119 #define RPD 0x09
olympux 0:707771bf6708 120
olympux 0:707771bf6708 121 /* P model bit Mnemonics */
olympux 0:707771bf6708 122 #define RF_DR_LOW 5
olympux 0:707771bf6708 123 #define RF_DR_HIGH 3
olympux 0:707771bf6708 124 #define RF_PWR_LOW 1
olympux 0:707771bf6708 125 #define RF_PWR_HIGH 2
olympux 0:707771bf6708 126
olympux 0:707771bf6708 127 #define HIGH 1
olympux 0:707771bf6708 128 #define LOW 0