MAX3100/3110E info SPI 0,0 device e.g. clock idles low, data clocked in on leading edge out on trailing edge transfers are 16 bit transmit bits 15,14

• 1,1 Write Configuration
• 0,1 Read Configuration
• 1,0 Write (and read) data
• 0,0 Read data

Receive bits 15,14 R (Data available), T (Transmit buffer empty)

Caution: due to the "write behind" property of SPI the T bit value returned immediately after a write operation will still be set (as it was immediately before the write), and will need masking to prevent another byte being sent on the next pass. This is not a silicon bug, the device returns what its status was immediately before the write operation so the status returned is always one cycle behind

short transfers might be supported for status polling since datasheet indicates that a transfer may be aborted by CS rise with no effects. This means it is possible to execute a quick 2-bit transfer to read the R and T bits.

Another option might be to transfer the first two bits, decide mid-transfer whether transmit is possible or not, then transmit the remaining 14 bits

A third undocumented possibility is to attempt to write regardless of state then test T after to determine if write succeeded. This assumes that a write while T=0 will simply be discarded.

Control bits 13-4

• 13 !FEN 1=disable Rx FIFO
• 12 SHDN 1=soft shutdown
• 11 !TM 1=TX buffer interrupt enable
• 10 !RM 1=RX Data available interrupt enable
• 9 !PM 1=Parity high interrupt enable
• 8 !RAM 1=Rx activity or Frame error enable
• 7 IR 1=Enable IrDA mode
• 6 ST 1=TX Two stop bits
• 5 PE 1=Enable parity
• 4 L 1=7 Bit mode

Control bits 3-0 are baud rate divisor

• Bit 3 1=Divide by 3
• Bits 2-0 Divide by 2^value With 3.6864MHz use 1011 for 9600 baud

Tx/Rx registers

• Bits 13-11 Zero
• Bit 10 Din 1=No transmit just update handshake
• Bit 10 Dout 1=Framing error (or indicates any receiver activity while in shutdown state)
• Bit 9 Handshake: Din sets RTS state CTS state returned by Dout
• Bit 8 Parity bit (microcontroller responsible for calculating and checking parity)
• Bits 7-0 Data

Note about RTS/CTS polarity: the RTS and CTS pins are inverted TTL, so that when buffered by an inverting RS232 buffer the interface pin state matches the regiter bit e.g. 1=+ve, 0=-ve.

If RTS is used to control direction in a RS485 application this inversion will need to be taken into account e.g. typically 0=transmit, 1=read