Suga koubou / Mbed 2 deprecated Drone_air

DJI NAZA-M controller (multi copter side) see: https://developer.mbed.org/users/okini3939/notebook/drone/

Dependencies:   FutabaSBUS NECnfc mbed

PowerControl/EthernetPowerControl.cpp@1:32cd1cf5d5b1, 2016-05-19 (annotated)

Committer:
okini3939
Date:
Thu May 19 08:59:45 2016 +0000
Revision:
1:32cd1cf5d5b1
Parent:
0:4a37291f07ca 
1st build;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
okini3939 0:4a37291f07ca 1 #include "EthernetPowerControl.h"
okini3939 0:4a37291f07ca 2
okini3939 0:4a37291f07ca 3 static void write_PHY (unsigned int PhyReg, unsigned short Value) {
okini3939 0:4a37291f07ca 4 /* Write a data 'Value' to PHY register 'PhyReg'. */
okini3939 0:4a37291f07ca 5 unsigned int tout;
okini3939 0:4a37291f07ca 6 /* Hardware MII Management for LPC176x devices. */
okini3939 0:4a37291f07ca 7 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
okini3939 0:4a37291f07ca 8 LPC_EMAC->MWTD = Value;
okini3939 0:4a37291f07ca 9
okini3939 0:4a37291f07ca 10 /* Wait utill operation completed */
okini3939 0:4a37291f07ca 11 for (tout = 0; tout < MII_WR_TOUT; tout++) {
okini3939 0:4a37291f07ca 12 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
okini3939 0:4a37291f07ca 13 break;
okini3939 0:4a37291f07ca 14 }
okini3939 0:4a37291f07ca 15 }
okini3939 0:4a37291f07ca 16 }
okini3939 0:4a37291f07ca 17
okini3939 0:4a37291f07ca 18 static unsigned short read_PHY (unsigned int PhyReg) {
okini3939 0:4a37291f07ca 19 /* Read a PHY register 'PhyReg'. */
okini3939 0:4a37291f07ca 20 unsigned int tout, val;
okini3939 0:4a37291f07ca 21
okini3939 0:4a37291f07ca 22 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
okini3939 0:4a37291f07ca 23 LPC_EMAC->MCMD = MCMD_READ;
okini3939 0:4a37291f07ca 24
okini3939 0:4a37291f07ca 25 /* Wait until operation completed */
okini3939 0:4a37291f07ca 26 for (tout = 0; tout < MII_RD_TOUT; tout++) {
okini3939 0:4a37291f07ca 27 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
okini3939 0:4a37291f07ca 28 break;
okini3939 0:4a37291f07ca 29 }
okini3939 0:4a37291f07ca 30 }
okini3939 0:4a37291f07ca 31 LPC_EMAC->MCMD = 0;
okini3939 0:4a37291f07ca 32 val = LPC_EMAC->MRDD;
okini3939 0:4a37291f07ca 33
okini3939 0:4a37291f07ca 34 return (val);
okini3939 0:4a37291f07ca 35 }
okini3939 0:4a37291f07ca 36
okini3939 0:4a37291f07ca 37 void EMAC_Init()
okini3939 0:4a37291f07ca 38 {
okini3939 0:4a37291f07ca 39 unsigned int tout,regv;
okini3939 0:4a37291f07ca 40 /* Power Up the EMAC controller. */
okini3939 0:4a37291f07ca 41 Peripheral_PowerUp(LPC1768_PCONP_PCENET);
okini3939 0:4a37291f07ca 42
okini3939 0:4a37291f07ca 43 LPC_PINCON->PINSEL2 = 0x50150105;
okini3939 0:4a37291f07ca 44 LPC_PINCON->PINSEL3 &= ~0x0000000F;
okini3939 0:4a37291f07ca 45 LPC_PINCON->PINSEL3 |= 0x00000005;
okini3939 0:4a37291f07ca 46
okini3939 0:4a37291f07ca 47 /* Reset all EMAC internal modules. */
okini3939 0:4a37291f07ca 48 LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
okini3939 0:4a37291f07ca 49 MAC1_SIM_RES | MAC1_SOFT_RES;
okini3939 0:4a37291f07ca 50 LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
okini3939 0:4a37291f07ca 51
okini3939 0:4a37291f07ca 52 /* A short delay after reset. */
okini3939 0:4a37291f07ca 53 for (tout = 100; tout; tout--);
okini3939 0:4a37291f07ca 54
okini3939 0:4a37291f07ca 55 /* Initialize MAC control registers. */
okini3939 0:4a37291f07ca 56 LPC_EMAC->MAC1 = MAC1_PASS_ALL;
okini3939 0:4a37291f07ca 57 LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
okini3939 0:4a37291f07ca 58 LPC_EMAC->MAXF = ETH_MAX_FLEN;
okini3939 0:4a37291f07ca 59 LPC_EMAC->CLRT = CLRT_DEF;
okini3939 0:4a37291f07ca 60 LPC_EMAC->IPGR = IPGR_DEF;
okini3939 0:4a37291f07ca 61
okini3939 0:4a37291f07ca 62 /* Enable Reduced MII interface. */
okini3939 0:4a37291f07ca 63 LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
okini3939 0:4a37291f07ca 64
okini3939 0:4a37291f07ca 65 /* Reset Reduced MII Logic. */
okini3939 0:4a37291f07ca 66 LPC_EMAC->SUPP = SUPP_RES_RMII;
okini3939 0:4a37291f07ca 67 for (tout = 100; tout; tout--);
okini3939 0:4a37291f07ca 68 LPC_EMAC->SUPP = 0;
okini3939 0:4a37291f07ca 69
okini3939 0:4a37291f07ca 70 /* Put the DP83848C in reset mode */
okini3939 0:4a37291f07ca 71 write_PHY (PHY_REG_BMCR, 0x8000);
okini3939 0:4a37291f07ca 72
okini3939 0:4a37291f07ca 73 /* Wait for hardware reset to end. */
okini3939 0:4a37291f07ca 74 for (tout = 0; tout < 0x100000; tout++) {
okini3939 0:4a37291f07ca 75 regv = read_PHY (PHY_REG_BMCR);
okini3939 0:4a37291f07ca 76 if (!(regv & 0x8000)) {
okini3939 0:4a37291f07ca 77 /* Reset complete */
okini3939 0:4a37291f07ca 78 break;
okini3939 0:4a37291f07ca 79 }
okini3939 0:4a37291f07ca 80 }
okini3939 0:4a37291f07ca 81 }
okini3939 0:4a37291f07ca 82
okini3939 0:4a37291f07ca 83
okini3939 0:4a37291f07ca 84 void PHY_PowerDown()
okini3939 0:4a37291f07ca 85 {
okini3939 0:4a37291f07ca 86 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
okini3939 0:4a37291f07ca 87 EMAC_Init(); //init EMAC if it is not already init'd
okini3939 0:4a37291f07ca 88
okini3939 0:4a37291f07ca 89 unsigned int regv;
okini3939 0:4a37291f07ca 90 regv = read_PHY(PHY_REG_BMCR);
okini3939 0:4a37291f07ca 91 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_BMCR_POWERDOWN));
okini3939 0:4a37291f07ca 92 regv = read_PHY(PHY_REG_BMCR);
okini3939 0:4a37291f07ca 93
okini3939 0:4a37291f07ca 94 //shouldn't need the EMAC now.
okini3939 0:4a37291f07ca 95 Peripheral_PowerDown(LPC1768_PCONP_PCENET);
okini3939 0:4a37291f07ca 96
okini3939 0:4a37291f07ca 97 //and turn off the PHY OSC
okini3939 0:4a37291f07ca 98 LPC_GPIO1->FIODIR |= 0x8000000;
okini3939 0:4a37291f07ca 99 LPC_GPIO1->FIOCLR = 0x8000000;
okini3939 0:4a37291f07ca 100 }
okini3939 0:4a37291f07ca 101
okini3939 0:4a37291f07ca 102 void PHY_PowerUp()
okini3939 0:4a37291f07ca 103 {
okini3939 0:4a37291f07ca 104 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
okini3939 0:4a37291f07ca 105 EMAC_Init(); //init EMAC if it is not already init'd
okini3939 0:4a37291f07ca 106
okini3939 0:4a37291f07ca 107 LPC_GPIO1->FIODIR |= 0x8000000;
okini3939 0:4a37291f07ca 108 LPC_GPIO1->FIOSET = 0x8000000;
okini3939 0:4a37291f07ca 109
okini3939 0:4a37291f07ca 110 //wait for osc to be stable
okini3939 0:4a37291f07ca 111 wait_ms(200);
okini3939 0:4a37291f07ca 112
okini3939 0:4a37291f07ca 113 unsigned int regv;
okini3939 0:4a37291f07ca 114 regv = read_PHY(PHY_REG_BMCR);
okini3939 0:4a37291f07ca 115 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_BMCR_POWERDOWN));
okini3939 0:4a37291f07ca 116 regv = read_PHY(PHY_REG_BMCR);
okini3939 0:4a37291f07ca 117 }
okini3939 0:4a37291f07ca 118
okini3939 0:4a37291f07ca 119 void PHY_EnergyDetect_Enable()
okini3939 0:4a37291f07ca 120 {
okini3939 0:4a37291f07ca 121 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
okini3939 0:4a37291f07ca 122 EMAC_Init(); //init EMAC if it is not already init'd
okini3939 0:4a37291f07ca 123
okini3939 0:4a37291f07ca 124 unsigned int regv;
okini3939 0:4a37291f07ca 125 regv = read_PHY(PHY_REG_EDCR);
okini3939 0:4a37291f07ca 126 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_EDCR_ENABLE));
okini3939 0:4a37291f07ca 127 regv = read_PHY(PHY_REG_EDCR);
okini3939 0:4a37291f07ca 128 }
okini3939 0:4a37291f07ca 129
okini3939 0:4a37291f07ca 130 void PHY_EnergyDetect_Disable()
okini3939 0:4a37291f07ca 131 {
okini3939 0:4a37291f07ca 132 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
okini3939 0:4a37291f07ca 133 EMAC_Init(); //init EMAC if it is not already init'd
okini3939 0:4a37291f07ca 134 unsigned int regv;
okini3939 0:4a37291f07ca 135 regv = read_PHY(PHY_REG_EDCR);
okini3939 0:4a37291f07ca 136 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_EDCR_ENABLE));
okini3939 0:4a37291f07ca 137 regv = read_PHY(PHY_REG_EDCR);
okini3939 0:4a37291f07ca 138 }