Soheil Novinfard / Mbed OS Watchdog_ADC

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Fork of ADCandticker_sample by William Marsh

KL25Z_SystemInit.c@3:c6c88a1a58a8, 2018-03-09 (annotated)

Committer:
novinfard
Date:
Fri Mar 09 15:19:12 2018 +0000
Revision:
3:c6c88a1a58a8
Finalising Project

Who changed what in which revision?

UserRevisionLine numberNew contents of line
novinfard 3:c6c88a1a58a8 1 /*
novinfard 3:c6c88a1a58a8 2 ** ###################################################################
novinfard 3:c6c88a1a58a8 3 ** Processor: MKL25Z128VLK4
novinfard 3:c6c88a1a58a8 4 ** Compilers: ARM Compiler
novinfard 3:c6c88a1a58a8 5 ** Freescale C/C++ for Embedded ARM
novinfard 3:c6c88a1a58a8 6 ** GNU C Compiler
novinfard 3:c6c88a1a58a8 7 ** IAR ANSI C/C++ Compiler for ARM
novinfard 3:c6c88a1a58a8 8 **
novinfard 3:c6c88a1a58a8 9 ** Reference manual: KL25RM, Rev.1, Jun 2012
novinfard 3:c6c88a1a58a8 10 ** Version: rev. 1.1, 2012-06-21
novinfard 3:c6c88a1a58a8 11 **
novinfard 3:c6c88a1a58a8 12 ** Abstract:
novinfard 3:c6c88a1a58a8 13 ** Provides a system configuration function and a global variable that
novinfard 3:c6c88a1a58a8 14 ** contains the system frequency. It configures the device and initializes
novinfard 3:c6c88a1a58a8 15 ** the oscillator (PLL) that is part of the microcontroller device.
novinfard 3:c6c88a1a58a8 16 **
novinfard 3:c6c88a1a58a8 17 ** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
novinfard 3:c6c88a1a58a8 18 **
novinfard 3:c6c88a1a58a8 19 ** http: www.freescale.com
novinfard 3:c6c88a1a58a8 20 ** mail: support@freescale.com
novinfard 3:c6c88a1a58a8 21 **
novinfard 3:c6c88a1a58a8 22 ** Revisions:
novinfard 3:c6c88a1a58a8 23 ** - rev. 1.0 (2012-06-13)
novinfard 3:c6c88a1a58a8 24 ** Initial version.
novinfard 3:c6c88a1a58a8 25 ** - rev. 1.1 (2012-06-21)
novinfard 3:c6c88a1a58a8 26 ** Update according to reference manual rev. 1.
novinfard 3:c6c88a1a58a8 27 **
novinfard 3:c6c88a1a58a8 28 ** ###################################################################
novinfard 3:c6c88a1a58a8 29 */
novinfard 3:c6c88a1a58a8 30
novinfard 3:c6c88a1a58a8 31 /**
novinfard 3:c6c88a1a58a8 32 * @file MKL25Z4
novinfard 3:c6c88a1a58a8 33 * @version 1.1
novinfard 3:c6c88a1a58a8 34 * @date 2012-06-21
novinfard 3:c6c88a1a58a8 35 * @brief Device specific configuration file for MKL25Z4 (implementation file)
novinfard 3:c6c88a1a58a8 36 *
novinfard 3:c6c88a1a58a8 37 * Provides a system configuration function and a global variable that contains
novinfard 3:c6c88a1a58a8 38 * the system frequency. It configures the device and initializes the oscillator
novinfard 3:c6c88a1a58a8 39 * (PLL) that is part of the microcontroller device.
novinfard 3:c6c88a1a58a8 40 */
novinfard 3:c6c88a1a58a8 41
novinfard 3:c6c88a1a58a8 42 #include <stdint.h>
novinfard 3:c6c88a1a58a8 43 #include "MKL25Z4.h"
novinfard 3:c6c88a1a58a8 44
novinfard 3:c6c88a1a58a8 45 //MODIFICATION: We DO want watchdog, uC default after reset is enabled with timeout=1024ms (2^10*LPO=1KHz)
novinfard 3:c6c88a1a58a8 46 //#define DISABLE_WDOG 1
novinfard 3:c6c88a1a58a8 47
novinfard 3:c6c88a1a58a8 48 #define CLOCK_SETUP 1
novinfard 3:c6c88a1a58a8 49 /* Predefined clock setups
novinfard 3:c6c88a1a58a8 50 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
novinfard 3:c6c88a1a58a8 51 Reference clock source for MCG module is the slow internal clock source 32.768kHz
novinfard 3:c6c88a1a58a8 52 Core clock = 41.94MHz, BusClock = 13.98MHz
novinfard 3:c6c88a1a58a8 53 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
novinfard 3:c6c88a1a58a8 54 Reference clock source for MCG module is an external crystal 8MHz
novinfard 3:c6c88a1a58a8 55 Core clock = 48MHz, BusClock = 24MHz
novinfard 3:c6c88a1a58a8 56 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
novinfard 3:c6c88a1a58a8 57 Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
novinfard 3:c6c88a1a58a8 58 Core clock = 8MHz, BusClock = 8MHz
novinfard 3:c6c88a1a58a8 59 3 ... Multipurpose Clock Generator (MCG) in FLL Engaged External (FEE) mode
novinfard 3:c6c88a1a58a8 60 Reference clock source for MCG module is an external crystal 32.768kHz
novinfard 3:c6c88a1a58a8 61 Core clock = 47.97MHz, BusClock = 23.98MHz
novinfard 3:c6c88a1a58a8 62 This setup sets the RTC to be driven by the MCU clock directly without the need of an external source.
novinfard 3:c6c88a1a58a8 63 RTC register values are retained when MCU is reset although there will be a slight (mSec's)loss of time
novinfard 3:c6c88a1a58a8 64 accuracy durring the reset period. RTC will reset on power down.
novinfard 3:c6c88a1a58a8 65 */
novinfard 3:c6c88a1a58a8 66
novinfard 3:c6c88a1a58a8 67 /*----------------------------------------------------------------------------
novinfard 3:c6c88a1a58a8 68 Define clock source values
novinfard 3:c6c88a1a58a8 69 *----------------------------------------------------------------------------*/
novinfard 3:c6c88a1a58a8 70 #if (CLOCK_SETUP == 0)
novinfard 3:c6c88a1a58a8 71 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
novinfard 3:c6c88a1a58a8 72 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
novinfard 3:c6c88a1a58a8 73 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
novinfard 3:c6c88a1a58a8 74 #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
novinfard 3:c6c88a1a58a8 75 #elif (CLOCK_SETUP == 1)
novinfard 3:c6c88a1a58a8 76 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
novinfard 3:c6c88a1a58a8 77 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
novinfard 3:c6c88a1a58a8 78 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
novinfard 3:c6c88a1a58a8 79 #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
novinfard 3:c6c88a1a58a8 80 #elif (CLOCK_SETUP == 2)
novinfard 3:c6c88a1a58a8 81 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
novinfard 3:c6c88a1a58a8 82 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
novinfard 3:c6c88a1a58a8 83 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
novinfard 3:c6c88a1a58a8 84 #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
novinfard 3:c6c88a1a58a8 85 #elif (CLOCK_SETUP == 3)
novinfard 3:c6c88a1a58a8 86 #define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
novinfard 3:c6c88a1a58a8 87 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
novinfard 3:c6c88a1a58a8 88 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
novinfard 3:c6c88a1a58a8 89 #define DEFAULT_SYSTEM_CLOCK 47972352u /* Default System clock value */
novinfard 3:c6c88a1a58a8 90 #endif /* (CLOCK_SETUP == 3) */
novinfard 3:c6c88a1a58a8 91
novinfard 3:c6c88a1a58a8 92 /* ----------------------------------------------------------------------------
novinfard 3:c6c88a1a58a8 93 -- Core clock
novinfard 3:c6c88a1a58a8 94 ---------------------------------------------------------------------------- */
novinfard 3:c6c88a1a58a8 95
novinfard 3:c6c88a1a58a8 96 //MODIFICATION: That vartiable already exists
novinfard 3:c6c88a1a58a8 97 // uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
novinfard 3:c6c88a1a58a8 98
novinfard 3:c6c88a1a58a8 99 /* ----------------------------------------------------------------------------
novinfard 3:c6c88a1a58a8 100 -- SystemInit()
novinfard 3:c6c88a1a58a8 101 ---------------------------------------------------------------------------- */
novinfard 3:c6c88a1a58a8 102
novinfard 3:c6c88a1a58a8 103 void $Sub$$SystemInit (void) {
novinfard 3:c6c88a1a58a8 104
novinfard 3:c6c88a1a58a8 105 //MODIFICATION:
novinfard 3:c6c88a1a58a8 106 // That variable already exists, we set it here
novinfard 3:c6c88a1a58a8 107 SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
novinfard 3:c6c88a1a58a8 108 // We want visual indication of boot time with red LED on
novinfard 3:c6c88a1a58a8 109 //TODO
novinfard 3:c6c88a1a58a8 110
novinfard 3:c6c88a1a58a8 111 #if (DISABLE_WDOG)
novinfard 3:c6c88a1a58a8 112 /* Disable the WDOG module */
novinfard 3:c6c88a1a58a8 113 /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
novinfard 3:c6c88a1a58a8 114 SIM->COPC = (uint32_t)0x00u;
novinfard 3:c6c88a1a58a8 115 #endif /* (DISABLE_WDOG) */
novinfard 3:c6c88a1a58a8 116 #if (CLOCK_SETUP == 0)
novinfard 3:c6c88a1a58a8 117 /* SIM->CLKDIV1: OUTDIV1=0 */
novinfard 3:c6c88a1a58a8 118 SIM->CLKDIV1 = (uint32_t)0x00020000UL; /* Update system prescalers */
novinfard 3:c6c88a1a58a8 119 /* Switch to FEI Mode */
novinfard 3:c6c88a1a58a8 120 /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
novinfard 3:c6c88a1a58a8 121 MCG->C1 = (uint8_t)0x06U;
novinfard 3:c6c88a1a58a8 122 /* MCG_C2: LOCRE0=0, =0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
novinfard 3:c6c88a1a58a8 123 MCG->C2 = (uint8_t)0x00U;
novinfard 3:c6c88a1a58a8 124 /* MCG->C4: DMX32=0,DRST_DRS=1 */
novinfard 3:c6c88a1a58a8 125 MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
novinfard 3:c6c88a1a58a8 126 /* OSC0->CR: ERCLKEN=1,=0,EREFSTEN=0,=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
novinfard 3:c6c88a1a58a8 127 OSC0->CR = (uint8_t)0x80U;
novinfard 3:c6c88a1a58a8 128 /* MCG->C5: =0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
novinfard 3:c6c88a1a58a8 129 MCG->C5 = (uint8_t)0x00U;
novinfard 3:c6c88a1a58a8 130 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
novinfard 3:c6c88a1a58a8 131 MCG->C6 = (uint8_t)0x00U;
novinfard 3:c6c88a1a58a8 132 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
novinfard 3:c6c88a1a58a8 133 }
novinfard 3:c6c88a1a58a8 134 while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
novinfard 3:c6c88a1a58a8 135 }
novinfard 3:c6c88a1a58a8 136 #elif (CLOCK_SETUP == 1)
novinfard 3:c6c88a1a58a8 137 /* SIM->SCGC5: PORTA=1 */
novinfard 3:c6c88a1a58a8 138 SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
novinfard 3:c6c88a1a58a8 139 /* SIM->CLKDIV1: OUTDIV1=1,OUTDIV4=1 */
novinfard 3:c6c88a1a58a8 140 SIM->CLKDIV1 = (uint32_t)0x10010000UL; /* Update system prescalers */
novinfard 3:c6c88a1a58a8 141 /* PORTA->PCR18: ISF=0,MUX=0 */
novinfard 3:c6c88a1a58a8 142 PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
novinfard 3:c6c88a1a58a8 143 /* PORTA->PCR19: ISF=0,MUX=0 */
novinfard 3:c6c88a1a58a8 144 PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
novinfard 3:c6c88a1a58a8 145 /* Switch to FBE Mode */
novinfard 3:c6c88a1a58a8 146 /* OSC0->CR: ERCLKEN=1,EREFSTEN=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
novinfard 3:c6c88a1a58a8 147 OSC0->CR = (uint8_t)0x89U;
novinfard 3:c6c88a1a58a8 148 /* MCG->C2: LOCRE0=0, RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
novinfard 3:c6c88a1a58a8 149 MCG->C2 = (uint8_t)0x24U;
novinfard 3:c6c88a1a58a8 150 /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
novinfard 3:c6c88a1a58a8 151 MCG->C1 = (uint8_t)0x9AU;
novinfard 3:c6c88a1a58a8 152 /* MCG->C4: DMX32=0,DRST_DRS=0 */
novinfard 3:c6c88a1a58a8 153 MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
novinfard 3:c6c88a1a58a8 154 /* MCG->C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
novinfard 3:c6c88a1a58a8 155 MCG->C5 = (uint8_t)0x01U;
novinfard 3:c6c88a1a58a8 156 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
novinfard 3:c6c88a1a58a8 157 MCG->C6 = (uint8_t)0x00U;
novinfard 3:c6c88a1a58a8 158 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
novinfard 3:c6c88a1a58a8 159 }
novinfard 3:c6c88a1a58a8 160 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
novinfard 3:c6c88a1a58a8 161 }
novinfard 3:c6c88a1a58a8 162 /* Switch to PBE Mode */
novinfard 3:c6c88a1a58a8 163 /* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
novinfard 3:c6c88a1a58a8 164 MCG->C6 = (uint8_t)0x40U;
novinfard 3:c6c88a1a58a8 165 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
novinfard 3:c6c88a1a58a8 166 }
novinfard 3:c6c88a1a58a8 167 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
novinfard 3:c6c88a1a58a8 168 }
novinfard 3:c6c88a1a58a8 169 /* Switch to PEE Mode */
novinfard 3:c6c88a1a58a8 170 /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
novinfard 3:c6c88a1a58a8 171 MCG->C1 = (uint8_t)0x1AU;
novinfard 3:c6c88a1a58a8 172 while((MCG->S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
novinfard 3:c6c88a1a58a8 173 }
novinfard 3:c6c88a1a58a8 174 #elif (CLOCK_SETUP == 2)
novinfard 3:c6c88a1a58a8 175 /* SIM->SCGC5: PORTA=1 */
novinfard 3:c6c88a1a58a8 176 SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
novinfard 3:c6c88a1a58a8 177 /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV4=0 */
novinfard 3:c6c88a1a58a8 178 SIM->CLKDIV1 = (uint32_t)0x00000000UL; /* Update system prescalers */
novinfard 3:c6c88a1a58a8 179 /* PORTA->PCR18: ISF=0,MUX=0 */
novinfard 3:c6c88a1a58a8 180 PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
novinfard 3:c6c88a1a58a8 181 /* PORTA->PCR19: ISF=0,MUX=0 */
novinfard 3:c6c88a1a58a8 182 PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
novinfard 3:c6c88a1a58a8 183 /* Switch to FBE Mode */
novinfard 3:c6c88a1a58a8 184 /* OSC0->CR: ERCLKEN=1,EREFSTEN=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
novinfard 3:c6c88a1a58a8 185 OSC0->CR = (uint8_t)0x89U;
novinfard 3:c6c88a1a58a8 186 /* MCG->C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
novinfard 3:c6c88a1a58a8 187 MCG->C2 = (uint8_t)0x24U;
novinfard 3:c6c88a1a58a8 188 /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
novinfard 3:c6c88a1a58a8 189 MCG->C1 = (uint8_t)0x9AU;
novinfard 3:c6c88a1a58a8 190 /* MCG->C4: DMX32=0,DRST_DRS=0 */
novinfard 3:c6c88a1a58a8 191 MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
novinfard 3:c6c88a1a58a8 192 /* MCG->C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
novinfard 3:c6c88a1a58a8 193 MCG->C5 = (uint8_t)0x00U;
novinfard 3:c6c88a1a58a8 194 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
novinfard 3:c6c88a1a58a8 195 MCG->C6 = (uint8_t)0x00U;
novinfard 3:c6c88a1a58a8 196 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
novinfard 3:c6c88a1a58a8 197 }
novinfard 3:c6c88a1a58a8 198 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
novinfard 3:c6c88a1a58a8 199 }
novinfard 3:c6c88a1a58a8 200 /* Switch to BLPE Mode */
novinfard 3:c6c88a1a58a8 201 /* MCG->C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=0 */
novinfard 3:c6c88a1a58a8 202 MCG->C2 = (uint8_t)0x26U;
novinfard 3:c6c88a1a58a8 203 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
novinfard 3:c6c88a1a58a8 204 }
novinfard 3:c6c88a1a58a8 205 #elif (CLOCK_SETUP == 3)
novinfard 3:c6c88a1a58a8 206 /* SIM->SCGC5: PORTA=1 */
novinfard 3:c6c88a1a58a8 207 SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */
novinfard 3:c6c88a1a58a8 208 /* SIM->CLKDIV1: OUTDIV1=0, OUTDIV4=1 */
novinfard 3:c6c88a1a58a8 209 SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */
novinfard 3:c6c88a1a58a8 210 /* PORTA->PCR[3]: ISF=0,MUX=0 */
novinfard 3:c6c88a1a58a8 211 PORTA->PCR[3] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
novinfard 3:c6c88a1a58a8 212 /* PORTA->PCR[4]: ISF=0,MUX=0 */
novinfard 3:c6c88a1a58a8 213 PORTA->PCR[4] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
novinfard 3:c6c88a1a58a8 214 /* Switch to FEE Mode */
novinfard 3:c6c88a1a58a8 215 /* MCG->C2: LOCRE0=0,RANGE0=0,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
novinfard 3:c6c88a1a58a8 216 MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_EREFS0_MASK);
novinfard 3:c6c88a1a58a8 217 /* OSC0->CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
novinfard 3:c6c88a1a58a8 218 OSC0->CR = OSC_CR_ERCLKEN_MASK | OSC_CR_SC16P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC2P_MASK;
novinfard 3:c6c88a1a58a8 219 /* MCG->C1: CLKS=0,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
novinfard 3:c6c88a1a58a8 220 MCG->C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x00) | MCG_C1_IRCLKEN_MASK);
novinfard 3:c6c88a1a58a8 221 /* MCG->C4: DMX32=1,DRST_DRS=1 */
novinfard 3:c6c88a1a58a8 222 MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)(
novinfard 3:c6c88a1a58a8 223 MCG_C4_DRST_DRS(0x02)
novinfard 3:c6c88a1a58a8 224 )) | (uint8_t)(
novinfard 3:c6c88a1a58a8 225 MCG_C4_DMX32_MASK |
novinfard 3:c6c88a1a58a8 226 MCG_C4_DRST_DRS(0x01)
novinfard 3:c6c88a1a58a8 227 ));
novinfard 3:c6c88a1a58a8 228 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
novinfard 3:c6c88a1a58a8 229 }
novinfard 3:c6c88a1a58a8 230 while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
novinfard 3:c6c88a1a58a8 231 }
novinfard 3:c6c88a1a58a8 232 #endif /* (CLOCK_SETUP == 3) */
novinfard 3:c6c88a1a58a8 233 }