LAN9252.h

00001 /* 
00002  * File:   LAN9252.h
00003  * Author: kitagami
00004  *
00005  * Created on January 29, 2020, 9:11 PM
00006  */
00007 
00008 #ifndef LAN9252_H
00009 #define LAN9252_H
00010 
00011 #include <SPI.h>
00012 #include <stdint.h>
00013 
00014 #define ECAT_PRAM_RD_DATA       0x000
00015 #define ECAT_PRAM_WR_DATA       0x020
00016 #define ID_REV                  0x050
00017 #define IRQ_CFG                 0x054
00018 #define INT_STS                 0x058
00019 #define INT_EN                  0x05C
00020 #define BYTE_TEST               0x064
00021 #define HW_CFG                  0x074
00022 #define PMT_CTRL                0x084
00023 #define GPT_CFG                 0x08C
00024 #define GPT_CNT                 0x090
00025 #define FREE_RUN                0x09C
00026 #define RESET_CTL               0x1F8
00027 
00028 #define ETHERCAT_RST            0x40
00029 #define PHY_B_RST               0x04
00030 #define PHY_A_RST               0x02
00031 #define DIGITAL_RST             0x01
00032 
00033 #define ECAT_CSR_DATA           0x300
00034 #define ECAT_CSR_CMD            0x304
00035 #define CSR_BUSY                1<<31
00036 #define CSR_SIZE_8bit           1
00037 #define CSR_SIZE_16bit          2
00038 #define CSR_SIZE_32bit          4
00039 #define ECAT_PRAM_RD_ADDR_LEN   0x308
00040 #define ECAT_PRAM_RD_CMD        0x30C
00041 #define ECAT_PRAM_WR_ADDR_LEN   0x310
00042 #define ECAT_PRAM_WR_CMD        0x314
00043 
00044 #define PRAM_READ_BUSY  1<<31
00045 #define PRAM_READ_ABORT 1<<30
00046 #define PRAM_WRITE_BUSY  1<<31
00047 #define PRAM_WRITE_ABORT 1<<30
00048     
00049 //-----------------------------------------------------------------------//
00050 // ESC Information
00051 //-----------------------------------------------------------------------//
00052 #define Type_Register                            0x0000
00053 #define Revision_Register                        0x0001
00054 #define Build_Register                           0x0002
00055 #define FMMUs_Supported                          0x0004
00056 #define SyncManagers_Supported                   0x0005
00057 #define RAM_Size                                 0x0006
00058 #define Port_Descriptor                          0x0007
00059 #define ESC_Features_Supported                   0x0008
00060 //-----------------------------------------------------------------------//
00061 // Station Address
00062 //-----------------------------------------------------------------------//
00063 #define Configured_Station                       0x0010
00064 #define Configured_Station_Alias                 0x0012
00065 //-----------------------------------------------------------------------//
00066 // Write Protection
00067 //-----------------------------------------------------------------------//
00068 #define Write_Enable                             0x0020
00069 #define Write_Protection                         0x0021
00070 #define ESC_Write_Enable                         0x0030
00071 #define ESC_Write_Protection                     0x0031
00072 //-----------------------------------------------------------------------//
00073 // Data Link Layer
00074 //-----------------------------------------------------------------------//
00075 #define ESC_Reset_ECAT                           0x0040
00076 #define ESC_Reset_PDI                            0x0041
00077 #define ESC_DL_Control                           0x0100
00078 #define Physical_Read_Write_Offset               0x0108
00079 #define ESC_DL_Status                            0x0110
00080 //-----------------------------------------------------------------------//
00081 // Application Layer
00082 //-----------------------------------------------------------------------//
00083 #define AL_Control                               0x0120
00084 #define AL_Status                                0x0130
00085 #define AL_Status_Code                           0x0134
00086 #define RUN_LED_Override                         0x0138
00087 //-----------------------------------------------------------------------//
00088 // PDI (Process Data Interface)
00089 //-----------------------------------------------------------------------//
00090 #define PDI_Control                              0x0140
00091 #define ESC_Configuration                        0x0141
00092 #define ASIC_Configuration                       0x0142
00093 #define PDI_Configuration                        0x0150
00094 #define Sync_Latch_PDI_Configuration             0x0151
00095 #define Extended_PDI_Configuration               0x0152
00096 //-----------------------------------------------------------------------//
00097 //Interrupts
00098 //-----------------------------------------------------------------------//
00099 #define ECAT_Event_Mask                          0x0200
00100 #define AL_Event_Mask                            0x0204
00101 #define ECAT_Event_Request                       0x0210
00102 #define AL_Event_Request                         0x0220
00103 //-----------------------------------------------------------------------//
00104 // Error Counters
00105 //-----------------------------------------------------------------------//
00106 #define RX_Error_Counters                        0x0300
00107 #define Forwarded_RX_Error_Counters              0x0308
00108 #define ECAT_Processing_Unit_Error_Counter       0x030C
00109 #define PDI_Error_Counter                        0x030D
00110 #define PDI_Error_Code                           0x030E
00111 #define Lost_Link_Counters                       0x0310
00112 //-----------------------------------------------------------------------//
00113 // Watchdogs
00114 //-----------------------------------------------------------------------//
00115 #define Watchdog_Time_PDI                        0x0410
00116 #define Watchdog_Time_Process_Data               0x0420
00117 #define Watchdog_Status_Process_Data             0x0440
00118 #define Watchdog_Counter_Process_Data            0x0442
00119 #define Watchdog_Counter_PDI                     0x0443
00120 //-----------------------------------------------------------------------//
00121 // EEPROM Interface
00122 //-----------------------------------------------------------------------//
00123 #define EEPROM_Configuration                     0x0500
00124 #define EEPROM_PDI_Access_State                  0x0501
00125 #define EEPROM_Control_Status                    0x0502
00126 #define EEPROM_Address                           0x0504
00127 #define EEPROM_Data                              0x0508
00128 //-----------------------------------------------------------------------//
00129 // MII Management Interface
00130 //-----------------------------------------------------------------------//
00131 #define MII_Management_Control_Status            0x0510
00132 #define PHY_Address                              0x0512
00133 #define PHY_Register_Address                     0x0513
00134 #define PHY_DATA                                 0x0514
00135 #define MII_Management_ECAT_Access_State         0x0516
00136 #define MII_Management_PDI_Access_State          0x0517
00137 #define PHY_Port_Statuss                         0x0518
00138 /*=========================================================
00139 0600h FMMU[2:0]s (3x16 bytes)
00140 +0h-3h FMMUx Logical Start Address
00141 +4h-5h FMMUx Length
00142 +6h FMMUx Logical Start Bit
00143 +7h FMMUx Logical Stop Bit
00144 +8h-9h FMMUx Physical Start Address
00145 +Ah FMMUx Physical Start Bit
00146 +Bh FMMUx Type
00147 +Ch FMMUx Activate
00148 +Dh-Fh FMMUx Reserved
00149 0800h-081Fh SyncManager[3:0]s (4x8 bytes)
00150 +0h-1h SyncManager x Physical Start Address
00151 +2h-3h SyncManager x Length
00152 +4h SyncManager x Control
00153 +5h SyncManager x Status
00154 +6h SyncManager x Activate
00155 +7h SyncManager x PDI Control
00156 ===========================================================*/
00157 //-----------------------------------------------------------------------//
00158 // Distributed Clocks - Receive Times
00159 //-----------------------------------------------------------------------//
00160 #define Receive_Time_Port_0                       0x0900
00161 #define Receive_Time_Port_1                       0x0904
00162 #define Receive_Time_Port_2                       0x0908
00163 //-----------------------------------------------------------------------//
00164 //Distributed Clocks - Time Loop Control Unit
00165 //-----------------------------------------------------------------------//
00166 #define System_Time                               0x0910
00167 #define Receive_Time_ECAT_Processing_Unit         0x0918
00168 #define System_Time_Offset                        0x0920
00169 #define System_Time_Delay                         0x0928
00170 #define System_Time_Difference                    0x092C
00171 #define Speed_Counter_Start                       0x0930
00172 #define Speed_Counter_Diff                        0x0932
00173 #define System_Time_Difference_Filter_Depth       0x0934
00174 #define Speed_Counter_Filter_Depth                0x0935
00175 //-----------------------------------------------------------------------//
00176 // Distributed Clocks - Cyclic Unit Control
00177 //-----------------------------------------------------------------------//
00178 #define Cyclic Unit Control                       0x0980
00179 //-----------------------------------------------------------------------//
00180 // Distributed Clocks - SYNC Out Unit
00181 //-----------------------------------------------------------------------//
00182 #define Activation                                0x0981
00183 #define Pulse_Length_of_SyncSignals               0x0982
00184 #define Activation_Status                         0x0984
00185 #define SYNC0_Status                              0x098E
00186 #define SYNC1_Status                              0x098F
00187 #define Start_Time_Cyclic_Operation               0x0990
00188 #define Next_SYNC1_Pulse                          0x0998
00189 #define SYNC0_Cycle_Time                          0x09A0
00190 #define SYNC1_Cycle_Time                          0x09A4
00191 //-----------------------------------------------------------------------//
00192 // Distributed Clocks - Latch In Unit
00193 //-----------------------------------------------------------------------//
00194 #define LATCH0_Control                            0x09A8
00195 #define LATCH1_Control                            0x09A9
00196 #define LATCH0_Status                             0x09AE
00197 #define LATCH1_Status                             0x09AF
00198 #define LATCH0_Time_Positive_Edge                 0x09B0
00199 #define LATCH0_Time_Negative_Edge                 0x09B8
00200 #define LATCH1_Time_Positive_Edge                 0x09C0
00201 #define LATCH1_Time_Negative_Edge                 0x09C8
00202 //-----------------------------------------------------------------------//
00203 // Distributed Clocks - SyncManager Event Times
00204 //-----------------------------------------------------------------------//
00205 #define EtherCAT_Buffer_Change_Event_Time         0x09F0
00206 #define PDI_Buffer_Start_Time_Event               0x09F8
00207 #define PDI_Buffer_Change_Event_Time              0x09FC
00208 //-----------------------------------------------------------------------//
00209 // ESC Specific
00210 //-----------------------------------------------------------------------//
00211 #define Product_ID                                0x0E00
00212 #define Vendor_ID                                 0x0E08
00213 //-----------------------------------------------------------------------//
00214 // Digital Input/Output
00215 //-----------------------------------------------------------------------//
00216 #define Digital_IO_Output_Data                    0x0F00
00217 #define General_Purpose_Output                    0x0F10
00218 #define General_Purpose_Input                     0x0F18
00219 //-----------------------------------------------------------------------//
00220 // User RAM
00221 //-----------------------------------------------------------------------//
00222 #define User_RAM                                  0x0F80
00223 //-----------------------------------------------------------------------//
00224 // Process Data RAM
00225 //-----------------------------------------------------------------------//
00226 #define Process_Data_RAM                          0x1000    
00227 
00228 void LAN9252_RESET(void);
00229 void LAN9252_EtherCAT_CSR_WRITE(uint8_t CSR_SIZE,uint16_t CSR_ADDR,uint32_t CSR_DATA);
00230 uint32_t LAN9252_EtherCAT_CSR_READ(uint8_t CSR_SIZE,uint16_t CSR_ADDR);
00231 uint32_t LAN9252_EtherCAT_PRAM_READ(uint16_t PRAM_READ_LEN,uint16_t PRAM_READ_ADDR);
00232 void LAN9252_EtherCAT_PRAM_WRITE(uint16_t PRAM_WRITE_LEN,uint16_t PRAM_WRITE_ADDR, uint32_t PRAM_WR_DATA);
00233 
00234 
00235 
00236 #endif  /* LAN9252_H */
00237 
00238