Yuta Kitagami / Mbed 2 deprecated EtherCAT_Nucleo_F401

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Dependencies:   mbed

Files at this revision

API Documentation at this revision

Revision 0:3516fed95f0b, committed 2021-01-18

Comitter:
nonNoise
Date:
Mon Jan 18 03:46:20 2021 +0000
Commit message:
EtherCAT-Slave-Lib (LAN9252); Ver1.0

Changed in this revision

LAN9252.cpp Show annotated file Show diff for this revision Revisions of this file
LAN9252.h Show annotated file Show diff for this revision Revisions of this file
LAN925X_SPI.cpp Show annotated file Show diff for this revision Revisions of this file
LAN925X_SPI.h Show annotated file Show diff for this revision Revisions of this file
main.cpp Show annotated file Show diff for this revision Revisions of this file
mbed.bld Show annotated file Show diff for this revision Revisions of this file 
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/LAN9252.cpp	Mon Jan 18 03:46:20 2021 +0000
@@ -0,0 +1,137 @@
+
+#include "LAN9252.h"
+#include "LAN925X_SPI.h"
+#include <stdint.h>
+
+//=============================================================================//
+// LAN9252 RESET
+//=============================================================================//
+void LAN9252_RESET(void)
+{
+    uint32_t rdata;
+    uint32_t wdata;
+    uint32_t addr;
+    
+    addr = RESET_CTL;
+    LAN925X_SPI_WRITE(addr,ETHERCAT_RST);       
+    addr = BYTE_TEST;
+    rdata = LAN925X_SPI_READ(addr);
+    while(rdata!=0x87654321)
+    {
+        addr = BYTE_TEST;
+        rdata = LAN925X_SPI_READ(addr);
+    }
+}
+
+//=============================================================================//
+// LAN9252 EtherCAT CSR WRITE
+//=============================================================================//
+void LAN9252_EtherCAT_CSR_WRITE(uint8_t CSR_SIZE,uint16_t CSR_ADDR,uint32_t CSR_DATA)
+{
+
+    uint32_t rdata;
+    uint32_t wdata;
+    uint16_t addr;
+    addr = ECAT_CSR_DATA;
+    wdata = CSR_DATA;
+    LAN925X_SPI_WRITE(addr,wdata);
+
+    addr = ECAT_CSR_CMD;
+    wdata = (uint32_t)CSR_BUSY | (uint32_t)0<<30 | (uint32_t)CSR_SIZE<<16 | (uint32_t)CSR_ADDR; //Write
+    LAN925X_SPI_WRITE(addr,wdata);
+    
+    addr = ECAT_CSR_CMD;
+    rdata = LAN925X_SPI_READ(addr);
+    while(CSR_BUSY&rdata)
+    {
+        addr = ECAT_CSR_CMD;
+        rdata = LAN925X_SPI_READ(addr);
+    }
+
+}
+//=============================================================================//
+// LAN9252 EtherCAT CSR READ
+//=============================================================================//
+uint32_t LAN9252_EtherCAT_CSR_READ(uint8_t CSR_SIZE,uint16_t CSR_ADDR)
+{
+
+    uint32_t rdata;
+    uint32_t wdata;
+    uint16_t addr;
+    addr = ECAT_CSR_CMD;
+    wdata = (uint32_t)CSR_BUSY | (uint32_t)1<<30 | (uint32_t)CSR_SIZE<<16 | (uint32_t)CSR_ADDR; //Read
+    LAN925X_SPI_WRITE(addr,wdata);
+    
+    addr = ECAT_CSR_CMD;
+    rdata = LAN925X_SPI_READ(addr);
+    while(CSR_BUSY&rdata)
+    {
+        addr = ECAT_CSR_CMD;
+        rdata = LAN925X_SPI_READ(addr);
+    }
+    addr = ECAT_CSR_DATA;
+    rdata = LAN925X_SPI_READ(addr);
+    return rdata;
+}
+//=============================================================================//
+// LAN9252 EtherCAT Prossec RAM Read
+//=============================================================================//
+uint32_t LAN9252_EtherCAT_PRAM_READ(uint16_t PRAM_READ_LEN,uint16_t PRAM_READ_ADDR)
+{
+    uint32_t rdata;
+    uint32_t wdata;
+    uint32_t tmp;
+    uint16_t addr;
+    
+    addr = ECAT_PRAM_RD_ADDR_LEN;
+    wdata = (uint32_t)PRAM_READ_LEN<<16 | (uint32_t)PRAM_READ_ADDR; 
+    LAN925X_SPI_WRITE(addr,wdata);
+
+    addr = ECAT_PRAM_RD_CMD;
+    wdata = PRAM_READ_BUSY ; 
+    LAN925X_SPI_WRITE(addr,wdata);
+
+    addr = ECAT_PRAM_RD_DATA;
+    rdata = LAN925X_SPI_READ(addr);
+
+    addr = ECAT_PRAM_RD_CMD;
+    tmp = LAN925X_SPI_READ(addr);
+    while(PRAM_READ_BUSY&tmp)
+    {
+        addr = ECAT_PRAM_RD_CMD;
+        tmp = LAN925X_SPI_READ(addr);
+    }
+    return rdata;
+}
+//=============================================================================//
+// LAN9252 EtherCAT Prossec RAM Read
+//=============================================================================//
+void LAN9252_EtherCAT_PRAM_WRITE(uint16_t PRAM_WRITE_LEN,uint16_t PRAM_WRITE_ADDR, uint32_t PRAM_WR_DATA)
+{
+    uint32_t rdata;
+    uint32_t wdata;
+    uint32_t tmp;
+    uint16_t addr;
+
+    
+    addr = ECAT_PRAM_WR_DATA;
+    wdata = PRAM_WR_DATA; 
+    LAN925X_SPI_WRITE(addr,wdata);
+    
+    addr = ECAT_PRAM_WR_ADDR_LEN;
+    wdata = (uint32_t)PRAM_WRITE_LEN<<16 | (uint32_t)PRAM_WRITE_ADDR; 
+    LAN925X_SPI_WRITE(addr,wdata);
+
+    addr = ECAT_PRAM_WR_CMD;
+    wdata = PRAM_WRITE_BUSY ; 
+    LAN925X_SPI_WRITE(addr,wdata);
+
+    addr = ECAT_PRAM_WR_CMD;
+    tmp = LAN925X_SPI_READ(addr);
+    while(PRAM_WRITE_BUSY&tmp)
+    {
+        addr = ECAT_PRAM_WR_CMD;
+        tmp = LAN925X_SPI_READ(addr);
+    }
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/LAN9252.h	Mon Jan 18 03:46:20 2021 +0000
@@ -0,0 +1,238 @@
+/* 
+ * File:   LAN9252.h
+ * Author: kitagami
+ *
+ * Created on January 29, 2020, 9:11 PM
+ */
+
+#ifndef LAN9252_H
+#define	LAN9252_H
+
+#include <SPI.h>
+#include <stdint.h>
+
+#define ECAT_PRAM_RD_DATA       0x000
+#define ECAT_PRAM_WR_DATA       0x020
+#define ID_REV                  0x050
+#define IRQ_CFG                 0x054
+#define INT_STS                 0x058
+#define INT_EN                  0x05C
+#define BYTE_TEST               0x064
+#define HW_CFG                  0x074
+#define PMT_CTRL                0x084
+#define GPT_CFG                 0x08C
+#define GPT_CNT                 0x090
+#define FREE_RUN                0x09C
+#define RESET_CTL               0x1F8
+
+#define ETHERCAT_RST            0x40
+#define PHY_B_RST               0x04
+#define PHY_A_RST               0x02
+#define DIGITAL_RST             0x01
+
+#define ECAT_CSR_DATA           0x300
+#define ECAT_CSR_CMD            0x304
+#define CSR_BUSY                1<<31
+#define CSR_SIZE_8bit           1
+#define CSR_SIZE_16bit          2
+#define CSR_SIZE_32bit          4
+#define ECAT_PRAM_RD_ADDR_LEN   0x308
+#define ECAT_PRAM_RD_CMD        0x30C
+#define ECAT_PRAM_WR_ADDR_LEN   0x310
+#define ECAT_PRAM_WR_CMD        0x314
+
+#define PRAM_READ_BUSY  1<<31
+#define PRAM_READ_ABORT 1<<30
+#define PRAM_WRITE_BUSY  1<<31
+#define PRAM_WRITE_ABORT 1<<30
+    
+//-----------------------------------------------------------------------//
+// ESC Information
+//-----------------------------------------------------------------------//
+#define Type_Register                            0x0000
+#define Revision_Register                        0x0001
+#define Build_Register                           0x0002
+#define FMMUs_Supported                          0x0004
+#define SyncManagers_Supported                   0x0005
+#define RAM_Size                                 0x0006
+#define Port_Descriptor                          0x0007
+#define ESC_Features_Supported                   0x0008
+//-----------------------------------------------------------------------//
+// Station Address
+//-----------------------------------------------------------------------//
+#define Configured_Station                       0x0010
+#define Configured_Station_Alias                 0x0012
+//-----------------------------------------------------------------------//
+// Write Protection
+//-----------------------------------------------------------------------//
+#define Write_Enable                             0x0020
+#define Write_Protection                         0x0021
+#define ESC_Write_Enable                         0x0030
+#define ESC_Write_Protection                     0x0031
+//-----------------------------------------------------------------------//
+// Data Link Layer
+//-----------------------------------------------------------------------//
+#define ESC_Reset_ECAT                           0x0040
+#define ESC_Reset_PDI                            0x0041
+#define ESC_DL_Control                           0x0100
+#define Physical_Read_Write_Offset               0x0108
+#define ESC_DL_Status                            0x0110
+//-----------------------------------------------------------------------//
+// Application Layer
+//-----------------------------------------------------------------------//
+#define AL_Control                               0x0120
+#define AL_Status                                0x0130
+#define AL_Status_Code                           0x0134
+#define RUN_LED_Override                         0x0138
+//-----------------------------------------------------------------------//
+// PDI (Process Data Interface)
+//-----------------------------------------------------------------------//
+#define PDI_Control                              0x0140
+#define ESC_Configuration                        0x0141
+#define ASIC_Configuration                       0x0142
+#define PDI_Configuration                        0x0150
+#define Sync_Latch_PDI_Configuration             0x0151
+#define Extended_PDI_Configuration               0x0152
+//-----------------------------------------------------------------------//
+//Interrupts
+//-----------------------------------------------------------------------//
+#define ECAT_Event_Mask                          0x0200
+#define AL_Event_Mask                            0x0204
+#define ECAT_Event_Request                       0x0210
+#define AL_Event_Request                         0x0220
+//-----------------------------------------------------------------------//
+// Error Counters
+//-----------------------------------------------------------------------//
+#define RX_Error_Counters                        0x0300
+#define Forwarded_RX_Error_Counters              0x0308
+#define ECAT_Processing_Unit_Error_Counter       0x030C
+#define PDI_Error_Counter                        0x030D
+#define PDI_Error_Code                           0x030E
+#define Lost_Link_Counters                       0x0310
+//-----------------------------------------------------------------------//
+// Watchdogs
+//-----------------------------------------------------------------------//
+#define Watchdog_Time_PDI                        0x0410
+#define Watchdog_Time_Process_Data               0x0420
+#define Watchdog_Status_Process_Data             0x0440
+#define Watchdog_Counter_Process_Data            0x0442
+#define Watchdog_Counter_PDI                     0x0443
+//-----------------------------------------------------------------------//
+// EEPROM Interface
+//-----------------------------------------------------------------------//
+#define EEPROM_Configuration                     0x0500
+#define EEPROM_PDI_Access_State                  0x0501
+#define EEPROM_Control_Status                    0x0502
+#define EEPROM_Address                           0x0504
+#define EEPROM_Data                              0x0508
+//-----------------------------------------------------------------------//
+// MII Management Interface
+//-----------------------------------------------------------------------//
+#define MII_Management_Control_Status            0x0510
+#define PHY_Address                              0x0512
+#define PHY_Register_Address                     0x0513
+#define PHY_DATA                                 0x0514
+#define MII_Management_ECAT_Access_State         0x0516
+#define MII_Management_PDI_Access_State          0x0517
+#define PHY_Port_Statuss                         0x0518
+/*=========================================================
+0600h FMMU[2:0]s (3x16 bytes)
++0h-3h FMMUx Logical Start Address
++4h-5h FMMUx Length
++6h FMMUx Logical Start Bit
++7h FMMUx Logical Stop Bit
++8h-9h FMMUx Physical Start Address
++Ah FMMUx Physical Start Bit
++Bh FMMUx Type
++Ch FMMUx Activate
++Dh-Fh FMMUx Reserved
+0800h-081Fh SyncManager[3:0]s (4x8 bytes)
++0h-1h SyncManager x Physical Start Address
++2h-3h SyncManager x Length
++4h SyncManager x Control
++5h SyncManager x Status
++6h SyncManager x Activate
++7h SyncManager x PDI Control
+===========================================================*/
+//-----------------------------------------------------------------------//
+// Distributed Clocks - Receive Times
+//-----------------------------------------------------------------------//
+#define Receive_Time_Port_0                       0x0900
+#define Receive_Time_Port_1                       0x0904
+#define Receive_Time_Port_2                       0x0908
+//-----------------------------------------------------------------------//
+//Distributed Clocks - Time Loop Control Unit
+//-----------------------------------------------------------------------//
+#define System_Time                               0x0910
+#define Receive_Time_ECAT_Processing_Unit         0x0918
+#define System_Time_Offset                        0x0920
+#define System_Time_Delay                         0x0928
+#define System_Time_Difference                    0x092C
+#define Speed_Counter_Start                       0x0930
+#define Speed_Counter_Diff                        0x0932
+#define System_Time_Difference_Filter_Depth       0x0934
+#define Speed_Counter_Filter_Depth                0x0935
+//-----------------------------------------------------------------------//
+// Distributed Clocks - Cyclic Unit Control
+//-----------------------------------------------------------------------//
+#define Cyclic Unit Control                       0x0980
+//-----------------------------------------------------------------------//
+// Distributed Clocks - SYNC Out Unit
+//-----------------------------------------------------------------------//
+#define Activation                                0x0981
+#define Pulse_Length_of_SyncSignals               0x0982
+#define Activation_Status                         0x0984
+#define SYNC0_Status                              0x098E
+#define SYNC1_Status                              0x098F
+#define Start_Time_Cyclic_Operation               0x0990
+#define Next_SYNC1_Pulse                          0x0998
+#define SYNC0_Cycle_Time                          0x09A0
+#define SYNC1_Cycle_Time                          0x09A4
+//-----------------------------------------------------------------------//
+// Distributed Clocks - Latch In Unit
+//-----------------------------------------------------------------------//
+#define LATCH0_Control                            0x09A8
+#define LATCH1_Control                            0x09A9
+#define LATCH0_Status                             0x09AE
+#define LATCH1_Status                             0x09AF
+#define LATCH0_Time_Positive_Edge                 0x09B0
+#define LATCH0_Time_Negative_Edge                 0x09B8
+#define LATCH1_Time_Positive_Edge                 0x09C0
+#define LATCH1_Time_Negative_Edge                 0x09C8
+//-----------------------------------------------------------------------//
+// Distributed Clocks - SyncManager Event Times
+//-----------------------------------------------------------------------//
+#define EtherCAT_Buffer_Change_Event_Time         0x09F0
+#define PDI_Buffer_Start_Time_Event               0x09F8
+#define PDI_Buffer_Change_Event_Time              0x09FC
+//-----------------------------------------------------------------------//
+// ESC Specific
+//-----------------------------------------------------------------------//
+#define Product_ID                                0x0E00
+#define Vendor_ID                                 0x0E08
+//-----------------------------------------------------------------------//
+// Digital Input/Output
+//-----------------------------------------------------------------------//
+#define Digital_IO_Output_Data                    0x0F00
+#define General_Purpose_Output                    0x0F10
+#define General_Purpose_Input                     0x0F18
+//-----------------------------------------------------------------------//
+// User RAM
+//-----------------------------------------------------------------------//
+#define User_RAM                                  0x0F80
+//-----------------------------------------------------------------------//
+// Process Data RAM
+//-----------------------------------------------------------------------//
+#define Process_Data_RAM                          0x1000    
+
+void LAN9252_RESET(void);
+void LAN9252_EtherCAT_CSR_WRITE(uint8_t CSR_SIZE,uint16_t CSR_ADDR,uint32_t CSR_DATA);
+uint32_t LAN9252_EtherCAT_CSR_READ(uint8_t CSR_SIZE,uint16_t CSR_ADDR);
+uint32_t LAN9252_EtherCAT_PRAM_READ(uint16_t PRAM_READ_LEN,uint16_t PRAM_READ_ADDR);
+void LAN9252_EtherCAT_PRAM_WRITE(uint16_t PRAM_WRITE_LEN,uint16_t PRAM_WRITE_ADDR, uint32_t PRAM_WR_DATA);
+
+
+
+#endif	/* LAN9252_H */
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/LAN925X_SPI.cpp	Mon Jan 18 03:46:20 2021 +0000
@@ -0,0 +1,81 @@
+#include "LAN925X_SPI.h"
+#include <stdint.h>
+
+#include "mbed.h"
+//********************************************************************//
+// HardWare Interface
+//********************************************************************//
+
+#define     SPI_CS_LOW()    cs = 0;
+#define     SPI_CS_HIGH()   cs = 1;
+
+SPI spi(PA_7, PA_6, PA_5); // mosi, miso, sclk
+DigitalOut cs(PB_6);
+
+void LAN925X_SPI_Init(void)
+{   
+   SPI_CS_HIGH();
+    // Setup the spi for 8 bit data, high steady state clock,
+    // second edge capture, with a 1MHz clock rate
+    spi.format(8,3);
+    spi.frequency(20000000);
+}
+uint8_t SPI_8bit_Read(void)
+{
+    return spi.write(0x00);
+}
+void SPI_8bit_Write(uint8_t wdata)
+{
+    spi.write(wdata);
+}
+
+void SQI_RESET(void)
+{
+    //SS2_SetDigitalInput();
+    //while(SS2_GetValue()!=1);
+    SPI_CS_HIGH();
+    SPI_CS_HIGH();
+    SPI_CS_HIGH();
+    SPI_CS_HIGH();
+    SPI_CS_HIGH();
+    SPI_CS_HIGH();
+    SPI_CS_HIGH();
+    SPI_CS_HIGH();
+    SPI_CS_LOW();
+    SPI_8bit_Write(0xFF);
+    SPI_CS_HIGH();
+}
+
+
+
+
+uint32_t LAN925X_SPI_READ(uint16_t addr)
+{
+    uint32_t rdata;
+    SPI_CS_LOW();
+    SPI_8bit_Write(0x03); //Instruction
+    SPI_8bit_Write( 0xFF&(addr>>8) ); //Address
+    SPI_8bit_Write( 0xFF&(addr>>0) ); //Address
+    rdata =  (uint32_t)SPI_8bit_Read();
+    rdata |= (uint32_t)SPI_8bit_Read()<<8;
+    rdata |= (uint32_t)SPI_8bit_Read()<<16;
+    rdata |= (uint32_t)SPI_8bit_Read()<<24;
+    SPI_CS_HIGH();
+    return rdata;
+}
+
+uint32_t LAN925X_SPI_WRITE(uint16_t addr,uint32_t data)
+{
+    uint32_t rdata;
+    SPI_CS_LOW();
+    SPI_8bit_Write(0x02); //Instruction
+    SPI_8bit_Write( 0xFF&(addr>>8) ); //Address
+    SPI_8bit_Write( 0xFF&(addr>>0) ); //Address
+    SPI_8bit_Write( 0xFF&(data>>0) );
+    SPI_8bit_Write( 0xFF&(data>>8) );
+    SPI_8bit_Write( 0xFF&(data>>16) );
+    SPI_8bit_Write( 0xFF&(data>>24) );
+    SPI_CS_HIGH();
+    return rdata;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/LAN925X_SPI.h	Mon Jan 18 03:46:20 2021 +0000
@@ -0,0 +1,19 @@
+/* 
+ * File:   LAN9250_SPI.h
+ * Author: kitagami
+ *
+ * Created on May 8, 2019, 1:38 AM
+ */
+#include <stdint.h>
+
+#ifndef LAN9250_SPI_H
+#define	LAN9250_SPI_H
+void LAN925X_SPI_Init(void);
+uint8_t SPI_8bit_Read(void);
+void SPI_8bit_Write(uint8_t wdata);
+void SQI_RESET(void);
+uint32_t LAN925X_SPI_READ(uint16_t addr);
+uint32_t LAN925X_SPI_WRITE(uint16_t addr,uint32_t data);
+#endif	/* LAN9250_SPI_H */
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/main.cpp	Mon Jan 18 03:46:20 2021 +0000
@@ -0,0 +1,94 @@
+#include "mbed.h"
+
+#include "LAN9252.h"
+#include "LAN925X_SPI.h"
+
+
+//DigitalOut myled(LED1);
+Serial serial(USBTX, USBRX);
+
+ void UART_TX_Stringth(char S1[])
+{
+    serial.printf(S1);
+}
+
+
+int main() {
+    uint32_t rdata;
+    uint32_t rdata_buff[100];
+    int cnt=0;
+    uint32_t wdata;
+    char  S1[100];
+    uint16_t addr=0;
+    
+    serial.baud(115200);
+    UART_TX_Stringth("================================================== \n\r");
+    UART_TX_Stringth("   EtherCAT TEST   \n\r");
+    UART_TX_Stringth("================================================== \n\r");
+    
+    LAN925X_SPI_Init();
+    // RESET
+    //LAN9252_RESET();
+
+    addr = ID_REV;
+    rdata = LAN925X_SPI_READ(addr);
+    sprintf(S1,"ID_REV[0x%04X]: 0x%08lX \n\r",addr,rdata);
+    UART_TX_Stringth(S1);
+    
+    addr = BYTE_TEST;
+    rdata = LAN925X_SPI_READ(addr);
+    sprintf(S1,"BYTE_TEST[0x%04X]: 0x%08lX \n\r",addr,rdata);
+    UART_TX_Stringth(S1);
+    
+    addr = FREE_RUN;
+    rdata = LAN925X_SPI_READ(addr);
+    sprintf(S1,"FREE_RUN[0x%04X]: 0x%08lX \n\r",addr,rdata);
+    UART_TX_Stringth(S1);
+
+        
+    addr = Type_Register;
+    rdata = LAN9252_EtherCAT_CSR_READ(CSR_SIZE_32bit,addr);
+    sprintf(S1,"Type_Register[0x%04X]: 0x%08lX \n\r",addr,rdata);
+    UART_TX_Stringth(S1);
+    
+    addr = Product_ID;
+    rdata = LAN9252_EtherCAT_CSR_READ(CSR_SIZE_32bit,addr);
+    sprintf(S1,"Product_ID[0x%04X]: 0x%08lX \n\r",addr,rdata);
+    UART_TX_Stringth(S1);
+
+    addr = Vendor_ID;
+    rdata = LAN9252_EtherCAT_CSR_READ(CSR_SIZE_32bit,addr);
+    sprintf(S1,"Vendor_ID[0x%04X]: 0x%08lX \n\r",addr,rdata);
+    UART_TX_Stringth(S1);
+
+    addr = Process_Data_RAM;
+    rdata = LAN9252_EtherCAT_CSR_READ(CSR_SIZE_32bit,addr);
+    sprintf(S1,"Process_Data_RAM[0x%04X]: 0x%08lX \n\r",addr,rdata);
+    UART_TX_Stringth(S1);
+    
+    addr = RUN_LED_Override;
+    LAN9252_EtherCAT_CSR_WRITE(CSR_SIZE_32bit,addr,1<<4 | 0x0D);
+    cnt=0;
+    while(1);
+    while(1) {
+        addr = Process_Data_RAM;
+        rdata = LAN9252_EtherCAT_CSR_READ(CSR_SIZE_32bit,addr);
+        rdata_buff[cnt]=rdata;
+        if(cnt==10)
+        {
+         for(int i=0;i<cnt;i++)
+         {
+            sprintf(S1,"Process_Data_RAM[0x%04X]: 0x%08lX \n\r",i,rdata_buff[i]);
+            UART_TX_Stringth(S1);
+         }
+         cnt = 0;
+        }
+        else
+            cnt++;
+        //myled = 1; // LED is ON
+        //wait(0.05); // 200 ms
+        //myled = 0; // LED is OFF
+        //wait(0.05); // 1 sec
+    }
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed.bld	Mon Jan 18 03:46:20 2021 +0000
@@ -0,0 +1,1 @@
+https://os.mbed.com/users/mbed_official/code/mbed/builds/65be27845400
\ No newline at end of file