MFRC522.h

00001 /**
00002  * MFRC522.h - Library to use ARDUINO RFID MODULE KIT 13.56 MHZ WITH TAGS SPI W AND R BY COOQROBOT.
00003  * Based on code Dr.Leong   ( WWW.B2CQSHOP.COM )
00004  * Created by Miguel Balboa (circuitito.com), Jan, 2012.
00005  * Rewritten by Soren Thing Andersen (access.thing.dk), fall of 2013 (Translation to English, refactored, comments, anti collision, cascade levels.)
00006  * Ported to mbed by Martin Olejar, Dec, 2013
00007  *
00008  * Please read this file for an overview and then MFRC522.cpp for comments on the specific functions.
00009  * Search for "mf-rc522" on ebay.com to purchase the MF-RC522 board.
00010  *
00011  * There are three hardware components involved:
00012  * 1) The micro controller: An Arduino
00013  * 2) The PCD (short for Proximity Coupling Device): NXP MFRC522 Contactless Reader IC
00014  * 3) The PICC (short for Proximity Integrated Circuit Card): A card or tag using the ISO 14443A interface, eg Mifare or NTAG203.
00015  *
00016  * The microcontroller and card reader uses SPI for communication.
00017  * The protocol is described in the MFRC522 datasheet: http://www.nxp.com/documents/data_sheet/MFRC522.pdf
00018  *
00019  * The card reader and the tags communicate using a 13.56MHz electromagnetic field.
00020  * The protocol is defined in ISO/IEC 14443-3 Identification cards -- Contactless integrated circuit cards -- Proximity cards -- Part 3: Initialization and anticollision".
00021  * A free version of the final draft can be found at http://wg8.de/wg8n1496_17n3613_Ballot_FCD14443-3.pdf
00022  * Details are found in chapter 6, Type A: Initialization and anticollision.
00023  *
00024  * If only the PICC UID is wanted, the above documents has all the needed information.
00025  * To read and write from MIFARE PICCs, the MIFARE protocol is used after the PICC has been selected.
00026  * The MIFARE Classic chips and protocol is described in the datasheets:
00027  *    1K:   http://www.nxp.com/documents/data_sheet/MF1S503x.pdf
00028  *    4K:   http://www.nxp.com/documents/data_sheet/MF1S703x.pdf
00029  *    Mini: http://www.idcardmarket.com/download/mifare_S20_datasheet.pdf
00030  * The MIFARE Ultralight chip and protocol is described in the datasheets:
00031  *    Ultralight:   http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf
00032  *    Ultralight C: http://www.nxp.com/documents/short_data_sheet/MF0ICU2_SDS.pdf
00033  *
00034  * MIFARE Classic 1K (MF1S503x):
00035  *    Has 16 sectors * 4 blocks/sector * 16 bytes/block = 1024 bytes.
00036  *    The blocks are numbered 0-63.
00037  *    Block 3 in each sector is the Sector Trailer. See http://www.nxp.com/documents/data_sheet/MF1S503x.pdf sections 8.6 and 8.7:
00038  *        Bytes 0-5:   Key A
00039  *        Bytes 6-8:   Access Bits
00040  *        Bytes 9:     User data
00041  *        Bytes 10-15: Key B (or user data)
00042  *    Block 0 is read only manufacturer data.
00043  *    To access a block, an authentication using a key from the block's sector must be performed first.
00044  *    Example: To read from block 10, first authenticate using a key from sector 3 (blocks 8-11).
00045  *    All keys are set to FFFFFFFFFFFFh at chip delivery.
00046  *    Warning: Please read section 8.7 "Memory Access". It includes this text: if the PICC detects a format violation the whole sector is irreversibly blocked.
00047  *    To use a block in "value block" mode (for Increment/Decrement operations) you need to change the sector trailer. Use PICC_SetAccessBits() to calculate the bit patterns.
00048  * MIFARE Classic 4K (MF1S703x):
00049  *    Has (32 sectors * 4 blocks/sector + 8 sectors * 16 blocks/sector) * 16 bytes/block = 4096 bytes.
00050  *    The blocks are numbered 0-255.
00051  *    The last block in each sector is the Sector Trailer like above.
00052  * MIFARE Classic Mini (MF1 IC S20):
00053  *    Has 5 sectors * 4 blocks/sector * 16 bytes/block = 320 bytes.
00054  *    The blocks are numbered 0-19.
00055  *    The last block in each sector is the Sector Trailer like above.
00056  *
00057  * MIFARE Ultralight (MF0ICU1):
00058  *    Has 16 pages of 4 bytes = 64 bytes.
00059  *    Pages 0 + 1 is used for the 7-byte UID.
00060  *    Page 2 contains the last chech digit for the UID, one byte manufacturer internal data, and the lock bytes (see http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf section 8.5.2)
00061  *    Page 3 is OTP, One Time Programmable bits. Once set to 1 they cannot revert to 0.
00062  *    Pages 4-15 are read/write unless blocked by the lock bytes in page 2.
00063  * MIFARE Ultralight C (MF0ICU2):
00064  *    Has 48 pages of 4 bytes = 64 bytes.
00065  *    Pages 0 + 1 is used for the 7-byte UID.
00066  *    Page 2 contains the last chech digit for the UID, one byte manufacturer internal data, and the lock bytes (see http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf section 8.5.2)
00067  *    Page 3 is OTP, One Time Programmable bits. Once set to 1 they cannot revert to 0.
00068  *    Pages 4-39 are read/write unless blocked by the lock bytes in page 2.
00069  *    Page 40 Lock bytes
00070  *    Page 41 16 bit one way counter
00071  *    Pages 42-43 Authentication configuration
00072  *    Pages 44-47 Authentication key
00073  */
00074 #ifndef MFRC522_h
00075 #define MFRC522_h
00076 
00077 #include "mbed.h"
00078 
00079 class MFRC522 {
00080 public:
00081 
00082   /**
00083    * MFRC522 registers (described in chapter 9 of the datasheet).
00084    * When using SPI all addresses are shifted one bit left in the "SPI address byte" (section 8.1.2.3)
00085    */
00086   enum PCD_Register {
00087     // Page 0: Command and status
00088     //                0x00        // reserved for future use
00089     CommandReg      = 0x01 << 1,  // starts and stops command execution
00090     ComIEnReg       = 0x02 << 1,  // enable and disable interrupt request control bits
00091     DivIEnReg       = 0x03 << 1,  // enable and disable interrupt request control bits
00092     ComIrqReg       = 0x04 << 1,  // interrupt request bits
00093     DivIrqReg       = 0x05 << 1,  // interrupt request bits
00094     ErrorReg        = 0x06 << 1,  // error bits showing the error status of the last command executed
00095     Status1Reg      = 0x07 << 1,  // communication status bits
00096     Status2Reg      = 0x08 << 1,  // receiver and transmitter status bits
00097     FIFODataReg     = 0x09 << 1,  // input and output of 64 byte FIFO buffer
00098     FIFOLevelReg    = 0x0A << 1,  // number of bytes stored in the FIFO buffer
00099     WaterLevelReg   = 0x0B << 1,  // level for FIFO underflow and overflow warning
00100     ControlReg      = 0x0C << 1,  // miscellaneous control registers
00101     BitFramingReg   = 0x0D << 1,  // adjustments for bit-oriented frames
00102     CollReg         = 0x0E << 1,  // bit position of the first bit-collision detected on the RF interface
00103     //                0x0F        // reserved for future use
00104 
00105     // Page 1:Command
00106     //                0x10        // reserved for future use
00107     ModeReg         = 0x11 << 1,  // defines general modes for transmitting and receiving
00108     TxModeReg       = 0x12 << 1,  // defines transmission data rate and framing
00109     RxModeReg       = 0x13 << 1,  // defines reception data rate and framing
00110     TxControlReg    = 0x14 << 1,  // controls the logical behavior of the antenna driver pins TX1 and TX2
00111     TxASKReg        = 0x15 << 1,  // controls the setting of the transmission modulation
00112     TxSelReg        = 0x16 << 1,  // selects the internal sources for the antenna driver
00113     RxSelReg        = 0x17 << 1,  // selects internal receiver settings
00114     RxThresholdReg  = 0x18 << 1,  // selects thresholds for the bit decoder
00115     DemodReg        = 0x19 << 1,  // defines demodulator settings
00116     //                0x1A        // reserved for future use
00117     //                0x1B        // reserved for future use
00118     MfTxReg         = 0x1C << 1,  // controls some MIFARE communication transmit parameters
00119     MfRxReg         = 0x1D << 1,  // controls some MIFARE communication receive parameters
00120     //                0x1E        // reserved for future use
00121     SerialSpeedReg  = 0x1F << 1,  // selects the speed of the serial UART interface
00122 
00123     // Page 2: Configuration
00124     //                0x20        // reserved for future use
00125     CRCResultRegH   = 0x21 << 1,  // shows the MSB and LSB values of the CRC calculation
00126     CRCResultRegL   = 0x22 << 1,
00127     //                0x23        // reserved for future use
00128     ModWidthReg     = 0x24 << 1,  // controls the ModWidth setting?
00129     //                0x25        // reserved for future use
00130     RFCfgReg        = 0x26 << 1,  // configures the receiver gain
00131     GsNReg          = 0x27 << 1,  // selects the conductance of the antenna driver pins TX1 and TX2 for modulation
00132     CWGsPReg        = 0x28 << 1,  // defines the conductance of the p-driver output during periods of no modulation
00133     ModGsPReg       = 0x29 << 1,  // defines the conductance of the p-driver output during periods of modulation
00134     TModeReg        = 0x2A << 1,  // defines settings for the internal timer
00135     TPrescalerReg   = 0x2B << 1,  // the lower 8 bits of the TPrescaler value. The 4 high bits are in TModeReg.
00136     TReloadRegH     = 0x2C << 1,  // defines the 16-bit timer reload value
00137     TReloadRegL     = 0x2D << 1,
00138     TCntValueRegH   = 0x2E << 1,  // shows the 16-bit timer value
00139     TCntValueRegL   = 0x2F << 1,
00140 
00141     // Page 3:Test Registers
00142     //                0x30        // reserved for future use
00143     TestSel1Reg     = 0x31 << 1,  // general test signal configuration
00144     TestSel2Reg     = 0x32 << 1,  // general test signal configuration
00145     TestPinEnReg    = 0x33 << 1,  // enables pin output driver on pins D1 to D7
00146     TestPinValueReg = 0x34 << 1,  // defines the values for D1 to D7 when it is used as an I/O bus
00147     TestBusReg      = 0x35 << 1,  // shows the status of the internal test bus
00148     AutoTestReg     = 0x36 << 1,  // controls the digital self test
00149     VersionReg      = 0x37 << 1,  // shows the software version
00150     AnalogTestReg   = 0x38 << 1,  // controls the pins AUX1 and AUX2
00151     TestDAC1Reg     = 0x39 << 1,  // defines the test value for TestDAC1
00152     TestDAC2Reg     = 0x3A << 1,  // defines the test value for TestDAC2
00153     TestADCReg      = 0x3B << 1   // shows the value of ADC I and Q channels
00154     //                0x3C        // reserved for production tests
00155     //                0x3D        // reserved for production tests
00156     //                0x3E        // reserved for production tests
00157     //                0x3F        // reserved for production tests
00158   };
00159 
00160   // MFRC522 commands Described in chapter 10 of the datasheet.
00161   enum PCD_Command {
00162     PCD_Idle               = 0x00,   // no action, cancels current command execution
00163     PCD_Mem                = 0x01,   // stores 25 bytes into the internal buffer
00164     PCD_GenerateRandomID   = 0x02,   // generates a 10-byte random ID number
00165     PCD_CalcCRC            = 0x03,   // activates the CRC coprocessor or performs a self test
00166     PCD_Transmit           = 0x04,   // transmits data from the FIFO buffer
00167     PCD_NoCmdChange        = 0x07,   // no command change, can be used to modify the CommandReg register bits without affecting the command, for example, the PowerDown bit
00168     PCD_Receive            = 0x08,   // activates the receiver circuits
00169     PCD_Transceive         = 0x0C,   // transmits data from FIFO buffer to antenna and automatically activates the receiver after transmission
00170     PCD_MFAuthent          = 0x0E,   // performs the MIFARE standard authentication as a reader
00171     PCD_SoftReset          = 0x0F    // resets the MFRC522
00172   };
00173 
00174   // Commands sent to the PICC.
00175   enum PICC_Command {
00176     // The commands used by the PCD to manage communication with several PICCs (ISO 14443-3, Type A, section 6.4)
00177     PICC_CMD_REQA          = 0x26,   // REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
00178     PICC_CMD_WUPA          = 0x52,   // Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
00179     PICC_CMD_CT            = 0x88,   // Cascade Tag. Not really a command, but used during anti collision.
00180     PICC_CMD_SEL_CL1       = 0x93,   // Anti collision/Select, Cascade Level 1
00181     PICC_CMD_SEL_CL2       = 0x95,   // Anti collision/Select, Cascade Level 1
00182     PICC_CMD_SEL_CL3       = 0x97,   // Anti collision/Select, Cascade Level 1
00183     PICC_CMD_HLTA          = 0x50,   // HaLT command, Type A. Instructs an ACTIVE PICC to go to state HALT.
00184 
00185     // The commands used for MIFARE Classic (from http://www.nxp.com/documents/data_sheet/MF1S503x.pdf, Section 9)
00186     // Use PCD_MFAuthent to authenticate access to a sector, then use these commands to read/write/modify the blocks on the sector.
00187     // The read/write commands can also be used for MIFARE Ultralight.
00188     PICC_CMD_MF_AUTH_KEY_A = 0x60,   // Perform authentication with Key A
00189     PICC_CMD_MF_AUTH_KEY_B = 0x61,   // Perform authentication with Key B
00190     PICC_CMD_MF_READ       = 0x30,   // Reads one 16 byte block from the authenticated sector of the PICC. Also used for MIFARE Ultralight.
00191     PICC_CMD_MF_WRITE      = 0xA0,   // Writes one 16 byte block to the authenticated sector of the PICC. Called "COMPATIBILITY WRITE" for MIFARE Ultralight.
00192     PICC_CMD_MF_DECREMENT  = 0xC0,   // Decrements the contents of a block and stores the result in the internal data register.
00193     PICC_CMD_MF_INCREMENT  = 0xC1,   // Increments the contents of a block and stores the result in the internal data register.
00194     PICC_CMD_MF_RESTORE    = 0xC2,   // Reads the contents of a block into the internal data register.
00195     PICC_CMD_MF_TRANSFER   = 0xB0,   // Writes the contents of the internal data register to a block.
00196 
00197     // The commands used for MIFARE Ultralight (from http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf, Section 8.6)
00198     // The PICC_CMD_MF_READ and PICC_CMD_MF_WRITE can also be used for MIFARE Ultralight.
00199     PICC_CMD_UL_WRITE      = 0xA2    // Writes one 4 byte page to the PICC.
00200   };
00201 
00202   // MIFARE constants that does not fit anywhere else
00203   enum MIFARE_Misc {
00204     MF_ACK                 = 0xA,    // The MIFARE Classic uses a 4 bit ACK/NAK. Any other value than 0xA is NAK.
00205     MF_KEY_SIZE            = 6       // A Mifare Crypto1 key is 6 bytes.
00206   };
00207 
00208   // PICC types we can detect. Remember to update PICC_GetTypeName() if you add more.
00209   enum PICC_Type {
00210     PICC_TYPE_UNKNOWN      = 0,
00211     PICC_TYPE_ISO_14443_4  = 1,  // PICC compliant with ISO/IEC 14443-4
00212     PICC_TYPE_ISO_18092    = 2,  // PICC compliant with ISO/IEC 18092 (NFC)
00213     PICC_TYPE_MIFARE_MINI  = 3,  // MIFARE Classic protocol, 320 bytes
00214     PICC_TYPE_MIFARE_1K    = 4,  // MIFARE Classic protocol, 1KB
00215     PICC_TYPE_MIFARE_4K    = 5,  // MIFARE Classic protocol, 4KB
00216     PICC_TYPE_MIFARE_UL    = 6,  // MIFARE Ultralight or Ultralight C
00217     PICC_TYPE_MIFARE_PLUS  = 7,  // MIFARE Plus
00218     PICC_TYPE_TNP3XXX      = 8,  // Only mentioned in NXP AN 10833 MIFARE Type Identification Procedure
00219     PICC_TYPE_NOT_COMPLETE = 255 // SAK indicates UID is not complete.
00220   };
00221 
00222   // Return codes from the functions in this class. Remember to update GetStatusCodeName() if you add more.
00223   enum StatusCode {
00224     STATUS_OK              = 1,  // Success
00225     STATUS_ERROR           = 2,  // Error in communication
00226     STATUS_COLLISION       = 3,  // Collision detected
00227     STATUS_TIMEOUT         = 4,  // Timeout in communication.
00228     STATUS_NO_ROOM         = 5,  // A buffer is not big enough.
00229     STATUS_INTERNAL_ERROR  = 6,  // Internal error in the code. Should not happen ;-)
00230     STATUS_INVALID         = 7,  // Invalid argument.
00231     STATUS_CRC_WRONG       = 8,  // The CRC_A does not match
00232     STATUS_MIFARE_NACK     = 9   // A MIFARE PICC responded with NAK.
00233   };
00234 
00235   // A struct used for passing the UID of a PICC.
00236   typedef struct {
00237     uint8_t    size;     // Number of bytes in the UID. 4, 7 or 10.
00238     uint8_t    uidByte[10];
00239     uint8_t    sak;      // The SAK (Select acknowledge) byte returned from the PICC after successful selection.
00240   } Uid;
00241 
00242   // A struct used for passing a MIFARE Crypto1 key
00243   typedef struct {
00244     uint8_t    keyByte[MF_KEY_SIZE];
00245   } MIFARE_Key;
00246 
00247   // Member variables
00248   Uid uid;                // Used by PICC_ReadCardSerial().
00249 
00250   // Size of the MFRC522 FIFO
00251   static const uint8_t FIFO_SIZE = 64;   // The FIFO is 64 bytes.
00252 
00253   /**
00254   * MFRC522 constructor
00255   *
00256   * @param mosi  SPI MOSI pin
00257   * @param miso  SPI MISO pin
00258   * @param sclk  SPI SCLK pin
00259   * @param cs    SPI CS pin
00260   * @param reset Reset pin
00261   */
00262   MFRC522(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName reset);
00263 
00264   /**
00265   * MFRC522 destructor
00266   */
00267   ~MFRC522();
00268   
00269 
00270   // ************************************************************************************
00271   //! @name Functions for manipulating the MFRC522
00272   // ************************************************************************************
00273   //@{
00274 
00275   /**
00276   * Initializes the MFRC522 chip.
00277   */
00278   void    PCD_Init           (void);
00279 
00280   /**
00281   * Performs a soft reset on the MFRC522 chip and waits for it to be ready again.
00282   */
00283   void    PCD_Reset          (void);
00284 
00285   /**
00286   * Turns the antenna on by enabling pins TX1 and TX2.
00287   * After a reset these pins disabled.
00288   */
00289   void    PCD_AntennaOn      (void);
00290 
00291   /**
00292   * Writes a byte to the specified register in the MFRC522 chip.
00293   * The interface is described in the datasheet section 8.1.2.
00294   *
00295   * @param reg   The register to write to. One of the PCD_Register enums.
00296   * @param value The value to write.
00297   */
00298   void    PCD_WriteRegister  (uint8_t reg, uint8_t value);
00299 
00300   /**
00301   * Writes a number of bytes to the specified register in the MFRC522 chip.
00302   * The interface is described in the datasheet section 8.1.2.
00303   *
00304   * @param reg    The register to write to. One of the PCD_Register enums.
00305   * @param count  The number of bytes to write to the register
00306   * @param values The values to write. Byte array.
00307   */
00308   void    PCD_WriteRegister  (uint8_t reg, uint8_t count, uint8_t *values);
00309 
00310   /**
00311   * Reads a byte from the specified register in the MFRC522 chip.
00312   * The interface is described in the datasheet section 8.1.2.
00313   *
00314   * @param reg The register to read from. One of the PCD_Register enums.
00315   * @returns Register value
00316   */
00317   uint8_t PCD_ReadRegister   (uint8_t reg);
00318 
00319   /**
00320   * Reads a number of bytes from the specified register in the MFRC522 chip.
00321   * The interface is described in the datasheet section 8.1.2.
00322   *
00323   * @param reg     The register to read from. One of the PCD_Register enums.
00324   * @param count   The number of bytes to read.
00325   * @param values  Byte array to store the values in.
00326   * @param rxAlign Only bit positions rxAlign..7 in values[0] are updated.
00327   */
00328   void    PCD_ReadRegister   (uint8_t reg, uint8_t count, uint8_t *values, uint8_t rxAlign = 0);
00329 
00330   /**
00331   * Sets the bits given in mask in register reg.
00332   *
00333   * @param reg  The register to update. One of the PCD_Register enums.
00334   * @param mask The bits to set.
00335   */
00336   void    PCD_SetRegisterBits(uint8_t reg, uint8_t mask);
00337 
00338   /**
00339   * Clears the bits given in mask from register reg.
00340   *
00341   * @param reg  The register to update. One of the PCD_Register enums.
00342   * @param mask The bits to clear.
00343   */
00344   void    PCD_ClrRegisterBits(uint8_t reg, uint8_t mask);
00345 
00346   /**
00347   * Use the CRC coprocessor in the MFRC522 to calculate a CRC_A.
00348   *
00349   * @param data   Pointer to the data to transfer to the FIFO for CRC calculation.
00350   * @param length The number of bytes to transfer.
00351   * @param result Pointer to result buffer. Result is written to result[0..1], low byte first.
00352   * @return STATUS_OK on success, STATUS_??? otherwise.
00353   */
00354   uint8_t PCD_CalculateCRC   (uint8_t *data, uint8_t length, uint8_t *result);
00355 
00356   /**
00357    * Executes the Transceive command.
00358    * CRC validation can only be done if backData and backLen are specified.
00359    *
00360    * @param sendData Pointer to the data to transfer to the FIFO.
00361    * @param sendLen  Number of bytes to transfer to the FIFO.
00362    * @param backData NULL or pointer to buffer if data should be read back after executing the command.
00363    * @param backLen  Max number of bytes to write to *backData. Out: The number of bytes returned.
00364    * @param validBits The number of valid bits in the last byte. 0 for 8 valid bits. Default NULL.
00365    * @param rxAlign  Defines the bit position in backData[0] for the first bit received. Default 0.
00366    * @param checkCRC True => The last two bytes of the response is assumed to be a CRC_A that must be validated.
00367    *
00368    * @return STATUS_OK on success, STATUS_??? otherwise.
00369    */
00370   uint8_t PCD_TransceiveData (uint8_t *sendData,
00371                               uint8_t sendLen,
00372                               uint8_t *backData,
00373                               uint8_t *backLen,
00374                               uint8_t *validBits = NULL,
00375                               uint8_t rxAlign    = 0,
00376                               bool    checkCRC   = false);
00377 
00378 
00379   /**
00380    * Transfers data to the MFRC522 FIFO, executes a commend, waits for completion and transfers data back from the FIFO.
00381    * CRC validation can only be done if backData and backLen are specified.
00382    *
00383    * @param command   The command to execute. One of the PCD_Command enums.
00384    * @param waitIRq   The bits in the ComIrqReg register that signals successful completion of the command.
00385    * @param sendData  Pointer to the data to transfer to the FIFO.
00386    * @param sendLen   Number of bytes to transfer to the FIFO.
00387    * @param backData  NULL or pointer to buffer if data should be read back after executing the command.
00388    * @param backLen   In: Max number of bytes to write to *backData. Out: The number of bytes returned.
00389    * @param validBits In/Out: The number of valid bits in the last byte. 0 for 8 valid bits.
00390    * @param rxAlign   In: Defines the bit position in backData[0] for the first bit received. Default 0.
00391    * @param checkCRC  In: True => The last two bytes of the response is assumed to be a CRC_A that must be validated.
00392    *
00393    * @return STATUS_OK on success, STATUS_??? otherwise.
00394    */
00395   uint8_t PCD_CommunicateWithPICC(uint8_t command,
00396                                   uint8_t waitIRq,
00397                                   uint8_t *sendData,
00398                                   uint8_t sendLen,
00399                                   uint8_t *backData  = NULL,
00400                                   uint8_t *backLen   = NULL,
00401                                   uint8_t *validBits = NULL,
00402                                   uint8_t rxAlign    = 0,
00403                                   bool    checkCRC   = false);
00404 
00405   /**
00406    * Transmits a REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
00407    * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
00408    *
00409    * @param bufferATQA  The buffer to store the ATQA (Answer to request) in
00410    * @param bufferSize  Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
00411    * 
00412    * @return STATUS_OK on success, STATUS_??? otherwise.
00413    */
00414   uint8_t PICC_RequestA      (uint8_t *bufferATQA, uint8_t *bufferSize);
00415   
00416   /**
00417    * Transmits a Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
00418    * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
00419    *
00420    * @param bufferATQA  The buffer to store the ATQA (Answer to request) in
00421    * @param bufferSize  Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
00422    * 
00423    * @return STATUS_OK on success, STATUS_??? otherwise.
00424    */  
00425   uint8_t PICC_WakeupA       (uint8_t *bufferATQA, uint8_t *bufferSize);
00426   
00427   /**
00428    * Transmits REQA or WUPA commands.
00429    * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
00430    *
00431    * @param command     The command to send - PICC_CMD_REQA or PICC_CMD_WUPA
00432    * @param bufferATQA  The buffer to store the ATQA (Answer to request) in
00433    * @param bufferSize  Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
00434    * 
00435    * @return STATUS_OK on success, STATUS_??? otherwise.
00436    */  
00437   uint8_t PICC_REQA_or_WUPA  (uint8_t command, uint8_t *bufferATQA, uint8_t *bufferSize);
00438   
00439   /**
00440    * Transmits SELECT/ANTICOLLISION commands to select a single PICC.
00441    * Before calling this function the PICCs must be placed in the READY(*) state by calling PICC_RequestA() or PICC_WakeupA().
00442    * On success:
00443    *   - The chosen PICC is in state ACTIVE(*) and all other PICCs have returned to state IDLE/HALT. (Figure 7 of the ISO/IEC 14443-3 draft.)
00444    *   - The UID size and value of the chosen PICC is returned in *uid along with the SAK.
00445    * 
00446    * A PICC UID consists of 4, 7 or 10 bytes.
00447    * Only 4 bytes can be specified in a SELECT command, so for the longer UIDs two or three iterations are used:
00448    *
00449    *   UID size        Number of UID bytes                Cascade levels                Example of PICC
00450    *   ========        ===================                ==============                ===============
00451    *   single                   4                                1                      MIFARE Classic
00452    *   double                   7                                2                      MIFARE Ultralight
00453    *   triple                  10                                3                      Not currently in use?
00454    *
00455    *
00456    * @param uid        Pointer to Uid struct. Normally output, but can also be used to supply a known UID.
00457    * @param validBits  The number of known UID bits supplied in *uid. Normally 0. If set you must also supply uid->size.
00458    *   
00459    * @return STATUS_OK on success, STATUS_??? otherwise.
00460    */
00461   uint8_t PICC_Select        (Uid *uid, uint8_t validBits = 0);
00462   
00463   /**
00464    * Instructs a PICC in state ACTIVE(*) to go to state HALT.
00465    *
00466    * @return STATUS_OK on success, STATUS_??? otherwise.
00467    */  
00468   uint8_t PICC_HaltA         (void);
00469   
00470   // ************************************************************************************
00471   //@}
00472 
00473 
00474   // ************************************************************************************
00475   //! @name Functions for communicating with MIFARE PICCs
00476   // ************************************************************************************
00477   //@{
00478   
00479   /**
00480    * Executes the MFRC522 MFAuthent command.
00481    * This command manages MIFARE authentication to enable a secure communication to any MIFARE Mini, MIFARE 1K and MIFARE 4K card.
00482    * The authentication is described in the MFRC522 datasheet section 10.3.1.9 and http://www.nxp.com/documents/data_sheet/MF1S503x.pdf section 10.1.
00483    * For use with MIFARE Classic PICCs.
00484    * The PICC must be selected - ie in state ACTIVE(*) - before calling this function.
00485    * Remember to call PCD_StopCrypto1() after communicating with the authenticated PICC - otherwise no new communications can start.
00486    * 
00487    * All keys are set to FFFFFFFFFFFFh at chip delivery.
00488    *
00489    * @param command    PICC_CMD_MF_AUTH_KEY_A or PICC_CMD_MF_AUTH_KEY_B
00490    * @param blockAddr  The block number. See numbering in the comments in the .h file.
00491    * @param key        Pointer to the Crypteo1 key to use (6 bytes)
00492    * @param uid        Pointer to Uid struct. The first 4 bytes of the UID is used.
00493    * 
00494    * @return STATUS_OK on success, STATUS_??? otherwise. Probably STATUS_TIMEOUT if you supply the wrong key.
00495    */
00496   uint8_t PCD_Authenticate   (uint8_t command, uint8_t blockAddr, MIFARE_Key *key, Uid *uid);
00497   
00498   /**
00499    * Used to exit the PCD from its authenticated state.
00500    * Remember to call this function after communicating with an authenticated PICC - otherwise no new communications can start.
00501    */
00502   void    PCD_StopCrypto1    (void);
00503   
00504   /**
00505    * Reads 16 bytes (+ 2 bytes CRC_A) from the active PICC.
00506    * 
00507    * For MIFARE Classic the sector containing the block must be authenticated before calling this function.
00508    * 
00509    * For MIFARE Ultralight only addresses 00h to 0Fh are decoded.
00510    * The MF0ICU1 returns a NAK for higher addresses.
00511    * The MF0ICU1 responds to the READ command by sending 16 bytes starting from the page address defined by the command argument.
00512    * For example; if blockAddr is 03h then pages 03h, 04h, 05h, 06h are returned.
00513    * A roll-back is implemented: If blockAddr is 0Eh, then the contents of pages 0Eh, 0Fh, 00h and 01h are returned.
00514    * 
00515    * The buffer must be at least 18 bytes because a CRC_A is also returned.
00516    * Checks the CRC_A before returning STATUS_OK.
00517    *
00518    * @param blockAddr  MIFARE Classic: The block (0-0xff) number. MIFARE Ultralight: The first page to return data from.
00519    * @param buffer     The buffer to store the data in
00520    * @param bufferSize Buffer size, at least 18 bytes. Also number of bytes returned if STATUS_OK.
00521    *
00522    * @return STATUS_OK on success, STATUS_??? otherwise.
00523    */
00524   uint8_t MIFARE_Read        (uint8_t blockAddr, uint8_t *buffer, uint8_t *bufferSize);
00525   
00526   /**
00527    * Writes 16 bytes to the active PICC.
00528    * 
00529    * For MIFARE Classic the sector containing the block must be authenticated before calling this function.
00530    * 
00531    * For MIFARE Ultralight the opretaion is called "COMPATIBILITY WRITE".
00532    * Even though 16 bytes are transferred to the Ultralight PICC, only the least significant 4 bytes (bytes 0 to 3)
00533    * are written to the specified address. It is recommended to set the remaining bytes 04h to 0Fh to all logic 0.
00534    *
00535    * @param blockAddr  MIFARE Classic: The block (0-0xff) number. MIFARE Ultralight: The page (2-15) to write to.
00536    * @param buffer     The 16 bytes to write to the PICC
00537    * @param bufferSize Buffer size, must be at least 16 bytes. Exactly 16 bytes are written.
00538    *
00539    * @return STATUS_OK on success, STATUS_??? otherwise.
00540  */
00541   uint8_t MIFARE_Write       (uint8_t blockAddr, uint8_t *buffer, uint8_t bufferSize);
00542   
00543   /**
00544    * Writes a 4 byte page to the active MIFARE Ultralight PICC.
00545    * 
00546    * @param page       The page (2-15) to write to.
00547    * @param buffer     The 4 bytes to write to the PICC
00548    * @param bufferSize Buffer size, must be at least 4 bytes. Exactly 4 bytes are written.
00549    *
00550    * @return STATUS_OK on success, STATUS_??? otherwise.
00551    */
00552   uint8_t MIFARE_UltralightWrite(uint8_t page, uint8_t *buffer, uint8_t bufferSize);
00553    
00554   /**
00555    * MIFARE Decrement subtracts the delta from the value of the addressed block, and stores the result in a volatile memory.
00556    * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
00557    * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
00558    * Use MIFARE_Transfer() to store the result in a block.
00559    *
00560    * @param blockAddr The block (0-0xff) number.
00561    * @param delta     This number is subtracted from the value of block blockAddr.
00562    *
00563    * @return STATUS_OK on success, STATUS_??? otherwise.
00564    */
00565   uint8_t MIFARE_Decrement   (uint8_t blockAddr, uint32_t delta);
00566   
00567   /**
00568    * MIFARE Increment adds the delta to the value of the addressed block, and stores the result in a volatile memory.
00569    * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
00570    * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
00571    * Use MIFARE_Transfer() to store the result in a block.
00572    * 
00573    * @param blockAddr The block (0-0xff) number.
00574    * @param delta     This number is added to the value of block blockAddr.
00575    *
00576    * @return STATUS_OK on success, STATUS_??? otherwise.
00577    */
00578   uint8_t MIFARE_Increment   (uint8_t blockAddr, uint32_t delta);
00579   
00580   /**
00581    * MIFARE Restore copies the value of the addressed block into a volatile memory.
00582    * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
00583    * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
00584    * Use MIFARE_Transfer() to store the result in a block.
00585    * 
00586    * @param blockAddr The block (0-0xff) number.
00587    *
00588    * @return STATUS_OK on success, STATUS_??? otherwise.
00589    */
00590   uint8_t MIFARE_Restore     (uint8_t blockAddr);
00591   
00592   /**
00593    * MIFARE Transfer writes the value stored in the volatile memory into one MIFARE Classic block.
00594    * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
00595    * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
00596    * 
00597    * @param blockAddr The block (0-0xff) number.
00598    *
00599    * @return STATUS_OK on success, STATUS_??? otherwise.
00600    */
00601   uint8_t MIFARE_Transfer    (uint8_t blockAddr);
00602   
00603   // ************************************************************************************
00604   //@}
00605 
00606 
00607   // ************************************************************************************
00608   //! @name Support functions
00609   // ************************************************************************************
00610   //@{
00611   
00612   /**
00613    * Wrapper for MIFARE protocol communication.
00614    * Adds CRC_A, executes the Transceive command and checks that the response is MF_ACK or a timeout.
00615    * 
00616    * @param sendData      Pointer to the data to transfer to the FIFO. Do NOT include the CRC_A.
00617    * @param sendLen       Number of bytes in sendData.
00618    * @param acceptTimeout True => A timeout is also success
00619    *
00620    * @return STATUS_OK on success, STATUS_??? otherwise.
00621    */
00622   uint8_t PCD_MIFARE_Transceive(uint8_t *sendData, uint8_t sendLen, bool acceptTimeout = false);
00623   
00624   /**
00625    * Translates the SAK (Select Acknowledge) to a PICC type.
00626    * 
00627    * @param sak The SAK byte returned from PICC_Select().
00628    *
00629    * @return PICC_Type
00630    */
00631   uint8_t PICC_GetType         (uint8_t sak);
00632   
00633   /**
00634    * Returns a string pointer to the PICC type name.
00635    * 
00636    * @param type One of the PICC_Type enums.
00637    *
00638    * @return A string pointer to the PICC type name.
00639    */
00640   char*   PICC_GetTypeName     (uint8_t type);
00641   
00642   /**
00643    * Returns a string pointer to a status code name.
00644    * 
00645    * @param code One of the StatusCode enums.
00646    *
00647    * @return A string pointer to a status code name.
00648    */
00649   char*   GetStatusCodeName    (uint8_t code);
00650   
00651   /**
00652    * Calculates the bit pattern needed for the specified access bits. In the [C1 C2 C3] tupples C1 is MSB (=4) and C3 is LSB (=1).
00653    * 
00654    * @param accessBitBuffer Pointer to byte 6, 7 and 8 in the sector trailer. Bytes [0..2] will be set.
00655    * @param g0              Access bits [C1 C2 C3] for block 0 (for sectors 0-31) or blocks 0-4 (for sectors 32-39)
00656    * @param g1              Access bits [C1 C2 C3] for block 1 (for sectors 0-31) or blocks 5-9 (for sectors 32-39)
00657    * @param g2              Access bits [C1 C2 C3] for block 2 (for sectors 0-31) or blocks 10-14 (for sectors 32-39)
00658    * @param g3              Access bits [C1 C2 C3] for the sector trailer, block 3 (for sectors 0-31) or block 15 (for sectors 32-39)
00659    */
00660   void    MIFARE_SetAccessBits (uint8_t *accessBitBuffer,
00661                                 uint8_t g0,
00662                                 uint8_t g1,
00663                                 uint8_t g2,
00664                                 uint8_t g3);
00665                                 
00666   // ************************************************************************************
00667   //@}
00668 
00669 
00670   // ************************************************************************************
00671   //! @name Convenience functions - does not add extra functionality
00672   // ************************************************************************************
00673   //@{
00674   
00675   /**
00676    * Returns true if a PICC responds to PICC_CMD_REQA.
00677    * Only "new" cards in state IDLE are invited. Sleeping cards in state HALT are ignored.
00678    * 
00679    * @return bool
00680    */
00681   bool    PICC_IsNewCardPresent(void);
00682   
00683   /**
00684    * Simple wrapper around PICC_Select.
00685    * Returns true if a UID could be read.
00686    * Remember to call PICC_IsNewCardPresent(), PICC_RequestA() or PICC_WakeupA() first.
00687    * The read UID is available in the class variable uid.
00688    * 
00689    * @return bool
00690    */
00691   bool    PICC_ReadCardSerial  (void);
00692   
00693   // ************************************************************************************
00694   //@}
00695 
00696 
00697 private:
00698   SPI              m_SPI;
00699   DigitalOut       m_CS;
00700   DigitalOut       m_RESET;
00701 
00702   /**
00703    * Helper function for the two-step MIFARE Classic protocol operations Decrement, Increment and Restore.
00704    * 
00705    * @param command    The command to use
00706    * @param blockAddr  The block (0-0xff) number.
00707    * @param data       The data to transfer in step 2
00708    *
00709    * @return STATUS_OK on success, STATUS_??? otherwise.
00710    */
00711   uint8_t MIFARE_TwoStepHelper(uint8_t command, uint8_t blockAddr, uint32_t data);
00712 };
00713 
00714 #endif