Maxim nexpaq / nexpaq_dev

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hal/hal/spi_api.h@0:6c56fb4bc5f0, 2016-11-04 (annotated)

Committer:
nexpaq
Date:
Fri Nov 04 20:27:58 2016 +0000
Revision:
0:6c56fb4bc5f0
Moving to library for sharing updates

Who changed what in which revision?

UserRevisionLine numberNew contents of line
nexpaq 0:6c56fb4bc5f0 1 /* mbed Microcontroller Library
nexpaq 0:6c56fb4bc5f0 2 * Copyright (c) 2006-2013 ARM Limited
nexpaq 0:6c56fb4bc5f0 3 *
nexpaq 0:6c56fb4bc5f0 4 * Licensed under the Apache License, Version 2.0 (the "License");
nexpaq 0:6c56fb4bc5f0 5 * you may not use this file except in compliance with the License.
nexpaq 0:6c56fb4bc5f0 6 * You may obtain a copy of the License at
nexpaq 0:6c56fb4bc5f0 7 *
nexpaq 0:6c56fb4bc5f0 8 * http://www.apache.org/licenses/LICENSE-2.0
nexpaq 0:6c56fb4bc5f0 9 *
nexpaq 0:6c56fb4bc5f0 10 * Unless required by applicable law or agreed to in writing, software
nexpaq 0:6c56fb4bc5f0 11 * distributed under the License is distributed on an "AS IS" BASIS,
nexpaq 0:6c56fb4bc5f0 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
nexpaq 0:6c56fb4bc5f0 13 * See the License for the specific language governing permissions and
nexpaq 0:6c56fb4bc5f0 14 * limitations under the License.
nexpaq 0:6c56fb4bc5f0 15 */
nexpaq 0:6c56fb4bc5f0 16 #ifndef MBED_SPI_API_H
nexpaq 0:6c56fb4bc5f0 17 #define MBED_SPI_API_H
nexpaq 0:6c56fb4bc5f0 18
nexpaq 0:6c56fb4bc5f0 19 #include "device.h"
nexpaq 0:6c56fb4bc5f0 20 #include "dma_api.h"
nexpaq 0:6c56fb4bc5f0 21 #include "buffer.h"
nexpaq 0:6c56fb4bc5f0 22
nexpaq 0:6c56fb4bc5f0 23 #if DEVICE_SPI
nexpaq 0:6c56fb4bc5f0 24
nexpaq 0:6c56fb4bc5f0 25 #define SPI_EVENT_ERROR (1 << 1)
nexpaq 0:6c56fb4bc5f0 26 #define SPI_EVENT_COMPLETE (1 << 2)
nexpaq 0:6c56fb4bc5f0 27 #define SPI_EVENT_RX_OVERFLOW (1 << 3)
nexpaq 0:6c56fb4bc5f0 28 #define SPI_EVENT_ALL (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)
nexpaq 0:6c56fb4bc5f0 29
nexpaq 0:6c56fb4bc5f0 30 #define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // Internal flag to report that an event occurred
nexpaq 0:6c56fb4bc5f0 31
nexpaq 0:6c56fb4bc5f0 32 #define SPI_FILL_WORD (0xFFFF)
nexpaq 0:6c56fb4bc5f0 33
nexpaq 0:6c56fb4bc5f0 34 #if DEVICE_SPI_ASYNCH
nexpaq 0:6c56fb4bc5f0 35 /** Asynch SPI HAL structure
nexpaq 0:6c56fb4bc5f0 36 */
nexpaq 0:6c56fb4bc5f0 37 typedef struct {
nexpaq 0:6c56fb4bc5f0 38 struct spi_s spi; /**< Target specific SPI structure */
nexpaq 0:6c56fb4bc5f0 39 struct buffer_s tx_buff; /**< Tx buffer */
nexpaq 0:6c56fb4bc5f0 40 struct buffer_s rx_buff; /**< Rx buffer */
nexpaq 0:6c56fb4bc5f0 41 } spi_t;
nexpaq 0:6c56fb4bc5f0 42
nexpaq 0:6c56fb4bc5f0 43 #else
nexpaq 0:6c56fb4bc5f0 44 /** Non-asynch SPI HAL structure
nexpaq 0:6c56fb4bc5f0 45 */
nexpaq 0:6c56fb4bc5f0 46 typedef struct spi_s spi_t;
nexpaq 0:6c56fb4bc5f0 47
nexpaq 0:6c56fb4bc5f0 48 #endif
nexpaq 0:6c56fb4bc5f0 49
nexpaq 0:6c56fb4bc5f0 50 #ifdef __cplusplus
nexpaq 0:6c56fb4bc5f0 51 extern "C" {
nexpaq 0:6c56fb4bc5f0 52 #endif
nexpaq 0:6c56fb4bc5f0 53
nexpaq 0:6c56fb4bc5f0 54 /**
nexpaq 0:6c56fb4bc5f0 55 * \defgroup hal_GeneralSPI SPI Configuration Functions
nexpaq 0:6c56fb4bc5f0 56 * @{
nexpaq 0:6c56fb4bc5f0 57 */
nexpaq 0:6c56fb4bc5f0 58
nexpaq 0:6c56fb4bc5f0 59 /** Initialize the SPI peripheral
nexpaq 0:6c56fb4bc5f0 60 *
nexpaq 0:6c56fb4bc5f0 61 * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
nexpaq 0:6c56fb4bc5f0 62 * @param[out] obj The SPI object to initialize
nexpaq 0:6c56fb4bc5f0 63 * @param[in] mosi The pin to use for MOSI
nexpaq 0:6c56fb4bc5f0 64 * @param[in] miso The pin to use for MISO
nexpaq 0:6c56fb4bc5f0 65 * @param[in] sclk The pin to use for SCLK
nexpaq 0:6c56fb4bc5f0 66 * @param[in] ssel The pin to use for SSEL
nexpaq 0:6c56fb4bc5f0 67 */
nexpaq 0:6c56fb4bc5f0 68 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
nexpaq 0:6c56fb4bc5f0 69
nexpaq 0:6c56fb4bc5f0 70 /** Release a SPI object
nexpaq 0:6c56fb4bc5f0 71 *
nexpaq 0:6c56fb4bc5f0 72 * TODO: spi_free is currently unimplemented
nexpaq 0:6c56fb4bc5f0 73 * This will require reference counting at the C++ level to be safe
nexpaq 0:6c56fb4bc5f0 74 *
nexpaq 0:6c56fb4bc5f0 75 * Return the pins owned by the SPI object to their reset state
nexpaq 0:6c56fb4bc5f0 76 * Disable the SPI peripheral
nexpaq 0:6c56fb4bc5f0 77 * Disable the SPI clock
nexpaq 0:6c56fb4bc5f0 78 * @param[in] obj The SPI object to deinitialize
nexpaq 0:6c56fb4bc5f0 79 */
nexpaq 0:6c56fb4bc5f0 80 void spi_free(spi_t *obj);
nexpaq 0:6c56fb4bc5f0 81
nexpaq 0:6c56fb4bc5f0 82 /** Configure the SPI format
nexpaq 0:6c56fb4bc5f0 83 *
nexpaq 0:6c56fb4bc5f0 84 * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode.
nexpaq 0:6c56fb4bc5f0 85 * The default bit order is MSB.
nexpaq 0:6c56fb4bc5f0 86 * @param[in,out] obj The SPI object to configure
nexpaq 0:6c56fb4bc5f0 87 * @param[in] bits The number of bits per frame
nexpaq 0:6c56fb4bc5f0 88 * @param[in] mode The SPI mode (clock polarity, phase, and shift direction)
nexpaq 0:6c56fb4bc5f0 89 * @param[in] slave Zero for master mode or non-zero for slave mode
nexpaq 0:6c56fb4bc5f0 90 */
nexpaq 0:6c56fb4bc5f0 91 void spi_format(spi_t *obj, int bits, int mode, int slave);
nexpaq 0:6c56fb4bc5f0 92
nexpaq 0:6c56fb4bc5f0 93 /** Set the SPI baud rate
nexpaq 0:6c56fb4bc5f0 94 *
nexpaq 0:6c56fb4bc5f0 95 * Actual frequency may differ from the desired frequency due to available dividers and bus clock
nexpaq 0:6c56fb4bc5f0 96 * Configures the SPI peripheral's baud rate
nexpaq 0:6c56fb4bc5f0 97 * @param[in,out] obj The SPI object to configure
nexpaq 0:6c56fb4bc5f0 98 * @param[in] hz The baud rate in Hz
nexpaq 0:6c56fb4bc5f0 99 */
nexpaq 0:6c56fb4bc5f0 100 void spi_frequency(spi_t *obj, int hz);
nexpaq 0:6c56fb4bc5f0 101
nexpaq 0:6c56fb4bc5f0 102 /**@}*/
nexpaq 0:6c56fb4bc5f0 103 /**
nexpaq 0:6c56fb4bc5f0 104 * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
nexpaq 0:6c56fb4bc5f0 105 * @{
nexpaq 0:6c56fb4bc5f0 106 */
nexpaq 0:6c56fb4bc5f0 107
nexpaq 0:6c56fb4bc5f0 108 /** Write a byte out in master mode and receive a value
nexpaq 0:6c56fb4bc5f0 109 *
nexpaq 0:6c56fb4bc5f0 110 * @param[in] obj The SPI peripheral to use for sending
nexpaq 0:6c56fb4bc5f0 111 * @param[in] value The value to send
nexpaq 0:6c56fb4bc5f0 112 * @return Returns the value received during send
nexpaq 0:6c56fb4bc5f0 113 */
nexpaq 0:6c56fb4bc5f0 114 int spi_master_write(spi_t *obj, int value);
nexpaq 0:6c56fb4bc5f0 115
nexpaq 0:6c56fb4bc5f0 116 /** Check if a value is available to read
nexpaq 0:6c56fb4bc5f0 117 *
nexpaq 0:6c56fb4bc5f0 118 * @param[in] obj The SPI peripheral to check
nexpaq 0:6c56fb4bc5f0 119 * @return non-zero if a value is available
nexpaq 0:6c56fb4bc5f0 120 */
nexpaq 0:6c56fb4bc5f0 121 int spi_slave_receive(spi_t *obj);
nexpaq 0:6c56fb4bc5f0 122
nexpaq 0:6c56fb4bc5f0 123 /** Get a received value out of the SPI receive buffer in slave mode
nexpaq 0:6c56fb4bc5f0 124 *
nexpaq 0:6c56fb4bc5f0 125 * Blocks until a value is available
nexpaq 0:6c56fb4bc5f0 126 * @param[in] obj The SPI peripheral to read
nexpaq 0:6c56fb4bc5f0 127 * @return The value received
nexpaq 0:6c56fb4bc5f0 128 */
nexpaq 0:6c56fb4bc5f0 129 int spi_slave_read(spi_t *obj);
nexpaq 0:6c56fb4bc5f0 130
nexpaq 0:6c56fb4bc5f0 131 /** Write a value to the SPI peripheral in slave mode
nexpaq 0:6c56fb4bc5f0 132 *
nexpaq 0:6c56fb4bc5f0 133 * Blocks until the SPI peripheral can be written to
nexpaq 0:6c56fb4bc5f0 134 * @param[in] obj The SPI peripheral to write
nexpaq 0:6c56fb4bc5f0 135 * @param[in] value The value to write
nexpaq 0:6c56fb4bc5f0 136 */
nexpaq 0:6c56fb4bc5f0 137 void spi_slave_write(spi_t *obj, int value);
nexpaq 0:6c56fb4bc5f0 138
nexpaq 0:6c56fb4bc5f0 139 /** Checks if the specified SPI peripheral is in use
nexpaq 0:6c56fb4bc5f0 140 *
nexpaq 0:6c56fb4bc5f0 141 * @param[in] obj The SPI peripheral to check
nexpaq 0:6c56fb4bc5f0 142 * @return non-zero if the peripheral is currently transmitting
nexpaq 0:6c56fb4bc5f0 143 */
nexpaq 0:6c56fb4bc5f0 144 int spi_busy(spi_t *obj);
nexpaq 0:6c56fb4bc5f0 145
nexpaq 0:6c56fb4bc5f0 146 /** Get the module number
nexpaq 0:6c56fb4bc5f0 147 *
nexpaq 0:6c56fb4bc5f0 148 * @param[in] obj The SPI peripheral to check
nexpaq 0:6c56fb4bc5f0 149 * @return The module number
nexpaq 0:6c56fb4bc5f0 150 */
nexpaq 0:6c56fb4bc5f0 151 uint8_t spi_get_module(spi_t *obj);
nexpaq 0:6c56fb4bc5f0 152
nexpaq 0:6c56fb4bc5f0 153 /**@}*/
nexpaq 0:6c56fb4bc5f0 154
nexpaq 0:6c56fb4bc5f0 155 #if DEVICE_SPI_ASYNCH
nexpaq 0:6c56fb4bc5f0 156 /**
nexpaq 0:6c56fb4bc5f0 157 * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
nexpaq 0:6c56fb4bc5f0 158 * @{
nexpaq 0:6c56fb4bc5f0 159 */
nexpaq 0:6c56fb4bc5f0 160
nexpaq 0:6c56fb4bc5f0 161 /** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
nexpaq 0:6c56fb4bc5f0 162 *
nexpaq 0:6c56fb4bc5f0 163 * @param[in] obj The SPI object that holds the transfer information
nexpaq 0:6c56fb4bc5f0 164 * @param[in] tx The transmit buffer
nexpaq 0:6c56fb4bc5f0 165 * @param[in] tx_length The number of bytes to transmit
nexpaq 0:6c56fb4bc5f0 166 * @param[in] rx The receive buffer
nexpaq 0:6c56fb4bc5f0 167 * @param[in] rx_length The number of bytes to receive
nexpaq 0:6c56fb4bc5f0 168 * @param[in] bit_width The bit width of buffer words
nexpaq 0:6c56fb4bc5f0 169 * @param[in] event The logical OR of events to be registered
nexpaq 0:6c56fb4bc5f0 170 * @param[in] handler SPI interrupt handler
nexpaq 0:6c56fb4bc5f0 171 * @param[in] hint A suggestion for how to use DMA with this transfer
nexpaq 0:6c56fb4bc5f0 172 */
nexpaq 0:6c56fb4bc5f0 173 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint);
nexpaq 0:6c56fb4bc5f0 174
nexpaq 0:6c56fb4bc5f0 175 /** The asynchronous IRQ handler
nexpaq 0:6c56fb4bc5f0 176 *
nexpaq 0:6c56fb4bc5f0 177 * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
nexpaq 0:6c56fb4bc5f0 178 * conditions, such as buffer overflows or transfer complete.
nexpaq 0:6c56fb4bc5f0 179 * @param[in] obj The SPI object that holds the transfer information
nexpaq 0:6c56fb4bc5f0 180 * @return Event flags if a transfer termination condition was met; otherwise 0.
nexpaq 0:6c56fb4bc5f0 181 */
nexpaq 0:6c56fb4bc5f0 182 uint32_t spi_irq_handler_asynch(spi_t *obj);
nexpaq 0:6c56fb4bc5f0 183
nexpaq 0:6c56fb4bc5f0 184 /** Attempts to determine if the SPI peripheral is already in use
nexpaq 0:6c56fb4bc5f0 185 *
nexpaq 0:6c56fb4bc5f0 186 * If a temporary DMA channel has been allocated, peripheral is in use.
nexpaq 0:6c56fb4bc5f0 187 * If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA
nexpaq 0:6c56fb4bc5f0 188 * channel were allocated.
nexpaq 0:6c56fb4bc5f0 189 * If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check
nexpaq 0:6c56fb4bc5f0 190 * if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if
nexpaq 0:6c56fb4bc5f0 191 * there are any bytes in the FIFOs.
nexpaq 0:6c56fb4bc5f0 192 * @param[in] obj The SPI object to check for activity
nexpaq 0:6c56fb4bc5f0 193 * @return Non-zero if the SPI port is active or zero if it is not.
nexpaq 0:6c56fb4bc5f0 194 */
nexpaq 0:6c56fb4bc5f0 195 uint8_t spi_active(spi_t *obj);
nexpaq 0:6c56fb4bc5f0 196
nexpaq 0:6c56fb4bc5f0 197 /** Abort an SPI transfer
nexpaq 0:6c56fb4bc5f0 198 *
nexpaq 0:6c56fb4bc5f0 199 * @param obj The SPI peripheral to stop
nexpaq 0:6c56fb4bc5f0 200 */
nexpaq 0:6c56fb4bc5f0 201 void spi_abort_asynch(spi_t *obj);
nexpaq 0:6c56fb4bc5f0 202
nexpaq 0:6c56fb4bc5f0 203
nexpaq 0:6c56fb4bc5f0 204 #endif
nexpaq 0:6c56fb4bc5f0 205
nexpaq 0:6c56fb4bc5f0 206 /**@}*/
nexpaq 0:6c56fb4bc5f0 207
nexpaq 0:6c56fb4bc5f0 208 #ifdef __cplusplus
nexpaq 0:6c56fb4bc5f0 209 }
nexpaq 0:6c56fb4bc5f0 210 #endif // __cplusplus
nexpaq 0:6c56fb4bc5f0 211
nexpaq 0:6c56fb4bc5f0 212 #endif // SPI_DEVICE
nexpaq 0:6c56fb4bc5f0 213
nexpaq 0:6c56fb4bc5f0 214 #endif // MBED_SPI_API_H