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targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_eth.c@70:b3a5af880266, 2016-02-23 (annotated)

Committer:
neurofun
Date:
Tue Feb 23 21:59:35 2016 +0000
Revision:
70:b3a5af880266
Parent:
19:112740acecfa 
Edited DAC routines to allow for the simultaneous use of three channels from two DACs as seen on the STM32F334R8 and STM32F303K8. Edited ADC routines to allow for the simultaneous use of more than one ADC.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f4xx_hal_eth.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
mbed_official 19:112740acecfa 5 * @version V1.4.1
mbed_official 19:112740acecfa 6 * @date 09-October-2015
bogdanm 0:9b334a45a8ff 7 * @brief ETH HAL module driver.
bogdanm 0:9b334a45a8ff 8 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 9 * functionalities of the Ethernet (ETH) peripheral:
bogdanm 0:9b334a45a8ff 10 * + Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 11 * + IO operation functions
bogdanm 0:9b334a45a8ff 12 * + Peripheral Control functions
bogdanm 0:9b334a45a8ff 13 * + Peripheral State and Errors functions
bogdanm 0:9b334a45a8ff 14 *
bogdanm 0:9b334a45a8ff 15 @verbatim
bogdanm 0:9b334a45a8ff 16 ==============================================================================
bogdanm 0:9b334a45a8ff 17 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 18 ==============================================================================
bogdanm 0:9b334a45a8ff 19 [..]
bogdanm 0:9b334a45a8ff 20 (#)Declare a ETH_HandleTypeDef handle structure, for example:
bogdanm 0:9b334a45a8ff 21 ETH_HandleTypeDef heth;
bogdanm 0:9b334a45a8ff 22
bogdanm 0:9b334a45a8ff 23 (#)Fill parameters of Init structure in heth handle
bogdanm 0:9b334a45a8ff 24
bogdanm 0:9b334a45a8ff 25 (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
bogdanm 0:9b334a45a8ff 26
bogdanm 0:9b334a45a8ff 27 (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
bogdanm 0:9b334a45a8ff 28 (##) Enable the Ethernet interface clock using
bogdanm 0:9b334a45a8ff 29 (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 30 (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 31 (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 32
bogdanm 0:9b334a45a8ff 33 (##) Initialize the related GPIO clocks
bogdanm 0:9b334a45a8ff 34 (##) Configure Ethernet pin-out
bogdanm 0:9b334a45a8ff 35 (##) Configure Ethernet NVIC interrupt (IT mode)
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37 (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
bogdanm 0:9b334a45a8ff 38 (##) HAL_ETH_DMATxDescListInit(); for Transmission process
bogdanm 0:9b334a45a8ff 39 (##) HAL_ETH_DMARxDescListInit(); for Reception process
bogdanm 0:9b334a45a8ff 40
bogdanm 0:9b334a45a8ff 41 (#)Enable MAC and DMA transmission and reception:
bogdanm 0:9b334a45a8ff 42 (##) HAL_ETH_Start();
bogdanm 0:9b334a45a8ff 43
bogdanm 0:9b334a45a8ff 44 (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
bogdanm 0:9b334a45a8ff 45 the frame to MAC TX FIFO:
bogdanm 0:9b334a45a8ff 46 (##) HAL_ETH_TransmitFrame();
bogdanm 0:9b334a45a8ff 47
bogdanm 0:9b334a45a8ff 48 (#)Poll for a received frame in ETH RX DMA Descriptors and get received
bogdanm 0:9b334a45a8ff 49 frame parameters
bogdanm 0:9b334a45a8ff 50 (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
bogdanm 0:9b334a45a8ff 51
bogdanm 0:9b334a45a8ff 52 (#) Get a received frame when an ETH RX interrupt occurs:
bogdanm 0:9b334a45a8ff 53 (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
bogdanm 0:9b334a45a8ff 54
bogdanm 0:9b334a45a8ff 55 (#) Communicate with external PHY device:
bogdanm 0:9b334a45a8ff 56 (##) Read a specific register from the PHY
bogdanm 0:9b334a45a8ff 57 HAL_ETH_ReadPHYRegister();
bogdanm 0:9b334a45a8ff 58 (##) Write data to a specific RHY register:
bogdanm 0:9b334a45a8ff 59 HAL_ETH_WritePHYRegister();
bogdanm 0:9b334a45a8ff 60
bogdanm 0:9b334a45a8ff 61 (#) Configure the Ethernet MAC after ETH peripheral initialization
bogdanm 0:9b334a45a8ff 62 HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
bogdanm 0:9b334a45a8ff 63
bogdanm 0:9b334a45a8ff 64 (#) Configure the Ethernet DMA after ETH peripheral initialization
bogdanm 0:9b334a45a8ff 65 HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
bogdanm 0:9b334a45a8ff 66
bogdanm 0:9b334a45a8ff 67 -@- The PTP protocol and the DMA descriptors ring mode are not supported
bogdanm 0:9b334a45a8ff 68 in this driver
bogdanm 0:9b334a45a8ff 69
bogdanm 0:9b334a45a8ff 70 @endverbatim
bogdanm 0:9b334a45a8ff 71 ******************************************************************************
bogdanm 0:9b334a45a8ff 72 * @attention
bogdanm 0:9b334a45a8ff 73 *
bogdanm 0:9b334a45a8ff 74 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 75 *
bogdanm 0:9b334a45a8ff 76 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 77 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 78 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 79 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 80 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 81 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 82 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 83 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 84 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 85 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 86 *
bogdanm 0:9b334a45a8ff 87 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 88 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 89 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 90 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 91 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 92 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 93 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 94 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 95 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 96 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 97 *
bogdanm 0:9b334a45a8ff 98 ******************************************************************************
bogdanm 0:9b334a45a8ff 99 */
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 102 #include "stm32f4xx_hal.h"
bogdanm 0:9b334a45a8ff 103
bogdanm 0:9b334a45a8ff 104 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 0:9b334a45a8ff 105 * @{
bogdanm 0:9b334a45a8ff 106 */
bogdanm 0:9b334a45a8ff 107
bogdanm 0:9b334a45a8ff 108 /** @defgroup ETH ETH
bogdanm 0:9b334a45a8ff 109 * @brief ETH HAL module driver
bogdanm 0:9b334a45a8ff 110 * @{
bogdanm 0:9b334a45a8ff 111 */
bogdanm 0:9b334a45a8ff 112
bogdanm 0:9b334a45a8ff 113 #ifdef HAL_ETH_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 114
mbed_official 19:112740acecfa 115 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
mbed_official 19:112740acecfa 116 defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
bogdanm 0:9b334a45a8ff 117
bogdanm 0:9b334a45a8ff 118 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 119 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 120 /** @defgroup ETH_Private_Constants ETH Private Constants
bogdanm 0:9b334a45a8ff 121 * @{
bogdanm 0:9b334a45a8ff 122 */
bogdanm 0:9b334a45a8ff 123 #define LINKED_STATE_TIMEOUT_VALUE ((uint32_t)2000) /* 2000 ms */
bogdanm 0:9b334a45a8ff 124 #define AUTONEGO_COMPLETED_TIMEOUT_VALUE ((uint32_t)1000) /* 1000 ms */
bogdanm 0:9b334a45a8ff 125
bogdanm 0:9b334a45a8ff 126 /**
bogdanm 0:9b334a45a8ff 127 * @}
bogdanm 0:9b334a45a8ff 128 */
bogdanm 0:9b334a45a8ff 129 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 130 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 131 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 132 /** @defgroup ETH_Private_Functions ETH Private Functions
bogdanm 0:9b334a45a8ff 133 * @{
bogdanm 0:9b334a45a8ff 134 */
bogdanm 0:9b334a45a8ff 135 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
bogdanm 0:9b334a45a8ff 136 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
bogdanm 0:9b334a45a8ff 137 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
bogdanm 0:9b334a45a8ff 138 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
bogdanm 0:9b334a45a8ff 139 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
bogdanm 0:9b334a45a8ff 140 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
bogdanm 0:9b334a45a8ff 141 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
bogdanm 0:9b334a45a8ff 142 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
bogdanm 0:9b334a45a8ff 143 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
bogdanm 0:9b334a45a8ff 144 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
bogdanm 0:9b334a45a8ff 145 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
bogdanm 0:9b334a45a8ff 146
bogdanm 0:9b334a45a8ff 147 /**
bogdanm 0:9b334a45a8ff 148 * @}
bogdanm 0:9b334a45a8ff 149 */
bogdanm 0:9b334a45a8ff 150 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 151
bogdanm 0:9b334a45a8ff 152 /** @defgroup ETH_Exported_Functions ETH Exported Functions
bogdanm 0:9b334a45a8ff 153 * @{
bogdanm 0:9b334a45a8ff 154 */
bogdanm 0:9b334a45a8ff 155
bogdanm 0:9b334a45a8ff 156 /** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 157 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 158 *
bogdanm 0:9b334a45a8ff 159 @verbatim
bogdanm 0:9b334a45a8ff 160 ===============================================================================
bogdanm 0:9b334a45a8ff 161 ##### Initialization and de-initialization functions #####
bogdanm 0:9b334a45a8ff 162 ===============================================================================
bogdanm 0:9b334a45a8ff 163 [..] This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 164 (+) Initialize and configure the Ethernet peripheral
bogdanm 0:9b334a45a8ff 165 (+) De-initialize the Ethernet peripheral
bogdanm 0:9b334a45a8ff 166
bogdanm 0:9b334a45a8ff 167 @endverbatim
bogdanm 0:9b334a45a8ff 168 * @{
bogdanm 0:9b334a45a8ff 169 */
bogdanm 0:9b334a45a8ff 170
bogdanm 0:9b334a45a8ff 171 /**
bogdanm 0:9b334a45a8ff 172 * @brief Initializes the Ethernet MAC and DMA according to default
bogdanm 0:9b334a45a8ff 173 * parameters.
bogdanm 0:9b334a45a8ff 174 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 175 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 176 * @retval HAL status
bogdanm 0:9b334a45a8ff 177 */
bogdanm 0:9b334a45a8ff 178 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 179 {
bogdanm 0:9b334a45a8ff 180 uint32_t tmpreg1 = 0, phyreg = 0;
bogdanm 0:9b334a45a8ff 181 uint32_t hclk = 60000000;
bogdanm 0:9b334a45a8ff 182 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 183 uint32_t err = ETH_SUCCESS;
bogdanm 0:9b334a45a8ff 184
bogdanm 0:9b334a45a8ff 185 /* Check the ETH peripheral state */
bogdanm 0:9b334a45a8ff 186 if(heth == NULL)
bogdanm 0:9b334a45a8ff 187 {
bogdanm 0:9b334a45a8ff 188 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 189 }
bogdanm 0:9b334a45a8ff 190
bogdanm 0:9b334a45a8ff 191 /* Check parameters */
bogdanm 0:9b334a45a8ff 192 assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
bogdanm 0:9b334a45a8ff 193 assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
bogdanm 0:9b334a45a8ff 194 assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
bogdanm 0:9b334a45a8ff 195 assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
bogdanm 0:9b334a45a8ff 196
bogdanm 0:9b334a45a8ff 197 if(heth->State == HAL_ETH_STATE_RESET)
bogdanm 0:9b334a45a8ff 198 {
bogdanm 0:9b334a45a8ff 199 /* Allocate lock resource and initialize it */
bogdanm 0:9b334a45a8ff 200 heth->Lock = HAL_UNLOCKED;
bogdanm 0:9b334a45a8ff 201 /* Init the low level hardware : GPIO, CLOCK, NVIC. */
bogdanm 0:9b334a45a8ff 202 HAL_ETH_MspInit(heth);
bogdanm 0:9b334a45a8ff 203 }
bogdanm 0:9b334a45a8ff 204
bogdanm 0:9b334a45a8ff 205 /* Enable SYSCFG Clock */
bogdanm 0:9b334a45a8ff 206 __HAL_RCC_SYSCFG_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 207
bogdanm 0:9b334a45a8ff 208 /* Select MII or RMII Mode*/
bogdanm 0:9b334a45a8ff 209 SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
bogdanm 0:9b334a45a8ff 210 SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
bogdanm 0:9b334a45a8ff 211
bogdanm 0:9b334a45a8ff 212 /* Ethernet Software reset */
bogdanm 0:9b334a45a8ff 213 /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
bogdanm 0:9b334a45a8ff 214 /* After reset all the registers holds their respective reset values */
bogdanm 0:9b334a45a8ff 215 (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
bogdanm 0:9b334a45a8ff 216
bogdanm 0:9b334a45a8ff 217 /* Wait for software reset */
bogdanm 0:9b334a45a8ff 218 while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
bogdanm 0:9b334a45a8ff 219 {
bogdanm 0:9b334a45a8ff 220 }
bogdanm 0:9b334a45a8ff 221
bogdanm 0:9b334a45a8ff 222 /*-------------------------------- MAC Initialization ----------------------*/
bogdanm 0:9b334a45a8ff 223 /* Get the ETHERNET MACMIIAR value */
bogdanm 0:9b334a45a8ff 224 tmpreg1 = (heth->Instance)->MACMIIAR;
bogdanm 0:9b334a45a8ff 225 /* Clear CSR Clock Range CR[2:0] bits */
bogdanm 0:9b334a45a8ff 226 tmpreg1 &= ETH_MACMIIAR_CR_MASK;
bogdanm 0:9b334a45a8ff 227
bogdanm 0:9b334a45a8ff 228 /* Get hclk frequency value */
bogdanm 0:9b334a45a8ff 229 hclk = HAL_RCC_GetHCLKFreq();
bogdanm 0:9b334a45a8ff 230
bogdanm 0:9b334a45a8ff 231 /* Set CR bits depending on hclk value */
bogdanm 0:9b334a45a8ff 232 if((hclk >= 20000000)&&(hclk < 35000000))
bogdanm 0:9b334a45a8ff 233 {
bogdanm 0:9b334a45a8ff 234 /* CSR Clock Range between 20-35 MHz */
bogdanm 0:9b334a45a8ff 235 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div16;
bogdanm 0:9b334a45a8ff 236 }
bogdanm 0:9b334a45a8ff 237 else if((hclk >= 35000000)&&(hclk < 60000000))
bogdanm 0:9b334a45a8ff 238 {
bogdanm 0:9b334a45a8ff 239 /* CSR Clock Range between 35-60 MHz */
bogdanm 0:9b334a45a8ff 240 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div26;
bogdanm 0:9b334a45a8ff 241 }
bogdanm 0:9b334a45a8ff 242 else if((hclk >= 60000000)&&(hclk < 100000000))
bogdanm 0:9b334a45a8ff 243 {
bogdanm 0:9b334a45a8ff 244 /* CSR Clock Range between 60-100 MHz */
bogdanm 0:9b334a45a8ff 245 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div42;
bogdanm 0:9b334a45a8ff 246 }
bogdanm 0:9b334a45a8ff 247 else if((hclk >= 100000000)&&(hclk < 150000000))
bogdanm 0:9b334a45a8ff 248 {
bogdanm 0:9b334a45a8ff 249 /* CSR Clock Range between 100-150 MHz */
bogdanm 0:9b334a45a8ff 250 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div62;
bogdanm 0:9b334a45a8ff 251 }
bogdanm 0:9b334a45a8ff 252 else /* ((hclk >= 150000000)&&(hclk <= 168000000)) */
bogdanm 0:9b334a45a8ff 253 {
bogdanm 0:9b334a45a8ff 254 /* CSR Clock Range between 150-168 MHz */
bogdanm 0:9b334a45a8ff 255 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div102;
bogdanm 0:9b334a45a8ff 256 }
bogdanm 0:9b334a45a8ff 257
bogdanm 0:9b334a45a8ff 258 /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
bogdanm 0:9b334a45a8ff 259 (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1;
bogdanm 0:9b334a45a8ff 260
bogdanm 0:9b334a45a8ff 261 /*-------------------- PHY initialization and configuration ----------------*/
bogdanm 0:9b334a45a8ff 262 /* Put the PHY in reset mode */
bogdanm 0:9b334a45a8ff 263 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
bogdanm 0:9b334a45a8ff 264 {
bogdanm 0:9b334a45a8ff 265 /* In case of write timeout */
bogdanm 0:9b334a45a8ff 266 err = ETH_ERROR;
bogdanm 0:9b334a45a8ff 267
bogdanm 0:9b334a45a8ff 268 /* Config MAC and DMA */
bogdanm 0:9b334a45a8ff 269 ETH_MACDMAConfig(heth, err);
bogdanm 0:9b334a45a8ff 270
bogdanm 0:9b334a45a8ff 271 /* Set the ETH peripheral state to READY */
bogdanm 0:9b334a45a8ff 272 heth->State = HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 273
bogdanm 0:9b334a45a8ff 274 /* Return HAL_ERROR */
bogdanm 0:9b334a45a8ff 275 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 276 }
bogdanm 0:9b334a45a8ff 277
bogdanm 0:9b334a45a8ff 278 /* Delay to assure PHY reset */
bogdanm 0:9b334a45a8ff 279 HAL_Delay(PHY_RESET_DELAY);
bogdanm 0:9b334a45a8ff 280
bogdanm 0:9b334a45a8ff 281 if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
bogdanm 0:9b334a45a8ff 282 {
bogdanm 0:9b334a45a8ff 283 /* Get tick */
bogdanm 0:9b334a45a8ff 284 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 285
bogdanm 0:9b334a45a8ff 286 /* We wait for linked status */
bogdanm 0:9b334a45a8ff 287 do
bogdanm 0:9b334a45a8ff 288 {
bogdanm 0:9b334a45a8ff 289 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
bogdanm 0:9b334a45a8ff 290
bogdanm 0:9b334a45a8ff 291 /* Check for the Timeout */
bogdanm 0:9b334a45a8ff 292 if((HAL_GetTick() - tickstart ) > LINKED_STATE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 293 {
bogdanm 0:9b334a45a8ff 294 /* In case of write timeout */
bogdanm 0:9b334a45a8ff 295 err = ETH_ERROR;
bogdanm 0:9b334a45a8ff 296
bogdanm 0:9b334a45a8ff 297 /* Config MAC and DMA */
bogdanm 0:9b334a45a8ff 298 ETH_MACDMAConfig(heth, err);
bogdanm 0:9b334a45a8ff 299
bogdanm 0:9b334a45a8ff 300 heth->State= HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 301
bogdanm 0:9b334a45a8ff 302 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 303 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 304
bogdanm 0:9b334a45a8ff 305 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 306 }
bogdanm 0:9b334a45a8ff 307 } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
bogdanm 0:9b334a45a8ff 308
bogdanm 0:9b334a45a8ff 309
bogdanm 0:9b334a45a8ff 310 /* Enable Auto-Negotiation */
bogdanm 0:9b334a45a8ff 311 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
bogdanm 0:9b334a45a8ff 312 {
bogdanm 0:9b334a45a8ff 313 /* In case of write timeout */
bogdanm 0:9b334a45a8ff 314 err = ETH_ERROR;
bogdanm 0:9b334a45a8ff 315
bogdanm 0:9b334a45a8ff 316 /* Config MAC and DMA */
bogdanm 0:9b334a45a8ff 317 ETH_MACDMAConfig(heth, err);
bogdanm 0:9b334a45a8ff 318
bogdanm 0:9b334a45a8ff 319 /* Set the ETH peripheral state to READY */
bogdanm 0:9b334a45a8ff 320 heth->State = HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 321
bogdanm 0:9b334a45a8ff 322 /* Return HAL_ERROR */
bogdanm 0:9b334a45a8ff 323 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 324 }
bogdanm 0:9b334a45a8ff 325
bogdanm 0:9b334a45a8ff 326 /* Get tick */
bogdanm 0:9b334a45a8ff 327 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 328
bogdanm 0:9b334a45a8ff 329 /* Wait until the auto-negotiation will be completed */
bogdanm 0:9b334a45a8ff 330 do
bogdanm 0:9b334a45a8ff 331 {
bogdanm 0:9b334a45a8ff 332 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
bogdanm 0:9b334a45a8ff 333
bogdanm 0:9b334a45a8ff 334 /* Check for the Timeout */
bogdanm 0:9b334a45a8ff 335 if((HAL_GetTick() - tickstart ) > AUTONEGO_COMPLETED_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 336 {
bogdanm 0:9b334a45a8ff 337 /* In case of write timeout */
bogdanm 0:9b334a45a8ff 338 err = ETH_ERROR;
bogdanm 0:9b334a45a8ff 339
bogdanm 0:9b334a45a8ff 340 /* Config MAC and DMA */
bogdanm 0:9b334a45a8ff 341 ETH_MACDMAConfig(heth, err);
bogdanm 0:9b334a45a8ff 342
bogdanm 0:9b334a45a8ff 343 heth->State= HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 344
bogdanm 0:9b334a45a8ff 345 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 346 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 347
bogdanm 0:9b334a45a8ff 348 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 349 }
bogdanm 0:9b334a45a8ff 350
bogdanm 0:9b334a45a8ff 351 } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
bogdanm 0:9b334a45a8ff 352
bogdanm 0:9b334a45a8ff 353 /* Read the result of the auto-negotiation */
bogdanm 0:9b334a45a8ff 354 if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
bogdanm 0:9b334a45a8ff 355 {
bogdanm 0:9b334a45a8ff 356 /* In case of write timeout */
bogdanm 0:9b334a45a8ff 357 err = ETH_ERROR;
bogdanm 0:9b334a45a8ff 358
bogdanm 0:9b334a45a8ff 359 /* Config MAC and DMA */
bogdanm 0:9b334a45a8ff 360 ETH_MACDMAConfig(heth, err);
bogdanm 0:9b334a45a8ff 361
bogdanm 0:9b334a45a8ff 362 /* Set the ETH peripheral state to READY */
bogdanm 0:9b334a45a8ff 363 heth->State = HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 364
bogdanm 0:9b334a45a8ff 365 /* Return HAL_ERROR */
bogdanm 0:9b334a45a8ff 366 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 367 }
bogdanm 0:9b334a45a8ff 368
bogdanm 0:9b334a45a8ff 369 /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
bogdanm 0:9b334a45a8ff 370 if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
bogdanm 0:9b334a45a8ff 371 {
bogdanm 0:9b334a45a8ff 372 /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
bogdanm 0:9b334a45a8ff 373 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
bogdanm 0:9b334a45a8ff 374 }
bogdanm 0:9b334a45a8ff 375 else
bogdanm 0:9b334a45a8ff 376 {
bogdanm 0:9b334a45a8ff 377 /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
bogdanm 0:9b334a45a8ff 378 (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
bogdanm 0:9b334a45a8ff 379 }
bogdanm 0:9b334a45a8ff 380 /* Configure the MAC with the speed fixed by the auto-negotiation process */
bogdanm 0:9b334a45a8ff 381 if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
bogdanm 0:9b334a45a8ff 382 {
bogdanm 0:9b334a45a8ff 383 /* Set Ethernet speed to 10M following the auto-negotiation */
bogdanm 0:9b334a45a8ff 384 (heth->Init).Speed = ETH_SPEED_10M;
bogdanm 0:9b334a45a8ff 385 }
bogdanm 0:9b334a45a8ff 386 else
bogdanm 0:9b334a45a8ff 387 {
bogdanm 0:9b334a45a8ff 388 /* Set Ethernet speed to 100M following the auto-negotiation */
bogdanm 0:9b334a45a8ff 389 (heth->Init).Speed = ETH_SPEED_100M;
bogdanm 0:9b334a45a8ff 390 }
bogdanm 0:9b334a45a8ff 391 }
bogdanm 0:9b334a45a8ff 392 else /* AutoNegotiation Disable */
bogdanm 0:9b334a45a8ff 393 {
bogdanm 0:9b334a45a8ff 394 /* Check parameters */
bogdanm 0:9b334a45a8ff 395 assert_param(IS_ETH_SPEED(heth->Init.Speed));
bogdanm 0:9b334a45a8ff 396 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
bogdanm 0:9b334a45a8ff 397
bogdanm 0:9b334a45a8ff 398 /* Set MAC Speed and Duplex Mode */
bogdanm 0:9b334a45a8ff 399 if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |
bogdanm 0:9b334a45a8ff 400 (uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
bogdanm 0:9b334a45a8ff 401 {
bogdanm 0:9b334a45a8ff 402 /* In case of write timeout */
bogdanm 0:9b334a45a8ff 403 err = ETH_ERROR;
bogdanm 0:9b334a45a8ff 404
bogdanm 0:9b334a45a8ff 405 /* Config MAC and DMA */
bogdanm 0:9b334a45a8ff 406 ETH_MACDMAConfig(heth, err);
bogdanm 0:9b334a45a8ff 407
bogdanm 0:9b334a45a8ff 408 /* Set the ETH peripheral state to READY */
bogdanm 0:9b334a45a8ff 409 heth->State = HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 410
bogdanm 0:9b334a45a8ff 411 /* Return HAL_ERROR */
bogdanm 0:9b334a45a8ff 412 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 413 }
bogdanm 0:9b334a45a8ff 414
bogdanm 0:9b334a45a8ff 415 /* Delay to assure PHY configuration */
bogdanm 0:9b334a45a8ff 416 HAL_Delay(PHY_CONFIG_DELAY);
bogdanm 0:9b334a45a8ff 417 }
bogdanm 0:9b334a45a8ff 418
bogdanm 0:9b334a45a8ff 419 /* Config MAC and DMA */
bogdanm 0:9b334a45a8ff 420 ETH_MACDMAConfig(heth, err);
bogdanm 0:9b334a45a8ff 421
bogdanm 0:9b334a45a8ff 422 /* Set ETH HAL State to Ready */
bogdanm 0:9b334a45a8ff 423 heth->State= HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 424
bogdanm 0:9b334a45a8ff 425 /* Return function status */
bogdanm 0:9b334a45a8ff 426 return HAL_OK;
bogdanm 0:9b334a45a8ff 427 }
bogdanm 0:9b334a45a8ff 428
bogdanm 0:9b334a45a8ff 429 /**
bogdanm 0:9b334a45a8ff 430 * @brief De-Initializes the ETH peripheral.
bogdanm 0:9b334a45a8ff 431 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 432 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 433 * @retval HAL status
bogdanm 0:9b334a45a8ff 434 */
bogdanm 0:9b334a45a8ff 435 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 436 {
bogdanm 0:9b334a45a8ff 437 /* Set the ETH peripheral state to BUSY */
bogdanm 0:9b334a45a8ff 438 heth->State = HAL_ETH_STATE_BUSY;
bogdanm 0:9b334a45a8ff 439
bogdanm 0:9b334a45a8ff 440 /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
bogdanm 0:9b334a45a8ff 441 HAL_ETH_MspDeInit(heth);
bogdanm 0:9b334a45a8ff 442
bogdanm 0:9b334a45a8ff 443 /* Set ETH HAL state to Disabled */
bogdanm 0:9b334a45a8ff 444 heth->State= HAL_ETH_STATE_RESET;
bogdanm 0:9b334a45a8ff 445
bogdanm 0:9b334a45a8ff 446 /* Release Lock */
bogdanm 0:9b334a45a8ff 447 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 448
bogdanm 0:9b334a45a8ff 449 /* Return function status */
bogdanm 0:9b334a45a8ff 450 return HAL_OK;
bogdanm 0:9b334a45a8ff 451 }
bogdanm 0:9b334a45a8ff 452
bogdanm 0:9b334a45a8ff 453 /**
bogdanm 0:9b334a45a8ff 454 * @brief Initializes the DMA Tx descriptors in chain mode.
bogdanm 0:9b334a45a8ff 455 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 456 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 457 * @param DMATxDescTab: Pointer to the first Tx desc list
bogdanm 0:9b334a45a8ff 458 * @param TxBuff: Pointer to the first TxBuffer list
bogdanm 0:9b334a45a8ff 459 * @param TxBuffCount: Number of the used Tx desc in the list
bogdanm 0:9b334a45a8ff 460 * @retval HAL status
bogdanm 0:9b334a45a8ff 461 */
bogdanm 0:9b334a45a8ff 462 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
bogdanm 0:9b334a45a8ff 463 {
bogdanm 0:9b334a45a8ff 464 uint32_t i = 0;
bogdanm 0:9b334a45a8ff 465 ETH_DMADescTypeDef *dmatxdesc;
bogdanm 0:9b334a45a8ff 466
bogdanm 0:9b334a45a8ff 467 /* Process Locked */
bogdanm 0:9b334a45a8ff 468 __HAL_LOCK(heth);
bogdanm 0:9b334a45a8ff 469
bogdanm 0:9b334a45a8ff 470 /* Set the ETH peripheral state to BUSY */
bogdanm 0:9b334a45a8ff 471 heth->State = HAL_ETH_STATE_BUSY;
bogdanm 0:9b334a45a8ff 472
bogdanm 0:9b334a45a8ff 473 /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
bogdanm 0:9b334a45a8ff 474 heth->TxDesc = DMATxDescTab;
bogdanm 0:9b334a45a8ff 475
bogdanm 0:9b334a45a8ff 476 /* Fill each DMATxDesc descriptor with the right values */
bogdanm 0:9b334a45a8ff 477 for(i=0; i < TxBuffCount; i++)
bogdanm 0:9b334a45a8ff 478 {
bogdanm 0:9b334a45a8ff 479 /* Get the pointer on the ith member of the Tx Desc list */
bogdanm 0:9b334a45a8ff 480 dmatxdesc = DMATxDescTab + i;
bogdanm 0:9b334a45a8ff 481
bogdanm 0:9b334a45a8ff 482 /* Set Second Address Chained bit */
bogdanm 0:9b334a45a8ff 483 dmatxdesc->Status = ETH_DMATXDESC_TCH;
bogdanm 0:9b334a45a8ff 484
bogdanm 0:9b334a45a8ff 485 /* Set Buffer1 address pointer */
bogdanm 0:9b334a45a8ff 486 dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
bogdanm 0:9b334a45a8ff 487
bogdanm 0:9b334a45a8ff 488 if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
bogdanm 0:9b334a45a8ff 489 {
bogdanm 0:9b334a45a8ff 490 /* Set the DMA Tx descriptors checksum insertion */
bogdanm 0:9b334a45a8ff 491 dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
bogdanm 0:9b334a45a8ff 492 }
bogdanm 0:9b334a45a8ff 493
bogdanm 0:9b334a45a8ff 494 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
bogdanm 0:9b334a45a8ff 495 if(i < (TxBuffCount-1))
bogdanm 0:9b334a45a8ff 496 {
bogdanm 0:9b334a45a8ff 497 /* Set next descriptor address register with next descriptor base address */
bogdanm 0:9b334a45a8ff 498 dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
bogdanm 0:9b334a45a8ff 499 }
bogdanm 0:9b334a45a8ff 500 else
bogdanm 0:9b334a45a8ff 501 {
bogdanm 0:9b334a45a8ff 502 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
bogdanm 0:9b334a45a8ff 503 dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
bogdanm 0:9b334a45a8ff 504 }
bogdanm 0:9b334a45a8ff 505 }
bogdanm 0:9b334a45a8ff 506
bogdanm 0:9b334a45a8ff 507 /* Set Transmit Descriptor List Address Register */
bogdanm 0:9b334a45a8ff 508 (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
bogdanm 0:9b334a45a8ff 509
bogdanm 0:9b334a45a8ff 510 /* Set ETH HAL State to Ready */
bogdanm 0:9b334a45a8ff 511 heth->State= HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 512
bogdanm 0:9b334a45a8ff 513 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 514 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 515
bogdanm 0:9b334a45a8ff 516 /* Return function status */
bogdanm 0:9b334a45a8ff 517 return HAL_OK;
bogdanm 0:9b334a45a8ff 518 }
bogdanm 0:9b334a45a8ff 519
bogdanm 0:9b334a45a8ff 520 /**
bogdanm 0:9b334a45a8ff 521 * @brief Initializes the DMA Rx descriptors in chain mode.
bogdanm 0:9b334a45a8ff 522 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 523 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 524 * @param DMARxDescTab: Pointer to the first Rx desc list
bogdanm 0:9b334a45a8ff 525 * @param RxBuff: Pointer to the first RxBuffer list
bogdanm 0:9b334a45a8ff 526 * @param RxBuffCount: Number of the used Rx desc in the list
bogdanm 0:9b334a45a8ff 527 * @retval HAL status
bogdanm 0:9b334a45a8ff 528 */
bogdanm 0:9b334a45a8ff 529 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
bogdanm 0:9b334a45a8ff 530 {
bogdanm 0:9b334a45a8ff 531 uint32_t i = 0;
bogdanm 0:9b334a45a8ff 532 ETH_DMADescTypeDef *DMARxDesc;
bogdanm 0:9b334a45a8ff 533
bogdanm 0:9b334a45a8ff 534 /* Process Locked */
bogdanm 0:9b334a45a8ff 535 __HAL_LOCK(heth);
bogdanm 0:9b334a45a8ff 536
bogdanm 0:9b334a45a8ff 537 /* Set the ETH peripheral state to BUSY */
bogdanm 0:9b334a45a8ff 538 heth->State = HAL_ETH_STATE_BUSY;
bogdanm 0:9b334a45a8ff 539
bogdanm 0:9b334a45a8ff 540 /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
bogdanm 0:9b334a45a8ff 541 heth->RxDesc = DMARxDescTab;
bogdanm 0:9b334a45a8ff 542
bogdanm 0:9b334a45a8ff 543 /* Fill each DMARxDesc descriptor with the right values */
bogdanm 0:9b334a45a8ff 544 for(i=0; i < RxBuffCount; i++)
bogdanm 0:9b334a45a8ff 545 {
bogdanm 0:9b334a45a8ff 546 /* Get the pointer on the ith member of the Rx Desc list */
bogdanm 0:9b334a45a8ff 547 DMARxDesc = DMARxDescTab+i;
bogdanm 0:9b334a45a8ff 548
bogdanm 0:9b334a45a8ff 549 /* Set Own bit of the Rx descriptor Status */
bogdanm 0:9b334a45a8ff 550 DMARxDesc->Status = ETH_DMARXDESC_OWN;
bogdanm 0:9b334a45a8ff 551
bogdanm 0:9b334a45a8ff 552 /* Set Buffer1 size and Second Address Chained bit */
bogdanm 0:9b334a45a8ff 553 DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
bogdanm 0:9b334a45a8ff 554
bogdanm 0:9b334a45a8ff 555 /* Set Buffer1 address pointer */
bogdanm 0:9b334a45a8ff 556 DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
bogdanm 0:9b334a45a8ff 557
bogdanm 0:9b334a45a8ff 558 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
bogdanm 0:9b334a45a8ff 559 {
bogdanm 0:9b334a45a8ff 560 /* Enable Ethernet DMA Rx Descriptor interrupt */
bogdanm 0:9b334a45a8ff 561 DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
bogdanm 0:9b334a45a8ff 562 }
bogdanm 0:9b334a45a8ff 563
bogdanm 0:9b334a45a8ff 564 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
bogdanm 0:9b334a45a8ff 565 if(i < (RxBuffCount-1))
bogdanm 0:9b334a45a8ff 566 {
bogdanm 0:9b334a45a8ff 567 /* Set next descriptor address register with next descriptor base address */
bogdanm 0:9b334a45a8ff 568 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
bogdanm 0:9b334a45a8ff 569 }
bogdanm 0:9b334a45a8ff 570 else
bogdanm 0:9b334a45a8ff 571 {
bogdanm 0:9b334a45a8ff 572 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
bogdanm 0:9b334a45a8ff 573 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
bogdanm 0:9b334a45a8ff 574 }
bogdanm 0:9b334a45a8ff 575 }
bogdanm 0:9b334a45a8ff 576
bogdanm 0:9b334a45a8ff 577 /* Set Receive Descriptor List Address Register */
bogdanm 0:9b334a45a8ff 578 (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
bogdanm 0:9b334a45a8ff 579
bogdanm 0:9b334a45a8ff 580 /* Set ETH HAL State to Ready */
bogdanm 0:9b334a45a8ff 581 heth->State= HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 582
bogdanm 0:9b334a45a8ff 583 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 584 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 585
bogdanm 0:9b334a45a8ff 586 /* Return function status */
bogdanm 0:9b334a45a8ff 587 return HAL_OK;
bogdanm 0:9b334a45a8ff 588 }
bogdanm 0:9b334a45a8ff 589
bogdanm 0:9b334a45a8ff 590 /**
bogdanm 0:9b334a45a8ff 591 * @brief Initializes the ETH MSP.
bogdanm 0:9b334a45a8ff 592 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 593 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 594 * @retval None
bogdanm 0:9b334a45a8ff 595 */
bogdanm 0:9b334a45a8ff 596 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 597 {
bogdanm 0:9b334a45a8ff 598 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 599 the HAL_ETH_MspInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 600 */
bogdanm 0:9b334a45a8ff 601 }
bogdanm 0:9b334a45a8ff 602
bogdanm 0:9b334a45a8ff 603 /**
bogdanm 0:9b334a45a8ff 604 * @brief DeInitializes ETH MSP.
bogdanm 0:9b334a45a8ff 605 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 606 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 607 * @retval None
bogdanm 0:9b334a45a8ff 608 */
bogdanm 0:9b334a45a8ff 609 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 610 {
bogdanm 0:9b334a45a8ff 611 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 612 the HAL_ETH_MspDeInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 613 */
bogdanm 0:9b334a45a8ff 614 }
bogdanm 0:9b334a45a8ff 615
bogdanm 0:9b334a45a8ff 616 /**
bogdanm 0:9b334a45a8ff 617 * @}
bogdanm 0:9b334a45a8ff 618 */
bogdanm 0:9b334a45a8ff 619
bogdanm 0:9b334a45a8ff 620 /** @defgroup ETH_Exported_Functions_Group2 IO operation functions
bogdanm 0:9b334a45a8ff 621 * @brief Data transfers functions
bogdanm 0:9b334a45a8ff 622 *
bogdanm 0:9b334a45a8ff 623 @verbatim
bogdanm 0:9b334a45a8ff 624 ==============================================================================
bogdanm 0:9b334a45a8ff 625 ##### IO operation functions #####
bogdanm 0:9b334a45a8ff 626 ==============================================================================
bogdanm 0:9b334a45a8ff 627 [..] This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 628 (+) Transmit a frame
bogdanm 0:9b334a45a8ff 629 HAL_ETH_TransmitFrame();
bogdanm 0:9b334a45a8ff 630 (+) Receive a frame
bogdanm 0:9b334a45a8ff 631 HAL_ETH_GetReceivedFrame();
bogdanm 0:9b334a45a8ff 632 HAL_ETH_GetReceivedFrame_IT();
bogdanm 0:9b334a45a8ff 633 (+) Read from an External PHY register
bogdanm 0:9b334a45a8ff 634 HAL_ETH_ReadPHYRegister();
bogdanm 0:9b334a45a8ff 635 (+) Write to an External PHY register
bogdanm 0:9b334a45a8ff 636 HAL_ETH_WritePHYRegister();
bogdanm 0:9b334a45a8ff 637
bogdanm 0:9b334a45a8ff 638 @endverbatim
bogdanm 0:9b334a45a8ff 639
bogdanm 0:9b334a45a8ff 640 * @{
bogdanm 0:9b334a45a8ff 641 */
bogdanm 0:9b334a45a8ff 642
bogdanm 0:9b334a45a8ff 643 /**
bogdanm 0:9b334a45a8ff 644 * @brief Sends an Ethernet frame.
bogdanm 0:9b334a45a8ff 645 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 646 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 647 * @param FrameLength: Amount of data to be sent
bogdanm 0:9b334a45a8ff 648 * @retval HAL status
bogdanm 0:9b334a45a8ff 649 */
bogdanm 0:9b334a45a8ff 650 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
bogdanm 0:9b334a45a8ff 651 {
bogdanm 0:9b334a45a8ff 652 uint32_t bufcount = 0, size = 0, i = 0;
bogdanm 0:9b334a45a8ff 653
bogdanm 0:9b334a45a8ff 654 /* Process Locked */
bogdanm 0:9b334a45a8ff 655 __HAL_LOCK(heth);
bogdanm 0:9b334a45a8ff 656
bogdanm 0:9b334a45a8ff 657 /* Set the ETH peripheral state to BUSY */
bogdanm 0:9b334a45a8ff 658 heth->State = HAL_ETH_STATE_BUSY;
bogdanm 0:9b334a45a8ff 659
bogdanm 0:9b334a45a8ff 660 if (FrameLength == 0)
bogdanm 0:9b334a45a8ff 661 {
bogdanm 0:9b334a45a8ff 662 /* Set ETH HAL state to READY */
bogdanm 0:9b334a45a8ff 663 heth->State = HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 664
bogdanm 0:9b334a45a8ff 665 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 666 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 667
bogdanm 0:9b334a45a8ff 668 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 669 }
bogdanm 0:9b334a45a8ff 670
bogdanm 0:9b334a45a8ff 671 /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
bogdanm 0:9b334a45a8ff 672 if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
bogdanm 0:9b334a45a8ff 673 {
bogdanm 0:9b334a45a8ff 674 /* OWN bit set */
bogdanm 0:9b334a45a8ff 675 heth->State = HAL_ETH_STATE_BUSY_TX;
bogdanm 0:9b334a45a8ff 676
bogdanm 0:9b334a45a8ff 677 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 678 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 679
bogdanm 0:9b334a45a8ff 680 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 681 }
bogdanm 0:9b334a45a8ff 682
bogdanm 0:9b334a45a8ff 683 /* Get the number of needed Tx buffers for the current frame */
bogdanm 0:9b334a45a8ff 684 if (FrameLength > ETH_TX_BUF_SIZE)
bogdanm 0:9b334a45a8ff 685 {
bogdanm 0:9b334a45a8ff 686 bufcount = FrameLength/ETH_TX_BUF_SIZE;
bogdanm 0:9b334a45a8ff 687 if (FrameLength % ETH_TX_BUF_SIZE)
bogdanm 0:9b334a45a8ff 688 {
bogdanm 0:9b334a45a8ff 689 bufcount++;
bogdanm 0:9b334a45a8ff 690 }
bogdanm 0:9b334a45a8ff 691 }
bogdanm 0:9b334a45a8ff 692 else
bogdanm 0:9b334a45a8ff 693 {
bogdanm 0:9b334a45a8ff 694 bufcount = 1;
bogdanm 0:9b334a45a8ff 695 }
bogdanm 0:9b334a45a8ff 696 if (bufcount == 1)
bogdanm 0:9b334a45a8ff 697 {
bogdanm 0:9b334a45a8ff 698 /* Set LAST and FIRST segment */
bogdanm 0:9b334a45a8ff 699 heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
bogdanm 0:9b334a45a8ff 700 /* Set frame size */
bogdanm 0:9b334a45a8ff 701 heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
bogdanm 0:9b334a45a8ff 702 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
bogdanm 0:9b334a45a8ff 703 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
bogdanm 0:9b334a45a8ff 704 /* Point to next descriptor */
bogdanm 0:9b334a45a8ff 705 heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
bogdanm 0:9b334a45a8ff 706 }
bogdanm 0:9b334a45a8ff 707 else
bogdanm 0:9b334a45a8ff 708 {
bogdanm 0:9b334a45a8ff 709 for (i=0; i< bufcount; i++)
bogdanm 0:9b334a45a8ff 710 {
bogdanm 0:9b334a45a8ff 711 /* Clear FIRST and LAST segment bits */
bogdanm 0:9b334a45a8ff 712 heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
bogdanm 0:9b334a45a8ff 713
bogdanm 0:9b334a45a8ff 714 if (i == 0)
bogdanm 0:9b334a45a8ff 715 {
bogdanm 0:9b334a45a8ff 716 /* Setting the first segment bit */
bogdanm 0:9b334a45a8ff 717 heth->TxDesc->Status |= ETH_DMATXDESC_FS;
bogdanm 0:9b334a45a8ff 718 }
bogdanm 0:9b334a45a8ff 719
bogdanm 0:9b334a45a8ff 720 /* Program size */
bogdanm 0:9b334a45a8ff 721 heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
bogdanm 0:9b334a45a8ff 722
bogdanm 0:9b334a45a8ff 723 if (i == (bufcount-1))
bogdanm 0:9b334a45a8ff 724 {
bogdanm 0:9b334a45a8ff 725 /* Setting the last segment bit */
bogdanm 0:9b334a45a8ff 726 heth->TxDesc->Status |= ETH_DMATXDESC_LS;
bogdanm 0:9b334a45a8ff 727 size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;
bogdanm 0:9b334a45a8ff 728 heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
bogdanm 0:9b334a45a8ff 729 }
bogdanm 0:9b334a45a8ff 730
bogdanm 0:9b334a45a8ff 731 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
bogdanm 0:9b334a45a8ff 732 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
bogdanm 0:9b334a45a8ff 733 /* point to next descriptor */
bogdanm 0:9b334a45a8ff 734 heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
bogdanm 0:9b334a45a8ff 735 }
bogdanm 0:9b334a45a8ff 736 }
bogdanm 0:9b334a45a8ff 737
bogdanm 0:9b334a45a8ff 738 /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
bogdanm 0:9b334a45a8ff 739 if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
bogdanm 0:9b334a45a8ff 740 {
bogdanm 0:9b334a45a8ff 741 /* Clear TBUS ETHERNET DMA flag */
bogdanm 0:9b334a45a8ff 742 (heth->Instance)->DMASR = ETH_DMASR_TBUS;
bogdanm 0:9b334a45a8ff 743 /* Resume DMA transmission*/
bogdanm 0:9b334a45a8ff 744 (heth->Instance)->DMATPDR = 0;
bogdanm 0:9b334a45a8ff 745 }
bogdanm 0:9b334a45a8ff 746
bogdanm 0:9b334a45a8ff 747 /* Set ETH HAL State to Ready */
bogdanm 0:9b334a45a8ff 748 heth->State = HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 749
bogdanm 0:9b334a45a8ff 750 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 751 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 752
bogdanm 0:9b334a45a8ff 753 /* Return function status */
bogdanm 0:9b334a45a8ff 754 return HAL_OK;
bogdanm 0:9b334a45a8ff 755 }
bogdanm 0:9b334a45a8ff 756
bogdanm 0:9b334a45a8ff 757 /**
bogdanm 0:9b334a45a8ff 758 * @brief Checks for received frames.
bogdanm 0:9b334a45a8ff 759 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 760 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 761 * @retval HAL status
bogdanm 0:9b334a45a8ff 762 */
bogdanm 0:9b334a45a8ff 763 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 764 {
bogdanm 0:9b334a45a8ff 765 uint32_t framelength = 0;
bogdanm 0:9b334a45a8ff 766
bogdanm 0:9b334a45a8ff 767 /* Process Locked */
bogdanm 0:9b334a45a8ff 768 __HAL_LOCK(heth);
bogdanm 0:9b334a45a8ff 769
bogdanm 0:9b334a45a8ff 770 /* Check the ETH state to BUSY */
bogdanm 0:9b334a45a8ff 771 heth->State = HAL_ETH_STATE_BUSY;
bogdanm 0:9b334a45a8ff 772
bogdanm 0:9b334a45a8ff 773 /* Check if segment is not owned by DMA */
bogdanm 0:9b334a45a8ff 774 /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
bogdanm 0:9b334a45a8ff 775 if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
bogdanm 0:9b334a45a8ff 776 {
bogdanm 0:9b334a45a8ff 777 /* Check if last segment */
bogdanm 0:9b334a45a8ff 778 if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
bogdanm 0:9b334a45a8ff 779 {
bogdanm 0:9b334a45a8ff 780 /* increment segment count */
bogdanm 0:9b334a45a8ff 781 (heth->RxFrameInfos).SegCount++;
bogdanm 0:9b334a45a8ff 782
bogdanm 0:9b334a45a8ff 783 /* Check if last segment is first segment: one segment contains the frame */
bogdanm 0:9b334a45a8ff 784 if ((heth->RxFrameInfos).SegCount == 1)
bogdanm 0:9b334a45a8ff 785 {
bogdanm 0:9b334a45a8ff 786 (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
bogdanm 0:9b334a45a8ff 787 }
bogdanm 0:9b334a45a8ff 788
bogdanm 0:9b334a45a8ff 789 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
bogdanm 0:9b334a45a8ff 790
bogdanm 0:9b334a45a8ff 791 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
bogdanm 0:9b334a45a8ff 792 framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
bogdanm 0:9b334a45a8ff 793 heth->RxFrameInfos.length = framelength;
bogdanm 0:9b334a45a8ff 794
bogdanm 0:9b334a45a8ff 795 /* Get the address of the buffer start address */
bogdanm 0:9b334a45a8ff 796 heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
bogdanm 0:9b334a45a8ff 797 /* point to next descriptor */
bogdanm 0:9b334a45a8ff 798 heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
bogdanm 0:9b334a45a8ff 799
bogdanm 0:9b334a45a8ff 800 /* Set HAL State to Ready */
bogdanm 0:9b334a45a8ff 801 heth->State = HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 802
bogdanm 0:9b334a45a8ff 803 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 804 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 805
bogdanm 0:9b334a45a8ff 806 /* Return function status */
bogdanm 0:9b334a45a8ff 807 return HAL_OK;
bogdanm 0:9b334a45a8ff 808 }
bogdanm 0:9b334a45a8ff 809 /* Check if first segment */
bogdanm 0:9b334a45a8ff 810 else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
bogdanm 0:9b334a45a8ff 811 {
bogdanm 0:9b334a45a8ff 812 (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
bogdanm 0:9b334a45a8ff 813 (heth->RxFrameInfos).LSRxDesc = NULL;
bogdanm 0:9b334a45a8ff 814 (heth->RxFrameInfos).SegCount = 1;
bogdanm 0:9b334a45a8ff 815 /* Point to next descriptor */
bogdanm 0:9b334a45a8ff 816 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
bogdanm 0:9b334a45a8ff 817 }
bogdanm 0:9b334a45a8ff 818 /* Check if intermediate segment */
bogdanm 0:9b334a45a8ff 819 else
bogdanm 0:9b334a45a8ff 820 {
bogdanm 0:9b334a45a8ff 821 (heth->RxFrameInfos).SegCount++;
bogdanm 0:9b334a45a8ff 822 /* Point to next descriptor */
bogdanm 0:9b334a45a8ff 823 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
bogdanm 0:9b334a45a8ff 824 }
bogdanm 0:9b334a45a8ff 825 }
bogdanm 0:9b334a45a8ff 826
bogdanm 0:9b334a45a8ff 827 /* Set ETH HAL State to Ready */
bogdanm 0:9b334a45a8ff 828 heth->State = HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 829
bogdanm 0:9b334a45a8ff 830 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 831 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 832
bogdanm 0:9b334a45a8ff 833 /* Return function status */
bogdanm 0:9b334a45a8ff 834 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 835 }
bogdanm 0:9b334a45a8ff 836
bogdanm 0:9b334a45a8ff 837 /**
bogdanm 0:9b334a45a8ff 838 * @brief Gets the Received frame in interrupt mode.
bogdanm 0:9b334a45a8ff 839 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 840 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 841 * @retval HAL status
bogdanm 0:9b334a45a8ff 842 */
bogdanm 0:9b334a45a8ff 843 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 844 {
bogdanm 0:9b334a45a8ff 845 uint32_t descriptorscancounter = 0;
bogdanm 0:9b334a45a8ff 846
bogdanm 0:9b334a45a8ff 847 /* Process Locked */
bogdanm 0:9b334a45a8ff 848 __HAL_LOCK(heth);
bogdanm 0:9b334a45a8ff 849
bogdanm 0:9b334a45a8ff 850 /* Set ETH HAL State to BUSY */
bogdanm 0:9b334a45a8ff 851 heth->State = HAL_ETH_STATE_BUSY;
bogdanm 0:9b334a45a8ff 852
bogdanm 0:9b334a45a8ff 853 /* Scan descriptors owned by CPU */
bogdanm 0:9b334a45a8ff 854 while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
bogdanm 0:9b334a45a8ff 855 {
bogdanm 0:9b334a45a8ff 856 /* Just for security */
bogdanm 0:9b334a45a8ff 857 descriptorscancounter++;
bogdanm 0:9b334a45a8ff 858
bogdanm 0:9b334a45a8ff 859 /* Check if first segment in frame */
bogdanm 0:9b334a45a8ff 860 /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
bogdanm 0:9b334a45a8ff 861 if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
bogdanm 0:9b334a45a8ff 862 {
bogdanm 0:9b334a45a8ff 863 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
bogdanm 0:9b334a45a8ff 864 heth->RxFrameInfos.SegCount = 1;
bogdanm 0:9b334a45a8ff 865 /* Point to next descriptor */
bogdanm 0:9b334a45a8ff 866 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
bogdanm 0:9b334a45a8ff 867 }
bogdanm 0:9b334a45a8ff 868 /* Check if intermediate segment */
bogdanm 0:9b334a45a8ff 869 /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
bogdanm 0:9b334a45a8ff 870 else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
bogdanm 0:9b334a45a8ff 871 {
bogdanm 0:9b334a45a8ff 872 /* Increment segment count */
bogdanm 0:9b334a45a8ff 873 (heth->RxFrameInfos.SegCount)++;
bogdanm 0:9b334a45a8ff 874 /* Point to next descriptor */
bogdanm 0:9b334a45a8ff 875 heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
bogdanm 0:9b334a45a8ff 876 }
bogdanm 0:9b334a45a8ff 877 /* Should be last segment */
bogdanm 0:9b334a45a8ff 878 else
bogdanm 0:9b334a45a8ff 879 {
bogdanm 0:9b334a45a8ff 880 /* Last segment */
bogdanm 0:9b334a45a8ff 881 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
bogdanm 0:9b334a45a8ff 882
bogdanm 0:9b334a45a8ff 883 /* Increment segment count */
bogdanm 0:9b334a45a8ff 884 (heth->RxFrameInfos.SegCount)++;
bogdanm 0:9b334a45a8ff 885
bogdanm 0:9b334a45a8ff 886 /* Check if last segment is first segment: one segment contains the frame */
bogdanm 0:9b334a45a8ff 887 if ((heth->RxFrameInfos.SegCount) == 1)
bogdanm 0:9b334a45a8ff 888 {
bogdanm 0:9b334a45a8ff 889 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
bogdanm 0:9b334a45a8ff 890 }
bogdanm 0:9b334a45a8ff 891
bogdanm 0:9b334a45a8ff 892 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
bogdanm 0:9b334a45a8ff 893 heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
bogdanm 0:9b334a45a8ff 894
bogdanm 0:9b334a45a8ff 895 /* Get the address of the buffer start address */
bogdanm 0:9b334a45a8ff 896 heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
bogdanm 0:9b334a45a8ff 897
bogdanm 0:9b334a45a8ff 898 /* Point to next descriptor */
bogdanm 0:9b334a45a8ff 899 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
bogdanm 0:9b334a45a8ff 900
bogdanm 0:9b334a45a8ff 901 /* Set HAL State to Ready */
bogdanm 0:9b334a45a8ff 902 heth->State = HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 903
bogdanm 0:9b334a45a8ff 904 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 905 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 906
bogdanm 0:9b334a45a8ff 907 /* Return function status */
bogdanm 0:9b334a45a8ff 908 return HAL_OK;
bogdanm 0:9b334a45a8ff 909 }
bogdanm 0:9b334a45a8ff 910 }
bogdanm 0:9b334a45a8ff 911
bogdanm 0:9b334a45a8ff 912 /* Set HAL State to Ready */
bogdanm 0:9b334a45a8ff 913 heth->State = HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 914
bogdanm 0:9b334a45a8ff 915 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 916 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 917
bogdanm 0:9b334a45a8ff 918 /* Return function status */
bogdanm 0:9b334a45a8ff 919 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 920 }
bogdanm 0:9b334a45a8ff 921
bogdanm 0:9b334a45a8ff 922 /**
bogdanm 0:9b334a45a8ff 923 * @brief This function handles ETH interrupt request.
bogdanm 0:9b334a45a8ff 924 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 925 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 926 * @retval HAL status
bogdanm 0:9b334a45a8ff 927 */
bogdanm 0:9b334a45a8ff 928 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 929 {
bogdanm 0:9b334a45a8ff 930 /* Frame received */
bogdanm 0:9b334a45a8ff 931 if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
bogdanm 0:9b334a45a8ff 932 {
bogdanm 0:9b334a45a8ff 933 /* Receive complete callback */
bogdanm 0:9b334a45a8ff 934 HAL_ETH_RxCpltCallback(heth);
bogdanm 0:9b334a45a8ff 935
bogdanm 0:9b334a45a8ff 936 /* Clear the Eth DMA Rx IT pending bits */
bogdanm 0:9b334a45a8ff 937 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
bogdanm 0:9b334a45a8ff 938
bogdanm 0:9b334a45a8ff 939 /* Set HAL State to Ready */
bogdanm 0:9b334a45a8ff 940 heth->State = HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 941
bogdanm 0:9b334a45a8ff 942 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 943 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 944
bogdanm 0:9b334a45a8ff 945 }
bogdanm 0:9b334a45a8ff 946 /* Frame transmitted */
bogdanm 0:9b334a45a8ff 947 else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
bogdanm 0:9b334a45a8ff 948 {
bogdanm 0:9b334a45a8ff 949 /* Transfer complete callback */
bogdanm 0:9b334a45a8ff 950 HAL_ETH_TxCpltCallback(heth);
bogdanm 0:9b334a45a8ff 951
bogdanm 0:9b334a45a8ff 952 /* Clear the Eth DMA Tx IT pending bits */
bogdanm 0:9b334a45a8ff 953 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
bogdanm 0:9b334a45a8ff 954
bogdanm 0:9b334a45a8ff 955 /* Set HAL State to Ready */
bogdanm 0:9b334a45a8ff 956 heth->State = HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 957
bogdanm 0:9b334a45a8ff 958 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 959 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 960 }
bogdanm 0:9b334a45a8ff 961
bogdanm 0:9b334a45a8ff 962 /* Clear the interrupt flags */
bogdanm 0:9b334a45a8ff 963 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
bogdanm 0:9b334a45a8ff 964
bogdanm 0:9b334a45a8ff 965 /* ETH DMA Error */
bogdanm 0:9b334a45a8ff 966 if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
bogdanm 0:9b334a45a8ff 967 {
bogdanm 0:9b334a45a8ff 968 /* Ethernet Error callback */
bogdanm 0:9b334a45a8ff 969 HAL_ETH_ErrorCallback(heth);
bogdanm 0:9b334a45a8ff 970
bogdanm 0:9b334a45a8ff 971 /* Clear the interrupt flags */
bogdanm 0:9b334a45a8ff 972 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
bogdanm 0:9b334a45a8ff 973
bogdanm 0:9b334a45a8ff 974 /* Set HAL State to Ready */
bogdanm 0:9b334a45a8ff 975 heth->State = HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 976
bogdanm 0:9b334a45a8ff 977 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 978 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 979 }
bogdanm 0:9b334a45a8ff 980 }
bogdanm 0:9b334a45a8ff 981
bogdanm 0:9b334a45a8ff 982 /**
bogdanm 0:9b334a45a8ff 983 * @brief Tx Transfer completed callbacks.
bogdanm 0:9b334a45a8ff 984 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 985 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 986 * @retval None
bogdanm 0:9b334a45a8ff 987 */
bogdanm 0:9b334a45a8ff 988 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 989 {
bogdanm 0:9b334a45a8ff 990 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 991 the HAL_ETH_TxCpltCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 992 */
bogdanm 0:9b334a45a8ff 993 }
bogdanm 0:9b334a45a8ff 994
bogdanm 0:9b334a45a8ff 995 /**
bogdanm 0:9b334a45a8ff 996 * @brief Rx Transfer completed callbacks.
bogdanm 0:9b334a45a8ff 997 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 998 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 999 * @retval None
bogdanm 0:9b334a45a8ff 1000 */
bogdanm 0:9b334a45a8ff 1001 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 1002 {
bogdanm 0:9b334a45a8ff 1003 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1004 the HAL_ETH_TxCpltCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 1005 */
bogdanm 0:9b334a45a8ff 1006 }
bogdanm 0:9b334a45a8ff 1007
bogdanm 0:9b334a45a8ff 1008 /**
bogdanm 0:9b334a45a8ff 1009 * @brief Ethernet transfer error callbacks
bogdanm 0:9b334a45a8ff 1010 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1011 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1012 * @retval None
bogdanm 0:9b334a45a8ff 1013 */
bogdanm 0:9b334a45a8ff 1014 __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 1015 {
bogdanm 0:9b334a45a8ff 1016 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1017 the HAL_ETH_TxCpltCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 1018 */
bogdanm 0:9b334a45a8ff 1019 }
bogdanm 0:9b334a45a8ff 1020
bogdanm 0:9b334a45a8ff 1021 /**
bogdanm 0:9b334a45a8ff 1022 * @brief Reads a PHY register
bogdanm 0:9b334a45a8ff 1023 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1024 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1025 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
bogdanm 0:9b334a45a8ff 1026 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1027 * PHY_BCR: Transceiver Basic Control Register,
bogdanm 0:9b334a45a8ff 1028 * PHY_BSR: Transceiver Basic Status Register.
bogdanm 0:9b334a45a8ff 1029 * More PHY register could be read depending on the used PHY
bogdanm 0:9b334a45a8ff 1030 * @param RegValue: PHY register value
bogdanm 0:9b334a45a8ff 1031 * @retval HAL status
bogdanm 0:9b334a45a8ff 1032 */
bogdanm 0:9b334a45a8ff 1033 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
bogdanm 0:9b334a45a8ff 1034 {
bogdanm 0:9b334a45a8ff 1035 uint32_t tmpreg1 = 0;
bogdanm 0:9b334a45a8ff 1036 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 1037
bogdanm 0:9b334a45a8ff 1038 /* Check parameters */
bogdanm 0:9b334a45a8ff 1039 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
bogdanm 0:9b334a45a8ff 1040
bogdanm 0:9b334a45a8ff 1041 /* Check the ETH peripheral state */
bogdanm 0:9b334a45a8ff 1042 if(heth->State == HAL_ETH_STATE_BUSY_RD)
bogdanm 0:9b334a45a8ff 1043 {
bogdanm 0:9b334a45a8ff 1044 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 1045 }
bogdanm 0:9b334a45a8ff 1046 /* Set ETH HAL State to BUSY_RD */
bogdanm 0:9b334a45a8ff 1047 heth->State = HAL_ETH_STATE_BUSY_RD;
bogdanm 0:9b334a45a8ff 1048
bogdanm 0:9b334a45a8ff 1049 /* Get the ETHERNET MACMIIAR value */
bogdanm 0:9b334a45a8ff 1050 tmpreg1 = heth->Instance->MACMIIAR;
bogdanm 0:9b334a45a8ff 1051
bogdanm 0:9b334a45a8ff 1052 /* Keep only the CSR Clock Range CR[2:0] bits value */
bogdanm 0:9b334a45a8ff 1053 tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
bogdanm 0:9b334a45a8ff 1054
bogdanm 0:9b334a45a8ff 1055 /* Prepare the MII address register value */
bogdanm 0:9b334a45a8ff 1056 tmpreg1 |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
bogdanm 0:9b334a45a8ff 1057 tmpreg1 |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
bogdanm 0:9b334a45a8ff 1058 tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */
bogdanm 0:9b334a45a8ff 1059 tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
bogdanm 0:9b334a45a8ff 1060
bogdanm 0:9b334a45a8ff 1061 /* Write the result value into the MII Address register */
bogdanm 0:9b334a45a8ff 1062 heth->Instance->MACMIIAR = tmpreg1;
bogdanm 0:9b334a45a8ff 1063
bogdanm 0:9b334a45a8ff 1064 /* Get tick */
bogdanm 0:9b334a45a8ff 1065 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 1066
bogdanm 0:9b334a45a8ff 1067 /* Check for the Busy flag */
bogdanm 0:9b334a45a8ff 1068 while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
bogdanm 0:9b334a45a8ff 1069 {
bogdanm 0:9b334a45a8ff 1070 /* Check for the Timeout */
bogdanm 0:9b334a45a8ff 1071 if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
bogdanm 0:9b334a45a8ff 1072 {
bogdanm 0:9b334a45a8ff 1073 heth->State= HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 1074
bogdanm 0:9b334a45a8ff 1075 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1076 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 1077
bogdanm 0:9b334a45a8ff 1078 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 1079 }
bogdanm 0:9b334a45a8ff 1080
bogdanm 0:9b334a45a8ff 1081 tmpreg1 = heth->Instance->MACMIIAR;
bogdanm 0:9b334a45a8ff 1082 }
bogdanm 0:9b334a45a8ff 1083
bogdanm 0:9b334a45a8ff 1084 /* Get MACMIIDR value */
bogdanm 0:9b334a45a8ff 1085 *RegValue = (uint16_t)(heth->Instance->MACMIIDR);
bogdanm 0:9b334a45a8ff 1086
bogdanm 0:9b334a45a8ff 1087 /* Set ETH HAL State to READY */
bogdanm 0:9b334a45a8ff 1088 heth->State = HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 1089
bogdanm 0:9b334a45a8ff 1090 /* Return function status */
bogdanm 0:9b334a45a8ff 1091 return HAL_OK;
bogdanm 0:9b334a45a8ff 1092 }
bogdanm 0:9b334a45a8ff 1093
bogdanm 0:9b334a45a8ff 1094 /**
bogdanm 0:9b334a45a8ff 1095 * @brief Writes to a PHY register.
bogdanm 0:9b334a45a8ff 1096 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1097 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1098 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
bogdanm 0:9b334a45a8ff 1099 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1100 * PHY_BCR: Transceiver Control Register.
bogdanm 0:9b334a45a8ff 1101 * More PHY register could be written depending on the used PHY
bogdanm 0:9b334a45a8ff 1102 * @param RegValue: the value to write
bogdanm 0:9b334a45a8ff 1103 * @retval HAL status
bogdanm 0:9b334a45a8ff 1104 */
bogdanm 0:9b334a45a8ff 1105 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
bogdanm 0:9b334a45a8ff 1106 {
bogdanm 0:9b334a45a8ff 1107 uint32_t tmpreg1 = 0;
bogdanm 0:9b334a45a8ff 1108 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 1109
bogdanm 0:9b334a45a8ff 1110 /* Check parameters */
bogdanm 0:9b334a45a8ff 1111 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
bogdanm 0:9b334a45a8ff 1112
bogdanm 0:9b334a45a8ff 1113 /* Check the ETH peripheral state */
bogdanm 0:9b334a45a8ff 1114 if(heth->State == HAL_ETH_STATE_BUSY_WR)
bogdanm 0:9b334a45a8ff 1115 {
bogdanm 0:9b334a45a8ff 1116 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 1117 }
bogdanm 0:9b334a45a8ff 1118 /* Set ETH HAL State to BUSY_WR */
bogdanm 0:9b334a45a8ff 1119 heth->State = HAL_ETH_STATE_BUSY_WR;
bogdanm 0:9b334a45a8ff 1120
bogdanm 0:9b334a45a8ff 1121 /* Get the ETHERNET MACMIIAR value */
bogdanm 0:9b334a45a8ff 1122 tmpreg1 = heth->Instance->MACMIIAR;
bogdanm 0:9b334a45a8ff 1123
bogdanm 0:9b334a45a8ff 1124 /* Keep only the CSR Clock Range CR[2:0] bits value */
bogdanm 0:9b334a45a8ff 1125 tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
bogdanm 0:9b334a45a8ff 1126
bogdanm 0:9b334a45a8ff 1127 /* Prepare the MII register address value */
bogdanm 0:9b334a45a8ff 1128 tmpreg1 |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
bogdanm 0:9b334a45a8ff 1129 tmpreg1 |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
bogdanm 0:9b334a45a8ff 1130 tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */
bogdanm 0:9b334a45a8ff 1131 tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
bogdanm 0:9b334a45a8ff 1132
bogdanm 0:9b334a45a8ff 1133 /* Give the value to the MII data register */
bogdanm 0:9b334a45a8ff 1134 heth->Instance->MACMIIDR = (uint16_t)RegValue;
bogdanm 0:9b334a45a8ff 1135
bogdanm 0:9b334a45a8ff 1136 /* Write the result value into the MII Address register */
bogdanm 0:9b334a45a8ff 1137 heth->Instance->MACMIIAR = tmpreg1;
bogdanm 0:9b334a45a8ff 1138
bogdanm 0:9b334a45a8ff 1139 /* Get tick */
bogdanm 0:9b334a45a8ff 1140 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 1141
bogdanm 0:9b334a45a8ff 1142 /* Check for the Busy flag */
bogdanm 0:9b334a45a8ff 1143 while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
bogdanm 0:9b334a45a8ff 1144 {
bogdanm 0:9b334a45a8ff 1145 /* Check for the Timeout */
bogdanm 0:9b334a45a8ff 1146 if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
bogdanm 0:9b334a45a8ff 1147 {
bogdanm 0:9b334a45a8ff 1148 heth->State= HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 1149
bogdanm 0:9b334a45a8ff 1150 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1151 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 1152
bogdanm 0:9b334a45a8ff 1153 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 1154 }
bogdanm 0:9b334a45a8ff 1155
bogdanm 0:9b334a45a8ff 1156 tmpreg1 = heth->Instance->MACMIIAR;
bogdanm 0:9b334a45a8ff 1157 }
bogdanm 0:9b334a45a8ff 1158
bogdanm 0:9b334a45a8ff 1159 /* Set ETH HAL State to READY */
bogdanm 0:9b334a45a8ff 1160 heth->State = HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 1161
bogdanm 0:9b334a45a8ff 1162 /* Return function status */
bogdanm 0:9b334a45a8ff 1163 return HAL_OK;
bogdanm 0:9b334a45a8ff 1164 }
bogdanm 0:9b334a45a8ff 1165
bogdanm 0:9b334a45a8ff 1166 /**
bogdanm 0:9b334a45a8ff 1167 * @}
bogdanm 0:9b334a45a8ff 1168 */
bogdanm 0:9b334a45a8ff 1169
bogdanm 0:9b334a45a8ff 1170 /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
bogdanm 0:9b334a45a8ff 1171 * @brief Peripheral Control functions
bogdanm 0:9b334a45a8ff 1172 *
bogdanm 0:9b334a45a8ff 1173 @verbatim
bogdanm 0:9b334a45a8ff 1174 ===============================================================================
bogdanm 0:9b334a45a8ff 1175 ##### Peripheral Control functions #####
bogdanm 0:9b334a45a8ff 1176 ===============================================================================
bogdanm 0:9b334a45a8ff 1177 [..] This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 1178 (+) Enable MAC and DMA transmission and reception.
bogdanm 0:9b334a45a8ff 1179 HAL_ETH_Start();
bogdanm 0:9b334a45a8ff 1180 (+) Disable MAC and DMA transmission and reception.
bogdanm 0:9b334a45a8ff 1181 HAL_ETH_Stop();
bogdanm 0:9b334a45a8ff 1182 (+) Set the MAC configuration in runtime mode
bogdanm 0:9b334a45a8ff 1183 HAL_ETH_ConfigMAC();
bogdanm 0:9b334a45a8ff 1184 (+) Set the DMA configuration in runtime mode
bogdanm 0:9b334a45a8ff 1185 HAL_ETH_ConfigDMA();
bogdanm 0:9b334a45a8ff 1186
bogdanm 0:9b334a45a8ff 1187 @endverbatim
bogdanm 0:9b334a45a8ff 1188 * @{
bogdanm 0:9b334a45a8ff 1189 */
bogdanm 0:9b334a45a8ff 1190
bogdanm 0:9b334a45a8ff 1191 /**
bogdanm 0:9b334a45a8ff 1192 * @brief Enables Ethernet MAC and DMA reception/transmission
bogdanm 0:9b334a45a8ff 1193 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1194 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1195 * @retval HAL status
bogdanm 0:9b334a45a8ff 1196 */
bogdanm 0:9b334a45a8ff 1197 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 1198 {
bogdanm 0:9b334a45a8ff 1199 /* Process Locked */
bogdanm 0:9b334a45a8ff 1200 __HAL_LOCK(heth);
bogdanm 0:9b334a45a8ff 1201
bogdanm 0:9b334a45a8ff 1202 /* Set the ETH peripheral state to BUSY */
bogdanm 0:9b334a45a8ff 1203 heth->State = HAL_ETH_STATE_BUSY;
bogdanm 0:9b334a45a8ff 1204
bogdanm 0:9b334a45a8ff 1205 /* Enable transmit state machine of the MAC for transmission on the MII */
bogdanm 0:9b334a45a8ff 1206 ETH_MACTransmissionEnable(heth);
bogdanm 0:9b334a45a8ff 1207
bogdanm 0:9b334a45a8ff 1208 /* Enable receive state machine of the MAC for reception from the MII */
bogdanm 0:9b334a45a8ff 1209 ETH_MACReceptionEnable(heth);
bogdanm 0:9b334a45a8ff 1210
bogdanm 0:9b334a45a8ff 1211 /* Flush Transmit FIFO */
bogdanm 0:9b334a45a8ff 1212 ETH_FlushTransmitFIFO(heth);
bogdanm 0:9b334a45a8ff 1213
bogdanm 0:9b334a45a8ff 1214 /* Start DMA transmission */
bogdanm 0:9b334a45a8ff 1215 ETH_DMATransmissionEnable(heth);
bogdanm 0:9b334a45a8ff 1216
bogdanm 0:9b334a45a8ff 1217 /* Start DMA reception */
bogdanm 0:9b334a45a8ff 1218 ETH_DMAReceptionEnable(heth);
bogdanm 0:9b334a45a8ff 1219
bogdanm 0:9b334a45a8ff 1220 /* Set the ETH state to READY*/
bogdanm 0:9b334a45a8ff 1221 heth->State= HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 1222
bogdanm 0:9b334a45a8ff 1223 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1224 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 1225
bogdanm 0:9b334a45a8ff 1226 /* Return function status */
bogdanm 0:9b334a45a8ff 1227 return HAL_OK;
bogdanm 0:9b334a45a8ff 1228 }
bogdanm 0:9b334a45a8ff 1229
bogdanm 0:9b334a45a8ff 1230 /**
bogdanm 0:9b334a45a8ff 1231 * @brief Stop Ethernet MAC and DMA reception/transmission
bogdanm 0:9b334a45a8ff 1232 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1233 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1234 * @retval HAL status
bogdanm 0:9b334a45a8ff 1235 */
bogdanm 0:9b334a45a8ff 1236 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 1237 {
bogdanm 0:9b334a45a8ff 1238 /* Process Locked */
bogdanm 0:9b334a45a8ff 1239 __HAL_LOCK(heth);
bogdanm 0:9b334a45a8ff 1240
bogdanm 0:9b334a45a8ff 1241 /* Set the ETH peripheral state to BUSY */
bogdanm 0:9b334a45a8ff 1242 heth->State = HAL_ETH_STATE_BUSY;
bogdanm 0:9b334a45a8ff 1243
bogdanm 0:9b334a45a8ff 1244 /* Stop DMA transmission */
bogdanm 0:9b334a45a8ff 1245 ETH_DMATransmissionDisable(heth);
bogdanm 0:9b334a45a8ff 1246
bogdanm 0:9b334a45a8ff 1247 /* Stop DMA reception */
bogdanm 0:9b334a45a8ff 1248 ETH_DMAReceptionDisable(heth);
bogdanm 0:9b334a45a8ff 1249
bogdanm 0:9b334a45a8ff 1250 /* Disable receive state machine of the MAC for reception from the MII */
bogdanm 0:9b334a45a8ff 1251 ETH_MACReceptionDisable(heth);
bogdanm 0:9b334a45a8ff 1252
bogdanm 0:9b334a45a8ff 1253 /* Flush Transmit FIFO */
bogdanm 0:9b334a45a8ff 1254 ETH_FlushTransmitFIFO(heth);
bogdanm 0:9b334a45a8ff 1255
bogdanm 0:9b334a45a8ff 1256 /* Disable transmit state machine of the MAC for transmission on the MII */
bogdanm 0:9b334a45a8ff 1257 ETH_MACTransmissionDisable(heth);
bogdanm 0:9b334a45a8ff 1258
bogdanm 0:9b334a45a8ff 1259 /* Set the ETH state*/
bogdanm 0:9b334a45a8ff 1260 heth->State = HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 1261
bogdanm 0:9b334a45a8ff 1262 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1263 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 1264
bogdanm 0:9b334a45a8ff 1265 /* Return function status */
bogdanm 0:9b334a45a8ff 1266 return HAL_OK;
bogdanm 0:9b334a45a8ff 1267 }
bogdanm 0:9b334a45a8ff 1268
bogdanm 0:9b334a45a8ff 1269 /**
bogdanm 0:9b334a45a8ff 1270 * @brief Set ETH MAC Configuration.
bogdanm 0:9b334a45a8ff 1271 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1272 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1273 * @param macconf: MAC Configuration structure
bogdanm 0:9b334a45a8ff 1274 * @retval HAL status
bogdanm 0:9b334a45a8ff 1275 */
bogdanm 0:9b334a45a8ff 1276 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
bogdanm 0:9b334a45a8ff 1277 {
bogdanm 0:9b334a45a8ff 1278 uint32_t tmpreg1 = 0;
bogdanm 0:9b334a45a8ff 1279
bogdanm 0:9b334a45a8ff 1280 /* Process Locked */
bogdanm 0:9b334a45a8ff 1281 __HAL_LOCK(heth);
bogdanm 0:9b334a45a8ff 1282
bogdanm 0:9b334a45a8ff 1283 /* Set the ETH peripheral state to BUSY */
bogdanm 0:9b334a45a8ff 1284 heth->State= HAL_ETH_STATE_BUSY;
bogdanm 0:9b334a45a8ff 1285
bogdanm 0:9b334a45a8ff 1286 assert_param(IS_ETH_SPEED(heth->Init.Speed));
bogdanm 0:9b334a45a8ff 1287 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
bogdanm 0:9b334a45a8ff 1288
bogdanm 0:9b334a45a8ff 1289 if (macconf != NULL)
bogdanm 0:9b334a45a8ff 1290 {
bogdanm 0:9b334a45a8ff 1291 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1292 assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
bogdanm 0:9b334a45a8ff 1293 assert_param(IS_ETH_JABBER(macconf->Jabber));
bogdanm 0:9b334a45a8ff 1294 assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
bogdanm 0:9b334a45a8ff 1295 assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
bogdanm 0:9b334a45a8ff 1296 assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
bogdanm 0:9b334a45a8ff 1297 assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
bogdanm 0:9b334a45a8ff 1298 assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
bogdanm 0:9b334a45a8ff 1299 assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
bogdanm 0:9b334a45a8ff 1300 assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
bogdanm 0:9b334a45a8ff 1301 assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
bogdanm 0:9b334a45a8ff 1302 assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
bogdanm 0:9b334a45a8ff 1303 assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
bogdanm 0:9b334a45a8ff 1304 assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
bogdanm 0:9b334a45a8ff 1305 assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
bogdanm 0:9b334a45a8ff 1306 assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
bogdanm 0:9b334a45a8ff 1307 assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
bogdanm 0:9b334a45a8ff 1308 assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
bogdanm 0:9b334a45a8ff 1309 assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
bogdanm 0:9b334a45a8ff 1310 assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
bogdanm 0:9b334a45a8ff 1311 assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
bogdanm 0:9b334a45a8ff 1312 assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
bogdanm 0:9b334a45a8ff 1313 assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
bogdanm 0:9b334a45a8ff 1314 assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
bogdanm 0:9b334a45a8ff 1315 assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
bogdanm 0:9b334a45a8ff 1316 assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
bogdanm 0:9b334a45a8ff 1317 assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
bogdanm 0:9b334a45a8ff 1318 assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
bogdanm 0:9b334a45a8ff 1319
bogdanm 0:9b334a45a8ff 1320 /*------------------------ ETHERNET MACCR Configuration --------------------*/
bogdanm 0:9b334a45a8ff 1321 /* Get the ETHERNET MACCR value */
bogdanm 0:9b334a45a8ff 1322 tmpreg1 = (heth->Instance)->MACCR;
bogdanm 0:9b334a45a8ff 1323 /* Clear WD, PCE, PS, TE and RE bits */
bogdanm 0:9b334a45a8ff 1324 tmpreg1 &= ETH_MACCR_CLEAR_MASK;
bogdanm 0:9b334a45a8ff 1325
bogdanm 0:9b334a45a8ff 1326 tmpreg1 |= (uint32_t)(macconf->Watchdog |
bogdanm 0:9b334a45a8ff 1327 macconf->Jabber |
bogdanm 0:9b334a45a8ff 1328 macconf->InterFrameGap |
bogdanm 0:9b334a45a8ff 1329 macconf->CarrierSense |
bogdanm 0:9b334a45a8ff 1330 (heth->Init).Speed |
bogdanm 0:9b334a45a8ff 1331 macconf->ReceiveOwn |
bogdanm 0:9b334a45a8ff 1332 macconf->LoopbackMode |
bogdanm 0:9b334a45a8ff 1333 (heth->Init).DuplexMode |
bogdanm 0:9b334a45a8ff 1334 macconf->ChecksumOffload |
bogdanm 0:9b334a45a8ff 1335 macconf->RetryTransmission |
bogdanm 0:9b334a45a8ff 1336 macconf->AutomaticPadCRCStrip |
bogdanm 0:9b334a45a8ff 1337 macconf->BackOffLimit |
bogdanm 0:9b334a45a8ff 1338 macconf->DeferralCheck);
bogdanm 0:9b334a45a8ff 1339
bogdanm 0:9b334a45a8ff 1340 /* Write to ETHERNET MACCR */
bogdanm 0:9b334a45a8ff 1341 (heth->Instance)->MACCR = (uint32_t)tmpreg1;
bogdanm 0:9b334a45a8ff 1342
bogdanm 0:9b334a45a8ff 1343 /* Wait until the write operation will be taken into account :
bogdanm 0:9b334a45a8ff 1344 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1345 tmpreg1 = (heth->Instance)->MACCR;
bogdanm 0:9b334a45a8ff 1346 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1347 (heth->Instance)->MACCR = tmpreg1;
bogdanm 0:9b334a45a8ff 1348
bogdanm 0:9b334a45a8ff 1349 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
bogdanm 0:9b334a45a8ff 1350 /* Write to ETHERNET MACFFR */
bogdanm 0:9b334a45a8ff 1351 (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
bogdanm 0:9b334a45a8ff 1352 macconf->SourceAddrFilter |
bogdanm 0:9b334a45a8ff 1353 macconf->PassControlFrames |
bogdanm 0:9b334a45a8ff 1354 macconf->BroadcastFramesReception |
bogdanm 0:9b334a45a8ff 1355 macconf->DestinationAddrFilter |
bogdanm 0:9b334a45a8ff 1356 macconf->PromiscuousMode |
bogdanm 0:9b334a45a8ff 1357 macconf->MulticastFramesFilter |
bogdanm 0:9b334a45a8ff 1358 macconf->UnicastFramesFilter);
bogdanm 0:9b334a45a8ff 1359
bogdanm 0:9b334a45a8ff 1360 /* Wait until the write operation will be taken into account :
bogdanm 0:9b334a45a8ff 1361 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1362 tmpreg1 = (heth->Instance)->MACFFR;
bogdanm 0:9b334a45a8ff 1363 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1364 (heth->Instance)->MACFFR = tmpreg1;
bogdanm 0:9b334a45a8ff 1365
bogdanm 0:9b334a45a8ff 1366 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
bogdanm 0:9b334a45a8ff 1367 /* Write to ETHERNET MACHTHR */
bogdanm 0:9b334a45a8ff 1368 (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
bogdanm 0:9b334a45a8ff 1369
bogdanm 0:9b334a45a8ff 1370 /* Write to ETHERNET MACHTLR */
bogdanm 0:9b334a45a8ff 1371 (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
bogdanm 0:9b334a45a8ff 1372 /*----------------------- ETHERNET MACFCR Configuration --------------------*/
bogdanm 0:9b334a45a8ff 1373
bogdanm 0:9b334a45a8ff 1374 /* Get the ETHERNET MACFCR value */
bogdanm 0:9b334a45a8ff 1375 tmpreg1 = (heth->Instance)->MACFCR;
bogdanm 0:9b334a45a8ff 1376 /* Clear xx bits */
bogdanm 0:9b334a45a8ff 1377 tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
bogdanm 0:9b334a45a8ff 1378
bogdanm 0:9b334a45a8ff 1379 tmpreg1 |= (uint32_t)((macconf->PauseTime << 16) |
bogdanm 0:9b334a45a8ff 1380 macconf->ZeroQuantaPause |
bogdanm 0:9b334a45a8ff 1381 macconf->PauseLowThreshold |
bogdanm 0:9b334a45a8ff 1382 macconf->UnicastPauseFrameDetect |
bogdanm 0:9b334a45a8ff 1383 macconf->ReceiveFlowControl |
bogdanm 0:9b334a45a8ff 1384 macconf->TransmitFlowControl);
bogdanm 0:9b334a45a8ff 1385
bogdanm 0:9b334a45a8ff 1386 /* Write to ETHERNET MACFCR */
bogdanm 0:9b334a45a8ff 1387 (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
bogdanm 0:9b334a45a8ff 1388
bogdanm 0:9b334a45a8ff 1389 /* Wait until the write operation will be taken into account :
bogdanm 0:9b334a45a8ff 1390 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1391 tmpreg1 = (heth->Instance)->MACFCR;
bogdanm 0:9b334a45a8ff 1392 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1393 (heth->Instance)->MACFCR = tmpreg1;
bogdanm 0:9b334a45a8ff 1394
bogdanm 0:9b334a45a8ff 1395 /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
bogdanm 0:9b334a45a8ff 1396 (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
bogdanm 0:9b334a45a8ff 1397 macconf->VLANTagIdentifier);
bogdanm 0:9b334a45a8ff 1398
bogdanm 0:9b334a45a8ff 1399 /* Wait until the write operation will be taken into account :
bogdanm 0:9b334a45a8ff 1400 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1401 tmpreg1 = (heth->Instance)->MACVLANTR;
bogdanm 0:9b334a45a8ff 1402 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1403 (heth->Instance)->MACVLANTR = tmpreg1;
bogdanm 0:9b334a45a8ff 1404 }
bogdanm 0:9b334a45a8ff 1405 else /* macconf == NULL : here we just configure Speed and Duplex mode */
bogdanm 0:9b334a45a8ff 1406 {
bogdanm 0:9b334a45a8ff 1407 /*------------------------ ETHERNET MACCR Configuration --------------------*/
bogdanm 0:9b334a45a8ff 1408 /* Get the ETHERNET MACCR value */
bogdanm 0:9b334a45a8ff 1409 tmpreg1 = (heth->Instance)->MACCR;
bogdanm 0:9b334a45a8ff 1410
bogdanm 0:9b334a45a8ff 1411 /* Clear FES and DM bits */
bogdanm 0:9b334a45a8ff 1412 tmpreg1 &= ~((uint32_t)0x00004800);
bogdanm 0:9b334a45a8ff 1413
bogdanm 0:9b334a45a8ff 1414 tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
bogdanm 0:9b334a45a8ff 1415
bogdanm 0:9b334a45a8ff 1416 /* Write to ETHERNET MACCR */
bogdanm 0:9b334a45a8ff 1417 (heth->Instance)->MACCR = (uint32_t)tmpreg1;
bogdanm 0:9b334a45a8ff 1418
bogdanm 0:9b334a45a8ff 1419 /* Wait until the write operation will be taken into account:
bogdanm 0:9b334a45a8ff 1420 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1421 tmpreg1 = (heth->Instance)->MACCR;
bogdanm 0:9b334a45a8ff 1422 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1423 (heth->Instance)->MACCR = tmpreg1;
bogdanm 0:9b334a45a8ff 1424 }
bogdanm 0:9b334a45a8ff 1425
bogdanm 0:9b334a45a8ff 1426 /* Set the ETH state to Ready */
bogdanm 0:9b334a45a8ff 1427 heth->State= HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 1428
bogdanm 0:9b334a45a8ff 1429 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1430 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 1431
bogdanm 0:9b334a45a8ff 1432 /* Return function status */
bogdanm 0:9b334a45a8ff 1433 return HAL_OK;
bogdanm 0:9b334a45a8ff 1434 }
bogdanm 0:9b334a45a8ff 1435
bogdanm 0:9b334a45a8ff 1436 /**
bogdanm 0:9b334a45a8ff 1437 * @brief Sets ETH DMA Configuration.
bogdanm 0:9b334a45a8ff 1438 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1439 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1440 * @param dmaconf: DMA Configuration structure
bogdanm 0:9b334a45a8ff 1441 * @retval HAL status
bogdanm 0:9b334a45a8ff 1442 */
bogdanm 0:9b334a45a8ff 1443 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
bogdanm 0:9b334a45a8ff 1444 {
bogdanm 0:9b334a45a8ff 1445 uint32_t tmpreg1 = 0;
bogdanm 0:9b334a45a8ff 1446
bogdanm 0:9b334a45a8ff 1447 /* Process Locked */
bogdanm 0:9b334a45a8ff 1448 __HAL_LOCK(heth);
bogdanm 0:9b334a45a8ff 1449
bogdanm 0:9b334a45a8ff 1450 /* Set the ETH peripheral state to BUSY */
bogdanm 0:9b334a45a8ff 1451 heth->State= HAL_ETH_STATE_BUSY;
bogdanm 0:9b334a45a8ff 1452
bogdanm 0:9b334a45a8ff 1453 /* Check parameters */
bogdanm 0:9b334a45a8ff 1454 assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
bogdanm 0:9b334a45a8ff 1455 assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
bogdanm 0:9b334a45a8ff 1456 assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
bogdanm 0:9b334a45a8ff 1457 assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
bogdanm 0:9b334a45a8ff 1458 assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
bogdanm 0:9b334a45a8ff 1459 assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
bogdanm 0:9b334a45a8ff 1460 assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
bogdanm 0:9b334a45a8ff 1461 assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
bogdanm 0:9b334a45a8ff 1462 assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
bogdanm 0:9b334a45a8ff 1463 assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
bogdanm 0:9b334a45a8ff 1464 assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
bogdanm 0:9b334a45a8ff 1465 assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
bogdanm 0:9b334a45a8ff 1466 assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
bogdanm 0:9b334a45a8ff 1467 assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
bogdanm 0:9b334a45a8ff 1468 assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
bogdanm 0:9b334a45a8ff 1469 assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
bogdanm 0:9b334a45a8ff 1470
bogdanm 0:9b334a45a8ff 1471 /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
bogdanm 0:9b334a45a8ff 1472 /* Get the ETHERNET DMAOMR value */
bogdanm 0:9b334a45a8ff 1473 tmpreg1 = (heth->Instance)->DMAOMR;
bogdanm 0:9b334a45a8ff 1474 /* Clear xx bits */
bogdanm 0:9b334a45a8ff 1475 tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
bogdanm 0:9b334a45a8ff 1476
bogdanm 0:9b334a45a8ff 1477 tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
bogdanm 0:9b334a45a8ff 1478 dmaconf->ReceiveStoreForward |
bogdanm 0:9b334a45a8ff 1479 dmaconf->FlushReceivedFrame |
bogdanm 0:9b334a45a8ff 1480 dmaconf->TransmitStoreForward |
bogdanm 0:9b334a45a8ff 1481 dmaconf->TransmitThresholdControl |
bogdanm 0:9b334a45a8ff 1482 dmaconf->ForwardErrorFrames |
bogdanm 0:9b334a45a8ff 1483 dmaconf->ForwardUndersizedGoodFrames |
bogdanm 0:9b334a45a8ff 1484 dmaconf->ReceiveThresholdControl |
bogdanm 0:9b334a45a8ff 1485 dmaconf->SecondFrameOperate);
bogdanm 0:9b334a45a8ff 1486
bogdanm 0:9b334a45a8ff 1487 /* Write to ETHERNET DMAOMR */
bogdanm 0:9b334a45a8ff 1488 (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
bogdanm 0:9b334a45a8ff 1489
bogdanm 0:9b334a45a8ff 1490 /* Wait until the write operation will be taken into account:
bogdanm 0:9b334a45a8ff 1491 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1492 tmpreg1 = (heth->Instance)->DMAOMR;
bogdanm 0:9b334a45a8ff 1493 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1494 (heth->Instance)->DMAOMR = tmpreg1;
bogdanm 0:9b334a45a8ff 1495
bogdanm 0:9b334a45a8ff 1496 /*----------------------- ETHERNET DMABMR Configuration --------------------*/
bogdanm 0:9b334a45a8ff 1497 (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
bogdanm 0:9b334a45a8ff 1498 dmaconf->FixedBurst |
bogdanm 0:9b334a45a8ff 1499 dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
bogdanm 0:9b334a45a8ff 1500 dmaconf->TxDMABurstLength |
bogdanm 0:9b334a45a8ff 1501 dmaconf->EnhancedDescriptorFormat |
bogdanm 0:9b334a45a8ff 1502 (dmaconf->DescriptorSkipLength << 2) |
bogdanm 0:9b334a45a8ff 1503 dmaconf->DMAArbitration |
bogdanm 0:9b334a45a8ff 1504 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
bogdanm 0:9b334a45a8ff 1505
bogdanm 0:9b334a45a8ff 1506 /* Wait until the write operation will be taken into account:
bogdanm 0:9b334a45a8ff 1507 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1508 tmpreg1 = (heth->Instance)->DMABMR;
bogdanm 0:9b334a45a8ff 1509 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1510 (heth->Instance)->DMABMR = tmpreg1;
bogdanm 0:9b334a45a8ff 1511
bogdanm 0:9b334a45a8ff 1512 /* Set the ETH state to Ready */
bogdanm 0:9b334a45a8ff 1513 heth->State= HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 1514
bogdanm 0:9b334a45a8ff 1515 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1516 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 1517
bogdanm 0:9b334a45a8ff 1518 /* Return function status */
bogdanm 0:9b334a45a8ff 1519 return HAL_OK;
bogdanm 0:9b334a45a8ff 1520 }
bogdanm 0:9b334a45a8ff 1521
bogdanm 0:9b334a45a8ff 1522 /**
bogdanm 0:9b334a45a8ff 1523 * @}
bogdanm 0:9b334a45a8ff 1524 */
bogdanm 0:9b334a45a8ff 1525
bogdanm 0:9b334a45a8ff 1526 /** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
bogdanm 0:9b334a45a8ff 1527 * @brief Peripheral State functions
bogdanm 0:9b334a45a8ff 1528 *
bogdanm 0:9b334a45a8ff 1529 @verbatim
bogdanm 0:9b334a45a8ff 1530 ===============================================================================
bogdanm 0:9b334a45a8ff 1531 ##### Peripheral State functions #####
bogdanm 0:9b334a45a8ff 1532 ===============================================================================
bogdanm 0:9b334a45a8ff 1533 [..]
bogdanm 0:9b334a45a8ff 1534 This subsection permits to get in run-time the status of the peripheral
bogdanm 0:9b334a45a8ff 1535 and the data flow.
bogdanm 0:9b334a45a8ff 1536 (+) Get the ETH handle state:
bogdanm 0:9b334a45a8ff 1537 HAL_ETH_GetState();
bogdanm 0:9b334a45a8ff 1538
bogdanm 0:9b334a45a8ff 1539
bogdanm 0:9b334a45a8ff 1540 @endverbatim
bogdanm 0:9b334a45a8ff 1541 * @{
bogdanm 0:9b334a45a8ff 1542 */
bogdanm 0:9b334a45a8ff 1543
bogdanm 0:9b334a45a8ff 1544 /**
bogdanm 0:9b334a45a8ff 1545 * @brief Return the ETH HAL state
bogdanm 0:9b334a45a8ff 1546 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1547 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1548 * @retval HAL state
bogdanm 0:9b334a45a8ff 1549 */
bogdanm 0:9b334a45a8ff 1550 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 1551 {
bogdanm 0:9b334a45a8ff 1552 /* Return ETH state */
bogdanm 0:9b334a45a8ff 1553 return heth->State;
bogdanm 0:9b334a45a8ff 1554 }
bogdanm 0:9b334a45a8ff 1555
bogdanm 0:9b334a45a8ff 1556 /**
bogdanm 0:9b334a45a8ff 1557 * @}
bogdanm 0:9b334a45a8ff 1558 */
bogdanm 0:9b334a45a8ff 1559
bogdanm 0:9b334a45a8ff 1560 /**
bogdanm 0:9b334a45a8ff 1561 * @}
bogdanm 0:9b334a45a8ff 1562 */
bogdanm 0:9b334a45a8ff 1563
bogdanm 0:9b334a45a8ff 1564 /** @addtogroup ETH_Private_Functions
bogdanm 0:9b334a45a8ff 1565 * @{
bogdanm 0:9b334a45a8ff 1566 */
bogdanm 0:9b334a45a8ff 1567
bogdanm 0:9b334a45a8ff 1568 /**
bogdanm 0:9b334a45a8ff 1569 * @brief Configures Ethernet MAC and DMA with default parameters.
bogdanm 0:9b334a45a8ff 1570 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1571 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1572 * @param err: Ethernet Init error
bogdanm 0:9b334a45a8ff 1573 * @retval HAL status
bogdanm 0:9b334a45a8ff 1574 */
bogdanm 0:9b334a45a8ff 1575 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
bogdanm 0:9b334a45a8ff 1576 {
bogdanm 0:9b334a45a8ff 1577 ETH_MACInitTypeDef macinit;
bogdanm 0:9b334a45a8ff 1578 ETH_DMAInitTypeDef dmainit;
bogdanm 0:9b334a45a8ff 1579 uint32_t tmpreg1 = 0;
bogdanm 0:9b334a45a8ff 1580
bogdanm 0:9b334a45a8ff 1581 if (err != ETH_SUCCESS) /* Auto-negotiation failed */
bogdanm 0:9b334a45a8ff 1582 {
bogdanm 0:9b334a45a8ff 1583 /* Set Ethernet duplex mode to Full-duplex */
bogdanm 0:9b334a45a8ff 1584 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
bogdanm 0:9b334a45a8ff 1585
bogdanm 0:9b334a45a8ff 1586 /* Set Ethernet speed to 100M */
bogdanm 0:9b334a45a8ff 1587 (heth->Init).Speed = ETH_SPEED_100M;
bogdanm 0:9b334a45a8ff 1588 }
bogdanm 0:9b334a45a8ff 1589
bogdanm 0:9b334a45a8ff 1590 /* Ethernet MAC default initialization **************************************/
bogdanm 0:9b334a45a8ff 1591 macinit.Watchdog = ETH_WATCHDOG_ENABLE;
bogdanm 0:9b334a45a8ff 1592 macinit.Jabber = ETH_JABBER_ENABLE;
bogdanm 0:9b334a45a8ff 1593 macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
bogdanm 0:9b334a45a8ff 1594 macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
bogdanm 0:9b334a45a8ff 1595 macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
bogdanm 0:9b334a45a8ff 1596 macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
bogdanm 0:9b334a45a8ff 1597 if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
bogdanm 0:9b334a45a8ff 1598 {
bogdanm 0:9b334a45a8ff 1599 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
bogdanm 0:9b334a45a8ff 1600 }
bogdanm 0:9b334a45a8ff 1601 else
bogdanm 0:9b334a45a8ff 1602 {
bogdanm 0:9b334a45a8ff 1603 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
bogdanm 0:9b334a45a8ff 1604 }
bogdanm 0:9b334a45a8ff 1605 macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
bogdanm 0:9b334a45a8ff 1606 macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
bogdanm 0:9b334a45a8ff 1607 macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
bogdanm 0:9b334a45a8ff 1608 macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
bogdanm 0:9b334a45a8ff 1609 macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
bogdanm 0:9b334a45a8ff 1610 macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
bogdanm 0:9b334a45a8ff 1611 macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
bogdanm 0:9b334a45a8ff 1612 macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
bogdanm 0:9b334a45a8ff 1613 macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
bogdanm 0:9b334a45a8ff 1614 macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
bogdanm 0:9b334a45a8ff 1615 macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
bogdanm 0:9b334a45a8ff 1616 macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
bogdanm 0:9b334a45a8ff 1617 macinit.HashTableHigh = 0x0;
bogdanm 0:9b334a45a8ff 1618 macinit.HashTableLow = 0x0;
bogdanm 0:9b334a45a8ff 1619 macinit.PauseTime = 0x0;
bogdanm 0:9b334a45a8ff 1620 macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
bogdanm 0:9b334a45a8ff 1621 macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
bogdanm 0:9b334a45a8ff 1622 macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
bogdanm 0:9b334a45a8ff 1623 macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
bogdanm 0:9b334a45a8ff 1624 macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
bogdanm 0:9b334a45a8ff 1625 macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
bogdanm 0:9b334a45a8ff 1626 macinit.VLANTagIdentifier = 0x0;
bogdanm 0:9b334a45a8ff 1627
bogdanm 0:9b334a45a8ff 1628 /*------------------------ ETHERNET MACCR Configuration --------------------*/
bogdanm 0:9b334a45a8ff 1629 /* Get the ETHERNET MACCR value */
bogdanm 0:9b334a45a8ff 1630 tmpreg1 = (heth->Instance)->MACCR;
bogdanm 0:9b334a45a8ff 1631 /* Clear WD, PCE, PS, TE and RE bits */
bogdanm 0:9b334a45a8ff 1632 tmpreg1 &= ETH_MACCR_CLEAR_MASK;
bogdanm 0:9b334a45a8ff 1633 /* Set the WD bit according to ETH Watchdog value */
bogdanm 0:9b334a45a8ff 1634 /* Set the JD: bit according to ETH Jabber value */
bogdanm 0:9b334a45a8ff 1635 /* Set the IFG bit according to ETH InterFrameGap value */
bogdanm 0:9b334a45a8ff 1636 /* Set the DCRS bit according to ETH CarrierSense value */
bogdanm 0:9b334a45a8ff 1637 /* Set the FES bit according to ETH Speed value */
bogdanm 0:9b334a45a8ff 1638 /* Set the DO bit according to ETH ReceiveOwn value */
bogdanm 0:9b334a45a8ff 1639 /* Set the LM bit according to ETH LoopbackMode value */
bogdanm 0:9b334a45a8ff 1640 /* Set the DM bit according to ETH Mode value */
bogdanm 0:9b334a45a8ff 1641 /* Set the IPCO bit according to ETH ChecksumOffload value */
bogdanm 0:9b334a45a8ff 1642 /* Set the DR bit according to ETH RetryTransmission value */
bogdanm 0:9b334a45a8ff 1643 /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
bogdanm 0:9b334a45a8ff 1644 /* Set the BL bit according to ETH BackOffLimit value */
bogdanm 0:9b334a45a8ff 1645 /* Set the DC bit according to ETH DeferralCheck value */
bogdanm 0:9b334a45a8ff 1646 tmpreg1 |= (uint32_t)(macinit.Watchdog |
bogdanm 0:9b334a45a8ff 1647 macinit.Jabber |
bogdanm 0:9b334a45a8ff 1648 macinit.InterFrameGap |
bogdanm 0:9b334a45a8ff 1649 macinit.CarrierSense |
bogdanm 0:9b334a45a8ff 1650 (heth->Init).Speed |
bogdanm 0:9b334a45a8ff 1651 macinit.ReceiveOwn |
bogdanm 0:9b334a45a8ff 1652 macinit.LoopbackMode |
bogdanm 0:9b334a45a8ff 1653 (heth->Init).DuplexMode |
bogdanm 0:9b334a45a8ff 1654 macinit.ChecksumOffload |
bogdanm 0:9b334a45a8ff 1655 macinit.RetryTransmission |
bogdanm 0:9b334a45a8ff 1656 macinit.AutomaticPadCRCStrip |
bogdanm 0:9b334a45a8ff 1657 macinit.BackOffLimit |
bogdanm 0:9b334a45a8ff 1658 macinit.DeferralCheck);
bogdanm 0:9b334a45a8ff 1659
bogdanm 0:9b334a45a8ff 1660 /* Write to ETHERNET MACCR */
bogdanm 0:9b334a45a8ff 1661 (heth->Instance)->MACCR = (uint32_t)tmpreg1;
bogdanm 0:9b334a45a8ff 1662
bogdanm 0:9b334a45a8ff 1663 /* Wait until the write operation will be taken into account:
bogdanm 0:9b334a45a8ff 1664 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1665 tmpreg1 = (heth->Instance)->MACCR;
bogdanm 0:9b334a45a8ff 1666 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1667 (heth->Instance)->MACCR = tmpreg1;
bogdanm 0:9b334a45a8ff 1668
bogdanm 0:9b334a45a8ff 1669 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
bogdanm 0:9b334a45a8ff 1670 /* Set the RA bit according to ETH ReceiveAll value */
bogdanm 0:9b334a45a8ff 1671 /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
bogdanm 0:9b334a45a8ff 1672 /* Set the PCF bit according to ETH PassControlFrames value */
bogdanm 0:9b334a45a8ff 1673 /* Set the DBF bit according to ETH BroadcastFramesReception value */
bogdanm 0:9b334a45a8ff 1674 /* Set the DAIF bit according to ETH DestinationAddrFilter value */
bogdanm 0:9b334a45a8ff 1675 /* Set the PR bit according to ETH PromiscuousMode value */
bogdanm 0:9b334a45a8ff 1676 /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
bogdanm 0:9b334a45a8ff 1677 /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
bogdanm 0:9b334a45a8ff 1678 /* Write to ETHERNET MACFFR */
bogdanm 0:9b334a45a8ff 1679 (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
bogdanm 0:9b334a45a8ff 1680 macinit.SourceAddrFilter |
bogdanm 0:9b334a45a8ff 1681 macinit.PassControlFrames |
bogdanm 0:9b334a45a8ff 1682 macinit.BroadcastFramesReception |
bogdanm 0:9b334a45a8ff 1683 macinit.DestinationAddrFilter |
bogdanm 0:9b334a45a8ff 1684 macinit.PromiscuousMode |
bogdanm 0:9b334a45a8ff 1685 macinit.MulticastFramesFilter |
bogdanm 0:9b334a45a8ff 1686 macinit.UnicastFramesFilter);
bogdanm 0:9b334a45a8ff 1687
bogdanm 0:9b334a45a8ff 1688 /* Wait until the write operation will be taken into account:
bogdanm 0:9b334a45a8ff 1689 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1690 tmpreg1 = (heth->Instance)->MACFFR;
bogdanm 0:9b334a45a8ff 1691 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1692 (heth->Instance)->MACFFR = tmpreg1;
bogdanm 0:9b334a45a8ff 1693
bogdanm 0:9b334a45a8ff 1694 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
bogdanm 0:9b334a45a8ff 1695 /* Write to ETHERNET MACHTHR */
bogdanm 0:9b334a45a8ff 1696 (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
bogdanm 0:9b334a45a8ff 1697
bogdanm 0:9b334a45a8ff 1698 /* Write to ETHERNET MACHTLR */
bogdanm 0:9b334a45a8ff 1699 (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
bogdanm 0:9b334a45a8ff 1700 /*----------------------- ETHERNET MACFCR Configuration -------------------*/
bogdanm 0:9b334a45a8ff 1701
bogdanm 0:9b334a45a8ff 1702 /* Get the ETHERNET MACFCR value */
bogdanm 0:9b334a45a8ff 1703 tmpreg1 = (heth->Instance)->MACFCR;
bogdanm 0:9b334a45a8ff 1704 /* Clear xx bits */
bogdanm 0:9b334a45a8ff 1705 tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
bogdanm 0:9b334a45a8ff 1706
bogdanm 0:9b334a45a8ff 1707 /* Set the PT bit according to ETH PauseTime value */
bogdanm 0:9b334a45a8ff 1708 /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
bogdanm 0:9b334a45a8ff 1709 /* Set the PLT bit according to ETH PauseLowThreshold value */
bogdanm 0:9b334a45a8ff 1710 /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
bogdanm 0:9b334a45a8ff 1711 /* Set the RFE bit according to ETH ReceiveFlowControl value */
bogdanm 0:9b334a45a8ff 1712 /* Set the TFE bit according to ETH TransmitFlowControl value */
bogdanm 0:9b334a45a8ff 1713 tmpreg1 |= (uint32_t)((macinit.PauseTime << 16) |
bogdanm 0:9b334a45a8ff 1714 macinit.ZeroQuantaPause |
bogdanm 0:9b334a45a8ff 1715 macinit.PauseLowThreshold |
bogdanm 0:9b334a45a8ff 1716 macinit.UnicastPauseFrameDetect |
bogdanm 0:9b334a45a8ff 1717 macinit.ReceiveFlowControl |
bogdanm 0:9b334a45a8ff 1718 macinit.TransmitFlowControl);
bogdanm 0:9b334a45a8ff 1719
bogdanm 0:9b334a45a8ff 1720 /* Write to ETHERNET MACFCR */
bogdanm 0:9b334a45a8ff 1721 (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
bogdanm 0:9b334a45a8ff 1722
bogdanm 0:9b334a45a8ff 1723 /* Wait until the write operation will be taken into account:
bogdanm 0:9b334a45a8ff 1724 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1725 tmpreg1 = (heth->Instance)->MACFCR;
bogdanm 0:9b334a45a8ff 1726 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1727 (heth->Instance)->MACFCR = tmpreg1;
bogdanm 0:9b334a45a8ff 1728
bogdanm 0:9b334a45a8ff 1729 /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
bogdanm 0:9b334a45a8ff 1730 /* Set the ETV bit according to ETH VLANTagComparison value */
bogdanm 0:9b334a45a8ff 1731 /* Set the VL bit according to ETH VLANTagIdentifier value */
bogdanm 0:9b334a45a8ff 1732 (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
bogdanm 0:9b334a45a8ff 1733 macinit.VLANTagIdentifier);
bogdanm 0:9b334a45a8ff 1734
bogdanm 0:9b334a45a8ff 1735 /* Wait until the write operation will be taken into account:
bogdanm 0:9b334a45a8ff 1736 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1737 tmpreg1 = (heth->Instance)->MACVLANTR;
bogdanm 0:9b334a45a8ff 1738 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1739 (heth->Instance)->MACVLANTR = tmpreg1;
bogdanm 0:9b334a45a8ff 1740
bogdanm 0:9b334a45a8ff 1741 /* Ethernet DMA default initialization ************************************/
bogdanm 0:9b334a45a8ff 1742 dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
bogdanm 0:9b334a45a8ff 1743 dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
bogdanm 0:9b334a45a8ff 1744 dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
bogdanm 0:9b334a45a8ff 1745 dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
bogdanm 0:9b334a45a8ff 1746 dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
bogdanm 0:9b334a45a8ff 1747 dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
bogdanm 0:9b334a45a8ff 1748 dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
bogdanm 0:9b334a45a8ff 1749 dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
bogdanm 0:9b334a45a8ff 1750 dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
bogdanm 0:9b334a45a8ff 1751 dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
bogdanm 0:9b334a45a8ff 1752 dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
bogdanm 0:9b334a45a8ff 1753 dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
bogdanm 0:9b334a45a8ff 1754 dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
bogdanm 0:9b334a45a8ff 1755 dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
bogdanm 0:9b334a45a8ff 1756 dmainit.DescriptorSkipLength = 0x0;
bogdanm 0:9b334a45a8ff 1757 dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
bogdanm 0:9b334a45a8ff 1758
bogdanm 0:9b334a45a8ff 1759 /* Get the ETHERNET DMAOMR value */
bogdanm 0:9b334a45a8ff 1760 tmpreg1 = (heth->Instance)->DMAOMR;
bogdanm 0:9b334a45a8ff 1761 /* Clear xx bits */
bogdanm 0:9b334a45a8ff 1762 tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
bogdanm 0:9b334a45a8ff 1763
bogdanm 0:9b334a45a8ff 1764 /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
bogdanm 0:9b334a45a8ff 1765 /* Set the RSF bit according to ETH ReceiveStoreForward value */
bogdanm 0:9b334a45a8ff 1766 /* Set the DFF bit according to ETH FlushReceivedFrame value */
bogdanm 0:9b334a45a8ff 1767 /* Set the TSF bit according to ETH TransmitStoreForward value */
bogdanm 0:9b334a45a8ff 1768 /* Set the TTC bit according to ETH TransmitThresholdControl value */
bogdanm 0:9b334a45a8ff 1769 /* Set the FEF bit according to ETH ForwardErrorFrames value */
bogdanm 0:9b334a45a8ff 1770 /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
bogdanm 0:9b334a45a8ff 1771 /* Set the RTC bit according to ETH ReceiveThresholdControl value */
bogdanm 0:9b334a45a8ff 1772 /* Set the OSF bit according to ETH SecondFrameOperate value */
bogdanm 0:9b334a45a8ff 1773 tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
bogdanm 0:9b334a45a8ff 1774 dmainit.ReceiveStoreForward |
bogdanm 0:9b334a45a8ff 1775 dmainit.FlushReceivedFrame |
bogdanm 0:9b334a45a8ff 1776 dmainit.TransmitStoreForward |
bogdanm 0:9b334a45a8ff 1777 dmainit.TransmitThresholdControl |
bogdanm 0:9b334a45a8ff 1778 dmainit.ForwardErrorFrames |
bogdanm 0:9b334a45a8ff 1779 dmainit.ForwardUndersizedGoodFrames |
bogdanm 0:9b334a45a8ff 1780 dmainit.ReceiveThresholdControl |
bogdanm 0:9b334a45a8ff 1781 dmainit.SecondFrameOperate);
bogdanm 0:9b334a45a8ff 1782
bogdanm 0:9b334a45a8ff 1783 /* Write to ETHERNET DMAOMR */
bogdanm 0:9b334a45a8ff 1784 (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
bogdanm 0:9b334a45a8ff 1785
bogdanm 0:9b334a45a8ff 1786 /* Wait until the write operation will be taken into account:
bogdanm 0:9b334a45a8ff 1787 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1788 tmpreg1 = (heth->Instance)->DMAOMR;
bogdanm 0:9b334a45a8ff 1789 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1790 (heth->Instance)->DMAOMR = tmpreg1;
bogdanm 0:9b334a45a8ff 1791
bogdanm 0:9b334a45a8ff 1792 /*----------------------- ETHERNET DMABMR Configuration ------------------*/
bogdanm 0:9b334a45a8ff 1793 /* Set the AAL bit according to ETH AddressAlignedBeats value */
bogdanm 0:9b334a45a8ff 1794 /* Set the FB bit according to ETH FixedBurst value */
bogdanm 0:9b334a45a8ff 1795 /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
bogdanm 0:9b334a45a8ff 1796 /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
bogdanm 0:9b334a45a8ff 1797 /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
bogdanm 0:9b334a45a8ff 1798 /* Set the DSL bit according to ETH DesciptorSkipLength value */
bogdanm 0:9b334a45a8ff 1799 /* Set the PR and DA bits according to ETH DMAArbitration value */
bogdanm 0:9b334a45a8ff 1800 (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
bogdanm 0:9b334a45a8ff 1801 dmainit.FixedBurst |
bogdanm 0:9b334a45a8ff 1802 dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
bogdanm 0:9b334a45a8ff 1803 dmainit.TxDMABurstLength |
bogdanm 0:9b334a45a8ff 1804 dmainit.EnhancedDescriptorFormat |
bogdanm 0:9b334a45a8ff 1805 (dmainit.DescriptorSkipLength << 2) |
bogdanm 0:9b334a45a8ff 1806 dmainit.DMAArbitration |
bogdanm 0:9b334a45a8ff 1807 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
bogdanm 0:9b334a45a8ff 1808
bogdanm 0:9b334a45a8ff 1809 /* Wait until the write operation will be taken into account:
bogdanm 0:9b334a45a8ff 1810 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1811 tmpreg1 = (heth->Instance)->DMABMR;
bogdanm 0:9b334a45a8ff 1812 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1813 (heth->Instance)->DMABMR = tmpreg1;
bogdanm 0:9b334a45a8ff 1814
bogdanm 0:9b334a45a8ff 1815 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
bogdanm 0:9b334a45a8ff 1816 {
bogdanm 0:9b334a45a8ff 1817 /* Enable the Ethernet Rx Interrupt */
bogdanm 0:9b334a45a8ff 1818 __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
bogdanm 0:9b334a45a8ff 1819 }
bogdanm 0:9b334a45a8ff 1820
bogdanm 0:9b334a45a8ff 1821 /* Initialize MAC address in ethernet MAC */
bogdanm 0:9b334a45a8ff 1822 ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
bogdanm 0:9b334a45a8ff 1823 }
bogdanm 0:9b334a45a8ff 1824
bogdanm 0:9b334a45a8ff 1825 /**
bogdanm 0:9b334a45a8ff 1826 * @brief Configures the selected MAC address.
bogdanm 0:9b334a45a8ff 1827 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1828 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1829 * @param MacAddr: The MAC address to configure
bogdanm 0:9b334a45a8ff 1830 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1831 * @arg ETH_MAC_Address0: MAC Address0
bogdanm 0:9b334a45a8ff 1832 * @arg ETH_MAC_Address1: MAC Address1
bogdanm 0:9b334a45a8ff 1833 * @arg ETH_MAC_Address2: MAC Address2
bogdanm 0:9b334a45a8ff 1834 * @arg ETH_MAC_Address3: MAC Address3
bogdanm 0:9b334a45a8ff 1835 * @param Addr: Pointer to MAC address buffer data (6 bytes)
bogdanm 0:9b334a45a8ff 1836 * @retval HAL status
bogdanm 0:9b334a45a8ff 1837 */
bogdanm 0:9b334a45a8ff 1838 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
bogdanm 0:9b334a45a8ff 1839 {
bogdanm 0:9b334a45a8ff 1840 uint32_t tmpreg1;
bogdanm 0:9b334a45a8ff 1841
bogdanm 0:9b334a45a8ff 1842 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1843 assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
bogdanm 0:9b334a45a8ff 1844
bogdanm 0:9b334a45a8ff 1845 /* Calculate the selected MAC address high register */
bogdanm 0:9b334a45a8ff 1846 tmpreg1 = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
bogdanm 0:9b334a45a8ff 1847 /* Load the selected MAC address high register */
bogdanm 0:9b334a45a8ff 1848 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1;
bogdanm 0:9b334a45a8ff 1849 /* Calculate the selected MAC address low register */
bogdanm 0:9b334a45a8ff 1850 tmpreg1 = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
bogdanm 0:9b334a45a8ff 1851
bogdanm 0:9b334a45a8ff 1852 /* Load the selected MAC address low register */
bogdanm 0:9b334a45a8ff 1853 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1;
bogdanm 0:9b334a45a8ff 1854 }
bogdanm 0:9b334a45a8ff 1855
bogdanm 0:9b334a45a8ff 1856 /**
bogdanm 0:9b334a45a8ff 1857 * @brief Enables the MAC transmission.
bogdanm 0:9b334a45a8ff 1858 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1859 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1860 * @retval None
bogdanm 0:9b334a45a8ff 1861 */
bogdanm 0:9b334a45a8ff 1862 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 1863 {
bogdanm 0:9b334a45a8ff 1864 __IO uint32_t tmpreg1 = 0;
bogdanm 0:9b334a45a8ff 1865
bogdanm 0:9b334a45a8ff 1866 /* Enable the MAC transmission */
bogdanm 0:9b334a45a8ff 1867 (heth->Instance)->MACCR |= ETH_MACCR_TE;
bogdanm 0:9b334a45a8ff 1868
bogdanm 0:9b334a45a8ff 1869 /* Wait until the write operation will be taken into account:
bogdanm 0:9b334a45a8ff 1870 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1871 tmpreg1 = (heth->Instance)->MACCR;
bogdanm 0:9b334a45a8ff 1872 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1873 (heth->Instance)->MACCR = tmpreg1;
bogdanm 0:9b334a45a8ff 1874 }
bogdanm 0:9b334a45a8ff 1875
bogdanm 0:9b334a45a8ff 1876 /**
bogdanm 0:9b334a45a8ff 1877 * @brief Disables the MAC transmission.
bogdanm 0:9b334a45a8ff 1878 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1879 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1880 * @retval None
bogdanm 0:9b334a45a8ff 1881 */
bogdanm 0:9b334a45a8ff 1882 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 1883 {
bogdanm 0:9b334a45a8ff 1884 __IO uint32_t tmpreg1 = 0;
bogdanm 0:9b334a45a8ff 1885
bogdanm 0:9b334a45a8ff 1886 /* Disable the MAC transmission */
bogdanm 0:9b334a45a8ff 1887 (heth->Instance)->MACCR &= ~ETH_MACCR_TE;
bogdanm 0:9b334a45a8ff 1888
bogdanm 0:9b334a45a8ff 1889 /* Wait until the write operation will be taken into account:
bogdanm 0:9b334a45a8ff 1890 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1891 tmpreg1 = (heth->Instance)->MACCR;
bogdanm 0:9b334a45a8ff 1892 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1893 (heth->Instance)->MACCR = tmpreg1;
bogdanm 0:9b334a45a8ff 1894 }
bogdanm 0:9b334a45a8ff 1895
bogdanm 0:9b334a45a8ff 1896 /**
bogdanm 0:9b334a45a8ff 1897 * @brief Enables the MAC reception.
bogdanm 0:9b334a45a8ff 1898 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1899 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1900 * @retval None
bogdanm 0:9b334a45a8ff 1901 */
bogdanm 0:9b334a45a8ff 1902 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 1903 {
bogdanm 0:9b334a45a8ff 1904 __IO uint32_t tmpreg1 = 0;
bogdanm 0:9b334a45a8ff 1905
bogdanm 0:9b334a45a8ff 1906 /* Enable the MAC reception */
bogdanm 0:9b334a45a8ff 1907 (heth->Instance)->MACCR |= ETH_MACCR_RE;
bogdanm 0:9b334a45a8ff 1908
bogdanm 0:9b334a45a8ff 1909 /* Wait until the write operation will be taken into account:
bogdanm 0:9b334a45a8ff 1910 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1911 tmpreg1 = (heth->Instance)->MACCR;
bogdanm 0:9b334a45a8ff 1912 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1913 (heth->Instance)->MACCR = tmpreg1;
bogdanm 0:9b334a45a8ff 1914 }
bogdanm 0:9b334a45a8ff 1915
bogdanm 0:9b334a45a8ff 1916 /**
bogdanm 0:9b334a45a8ff 1917 * @brief Disables the MAC reception.
bogdanm 0:9b334a45a8ff 1918 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1919 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1920 * @retval None
bogdanm 0:9b334a45a8ff 1921 */
bogdanm 0:9b334a45a8ff 1922 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 1923 {
bogdanm 0:9b334a45a8ff 1924 __IO uint32_t tmpreg1 = 0;
bogdanm 0:9b334a45a8ff 1925
bogdanm 0:9b334a45a8ff 1926 /* Disable the MAC reception */
bogdanm 0:9b334a45a8ff 1927 (heth->Instance)->MACCR &= ~ETH_MACCR_RE;
bogdanm 0:9b334a45a8ff 1928
bogdanm 0:9b334a45a8ff 1929 /* Wait until the write operation will be taken into account:
bogdanm 0:9b334a45a8ff 1930 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1931 tmpreg1 = (heth->Instance)->MACCR;
bogdanm 0:9b334a45a8ff 1932 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1933 (heth->Instance)->MACCR = tmpreg1;
bogdanm 0:9b334a45a8ff 1934 }
bogdanm 0:9b334a45a8ff 1935
bogdanm 0:9b334a45a8ff 1936 /**
bogdanm 0:9b334a45a8ff 1937 * @brief Enables the DMA transmission.
bogdanm 0:9b334a45a8ff 1938 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1939 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1940 * @retval None
bogdanm 0:9b334a45a8ff 1941 */
bogdanm 0:9b334a45a8ff 1942 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 1943 {
bogdanm 0:9b334a45a8ff 1944 /* Enable the DMA transmission */
bogdanm 0:9b334a45a8ff 1945 (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
bogdanm 0:9b334a45a8ff 1946 }
bogdanm 0:9b334a45a8ff 1947
bogdanm 0:9b334a45a8ff 1948 /**
bogdanm 0:9b334a45a8ff 1949 * @brief Disables the DMA transmission.
bogdanm 0:9b334a45a8ff 1950 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1951 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1952 * @retval None
bogdanm 0:9b334a45a8ff 1953 */
bogdanm 0:9b334a45a8ff 1954 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 1955 {
bogdanm 0:9b334a45a8ff 1956 /* Disable the DMA transmission */
bogdanm 0:9b334a45a8ff 1957 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
bogdanm 0:9b334a45a8ff 1958 }
bogdanm 0:9b334a45a8ff 1959
bogdanm 0:9b334a45a8ff 1960 /**
bogdanm 0:9b334a45a8ff 1961 * @brief Enables the DMA reception.
bogdanm 0:9b334a45a8ff 1962 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1963 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1964 * @retval None
bogdanm 0:9b334a45a8ff 1965 */
bogdanm 0:9b334a45a8ff 1966 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 1967 {
bogdanm 0:9b334a45a8ff 1968 /* Enable the DMA reception */
bogdanm 0:9b334a45a8ff 1969 (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
bogdanm 0:9b334a45a8ff 1970 }
bogdanm 0:9b334a45a8ff 1971
bogdanm 0:9b334a45a8ff 1972 /**
bogdanm 0:9b334a45a8ff 1973 * @brief Disables the DMA reception.
bogdanm 0:9b334a45a8ff 1974 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1975 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1976 * @retval None
bogdanm 0:9b334a45a8ff 1977 */
bogdanm 0:9b334a45a8ff 1978 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 1979 {
bogdanm 0:9b334a45a8ff 1980 /* Disable the DMA reception */
bogdanm 0:9b334a45a8ff 1981 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
bogdanm 0:9b334a45a8ff 1982 }
bogdanm 0:9b334a45a8ff 1983
bogdanm 0:9b334a45a8ff 1984 /**
bogdanm 0:9b334a45a8ff 1985 * @brief Clears the ETHERNET transmit FIFO.
bogdanm 0:9b334a45a8ff 1986 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1987 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1988 * @retval None
bogdanm 0:9b334a45a8ff 1989 */
bogdanm 0:9b334a45a8ff 1990 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 1991 {
bogdanm 0:9b334a45a8ff 1992 __IO uint32_t tmpreg1 = 0;
bogdanm 0:9b334a45a8ff 1993
bogdanm 0:9b334a45a8ff 1994 /* Set the Flush Transmit FIFO bit */
bogdanm 0:9b334a45a8ff 1995 (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
bogdanm 0:9b334a45a8ff 1996
bogdanm 0:9b334a45a8ff 1997 /* Wait until the write operation will be taken into account:
bogdanm 0:9b334a45a8ff 1998 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1999 tmpreg1 = (heth->Instance)->DMAOMR;
bogdanm 0:9b334a45a8ff 2000 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 2001 (heth->Instance)->DMAOMR = tmpreg1;
bogdanm 0:9b334a45a8ff 2002 }
bogdanm 0:9b334a45a8ff 2003
bogdanm 0:9b334a45a8ff 2004 /**
bogdanm 0:9b334a45a8ff 2005 * @}
bogdanm 0:9b334a45a8ff 2006 */
bogdanm 0:9b334a45a8ff 2007
mbed_official 19:112740acecfa 2008 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
mbed_official 19:112740acecfa 2009 STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
bogdanm 0:9b334a45a8ff 2010 #endif /* HAL_ETH_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 2011 /**
bogdanm 0:9b334a45a8ff 2012 * @}
bogdanm 0:9b334a45a8ff 2013 */
bogdanm 0:9b334a45a8ff 2014
bogdanm 0:9b334a45a8ff 2015 /**
bogdanm 0:9b334a45a8ff 2016 * @}
bogdanm 0:9b334a45a8ff 2017 */
bogdanm 0:9b334a45a8ff 2018
bogdanm 0:9b334a45a8ff 2019 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/