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targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/system_stm32f3xx.c@7:cf567a118ec7, 2015-10-16 (annotated)

Committer:
mbed_official
Date:
Fri Oct 16 07:45:35 2015 +0100
Revision:
7:cf567a118ec7
Child:
34:bb6061527455
Synchronized with git revision 856efdc67db6f7de450e78624ace39a2917f2f33



Full URL: https://github.com/mbedmicro/mbed/commit/856efdc67db6f7de450e78624ace39a2917f2f33/



NUCLEO_F303K8 - Dev nucleo f303k8

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 7:cf567a118ec7 1 /**
mbed_official 7:cf567a118ec7 2 ******************************************************************************
mbed_official 7:cf567a118ec7 3 * @file system_stm32f3xx.c
mbed_official 7:cf567a118ec7 4 * @author MCD Application Team
mbed_official 7:cf567a118ec7 5 * @version V2.1.0
mbed_official 7:cf567a118ec7 6 * @date 12-Sept-2014
mbed_official 7:cf567a118ec7 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
mbed_official 7:cf567a118ec7 8 *
mbed_official 7:cf567a118ec7 9 * 1. This file provides two functions and one global variable to be called from
mbed_official 7:cf567a118ec7 10 * user application:
mbed_official 7:cf567a118ec7 11 * - SystemInit(): This function is called at startup just after reset and
mbed_official 7:cf567a118ec7 12 * before branch to main program. This call is made inside
mbed_official 7:cf567a118ec7 13 * the "startup_stm32f3xx.s" file.
mbed_official 7:cf567a118ec7 14 *
mbed_official 7:cf567a118ec7 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 7:cf567a118ec7 16 * by the user application to setup the SysTick
mbed_official 7:cf567a118ec7 17 * timer or configure other parameters.
mbed_official 7:cf567a118ec7 18 *
mbed_official 7:cf567a118ec7 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 7:cf567a118ec7 20 * be called whenever the core clock is changed
mbed_official 7:cf567a118ec7 21 * during program execution.
mbed_official 7:cf567a118ec7 22 *
mbed_official 7:cf567a118ec7 23 * 2. After each device reset the HSI (8 MHz) is used as system clock source.
mbed_official 7:cf567a118ec7 24 * Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to
mbed_official 7:cf567a118ec7 25 * configure the system clock before to branch to main program.
mbed_official 7:cf567a118ec7 26 *
mbed_official 7:cf567a118ec7 27 * 3. This file configures the system clock as follows:
mbed_official 7:cf567a118ec7 28 *-----------------------------------------------------------------------------
mbed_official 7:cf567a118ec7 29 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
mbed_official 7:cf567a118ec7 30 * | (external 8 MHz clock) | (internal 8 MHz)
mbed_official 7:cf567a118ec7 31 * | 2- PLL_HSE_XTAL |
mbed_official 7:cf567a118ec7 32 * | (external 8 MHz xtal) |
mbed_official 7:cf567a118ec7 33 *-----------------------------------------------------------------------------
mbed_official 7:cf567a118ec7 34 * SYSCLK(MHz) | 72 | 64
mbed_official 7:cf567a118ec7 35 *-----------------------------------------------------------------------------
mbed_official 7:cf567a118ec7 36 * AHBCLK (MHz) | 72 | 64
mbed_official 7:cf567a118ec7 37 *-----------------------------------------------------------------------------
mbed_official 7:cf567a118ec7 38 * APB1CLK (MHz) | 36 | 32
mbed_official 7:cf567a118ec7 39 *-----------------------------------------------------------------------------
mbed_official 7:cf567a118ec7 40 * APB2CLK (MHz) | 72 | 64
mbed_official 7:cf567a118ec7 41 *-----------------------------------------------------------------------------
mbed_official 7:cf567a118ec7 42 * USB capable (48 MHz precise clock) | NO | NO
mbed_official 7:cf567a118ec7 43 *-----------------------------------------------------------------------------
mbed_official 7:cf567a118ec7 44 ******************************************************************************
mbed_official 7:cf567a118ec7 45 * @attention
mbed_official 7:cf567a118ec7 46 *
mbed_official 7:cf567a118ec7 47 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 7:cf567a118ec7 48 *
mbed_official 7:cf567a118ec7 49 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 7:cf567a118ec7 50 * are permitted provided that the following conditions are met:
mbed_official 7:cf567a118ec7 51 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 7:cf567a118ec7 52 * this list of conditions and the following disclaimer.
mbed_official 7:cf567a118ec7 53 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 7:cf567a118ec7 54 * this list of conditions and the following disclaimer in the documentation
mbed_official 7:cf567a118ec7 55 * and/or other materials provided with the distribution.
mbed_official 7:cf567a118ec7 56 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 7:cf567a118ec7 57 * may be used to endorse or promote products derived from this software
mbed_official 7:cf567a118ec7 58 * without specific prior written permission.
mbed_official 7:cf567a118ec7 59 *
mbed_official 7:cf567a118ec7 60 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 7:cf567a118ec7 61 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 7:cf567a118ec7 62 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 7:cf567a118ec7 63 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 7:cf567a118ec7 64 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 7:cf567a118ec7 65 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 7:cf567a118ec7 66 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 7:cf567a118ec7 67 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 7:cf567a118ec7 68 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 7:cf567a118ec7 69 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 7:cf567a118ec7 70 *
mbed_official 7:cf567a118ec7 71 ******************************************************************************
mbed_official 7:cf567a118ec7 72 */
mbed_official 7:cf567a118ec7 73
mbed_official 7:cf567a118ec7 74 /** @addtogroup CMSIS
mbed_official 7:cf567a118ec7 75 * @{
mbed_official 7:cf567a118ec7 76 */
mbed_official 7:cf567a118ec7 77
mbed_official 7:cf567a118ec7 78 /** @addtogroup stm32f3xx_system
mbed_official 7:cf567a118ec7 79 * @{
mbed_official 7:cf567a118ec7 80 */
mbed_official 7:cf567a118ec7 81
mbed_official 7:cf567a118ec7 82 /** @addtogroup STM32F3xx_System_Private_Includes
mbed_official 7:cf567a118ec7 83 * @{
mbed_official 7:cf567a118ec7 84 */
mbed_official 7:cf567a118ec7 85
mbed_official 7:cf567a118ec7 86 #include "stm32f3xx.h"
mbed_official 7:cf567a118ec7 87 #include "hal_tick.h"
mbed_official 7:cf567a118ec7 88
mbed_official 7:cf567a118ec7 89 /**
mbed_official 7:cf567a118ec7 90 * @}
mbed_official 7:cf567a118ec7 91 */
mbed_official 7:cf567a118ec7 92
mbed_official 7:cf567a118ec7 93 /** @addtogroup STM32F3xx_System_Private_TypesDefinitions
mbed_official 7:cf567a118ec7 94 * @{
mbed_official 7:cf567a118ec7 95 */
mbed_official 7:cf567a118ec7 96
mbed_official 7:cf567a118ec7 97 /**
mbed_official 7:cf567a118ec7 98 * @}
mbed_official 7:cf567a118ec7 99 */
mbed_official 7:cf567a118ec7 100
mbed_official 7:cf567a118ec7 101 /** @addtogroup STM32F3xx_System_Private_Defines
mbed_official 7:cf567a118ec7 102 * @{
mbed_official 7:cf567a118ec7 103 */
mbed_official 7:cf567a118ec7 104 #if !defined (HSE_VALUE)
mbed_official 7:cf567a118ec7 105 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
mbed_official 7:cf567a118ec7 106 This value can be provided and adapted by the user application. */
mbed_official 7:cf567a118ec7 107 #endif /* HSE_VALUE */
mbed_official 7:cf567a118ec7 108
mbed_official 7:cf567a118ec7 109 #if !defined (HSI_VALUE)
mbed_official 7:cf567a118ec7 110 #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
mbed_official 7:cf567a118ec7 111 This value can be provided and adapted by the user application. */
mbed_official 7:cf567a118ec7 112 #endif /* HSI_VALUE */
mbed_official 7:cf567a118ec7 113
mbed_official 7:cf567a118ec7 114 /*!< Uncomment the following line if you need to relocate your vector Table in
mbed_official 7:cf567a118ec7 115 Internal SRAM. */
mbed_official 7:cf567a118ec7 116 /* #define VECT_TAB_SRAM */
mbed_official 7:cf567a118ec7 117 #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
mbed_official 7:cf567a118ec7 118 This value must be a multiple of 0x200. */
mbed_official 7:cf567a118ec7 119 /**
mbed_official 7:cf567a118ec7 120 * @}
mbed_official 7:cf567a118ec7 121 */
mbed_official 7:cf567a118ec7 122
mbed_official 7:cf567a118ec7 123 /** @addtogroup STM32F3xx_System_Private_Macros
mbed_official 7:cf567a118ec7 124 * @{
mbed_official 7:cf567a118ec7 125 */
mbed_official 7:cf567a118ec7 126
mbed_official 7:cf567a118ec7 127 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
mbed_official 7:cf567a118ec7 128 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
mbed_official 7:cf567a118ec7 129 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
mbed_official 7:cf567a118ec7 130
mbed_official 7:cf567a118ec7 131 /**
mbed_official 7:cf567a118ec7 132 * @}
mbed_official 7:cf567a118ec7 133 */
mbed_official 7:cf567a118ec7 134
mbed_official 7:cf567a118ec7 135 /** @addtogroup STM32F3xx_System_Private_Variables
mbed_official 7:cf567a118ec7 136 * @{
mbed_official 7:cf567a118ec7 137 */
mbed_official 7:cf567a118ec7 138 /* This variable is updated in three ways:
mbed_official 7:cf567a118ec7 139 1) by calling CMSIS function SystemCoreClockUpdate()
mbed_official 7:cf567a118ec7 140 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
mbed_official 7:cf567a118ec7 141 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
mbed_official 7:cf567a118ec7 142 Note: If you use this function to configure the system clock there is no need to
mbed_official 7:cf567a118ec7 143 call the 2 first functions listed above, since SystemCoreClock variable is
mbed_official 7:cf567a118ec7 144 updated automatically.
mbed_official 7:cf567a118ec7 145 */
mbed_official 7:cf567a118ec7 146 uint32_t SystemCoreClock = 72000000;
mbed_official 7:cf567a118ec7 147 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 7:cf567a118ec7 148
mbed_official 7:cf567a118ec7 149 /**
mbed_official 7:cf567a118ec7 150 * @}
mbed_official 7:cf567a118ec7 151 */
mbed_official 7:cf567a118ec7 152
mbed_official 7:cf567a118ec7 153 /** @addtogroup STM32F3xx_System_Private_FunctionPrototypes
mbed_official 7:cf567a118ec7 154 * @{
mbed_official 7:cf567a118ec7 155 */
mbed_official 7:cf567a118ec7 156
mbed_official 7:cf567a118ec7 157 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 7:cf567a118ec7 158 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
mbed_official 7:cf567a118ec7 159 #endif
mbed_official 7:cf567a118ec7 160
mbed_official 7:cf567a118ec7 161 uint8_t SetSysClock_PLL_HSI(void);
mbed_official 7:cf567a118ec7 162
mbed_official 7:cf567a118ec7 163 /**
mbed_official 7:cf567a118ec7 164 * @}
mbed_official 7:cf567a118ec7 165 */
mbed_official 7:cf567a118ec7 166
mbed_official 7:cf567a118ec7 167 /** @addtogroup STM32F3xx_System_Private_Functions
mbed_official 7:cf567a118ec7 168 * @{
mbed_official 7:cf567a118ec7 169 */
mbed_official 7:cf567a118ec7 170
mbed_official 7:cf567a118ec7 171 /**
mbed_official 7:cf567a118ec7 172 * @brief Setup the microcontroller system
mbed_official 7:cf567a118ec7 173 * Initialize the FPU setting, vector table location and the PLL configuration is reset.
mbed_official 7:cf567a118ec7 174 * @param None
mbed_official 7:cf567a118ec7 175 * @retval None
mbed_official 7:cf567a118ec7 176 */
mbed_official 7:cf567a118ec7 177 void SystemInit(void)
mbed_official 7:cf567a118ec7 178 {
mbed_official 7:cf567a118ec7 179 /* FPU settings ------------------------------------------------------------*/
mbed_official 7:cf567a118ec7 180 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mbed_official 7:cf567a118ec7 181 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
mbed_official 7:cf567a118ec7 182 #endif
mbed_official 7:cf567a118ec7 183
mbed_official 7:cf567a118ec7 184 /* Reset the RCC clock configuration to the default reset state ------------*/
mbed_official 7:cf567a118ec7 185 /* Set HSION bit */
mbed_official 7:cf567a118ec7 186 RCC->CR |= (uint32_t)0x00000001;
mbed_official 7:cf567a118ec7 187
mbed_official 7:cf567a118ec7 188 /* Reset CFGR register */
mbed_official 7:cf567a118ec7 189 RCC->CFGR &= 0xF87FC00C;
mbed_official 7:cf567a118ec7 190
mbed_official 7:cf567a118ec7 191 /* Reset HSEON, CSSON and PLLON bits */
mbed_official 7:cf567a118ec7 192 RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official 7:cf567a118ec7 193
mbed_official 7:cf567a118ec7 194 /* Reset HSEBYP bit */
mbed_official 7:cf567a118ec7 195 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 7:cf567a118ec7 196
mbed_official 7:cf567a118ec7 197 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
mbed_official 7:cf567a118ec7 198 RCC->CFGR &= (uint32_t)0xFF80FFFF;
mbed_official 7:cf567a118ec7 199
mbed_official 7:cf567a118ec7 200 /* Reset PREDIV1[3:0] bits */
mbed_official 7:cf567a118ec7 201 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
mbed_official 7:cf567a118ec7 202
mbed_official 7:cf567a118ec7 203 /* Reset USARTSW[1:0], I2CSW and TIMs bits */
mbed_official 7:cf567a118ec7 204 RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
mbed_official 7:cf567a118ec7 205
mbed_official 7:cf567a118ec7 206 /* Disable all interrupts */
mbed_official 7:cf567a118ec7 207 RCC->CIR = 0x00000000;
mbed_official 7:cf567a118ec7 208
mbed_official 7:cf567a118ec7 209 #ifdef VECT_TAB_SRAM
mbed_official 7:cf567a118ec7 210 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
mbed_official 7:cf567a118ec7 211 #else
mbed_official 7:cf567a118ec7 212 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
mbed_official 7:cf567a118ec7 213 #endif
mbed_official 7:cf567a118ec7 214
mbed_official 7:cf567a118ec7 215 /* Configure the Cube driver */
mbed_official 7:cf567a118ec7 216 SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
mbed_official 7:cf567a118ec7 217 HAL_Init();
mbed_official 7:cf567a118ec7 218
mbed_official 7:cf567a118ec7 219 /* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official 7:cf567a118ec7 220 AHB/APBx prescalers and Flash settings */
mbed_official 7:cf567a118ec7 221 SetSysClock();
mbed_official 7:cf567a118ec7 222
mbed_official 7:cf567a118ec7 223 /* Reset the timer to avoid issues after the RAM initialization */
mbed_official 7:cf567a118ec7 224 TIM_MST_RESET_ON;
mbed_official 7:cf567a118ec7 225 TIM_MST_RESET_OFF;
mbed_official 7:cf567a118ec7 226 }
mbed_official 7:cf567a118ec7 227
mbed_official 7:cf567a118ec7 228 /**
mbed_official 7:cf567a118ec7 229 * @brief Update SystemCoreClock variable according to Clock Register Values.
mbed_official 7:cf567a118ec7 230 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 7:cf567a118ec7 231 * be used by the user application to setup the SysTick timer or configure
mbed_official 7:cf567a118ec7 232 * other parameters.
mbed_official 7:cf567a118ec7 233 *
mbed_official 7:cf567a118ec7 234 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 7:cf567a118ec7 235 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 7:cf567a118ec7 236 * based on this variable will be incorrect.
mbed_official 7:cf567a118ec7 237 *
mbed_official 7:cf567a118ec7 238 * @note - The system frequency computed by this function is not the real
mbed_official 7:cf567a118ec7 239 * frequency in the chip. It is calculated based on the predefined
mbed_official 7:cf567a118ec7 240 * constant and the selected clock source:
mbed_official 7:cf567a118ec7 241 *
mbed_official 7:cf567a118ec7 242 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 7:cf567a118ec7 243 *
mbed_official 7:cf567a118ec7 244 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 7:cf567a118ec7 245 *
mbed_official 7:cf567a118ec7 246 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 7:cf567a118ec7 247 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 7:cf567a118ec7 248 *
mbed_official 7:cf567a118ec7 249 * (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value
mbed_official 7:cf567a118ec7 250 * 8 MHz) but the real value may vary depending on the variations
mbed_official 7:cf567a118ec7 251 * in voltage and temperature.
mbed_official 7:cf567a118ec7 252 *
mbed_official 7:cf567a118ec7 253 * (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value
mbed_official 7:cf567a118ec7 254 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 7:cf567a118ec7 255 * frequency of the crystal used. Otherwise, this function may
mbed_official 7:cf567a118ec7 256 * have wrong result.
mbed_official 7:cf567a118ec7 257 *
mbed_official 7:cf567a118ec7 258 * - The result of this function could be not correct when using fractional
mbed_official 7:cf567a118ec7 259 * value for HSE crystal.
mbed_official 7:cf567a118ec7 260 *
mbed_official 7:cf567a118ec7 261 * @param None
mbed_official 7:cf567a118ec7 262 * @retval None
mbed_official 7:cf567a118ec7 263 */
mbed_official 7:cf567a118ec7 264 void SystemCoreClockUpdate (void)
mbed_official 7:cf567a118ec7 265 {
mbed_official 7:cf567a118ec7 266 uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
mbed_official 7:cf567a118ec7 267
mbed_official 7:cf567a118ec7 268 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 7:cf567a118ec7 269 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 7:cf567a118ec7 270
mbed_official 7:cf567a118ec7 271 switch (tmp)
mbed_official 7:cf567a118ec7 272 {
mbed_official 7:cf567a118ec7 273 case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
mbed_official 7:cf567a118ec7 274 SystemCoreClock = HSI_VALUE;
mbed_official 7:cf567a118ec7 275 break;
mbed_official 7:cf567a118ec7 276 case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
mbed_official 7:cf567a118ec7 277 SystemCoreClock = HSE_VALUE;
mbed_official 7:cf567a118ec7 278 break;
mbed_official 7:cf567a118ec7 279 case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
mbed_official 7:cf567a118ec7 280 /* Get PLL clock source and multiplication factor ----------------------*/
mbed_official 7:cf567a118ec7 281 pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
mbed_official 7:cf567a118ec7 282 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official 7:cf567a118ec7 283 pllmull = ( pllmull >> 18) + 2;
mbed_official 7:cf567a118ec7 284
mbed_official 7:cf567a118ec7 285 #if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
mbed_official 7:cf567a118ec7 286 predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
mbed_official 7:cf567a118ec7 287 if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
mbed_official 7:cf567a118ec7 288 {
mbed_official 7:cf567a118ec7 289 /* HSE oscillator clock selected as PREDIV1 clock entry */
mbed_official 7:cf567a118ec7 290 SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
mbed_official 7:cf567a118ec7 291 }
mbed_official 7:cf567a118ec7 292 else
mbed_official 7:cf567a118ec7 293 {
mbed_official 7:cf567a118ec7 294 /* HSI oscillator clock selected as PREDIV1 clock entry */
mbed_official 7:cf567a118ec7 295 SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull;
mbed_official 7:cf567a118ec7 296 }
mbed_official 7:cf567a118ec7 297 #else
mbed_official 7:cf567a118ec7 298 if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2)
mbed_official 7:cf567a118ec7 299 {
mbed_official 7:cf567a118ec7 300 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
mbed_official 7:cf567a118ec7 301 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
mbed_official 7:cf567a118ec7 302 }
mbed_official 7:cf567a118ec7 303 else
mbed_official 7:cf567a118ec7 304 {
mbed_official 7:cf567a118ec7 305 predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
mbed_official 7:cf567a118ec7 306 /* HSE oscillator clock selected as PREDIV1 clock entry */
mbed_official 7:cf567a118ec7 307 SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
mbed_official 7:cf567a118ec7 308 }
mbed_official 7:cf567a118ec7 309 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
mbed_official 7:cf567a118ec7 310 break;
mbed_official 7:cf567a118ec7 311 default: /* HSI used as system clock */
mbed_official 7:cf567a118ec7 312 SystemCoreClock = HSI_VALUE;
mbed_official 7:cf567a118ec7 313 break;
mbed_official 7:cf567a118ec7 314 }
mbed_official 7:cf567a118ec7 315 /* Compute HCLK clock frequency ----------------*/
mbed_official 7:cf567a118ec7 316 /* Get HCLK prescaler */
mbed_official 7:cf567a118ec7 317 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 7:cf567a118ec7 318 /* HCLK clock frequency */
mbed_official 7:cf567a118ec7 319 SystemCoreClock >>= tmp;
mbed_official 7:cf567a118ec7 320 }
mbed_official 7:cf567a118ec7 321
mbed_official 7:cf567a118ec7 322 /**
mbed_official 7:cf567a118ec7 323 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
mbed_official 7:cf567a118ec7 324 * AHB/APBx prescalers and Flash settings
mbed_official 7:cf567a118ec7 325 * @note This function should be called only once the RCC clock configuration
mbed_official 7:cf567a118ec7 326 * is reset to the default reset state (done in SystemInit() function).
mbed_official 7:cf567a118ec7 327 * @param None
mbed_official 7:cf567a118ec7 328 * @retval None
mbed_official 7:cf567a118ec7 329 */
mbed_official 7:cf567a118ec7 330 void SetSysClock(void)
mbed_official 7:cf567a118ec7 331 {
mbed_official 7:cf567a118ec7 332 /* 1- Try to start with HSE and external clock */
mbed_official 7:cf567a118ec7 333 #if USE_PLL_HSE_EXTC != 0
mbed_official 7:cf567a118ec7 334 if (SetSysClock_PLL_HSE(1) == 0)
mbed_official 7:cf567a118ec7 335 #endif
mbed_official 7:cf567a118ec7 336 {
mbed_official 7:cf567a118ec7 337 /* 2- If fail try to start with HSE and external xtal */
mbed_official 7:cf567a118ec7 338 #if USE_PLL_HSE_XTAL != 0
mbed_official 7:cf567a118ec7 339 if (SetSysClock_PLL_HSE(0) == 0)
mbed_official 7:cf567a118ec7 340 #endif
mbed_official 7:cf567a118ec7 341 {
mbed_official 7:cf567a118ec7 342 /* 3- If fail start with HSI clock */
mbed_official 7:cf567a118ec7 343 if (SetSysClock_PLL_HSI() == 0)
mbed_official 7:cf567a118ec7 344 {
mbed_official 7:cf567a118ec7 345 while(1)
mbed_official 7:cf567a118ec7 346 {
mbed_official 7:cf567a118ec7 347 // [TODO] Put something here to tell the user that a problem occured...
mbed_official 7:cf567a118ec7 348 }
mbed_official 7:cf567a118ec7 349 }
mbed_official 7:cf567a118ec7 350 }
mbed_official 7:cf567a118ec7 351 }
mbed_official 7:cf567a118ec7 352
mbed_official 7:cf567a118ec7 353 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 7:cf567a118ec7 354 //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 72 MHz or 64 MHz
mbed_official 7:cf567a118ec7 355 }
mbed_official 7:cf567a118ec7 356
mbed_official 7:cf567a118ec7 357 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 7:cf567a118ec7 358 /******************************************************************************/
mbed_official 7:cf567a118ec7 359 /* PLL (clocked by HSE) used as System clock source */
mbed_official 7:cf567a118ec7 360 /******************************************************************************/
mbed_official 7:cf567a118ec7 361 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
mbed_official 7:cf567a118ec7 362 {
mbed_official 7:cf567a118ec7 363 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 7:cf567a118ec7 364 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 7:cf567a118ec7 365
mbed_official 7:cf567a118ec7 366 /* Enable HSE oscillator and activate PLL with HSE as source */
mbed_official 7:cf567a118ec7 367 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
mbed_official 7:cf567a118ec7 368 if (bypass == 0)
mbed_official 7:cf567a118ec7 369 {
mbed_official 7:cf567a118ec7 370 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
mbed_official 7:cf567a118ec7 371 }
mbed_official 7:cf567a118ec7 372 else
mbed_official 7:cf567a118ec7 373 {
mbed_official 7:cf567a118ec7 374 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
mbed_official 7:cf567a118ec7 375 }
mbed_official 7:cf567a118ec7 376 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 7:cf567a118ec7 377 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
mbed_official 7:cf567a118ec7 378 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
mbed_official 7:cf567a118ec7 379 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 7:cf567a118ec7 380 {
mbed_official 7:cf567a118ec7 381 return 0; // FAIL
mbed_official 7:cf567a118ec7 382 }
mbed_official 7:cf567a118ec7 383
mbed_official 7:cf567a118ec7 384 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official 7:cf567a118ec7 385 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 7:cf567a118ec7 386 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
mbed_official 7:cf567a118ec7 387 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz
mbed_official 7:cf567a118ec7 388 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz
mbed_official 7:cf567a118ec7 389 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz
mbed_official 7:cf567a118ec7 390 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
mbed_official 7:cf567a118ec7 391 {
mbed_official 7:cf567a118ec7 392 return 0; // FAIL
mbed_official 7:cf567a118ec7 393 }
mbed_official 7:cf567a118ec7 394
mbed_official 7:cf567a118ec7 395 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 7:cf567a118ec7 396 //if (bypass == 0)
mbed_official 7:cf567a118ec7 397 // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
mbed_official 7:cf567a118ec7 398 //else
mbed_official 7:cf567a118ec7 399 // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock
mbed_official 7:cf567a118ec7 400
mbed_official 7:cf567a118ec7 401 return 1; // OK
mbed_official 7:cf567a118ec7 402 }
mbed_official 7:cf567a118ec7 403 #endif
mbed_official 7:cf567a118ec7 404
mbed_official 7:cf567a118ec7 405 /******************************************************************************/
mbed_official 7:cf567a118ec7 406 /* PLL (clocked by HSI) used as System clock source */
mbed_official 7:cf567a118ec7 407 /******************************************************************************/
mbed_official 7:cf567a118ec7 408 uint8_t SetSysClock_PLL_HSI(void)
mbed_official 7:cf567a118ec7 409 {
mbed_official 7:cf567a118ec7 410 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 7:cf567a118ec7 411 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 7:cf567a118ec7 412
mbed_official 7:cf567a118ec7 413 /* Enable HSI oscillator and activate PLL with HSI as source */
mbed_official 7:cf567a118ec7 414 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
mbed_official 7:cf567a118ec7 415 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
mbed_official 7:cf567a118ec7 416 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
mbed_official 7:cf567a118ec7 417 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
mbed_official 7:cf567a118ec7 418 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 7:cf567a118ec7 419 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
mbed_official 7:cf567a118ec7 420 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)
mbed_official 7:cf567a118ec7 421 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 7:cf567a118ec7 422 {
mbed_official 7:cf567a118ec7 423 return 0; // FAIL
mbed_official 7:cf567a118ec7 424 }
mbed_official 7:cf567a118ec7 425
mbed_official 7:cf567a118ec7 426 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official 7:cf567a118ec7 427 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 7:cf567a118ec7 428 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
mbed_official 7:cf567a118ec7 429 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 64 MHz
mbed_official 7:cf567a118ec7 430 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 32 MHz
mbed_official 7:cf567a118ec7 431 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 64 MHz
mbed_official 7:cf567a118ec7 432 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
mbed_official 7:cf567a118ec7 433 {
mbed_official 7:cf567a118ec7 434 return 0; // FAIL
mbed_official 7:cf567a118ec7 435 }
mbed_official 7:cf567a118ec7 436
mbed_official 7:cf567a118ec7 437 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 7:cf567a118ec7 438 //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz
mbed_official 7:cf567a118ec7 439
mbed_official 7:cf567a118ec7 440 return 1; // OK
mbed_official 7:cf567a118ec7 441 }
mbed_official 7:cf567a118ec7 442
mbed_official 7:cf567a118ec7 443 /**
mbed_official 7:cf567a118ec7 444 * @}
mbed_official 7:cf567a118ec7 445 */
mbed_official 7:cf567a118ec7 446
mbed_official 7:cf567a118ec7 447 /**
mbed_official 7:cf567a118ec7 448 * @}
mbed_official 7:cf567a118ec7 449 */
mbed_official 7:cf567a118ec7 450
mbed_official 7:cf567a118ec7 451 /**
mbed_official 7:cf567a118ec7 452 * @}
mbed_official 7:cf567a118ec7 453 */
mbed_official 7:cf567a118ec7 454
mbed_official 7:cf567a118ec7 455 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
mbed_official 7:cf567a118ec7 456