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targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_spi.c@70:b3a5af880266, 2016-02-23 (annotated)

Committer:
neurofun
Date:
Tue Feb 23 21:59:35 2016 +0000
Revision:
70:b3a5af880266
Parent:
0:9b334a45a8ff 
Edited DAC routines to allow for the simultaneous use of three channels from two DACs as seen on the STM32F334R8 and STM32F303K8. Edited ADC routines to allow for the simultaneous use of more than one ADC.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f30x_spi.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.1.0
bogdanm 0:9b334a45a8ff 6 * @date 27-February-2014
bogdanm 0:9b334a45a8ff 7 * @brief This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 8 * functionalities of the Serial peripheral interface (SPI):
bogdanm 0:9b334a45a8ff 9 * + Initialization and Configuration
bogdanm 0:9b334a45a8ff 10 * + Data transfers functions
bogdanm 0:9b334a45a8ff 11 * + Hardware CRC Calculation
bogdanm 0:9b334a45a8ff 12 * + DMA transfers management
bogdanm 0:9b334a45a8ff 13 * + Interrupts and flags management
bogdanm 0:9b334a45a8ff 14 *
bogdanm 0:9b334a45a8ff 15 * @verbatim
bogdanm 0:9b334a45a8ff 16
bogdanm 0:9b334a45a8ff 17
bogdanm 0:9b334a45a8ff 18 ===============================================================================
bogdanm 0:9b334a45a8ff 19 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 20 ===============================================================================
bogdanm 0:9b334a45a8ff 21 [..]
bogdanm 0:9b334a45a8ff 22 (#) Enable peripheral clock using RCC_APBPeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE)
bogdanm 0:9b334a45a8ff 23 function for SPI1 or using RCC_APBPeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE)
bogdanm 0:9b334a45a8ff 24 function for SPI2.
bogdanm 0:9b334a45a8ff 25 (#) Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHBPeriphClockCmd()
bogdanm 0:9b334a45a8ff 26 function.
bogdanm 0:9b334a45a8ff 27 (#) Peripherals alternate function:
bogdanm 0:9b334a45a8ff 28 (++) Connect the pin to the desired peripherals' Alternate
bogdanm 0:9b334a45a8ff 29 Function (AF) using GPIO_PinAFConfig() function.
bogdanm 0:9b334a45a8ff 30 (++) Configure the desired pin in alternate function by:
bogdanm 0:9b334a45a8ff 31 GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
bogdanm 0:9b334a45a8ff 32 (++) Select the type, pull-up/pull-down and output speed via
bogdanm 0:9b334a45a8ff 33 GPIO_PuPd, GPIO_OType and GPIO_Speed members.
bogdanm 0:9b334a45a8ff 34 (++) Call GPIO_Init() function.
bogdanm 0:9b334a45a8ff 35 (#) Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave
bogdanm 0:9b334a45a8ff 36 Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
bogdanm 0:9b334a45a8ff 37 function in SPI mode. In I2S mode, program the Mode, Standard, Data Format,
bogdanm 0:9b334a45a8ff 38 MCLK Output, Audio frequency and Polarity using I2S_Init() function.
bogdanm 0:9b334a45a8ff 39 (#) Configure the FIFO threshold using SPI_RxFIFOThresholdConfig() to select
bogdanm 0:9b334a45a8ff 40 at which threshold the RXNE event is generated.
bogdanm 0:9b334a45a8ff 41 (#) Enable the NVIC and the corresponding interrupt using the function
bogdanm 0:9b334a45a8ff 42 SPI_I2S_ITConfig() if you need to use interrupt mode.
bogdanm 0:9b334a45a8ff 43 (#) When using the DMA mode
bogdanm 0:9b334a45a8ff 44 (++) Configure the DMA using DMA_Init() function.
bogdanm 0:9b334a45a8ff 45 (++) Active the needed channel Request using SPI_I2S_DMACmd() function.
bogdanm 0:9b334a45a8ff 46 (#) Enable the SPI using the SPI_Cmd() function or enable the I2S using
bogdanm 0:9b334a45a8ff 47 I2S_Cmd().
bogdanm 0:9b334a45a8ff 48 (#) Enable the DMA using the DMA_Cmd() function when using DMA mode.
bogdanm 0:9b334a45a8ff 49 (#) Optionally you can enable/configure the following parameters without
bogdanm 0:9b334a45a8ff 50 re-initialization (i.e there is no need to call again SPI_Init() function):
bogdanm 0:9b334a45a8ff 51 (++) When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)
bogdanm 0:9b334a45a8ff 52 is programmed as Data direction parameter using the SPI_Init() function
bogdanm 0:9b334a45a8ff 53 it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx
bogdanm 0:9b334a45a8ff 54 using the SPI_BiDirectionalLineConfig() function.
bogdanm 0:9b334a45a8ff 55 (++) When SPI_NSS_Soft is selected as Slave Select Management parameter
bogdanm 0:9b334a45a8ff 56 using the SPI_Init() function it can be possible to manage the
bogdanm 0:9b334a45a8ff 57 NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.
bogdanm 0:9b334a45a8ff 58 (++) Reconfigure the data size using the SPI_DataSizeConfig() function.
bogdanm 0:9b334a45a8ff 59 (++) Enable or disable the SS output using the SPI_SSOutputCmd() function.
bogdanm 0:9b334a45a8ff 60 (#) To use the CRC Hardware calculation feature refer to the Peripheral
bogdanm 0:9b334a45a8ff 61 CRC hardware Calculation subsection.
bogdanm 0:9b334a45a8ff 62 [..] It is possible to use SPI in I2S full duplex mode, in this case, each SPI
bogdanm 0:9b334a45a8ff 63 peripheral is able to manage sending and receiving data simultaneously
bogdanm 0:9b334a45a8ff 64 using two data lines. Each SPI peripheral has an extended block called I2Sxext
bogdanm 0:9b334a45a8ff 65 (ie. I2S2ext for SPI2 and I2S3ext for SPI3).
bogdanm 0:9b334a45a8ff 66 The extension block is not a full SPI IP, it is used only as I2S slave to
bogdanm 0:9b334a45a8ff 67 implement full duplex mode. The extension block uses the same clock sources
bogdanm 0:9b334a45a8ff 68 as its master.
bogdanm 0:9b334a45a8ff 69 To configure I2S full duplex you have to:
bogdanm 0:9b334a45a8ff 70 (#) Configure SPIx in I2S mode (I2S_Init() function) as described above.
bogdanm 0:9b334a45a8ff 71 (#) Call the I2S_FullDuplexConfig() function using the same strucutre passed to
bogdanm 0:9b334a45a8ff 72 I2S_Init() function.
bogdanm 0:9b334a45a8ff 73 (#) Call I2S_Cmd() for SPIx then for its extended block.
bogdanm 0:9b334a45a8ff 74 (#) Configure interrupts or DMA requests and to get/clear flag status,
bogdanm 0:9b334a45a8ff 75 use I2Sxext instance for the extension block.
bogdanm 0:9b334a45a8ff 76 [..] Functions that can be called with I2Sxext instances are:
bogdanm 0:9b334a45a8ff 77 I2S_Cmd(), I2S_FullDuplexConfig(), SPI_I2S_ReceiveData16(), SPI_I2S_SendData16(),
bogdanm 0:9b334a45a8ff 78 SPI_I2S_DMACmd(), SPI_I2S_ITConfig(), SPI_I2S_GetFlagStatus(), SPI_I2S_ClearFlag(),
bogdanm 0:9b334a45a8ff 79 SPI_I2S_GetITStatus() and SPI_I2S_ClearITPendingBit().
bogdanm 0:9b334a45a8ff 80 [..] Example: To use SPI3 in Full duplex mode (SPI3 is Master Tx, I2S3ext is Slave Rx):
bogdanm 0:9b334a45a8ff 81 [..] RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);
bogdanm 0:9b334a45a8ff 82 I2S_StructInit(&I2SInitStruct);
bogdanm 0:9b334a45a8ff 83 I2SInitStruct.Mode = I2S_Mode_MasterTx;
bogdanm 0:9b334a45a8ff 84 I2S_Init(SPI3, &I2SInitStruct);
bogdanm 0:9b334a45a8ff 85 I2S_FullDuplexConfig(SPI3ext, &I2SInitStruct)
bogdanm 0:9b334a45a8ff 86 I2S_Cmd(SPI3, ENABLE);
bogdanm 0:9b334a45a8ff 87 I2S_Cmd(SPI3ext, ENABLE);
bogdanm 0:9b334a45a8ff 88 ...
bogdanm 0:9b334a45a8ff 89 while (SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
bogdanm 0:9b334a45a8ff 90 {}
bogdanm 0:9b334a45a8ff 91 SPI_I2S_SendData16(SPI3, txdata[i]);
bogdanm 0:9b334a45a8ff 92 ...
bogdanm 0:9b334a45a8ff 93 while (SPI_I2S_GetFlagStatus(I2S3ext, SPI_FLAG_RXNE) == RESET)
bogdanm 0:9b334a45a8ff 94 {}
bogdanm 0:9b334a45a8ff 95 rxdata[i] = SPI_I2S_ReceiveData16(I2S3ext);
bogdanm 0:9b334a45a8ff 96 ...
bogdanm 0:9b334a45a8ff 97 [..]
bogdanm 0:9b334a45a8ff 98 (@) In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd()
bogdanm 0:9b334a45a8ff 99 just after calling the function SPI_Init().
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 @endverbatim
bogdanm 0:9b334a45a8ff 102 ******************************************************************************
bogdanm 0:9b334a45a8ff 103 * @attention
bogdanm 0:9b334a45a8ff 104 *
bogdanm 0:9b334a45a8ff 105 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 106 *
bogdanm 0:9b334a45a8ff 107 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 108 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 109 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 110 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 111 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 112 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 113 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 114 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 115 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 116 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 117 *
bogdanm 0:9b334a45a8ff 118 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 119 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 120 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 121 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 122 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 123 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 124 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 125 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 126 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 127 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 128 *
bogdanm 0:9b334a45a8ff 129 ******************************************************************************
bogdanm 0:9b334a45a8ff 130 */
bogdanm 0:9b334a45a8ff 131
bogdanm 0:9b334a45a8ff 132 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 133 #include "stm32f30x_spi.h"
bogdanm 0:9b334a45a8ff 134 #include "stm32f30x_rcc.h"
bogdanm 0:9b334a45a8ff 135
bogdanm 0:9b334a45a8ff 136 /** @addtogroup STM32F30x_StdPeriph_Driver
bogdanm 0:9b334a45a8ff 137 * @{
bogdanm 0:9b334a45a8ff 138 */
bogdanm 0:9b334a45a8ff 139
bogdanm 0:9b334a45a8ff 140 /** @defgroup SPI
bogdanm 0:9b334a45a8ff 141 * @brief SPI driver modules
bogdanm 0:9b334a45a8ff 142 * @{
bogdanm 0:9b334a45a8ff 143 */
bogdanm 0:9b334a45a8ff 144
bogdanm 0:9b334a45a8ff 145 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 146 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 147 /* SPI registers Masks */
bogdanm 0:9b334a45a8ff 148 #define CR1_CLEAR_MASK ((uint16_t)0x3040)
bogdanm 0:9b334a45a8ff 149 #define CR2_LDMA_MASK ((uint16_t)0x9FFF)
bogdanm 0:9b334a45a8ff 150
bogdanm 0:9b334a45a8ff 151 #define I2SCFGR_CLEAR_MASK ((uint16_t)0xF040)
bogdanm 0:9b334a45a8ff 152
bogdanm 0:9b334a45a8ff 153 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 154 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 155 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 156 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 157
bogdanm 0:9b334a45a8ff 158 /** @defgroup SPI_Private_Functions
bogdanm 0:9b334a45a8ff 159 * @{
bogdanm 0:9b334a45a8ff 160 */
bogdanm 0:9b334a45a8ff 161
bogdanm 0:9b334a45a8ff 162 /** @defgroup SPI_Group1 Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 163 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 164 *
bogdanm 0:9b334a45a8ff 165 @verbatim
bogdanm 0:9b334a45a8ff 166 ===============================================================================
bogdanm 0:9b334a45a8ff 167 ##### Initialization and Configuration functions #####
bogdanm 0:9b334a45a8ff 168 ===============================================================================
bogdanm 0:9b334a45a8ff 169 [..] This section provides a set of functions allowing to initialize the SPI Direction,
bogdanm 0:9b334a45a8ff 170 SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud
bogdanm 0:9b334a45a8ff 171 Rate Prescaler, SPI First Bit and SPI CRC Polynomial.
bogdanm 0:9b334a45a8ff 172 [..] The SPI_Init() function follows the SPI configuration procedures for Master mode
bogdanm 0:9b334a45a8ff 173 and Slave mode (details for these procedures are available in reference manual).
bogdanm 0:9b334a45a8ff 174 [..] When the Software NSS management (SPI_InitStruct->SPI_NSS = SPI_NSS_Soft) is selected,
bogdanm 0:9b334a45a8ff 175 use the following function to manage the NSS bit:
bogdanm 0:9b334a45a8ff 176 void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
bogdanm 0:9b334a45a8ff 177 [..] In Master mode, when the Hardware NSS management (SPI_InitStruct->SPI_NSS = SPI_NSS_Hard)
bogdanm 0:9b334a45a8ff 178 is selected, use the follwoing function to enable the NSS output feature.
bogdanm 0:9b334a45a8ff 179 void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
bogdanm 0:9b334a45a8ff 180 [..] The NSS pulse mode can be managed by the SPI TI mode when enabling it using the
bogdanm 0:9b334a45a8ff 181 following function: void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
bogdanm 0:9b334a45a8ff 182 And it can be managed by software in the SPI Motorola mode using this function:
bogdanm 0:9b334a45a8ff 183 void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
bogdanm 0:9b334a45a8ff 184 [..] This section provides also functions to initialize the I2S Mode, Standard,
bogdanm 0:9b334a45a8ff 185 Data Format, MCLK Output, Audio frequency and Polarity.
bogdanm 0:9b334a45a8ff 186 [..] The I2S_Init() function follows the I2S configuration procedures for Master mode
bogdanm 0:9b334a45a8ff 187 and Slave mode.
bogdanm 0:9b334a45a8ff 188
bogdanm 0:9b334a45a8ff 189 @endverbatim
bogdanm 0:9b334a45a8ff 190 * @{
bogdanm 0:9b334a45a8ff 191 */
bogdanm 0:9b334a45a8ff 192
bogdanm 0:9b334a45a8ff 193 /**
bogdanm 0:9b334a45a8ff 194 * @brief Deinitializes the SPIx peripheral registers to their default
bogdanm 0:9b334a45a8ff 195 * reset values.
bogdanm 0:9b334a45a8ff 196 * @param SPIx: To select the SPIx peripheral, where x can be: 1, 2 or 3
bogdanm 0:9b334a45a8ff 197 * in SPI mode.
bogdanm 0:9b334a45a8ff 198 * @retval None
bogdanm 0:9b334a45a8ff 199 */
bogdanm 0:9b334a45a8ff 200 void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
bogdanm 0:9b334a45a8ff 201 {
bogdanm 0:9b334a45a8ff 202 /* Check the parameters */
bogdanm 0:9b334a45a8ff 203 assert_param(IS_SPI_ALL_PERIPH(SPIx));
bogdanm 0:9b334a45a8ff 204
bogdanm 0:9b334a45a8ff 205 if (SPIx == SPI1)
bogdanm 0:9b334a45a8ff 206 {
bogdanm 0:9b334a45a8ff 207 /* Enable SPI1 reset state */
bogdanm 0:9b334a45a8ff 208 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
bogdanm 0:9b334a45a8ff 209 /* Release SPI1 from reset state */
bogdanm 0:9b334a45a8ff 210 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
bogdanm 0:9b334a45a8ff 211 }
bogdanm 0:9b334a45a8ff 212 else if (SPIx == SPI2)
bogdanm 0:9b334a45a8ff 213 {
bogdanm 0:9b334a45a8ff 214 /* Enable SPI2 reset state */
bogdanm 0:9b334a45a8ff 215 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
bogdanm 0:9b334a45a8ff 216 /* Release SPI2 from reset state */
bogdanm 0:9b334a45a8ff 217 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
bogdanm 0:9b334a45a8ff 218 }
bogdanm 0:9b334a45a8ff 219 else
bogdanm 0:9b334a45a8ff 220 {
bogdanm 0:9b334a45a8ff 221 if (SPIx == SPI3)
bogdanm 0:9b334a45a8ff 222 {
bogdanm 0:9b334a45a8ff 223 /* Enable SPI3 reset state */
bogdanm 0:9b334a45a8ff 224 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
bogdanm 0:9b334a45a8ff 225 /* Release SPI3 from reset state */
bogdanm 0:9b334a45a8ff 226 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
bogdanm 0:9b334a45a8ff 227 }
bogdanm 0:9b334a45a8ff 228 }
bogdanm 0:9b334a45a8ff 229 }
bogdanm 0:9b334a45a8ff 230
bogdanm 0:9b334a45a8ff 231 /**
bogdanm 0:9b334a45a8ff 232 * @brief Fills each SPI_InitStruct member with its default value.
bogdanm 0:9b334a45a8ff 233 * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized.
bogdanm 0:9b334a45a8ff 234 * @retval None
bogdanm 0:9b334a45a8ff 235 */
bogdanm 0:9b334a45a8ff 236 void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
bogdanm 0:9b334a45a8ff 237 {
bogdanm 0:9b334a45a8ff 238 /*--------------- Reset SPI init structure parameters values -----------------*/
bogdanm 0:9b334a45a8ff 239 /* Initialize the SPI_Direction member */
bogdanm 0:9b334a45a8ff 240 SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
bogdanm 0:9b334a45a8ff 241 /* Initialize the SPI_Mode member */
bogdanm 0:9b334a45a8ff 242 SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
bogdanm 0:9b334a45a8ff 243 /* Initialize the SPI_DataSize member */
bogdanm 0:9b334a45a8ff 244 SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
bogdanm 0:9b334a45a8ff 245 /* Initialize the SPI_CPOL member */
bogdanm 0:9b334a45a8ff 246 SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
bogdanm 0:9b334a45a8ff 247 /* Initialize the SPI_CPHA member */
bogdanm 0:9b334a45a8ff 248 SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
bogdanm 0:9b334a45a8ff 249 /* Initialize the SPI_NSS member */
bogdanm 0:9b334a45a8ff 250 SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
bogdanm 0:9b334a45a8ff 251 /* Initialize the SPI_BaudRatePrescaler member */
bogdanm 0:9b334a45a8ff 252 SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
bogdanm 0:9b334a45a8ff 253 /* Initialize the SPI_FirstBit member */
bogdanm 0:9b334a45a8ff 254 SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
bogdanm 0:9b334a45a8ff 255 /* Initialize the SPI_CRCPolynomial member */
bogdanm 0:9b334a45a8ff 256 SPI_InitStruct->SPI_CRCPolynomial = 7;
bogdanm 0:9b334a45a8ff 257 }
bogdanm 0:9b334a45a8ff 258
bogdanm 0:9b334a45a8ff 259 /**
bogdanm 0:9b334a45a8ff 260 * @brief Initializes the SPIx peripheral according to the specified
bogdanm 0:9b334a45a8ff 261 * parameters in the SPI_InitStruct.
bogdanm 0:9b334a45a8ff 262 * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
bogdanm 0:9b334a45a8ff 263 * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
bogdanm 0:9b334a45a8ff 264 * contains the configuration information for the specified SPI peripheral.
bogdanm 0:9b334a45a8ff 265 * @retval None
bogdanm 0:9b334a45a8ff 266 */
bogdanm 0:9b334a45a8ff 267 void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
bogdanm 0:9b334a45a8ff 268 {
bogdanm 0:9b334a45a8ff 269 uint16_t tmpreg = 0;
bogdanm 0:9b334a45a8ff 270
bogdanm 0:9b334a45a8ff 271 /* check the parameters */
bogdanm 0:9b334a45a8ff 272 assert_param(IS_SPI_ALL_PERIPH(SPIx));
bogdanm 0:9b334a45a8ff 273
bogdanm 0:9b334a45a8ff 274 /* Check the SPI parameters */
bogdanm 0:9b334a45a8ff 275 assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
bogdanm 0:9b334a45a8ff 276 assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
bogdanm 0:9b334a45a8ff 277 assert_param(IS_SPI_DATA_SIZE(SPI_InitStruct->SPI_DataSize));
bogdanm 0:9b334a45a8ff 278 assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
bogdanm 0:9b334a45a8ff 279 assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
bogdanm 0:9b334a45a8ff 280 assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
bogdanm 0:9b334a45a8ff 281 assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
bogdanm 0:9b334a45a8ff 282 assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
bogdanm 0:9b334a45a8ff 283 assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
bogdanm 0:9b334a45a8ff 284
bogdanm 0:9b334a45a8ff 285 /* Configuring the SPI in master mode */
bogdanm 0:9b334a45a8ff 286 if(SPI_InitStruct->SPI_Mode == SPI_Mode_Master)
bogdanm 0:9b334a45a8ff 287 {
bogdanm 0:9b334a45a8ff 288 /*---------------------------- SPIx CR1 Configuration ------------------------*/
bogdanm 0:9b334a45a8ff 289 /* Get the SPIx CR1 value */
bogdanm 0:9b334a45a8ff 290 tmpreg = SPIx->CR1;
bogdanm 0:9b334a45a8ff 291 /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
bogdanm 0:9b334a45a8ff 292 tmpreg &= CR1_CLEAR_MASK;
bogdanm 0:9b334a45a8ff 293 /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
bogdanm 0:9b334a45a8ff 294 master/slave mode, CPOL and CPHA */
bogdanm 0:9b334a45a8ff 295 /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
bogdanm 0:9b334a45a8ff 296 /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
bogdanm 0:9b334a45a8ff 297 /* Set LSBFirst bit according to SPI_FirstBit value */
bogdanm 0:9b334a45a8ff 298 /* Set BR bits according to SPI_BaudRatePrescaler value */
bogdanm 0:9b334a45a8ff 299 /* Set CPOL bit according to SPI_CPOL value */
bogdanm 0:9b334a45a8ff 300 /* Set CPHA bit according to SPI_CPHA value */
bogdanm 0:9b334a45a8ff 301 tmpreg |= (uint16_t)((uint16_t)(SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode) |
bogdanm 0:9b334a45a8ff 302 (uint16_t)((uint16_t)(SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA) |
bogdanm 0:9b334a45a8ff 303 (uint16_t)((uint16_t)(SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler) |
bogdanm 0:9b334a45a8ff 304 SPI_InitStruct->SPI_FirstBit)));
bogdanm 0:9b334a45a8ff 305 /* Write to SPIx CR1 */
bogdanm 0:9b334a45a8ff 306 SPIx->CR1 = tmpreg;
bogdanm 0:9b334a45a8ff 307 /*-------------------------Data Size Configuration -----------------------*/
bogdanm 0:9b334a45a8ff 308 /* Get the SPIx CR2 value */
bogdanm 0:9b334a45a8ff 309 tmpreg = SPIx->CR2;
bogdanm 0:9b334a45a8ff 310 /* Clear DS[3:0] bits */
bogdanm 0:9b334a45a8ff 311 tmpreg &= (uint16_t)~SPI_CR2_DS;
bogdanm 0:9b334a45a8ff 312 /* Configure SPIx: Data Size */
bogdanm 0:9b334a45a8ff 313 tmpreg |= (uint16_t)(SPI_InitStruct->SPI_DataSize);
bogdanm 0:9b334a45a8ff 314 /* Write to SPIx CR2 */
bogdanm 0:9b334a45a8ff 315 SPIx->CR2 = tmpreg;
bogdanm 0:9b334a45a8ff 316 }
bogdanm 0:9b334a45a8ff 317 /* Configuring the SPI in slave mode */
bogdanm 0:9b334a45a8ff 318 else
bogdanm 0:9b334a45a8ff 319 {
bogdanm 0:9b334a45a8ff 320 /*---------------------------- Data size Configuration -----------------------*/
bogdanm 0:9b334a45a8ff 321 /* Get the SPIx CR2 value */
bogdanm 0:9b334a45a8ff 322 tmpreg = SPIx->CR2;
bogdanm 0:9b334a45a8ff 323 /* Clear DS[3:0] bits */
bogdanm 0:9b334a45a8ff 324 tmpreg &= (uint16_t)~SPI_CR2_DS;
bogdanm 0:9b334a45a8ff 325 /* Configure SPIx: Data Size */
bogdanm 0:9b334a45a8ff 326 tmpreg |= (uint16_t)(SPI_InitStruct->SPI_DataSize);
bogdanm 0:9b334a45a8ff 327 /* Write to SPIx CR2 */
bogdanm 0:9b334a45a8ff 328 SPIx->CR2 = tmpreg;
bogdanm 0:9b334a45a8ff 329 /*---------------------------- SPIx CR1 Configuration ------------------------*/
bogdanm 0:9b334a45a8ff 330 /* Get the SPIx CR1 value */
bogdanm 0:9b334a45a8ff 331 tmpreg = SPIx->CR1;
bogdanm 0:9b334a45a8ff 332 /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
bogdanm 0:9b334a45a8ff 333 tmpreg &= CR1_CLEAR_MASK;
bogdanm 0:9b334a45a8ff 334 /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
bogdanm 0:9b334a45a8ff 335 master/salve mode, CPOL and CPHA */
bogdanm 0:9b334a45a8ff 336 /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
bogdanm 0:9b334a45a8ff 337 /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
bogdanm 0:9b334a45a8ff 338 /* Set LSBFirst bit according to SPI_FirstBit value */
bogdanm 0:9b334a45a8ff 339 /* Set BR bits according to SPI_BaudRatePrescaler value */
bogdanm 0:9b334a45a8ff 340 /* Set CPOL bit according to SPI_CPOL value */
bogdanm 0:9b334a45a8ff 341 /* Set CPHA bit according to SPI_CPHA value */
bogdanm 0:9b334a45a8ff 342 tmpreg |= (uint16_t)((uint16_t)(SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode) |
bogdanm 0:9b334a45a8ff 343 (uint16_t)((uint16_t)(SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA) |
bogdanm 0:9b334a45a8ff 344 (uint16_t)((uint16_t)(SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler) |
bogdanm 0:9b334a45a8ff 345 SPI_InitStruct->SPI_FirstBit)));
bogdanm 0:9b334a45a8ff 346
bogdanm 0:9b334a45a8ff 347 /* Write to SPIx CR1 */
bogdanm 0:9b334a45a8ff 348 SPIx->CR1 = tmpreg;
bogdanm 0:9b334a45a8ff 349 }
bogdanm 0:9b334a45a8ff 350
bogdanm 0:9b334a45a8ff 351 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
bogdanm 0:9b334a45a8ff 352 SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD);
bogdanm 0:9b334a45a8ff 353
bogdanm 0:9b334a45a8ff 354 /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
bogdanm 0:9b334a45a8ff 355 /* Write to SPIx CRCPOLY */
bogdanm 0:9b334a45a8ff 356 SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
bogdanm 0:9b334a45a8ff 357 }
bogdanm 0:9b334a45a8ff 358
bogdanm 0:9b334a45a8ff 359 /**
bogdanm 0:9b334a45a8ff 360 * @brief Fills each I2S_InitStruct member with its default value.
bogdanm 0:9b334a45a8ff 361 * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized.
bogdanm 0:9b334a45a8ff 362 * @retval None
bogdanm 0:9b334a45a8ff 363 */
bogdanm 0:9b334a45a8ff 364 void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
bogdanm 0:9b334a45a8ff 365 {
bogdanm 0:9b334a45a8ff 366 /*--------------- Reset I2S init structure parameters values -----------------*/
bogdanm 0:9b334a45a8ff 367 /* Initialize the I2S_Mode member */
bogdanm 0:9b334a45a8ff 368 I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
bogdanm 0:9b334a45a8ff 369
bogdanm 0:9b334a45a8ff 370 /* Initialize the I2S_Standard member */
bogdanm 0:9b334a45a8ff 371 I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
bogdanm 0:9b334a45a8ff 372
bogdanm 0:9b334a45a8ff 373 /* Initialize the I2S_DataFormat member */
bogdanm 0:9b334a45a8ff 374 I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
bogdanm 0:9b334a45a8ff 375
bogdanm 0:9b334a45a8ff 376 /* Initialize the I2S_MCLKOutput member */
bogdanm 0:9b334a45a8ff 377 I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
bogdanm 0:9b334a45a8ff 378
bogdanm 0:9b334a45a8ff 379 /* Initialize the I2S_AudioFreq member */
bogdanm 0:9b334a45a8ff 380 I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
bogdanm 0:9b334a45a8ff 381
bogdanm 0:9b334a45a8ff 382 /* Initialize the I2S_CPOL member */
bogdanm 0:9b334a45a8ff 383 I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
bogdanm 0:9b334a45a8ff 384 }
bogdanm 0:9b334a45a8ff 385
bogdanm 0:9b334a45a8ff 386 /**
bogdanm 0:9b334a45a8ff 387 * @brief Initializes the SPIx peripheral according to the specified
bogdanm 0:9b334a45a8ff 388 * parameters in the I2S_InitStruct.
bogdanm 0:9b334a45a8ff 389 * @param SPIx:To select the SPIx peripheral, where x can be: 2 or 3
bogdanm 0:9b334a45a8ff 390 * in I2S mode.
bogdanm 0:9b334a45a8ff 391 * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
bogdanm 0:9b334a45a8ff 392 * contains the configuration information for the specified SPI peripheral
bogdanm 0:9b334a45a8ff 393 * configured in I2S mode.
bogdanm 0:9b334a45a8ff 394 * @note
bogdanm 0:9b334a45a8ff 395 * The function calculates the optimal prescaler needed to obtain the most
bogdanm 0:9b334a45a8ff 396 * accurate audio frequency (depending on the I2S clock source, the PLL values
bogdanm 0:9b334a45a8ff 397 * and the product configuration). But in case the prescaler value is greater
bogdanm 0:9b334a45a8ff 398 * than 511, the default value (0x02) will be configured instead.
bogdanm 0:9b334a45a8ff 399 * @retval None
bogdanm 0:9b334a45a8ff 400 */
bogdanm 0:9b334a45a8ff 401 void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
bogdanm 0:9b334a45a8ff 402 {
bogdanm 0:9b334a45a8ff 403 uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
bogdanm 0:9b334a45a8ff 404 uint32_t tmp = 0;
bogdanm 0:9b334a45a8ff 405 RCC_ClocksTypeDef RCC_Clocks;
bogdanm 0:9b334a45a8ff 406 uint32_t sourceclock = 0;
bogdanm 0:9b334a45a8ff 407
bogdanm 0:9b334a45a8ff 408 /* Check the I2S parameters */
bogdanm 0:9b334a45a8ff 409 assert_param(IS_SPI_23_PERIPH(SPIx));
bogdanm 0:9b334a45a8ff 410 assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
bogdanm 0:9b334a45a8ff 411 assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
bogdanm 0:9b334a45a8ff 412 assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
bogdanm 0:9b334a45a8ff 413 assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
bogdanm 0:9b334a45a8ff 414 assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
bogdanm 0:9b334a45a8ff 415 assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
bogdanm 0:9b334a45a8ff 416
bogdanm 0:9b334a45a8ff 417 /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
bogdanm 0:9b334a45a8ff 418 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
bogdanm 0:9b334a45a8ff 419 SPIx->I2SCFGR &= I2SCFGR_CLEAR_MASK;
bogdanm 0:9b334a45a8ff 420 SPIx->I2SPR = 0x0002;
bogdanm 0:9b334a45a8ff 421
bogdanm 0:9b334a45a8ff 422 /* Get the I2SCFGR register value */
bogdanm 0:9b334a45a8ff 423 tmpreg = SPIx->I2SCFGR;
bogdanm 0:9b334a45a8ff 424
bogdanm 0:9b334a45a8ff 425 /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
bogdanm 0:9b334a45a8ff 426 if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
bogdanm 0:9b334a45a8ff 427 {
bogdanm 0:9b334a45a8ff 428 i2sodd = (uint16_t)0;
bogdanm 0:9b334a45a8ff 429 i2sdiv = (uint16_t)2;
bogdanm 0:9b334a45a8ff 430 }
bogdanm 0:9b334a45a8ff 431 /* If the requested audio frequency is not the default, compute the prescaler */
bogdanm 0:9b334a45a8ff 432 else
bogdanm 0:9b334a45a8ff 433 {
bogdanm 0:9b334a45a8ff 434 /* Check the frame length (For the Prescaler computing) */
bogdanm 0:9b334a45a8ff 435 if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
bogdanm 0:9b334a45a8ff 436 {
bogdanm 0:9b334a45a8ff 437 /* Packet length is 16 bits */
bogdanm 0:9b334a45a8ff 438 packetlength = 1;
bogdanm 0:9b334a45a8ff 439 }
bogdanm 0:9b334a45a8ff 440 else
bogdanm 0:9b334a45a8ff 441 {
bogdanm 0:9b334a45a8ff 442 /* Packet length is 32 bits */
bogdanm 0:9b334a45a8ff 443 packetlength = 2;
bogdanm 0:9b334a45a8ff 444 }
bogdanm 0:9b334a45a8ff 445
bogdanm 0:9b334a45a8ff 446 /* I2S Clock source is System clock: Get System Clock frequency */
bogdanm 0:9b334a45a8ff 447 RCC_GetClocksFreq(&RCC_Clocks);
bogdanm 0:9b334a45a8ff 448
bogdanm 0:9b334a45a8ff 449 /* Get the source clock value: based on System Clock value */
bogdanm 0:9b334a45a8ff 450 sourceclock = RCC_Clocks.SYSCLK_Frequency;
bogdanm 0:9b334a45a8ff 451
bogdanm 0:9b334a45a8ff 452 /* Compute the Real divider depending on the MCLK output state with a floating point */
bogdanm 0:9b334a45a8ff 453 if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
bogdanm 0:9b334a45a8ff 454 {
bogdanm 0:9b334a45a8ff 455 /* MCLK output is enabled */
bogdanm 0:9b334a45a8ff 456 tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
bogdanm 0:9b334a45a8ff 457 }
bogdanm 0:9b334a45a8ff 458 else
bogdanm 0:9b334a45a8ff 459 {
bogdanm 0:9b334a45a8ff 460 /* MCLK output is disabled */
bogdanm 0:9b334a45a8ff 461 tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
bogdanm 0:9b334a45a8ff 462 }
bogdanm 0:9b334a45a8ff 463
bogdanm 0:9b334a45a8ff 464 /* Remove the floating point */
bogdanm 0:9b334a45a8ff 465 tmp = tmp / 10;
bogdanm 0:9b334a45a8ff 466
bogdanm 0:9b334a45a8ff 467 /* Check the parity of the divider */
bogdanm 0:9b334a45a8ff 468 i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
bogdanm 0:9b334a45a8ff 469
bogdanm 0:9b334a45a8ff 470 /* Compute the i2sdiv prescaler */
bogdanm 0:9b334a45a8ff 471 i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
bogdanm 0:9b334a45a8ff 472
bogdanm 0:9b334a45a8ff 473 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
bogdanm 0:9b334a45a8ff 474 i2sodd = (uint16_t) (i2sodd << 8);
bogdanm 0:9b334a45a8ff 475 }
bogdanm 0:9b334a45a8ff 476
bogdanm 0:9b334a45a8ff 477 /* Test if the divider is 1 or 0 or greater than 0xFF */
bogdanm 0:9b334a45a8ff 478 if ((i2sdiv < 2) || (i2sdiv > 0xFF))
bogdanm 0:9b334a45a8ff 479 {
bogdanm 0:9b334a45a8ff 480 /* Set the default values */
bogdanm 0:9b334a45a8ff 481 i2sdiv = 2;
bogdanm 0:9b334a45a8ff 482 i2sodd = 0;
bogdanm 0:9b334a45a8ff 483 }
bogdanm 0:9b334a45a8ff 484
bogdanm 0:9b334a45a8ff 485 /* Write to SPIx I2SPR register the computed value */
bogdanm 0:9b334a45a8ff 486 SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
bogdanm 0:9b334a45a8ff 487
bogdanm 0:9b334a45a8ff 488 /* Configure the I2S with the SPI_InitStruct values */
bogdanm 0:9b334a45a8ff 489 tmpreg |= (uint16_t)((uint16_t)(SPI_I2SCFGR_I2SMOD | I2S_InitStruct->I2S_Mode) | \
bogdanm 0:9b334a45a8ff 490 (uint16_t)((uint16_t)((uint16_t)(I2S_InitStruct->I2S_Standard |I2S_InitStruct->I2S_DataFormat) |\
bogdanm 0:9b334a45a8ff 491 I2S_InitStruct->I2S_CPOL)));
bogdanm 0:9b334a45a8ff 492
bogdanm 0:9b334a45a8ff 493 /* Write to SPIx I2SCFGR */
bogdanm 0:9b334a45a8ff 494 SPIx->I2SCFGR = tmpreg;
bogdanm 0:9b334a45a8ff 495 }
bogdanm 0:9b334a45a8ff 496
bogdanm 0:9b334a45a8ff 497 /**
bogdanm 0:9b334a45a8ff 498 * @brief Enables or disables the specified SPI peripheral.
bogdanm 0:9b334a45a8ff 499 * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
bogdanm 0:9b334a45a8ff 500 * @param NewState: new state of the SPIx peripheral.
bogdanm 0:9b334a45a8ff 501 * This parameter can be: ENABLE or DISABLE.
bogdanm 0:9b334a45a8ff 502 * @retval None
bogdanm 0:9b334a45a8ff 503 */
bogdanm 0:9b334a45a8ff 504 void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
bogdanm 0:9b334a45a8ff 505 {
bogdanm 0:9b334a45a8ff 506 /* Check the parameters */
bogdanm 0:9b334a45a8ff 507 assert_param(IS_SPI_ALL_PERIPH(SPIx));
bogdanm 0:9b334a45a8ff 508 assert_param(IS_FUNCTIONAL_STATE(NewState));
bogdanm 0:9b334a45a8ff 509
bogdanm 0:9b334a45a8ff 510 if (NewState != DISABLE)
bogdanm 0:9b334a45a8ff 511 {
bogdanm 0:9b334a45a8ff 512 /* Enable the selected SPI peripheral */
bogdanm 0:9b334a45a8ff 513 SPIx->CR1 |= SPI_CR1_SPE;
bogdanm 0:9b334a45a8ff 514 }
bogdanm 0:9b334a45a8ff 515 else
bogdanm 0:9b334a45a8ff 516 {
bogdanm 0:9b334a45a8ff 517 /* Disable the selected SPI peripheral */
bogdanm 0:9b334a45a8ff 518 SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);
bogdanm 0:9b334a45a8ff 519 }
bogdanm 0:9b334a45a8ff 520 }
bogdanm 0:9b334a45a8ff 521
bogdanm 0:9b334a45a8ff 522 /**
bogdanm 0:9b334a45a8ff 523 * @brief Enables or disables the TI Mode.
bogdanm 0:9b334a45a8ff 524 * @note This function can be called only after the SPI_Init() function has
bogdanm 0:9b334a45a8ff 525 * been called.
bogdanm 0:9b334a45a8ff 526 * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA
bogdanm 0:9b334a45a8ff 527 * are not taken into consideration and are configured by hardware
bogdanm 0:9b334a45a8ff 528 * respectively to the TI mode requirements.
bogdanm 0:9b334a45a8ff 529 * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
bogdanm 0:9b334a45a8ff 530 * @param NewState: new state of the selected SPI TI communication mode.
bogdanm 0:9b334a45a8ff 531 * This parameter can be: ENABLE or DISABLE.
bogdanm 0:9b334a45a8ff 532 * @retval None
bogdanm 0:9b334a45a8ff 533 */
bogdanm 0:9b334a45a8ff 534 void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
bogdanm 0:9b334a45a8ff 535 {
bogdanm 0:9b334a45a8ff 536 /* Check the parameters */
bogdanm 0:9b334a45a8ff 537 assert_param(IS_SPI_ALL_PERIPH(SPIx));
bogdanm 0:9b334a45a8ff 538 assert_param(IS_FUNCTIONAL_STATE(NewState));
bogdanm 0:9b334a45a8ff 539
bogdanm 0:9b334a45a8ff 540 if (NewState != DISABLE)
bogdanm 0:9b334a45a8ff 541 {
bogdanm 0:9b334a45a8ff 542 /* Enable the TI mode for the selected SPI peripheral */
bogdanm 0:9b334a45a8ff 543 SPIx->CR2 |= SPI_CR2_FRF;
bogdanm 0:9b334a45a8ff 544 }
bogdanm 0:9b334a45a8ff 545 else
bogdanm 0:9b334a45a8ff 546 {
bogdanm 0:9b334a45a8ff 547 /* Disable the TI mode for the selected SPI peripheral */
bogdanm 0:9b334a45a8ff 548 SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRF);
bogdanm 0:9b334a45a8ff 549 }
bogdanm 0:9b334a45a8ff 550 }
bogdanm 0:9b334a45a8ff 551
bogdanm 0:9b334a45a8ff 552 /**
bogdanm 0:9b334a45a8ff 553 * @brief Enables or disables the specified SPI peripheral (in I2S mode).
bogdanm 0:9b334a45a8ff 554 * @param SPIx:To select the SPIx peripheral, where x can be: 2 or 3 in
bogdanm 0:9b334a45a8ff 555 * I2S mode or I2Sxext for I2S full duplex mode.
bogdanm 0:9b334a45a8ff 556 * @param NewState: new state of the SPIx peripheral.
bogdanm 0:9b334a45a8ff 557 * This parameter can be: ENABLE or DISABLE.
bogdanm 0:9b334a45a8ff 558 * @retval None
bogdanm 0:9b334a45a8ff 559 */
bogdanm 0:9b334a45a8ff 560 void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
bogdanm 0:9b334a45a8ff 561 {
bogdanm 0:9b334a45a8ff 562 /* Check the parameters */
bogdanm 0:9b334a45a8ff 563 assert_param(IS_SPI_23_PERIPH_EXT(SPIx));
bogdanm 0:9b334a45a8ff 564 assert_param(IS_FUNCTIONAL_STATE(NewState));
bogdanm 0:9b334a45a8ff 565 if (NewState != DISABLE)
bogdanm 0:9b334a45a8ff 566 {
bogdanm 0:9b334a45a8ff 567 /* Enable the selected SPI peripheral in I2S mode */
bogdanm 0:9b334a45a8ff 568 SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE;
bogdanm 0:9b334a45a8ff 569 }
bogdanm 0:9b334a45a8ff 570 else
bogdanm 0:9b334a45a8ff 571 {
bogdanm 0:9b334a45a8ff 572 /* Disable the selected SPI peripheral in I2S mode */
bogdanm 0:9b334a45a8ff 573 SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE);
bogdanm 0:9b334a45a8ff 574 }
bogdanm 0:9b334a45a8ff 575 }
bogdanm 0:9b334a45a8ff 576
bogdanm 0:9b334a45a8ff 577 /**
bogdanm 0:9b334a45a8ff 578 * @brief Configures the data size for the selected SPI.
bogdanm 0:9b334a45a8ff 579 * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
bogdanm 0:9b334a45a8ff 580 * @param SPI_DataSize: specifies the SPI data size.
bogdanm 0:9b334a45a8ff 581 * For the SPIx peripheral this parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 582 * @arg SPI_DataSize_4b: Set data size to 4 bits
bogdanm 0:9b334a45a8ff 583 * @arg SPI_DataSize_5b: Set data size to 5 bits
bogdanm 0:9b334a45a8ff 584 * @arg SPI_DataSize_6b: Set data size to 6 bits
bogdanm 0:9b334a45a8ff 585 * @arg SPI_DataSize_7b: Set data size to 7 bits
bogdanm 0:9b334a45a8ff 586 * @arg SPI_DataSize_8b: Set data size to 8 bits
bogdanm 0:9b334a45a8ff 587 * @arg SPI_DataSize_9b: Set data size to 9 bits
bogdanm 0:9b334a45a8ff 588 * @arg SPI_DataSize_10b: Set data size to 10 bits
bogdanm 0:9b334a45a8ff 589 * @arg SPI_DataSize_11b: Set data size to 11 bits
bogdanm 0:9b334a45a8ff 590 * @arg SPI_DataSize_12b: Set data size to 12 bits
bogdanm 0:9b334a45a8ff 591 * @arg SPI_DataSize_13b: Set data size to 13 bits
bogdanm 0:9b334a45a8ff 592 * @arg SPI_DataSize_14b: Set data size to 14 bits
bogdanm 0:9b334a45a8ff 593 * @arg SPI_DataSize_15b: Set data size to 15 bits
bogdanm 0:9b334a45a8ff 594 * @arg SPI_DataSize_16b: Set data size to 16 bits
bogdanm 0:9b334a45a8ff 595 * @retval None
bogdanm 0:9b334a45a8ff 596 */
bogdanm 0:9b334a45a8ff 597 void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
bogdanm 0:9b334a45a8ff 598 {
bogdanm 0:9b334a45a8ff 599 uint16_t tmpreg = 0;
bogdanm 0:9b334a45a8ff 600
bogdanm 0:9b334a45a8ff 601 /* Check the parameters */
bogdanm 0:9b334a45a8ff 602 assert_param(IS_SPI_ALL_PERIPH(SPIx));
bogdanm 0:9b334a45a8ff 603 assert_param(IS_SPI_DATA_SIZE(SPI_DataSize));
bogdanm 0:9b334a45a8ff 604 /* Read the CR2 register */
bogdanm 0:9b334a45a8ff 605 tmpreg = SPIx->CR2;
bogdanm 0:9b334a45a8ff 606 /* Clear DS[3:0] bits */
bogdanm 0:9b334a45a8ff 607 tmpreg &= (uint16_t)~SPI_CR2_DS;
bogdanm 0:9b334a45a8ff 608 /* Set new DS[3:0] bits value */
bogdanm 0:9b334a45a8ff 609 tmpreg |= SPI_DataSize;
bogdanm 0:9b334a45a8ff 610 SPIx->CR2 = tmpreg;
bogdanm 0:9b334a45a8ff 611 }
bogdanm 0:9b334a45a8ff 612
bogdanm 0:9b334a45a8ff 613 /**
bogdanm 0:9b334a45a8ff 614 * @brief Configures the FIFO reception threshold for the selected SPI.
bogdanm 0:9b334a45a8ff 615 * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
bogdanm 0:9b334a45a8ff 616 * @param SPI_RxFIFOThreshold: specifies the FIFO reception threshold.
bogdanm 0:9b334a45a8ff 617 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 618 * @arg SPI_RxFIFOThreshold_HF: RXNE event is generated if the FIFO
bogdanm 0:9b334a45a8ff 619 * level is greater or equal to 1/2.
bogdanm 0:9b334a45a8ff 620 * @arg SPI_RxFIFOThreshold_QF: RXNE event is generated if the FIFO
bogdanm 0:9b334a45a8ff 621 * level is greater or equal to 1/4.
bogdanm 0:9b334a45a8ff 622 * @retval None
bogdanm 0:9b334a45a8ff 623 */
bogdanm 0:9b334a45a8ff 624 void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold)
bogdanm 0:9b334a45a8ff 625 {
bogdanm 0:9b334a45a8ff 626 /* Check the parameters */
bogdanm 0:9b334a45a8ff 627 assert_param(IS_SPI_ALL_PERIPH(SPIx));
bogdanm 0:9b334a45a8ff 628 assert_param(IS_SPI_RX_FIFO_THRESHOLD(SPI_RxFIFOThreshold));
bogdanm 0:9b334a45a8ff 629
bogdanm 0:9b334a45a8ff 630 /* Clear FRXTH bit */
bogdanm 0:9b334a45a8ff 631 SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRXTH);
bogdanm 0:9b334a45a8ff 632
bogdanm 0:9b334a45a8ff 633 /* Set new FRXTH bit value */
bogdanm 0:9b334a45a8ff 634 SPIx->CR2 |= SPI_RxFIFOThreshold;
bogdanm 0:9b334a45a8ff 635 }
bogdanm 0:9b334a45a8ff 636
bogdanm 0:9b334a45a8ff 637 /**
bogdanm 0:9b334a45a8ff 638 * @brief Selects the data transfer direction in bidirectional mode for the specified SPI.
bogdanm 0:9b334a45a8ff 639 * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
bogdanm 0:9b334a45a8ff 640 * @param SPI_Direction: specifies the data transfer direction in bidirectional mode.
bogdanm 0:9b334a45a8ff 641 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 642 * @arg SPI_Direction_Tx: Selects Tx transmission direction
bogdanm 0:9b334a45a8ff 643 * @arg SPI_Direction_Rx: Selects Rx receive direction
bogdanm 0:9b334a45a8ff 644 * @retval None
bogdanm 0:9b334a45a8ff 645 */
bogdanm 0:9b334a45a8ff 646 void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
bogdanm 0:9b334a45a8ff 647 {
bogdanm 0:9b334a45a8ff 648 /* Check the parameters */
bogdanm 0:9b334a45a8ff 649 assert_param(IS_SPI_ALL_PERIPH(SPIx));
bogdanm 0:9b334a45a8ff 650 assert_param(IS_SPI_DIRECTION(SPI_Direction));
bogdanm 0:9b334a45a8ff 651 if (SPI_Direction == SPI_Direction_Tx)
bogdanm 0:9b334a45a8ff 652 {
bogdanm 0:9b334a45a8ff 653 /* Set the Tx only mode */
bogdanm 0:9b334a45a8ff 654 SPIx->CR1 |= SPI_Direction_Tx;
bogdanm 0:9b334a45a8ff 655 }
bogdanm 0:9b334a45a8ff 656 else
bogdanm 0:9b334a45a8ff 657 {
bogdanm 0:9b334a45a8ff 658 /* Set the Rx only mode */
bogdanm 0:9b334a45a8ff 659 SPIx->CR1 &= SPI_Direction_Rx;
bogdanm 0:9b334a45a8ff 660 }
bogdanm 0:9b334a45a8ff 661 }
bogdanm 0:9b334a45a8ff 662
bogdanm 0:9b334a45a8ff 663 /**
bogdanm 0:9b334a45a8ff 664 * @brief Configures internally by software the NSS pin for the selected SPI.
bogdanm 0:9b334a45a8ff 665 * @note This function can be called only after the SPI_Init() function has
bogdanm 0:9b334a45a8ff 666 * been called.
bogdanm 0:9b334a45a8ff 667 * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
bogdanm 0:9b334a45a8ff 668 * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.
bogdanm 0:9b334a45a8ff 669 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 670 * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
bogdanm 0:9b334a45a8ff 671 * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
bogdanm 0:9b334a45a8ff 672 * @retval None
bogdanm 0:9b334a45a8ff 673 */
bogdanm 0:9b334a45a8ff 674 void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
bogdanm 0:9b334a45a8ff 675 {
bogdanm 0:9b334a45a8ff 676 /* Check the parameters */
bogdanm 0:9b334a45a8ff 677 assert_param(IS_SPI_ALL_PERIPH(SPIx));
bogdanm 0:9b334a45a8ff 678 assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
bogdanm 0:9b334a45a8ff 679
bogdanm 0:9b334a45a8ff 680 if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
bogdanm 0:9b334a45a8ff 681 {
bogdanm 0:9b334a45a8ff 682 /* Set NSS pin internally by software */
bogdanm 0:9b334a45a8ff 683 SPIx->CR1 |= SPI_NSSInternalSoft_Set;
bogdanm 0:9b334a45a8ff 684 }
bogdanm 0:9b334a45a8ff 685 else
bogdanm 0:9b334a45a8ff 686 {
bogdanm 0:9b334a45a8ff 687 /* Reset NSS pin internally by software */
bogdanm 0:9b334a45a8ff 688 SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
bogdanm 0:9b334a45a8ff 689 }
bogdanm 0:9b334a45a8ff 690 }
bogdanm 0:9b334a45a8ff 691
bogdanm 0:9b334a45a8ff 692 /**
bogdanm 0:9b334a45a8ff 693 * @brief Configures the full duplex mode for the I2Sx peripheral using its
bogdanm 0:9b334a45a8ff 694 * extension I2Sxext according to the specified parameters in the
bogdanm 0:9b334a45a8ff 695 * I2S_InitStruct.
bogdanm 0:9b334a45a8ff 696 * @param I2Sxext: where x can be 2 or 3 to select the I2S peripheral extension block.
bogdanm 0:9b334a45a8ff 697 * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
bogdanm 0:9b334a45a8ff 698 * contains the configuration information for the specified I2S peripheral
bogdanm 0:9b334a45a8ff 699 * extension.
bogdanm 0:9b334a45a8ff 700 *
bogdanm 0:9b334a45a8ff 701 * @note The structure pointed by I2S_InitStruct parameter should be the same
bogdanm 0:9b334a45a8ff 702 * used for the master I2S peripheral. In this case, if the master is
bogdanm 0:9b334a45a8ff 703 * configured as transmitter, the slave will be receiver and vice versa.
bogdanm 0:9b334a45a8ff 704 * Or you can force a different mode by modifying the field I2S_Mode to the
bogdanm 0:9b334a45a8ff 705 * value I2S_SlaveRx or I2S_SlaveTx indepedently of the master configuration.
bogdanm 0:9b334a45a8ff 706 *
bogdanm 0:9b334a45a8ff 707 * @note The I2S full duplex extension can be configured in slave mode only.
bogdanm 0:9b334a45a8ff 708 *
bogdanm 0:9b334a45a8ff 709 * @retval None
bogdanm 0:9b334a45a8ff 710 */
bogdanm 0:9b334a45a8ff 711 void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct)
bogdanm 0:9b334a45a8ff 712 {
bogdanm 0:9b334a45a8ff 713 uint16_t tmpreg = 0, tmp = 0;
bogdanm 0:9b334a45a8ff 714
bogdanm 0:9b334a45a8ff 715 /* Check the I2S parameters */
bogdanm 0:9b334a45a8ff 716 assert_param(IS_I2S_EXT_PERIPH(I2Sxext));
bogdanm 0:9b334a45a8ff 717 assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
bogdanm 0:9b334a45a8ff 718 assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
bogdanm 0:9b334a45a8ff 719 assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
bogdanm 0:9b334a45a8ff 720 assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
bogdanm 0:9b334a45a8ff 721
bogdanm 0:9b334a45a8ff 722 /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
bogdanm 0:9b334a45a8ff 723 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
bogdanm 0:9b334a45a8ff 724 I2Sxext->I2SCFGR &= I2SCFGR_CLEAR_MASK;
bogdanm 0:9b334a45a8ff 725 I2Sxext->I2SPR = 0x0002;
bogdanm 0:9b334a45a8ff 726
bogdanm 0:9b334a45a8ff 727 /* Get the I2SCFGR register value */
bogdanm 0:9b334a45a8ff 728 tmpreg = I2Sxext->I2SCFGR;
bogdanm 0:9b334a45a8ff 729
bogdanm 0:9b334a45a8ff 730 /* Get the mode to be configured for the extended I2S */
bogdanm 0:9b334a45a8ff 731 if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveTx))
bogdanm 0:9b334a45a8ff 732 {
bogdanm 0:9b334a45a8ff 733 tmp = I2S_Mode_SlaveRx;
bogdanm 0:9b334a45a8ff 734 }
bogdanm 0:9b334a45a8ff 735 else
bogdanm 0:9b334a45a8ff 736 {
bogdanm 0:9b334a45a8ff 737 if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterRx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveRx))
bogdanm 0:9b334a45a8ff 738 {
bogdanm 0:9b334a45a8ff 739 tmp = I2S_Mode_SlaveTx;
bogdanm 0:9b334a45a8ff 740 }
bogdanm 0:9b334a45a8ff 741 }
bogdanm 0:9b334a45a8ff 742
bogdanm 0:9b334a45a8ff 743
bogdanm 0:9b334a45a8ff 744 /* Configure the I2S with the SPI_InitStruct values */
bogdanm 0:9b334a45a8ff 745 tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \
bogdanm 0:9b334a45a8ff 746 (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
bogdanm 0:9b334a45a8ff 747 (uint16_t)I2S_InitStruct->I2S_CPOL))));
bogdanm 0:9b334a45a8ff 748
bogdanm 0:9b334a45a8ff 749 /* Write to SPIx I2SCFGR */
bogdanm 0:9b334a45a8ff 750 I2Sxext->I2SCFGR = tmpreg;
bogdanm 0:9b334a45a8ff 751 }
bogdanm 0:9b334a45a8ff 752
bogdanm 0:9b334a45a8ff 753 /**
bogdanm 0:9b334a45a8ff 754 * @brief Enables or disables the SS output for the selected SPI.
bogdanm 0:9b334a45a8ff 755 * @note This function can be called only after the SPI_Init() function has
bogdanm 0:9b334a45a8ff 756 * been called and the NSS hardware management mode is selected.
bogdanm 0:9b334a45a8ff 757 * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
bogdanm 0:9b334a45a8ff 758 * @param NewState: new state of the SPIx SS output.
bogdanm 0:9b334a45a8ff 759 * This parameter can be: ENABLE or DISABLE.
bogdanm 0:9b334a45a8ff 760 * @retval None
bogdanm 0:9b334a45a8ff 761 */
bogdanm 0:9b334a45a8ff 762 void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
bogdanm 0:9b334a45a8ff 763 {
bogdanm 0:9b334a45a8ff 764 /* Check the parameters */
bogdanm 0:9b334a45a8ff 765 assert_param(IS_SPI_ALL_PERIPH(SPIx));
bogdanm 0:9b334a45a8ff 766 assert_param(IS_FUNCTIONAL_STATE(NewState));
bogdanm 0:9b334a45a8ff 767 if (NewState != DISABLE)
bogdanm 0:9b334a45a8ff 768 {
bogdanm 0:9b334a45a8ff 769 /* Enable the selected SPI SS output */
bogdanm 0:9b334a45a8ff 770 SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE;
bogdanm 0:9b334a45a8ff 771 }
bogdanm 0:9b334a45a8ff 772 else
bogdanm 0:9b334a45a8ff 773 {
bogdanm 0:9b334a45a8ff 774 /* Disable the selected SPI SS output */
bogdanm 0:9b334a45a8ff 775 SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);
bogdanm 0:9b334a45a8ff 776 }
bogdanm 0:9b334a45a8ff 777 }
bogdanm 0:9b334a45a8ff 778
bogdanm 0:9b334a45a8ff 779 /**
bogdanm 0:9b334a45a8ff 780 * @brief Enables or disables the NSS pulse management mode.
bogdanm 0:9b334a45a8ff 781 * @note This function can be called only after the SPI_Init() function has
bogdanm 0:9b334a45a8ff 782 * been called.
bogdanm 0:9b334a45a8ff 783 * @note When TI mode is selected, the control bits NSSP is not taken into
bogdanm 0:9b334a45a8ff 784 * consideration and are configured by hardware respectively to the
bogdanm 0:9b334a45a8ff 785 * TI mode requirements.
bogdanm 0:9b334a45a8ff 786 * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
bogdanm 0:9b334a45a8ff 787 * @param NewState: new state of the NSS pulse management mode.
bogdanm 0:9b334a45a8ff 788 * This parameter can be: ENABLE or DISABLE.
bogdanm 0:9b334a45a8ff 789 * @retval None
bogdanm 0:9b334a45a8ff 790 */
bogdanm 0:9b334a45a8ff 791 void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
bogdanm 0:9b334a45a8ff 792 {
bogdanm 0:9b334a45a8ff 793 /* Check the parameters */
bogdanm 0:9b334a45a8ff 794 assert_param(IS_SPI_ALL_PERIPH(SPIx));
bogdanm 0:9b334a45a8ff 795 assert_param(IS_FUNCTIONAL_STATE(NewState));
bogdanm 0:9b334a45a8ff 796
bogdanm 0:9b334a45a8ff 797 if (NewState != DISABLE)
bogdanm 0:9b334a45a8ff 798 {
bogdanm 0:9b334a45a8ff 799 /* Enable the NSS pulse management mode */
bogdanm 0:9b334a45a8ff 800 SPIx->CR2 |= SPI_CR2_NSSP;
bogdanm 0:9b334a45a8ff 801 }
bogdanm 0:9b334a45a8ff 802 else
bogdanm 0:9b334a45a8ff 803 {
bogdanm 0:9b334a45a8ff 804 /* Disable the NSS pulse management mode */
bogdanm 0:9b334a45a8ff 805 SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_NSSP);
bogdanm 0:9b334a45a8ff 806 }
bogdanm 0:9b334a45a8ff 807 }
bogdanm 0:9b334a45a8ff 808
bogdanm 0:9b334a45a8ff 809 /**
bogdanm 0:9b334a45a8ff 810 * @}
bogdanm 0:9b334a45a8ff 811 */
bogdanm 0:9b334a45a8ff 812
bogdanm 0:9b334a45a8ff 813 /** @defgroup SPI_Group2 Data transfers functions
bogdanm 0:9b334a45a8ff 814 * @brief Data transfers functions
bogdanm 0:9b334a45a8ff 815 *
bogdanm 0:9b334a45a8ff 816 @verbatim
bogdanm 0:9b334a45a8ff 817 ===============================================================================
bogdanm 0:9b334a45a8ff 818 ##### Data transfers functions #####
bogdanm 0:9b334a45a8ff 819 ===============================================================================
bogdanm 0:9b334a45a8ff 820 [..] This section provides a set of functions allowing to manage the SPI or I2S
bogdanm 0:9b334a45a8ff 821 data transfers.
bogdanm 0:9b334a45a8ff 822 [..] In reception, data are received and then stored into an internal Rx buffer while
bogdanm 0:9b334a45a8ff 823 In transmission, data are first stored into an internal Tx buffer before being
bogdanm 0:9b334a45a8ff 824 transmitted.
bogdanm 0:9b334a45a8ff 825 [..] The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData()
bogdanm 0:9b334a45a8ff 826 function and returns the Rx buffered value. Whereas a write access to the SPI_DR
bogdanm 0:9b334a45a8ff 827 can be done using SPI_I2S_SendData() function and stores the written data into
bogdanm 0:9b334a45a8ff 828 Tx buffer.
bogdanm 0:9b334a45a8ff 829
bogdanm 0:9b334a45a8ff 830 @endverbatim
bogdanm 0:9b334a45a8ff 831 * @{
bogdanm 0:9b334a45a8ff 832 */
bogdanm 0:9b334a45a8ff 833
bogdanm 0:9b334a45a8ff 834 /**
bogdanm 0:9b334a45a8ff 835 * @brief Transmits a Data through the SPIx peripheral.
bogdanm 0:9b334a45a8ff 836 * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
bogdanm 0:9b334a45a8ff 837 * @param Data: Data to be transmitted.
bogdanm 0:9b334a45a8ff 838 * @retval None
bogdanm 0:9b334a45a8ff 839 */
bogdanm 0:9b334a45a8ff 840 void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data)
bogdanm 0:9b334a45a8ff 841 {
bogdanm 0:9b334a45a8ff 842 uint32_t spixbase = 0x00;
bogdanm 0:9b334a45a8ff 843
bogdanm 0:9b334a45a8ff 844 /* Check the parameters */
bogdanm 0:9b334a45a8ff 845 assert_param(IS_SPI_ALL_PERIPH(SPIx));
bogdanm 0:9b334a45a8ff 846
bogdanm 0:9b334a45a8ff 847 spixbase = (uint32_t)SPIx;
bogdanm 0:9b334a45a8ff 848 spixbase += 0x0C;
bogdanm 0:9b334a45a8ff 849
bogdanm 0:9b334a45a8ff 850 *(__IO uint8_t *) spixbase = Data;
bogdanm 0:9b334a45a8ff 851 }
bogdanm 0:9b334a45a8ff 852
bogdanm 0:9b334a45a8ff 853 /**
bogdanm 0:9b334a45a8ff 854 * @brief Transmits a Data through the SPIx/I2Sx peripheral.
bogdanm 0:9b334a45a8ff 855 * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
bogdanm 0:9b334a45a8ff 856 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
bogdanm 0:9b334a45a8ff 857 * @param Data: Data to be transmitted.
bogdanm 0:9b334a45a8ff 858 * @retval None
bogdanm 0:9b334a45a8ff 859 */
bogdanm 0:9b334a45a8ff 860 void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data)
bogdanm 0:9b334a45a8ff 861 {
bogdanm 0:9b334a45a8ff 862 /* Check the parameters */
bogdanm 0:9b334a45a8ff 863 assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
bogdanm 0:9b334a45a8ff 864
bogdanm 0:9b334a45a8ff 865 SPIx->DR = (uint16_t)Data;
bogdanm 0:9b334a45a8ff 866 }
bogdanm 0:9b334a45a8ff 867
bogdanm 0:9b334a45a8ff 868 /**
bogdanm 0:9b334a45a8ff 869 * @brief Returns the most recent received data by the SPIx peripheral.
bogdanm 0:9b334a45a8ff 870 * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
bogdanm 0:9b334a45a8ff 871 * @retval The value of the received data.
bogdanm 0:9b334a45a8ff 872 */
bogdanm 0:9b334a45a8ff 873 uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx)
bogdanm 0:9b334a45a8ff 874 {
bogdanm 0:9b334a45a8ff 875 uint32_t spixbase = 0x00;
bogdanm 0:9b334a45a8ff 876
bogdanm 0:9b334a45a8ff 877 /* Check the parameters */
bogdanm 0:9b334a45a8ff 878 assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
bogdanm 0:9b334a45a8ff 879
bogdanm 0:9b334a45a8ff 880 spixbase = (uint32_t)SPIx;
bogdanm 0:9b334a45a8ff 881 spixbase += 0x0C;
bogdanm 0:9b334a45a8ff 882
bogdanm 0:9b334a45a8ff 883 return *(__IO uint8_t *) spixbase;
bogdanm 0:9b334a45a8ff 884 }
bogdanm 0:9b334a45a8ff 885
bogdanm 0:9b334a45a8ff 886 /**
bogdanm 0:9b334a45a8ff 887 * @brief Returns the most recent received data by the SPIx peripheral.
bogdanm 0:9b334a45a8ff 888 * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
bogdanm 0:9b334a45a8ff 889 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
bogdanm 0:9b334a45a8ff 890 * @retval The value of the received data.
bogdanm 0:9b334a45a8ff 891 */
bogdanm 0:9b334a45a8ff 892 uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx)
bogdanm 0:9b334a45a8ff 893 {
bogdanm 0:9b334a45a8ff 894 /* Check the parameters */
bogdanm 0:9b334a45a8ff 895 assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
bogdanm 0:9b334a45a8ff 896
bogdanm 0:9b334a45a8ff 897 return SPIx->DR;
bogdanm 0:9b334a45a8ff 898 }
bogdanm 0:9b334a45a8ff 899 /**
bogdanm 0:9b334a45a8ff 900 * @}
bogdanm 0:9b334a45a8ff 901 */
bogdanm 0:9b334a45a8ff 902
bogdanm 0:9b334a45a8ff 903 /** @defgroup SPI_Group3 Hardware CRC Calculation functions
bogdanm 0:9b334a45a8ff 904 * @brief Hardware CRC Calculation functions
bogdanm 0:9b334a45a8ff 905 *
bogdanm 0:9b334a45a8ff 906 @verbatim
bogdanm 0:9b334a45a8ff 907 ===============================================================================
bogdanm 0:9b334a45a8ff 908 ##### Hardware CRC Calculation functions #####
bogdanm 0:9b334a45a8ff 909 ===============================================================================
bogdanm 0:9b334a45a8ff 910 [..] This section provides a set of functions allowing to manage the SPI CRC hardware
bogdanm 0:9b334a45a8ff 911 calculation.
bogdanm 0:9b334a45a8ff 912 [..] SPI communication using CRC is possible through the following procedure:
bogdanm 0:9b334a45a8ff 913 (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler,
bogdanm 0:9b334a45a8ff 914 Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
bogdanm 0:9b334a45a8ff 915 function.
bogdanm 0:9b334a45a8ff 916 (#) Enable the CRC calculation using the SPI_CalculateCRC() function.
bogdanm 0:9b334a45a8ff 917 (#) Enable the SPI using the SPI_Cmd() function
bogdanm 0:9b334a45a8ff 918 (#) Before writing the last data to the TX buffer, set the CRCNext bit using the
bogdanm 0:9b334a45a8ff 919 SPI_TransmitCRC() function to indicate that after transmission of the last
bogdanm 0:9b334a45a8ff 920 data, the CRC should be transmitted.
bogdanm 0:9b334a45a8ff 921 (#) After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT
bogdanm 0:9b334a45a8ff 922 bit is reset. The CRC is also received and compared against the SPI_RXCRCR
bogdanm 0:9b334a45a8ff 923 value.
bogdanm 0:9b334a45a8ff 924 If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt
bogdanm 0:9b334a45a8ff 925 can be generated when the SPI_I2S_IT_ERR interrupt is enabled.
bogdanm 0:9b334a45a8ff 926 [..]
bogdanm 0:9b334a45a8ff 927 (@)
bogdanm 0:9b334a45a8ff 928 (+@) It is advised to don't read the calculate CRC values during the communication.
bogdanm 0:9b334a45a8ff 929 (+@) When the SPI is in slave mode, be careful to enable CRC calculation only
bogdanm 0:9b334a45a8ff 930 when the clock is stable, that is, when the clock is in the steady state.
bogdanm 0:9b334a45a8ff 931 If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive
bogdanm 0:9b334a45a8ff 932 to the SCK slave input clock as soon as CRCEN is set, and this, whatever
bogdanm 0:9b334a45a8ff 933 the value of the SPE bit.
bogdanm 0:9b334a45a8ff 934 (+@) With high bitrate frequencies, be careful when transmitting the CRC.
bogdanm 0:9b334a45a8ff 935 As the number of used CPU cycles has to be as low as possible in the CRC
bogdanm 0:9b334a45a8ff 936 transfer phase, it is forbidden to call software functions in the CRC
bogdanm 0:9b334a45a8ff 937 transmission sequence to avoid errors in the last data and CRC reception.
bogdanm 0:9b334a45a8ff 938 In fact, CRCNEXT bit has to be written before the end of the transmission/reception
bogdanm 0:9b334a45a8ff 939 of the last data.
bogdanm 0:9b334a45a8ff 940 (+@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the
bogdanm 0:9b334a45a8ff 941 degradation of the SPI speed performance due to CPU accesses impacting the
bogdanm 0:9b334a45a8ff 942 SPI bandwidth.
bogdanm 0:9b334a45a8ff 943 (+@) When the STM32F30x are configured as slaves and the NSS hardware mode is
bogdanm 0:9b334a45a8ff 944 used, the NSS pin needs to be kept low between the data phase and the CRC
bogdanm 0:9b334a45a8ff 945 phase.
bogdanm 0:9b334a45a8ff 946 (+@) When the SPI is configured in slave mode with the CRC feature enabled, CRC
bogdanm 0:9b334a45a8ff 947 calculation takes place even if a high level is applied on the NSS pin.
bogdanm 0:9b334a45a8ff 948 This may happen for example in case of a multislave environment where the
bogdanm 0:9b334a45a8ff 949 communication master addresses slaves alternately.
bogdanm 0:9b334a45a8ff 950 (+@) Between a slave deselection (high level on NSS) and a new slave selection
bogdanm 0:9b334a45a8ff 951 (low level on NSS), the CRC value should be cleared on both master and slave
bogdanm 0:9b334a45a8ff 952 sides in order to resynchronize the master and slave for their respective
bogdanm 0:9b334a45a8ff 953 CRC calculation.
bogdanm 0:9b334a45a8ff 954 [..]
bogdanm 0:9b334a45a8ff 955 (@) To clear the CRC, follow the procedure below:
bogdanm 0:9b334a45a8ff 956 (#@) Disable SPI using the SPI_Cmd() function.
bogdanm 0:9b334a45a8ff 957 (#@) Disable the CRC calculation using the SPI_CalculateCRC() function.
bogdanm 0:9b334a45a8ff 958 (#@) Enable the CRC calculation using the SPI_CalculateCRC() function.
bogdanm 0:9b334a45a8ff 959 (#@) Enable SPI using the SPI_Cmd() function.
bogdanm 0:9b334a45a8ff 960
bogdanm 0:9b334a45a8ff 961 @endverbatim
bogdanm 0:9b334a45a8ff 962 * @{
bogdanm 0:9b334a45a8ff 963 */
bogdanm 0:9b334a45a8ff 964
bogdanm 0:9b334a45a8ff 965 /**
bogdanm 0:9b334a45a8ff 966 * @brief Configures the CRC calculation length for the selected SPI.
bogdanm 0:9b334a45a8ff 967 * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
bogdanm 0:9b334a45a8ff 968 * @param SPI_CRCLength: specifies the SPI CRC calculation length.
bogdanm 0:9b334a45a8ff 969 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 970 * @arg SPI_CRCLength_8b: Set CRC Calculation to 8 bits
bogdanm 0:9b334a45a8ff 971 * @arg SPI_CRCLength_16b: Set CRC Calculation to 16 bits
bogdanm 0:9b334a45a8ff 972 * @retval None
bogdanm 0:9b334a45a8ff 973 */
bogdanm 0:9b334a45a8ff 974 void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength)
bogdanm 0:9b334a45a8ff 975 {
bogdanm 0:9b334a45a8ff 976 /* Check the parameters */
bogdanm 0:9b334a45a8ff 977 assert_param(IS_SPI_ALL_PERIPH(SPIx));
bogdanm 0:9b334a45a8ff 978 assert_param(IS_SPI_CRC_LENGTH(SPI_CRCLength));
bogdanm 0:9b334a45a8ff 979
bogdanm 0:9b334a45a8ff 980 /* Clear CRCL bit */
bogdanm 0:9b334a45a8ff 981 SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCL);
bogdanm 0:9b334a45a8ff 982
bogdanm 0:9b334a45a8ff 983 /* Set new CRCL bit value */
bogdanm 0:9b334a45a8ff 984 SPIx->CR1 |= SPI_CRCLength;
bogdanm 0:9b334a45a8ff 985 }
bogdanm 0:9b334a45a8ff 986
bogdanm 0:9b334a45a8ff 987 /**
bogdanm 0:9b334a45a8ff 988 * @brief Enables or disables the CRC value calculation of the transferred bytes.
bogdanm 0:9b334a45a8ff 989 * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
bogdanm 0:9b334a45a8ff 990 * @param NewState: new state of the SPIx CRC value calculation.
bogdanm 0:9b334a45a8ff 991 * This parameter can be: ENABLE or DISABLE.
bogdanm 0:9b334a45a8ff 992 * @retval None
bogdanm 0:9b334a45a8ff 993 */
bogdanm 0:9b334a45a8ff 994 void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
bogdanm 0:9b334a45a8ff 995 {
bogdanm 0:9b334a45a8ff 996 /* Check the parameters */
bogdanm 0:9b334a45a8ff 997 assert_param(IS_SPI_ALL_PERIPH(SPIx));
bogdanm 0:9b334a45a8ff 998 assert_param(IS_FUNCTIONAL_STATE(NewState));
bogdanm 0:9b334a45a8ff 999
bogdanm 0:9b334a45a8ff 1000 if (NewState != DISABLE)
bogdanm 0:9b334a45a8ff 1001 {
bogdanm 0:9b334a45a8ff 1002 /* Enable the selected SPI CRC calculation */
bogdanm 0:9b334a45a8ff 1003 SPIx->CR1 |= SPI_CR1_CRCEN;
bogdanm 0:9b334a45a8ff 1004 }
bogdanm 0:9b334a45a8ff 1005 else
bogdanm 0:9b334a45a8ff 1006 {
bogdanm 0:9b334a45a8ff 1007 /* Disable the selected SPI CRC calculation */
bogdanm 0:9b334a45a8ff 1008 SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);
bogdanm 0:9b334a45a8ff 1009 }
bogdanm 0:9b334a45a8ff 1010 }
bogdanm 0:9b334a45a8ff 1011
bogdanm 0:9b334a45a8ff 1012 /**
bogdanm 0:9b334a45a8ff 1013 * @brief Transmits the SPIx CRC value.
bogdanm 0:9b334a45a8ff 1014 * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
bogdanm 0:9b334a45a8ff 1015 * @retval None
bogdanm 0:9b334a45a8ff 1016 */
bogdanm 0:9b334a45a8ff 1017 void SPI_TransmitCRC(SPI_TypeDef* SPIx)
bogdanm 0:9b334a45a8ff 1018 {
bogdanm 0:9b334a45a8ff 1019 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1020 assert_param(IS_SPI_ALL_PERIPH(SPIx));
bogdanm 0:9b334a45a8ff 1021
bogdanm 0:9b334a45a8ff 1022 /* Enable the selected SPI CRC transmission */
bogdanm 0:9b334a45a8ff 1023 SPIx->CR1 |= SPI_CR1_CRCNEXT;
bogdanm 0:9b334a45a8ff 1024 }
bogdanm 0:9b334a45a8ff 1025
bogdanm 0:9b334a45a8ff 1026 /**
bogdanm 0:9b334a45a8ff 1027 * @brief Returns the transmit or the receive CRC register value for the specified SPI.
bogdanm 0:9b334a45a8ff 1028 * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
bogdanm 0:9b334a45a8ff 1029 * @param SPI_CRC: specifies the CRC register to be read.
bogdanm 0:9b334a45a8ff 1030 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1031 * @arg SPI_CRC_Tx: Selects Tx CRC register
bogdanm 0:9b334a45a8ff 1032 * @arg SPI_CRC_Rx: Selects Rx CRC register
bogdanm 0:9b334a45a8ff 1033 * @retval The selected CRC register value..
bogdanm 0:9b334a45a8ff 1034 */
bogdanm 0:9b334a45a8ff 1035 uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
bogdanm 0:9b334a45a8ff 1036 {
bogdanm 0:9b334a45a8ff 1037 uint16_t crcreg = 0;
bogdanm 0:9b334a45a8ff 1038 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1039 assert_param(IS_SPI_ALL_PERIPH(SPIx));
bogdanm 0:9b334a45a8ff 1040 assert_param(IS_SPI_CRC(SPI_CRC));
bogdanm 0:9b334a45a8ff 1041
bogdanm 0:9b334a45a8ff 1042 if (SPI_CRC != SPI_CRC_Rx)
bogdanm 0:9b334a45a8ff 1043 {
bogdanm 0:9b334a45a8ff 1044 /* Get the Tx CRC register */
bogdanm 0:9b334a45a8ff 1045 crcreg = SPIx->TXCRCR;
bogdanm 0:9b334a45a8ff 1046 }
bogdanm 0:9b334a45a8ff 1047 else
bogdanm 0:9b334a45a8ff 1048 {
bogdanm 0:9b334a45a8ff 1049 /* Get the Rx CRC register */
bogdanm 0:9b334a45a8ff 1050 crcreg = SPIx->RXCRCR;
bogdanm 0:9b334a45a8ff 1051 }
bogdanm 0:9b334a45a8ff 1052 /* Return the selected CRC register */
bogdanm 0:9b334a45a8ff 1053 return crcreg;
bogdanm 0:9b334a45a8ff 1054 }
bogdanm 0:9b334a45a8ff 1055
bogdanm 0:9b334a45a8ff 1056 /**
bogdanm 0:9b334a45a8ff 1057 * @brief Returns the CRC Polynomial register value for the specified SPI.
bogdanm 0:9b334a45a8ff 1058 * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
bogdanm 0:9b334a45a8ff 1059 * @retval The CRC Polynomial register value.
bogdanm 0:9b334a45a8ff 1060 */
bogdanm 0:9b334a45a8ff 1061 uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
bogdanm 0:9b334a45a8ff 1062 {
bogdanm 0:9b334a45a8ff 1063 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1064 assert_param(IS_SPI_ALL_PERIPH(SPIx));
bogdanm 0:9b334a45a8ff 1065
bogdanm 0:9b334a45a8ff 1066 /* Return the CRC polynomial register */
bogdanm 0:9b334a45a8ff 1067 return SPIx->CRCPR;
bogdanm 0:9b334a45a8ff 1068 }
bogdanm 0:9b334a45a8ff 1069
bogdanm 0:9b334a45a8ff 1070 /**
bogdanm 0:9b334a45a8ff 1071 * @}
bogdanm 0:9b334a45a8ff 1072 */
bogdanm 0:9b334a45a8ff 1073
bogdanm 0:9b334a45a8ff 1074 /** @defgroup SPI_Group4 DMA transfers management functions
bogdanm 0:9b334a45a8ff 1075 * @brief DMA transfers management functions
bogdanm 0:9b334a45a8ff 1076 *
bogdanm 0:9b334a45a8ff 1077 @verbatim
bogdanm 0:9b334a45a8ff 1078 ===============================================================================
bogdanm 0:9b334a45a8ff 1079 ##### DMA transfers management functions #####
bogdanm 0:9b334a45a8ff 1080 ===============================================================================
bogdanm 0:9b334a45a8ff 1081
bogdanm 0:9b334a45a8ff 1082 @endverbatim
bogdanm 0:9b334a45a8ff 1083 * @{
bogdanm 0:9b334a45a8ff 1084 */
bogdanm 0:9b334a45a8ff 1085
bogdanm 0:9b334a45a8ff 1086 /**
bogdanm 0:9b334a45a8ff 1087 * @brief Enables or disables the SPIx/I2Sx DMA interface.
bogdanm 0:9b334a45a8ff 1088 * @param SPIx:To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
bogdanm 0:9b334a45a8ff 1089 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
bogdanm 0:9b334a45a8ff 1090 * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled.
bogdanm 0:9b334a45a8ff 1091 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 1092 * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
bogdanm 0:9b334a45a8ff 1093 * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
bogdanm 0:9b334a45a8ff 1094 * @param NewState: new state of the selected SPI DMA transfer request.
bogdanm 0:9b334a45a8ff 1095 * This parameter can be: ENABLE or DISABLE.
bogdanm 0:9b334a45a8ff 1096 * @retval None
bogdanm 0:9b334a45a8ff 1097 */
bogdanm 0:9b334a45a8ff 1098 void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
bogdanm 0:9b334a45a8ff 1099 {
bogdanm 0:9b334a45a8ff 1100 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1101 assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
bogdanm 0:9b334a45a8ff 1102 assert_param(IS_FUNCTIONAL_STATE(NewState));
bogdanm 0:9b334a45a8ff 1103 assert_param(IS_SPI_I2S_DMA_REQ(SPI_I2S_DMAReq));
bogdanm 0:9b334a45a8ff 1104
bogdanm 0:9b334a45a8ff 1105 if (NewState != DISABLE)
bogdanm 0:9b334a45a8ff 1106 {
bogdanm 0:9b334a45a8ff 1107 /* Enable the selected SPI DMA requests */
bogdanm 0:9b334a45a8ff 1108 SPIx->CR2 |= SPI_I2S_DMAReq;
bogdanm 0:9b334a45a8ff 1109 }
bogdanm 0:9b334a45a8ff 1110 else
bogdanm 0:9b334a45a8ff 1111 {
bogdanm 0:9b334a45a8ff 1112 /* Disable the selected SPI DMA requests */
bogdanm 0:9b334a45a8ff 1113 SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
bogdanm 0:9b334a45a8ff 1114 }
bogdanm 0:9b334a45a8ff 1115 }
bogdanm 0:9b334a45a8ff 1116
bogdanm 0:9b334a45a8ff 1117 /**
bogdanm 0:9b334a45a8ff 1118 * @brief Configures the number of data to transfer type(Even/Odd) for the DMA
bogdanm 0:9b334a45a8ff 1119 * last transfers and for the selected SPI.
bogdanm 0:9b334a45a8ff 1120 * @note This function have a meaning only if DMA mode is selected and if
bogdanm 0:9b334a45a8ff 1121 * the packing mode is used (data length <= 8 and DMA transfer size halfword)
bogdanm 0:9b334a45a8ff 1122 * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
bogdanm 0:9b334a45a8ff 1123 * @param SPI_LastDMATransfer: specifies the SPI last DMA transfers state.
bogdanm 0:9b334a45a8ff 1124 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1125 * @arg SPI_LastDMATransfer_TxEvenRxEven: Number of data for transmission Even
bogdanm 0:9b334a45a8ff 1126 * and number of data for reception Even.
bogdanm 0:9b334a45a8ff 1127 * @arg SPI_LastDMATransfer_TxOddRxEven: Number of data for transmission Odd
bogdanm 0:9b334a45a8ff 1128 * and number of data for reception Even.
bogdanm 0:9b334a45a8ff 1129 * @arg SPI_LastDMATransfer_TxEvenRxOdd: Number of data for transmission Even
bogdanm 0:9b334a45a8ff 1130 * and number of data for reception Odd.
bogdanm 0:9b334a45a8ff 1131 * @arg SPI_LastDMATransfer_TxOddRxOdd: RNumber of data for transmission Odd
bogdanm 0:9b334a45a8ff 1132 * and number of data for reception Odd.
bogdanm 0:9b334a45a8ff 1133 * @retval None
bogdanm 0:9b334a45a8ff 1134 */
bogdanm 0:9b334a45a8ff 1135 void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer)
bogdanm 0:9b334a45a8ff 1136 {
bogdanm 0:9b334a45a8ff 1137 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1138 assert_param(IS_SPI_ALL_PERIPH(SPIx));
bogdanm 0:9b334a45a8ff 1139 assert_param(IS_SPI_LAST_DMA_TRANSFER(SPI_LastDMATransfer));
bogdanm 0:9b334a45a8ff 1140
bogdanm 0:9b334a45a8ff 1141 /* Clear LDMA_TX and LDMA_RX bits */
bogdanm 0:9b334a45a8ff 1142 SPIx->CR2 &= CR2_LDMA_MASK;
bogdanm 0:9b334a45a8ff 1143
bogdanm 0:9b334a45a8ff 1144 /* Set new LDMA_TX and LDMA_RX bits value */
bogdanm 0:9b334a45a8ff 1145 SPIx->CR2 |= SPI_LastDMATransfer;
bogdanm 0:9b334a45a8ff 1146 }
bogdanm 0:9b334a45a8ff 1147
bogdanm 0:9b334a45a8ff 1148 /**
bogdanm 0:9b334a45a8ff 1149 * @}
bogdanm 0:9b334a45a8ff 1150 */
bogdanm 0:9b334a45a8ff 1151
bogdanm 0:9b334a45a8ff 1152 /** @defgroup SPI_Group5 Interrupts and flags management functions
bogdanm 0:9b334a45a8ff 1153 * @brief Interrupts and flags management functions
bogdanm 0:9b334a45a8ff 1154 *
bogdanm 0:9b334a45a8ff 1155 @verbatim
bogdanm 0:9b334a45a8ff 1156 ===============================================================================
bogdanm 0:9b334a45a8ff 1157 ##### Interrupts and flags management functions #####
bogdanm 0:9b334a45a8ff 1158 ===============================================================================
bogdanm 0:9b334a45a8ff 1159 [..] This section provides a set of functions allowing to configure the SPI/I2S
bogdanm 0:9b334a45a8ff 1160 Interrupts sources and check or clear the flags or pending bits status.
bogdanm 0:9b334a45a8ff 1161 The user should identify which mode will be used in his application to manage
bogdanm 0:9b334a45a8ff 1162 the communication: Polling mode, Interrupt mode or DMA mode.
bogdanm 0:9b334a45a8ff 1163
bogdanm 0:9b334a45a8ff 1164 *** Polling Mode ***
bogdanm 0:9b334a45a8ff 1165 ====================
bogdanm 0:9b334a45a8ff 1166 [..] In Polling Mode, the SPI/I2S communication can be managed by 9 flags:
bogdanm 0:9b334a45a8ff 1167 (#) SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register.
bogdanm 0:9b334a45a8ff 1168 (#) SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register.
bogdanm 0:9b334a45a8ff 1169 (#) SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI.
bogdanm 0:9b334a45a8ff 1170 (#) SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur.
bogdanm 0:9b334a45a8ff 1171 (#) SPI_FLAG_MODF : to indicate if a Mode Fault error occur.
bogdanm 0:9b334a45a8ff 1172 (#) SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur.
bogdanm 0:9b334a45a8ff 1173 (#) SPI_I2S_FLAG_FRE: to indicate a Frame Format error occurs.
bogdanm 0:9b334a45a8ff 1174 (#) I2S_FLAG_UDR: to indicate an Underrun error occurs.
bogdanm 0:9b334a45a8ff 1175 (#) I2S_FLAG_CHSIDE: to indicate Channel Side.
bogdanm 0:9b334a45a8ff 1176 [..]
bogdanm 0:9b334a45a8ff 1177 (@) Do not use the BSY flag to handle each data transmission or reception.
bogdanm 0:9b334a45a8ff 1178 It is better to use the TXE and RXNE flags instead.
bogdanm 0:9b334a45a8ff 1179 [..] In this Mode it is advised to use the following functions:
bogdanm 0:9b334a45a8ff 1180 (+) FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
bogdanm 0:9b334a45a8ff 1181 (+) void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
bogdanm 0:9b334a45a8ff 1182
bogdanm 0:9b334a45a8ff 1183 *** Interrupt Mode ***
bogdanm 0:9b334a45a8ff 1184 ======================
bogdanm 0:9b334a45a8ff 1185 [..] In Interrupt Mode, the SPI/I2S communication can be managed by 3 interrupt sources
bogdanm 0:9b334a45a8ff 1186 and 5 pending bits:
bogdanm 0:9b334a45a8ff 1187 [..] Pending Bits:
bogdanm 0:9b334a45a8ff 1188 (#) SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register.
bogdanm 0:9b334a45a8ff 1189 (#) SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register.
bogdanm 0:9b334a45a8ff 1190 (#) SPI_I2S_IT_OVR : to indicate if an Overrun error occur.
bogdanm 0:9b334a45a8ff 1191 (#) I2S_IT_UDR : to indicate an Underrun Error occurs.
bogdanm 0:9b334a45a8ff 1192 (#) SPI_I2S_FLAG_FRE : to indicate a Frame Format error occurs.
bogdanm 0:9b334a45a8ff 1193 [..] Interrupt Source:
bogdanm 0:9b334a45a8ff 1194 (#) SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty
bogdanm 0:9b334a45a8ff 1195 interrupt.
bogdanm 0:9b334a45a8ff 1196 (#) SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not
bogdanm 0:9b334a45a8ff 1197 empty interrupt.
bogdanm 0:9b334a45a8ff 1198 (#) SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt.
bogdanm 0:9b334a45a8ff 1199 [..] In this Mode it is advised to use the following functions:
bogdanm 0:9b334a45a8ff 1200 (+) void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
bogdanm 0:9b334a45a8ff 1201 (+) ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
bogdanm 0:9b334a45a8ff 1202
bogdanm 0:9b334a45a8ff 1203 *** FIFO Status ***
bogdanm 0:9b334a45a8ff 1204 ===================
bogdanm 0:9b334a45a8ff 1205 [..] It is possible to monitor the FIFO status when a transfer is ongoing using the
bogdanm 0:9b334a45a8ff 1206 following function:
bogdanm 0:9b334a45a8ff 1207 (+) uint32_t SPI_GetFIFOStatus(uint8_t SPI_FIFO_Direction);
bogdanm 0:9b334a45a8ff 1208
bogdanm 0:9b334a45a8ff 1209 *** DMA Mode ***
bogdanm 0:9b334a45a8ff 1210 ================
bogdanm 0:9b334a45a8ff 1211 [..] In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests:
bogdanm 0:9b334a45a8ff 1212 (#) SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
bogdanm 0:9b334a45a8ff 1213 (#) SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
bogdanm 0:9b334a45a8ff 1214 [..] In this Mode it is advised to use the following function:
bogdanm 0:9b334a45a8ff 1215 (+) void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
bogdanm 0:9b334a45a8ff 1216
bogdanm 0:9b334a45a8ff 1217 @endverbatim
bogdanm 0:9b334a45a8ff 1218 * @{
bogdanm 0:9b334a45a8ff 1219 */
bogdanm 0:9b334a45a8ff 1220
bogdanm 0:9b334a45a8ff 1221 /**
bogdanm 0:9b334a45a8ff 1222 * @brief Enables or disables the specified SPI/I2S interrupts.
bogdanm 0:9b334a45a8ff 1223 * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
bogdanm 0:9b334a45a8ff 1224 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
bogdanm 0:9b334a45a8ff 1225 * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled.
bogdanm 0:9b334a45a8ff 1226 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1227 * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
bogdanm 0:9b334a45a8ff 1228 * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
bogdanm 0:9b334a45a8ff 1229 * @arg SPI_I2S_IT_ERR: Error interrupt mask
bogdanm 0:9b334a45a8ff 1230 * @param NewState: new state of the specified SPI interrupt.
bogdanm 0:9b334a45a8ff 1231 * This parameter can be: ENABLE or DISABLE.
bogdanm 0:9b334a45a8ff 1232 * @retval None
bogdanm 0:9b334a45a8ff 1233 */
bogdanm 0:9b334a45a8ff 1234 void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
bogdanm 0:9b334a45a8ff 1235 {
bogdanm 0:9b334a45a8ff 1236 uint16_t itpos = 0, itmask = 0 ;
bogdanm 0:9b334a45a8ff 1237
bogdanm 0:9b334a45a8ff 1238 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1239 assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
bogdanm 0:9b334a45a8ff 1240 assert_param(IS_FUNCTIONAL_STATE(NewState));
bogdanm 0:9b334a45a8ff 1241 assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
bogdanm 0:9b334a45a8ff 1242
bogdanm 0:9b334a45a8ff 1243 /* Get the SPI IT index */
bogdanm 0:9b334a45a8ff 1244 itpos = SPI_I2S_IT >> 4;
bogdanm 0:9b334a45a8ff 1245
bogdanm 0:9b334a45a8ff 1246 /* Set the IT mask */
bogdanm 0:9b334a45a8ff 1247 itmask = (uint16_t)1 << (uint16_t)itpos;
bogdanm 0:9b334a45a8ff 1248
bogdanm 0:9b334a45a8ff 1249 if (NewState != DISABLE)
bogdanm 0:9b334a45a8ff 1250 {
bogdanm 0:9b334a45a8ff 1251 /* Enable the selected SPI interrupt */
bogdanm 0:9b334a45a8ff 1252 SPIx->CR2 |= itmask;
bogdanm 0:9b334a45a8ff 1253 }
bogdanm 0:9b334a45a8ff 1254 else
bogdanm 0:9b334a45a8ff 1255 {
bogdanm 0:9b334a45a8ff 1256 /* Disable the selected SPI interrupt */
bogdanm 0:9b334a45a8ff 1257 SPIx->CR2 &= (uint16_t)~itmask;
bogdanm 0:9b334a45a8ff 1258 }
bogdanm 0:9b334a45a8ff 1259 }
bogdanm 0:9b334a45a8ff 1260
bogdanm 0:9b334a45a8ff 1261 /**
bogdanm 0:9b334a45a8ff 1262 * @brief Returns the current SPIx Transmission FIFO filled level.
bogdanm 0:9b334a45a8ff 1263 * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
bogdanm 0:9b334a45a8ff 1264 * @retval The Transmission FIFO filling state.
bogdanm 0:9b334a45a8ff 1265 * - SPI_TransmissionFIFOStatus_Empty: when FIFO is empty
bogdanm 0:9b334a45a8ff 1266 * - SPI_TransmissionFIFOStatus_1QuarterFull: if more than 1 quarter-full.
bogdanm 0:9b334a45a8ff 1267 * - SPI_TransmissionFIFOStatus_HalfFull: if more than 1 half-full.
bogdanm 0:9b334a45a8ff 1268 * - SPI_TransmissionFIFOStatus_Full: when FIFO is full.
bogdanm 0:9b334a45a8ff 1269 */
bogdanm 0:9b334a45a8ff 1270 uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx)
bogdanm 0:9b334a45a8ff 1271 {
bogdanm 0:9b334a45a8ff 1272 /* Get the SPIx Transmission FIFO level bits */
bogdanm 0:9b334a45a8ff 1273 return (uint16_t)((SPIx->SR & SPI_SR_FTLVL));
bogdanm 0:9b334a45a8ff 1274 }
bogdanm 0:9b334a45a8ff 1275
bogdanm 0:9b334a45a8ff 1276 /**
bogdanm 0:9b334a45a8ff 1277 * @brief Returns the current SPIx Reception FIFO filled level.
bogdanm 0:9b334a45a8ff 1278 * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
bogdanm 0:9b334a45a8ff 1279 * @retval The Reception FIFO filling state.
bogdanm 0:9b334a45a8ff 1280 * - SPI_ReceptionFIFOStatus_Empty: when FIFO is empty
bogdanm 0:9b334a45a8ff 1281 * - SPI_ReceptionFIFOStatus_1QuarterFull: if more than 1 quarter-full.
bogdanm 0:9b334a45a8ff 1282 * - SPI_ReceptionFIFOStatus_HalfFull: if more than 1 half-full.
bogdanm 0:9b334a45a8ff 1283 * - SPI_ReceptionFIFOStatus_Full: when FIFO is full.
bogdanm 0:9b334a45a8ff 1284 */
bogdanm 0:9b334a45a8ff 1285 uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx)
bogdanm 0:9b334a45a8ff 1286 {
bogdanm 0:9b334a45a8ff 1287 /* Get the SPIx Reception FIFO level bits */
bogdanm 0:9b334a45a8ff 1288 return (uint16_t)((SPIx->SR & SPI_SR_FRLVL));
bogdanm 0:9b334a45a8ff 1289 }
bogdanm 0:9b334a45a8ff 1290
bogdanm 0:9b334a45a8ff 1291 /**
bogdanm 0:9b334a45a8ff 1292 * @brief Checks whether the specified SPI flag is set or not.
bogdanm 0:9b334a45a8ff 1293 * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
bogdanm 0:9b334a45a8ff 1294 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
bogdanm 0:9b334a45a8ff 1295 * @param SPI_I2S_FLAG: specifies the SPI flag to check.
bogdanm 0:9b334a45a8ff 1296 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1297 * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
bogdanm 0:9b334a45a8ff 1298 * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
bogdanm 0:9b334a45a8ff 1299 * @arg SPI_I2S_FLAG_BSY: Busy flag.
bogdanm 0:9b334a45a8ff 1300 * @arg SPI_I2S_FLAG_OVR: Overrun flag.
bogdanm 0:9b334a45a8ff 1301 * @arg SPI_I2S_FLAG_MODF: Mode Fault flag.
bogdanm 0:9b334a45a8ff 1302 * @arg SPI_I2S_FLAG_CRCERR: CRC Error flag.
bogdanm 0:9b334a45a8ff 1303 * @arg SPI_I2S_FLAG_FRE: TI frame format error flag.
bogdanm 0:9b334a45a8ff 1304 * @arg I2S_FLAG_UDR: Underrun Error flag.
bogdanm 0:9b334a45a8ff 1305 * @arg I2S_FLAG_CHSIDE: Channel Side flag.
bogdanm 0:9b334a45a8ff 1306 * @retval The new state of SPI_I2S_FLAG (SET or RESET).
bogdanm 0:9b334a45a8ff 1307 */
bogdanm 0:9b334a45a8ff 1308 FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
bogdanm 0:9b334a45a8ff 1309 {
bogdanm 0:9b334a45a8ff 1310 FlagStatus bitstatus = RESET;
bogdanm 0:9b334a45a8ff 1311 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1312 assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
bogdanm 0:9b334a45a8ff 1313 assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
bogdanm 0:9b334a45a8ff 1314
bogdanm 0:9b334a45a8ff 1315 /* Check the status of the specified SPI flag */
bogdanm 0:9b334a45a8ff 1316 if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
bogdanm 0:9b334a45a8ff 1317 {
bogdanm 0:9b334a45a8ff 1318 /* SPI_I2S_FLAG is set */
bogdanm 0:9b334a45a8ff 1319 bitstatus = SET;
bogdanm 0:9b334a45a8ff 1320 }
bogdanm 0:9b334a45a8ff 1321 else
bogdanm 0:9b334a45a8ff 1322 {
bogdanm 0:9b334a45a8ff 1323 /* SPI_I2S_FLAG is reset */
bogdanm 0:9b334a45a8ff 1324 bitstatus = RESET;
bogdanm 0:9b334a45a8ff 1325 }
bogdanm 0:9b334a45a8ff 1326 /* Return the SPI_I2S_FLAG status */
bogdanm 0:9b334a45a8ff 1327 return bitstatus;
bogdanm 0:9b334a45a8ff 1328 }
bogdanm 0:9b334a45a8ff 1329
bogdanm 0:9b334a45a8ff 1330 /**
bogdanm 0:9b334a45a8ff 1331 * @brief Clears the SPIx CRC Error (CRCERR) flag.
bogdanm 0:9b334a45a8ff 1332 * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
bogdanm 0:9b334a45a8ff 1333 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
bogdanm 0:9b334a45a8ff 1334 * @param SPI_I2S_FLAG: specifies the SPI flag to clear.
bogdanm 0:9b334a45a8ff 1335 * This function clears only CRCERR flag.
bogdanm 0:9b334a45a8ff 1336 * @note OVR (OverRun error) flag is cleared by software sequence: a read
bogdanm 0:9b334a45a8ff 1337 * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read
bogdanm 0:9b334a45a8ff 1338 * operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
bogdanm 0:9b334a45a8ff 1339 * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write
bogdanm 0:9b334a45a8ff 1340 * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a
bogdanm 0:9b334a45a8ff 1341 * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
bogdanm 0:9b334a45a8ff 1342 * @retval None
bogdanm 0:9b334a45a8ff 1343 */
bogdanm 0:9b334a45a8ff 1344 void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
bogdanm 0:9b334a45a8ff 1345 {
bogdanm 0:9b334a45a8ff 1346 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1347 assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
bogdanm 0:9b334a45a8ff 1348 assert_param(IS_SPI_CLEAR_FLAG(SPI_I2S_FLAG));
bogdanm 0:9b334a45a8ff 1349
bogdanm 0:9b334a45a8ff 1350 /* Clear the selected SPI CRC Error (CRCERR) flag */
bogdanm 0:9b334a45a8ff 1351 SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
bogdanm 0:9b334a45a8ff 1352 }
bogdanm 0:9b334a45a8ff 1353
bogdanm 0:9b334a45a8ff 1354 /**
bogdanm 0:9b334a45a8ff 1355 * @brief Checks whether the specified SPI/I2S interrupt has occurred or not.
bogdanm 0:9b334a45a8ff 1356 * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
bogdanm 0:9b334a45a8ff 1357 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
bogdanm 0:9b334a45a8ff 1358 * @param SPI_I2S_IT: specifies the SPI interrupt source to check.
bogdanm 0:9b334a45a8ff 1359 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1360 * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
bogdanm 0:9b334a45a8ff 1361 * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
bogdanm 0:9b334a45a8ff 1362 * @arg SPI_IT_MODF: Mode Fault interrupt.
bogdanm 0:9b334a45a8ff 1363 * @arg SPI_I2S_IT_OVR: Overrun interrupt.
bogdanm 0:9b334a45a8ff 1364 * @arg I2S_IT_UDR: Underrun interrupt.
bogdanm 0:9b334a45a8ff 1365 * @arg SPI_I2S_IT_FRE: Format Error interrupt.
bogdanm 0:9b334a45a8ff 1366 * @retval The new state of SPI_I2S_IT (SET or RESET).
bogdanm 0:9b334a45a8ff 1367 */
bogdanm 0:9b334a45a8ff 1368 ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
bogdanm 0:9b334a45a8ff 1369 {
bogdanm 0:9b334a45a8ff 1370 ITStatus bitstatus = RESET;
bogdanm 0:9b334a45a8ff 1371 uint16_t itpos = 0, itmask = 0, enablestatus = 0;
bogdanm 0:9b334a45a8ff 1372
bogdanm 0:9b334a45a8ff 1373 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1374 assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
bogdanm 0:9b334a45a8ff 1375 assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
bogdanm 0:9b334a45a8ff 1376
bogdanm 0:9b334a45a8ff 1377 /* Get the SPI_I2S_IT index */
bogdanm 0:9b334a45a8ff 1378 itpos = 0x01 << (SPI_I2S_IT & 0x0F);
bogdanm 0:9b334a45a8ff 1379
bogdanm 0:9b334a45a8ff 1380 /* Get the SPI_I2S_IT IT mask */
bogdanm 0:9b334a45a8ff 1381 itmask = SPI_I2S_IT >> 4;
bogdanm 0:9b334a45a8ff 1382
bogdanm 0:9b334a45a8ff 1383 /* Set the IT mask */
bogdanm 0:9b334a45a8ff 1384 itmask = 0x01 << itmask;
bogdanm 0:9b334a45a8ff 1385
bogdanm 0:9b334a45a8ff 1386 /* Get the SPI_I2S_IT enable bit status */
bogdanm 0:9b334a45a8ff 1387 enablestatus = (SPIx->CR2 & itmask) ;
bogdanm 0:9b334a45a8ff 1388
bogdanm 0:9b334a45a8ff 1389 /* Check the status of the specified SPI interrupt */
bogdanm 0:9b334a45a8ff 1390 if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
bogdanm 0:9b334a45a8ff 1391 {
bogdanm 0:9b334a45a8ff 1392 /* SPI_I2S_IT is set */
bogdanm 0:9b334a45a8ff 1393 bitstatus = SET;
bogdanm 0:9b334a45a8ff 1394 }
bogdanm 0:9b334a45a8ff 1395 else
bogdanm 0:9b334a45a8ff 1396 {
bogdanm 0:9b334a45a8ff 1397 /* SPI_I2S_IT is reset */
bogdanm 0:9b334a45a8ff 1398 bitstatus = RESET;
bogdanm 0:9b334a45a8ff 1399 }
bogdanm 0:9b334a45a8ff 1400 /* Return the SPI_I2S_IT status */
bogdanm 0:9b334a45a8ff 1401 return bitstatus;
bogdanm 0:9b334a45a8ff 1402 }
bogdanm 0:9b334a45a8ff 1403
bogdanm 0:9b334a45a8ff 1404 /**
bogdanm 0:9b334a45a8ff 1405 * @}
bogdanm 0:9b334a45a8ff 1406 */
bogdanm 0:9b334a45a8ff 1407
bogdanm 0:9b334a45a8ff 1408 /**
bogdanm 0:9b334a45a8ff 1409 * @}
bogdanm 0:9b334a45a8ff 1410 */
bogdanm 0:9b334a45a8ff 1411
bogdanm 0:9b334a45a8ff 1412 /**
bogdanm 0:9b334a45a8ff 1413 * @}
bogdanm 0:9b334a45a8ff 1414 */
bogdanm 0:9b334a45a8ff 1415
bogdanm 0:9b334a45a8ff 1416 /**
bogdanm 0:9b334a45a8ff 1417 * @}
bogdanm 0:9b334a45a8ff 1418 */
bogdanm 0:9b334a45a8ff 1419
bogdanm 0:9b334a45a8ff 1420 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/