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targets/cmsis/TARGET_NXP/TARGET_LPC13XX/system_LPC13Uxx.h@70:b3a5af880266, 2016-02-23 (annotated)

Committer:
neurofun
Date:
Tue Feb 23 21:59:35 2016 +0000
Revision:
70:b3a5af880266
Parent:
0:9b334a45a8ff 
Edited DAC routines to allow for the simultaneous use of three channels from two DACs as seen on the STM32F334R8 and STM32F303K8. Edited ADC routines to allow for the simultaneous use of more than one ADC.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 2 * @file system_LPC13Uxx.h
bogdanm 0:9b334a45a8ff 3 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File
bogdanm 0:9b334a45a8ff 4 * for the NXP LPC13Uxx Device Series
bogdanm 0:9b334a45a8ff 5 * @version V1.10
bogdanm 0:9b334a45a8ff 6 * @date 24. November 2010
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * @note
bogdanm 0:9b334a45a8ff 9 * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * @par
bogdanm 0:9b334a45a8ff 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
bogdanm 0:9b334a45a8ff 13 * processor based microcontrollers. This file can be freely distributed
bogdanm 0:9b334a45a8ff 14 * within development tools that are supporting such ARM based processors.
bogdanm 0:9b334a45a8ff 15 *
bogdanm 0:9b334a45a8ff 16 * @par
bogdanm 0:9b334a45a8ff 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
bogdanm 0:9b334a45a8ff 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
bogdanm 0:9b334a45a8ff 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
bogdanm 0:9b334a45a8ff 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
bogdanm 0:9b334a45a8ff 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
bogdanm 0:9b334a45a8ff 22 *
bogdanm 0:9b334a45a8ff 23 ******************************************************************************/
bogdanm 0:9b334a45a8ff 24
bogdanm 0:9b334a45a8ff 25
bogdanm 0:9b334a45a8ff 26 #ifndef __SYSTEM_LPC13Uxx_H
bogdanm 0:9b334a45a8ff 27 #define __SYSTEM_LPC13Uxx_H
bogdanm 0:9b334a45a8ff 28
bogdanm 0:9b334a45a8ff 29 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 30 extern "C" {
bogdanm 0:9b334a45a8ff 31 #endif
bogdanm 0:9b334a45a8ff 32
bogdanm 0:9b334a45a8ff 33 #include <stdint.h>
bogdanm 0:9b334a45a8ff 34
bogdanm 0:9b334a45a8ff 35 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 /**
bogdanm 0:9b334a45a8ff 39 * Initialize the system
bogdanm 0:9b334a45a8ff 40 *
bogdanm 0:9b334a45a8ff 41 * @param none
bogdanm 0:9b334a45a8ff 42 * @return none
bogdanm 0:9b334a45a8ff 43 *
bogdanm 0:9b334a45a8ff 44 * @brief Setup the microcontroller system.
bogdanm 0:9b334a45a8ff 45 * Initialize the System and update the SystemCoreClock variable.
bogdanm 0:9b334a45a8ff 46 */
bogdanm 0:9b334a45a8ff 47 extern void SystemInit (void);
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 /**
bogdanm 0:9b334a45a8ff 50 * Update SystemCoreClock variable
bogdanm 0:9b334a45a8ff 51 *
bogdanm 0:9b334a45a8ff 52 * @param none
bogdanm 0:9b334a45a8ff 53 * @return none
bogdanm 0:9b334a45a8ff 54 *
bogdanm 0:9b334a45a8ff 55 * @brief Updates the SystemCoreClock with current core Clock
bogdanm 0:9b334a45a8ff 56 * retrieved from cpu registers.
bogdanm 0:9b334a45a8ff 57 */
bogdanm 0:9b334a45a8ff 58 extern void SystemCoreClockUpdate (void);
bogdanm 0:9b334a45a8ff 59
bogdanm 0:9b334a45a8ff 60 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 61 }
bogdanm 0:9b334a45a8ff 62 #endif
bogdanm 0:9b334a45a8ff 63
bogdanm 0:9b334a45a8ff 64 #endif /* __SYSTEM_LPC13Uxx_H */