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targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/LPC11xx.h@70:b3a5af880266, 2016-02-23 (annotated)

Committer:
neurofun
Date:
Tue Feb 23 21:59:35 2016 +0000
Revision:
70:b3a5af880266
Parent:
0:9b334a45a8ff 
Edited DAC routines to allow for the simultaneous use of three channels from two DACs as seen on the STM32F334R8 and STM32F303K8. Edited ADC routines to allow for the simultaneous use of more than one ADC.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /****************************************************************************
bogdanm 0:9b334a45a8ff 2 * $Id:: LPC11xx.h 9198 2012-05-29 usb00175 $
bogdanm 0:9b334a45a8ff 3 * Project: NXP LPC11xx software example
bogdanm 0:9b334a45a8ff 4 *
bogdanm 0:9b334a45a8ff 5 * Description:
bogdanm 0:9b334a45a8ff 6 * CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
bogdanm 0:9b334a45a8ff 7 * NXP LPC11xx Device Series
bogdanm 0:9b334a45a8ff 8
bogdanm 0:9b334a45a8ff 9 ****************************************************************************
bogdanm 0:9b334a45a8ff 10 * Software that is described herein is for illustrative purposes only
bogdanm 0:9b334a45a8ff 11 * which provides customers with programming information regarding the
bogdanm 0:9b334a45a8ff 12 * products. This software is supplied "AS IS" without any warranties.
bogdanm 0:9b334a45a8ff 13 * NXP Semiconductors assumes no responsibility or liability for the
bogdanm 0:9b334a45a8ff 14 * use of the software, conveys no license or title under any patent,
bogdanm 0:9b334a45a8ff 15 * copyright, or mask work right to the product. NXP Semiconductors
bogdanm 0:9b334a45a8ff 16 * reserves the right to make changes in the software without
bogdanm 0:9b334a45a8ff 17 * notification. NXP Semiconductors also make no representation or
bogdanm 0:9b334a45a8ff 18 * warranty that such application will be suitable for the specified
bogdanm 0:9b334a45a8ff 19 * use without further testing or modification.
bogdanm 0:9b334a45a8ff 20
bogdanm 0:9b334a45a8ff 21 * Permission to use, copy, modify, and distribute this software and its
bogdanm 0:9b334a45a8ff 22 * documentation is hereby granted, under NXP Semiconductors'
bogdanm 0:9b334a45a8ff 23 * relevant copyright in the software, without fee, provided that it
bogdanm 0:9b334a45a8ff 24 * is used in conjunction with NXP Semiconductors microcontrollers. This
bogdanm 0:9b334a45a8ff 25 * copyright, permission, and disclaimer notice must appear in all copies of
bogdanm 0:9b334a45a8ff 26 * this code.
bogdanm 0:9b334a45a8ff 27
bogdanm 0:9b334a45a8ff 28 ****************************************************************************/
bogdanm 0:9b334a45a8ff 29 #ifndef __LPC11xx_H__
bogdanm 0:9b334a45a8ff 30 #define __LPC11xx_H__
bogdanm 0:9b334a45a8ff 31
bogdanm 0:9b334a45a8ff 32 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 33 extern "C" {
bogdanm 0:9b334a45a8ff 34 #endif
bogdanm 0:9b334a45a8ff 35
bogdanm 0:9b334a45a8ff 36 /** @addtogroup LPC11xx_Definitions LPC11xx Definitions
bogdanm 0:9b334a45a8ff 37 This file defines all structures and symbols for LPC11xx:
bogdanm 0:9b334a45a8ff 38 - Registers and bitfields
bogdanm 0:9b334a45a8ff 39 - peripheral base address
bogdanm 0:9b334a45a8ff 40 - peripheral ID
bogdanm 0:9b334a45a8ff 41 - PIO definitions
bogdanm 0:9b334a45a8ff 42 @{
bogdanm 0:9b334a45a8ff 43 */
bogdanm 0:9b334a45a8ff 44
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 /******************************************************************************/
bogdanm 0:9b334a45a8ff 47 /* Processor and Core Peripherals */
bogdanm 0:9b334a45a8ff 48 /******************************************************************************/
bogdanm 0:9b334a45a8ff 49 /** @addtogroup LPC11xx_CMSIS LPC11xx CMSIS Definitions
bogdanm 0:9b334a45a8ff 50 Configuration of the Cortex-M0 Processor and Core Peripherals
bogdanm 0:9b334a45a8ff 51 @{
bogdanm 0:9b334a45a8ff 52 */
bogdanm 0:9b334a45a8ff 53
bogdanm 0:9b334a45a8ff 54 /*
bogdanm 0:9b334a45a8ff 55 * ==========================================================================
bogdanm 0:9b334a45a8ff 56 * ---------- Interrupt Number Definition -----------------------------------
bogdanm 0:9b334a45a8ff 57 * ==========================================================================
bogdanm 0:9b334a45a8ff 58 */
bogdanm 0:9b334a45a8ff 59 typedef enum IRQn
bogdanm 0:9b334a45a8ff 60 {
bogdanm 0:9b334a45a8ff 61 /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
bogdanm 0:9b334a45a8ff 62 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
bogdanm 0:9b334a45a8ff 63 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
bogdanm 0:9b334a45a8ff 64 SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
bogdanm 0:9b334a45a8ff 65 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
bogdanm 0:9b334a45a8ff 66 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
bogdanm 0:9b334a45a8ff 67
bogdanm 0:9b334a45a8ff 68 /****** LPC11Cxx or LPC11xx Specific Interrupt Numbers *******************************************************/
bogdanm 0:9b334a45a8ff 69 WAKEUP0_IRQn = 0, /*!< All I/O pins can be used as wakeup source. */
bogdanm 0:9b334a45a8ff 70 WAKEUP1_IRQn = 1, /*!< There are 13 pins in total for LPC11xx */
bogdanm 0:9b334a45a8ff 71 WAKEUP2_IRQn = 2,
bogdanm 0:9b334a45a8ff 72 WAKEUP3_IRQn = 3,
bogdanm 0:9b334a45a8ff 73 WAKEUP4_IRQn = 4,
bogdanm 0:9b334a45a8ff 74 WAKEUP5_IRQn = 5,
bogdanm 0:9b334a45a8ff 75 WAKEUP6_IRQn = 6,
bogdanm 0:9b334a45a8ff 76 WAKEUP7_IRQn = 7,
bogdanm 0:9b334a45a8ff 77 WAKEUP8_IRQn = 8,
bogdanm 0:9b334a45a8ff 78 WAKEUP9_IRQn = 9,
bogdanm 0:9b334a45a8ff 79 WAKEUP10_IRQn = 10,
bogdanm 0:9b334a45a8ff 80 WAKEUP11_IRQn = 11,
bogdanm 0:9b334a45a8ff 81 WAKEUP12_IRQn = 12,
bogdanm 0:9b334a45a8ff 82 CAN_IRQn = 13, /*!< CAN Interrupt */
bogdanm 0:9b334a45a8ff 83 SSP1_IRQn = 14, /*!< SSP1 Interrupt */
bogdanm 0:9b334a45a8ff 84 I2C_IRQn = 15, /*!< I2C Interrupt */
bogdanm 0:9b334a45a8ff 85 TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */
bogdanm 0:9b334a45a8ff 86 TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */
bogdanm 0:9b334a45a8ff 87 TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */
bogdanm 0:9b334a45a8ff 88 TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */
bogdanm 0:9b334a45a8ff 89 SSP0_IRQn = 20, /*!< SSP0 Interrupt */
bogdanm 0:9b334a45a8ff 90 UART_IRQn = 21, /*!< UART Interrupt */
bogdanm 0:9b334a45a8ff 91 Reserved0_IRQn = 22, /*!< Reserved Interrupt */
bogdanm 0:9b334a45a8ff 92 Reserved1_IRQn = 23,
bogdanm 0:9b334a45a8ff 93 ADC_IRQn = 24, /*!< A/D Converter Interrupt */
bogdanm 0:9b334a45a8ff 94 WDT_IRQn = 25, /*!< Watchdog timer Interrupt */
bogdanm 0:9b334a45a8ff 95 BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */
bogdanm 0:9b334a45a8ff 96 FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */
bogdanm 0:9b334a45a8ff 97 EINT3_IRQn = 28, /*!< External Interrupt 3 Interrupt */
bogdanm 0:9b334a45a8ff 98 EINT2_IRQn = 29, /*!< External Interrupt 2 Interrupt */
bogdanm 0:9b334a45a8ff 99 EINT1_IRQn = 30, /*!< External Interrupt 1 Interrupt */
bogdanm 0:9b334a45a8ff 100 EINT0_IRQn = 31, /*!< External Interrupt 0 Interrupt */
bogdanm 0:9b334a45a8ff 101 } IRQn_Type;
bogdanm 0:9b334a45a8ff 102
bogdanm 0:9b334a45a8ff 103 /*
bogdanm 0:9b334a45a8ff 104 * ==========================================================================
bogdanm 0:9b334a45a8ff 105 * ----------- Processor and Core Peripheral Section ------------------------
bogdanm 0:9b334a45a8ff 106 * ==========================================================================
bogdanm 0:9b334a45a8ff 107 */
bogdanm 0:9b334a45a8ff 108
bogdanm 0:9b334a45a8ff 109 /* Configuration of the Cortex-M0 Processor and Core Peripherals */
bogdanm 0:9b334a45a8ff 110 #define __MPU_PRESENT 0 /*!< MPU present or not */
bogdanm 0:9b334a45a8ff 111 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
bogdanm 0:9b334a45a8ff 112 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 0:9b334a45a8ff 113
bogdanm 0:9b334a45a8ff 114 /*@}*/ /* end of group LPC11xx_CMSIS */
bogdanm 0:9b334a45a8ff 115
bogdanm 0:9b334a45a8ff 116
bogdanm 0:9b334a45a8ff 117 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
bogdanm 0:9b334a45a8ff 118 #include "system_LPC11xx.h" /* System Header */
bogdanm 0:9b334a45a8ff 119
bogdanm 0:9b334a45a8ff 120
bogdanm 0:9b334a45a8ff 121 /******************************************************************************/
bogdanm 0:9b334a45a8ff 122 /* Device Specific Peripheral Registers structures */
bogdanm 0:9b334a45a8ff 123 /******************************************************************************/
bogdanm 0:9b334a45a8ff 124
bogdanm 0:9b334a45a8ff 125 #if defined ( __CC_ARM )
bogdanm 0:9b334a45a8ff 126 #pragma anon_unions
bogdanm 0:9b334a45a8ff 127 #endif
bogdanm 0:9b334a45a8ff 128
bogdanm 0:9b334a45a8ff 129 /*------------- System Control (SYSCON) --------------------------------------*/
bogdanm 0:9b334a45a8ff 130 /** @addtogroup LPC11xx_SYSCON LPC11xx System Control Block
bogdanm 0:9b334a45a8ff 131 @{
bogdanm 0:9b334a45a8ff 132 */
bogdanm 0:9b334a45a8ff 133 typedef struct
bogdanm 0:9b334a45a8ff 134 {
bogdanm 0:9b334a45a8ff 135 __IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 System memory remap (R/W) */
bogdanm 0:9b334a45a8ff 136 __IO uint32_t PRESETCTRL; /*!< Offset: 0x004 Peripheral reset control (R/W) */
bogdanm 0:9b334a45a8ff 137 __IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 System PLL control (R/W) */
bogdanm 0:9b334a45a8ff 138 __I uint32_t SYSPLLSTAT; /*!< Offset: 0x00C System PLL status (R/ ) */
bogdanm 0:9b334a45a8ff 139 uint32_t RESERVED0[4];
bogdanm 0:9b334a45a8ff 140
bogdanm 0:9b334a45a8ff 141 __IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 System oscillator control (R/W) */
bogdanm 0:9b334a45a8ff 142 __IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 Watchdog oscillator control (R/W) */
bogdanm 0:9b334a45a8ff 143 __IO uint32_t IRCCTRL; /*!< Offset: 0x028 IRC control (R/W) */
bogdanm 0:9b334a45a8ff 144 uint32_t RESERVED1[1];
bogdanm 0:9b334a45a8ff 145 __IO uint32_t SYSRSTSTAT; /*!< Offset: 0x030 System reset status Register (R/ ) */
bogdanm 0:9b334a45a8ff 146 uint32_t RESERVED2[3];
bogdanm 0:9b334a45a8ff 147 __IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */
bogdanm 0:9b334a45a8ff 148 __IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 System PLL clock source update enable (R/W) */
bogdanm 0:9b334a45a8ff 149 uint32_t RESERVED3[10];
bogdanm 0:9b334a45a8ff 150
bogdanm 0:9b334a45a8ff 151 __IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 Main clock source select (R/W) */
bogdanm 0:9b334a45a8ff 152 __IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 Main clock source update enable (R/W) */
bogdanm 0:9b334a45a8ff 153 __IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 System AHB clock divider (R/W) */
bogdanm 0:9b334a45a8ff 154 uint32_t RESERVED4[1];
bogdanm 0:9b334a45a8ff 155
bogdanm 0:9b334a45a8ff 156 __IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 System AHB clock control (R/W) */
bogdanm 0:9b334a45a8ff 157 uint32_t RESERVED5[4];
bogdanm 0:9b334a45a8ff 158 __IO uint32_t SSP0CLKDIV; /*!< Offset: 0x094 SSP0 clock divider (R/W) */
bogdanm 0:9b334a45a8ff 159 __IO uint32_t UARTCLKDIV; /*!< Offset: 0x098 UART clock divider (R/W) */
bogdanm 0:9b334a45a8ff 160 __IO uint32_t SSP1CLKDIV; /*!< Offset: 0x09C SSP1 clock divider (R/W) */
bogdanm 0:9b334a45a8ff 161 uint32_t RESERVED6[12];
bogdanm 0:9b334a45a8ff 162
bogdanm 0:9b334a45a8ff 163 __IO uint32_t WDTCLKSEL; /*!< Offset: 0x0D0 WDT clock source select (R/W) */
bogdanm 0:9b334a45a8ff 164 __IO uint32_t WDTCLKUEN; /*!< Offset: 0x0D4 WDT clock source update enable (R/W) */
bogdanm 0:9b334a45a8ff 165 __IO uint32_t WDTCLKDIV; /*!< Offset: 0x0D8 WDT clock divider (R/W) */
bogdanm 0:9b334a45a8ff 166 uint32_t RESERVED8[1];
bogdanm 0:9b334a45a8ff 167 __IO uint32_t CLKOUTCLKSEL; /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */
bogdanm 0:9b334a45a8ff 168 __IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */
bogdanm 0:9b334a45a8ff 169 __IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */
bogdanm 0:9b334a45a8ff 170 uint32_t RESERVED9[5];
bogdanm 0:9b334a45a8ff 171
bogdanm 0:9b334a45a8ff 172 __IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */
bogdanm 0:9b334a45a8ff 173 __IO uint32_t PIOPORCAP1; /*!< Offset: 0x104 POR captured PIO status 1 (R/ ) */
bogdanm 0:9b334a45a8ff 174 uint32_t RESERVED10[18];
bogdanm 0:9b334a45a8ff 175 __IO uint32_t BODCTRL; /*!< Offset: 0x150 BOD control (R/W) */
bogdanm 0:9b334a45a8ff 176 __IO uint32_t SYSTCKCAL; /*!< Offset: 0x154 System tick counter calibration (R/W) */
bogdanm 0:9b334a45a8ff 177
bogdanm 0:9b334a45a8ff 178 uint32_t RESERVED13[7];
bogdanm 0:9b334a45a8ff 179 __IO uint32_t NMISRC; /*!< Offset: 0x174 NMI source selection register (R/W) */
bogdanm 0:9b334a45a8ff 180 uint32_t RESERVED14[34];
bogdanm 0:9b334a45a8ff 181
bogdanm 0:9b334a45a8ff 182 __IO uint32_t STARTAPRP0; /*!< Offset: 0x200 Start logic edge control Register 0 (R/W) */
bogdanm 0:9b334a45a8ff 183 __IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */
bogdanm 0:9b334a45a8ff 184 __O uint32_t STARTRSRP0CLR; /*!< Offset: 0x208 Start logic reset Register 0 ( /W) */
bogdanm 0:9b334a45a8ff 185 __I uint32_t STARTSRP0; /*!< Offset: 0x20C Start logic status Register 0 (R/) */
bogdanm 0:9b334a45a8ff 186 __IO uint32_t STARTAPRP1; /*!< Offset: 0x210 Start logic edge control Register 0 (R/W). (LPC11UXX only) */
bogdanm 0:9b334a45a8ff 187 __IO uint32_t STARTERP1; /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W). (LPC11UXX only) */
bogdanm 0:9b334a45a8ff 188 __O uint32_t STARTRSRP1CLR; /*!< Offset: 0x218 Start logic reset Register 0 ( /W). (LPC11UXX only) */
bogdanm 0:9b334a45a8ff 189 __IO uint32_t STARTSRP1; /*!< Offset: 0x21C Start logic status Register 0 (R/W). (LPC11UXX only) */
bogdanm 0:9b334a45a8ff 190 uint32_t RESERVED17[4];
bogdanm 0:9b334a45a8ff 191
bogdanm 0:9b334a45a8ff 192 __IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */
bogdanm 0:9b334a45a8ff 193 __IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */
bogdanm 0:9b334a45a8ff 194 __IO uint32_t PDRUNCFG; /*!< Offset: 0x238 Power-down configuration Register (R/W) */
bogdanm 0:9b334a45a8ff 195 uint32_t RESERVED15[110];
bogdanm 0:9b334a45a8ff 196 __I uint32_t DEVICE_ID; /*!< Offset: 0x3F4 Device ID (R/ ) */
bogdanm 0:9b334a45a8ff 197 } LPC_SYSCON_TypeDef;
bogdanm 0:9b334a45a8ff 198 /*@}*/ /* end of group LPC11xx_SYSCON */
bogdanm 0:9b334a45a8ff 199
bogdanm 0:9b334a45a8ff 200
bogdanm 0:9b334a45a8ff 201 /*------------- Pin Connect Block (IOCON) --------------------------------*/
bogdanm 0:9b334a45a8ff 202 /** @addtogroup LPC11xx_IOCON LPC11xx I/O Configuration Block
bogdanm 0:9b334a45a8ff 203 @{
bogdanm 0:9b334a45a8ff 204 */
bogdanm 0:9b334a45a8ff 205 typedef struct
bogdanm 0:9b334a45a8ff 206 {
bogdanm 0:9b334a45a8ff 207 __IO uint32_t PIO2_6; /*!< Offset: 0x000 I/O configuration for pin PIO2_6 (R/W) */
bogdanm 0:9b334a45a8ff 208 uint32_t RESERVED0[1];
bogdanm 0:9b334a45a8ff 209 __IO uint32_t PIO2_0; /*!< Offset: 0x008 I/O configuration for pin PIO2_0/DTR/SSEL1 (R/W) */
bogdanm 0:9b334a45a8ff 210 __IO uint32_t RESET_PIO0_0; /*!< Offset: 0x00C I/O configuration for pin RESET/PIO0_0 (R/W) */
bogdanm 0:9b334a45a8ff 211 __IO uint32_t PIO0_1; /*!< Offset: 0x010 I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2 (R/W) */
bogdanm 0:9b334a45a8ff 212 __IO uint32_t PIO1_8; /*!< Offset: 0x014 I/O configuration for pin PIO1_8/CT16B1_CAP0 (R/W) */
bogdanm 0:9b334a45a8ff 213 __IO uint32_t SSEL1_LOC; /*!< Offset: 0x018 IOCON SSEL1 location register (IOCON_SSEL1_LOC, address 0x4004 4018) */
bogdanm 0:9b334a45a8ff 214 __IO uint32_t PIO0_2; /*!< Offset: 0x01C I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 (R/W) */
bogdanm 0:9b334a45a8ff 215
bogdanm 0:9b334a45a8ff 216 __IO uint32_t PIO2_7; /*!< Offset: 0x020 I/O configuration for pin PIO2_7 (R/W) */
bogdanm 0:9b334a45a8ff 217 __IO uint32_t PIO2_8; /*!< Offset: 0x024 I/O configuration for pin PIO2_8 (R/W) */
bogdanm 0:9b334a45a8ff 218 __IO uint32_t PIO2_1; /*!< Offset: 0x028 I/O configuration for pin PIO2_1/nDSR/SCK1 (R/W) */
bogdanm 0:9b334a45a8ff 219 __IO uint32_t PIO0_3; /*!< Offset: 0x02C I/O configuration for pin PIO0_3 (R/W) */
bogdanm 0:9b334a45a8ff 220 __IO uint32_t PIO0_4; /*!< Offset: 0x030 I/O configuration for pin PIO0_4/SCL (R/W) */
bogdanm 0:9b334a45a8ff 221 __IO uint32_t PIO0_5; /*!< Offset: 0x034 I/O configuration for pin PIO0_5/SDA (R/W) */
bogdanm 0:9b334a45a8ff 222 __IO uint32_t PIO1_9; /*!< Offset: 0x038 I/O configuration for pin PIO1_9/CT16B1_MAT0 (R/W) */
bogdanm 0:9b334a45a8ff 223 __IO uint32_t PIO3_4; /*!< Offset: 0x03C I/O configuration for pin PIO3_4 (R/W) */
bogdanm 0:9b334a45a8ff 224
bogdanm 0:9b334a45a8ff 225 __IO uint32_t PIO2_4; /*!< Offset: 0x040 I/O configuration for pin PIO2_4 (R/W) */
bogdanm 0:9b334a45a8ff 226 __IO uint32_t PIO2_5; /*!< Offset: 0x044 I/O configuration for pin PIO2_5 (R/W) */
bogdanm 0:9b334a45a8ff 227 __IO uint32_t PIO3_5; /*!< Offset: 0x048 I/O configuration for pin PIO3_5 (R/W) */
bogdanm 0:9b334a45a8ff 228 __IO uint32_t PIO0_6; /*!< Offset: 0x04C I/O configuration for pin PIO0_6/SCK0 (R/W) */
bogdanm 0:9b334a45a8ff 229 __IO uint32_t PIO0_7; /*!< Offset: 0x050 I/O configuration for pin PIO0_7/nCTS (R/W) */
bogdanm 0:9b334a45a8ff 230 __IO uint32_t PIO2_9; /*!< Offset: 0x054 I/O configuration for pin PIO2_9 (R/W) */
bogdanm 0:9b334a45a8ff 231 __IO uint32_t PIO2_10; /*!< Offset: 0x058 I/O configuration for pin PIO2_10 (R/W) */
bogdanm 0:9b334a45a8ff 232 __IO uint32_t PIO2_2; /*!< Offset: 0x05C I/O configuration for pin PIO2_2/DCD/MISO1 (R/W) */
bogdanm 0:9b334a45a8ff 233
bogdanm 0:9b334a45a8ff 234 __IO uint32_t PIO0_8; /*!< Offset: 0x060 I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 (R/W) */
bogdanm 0:9b334a45a8ff 235 __IO uint32_t PIO0_9; /*!< Offset: 0x064 I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 (R/W) */
bogdanm 0:9b334a45a8ff 236 __IO uint32_t SWCLK_PIO0_10; /*!< Offset: 0x068 I/O configuration for pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2 (R/W) */
bogdanm 0:9b334a45a8ff 237 __IO uint32_t PIO1_10; /*!< Offset: 0x06C I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1 (R/W) */
bogdanm 0:9b334a45a8ff 238 __IO uint32_t PIO2_11; /*!< Offset: 0x070 I/O configuration for pin PIO2_11/SCK0 (R/W) */
bogdanm 0:9b334a45a8ff 239 __IO uint32_t R_PIO0_11; /*!< Offset: 0x074 I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 (R/W) */
bogdanm 0:9b334a45a8ff 240 __IO uint32_t R_PIO1_0; /*!< Offset: 0x078 I/O configuration for pin TMS/PIO1_0/AD1/CT32B1_CAP0 (R/W) */
bogdanm 0:9b334a45a8ff 241 __IO uint32_t R_PIO1_1; /*!< Offset: 0x07C I/O configuration for pin TDO/PIO1_1/AD2/CT32B1_MAT0 (R/W) */
bogdanm 0:9b334a45a8ff 242
bogdanm 0:9b334a45a8ff 243 __IO uint32_t R_PIO1_2; /*!< Offset: 0x080 I/O configuration for pin nTRST/PIO1_2/AD3/CT32B1_MAT1 (R/W) */
bogdanm 0:9b334a45a8ff 244 __IO uint32_t PIO3_0; /*!< Offset: 0x084 I/O configuration for pin PIO3_0/nDTR (R/W) */
bogdanm 0:9b334a45a8ff 245 __IO uint32_t PIO3_1; /*!< Offset: 0x088 I/O configuration for pin PIO3_1/nDSR (R/W) */
bogdanm 0:9b334a45a8ff 246 __IO uint32_t PIO2_3; /*!< Offset: 0x08C I/O configuration for pin PIO2_3/RI/MOSI1 (R/W) */
bogdanm 0:9b334a45a8ff 247 __IO uint32_t SWDIO_PIO1_3; /*!< Offset: 0x090 I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2 (R/W) */
bogdanm 0:9b334a45a8ff 248 __IO uint32_t PIO1_4; /*!< Offset: 0x094 I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3 (R/W) */
bogdanm 0:9b334a45a8ff 249 __IO uint32_t PIO1_11; /*!< Offset: 0x098 I/O configuration for pin PIO1_11/AD7 (R/W) */
bogdanm 0:9b334a45a8ff 250 __IO uint32_t PIO3_2; /*!< Offset: 0x09C I/O configuration for pin PIO3_2/nDCD (R/W) */
bogdanm 0:9b334a45a8ff 251
bogdanm 0:9b334a45a8ff 252 __IO uint32_t PIO1_5; /*!< Offset: 0x0A0 I/O configuration for pin PIO1_5/nRTS/CT32B0_CAP0 (R/W) */
bogdanm 0:9b334a45a8ff 253 __IO uint32_t PIO1_6; /*!< Offset: 0x0A4 I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0 (R/W) */
bogdanm 0:9b334a45a8ff 254 __IO uint32_t PIO1_7; /*!< Offset: 0x0A8 I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1 (R/W) */
bogdanm 0:9b334a45a8ff 255 __IO uint32_t PIO3_3; /*!< Offset: 0x0AC I/O configuration for pin PIO3_3/nRI (R/W) */
bogdanm 0:9b334a45a8ff 256 __IO uint32_t SCK_LOC; /*!< Offset: 0x0B0 SCK pin location select Register (R/W) */
bogdanm 0:9b334a45a8ff 257 __IO uint32_t DSR_LOC; /*!< Offset: 0x0B4 DSR pin location select Register (R/W) */
bogdanm 0:9b334a45a8ff 258 __IO uint32_t DCD_LOC; /*!< Offset: 0x0B8 DCD pin location select Register (R/W) */
bogdanm 0:9b334a45a8ff 259 __IO uint32_t RI_LOC; /*!< Offset: 0x0BC RI pin location Register (R/W) */
bogdanm 0:9b334a45a8ff 260
bogdanm 0:9b334a45a8ff 261 __IO uint32_t CT16B0_CAP0_LOC; /*!< Offset: 0x0C0 IOCON CT16B0_CAP0 location register (IOCON_CT16B0_CAP0_LOC, address 0x4004 40C0) */
bogdanm 0:9b334a45a8ff 262 __IO uint32_t SCK1_LOC; /*!< Offset: 0x0C4 IOCON SCK1 location register (IOCON_SCK1_LOC, address 0x4004 40C4) */
bogdanm 0:9b334a45a8ff 263 __IO uint32_t MISO1_LOC; /*!< Offset: 0x0C8 IOCON MISO1 location register (IOCON_MISO1_LOC, address 0x4004 40C8) */
bogdanm 0:9b334a45a8ff 264 __IO uint32_t MOSI1_LOC; /*!< Offset: 0x0CC IOCON MOSI1 location register (IOCON_MOSI1_LOC, address 0x4004 40CC) */
bogdanm 0:9b334a45a8ff 265 __IO uint32_t CT32B0_CAP0_LOC; /*!< Offset: 0x0D0 IOCON CT32B0_CAP0 location register (IOCON_CT32B0_CAP0_LOC, address 0x4004 40D0) */
bogdanm 0:9b334a45a8ff 266 __IO uint32_t RXD_LOC; /*!< Offset: 0x0D4 IOCON RXD location register (IOCON_RXD_LOC, address 0x4004 40D4) */
bogdanm 0:9b334a45a8ff 267 } LPC_IOCON_TypeDef;
bogdanm 0:9b334a45a8ff 268 /*@}*/ /* end of group LPC11xx_IOCON */
bogdanm 0:9b334a45a8ff 269
bogdanm 0:9b334a45a8ff 270
bogdanm 0:9b334a45a8ff 271 /*------------- Power Management Unit (PMU) --------------------------*/
bogdanm 0:9b334a45a8ff 272 /** @addtogroup LPC11xx_PMU LPC11xx Power Management Unit
bogdanm 0:9b334a45a8ff 273 @{
bogdanm 0:9b334a45a8ff 274 */
bogdanm 0:9b334a45a8ff 275 typedef struct
bogdanm 0:9b334a45a8ff 276 {
bogdanm 0:9b334a45a8ff 277 __IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */
bogdanm 0:9b334a45a8ff 278 __IO uint32_t GPREG0; /*!< Offset: 0x004 General purpose Register 0 (R/W) */
bogdanm 0:9b334a45a8ff 279 __IO uint32_t GPREG1; /*!< Offset: 0x008 General purpose Register 1 (R/W) */
bogdanm 0:9b334a45a8ff 280 __IO uint32_t GPREG2; /*!< Offset: 0x00C General purpose Register 2 (R/W) */
bogdanm 0:9b334a45a8ff 281 __IO uint32_t GPREG3; /*!< Offset: 0x010 General purpose Register 3 (R/W) */
bogdanm 0:9b334a45a8ff 282 __IO uint32_t GPREG4; /*!< Offset: 0x014 General purpose Register 4 (R/W) */
bogdanm 0:9b334a45a8ff 283 } LPC_PMU_TypeDef;
bogdanm 0:9b334a45a8ff 284 /*@}*/ /* end of group LPC11xx_PMU */
bogdanm 0:9b334a45a8ff 285
bogdanm 0:9b334a45a8ff 286
bogdanm 0:9b334a45a8ff 287
bogdanm 0:9b334a45a8ff 288 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 289 // ----- FLASHCTRL -----
bogdanm 0:9b334a45a8ff 290 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 291
bogdanm 0:9b334a45a8ff 292 typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
bogdanm 0:9b334a45a8ff 293 __I uint32_t RESERVED0[4];
bogdanm 0:9b334a45a8ff 294 __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
bogdanm 0:9b334a45a8ff 295 __I uint32_t RESERVED1[3];
bogdanm 0:9b334a45a8ff 296 __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
bogdanm 0:9b334a45a8ff 297 __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
bogdanm 0:9b334a45a8ff 298 __I uint32_t RESERVED2[1];
bogdanm 0:9b334a45a8ff 299 __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
bogdanm 0:9b334a45a8ff 300 __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
bogdanm 0:9b334a45a8ff 301 __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
bogdanm 0:9b334a45a8ff 302 __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
bogdanm 0:9b334a45a8ff 303 __I uint32_t RESERVED3[1001];
bogdanm 0:9b334a45a8ff 304 __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
bogdanm 0:9b334a45a8ff 305 __I uint32_t RESERVED4[1];
bogdanm 0:9b334a45a8ff 306 __IO uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
bogdanm 0:9b334a45a8ff 307 } LPC_FLASHCTRL_Type;
bogdanm 0:9b334a45a8ff 308
bogdanm 0:9b334a45a8ff 309
bogdanm 0:9b334a45a8ff 310 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
bogdanm 0:9b334a45a8ff 311 /** @addtogroup LPC11xx_GPIO LPC11xx General Purpose Input/Output
bogdanm 0:9b334a45a8ff 312 @{
bogdanm 0:9b334a45a8ff 313 */
bogdanm 0:9b334a45a8ff 314 typedef struct
bogdanm 0:9b334a45a8ff 315 {
bogdanm 0:9b334a45a8ff 316 union {
bogdanm 0:9b334a45a8ff 317 __IO uint32_t MASKED_ACCESS[4096]; /*!< Offset: 0x0000 to 0x3FFC Port data Register for pins PIOn_0 to PIOn_11 (R/W) */
bogdanm 0:9b334a45a8ff 318 struct {
bogdanm 0:9b334a45a8ff 319 uint32_t RESERVED0[4095];
bogdanm 0:9b334a45a8ff 320 __IO uint32_t DATA; /*!< Offset: 0x3FFC Port data Register (R/W) */
bogdanm 0:9b334a45a8ff 321 };
bogdanm 0:9b334a45a8ff 322 };
bogdanm 0:9b334a45a8ff 323 uint32_t RESERVED1[4096];
bogdanm 0:9b334a45a8ff 324 __IO uint32_t DIR; /*!< Offset: 0x8000 Data direction Register (R/W) */
bogdanm 0:9b334a45a8ff 325 __IO uint32_t IS; /*!< Offset: 0x8004 Interrupt sense Register (R/W) */
bogdanm 0:9b334a45a8ff 326 __IO uint32_t IBE; /*!< Offset: 0x8008 Interrupt both edges Register (R/W) */
bogdanm 0:9b334a45a8ff 327 __IO uint32_t IEV; /*!< Offset: 0x800C Interrupt event Register (R/W) */
bogdanm 0:9b334a45a8ff 328 __IO uint32_t IE; /*!< Offset: 0x8010 Interrupt mask Register (R/W) */
bogdanm 0:9b334a45a8ff 329 __I uint32_t RIS; /*!< Offset: 0x8014 Raw interrupt status Register (R/ ) */
bogdanm 0:9b334a45a8ff 330 __I uint32_t MIS; /*!< Offset: 0x8018 Masked interrupt status Register (R/ ) */
bogdanm 0:9b334a45a8ff 331 __O uint32_t IC; /*!< Offset: 0x801C Interrupt clear Register (/W) */
bogdanm 0:9b334a45a8ff 332 } LPC_GPIO_TypeDef;
bogdanm 0:9b334a45a8ff 333 /*@}*/ /* end of group LPC11xx_GPIO */
bogdanm 0:9b334a45a8ff 334
bogdanm 0:9b334a45a8ff 335 /*------------- Timer (TMR) --------------------------------------------------*/
bogdanm 0:9b334a45a8ff 336 /** @addtogroup LPC11xx_TMR LPC11xx 16/32-bit Counter/Timer
bogdanm 0:9b334a45a8ff 337 @{
bogdanm 0:9b334a45a8ff 338 */
bogdanm 0:9b334a45a8ff 339 typedef struct
bogdanm 0:9b334a45a8ff 340 {
bogdanm 0:9b334a45a8ff 341 __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */
bogdanm 0:9b334a45a8ff 342 __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */
bogdanm 0:9b334a45a8ff 343 __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */
bogdanm 0:9b334a45a8ff 344 __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */
bogdanm 0:9b334a45a8ff 345 __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */
bogdanm 0:9b334a45a8ff 346 __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */
bogdanm 0:9b334a45a8ff 347 union {
bogdanm 0:9b334a45a8ff 348 __IO uint32_t MR[4]; /*!< Offset: Match Register base */
bogdanm 0:9b334a45a8ff 349 struct{
bogdanm 0:9b334a45a8ff 350 __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */
bogdanm 0:9b334a45a8ff 351 __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */
bogdanm 0:9b334a45a8ff 352 __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */
bogdanm 0:9b334a45a8ff 353 __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */
bogdanm 0:9b334a45a8ff 354 };
bogdanm 0:9b334a45a8ff 355 };
bogdanm 0:9b334a45a8ff 356 __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */
bogdanm 0:9b334a45a8ff 357 __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */
bogdanm 0:9b334a45a8ff 358 __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */
bogdanm 0:9b334a45a8ff 359 uint32_t RESERVED1[2];
bogdanm 0:9b334a45a8ff 360 __IO uint32_t EMR; /*!< Offset: 0x03C External Match Register (R/W) */
bogdanm 0:9b334a45a8ff 361 uint32_t RESERVED2[12];
bogdanm 0:9b334a45a8ff 362 __IO uint32_t CTCR; /*!< Offset: 0x070 Count Control Register (R/W) */
bogdanm 0:9b334a45a8ff 363 __IO uint32_t PWMC; /*!< Offset: 0x074 PWM Control Register (R/W) */
bogdanm 0:9b334a45a8ff 364 } LPC_TMR_TypeDef;
bogdanm 0:9b334a45a8ff 365 /*@}*/ /* end of group LPC11xx_TMR */
bogdanm 0:9b334a45a8ff 366
bogdanm 0:9b334a45a8ff 367
bogdanm 0:9b334a45a8ff 368 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
bogdanm 0:9b334a45a8ff 369 /** @addtogroup LPC11xx_UART LPC11xx Universal Asynchronous Receiver/Transmitter
bogdanm 0:9b334a45a8ff 370 @{
bogdanm 0:9b334a45a8ff 371 */
bogdanm 0:9b334a45a8ff 372 typedef struct
bogdanm 0:9b334a45a8ff 373 {
bogdanm 0:9b334a45a8ff 374 union {
bogdanm 0:9b334a45a8ff 375 __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */
bogdanm 0:9b334a45a8ff 376 __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */
bogdanm 0:9b334a45a8ff 377 __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */
bogdanm 0:9b334a45a8ff 378 };
bogdanm 0:9b334a45a8ff 379 union {
bogdanm 0:9b334a45a8ff 380 __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
bogdanm 0:9b334a45a8ff 381 __IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */
bogdanm 0:9b334a45a8ff 382 };
bogdanm 0:9b334a45a8ff 383 union {
bogdanm 0:9b334a45a8ff 384 __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */
bogdanm 0:9b334a45a8ff 385 __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */
bogdanm 0:9b334a45a8ff 386 };
bogdanm 0:9b334a45a8ff 387 __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */
bogdanm 0:9b334a45a8ff 388 __IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */
bogdanm 0:9b334a45a8ff 389 __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */
bogdanm 0:9b334a45a8ff 390 __I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */
bogdanm 0:9b334a45a8ff 391 __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */
bogdanm 0:9b334a45a8ff 392 __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
bogdanm 0:9b334a45a8ff 393 uint32_t RESERVED0;
bogdanm 0:9b334a45a8ff 394 __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */
bogdanm 0:9b334a45a8ff 395 uint32_t RESERVED1;
bogdanm 0:9b334a45a8ff 396 __IO uint32_t TER; /*!< Offset: 0x030 Transmit Enable Register (R/W) */
bogdanm 0:9b334a45a8ff 397 uint32_t RESERVED2[6];
bogdanm 0:9b334a45a8ff 398 __IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */
bogdanm 0:9b334a45a8ff 399 __IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */
bogdanm 0:9b334a45a8ff 400 __IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */
bogdanm 0:9b334a45a8ff 401 __I uint32_t FIFOLVL; /*!< Offset: 0x058 FIFO Level Register (R) */
bogdanm 0:9b334a45a8ff 402 } LPC_UART_TypeDef;
bogdanm 0:9b334a45a8ff 403 /*@}*/ /* end of group LPC11xx_UART */
bogdanm 0:9b334a45a8ff 404
bogdanm 0:9b334a45a8ff 405
bogdanm 0:9b334a45a8ff 406 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
bogdanm 0:9b334a45a8ff 407 /** @addtogroup LPC11xx_SSP LPC11xx Synchronous Serial Port
bogdanm 0:9b334a45a8ff 408 @{
bogdanm 0:9b334a45a8ff 409 */
bogdanm 0:9b334a45a8ff 410 typedef struct
bogdanm 0:9b334a45a8ff 411 {
bogdanm 0:9b334a45a8ff 412 __IO uint32_t CR0; /*!< Offset: 0x000 Control Register 0 (R/W) */
bogdanm 0:9b334a45a8ff 413 __IO uint32_t CR1; /*!< Offset: 0x004 Control Register 1 (R/W) */
bogdanm 0:9b334a45a8ff 414 __IO uint32_t DR; /*!< Offset: 0x008 Data Register (R/W) */
bogdanm 0:9b334a45a8ff 415 __I uint32_t SR; /*!< Offset: 0x00C Status Registe (R/ ) */
bogdanm 0:9b334a45a8ff 416 __IO uint32_t CPSR; /*!< Offset: 0x010 Clock Prescale Register (R/W) */
bogdanm 0:9b334a45a8ff 417 __IO uint32_t IMSC; /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */
bogdanm 0:9b334a45a8ff 418 __I uint32_t RIS; /*!< Offset: 0x018 Raw Interrupt Status Register (R/) */
bogdanm 0:9b334a45a8ff 419 __I uint32_t MIS; /*!< Offset: 0x01C Masked Interrupt Status Register (R/) */
bogdanm 0:9b334a45a8ff 420 __O uint32_t ICR; /*!< Offset: 0x020 SSPICR Interrupt Clear Register (/W) */
bogdanm 0:9b334a45a8ff 421 } LPC_SSP_TypeDef;
bogdanm 0:9b334a45a8ff 422 /*@}*/ /* end of group LPC11xx_SSP */
bogdanm 0:9b334a45a8ff 423
bogdanm 0:9b334a45a8ff 424
bogdanm 0:9b334a45a8ff 425 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
bogdanm 0:9b334a45a8ff 426 /** @addtogroup LPC11xx_I2C LPC11xx I2C-Bus Interface
bogdanm 0:9b334a45a8ff 427 @{
bogdanm 0:9b334a45a8ff 428 */
bogdanm 0:9b334a45a8ff 429 typedef struct
bogdanm 0:9b334a45a8ff 430 {
bogdanm 0:9b334a45a8ff 431 __IO uint32_t CONSET; /*!< Offset: 0x000 I2C Control Set Register (R/W) */
bogdanm 0:9b334a45a8ff 432 __I uint32_t STAT; /*!< Offset: 0x004 I2C Status Register (R/ ) */
bogdanm 0:9b334a45a8ff 433 __IO uint32_t DAT; /*!< Offset: 0x008 I2C Data Register (R/W) */
bogdanm 0:9b334a45a8ff 434 __IO uint32_t ADR0; /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */
bogdanm 0:9b334a45a8ff 435 __IO uint32_t SCLH; /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */
bogdanm 0:9b334a45a8ff 436 __IO uint32_t SCLL; /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */
bogdanm 0:9b334a45a8ff 437 __O uint32_t CONCLR; /*!< Offset: 0x018 I2C Control Clear Register ( /W) */
bogdanm 0:9b334a45a8ff 438 __IO uint32_t MMCTRL; /*!< Offset: 0x01C Monitor mode control register (R/W) */
bogdanm 0:9b334a45a8ff 439 __IO uint32_t ADR1; /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */
bogdanm 0:9b334a45a8ff 440 __IO uint32_t ADR2; /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */
bogdanm 0:9b334a45a8ff 441 __IO uint32_t ADR3; /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */
bogdanm 0:9b334a45a8ff 442 __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C Data buffer register ( /W) */
bogdanm 0:9b334a45a8ff 443 __IO uint32_t MASK0; /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */
bogdanm 0:9b334a45a8ff 444 __IO uint32_t MASK1; /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */
bogdanm 0:9b334a45a8ff 445 __IO uint32_t MASK2; /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */
bogdanm 0:9b334a45a8ff 446 __IO uint32_t MASK3; /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */
bogdanm 0:9b334a45a8ff 447 } LPC_I2C_TypeDef;
bogdanm 0:9b334a45a8ff 448 /*@}*/ /* end of group LPC11xx_I2C */
bogdanm 0:9b334a45a8ff 449
bogdanm 0:9b334a45a8ff 450
bogdanm 0:9b334a45a8ff 451 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
bogdanm 0:9b334a45a8ff 452 /** @addtogroup LPC11xx_WDT LPC11xx WatchDog Timer
bogdanm 0:9b334a45a8ff 453 @{
bogdanm 0:9b334a45a8ff 454 */
bogdanm 0:9b334a45a8ff 455 typedef struct
bogdanm 0:9b334a45a8ff 456 {
bogdanm 0:9b334a45a8ff 457 __IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */
bogdanm 0:9b334a45a8ff 458 __IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */
bogdanm 0:9b334a45a8ff 459 __O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register (W) */
bogdanm 0:9b334a45a8ff 460 __I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R) */
bogdanm 0:9b334a45a8ff 461 uint32_t RESERVED0;
bogdanm 0:9b334a45a8ff 462 __IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */
bogdanm 0:9b334a45a8ff 463 __IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */
bogdanm 0:9b334a45a8ff 464 } LPC_WDT_TypeDef;
bogdanm 0:9b334a45a8ff 465 /*@}*/ /* end of group LPC11xx_WDT */
bogdanm 0:9b334a45a8ff 466
bogdanm 0:9b334a45a8ff 467
bogdanm 0:9b334a45a8ff 468 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
bogdanm 0:9b334a45a8ff 469 /** @addtogroup LPC11xx_ADC LPC11xx Analog-to-Digital Converter
bogdanm 0:9b334a45a8ff 470 @{
bogdanm 0:9b334a45a8ff 471 */
bogdanm 0:9b334a45a8ff 472 typedef struct
bogdanm 0:9b334a45a8ff 473 {
bogdanm 0:9b334a45a8ff 474 __IO uint32_t CR; /*!< Offset: 0x000 A/D Control Register (R/W) */
bogdanm 0:9b334a45a8ff 475 __IO uint32_t GDR; /*!< Offset: 0x004 A/D Global Data Register (R/W) */
bogdanm 0:9b334a45a8ff 476 uint32_t RESERVED0;
bogdanm 0:9b334a45a8ff 477 __IO uint32_t INTEN; /*!< Offset: 0x00C A/D Interrupt Enable Register (R/W) */
bogdanm 0:9b334a45a8ff 478 __IO uint32_t DR[8]; /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */
bogdanm 0:9b334a45a8ff 479 __I uint32_t STAT; /*!< Offset: 0x030 A/D Status Register (R/ ) */
bogdanm 0:9b334a45a8ff 480 } LPC_ADC_TypeDef;
bogdanm 0:9b334a45a8ff 481 /*@}*/ /* end of group LPC11xx_ADC */
bogdanm 0:9b334a45a8ff 482
bogdanm 0:9b334a45a8ff 483
bogdanm 0:9b334a45a8ff 484 /*------------- CAN Controller (CAN) ----------------------------*/
bogdanm 0:9b334a45a8ff 485 /** @addtogroup LPC11xx_CAN LPC11xx Controller Area Network(CAN)
bogdanm 0:9b334a45a8ff 486 @{
bogdanm 0:9b334a45a8ff 487 */
bogdanm 0:9b334a45a8ff 488 typedef struct
bogdanm 0:9b334a45a8ff 489 {
bogdanm 0:9b334a45a8ff 490 __IO uint32_t CNTL; /* 0x000 */
bogdanm 0:9b334a45a8ff 491 __IO uint32_t STAT;
bogdanm 0:9b334a45a8ff 492 __IO uint32_t EC;
bogdanm 0:9b334a45a8ff 493 __IO uint32_t BT;
bogdanm 0:9b334a45a8ff 494 __IO uint32_t INT;
bogdanm 0:9b334a45a8ff 495 __IO uint32_t TEST;
bogdanm 0:9b334a45a8ff 496 __IO uint32_t BRPE;
bogdanm 0:9b334a45a8ff 497 uint32_t RESERVED0;
bogdanm 0:9b334a45a8ff 498 __IO uint32_t IF1_CMDREQ; /* 0x020 */
bogdanm 0:9b334a45a8ff 499 __IO uint32_t IF1_CMDMSK;
bogdanm 0:9b334a45a8ff 500 __IO uint32_t IF1_MSK1;
bogdanm 0:9b334a45a8ff 501 __IO uint32_t IF1_MSK2;
bogdanm 0:9b334a45a8ff 502 __IO uint32_t IF1_ARB1;
bogdanm 0:9b334a45a8ff 503 __IO uint32_t IF1_ARB2;
bogdanm 0:9b334a45a8ff 504 __IO uint32_t IF1_MCTRL;
bogdanm 0:9b334a45a8ff 505 __IO uint32_t IF1_DA1;
bogdanm 0:9b334a45a8ff 506 __IO uint32_t IF1_DA2;
bogdanm 0:9b334a45a8ff 507 __IO uint32_t IF1_DB1;
bogdanm 0:9b334a45a8ff 508 __IO uint32_t IF1_DB2;
bogdanm 0:9b334a45a8ff 509 uint32_t RESERVED1[13];
bogdanm 0:9b334a45a8ff 510 __IO uint32_t IF2_CMDREQ; /* 0x080 */
bogdanm 0:9b334a45a8ff 511 __IO uint32_t IF2_CMDMSK;
bogdanm 0:9b334a45a8ff 512 __IO uint32_t IF2_MSK1;
bogdanm 0:9b334a45a8ff 513 __IO uint32_t IF2_MSK2;
bogdanm 0:9b334a45a8ff 514 __IO uint32_t IF2_ARB1;
bogdanm 0:9b334a45a8ff 515 __IO uint32_t IF2_ARB2;
bogdanm 0:9b334a45a8ff 516 __IO uint32_t IF2_MCTRL;
bogdanm 0:9b334a45a8ff 517 __IO uint32_t IF2_DA1;
bogdanm 0:9b334a45a8ff 518 __IO uint32_t IF2_DA2;
bogdanm 0:9b334a45a8ff 519 __IO uint32_t IF2_DB1;
bogdanm 0:9b334a45a8ff 520 __IO uint32_t IF2_DB2;
bogdanm 0:9b334a45a8ff 521 uint32_t RESERVED2[21];
bogdanm 0:9b334a45a8ff 522 __I uint32_t TXREQ1; /* 0x100 */
bogdanm 0:9b334a45a8ff 523 __I uint32_t TXREQ2;
bogdanm 0:9b334a45a8ff 524 uint32_t RESERVED3[6];
bogdanm 0:9b334a45a8ff 525 __I uint32_t ND1; /* 0x120 */
bogdanm 0:9b334a45a8ff 526 __I uint32_t ND2;
bogdanm 0:9b334a45a8ff 527 uint32_t RESERVED4[6];
bogdanm 0:9b334a45a8ff 528 __I uint32_t IR1; /* 0x140 */
bogdanm 0:9b334a45a8ff 529 __I uint32_t IR2;
bogdanm 0:9b334a45a8ff 530 uint32_t RESERVED5[6];
bogdanm 0:9b334a45a8ff 531 __I uint32_t MSGV1; /* 0x160 */
bogdanm 0:9b334a45a8ff 532 __I uint32_t MSGV2;
bogdanm 0:9b334a45a8ff 533 uint32_t RESERVED6[6];
bogdanm 0:9b334a45a8ff 534 __IO uint32_t CLKDIV; /* 0x180 */
bogdanm 0:9b334a45a8ff 535 } LPC_CAN_TypeDef;
bogdanm 0:9b334a45a8ff 536 /*@}*/ /* end of group LPC11xx_CAN */
bogdanm 0:9b334a45a8ff 537
bogdanm 0:9b334a45a8ff 538 #if defined ( __CC_ARM )
bogdanm 0:9b334a45a8ff 539 #pragma no_anon_unions
bogdanm 0:9b334a45a8ff 540 #endif
bogdanm 0:9b334a45a8ff 541
bogdanm 0:9b334a45a8ff 542 /******************************************************************************/
bogdanm 0:9b334a45a8ff 543 /* Peripheral memory map */
bogdanm 0:9b334a45a8ff 544 /******************************************************************************/
bogdanm 0:9b334a45a8ff 545 /* Base addresses */
bogdanm 0:9b334a45a8ff 546 #define LPC_FLASH_BASE (0x00000000UL)
bogdanm 0:9b334a45a8ff 547 #define LPC_RAM_BASE (0x10000000UL)
bogdanm 0:9b334a45a8ff 548 #define LPC_APB0_BASE (0x40000000UL)
bogdanm 0:9b334a45a8ff 549 #define LPC_AHB_BASE (0x50000000UL)
bogdanm 0:9b334a45a8ff 550
bogdanm 0:9b334a45a8ff 551 /* APB0 peripherals */
bogdanm 0:9b334a45a8ff 552 #define LPC_I2C_BASE (LPC_APB0_BASE + 0x00000)
bogdanm 0:9b334a45a8ff 553 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x04000)
bogdanm 0:9b334a45a8ff 554 #define LPC_UART_BASE (LPC_APB0_BASE + 0x08000)
bogdanm 0:9b334a45a8ff 555 #define LPC_CT16B0_BASE (LPC_APB0_BASE + 0x0C000)
bogdanm 0:9b334a45a8ff 556 #define LPC_CT16B1_BASE (LPC_APB0_BASE + 0x10000)
bogdanm 0:9b334a45a8ff 557 #define LPC_CT32B0_BASE (LPC_APB0_BASE + 0x14000)
bogdanm 0:9b334a45a8ff 558 #define LPC_CT32B1_BASE (LPC_APB0_BASE + 0x18000)
bogdanm 0:9b334a45a8ff 559 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000)
bogdanm 0:9b334a45a8ff 560 #define LPC_PMU_BASE (LPC_APB0_BASE + 0x38000)
bogdanm 0:9b334a45a8ff 561 #define LPC_FLASHCTRL_BASE (LPC_APB0_BASE + 0x3C000)
bogdanm 0:9b334a45a8ff 562 #define LPC_SSP0_BASE (LPC_APB0_BASE + 0x40000)
bogdanm 0:9b334a45a8ff 563 #define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000)
bogdanm 0:9b334a45a8ff 564 #define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000)
bogdanm 0:9b334a45a8ff 565 #define LPC_CAN_BASE (LPC_APB0_BASE + 0x50000)
bogdanm 0:9b334a45a8ff 566 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x58000)
bogdanm 0:9b334a45a8ff 567
bogdanm 0:9b334a45a8ff 568 /* AHB peripherals */
bogdanm 0:9b334a45a8ff 569 #define LPC_GPIO_BASE (LPC_AHB_BASE + 0x00000)
bogdanm 0:9b334a45a8ff 570 #define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x00000)
bogdanm 0:9b334a45a8ff 571 #define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x10000)
bogdanm 0:9b334a45a8ff 572 #define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x20000)
bogdanm 0:9b334a45a8ff 573 #define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x30000)
bogdanm 0:9b334a45a8ff 574
bogdanm 0:9b334a45a8ff 575 /******************************************************************************/
bogdanm 0:9b334a45a8ff 576 /* Peripheral declaration */
bogdanm 0:9b334a45a8ff 577 /******************************************************************************/
bogdanm 0:9b334a45a8ff 578 #define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE )
bogdanm 0:9b334a45a8ff 579 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
bogdanm 0:9b334a45a8ff 580 #define LPC_UART ((LPC_UART_TypeDef *) LPC_UART_BASE )
bogdanm 0:9b334a45a8ff 581 #define LPC_TMR16B0 ((LPC_TMR_TypeDef *) LPC_CT16B0_BASE)
bogdanm 0:9b334a45a8ff 582 #define LPC_TMR16B1 ((LPC_TMR_TypeDef *) LPC_CT16B1_BASE)
bogdanm 0:9b334a45a8ff 583 #define LPC_TMR32B0 ((LPC_TMR_TypeDef *) LPC_CT32B0_BASE)
bogdanm 0:9b334a45a8ff 584 #define LPC_TMR32B1 ((LPC_TMR_TypeDef *) LPC_CT32B1_BASE)
bogdanm 0:9b334a45a8ff 585 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
bogdanm 0:9b334a45a8ff 586 #define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE )
bogdanm 0:9b334a45a8ff 587 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
bogdanm 0:9b334a45a8ff 588 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
bogdanm 0:9b334a45a8ff 589 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
bogdanm 0:9b334a45a8ff 590 #define LPC_CAN ((LPC_CAN_TypeDef *) LPC_CAN_BASE )
bogdanm 0:9b334a45a8ff 591 #define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
bogdanm 0:9b334a45a8ff 592 #define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
bogdanm 0:9b334a45a8ff 593 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
bogdanm 0:9b334a45a8ff 594 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
bogdanm 0:9b334a45a8ff 595 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
bogdanm 0:9b334a45a8ff 596 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
bogdanm 0:9b334a45a8ff 597
bogdanm 0:9b334a45a8ff 598 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 599 }
bogdanm 0:9b334a45a8ff 600 #endif
bogdanm 0:9b334a45a8ff 601
bogdanm 0:9b334a45a8ff 602 #endif /* __LPC11xx_H__ */