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targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/system_stm32l0xx.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file system_stm32l0xx.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.2.0
bogdanm 0:9b334a45a8ff 6 * @date 06-February-2015
bogdanm 0:9b334a45a8ff 7 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 * This file provides two functions and one global variable to be called from
bogdanm 0:9b334a45a8ff 10 * user application:
bogdanm 0:9b334a45a8ff 11 * - SystemInit(): This function is called at startup just after reset and
bogdanm 0:9b334a45a8ff 12 * before branch to main program. This call is made inside
bogdanm 0:9b334a45a8ff 13 * the "startup_stm32l0xx.s" file.
bogdanm 0:9b334a45a8ff 14 *
bogdanm 0:9b334a45a8ff 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
bogdanm 0:9b334a45a8ff 16 * by the user application to setup the SysTick
bogdanm 0:9b334a45a8ff 17 * timer or configure other parameters.
bogdanm 0:9b334a45a8ff 18 *
bogdanm 0:9b334a45a8ff 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
bogdanm 0:9b334a45a8ff 20 * be called whenever the core clock is changed
bogdanm 0:9b334a45a8ff 21 * during program execution.
bogdanm 0:9b334a45a8ff 22 *
bogdanm 0:9b334a45a8ff 23 * This file configures the system clock as follows:
bogdanm 0:9b334a45a8ff 24 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 25 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
bogdanm 0:9b334a45a8ff 26 * | (external 8 MHz clock) | (internal 16 MHz)
bogdanm 0:9b334a45a8ff 27 * | 2- PLL_HSE_XTAL |
bogdanm 0:9b334a45a8ff 28 * | (external 8 MHz xtal) |
bogdanm 0:9b334a45a8ff 29 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 30 * SYSCLK(MHz) | 32 | 32
bogdanm 0:9b334a45a8ff 31 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 32 * AHBCLK (MHz) | 32 | 32
bogdanm 0:9b334a45a8ff 33 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 34 * APB1CLK (MHz) | 32 | 32
bogdanm 0:9b334a45a8ff 35 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 36 * APB2CLK (MHz) | 32 | 32
bogdanm 0:9b334a45a8ff 37 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 38 * USB capable (48 MHz precise clock) | YES | YES
bogdanm 0:9b334a45a8ff 39 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 40 ******************************************************************************
bogdanm 0:9b334a45a8ff 41 * @attention
bogdanm 0:9b334a45a8ff 42 *
bogdanm 0:9b334a45a8ff 43 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 44 *
bogdanm 0:9b334a45a8ff 45 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 46 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 47 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 48 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 49 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 50 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 51 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 52 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 53 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 54 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 55 *
bogdanm 0:9b334a45a8ff 56 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 57 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 58 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 59 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 60 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 61 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 62 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 63 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 64 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 65 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 66 *
bogdanm 0:9b334a45a8ff 67 ******************************************************************************
bogdanm 0:9b334a45a8ff 68 */
bogdanm 0:9b334a45a8ff 69
bogdanm 0:9b334a45a8ff 70 /** @addtogroup CMSIS
bogdanm 0:9b334a45a8ff 71 * @{
bogdanm 0:9b334a45a8ff 72 */
bogdanm 0:9b334a45a8ff 73
bogdanm 0:9b334a45a8ff 74 /** @addtogroup stm32l0xx_system
bogdanm 0:9b334a45a8ff 75 * @{
bogdanm 0:9b334a45a8ff 76 */
bogdanm 0:9b334a45a8ff 77
bogdanm 0:9b334a45a8ff 78 /** @addtogroup STM32L0xx_System_Private_Includes
bogdanm 0:9b334a45a8ff 79 * @{
bogdanm 0:9b334a45a8ff 80 */
bogdanm 0:9b334a45a8ff 81
bogdanm 0:9b334a45a8ff 82 #include "stm32l0xx.h"
bogdanm 0:9b334a45a8ff 83 #include "hal_tick.h"
bogdanm 0:9b334a45a8ff 84
bogdanm 0:9b334a45a8ff 85 #if !defined (HSE_VALUE)
bogdanm 0:9b334a45a8ff 86 #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
bogdanm 0:9b334a45a8ff 87 #endif /* HSE_VALUE */
bogdanm 0:9b334a45a8ff 88
bogdanm 0:9b334a45a8ff 89 #if !defined (MSI_VALUE)
bogdanm 0:9b334a45a8ff 90 #define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/
bogdanm 0:9b334a45a8ff 91 #endif /* MSI_VALUE */
bogdanm 0:9b334a45a8ff 92
bogdanm 0:9b334a45a8ff 93 #if !defined (HSI_VALUE)
bogdanm 0:9b334a45a8ff 94 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
bogdanm 0:9b334a45a8ff 95 #endif /* HSI_VALUE */
bogdanm 0:9b334a45a8ff 96
bogdanm 0:9b334a45a8ff 97
bogdanm 0:9b334a45a8ff 98 /**
bogdanm 0:9b334a45a8ff 99 * @}
bogdanm 0:9b334a45a8ff 100 */
bogdanm 0:9b334a45a8ff 101
bogdanm 0:9b334a45a8ff 102 /** @addtogroup STM32L0xx_System_Private_TypesDefinitions
bogdanm 0:9b334a45a8ff 103 * @{
bogdanm 0:9b334a45a8ff 104 */
bogdanm 0:9b334a45a8ff 105
bogdanm 0:9b334a45a8ff 106 /**
bogdanm 0:9b334a45a8ff 107 * @}
bogdanm 0:9b334a45a8ff 108 */
bogdanm 0:9b334a45a8ff 109
bogdanm 0:9b334a45a8ff 110 /** @addtogroup STM32L0xx_System_Private_Defines
bogdanm 0:9b334a45a8ff 111 * @{
bogdanm 0:9b334a45a8ff 112 */
bogdanm 0:9b334a45a8ff 113 /************************* Miscellaneous Configuration ************************/
bogdanm 0:9b334a45a8ff 114
bogdanm 0:9b334a45a8ff 115 /*!< Uncomment the following line if you need to relocate your vector Table in
bogdanm 0:9b334a45a8ff 116 Internal SRAM. */
bogdanm 0:9b334a45a8ff 117 /* #define VECT_TAB_SRAM */
bogdanm 0:9b334a45a8ff 118 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
bogdanm 0:9b334a45a8ff 119 This value must be a multiple of 0x200. */
bogdanm 0:9b334a45a8ff 120 /******************************************************************************/
bogdanm 0:9b334a45a8ff 121 /**
bogdanm 0:9b334a45a8ff 122 * @}
bogdanm 0:9b334a45a8ff 123 */
bogdanm 0:9b334a45a8ff 124
bogdanm 0:9b334a45a8ff 125 /** @addtogroup STM32L0xx_System_Private_Macros
bogdanm 0:9b334a45a8ff 126 * @{
bogdanm 0:9b334a45a8ff 127 */
bogdanm 0:9b334a45a8ff 128
bogdanm 0:9b334a45a8ff 129 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
bogdanm 0:9b334a45a8ff 130 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
bogdanm 0:9b334a45a8ff 131 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
bogdanm 0:9b334a45a8ff 132
bogdanm 0:9b334a45a8ff 133 /**
bogdanm 0:9b334a45a8ff 134 * @}
bogdanm 0:9b334a45a8ff 135 */
bogdanm 0:9b334a45a8ff 136
bogdanm 0:9b334a45a8ff 137 /** @addtogroup STM32L0xx_System_Private_Variables
bogdanm 0:9b334a45a8ff 138 * @{
bogdanm 0:9b334a45a8ff 139 */
bogdanm 0:9b334a45a8ff 140 /* This variable is updated in three ways:
bogdanm 0:9b334a45a8ff 141 1) by calling CMSIS function SystemCoreClockUpdate()
bogdanm 0:9b334a45a8ff 142 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
bogdanm 0:9b334a45a8ff 143 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
bogdanm 0:9b334a45a8ff 144 Note: If you use this function to configure the system clock; then there
bogdanm 0:9b334a45a8ff 145 is no need to call the 2 first functions listed above, since SystemCoreClock
bogdanm 0:9b334a45a8ff 146 variable is updated automatically.
bogdanm 0:9b334a45a8ff 147 */
bogdanm 0:9b334a45a8ff 148 uint32_t SystemCoreClock = 32000000;
bogdanm 0:9b334a45a8ff 149 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
bogdanm 0:9b334a45a8ff 150 const uint8_t PLLMulTable_2[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
bogdanm 0:9b334a45a8ff 151
bogdanm 0:9b334a45a8ff 152 /**
bogdanm 0:9b334a45a8ff 153 * @}
bogdanm 0:9b334a45a8ff 154 */
bogdanm 0:9b334a45a8ff 155
bogdanm 0:9b334a45a8ff 156 /** @addtogroup STM32L0xx_System_Private_FunctionPrototypes
bogdanm 0:9b334a45a8ff 157 * @{
bogdanm 0:9b334a45a8ff 158 */
bogdanm 0:9b334a45a8ff 159
bogdanm 0:9b334a45a8ff 160 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
bogdanm 0:9b334a45a8ff 161 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
bogdanm 0:9b334a45a8ff 162 #endif
bogdanm 0:9b334a45a8ff 163
bogdanm 0:9b334a45a8ff 164 uint8_t SetSysClock_PLL_HSI(void);
bogdanm 0:9b334a45a8ff 165
bogdanm 0:9b334a45a8ff 166 /**
bogdanm 0:9b334a45a8ff 167 * @}
bogdanm 0:9b334a45a8ff 168 */
bogdanm 0:9b334a45a8ff 169
bogdanm 0:9b334a45a8ff 170 /** @addtogroup STM32L0xx_System_Private_Functions
bogdanm 0:9b334a45a8ff 171 * @{
bogdanm 0:9b334a45a8ff 172 */
bogdanm 0:9b334a45a8ff 173
bogdanm 0:9b334a45a8ff 174 /**
bogdanm 0:9b334a45a8ff 175 * @brief Setup the microcontroller system.
bogdanm 0:9b334a45a8ff 176 * @param None
bogdanm 0:9b334a45a8ff 177 * @retval None
bogdanm 0:9b334a45a8ff 178 */
bogdanm 0:9b334a45a8ff 179 void SystemInit (void)
bogdanm 0:9b334a45a8ff 180 {
bogdanm 0:9b334a45a8ff 181 /*!< Set MSION bit */
bogdanm 0:9b334a45a8ff 182 RCC->CR |= (uint32_t)0x00000100;
bogdanm 0:9b334a45a8ff 183
bogdanm 0:9b334a45a8ff 184 /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
bogdanm 0:9b334a45a8ff 185 RCC->CFGR &= (uint32_t) 0x88FF400C;
bogdanm 0:9b334a45a8ff 186
bogdanm 0:9b334a45a8ff 187 /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
bogdanm 0:9b334a45a8ff 188 RCC->CR &= (uint32_t)0xFEF6FFF6;
bogdanm 0:9b334a45a8ff 189
bogdanm 0:9b334a45a8ff 190 /*!< Reset HSI48ON bit */
bogdanm 0:9b334a45a8ff 191 RCC->CRRCR &= (uint32_t)0xFFFFFFFE;
bogdanm 0:9b334a45a8ff 192
bogdanm 0:9b334a45a8ff 193 /*!< Reset HSEBYP bit */
bogdanm 0:9b334a45a8ff 194 RCC->CR &= (uint32_t)0xFFFBFFFF;
bogdanm 0:9b334a45a8ff 195
bogdanm 0:9b334a45a8ff 196 /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
bogdanm 0:9b334a45a8ff 197 RCC->CFGR &= (uint32_t)0xFF02FFFF;
bogdanm 0:9b334a45a8ff 198
bogdanm 0:9b334a45a8ff 199 /*!< Disable all interrupts */
bogdanm 0:9b334a45a8ff 200 RCC->CIER = 0x00000000;
bogdanm 0:9b334a45a8ff 201
bogdanm 0:9b334a45a8ff 202 /* Configure the Vector Table location add offset address ------------------*/
bogdanm 0:9b334a45a8ff 203 #ifdef VECT_TAB_SRAM
bogdanm 0:9b334a45a8ff 204 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
bogdanm 0:9b334a45a8ff 205 #else
bogdanm 0:9b334a45a8ff 206 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
bogdanm 0:9b334a45a8ff 207 #endif
bogdanm 0:9b334a45a8ff 208
bogdanm 0:9b334a45a8ff 209 /* Configure the Cube driver */
bogdanm 0:9b334a45a8ff 210 SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
bogdanm 0:9b334a45a8ff 211 HAL_Init();
bogdanm 0:9b334a45a8ff 212
bogdanm 0:9b334a45a8ff 213 /* Configure the System clock source, PLL Multiplier and Divider factors,
bogdanm 0:9b334a45a8ff 214 AHB/APBx prescalers and Flash settings */
bogdanm 0:9b334a45a8ff 215 SetSysClock();
bogdanm 0:9b334a45a8ff 216
bogdanm 0:9b334a45a8ff 217 /* Reset the timer to avoid issues after the RAM initialization */
bogdanm 0:9b334a45a8ff 218 TIM_MST_RESET_ON;
bogdanm 0:9b334a45a8ff 219 TIM_MST_RESET_OFF;
bogdanm 0:9b334a45a8ff 220 }
bogdanm 0:9b334a45a8ff 221
bogdanm 0:9b334a45a8ff 222 /**
bogdanm 0:9b334a45a8ff 223 * @brief Update SystemCoreClock according to Clock Register Values
bogdanm 0:9b334a45a8ff 224 * The SystemCoreClock variable contains the core clock (HCLK), it can
bogdanm 0:9b334a45a8ff 225 * be used by the user application to setup the SysTick timer or configure
bogdanm 0:9b334a45a8ff 226 * other parameters.
bogdanm 0:9b334a45a8ff 227 *
bogdanm 0:9b334a45a8ff 228 * @note Each time the core clock (HCLK) changes, this function must be called
bogdanm 0:9b334a45a8ff 229 * to update SystemCoreClock variable value. Otherwise, any configuration
bogdanm 0:9b334a45a8ff 230 * based on this variable will be incorrect.
bogdanm 0:9b334a45a8ff 231 *
bogdanm 0:9b334a45a8ff 232 * @note - The system frequency computed by this function is not the real
bogdanm 0:9b334a45a8ff 233 * frequency in the chip. It is calculated based on the predefined
bogdanm 0:9b334a45a8ff 234 * constant and the selected clock source:
bogdanm 0:9b334a45a8ff 235 *
bogdanm 0:9b334a45a8ff 236 * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
bogdanm 0:9b334a45a8ff 237 * value as defined by the MSI range.
bogdanm 0:9b334a45a8ff 238 *
bogdanm 0:9b334a45a8ff 239 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
bogdanm 0:9b334a45a8ff 240 *
bogdanm 0:9b334a45a8ff 241 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
bogdanm 0:9b334a45a8ff 242 *
bogdanm 0:9b334a45a8ff 243 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
bogdanm 0:9b334a45a8ff 244 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
bogdanm 0:9b334a45a8ff 245 *
bogdanm 0:9b334a45a8ff 246 * (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value
bogdanm 0:9b334a45a8ff 247 * 16 MHz) but the real value may vary depending on the variations
bogdanm 0:9b334a45a8ff 248 * in voltage and temperature.
bogdanm 0:9b334a45a8ff 249 *
bogdanm 0:9b334a45a8ff 250 * (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value
bogdanm 0:9b334a45a8ff 251 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
bogdanm 0:9b334a45a8ff 252 * frequency of the crystal used. Otherwise, this function may
bogdanm 0:9b334a45a8ff 253 * have wrong result.
bogdanm 0:9b334a45a8ff 254 *
bogdanm 0:9b334a45a8ff 255 * - The result of this function could be not correct when using fractional
bogdanm 0:9b334a45a8ff 256 * value for HSE crystal.
bogdanm 0:9b334a45a8ff 257 * @param None
bogdanm 0:9b334a45a8ff 258 * @retval None
bogdanm 0:9b334a45a8ff 259 */
bogdanm 0:9b334a45a8ff 260 void SystemCoreClockUpdate (void)
bogdanm 0:9b334a45a8ff 261 {
bogdanm 0:9b334a45a8ff 262 uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
bogdanm 0:9b334a45a8ff 263
bogdanm 0:9b334a45a8ff 264 /* Get SYSCLK source -------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 265 tmp = RCC->CFGR & RCC_CFGR_SWS;
bogdanm 0:9b334a45a8ff 266
bogdanm 0:9b334a45a8ff 267 switch (tmp)
bogdanm 0:9b334a45a8ff 268 {
bogdanm 0:9b334a45a8ff 269 case 0x00: /* MSI used as system clock */
bogdanm 0:9b334a45a8ff 270 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
bogdanm 0:9b334a45a8ff 271 SystemCoreClock = (32768 * (1 << (msirange + 1)));
bogdanm 0:9b334a45a8ff 272 break;
bogdanm 0:9b334a45a8ff 273 case 0x04: /* HSI used as system clock */
bogdanm 0:9b334a45a8ff 274 SystemCoreClock = HSI_VALUE;
bogdanm 0:9b334a45a8ff 275 break;
bogdanm 0:9b334a45a8ff 276 case 0x08: /* HSE used as system clock */
bogdanm 0:9b334a45a8ff 277 SystemCoreClock = HSE_VALUE;
bogdanm 0:9b334a45a8ff 278 break;
bogdanm 0:9b334a45a8ff 279 case 0x0C: /* PLL used as system clock */
bogdanm 0:9b334a45a8ff 280 /* Get PLL clock source and multiplication factor ----------------------*/
bogdanm 0:9b334a45a8ff 281 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
bogdanm 0:9b334a45a8ff 282 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
bogdanm 0:9b334a45a8ff 283 pllmul = PLLMulTable_2[(pllmul >> 18)];
bogdanm 0:9b334a45a8ff 284 plldiv = (plldiv >> 22) + 1;
bogdanm 0:9b334a45a8ff 285
bogdanm 0:9b334a45a8ff 286 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
bogdanm 0:9b334a45a8ff 287
bogdanm 0:9b334a45a8ff 288 if (pllsource == 0x00)
bogdanm 0:9b334a45a8ff 289 {
bogdanm 0:9b334a45a8ff 290 /* HSI oscillator clock selected as PLL clock entry */
bogdanm 0:9b334a45a8ff 291 SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
bogdanm 0:9b334a45a8ff 292 }
bogdanm 0:9b334a45a8ff 293 else
bogdanm 0:9b334a45a8ff 294 {
bogdanm 0:9b334a45a8ff 295 /* HSE selected as PLL clock entry */
bogdanm 0:9b334a45a8ff 296 SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
bogdanm 0:9b334a45a8ff 297 }
bogdanm 0:9b334a45a8ff 298 break;
bogdanm 0:9b334a45a8ff 299 default: /* MSI used as system clock */
bogdanm 0:9b334a45a8ff 300 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
bogdanm 0:9b334a45a8ff 301 SystemCoreClock = (32768 * (1 << (msirange + 1)));
bogdanm 0:9b334a45a8ff 302 break;
bogdanm 0:9b334a45a8ff 303 }
bogdanm 0:9b334a45a8ff 304 /* Compute HCLK clock frequency --------------------------------------------*/
bogdanm 0:9b334a45a8ff 305 /* Get HCLK prescaler */
bogdanm 0:9b334a45a8ff 306 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
bogdanm 0:9b334a45a8ff 307 /* HCLK clock frequency */
bogdanm 0:9b334a45a8ff 308 SystemCoreClock >>= tmp;
bogdanm 0:9b334a45a8ff 309 }
bogdanm 0:9b334a45a8ff 310
bogdanm 0:9b334a45a8ff 311 /**
bogdanm 0:9b334a45a8ff 312 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
bogdanm 0:9b334a45a8ff 313 * AHB/APBx prescalers and Flash settings
bogdanm 0:9b334a45a8ff 314 * @note This function should be called only once the RCC clock configuration
bogdanm 0:9b334a45a8ff 315 * is reset to the default reset state (done in SystemInit() function).
bogdanm 0:9b334a45a8ff 316 * @param None
bogdanm 0:9b334a45a8ff 317 * @retval None
bogdanm 0:9b334a45a8ff 318 */
bogdanm 0:9b334a45a8ff 319 void SetSysClock(void)
bogdanm 0:9b334a45a8ff 320 {
bogdanm 0:9b334a45a8ff 321 /* 1- Try to start with HSE and external clock */
bogdanm 0:9b334a45a8ff 322 #if USE_PLL_HSE_EXTC != 0
bogdanm 0:9b334a45a8ff 323 if (SetSysClock_PLL_HSE(1) == 0)
bogdanm 0:9b334a45a8ff 324 #endif
bogdanm 0:9b334a45a8ff 325 {
bogdanm 0:9b334a45a8ff 326 /* 2- If fail try to start with HSE and external xtal */
bogdanm 0:9b334a45a8ff 327 #if USE_PLL_HSE_XTAL != 0
bogdanm 0:9b334a45a8ff 328 if (SetSysClock_PLL_HSE(0) == 0)
bogdanm 0:9b334a45a8ff 329 #endif
bogdanm 0:9b334a45a8ff 330 {
bogdanm 0:9b334a45a8ff 331 /* 3- If fail start with HSI clock */
bogdanm 0:9b334a45a8ff 332 if (SetSysClock_PLL_HSI() == 0)
bogdanm 0:9b334a45a8ff 333 {
bogdanm 0:9b334a45a8ff 334 while(1)
bogdanm 0:9b334a45a8ff 335 {
bogdanm 0:9b334a45a8ff 336 // [TODO] Put something here to tell the user that a problem occured...
bogdanm 0:9b334a45a8ff 337 }
bogdanm 0:9b334a45a8ff 338 }
bogdanm 0:9b334a45a8ff 339 }
bogdanm 0:9b334a45a8ff 340 }
bogdanm 0:9b334a45a8ff 341
bogdanm 0:9b334a45a8ff 342 /* Output clock on MCO1 pin(PA8) for debugging purpose */
bogdanm 0:9b334a45a8ff 343 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
bogdanm 0:9b334a45a8ff 344 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
bogdanm 0:9b334a45a8ff 345 }
bogdanm 0:9b334a45a8ff 346
bogdanm 0:9b334a45a8ff 347 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
bogdanm 0:9b334a45a8ff 348 /******************************************************************************/
bogdanm 0:9b334a45a8ff 349 /* PLL (clocked by HSE) used as System clock source */
bogdanm 0:9b334a45a8ff 350 /******************************************************************************/
bogdanm 0:9b334a45a8ff 351 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
bogdanm 0:9b334a45a8ff 352 {
bogdanm 0:9b334a45a8ff 353 RCC_ClkInitTypeDef RCC_ClkInitStruct;
bogdanm 0:9b334a45a8ff 354 RCC_OscInitTypeDef RCC_OscInitStruct;
bogdanm 0:9b334a45a8ff 355
bogdanm 0:9b334a45a8ff 356 /* Used to gain time after DeepSleep in case HSI is used */
bogdanm 0:9b334a45a8ff 357 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
bogdanm 0:9b334a45a8ff 358 {
bogdanm 0:9b334a45a8ff 359 return 0;
bogdanm 0:9b334a45a8ff 360 }
bogdanm 0:9b334a45a8ff 361
bogdanm 0:9b334a45a8ff 362 /* The voltage scaling allows optimizing the power consumption when the device is
bogdanm 0:9b334a45a8ff 363 clocked below the maximum system frequency, to update the voltage scaling value
bogdanm 0:9b334a45a8ff 364 regarding system frequency refer to product datasheet. */
bogdanm 0:9b334a45a8ff 365 __PWR_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 366 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
bogdanm 0:9b334a45a8ff 367
bogdanm 0:9b334a45a8ff 368 /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
bogdanm 0:9b334a45a8ff 369 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
bogdanm 0:9b334a45a8ff 370 if (bypass == 0)
bogdanm 0:9b334a45a8ff 371 {
bogdanm 0:9b334a45a8ff 372 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
bogdanm 0:9b334a45a8ff 373 }
bogdanm 0:9b334a45a8ff 374 else
bogdanm 0:9b334a45a8ff 375 {
bogdanm 0:9b334a45a8ff 376 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
bogdanm 0:9b334a45a8ff 377 }
bogdanm 0:9b334a45a8ff 378 RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
bogdanm 0:9b334a45a8ff 379 RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */
bogdanm 0:9b334a45a8ff 380 // PLLCLK = (8 MHz * 8)/2 = 32 MHz
bogdanm 0:9b334a45a8ff 381 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
bogdanm 0:9b334a45a8ff 382 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
bogdanm 0:9b334a45a8ff 383 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_8;
bogdanm 0:9b334a45a8ff 384 RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
bogdanm 0:9b334a45a8ff 385 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
bogdanm 0:9b334a45a8ff 386 {
bogdanm 0:9b334a45a8ff 387 return 0; // FAIL
bogdanm 0:9b334a45a8ff 388 }
bogdanm 0:9b334a45a8ff 389
bogdanm 0:9b334a45a8ff 390 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
bogdanm 0:9b334a45a8ff 391 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
bogdanm 0:9b334a45a8ff 392 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
bogdanm 0:9b334a45a8ff 393 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz
bogdanm 0:9b334a45a8ff 394 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz
bogdanm 0:9b334a45a8ff 395 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz
bogdanm 0:9b334a45a8ff 396 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
bogdanm 0:9b334a45a8ff 397 {
bogdanm 0:9b334a45a8ff 398 return 0; // FAIL
bogdanm 0:9b334a45a8ff 399 }
bogdanm 0:9b334a45a8ff 400
bogdanm 0:9b334a45a8ff 401 /* Output clock on MCO1 pin(PA8) for debugging purpose */
bogdanm 0:9b334a45a8ff 402 //if (bypass == 0)
bogdanm 0:9b334a45a8ff 403 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
bogdanm 0:9b334a45a8ff 404 //else
bogdanm 0:9b334a45a8ff 405 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
bogdanm 0:9b334a45a8ff 406
bogdanm 0:9b334a45a8ff 407 return 1; // OK
bogdanm 0:9b334a45a8ff 408 }
bogdanm 0:9b334a45a8ff 409 #endif
bogdanm 0:9b334a45a8ff 410
bogdanm 0:9b334a45a8ff 411 /******************************************************************************/
bogdanm 0:9b334a45a8ff 412 /* PLL (clocked by HSI) used as System clock source */
bogdanm 0:9b334a45a8ff 413 /******************************************************************************/
bogdanm 0:9b334a45a8ff 414 uint8_t SetSysClock_PLL_HSI(void)
bogdanm 0:9b334a45a8ff 415 {
bogdanm 0:9b334a45a8ff 416 RCC_ClkInitTypeDef RCC_ClkInitStruct;
bogdanm 0:9b334a45a8ff 417 RCC_OscInitTypeDef RCC_OscInitStruct;
bogdanm 0:9b334a45a8ff 418
bogdanm 0:9b334a45a8ff 419 /* The voltage scaling allows optimizing the power consumption when the device is
bogdanm 0:9b334a45a8ff 420 clocked below the maximum system frequency, to update the voltage scaling value
bogdanm 0:9b334a45a8ff 421 regarding system frequency refer to product datasheet. */
bogdanm 0:9b334a45a8ff 422 __PWR_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 423 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
bogdanm 0:9b334a45a8ff 424
bogdanm 0:9b334a45a8ff 425 /* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */
bogdanm 0:9b334a45a8ff 426 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
bogdanm 0:9b334a45a8ff 427 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
bogdanm 0:9b334a45a8ff 428 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
bogdanm 0:9b334a45a8ff 429 RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */
bogdanm 0:9b334a45a8ff 430 // PLLCLK = (16 MHz * 4)/2 = 32 MHz
bogdanm 0:9b334a45a8ff 431 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
bogdanm 0:9b334a45a8ff 432 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
bogdanm 0:9b334a45a8ff 433 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
bogdanm 0:9b334a45a8ff 434 RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
bogdanm 0:9b334a45a8ff 435 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
bogdanm 0:9b334a45a8ff 436 {
bogdanm 0:9b334a45a8ff 437 return 0; // FAIL
bogdanm 0:9b334a45a8ff 438 }
bogdanm 0:9b334a45a8ff 439
bogdanm 0:9b334a45a8ff 440 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
bogdanm 0:9b334a45a8ff 441 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
bogdanm 0:9b334a45a8ff 442 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
bogdanm 0:9b334a45a8ff 443 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz
bogdanm 0:9b334a45a8ff 444 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz
bogdanm 0:9b334a45a8ff 445 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz
bogdanm 0:9b334a45a8ff 446 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
bogdanm 0:9b334a45a8ff 447 {
bogdanm 0:9b334a45a8ff 448 return 0; // FAIL
bogdanm 0:9b334a45a8ff 449 }
bogdanm 0:9b334a45a8ff 450
bogdanm 0:9b334a45a8ff 451 /* Output clock on MCO1 pin(PA8) for debugging purpose */
bogdanm 0:9b334a45a8ff 452 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
bogdanm 0:9b334a45a8ff 453
bogdanm 0:9b334a45a8ff 454 return 1; // OK
bogdanm 0:9b334a45a8ff 455 }
bogdanm 0:9b334a45a8ff 456
bogdanm 0:9b334a45a8ff 457 /**
bogdanm 0:9b334a45a8ff 458 * @}
bogdanm 0:9b334a45a8ff 459 */
bogdanm 0:9b334a45a8ff 460
bogdanm 0:9b334a45a8ff 461 /**
bogdanm 0:9b334a45a8ff 462 * @}
bogdanm 0:9b334a45a8ff 463 */
bogdanm 0:9b334a45a8ff 464
bogdanm 0:9b334a45a8ff 465 /**
bogdanm 0:9b334a45a8ff 466 * @}
bogdanm 0:9b334a45a8ff 467 */
bogdanm 0:9b334a45a8ff 468
bogdanm 0:9b334a45a8ff 469 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/