philippe s. / mbed-dev

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/system_stm32f7xx.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file system_stm32f7xx.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.0.1
bogdanm 0:9b334a45a8ff 6 * @date 25-June-2015
bogdanm 0:9b334a45a8ff 7 * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 * This file provides two functions and one global variable to be called from
bogdanm 0:9b334a45a8ff 10 * user application:
bogdanm 0:9b334a45a8ff 11 * - SystemInit(): This function is called at startup just after reset and
bogdanm 0:9b334a45a8ff 12 * before branch to main program. This call is made inside
bogdanm 0:9b334a45a8ff 13 * the "startup_stm32f7xx.s" file.
bogdanm 0:9b334a45a8ff 14 *
bogdanm 0:9b334a45a8ff 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
bogdanm 0:9b334a45a8ff 16 * by the user application to setup the SysTick
bogdanm 0:9b334a45a8ff 17 * timer or configure other parameters.
bogdanm 0:9b334a45a8ff 18 *
bogdanm 0:9b334a45a8ff 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
bogdanm 0:9b334a45a8ff 20 * be called whenever the core clock is changed
bogdanm 0:9b334a45a8ff 21 * during program execution.
bogdanm 0:9b334a45a8ff 22 *
bogdanm 0:9b334a45a8ff 23 * This file configures the system clock as follows:
bogdanm 0:9b334a45a8ff 24 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 25 * System clock source | [1] PLL_HSE_XTAL | [2] PLL_HSI if [1] fails
bogdanm 0:9b334a45a8ff 26 * | (external 25MHz xtal) | (internal 16MHz clock)
bogdanm 0:9b334a45a8ff 27 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 28 * SYSCLK(MHz) | 216 | 216
bogdanm 0:9b334a45a8ff 29 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 30 * AHBCLK (MHz) | 216 | 216
bogdanm 0:9b334a45a8ff 31 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 32 * APB1CLK (MHz) | 54 | 54
bogdanm 0:9b334a45a8ff 33 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 34 * APB2CLK (MHz) | 108 | 108
bogdanm 0:9b334a45a8ff 35 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 36 * USB capable | YES | NO
bogdanm 0:9b334a45a8ff 37 * with 48 MHz precise clock | |
bogdanm 0:9b334a45a8ff 38 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 39 ******************************************************************************
bogdanm 0:9b334a45a8ff 40 * @attention
bogdanm 0:9b334a45a8ff 41 *
bogdanm 0:9b334a45a8ff 42 * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 43 *
bogdanm 0:9b334a45a8ff 44 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 45 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 46 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 47 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 48 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 49 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 50 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 51 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 52 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 53 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 54 *
bogdanm 0:9b334a45a8ff 55 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 56 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 58 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 61 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 62 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 63 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 65 *
bogdanm 0:9b334a45a8ff 66 ******************************************************************************
bogdanm 0:9b334a45a8ff 67 */
bogdanm 0:9b334a45a8ff 68
bogdanm 0:9b334a45a8ff 69 /** @addtogroup CMSIS
bogdanm 0:9b334a45a8ff 70 * @{
bogdanm 0:9b334a45a8ff 71 */
bogdanm 0:9b334a45a8ff 72
bogdanm 0:9b334a45a8ff 73 /** @addtogroup stm32f7xx_system
bogdanm 0:9b334a45a8ff 74 * @{
bogdanm 0:9b334a45a8ff 75 */
bogdanm 0:9b334a45a8ff 76
bogdanm 0:9b334a45a8ff 77 /** @addtogroup STM32F7xx_System_Private_Includes
bogdanm 0:9b334a45a8ff 78 * @{
bogdanm 0:9b334a45a8ff 79 */
bogdanm 0:9b334a45a8ff 80
bogdanm 0:9b334a45a8ff 81 #include "stm32f7xx.h"
bogdanm 0:9b334a45a8ff 82 #include "hal_tick.h"
bogdanm 0:9b334a45a8ff 83
bogdanm 0:9b334a45a8ff 84 HAL_StatusTypeDef HAL_Init(void);
bogdanm 0:9b334a45a8ff 85
bogdanm 0:9b334a45a8ff 86 #if !defined (HSE_VALUE)
bogdanm 0:9b334a45a8ff 87 #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
bogdanm 0:9b334a45a8ff 88 #endif /* HSE_VALUE */
bogdanm 0:9b334a45a8ff 89
bogdanm 0:9b334a45a8ff 90 #if !defined (HSI_VALUE)
bogdanm 0:9b334a45a8ff 91 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
bogdanm 0:9b334a45a8ff 92 #endif /* HSI_VALUE */
bogdanm 0:9b334a45a8ff 93
bogdanm 0:9b334a45a8ff 94 /**
bogdanm 0:9b334a45a8ff 95 * @}
bogdanm 0:9b334a45a8ff 96 */
bogdanm 0:9b334a45a8ff 97
bogdanm 0:9b334a45a8ff 98 /** @addtogroup STM32F7xx_System_Private_TypesDefinitions
bogdanm 0:9b334a45a8ff 99 * @{
bogdanm 0:9b334a45a8ff 100 */
bogdanm 0:9b334a45a8ff 101
bogdanm 0:9b334a45a8ff 102 /**
bogdanm 0:9b334a45a8ff 103 * @}
bogdanm 0:9b334a45a8ff 104 */
bogdanm 0:9b334a45a8ff 105
bogdanm 0:9b334a45a8ff 106 /** @addtogroup STM32F7xx_System_Private_Defines
bogdanm 0:9b334a45a8ff 107 * @{
bogdanm 0:9b334a45a8ff 108 */
bogdanm 0:9b334a45a8ff 109
bogdanm 0:9b334a45a8ff 110 /************************* Miscellaneous Configuration ************************/
bogdanm 0:9b334a45a8ff 111 /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
bogdanm 0:9b334a45a8ff 112 on EVAL board as data memory */
bogdanm 0:9b334a45a8ff 113 /* #define DATA_IN_ExtSRAM */
bogdanm 0:9b334a45a8ff 114 /* #define DATA_IN_ExtSDRAM */
bogdanm 0:9b334a45a8ff 115
bogdanm 0:9b334a45a8ff 116 #if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
bogdanm 0:9b334a45a8ff 117 #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
bogdanm 0:9b334a45a8ff 118 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
bogdanm 0:9b334a45a8ff 119
bogdanm 0:9b334a45a8ff 120 /*!< Uncomment the following line if you need to relocate your vector Table in
bogdanm 0:9b334a45a8ff 121 Internal SRAM. */
bogdanm 0:9b334a45a8ff 122 /* #define VECT_TAB_SRAM */
bogdanm 0:9b334a45a8ff 123 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
bogdanm 0:9b334a45a8ff 124 This value must be a multiple of 0x200. */
bogdanm 0:9b334a45a8ff 125 /******************************************************************************/
bogdanm 0:9b334a45a8ff 126
bogdanm 0:9b334a45a8ff 127 /**
bogdanm 0:9b334a45a8ff 128 * @}
bogdanm 0:9b334a45a8ff 129 */
bogdanm 0:9b334a45a8ff 130
bogdanm 0:9b334a45a8ff 131 /** @addtogroup STM32F7xx_System_Private_Macros
bogdanm 0:9b334a45a8ff 132 * @{
bogdanm 0:9b334a45a8ff 133 */
bogdanm 0:9b334a45a8ff 134
bogdanm 0:9b334a45a8ff 135 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
bogdanm 0:9b334a45a8ff 136 #define USE_PLL_HSE_EXTC (0) /* Use external clock --> NOT USED ON THIS BOARD */
bogdanm 0:9b334a45a8ff 137 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
bogdanm 0:9b334a45a8ff 138
bogdanm 0:9b334a45a8ff 139 /**
bogdanm 0:9b334a45a8ff 140 * @}
bogdanm 0:9b334a45a8ff 141 */
bogdanm 0:9b334a45a8ff 142
bogdanm 0:9b334a45a8ff 143 /** @addtogroup STM32F7xx_System_Private_Variables
bogdanm 0:9b334a45a8ff 144 * @{
bogdanm 0:9b334a45a8ff 145 */
bogdanm 0:9b334a45a8ff 146
bogdanm 0:9b334a45a8ff 147 /* This variable is updated in three ways:
bogdanm 0:9b334a45a8ff 148 1) by calling CMSIS function SystemCoreClockUpdate()
bogdanm 0:9b334a45a8ff 149 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
bogdanm 0:9b334a45a8ff 150 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
bogdanm 0:9b334a45a8ff 151 Note: If you use this function to configure the system clock; then there
bogdanm 0:9b334a45a8ff 152 is no need to call the 2 first functions listed above, since SystemCoreClock
bogdanm 0:9b334a45a8ff 153 variable is updated automatically.
bogdanm 0:9b334a45a8ff 154 */
bogdanm 0:9b334a45a8ff 155 uint32_t SystemCoreClock = HSI_VALUE;
bogdanm 0:9b334a45a8ff 156 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
bogdanm 0:9b334a45a8ff 157
bogdanm 0:9b334a45a8ff 158 /**
bogdanm 0:9b334a45a8ff 159 * @}
bogdanm 0:9b334a45a8ff 160 */
bogdanm 0:9b334a45a8ff 161
bogdanm 0:9b334a45a8ff 162 /** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
bogdanm 0:9b334a45a8ff 163 * @{
bogdanm 0:9b334a45a8ff 164 */
bogdanm 0:9b334a45a8ff 165 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
bogdanm 0:9b334a45a8ff 166 static void SystemInit_ExtMemCtl(void);
bogdanm 0:9b334a45a8ff 167 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
bogdanm 0:9b334a45a8ff 168
bogdanm 0:9b334a45a8ff 169 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
bogdanm 0:9b334a45a8ff 170 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
bogdanm 0:9b334a45a8ff 171 #endif
bogdanm 0:9b334a45a8ff 172
bogdanm 0:9b334a45a8ff 173 uint8_t SetSysClock_PLL_HSI(void);
bogdanm 0:9b334a45a8ff 174
bogdanm 0:9b334a45a8ff 175 /**
bogdanm 0:9b334a45a8ff 176 * @}
bogdanm 0:9b334a45a8ff 177 */
bogdanm 0:9b334a45a8ff 178
bogdanm 0:9b334a45a8ff 179 /** @addtogroup STM32F7xx_System_Private_Functions
bogdanm 0:9b334a45a8ff 180 * @{
bogdanm 0:9b334a45a8ff 181 */
bogdanm 0:9b334a45a8ff 182
bogdanm 0:9b334a45a8ff 183 /**
bogdanm 0:9b334a45a8ff 184 * @brief Setup the microcontroller system
bogdanm 0:9b334a45a8ff 185 * Initialize the Embedded Flash Interface, the PLL and update the
bogdanm 0:9b334a45a8ff 186 * SystemFrequency variable.
bogdanm 0:9b334a45a8ff 187 * @param None
bogdanm 0:9b334a45a8ff 188 * @retval None
bogdanm 0:9b334a45a8ff 189 */
bogdanm 0:9b334a45a8ff 190 void SystemInit(void)
bogdanm 0:9b334a45a8ff 191 {
bogdanm 0:9b334a45a8ff 192 /* FPU settings ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 193 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
bogdanm 0:9b334a45a8ff 194 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
bogdanm 0:9b334a45a8ff 195 #endif
bogdanm 0:9b334a45a8ff 196 /* Reset the RCC clock configuration to the default reset state ------------*/
bogdanm 0:9b334a45a8ff 197 /* Set HSION bit */
bogdanm 0:9b334a45a8ff 198 RCC->CR |= (uint32_t)0x00000001;
bogdanm 0:9b334a45a8ff 199
bogdanm 0:9b334a45a8ff 200 /* Reset CFGR register */
bogdanm 0:9b334a45a8ff 201 RCC->CFGR = 0x00000000;
bogdanm 0:9b334a45a8ff 202
bogdanm 0:9b334a45a8ff 203 /* Reset HSEON, CSSON and PLLON bits */
bogdanm 0:9b334a45a8ff 204 RCC->CR &= (uint32_t)0xFEF6FFFF;
bogdanm 0:9b334a45a8ff 205
bogdanm 0:9b334a45a8ff 206 /* Reset PLLCFGR register */
bogdanm 0:9b334a45a8ff 207 RCC->PLLCFGR = 0x24003010;
bogdanm 0:9b334a45a8ff 208
bogdanm 0:9b334a45a8ff 209 /* Reset HSEBYP bit */
bogdanm 0:9b334a45a8ff 210 RCC->CR &= (uint32_t)0xFFFBFFFF;
bogdanm 0:9b334a45a8ff 211
bogdanm 0:9b334a45a8ff 212 /* Disable all interrupts */
bogdanm 0:9b334a45a8ff 213 RCC->CIR = 0x00000000;
bogdanm 0:9b334a45a8ff 214
bogdanm 0:9b334a45a8ff 215 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
bogdanm 0:9b334a45a8ff 216 SystemInit_ExtMemCtl();
bogdanm 0:9b334a45a8ff 217 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
bogdanm 0:9b334a45a8ff 218
bogdanm 0:9b334a45a8ff 219 /* Configure the Vector Table location add offset address ------------------*/
bogdanm 0:9b334a45a8ff 220 #ifdef VECT_TAB_SRAM
bogdanm 0:9b334a45a8ff 221 SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
bogdanm 0:9b334a45a8ff 222 #else
bogdanm 0:9b334a45a8ff 223 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
bogdanm 0:9b334a45a8ff 224 #endif
bogdanm 0:9b334a45a8ff 225
bogdanm 0:9b334a45a8ff 226 /* Configure the Cube driver */
bogdanm 0:9b334a45a8ff 227 SystemCoreClock = HSI_VALUE; // At this stage the HSI is used as system clock
bogdanm 0:9b334a45a8ff 228 HAL_Init();
bogdanm 0:9b334a45a8ff 229
bogdanm 0:9b334a45a8ff 230 // Enable CPU L1-Cache
bogdanm 0:9b334a45a8ff 231 SCB_EnableICache();
bogdanm 0:9b334a45a8ff 232 SCB_EnableDCache();
bogdanm 0:9b334a45a8ff 233
bogdanm 0:9b334a45a8ff 234 /* Configure the System clock source, PLL Multiplier and Divider factors,
bogdanm 0:9b334a45a8ff 235 AHB/APBx prescalers and Flash settings */
bogdanm 0:9b334a45a8ff 236 SetSysClock();
bogdanm 0:9b334a45a8ff 237
bogdanm 0:9b334a45a8ff 238 /* Reset the timer to avoid issues after the RAM initialization */
bogdanm 0:9b334a45a8ff 239 TIM_MST_RESET_ON;
bogdanm 0:9b334a45a8ff 240 TIM_MST_RESET_OFF;
bogdanm 0:9b334a45a8ff 241 }
bogdanm 0:9b334a45a8ff 242
bogdanm 0:9b334a45a8ff 243 /**
bogdanm 0:9b334a45a8ff 244 * @brief Update SystemCoreClock variable according to Clock Register Values.
bogdanm 0:9b334a45a8ff 245 * The SystemCoreClock variable contains the core clock (HCLK), it can
bogdanm 0:9b334a45a8ff 246 * be used by the user application to setup the SysTick timer or configure
bogdanm 0:9b334a45a8ff 247 * other parameters.
bogdanm 0:9b334a45a8ff 248 *
bogdanm 0:9b334a45a8ff 249 * @note Each time the core clock (HCLK) changes, this function must be called
bogdanm 0:9b334a45a8ff 250 * to update SystemCoreClock variable value. Otherwise, any configuration
bogdanm 0:9b334a45a8ff 251 * based on this variable will be incorrect.
bogdanm 0:9b334a45a8ff 252 *
bogdanm 0:9b334a45a8ff 253 * @note - The system frequency computed by this function is not the real
bogdanm 0:9b334a45a8ff 254 * frequency in the chip. It is calculated based on the predefined
bogdanm 0:9b334a45a8ff 255 * constant and the selected clock source:
bogdanm 0:9b334a45a8ff 256 *
bogdanm 0:9b334a45a8ff 257 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
bogdanm 0:9b334a45a8ff 258 *
bogdanm 0:9b334a45a8ff 259 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
bogdanm 0:9b334a45a8ff 260 *
bogdanm 0:9b334a45a8ff 261 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
bogdanm 0:9b334a45a8ff 262 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
bogdanm 0:9b334a45a8ff 263 *
bogdanm 0:9b334a45a8ff 264 * (*) HSI_VALUE is a constant defined in stm32f7xx.h file (default value
bogdanm 0:9b334a45a8ff 265 * 16 MHz) but the real value may vary depending on the variations
bogdanm 0:9b334a45a8ff 266 * in voltage and temperature.
bogdanm 0:9b334a45a8ff 267 *
bogdanm 0:9b334a45a8ff 268 * (**) HSE_VALUE is a constant defined in stm32f7xx.h file (default value
bogdanm 0:9b334a45a8ff 269 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
bogdanm 0:9b334a45a8ff 270 * frequency of the crystal used. Otherwise, this function may
bogdanm 0:9b334a45a8ff 271 * have wrong result.
bogdanm 0:9b334a45a8ff 272 *
bogdanm 0:9b334a45a8ff 273 * - The result of this function could be not correct when using fractional
bogdanm 0:9b334a45a8ff 274 * value for HSE crystal.
bogdanm 0:9b334a45a8ff 275 *
bogdanm 0:9b334a45a8ff 276 * @param None
bogdanm 0:9b334a45a8ff 277 * @retval None
bogdanm 0:9b334a45a8ff 278 */
bogdanm 0:9b334a45a8ff 279 void SystemCoreClockUpdate(void)
bogdanm 0:9b334a45a8ff 280 {
bogdanm 0:9b334a45a8ff 281 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
bogdanm 0:9b334a45a8ff 282
bogdanm 0:9b334a45a8ff 283 /* Get SYSCLK source -------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 284 tmp = RCC->CFGR & RCC_CFGR_SWS;
bogdanm 0:9b334a45a8ff 285
bogdanm 0:9b334a45a8ff 286 switch (tmp)
bogdanm 0:9b334a45a8ff 287 {
bogdanm 0:9b334a45a8ff 288 case 0x00: /* HSI used as system clock source */
bogdanm 0:9b334a45a8ff 289 SystemCoreClock = HSI_VALUE;
bogdanm 0:9b334a45a8ff 290 break;
bogdanm 0:9b334a45a8ff 291 case 0x04: /* HSE used as system clock source */
bogdanm 0:9b334a45a8ff 292 SystemCoreClock = HSE_VALUE;
bogdanm 0:9b334a45a8ff 293 break;
bogdanm 0:9b334a45a8ff 294 case 0x08: /* PLL used as system clock source */
bogdanm 0:9b334a45a8ff 295
bogdanm 0:9b334a45a8ff 296 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
bogdanm 0:9b334a45a8ff 297 SYSCLK = PLL_VCO / PLL_P
bogdanm 0:9b334a45a8ff 298 */
bogdanm 0:9b334a45a8ff 299 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
bogdanm 0:9b334a45a8ff 300 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
bogdanm 0:9b334a45a8ff 301
bogdanm 0:9b334a45a8ff 302 if (pllsource != 0)
bogdanm 0:9b334a45a8ff 303 {
bogdanm 0:9b334a45a8ff 304 /* HSE used as PLL clock source */
bogdanm 0:9b334a45a8ff 305 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
bogdanm 0:9b334a45a8ff 306 }
bogdanm 0:9b334a45a8ff 307 else
bogdanm 0:9b334a45a8ff 308 {
bogdanm 0:9b334a45a8ff 309 /* HSI used as PLL clock source */
bogdanm 0:9b334a45a8ff 310 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
bogdanm 0:9b334a45a8ff 311 }
bogdanm 0:9b334a45a8ff 312
bogdanm 0:9b334a45a8ff 313 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
bogdanm 0:9b334a45a8ff 314 SystemCoreClock = pllvco/pllp;
bogdanm 0:9b334a45a8ff 315 break;
bogdanm 0:9b334a45a8ff 316 default:
bogdanm 0:9b334a45a8ff 317 SystemCoreClock = HSI_VALUE;
bogdanm 0:9b334a45a8ff 318 break;
bogdanm 0:9b334a45a8ff 319 }
bogdanm 0:9b334a45a8ff 320 /* Compute HCLK frequency --------------------------------------------------*/
bogdanm 0:9b334a45a8ff 321 /* Get HCLK prescaler */
bogdanm 0:9b334a45a8ff 322 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
bogdanm 0:9b334a45a8ff 323 /* HCLK frequency */
bogdanm 0:9b334a45a8ff 324 SystemCoreClock >>= tmp;
bogdanm 0:9b334a45a8ff 325 }
bogdanm 0:9b334a45a8ff 326
bogdanm 0:9b334a45a8ff 327 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
bogdanm 0:9b334a45a8ff 328 /**
bogdanm 0:9b334a45a8ff 329 * @brief Setup the external memory controller.
bogdanm 0:9b334a45a8ff 330 * Called in startup_stm32f7xx.s before jump to main.
bogdanm 0:9b334a45a8ff 331 * This function configures the external memories (SRAM/SDRAM)
bogdanm 0:9b334a45a8ff 332 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
bogdanm 0:9b334a45a8ff 333 * @param None
bogdanm 0:9b334a45a8ff 334 * @retval None
bogdanm 0:9b334a45a8ff 335 */
bogdanm 0:9b334a45a8ff 336 void SystemInit_ExtMemCtl(void)
bogdanm 0:9b334a45a8ff 337 {
bogdanm 0:9b334a45a8ff 338 __IO uint32_t tmp = 0;
bogdanm 0:9b334a45a8ff 339 #if defined (DATA_IN_ExtSDRAM)
bogdanm 0:9b334a45a8ff 340 register uint32_t tmpreg = 0, timeout = 0xFFFF;
bogdanm 0:9b334a45a8ff 341 register uint32_t index;
bogdanm 0:9b334a45a8ff 342
bogdanm 0:9b334a45a8ff 343 /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
bogdanm 0:9b334a45a8ff 344 clock */
bogdanm 0:9b334a45a8ff 345 RCC->AHB1ENR |= 0x000001F8;
bogdanm 0:9b334a45a8ff 346
bogdanm 0:9b334a45a8ff 347 /* Delay after an RCC peripheral clock enabling */
bogdanm 0:9b334a45a8ff 348 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
bogdanm 0:9b334a45a8ff 349
bogdanm 0:9b334a45a8ff 350 /* Connect PDx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 351 GPIOD->AFR[0] = 0x000000CC;
bogdanm 0:9b334a45a8ff 352 GPIOD->AFR[1] = 0xCC000CCC;
bogdanm 0:9b334a45a8ff 353 /* Configure PDx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 354 GPIOD->MODER = 0xA02A000A;
bogdanm 0:9b334a45a8ff 355 /* Configure PDx pins speed to 50 MHz */
bogdanm 0:9b334a45a8ff 356 GPIOD->OSPEEDR = 0xA02A000A;
bogdanm 0:9b334a45a8ff 357 /* Configure PDx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 358 GPIOD->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 359 /* No pull-up, pull-down for PDx pins */
bogdanm 0:9b334a45a8ff 360 GPIOD->PUPDR = 0x50150005;
bogdanm 0:9b334a45a8ff 361
bogdanm 0:9b334a45a8ff 362 /* Connect PEx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 363 GPIOE->AFR[0] = 0xC00000CC;
bogdanm 0:9b334a45a8ff 364 GPIOE->AFR[1] = 0xCCCCCCCC;
bogdanm 0:9b334a45a8ff 365 /* Configure PEx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 366 GPIOE->MODER = 0xAAAA800A;
bogdanm 0:9b334a45a8ff 367 /* Configure PEx pins speed to 50 MHz */
bogdanm 0:9b334a45a8ff 368 GPIOE->OSPEEDR = 0xAAAA800A;
bogdanm 0:9b334a45a8ff 369 /* Configure PEx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 370 GPIOE->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 371 /* No pull-up, pull-down for PEx pins */
bogdanm 0:9b334a45a8ff 372 GPIOE->PUPDR = 0x55554005;
bogdanm 0:9b334a45a8ff 373
bogdanm 0:9b334a45a8ff 374 /* Connect PFx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 375 GPIOF->AFR[0] = 0x00CCCCCC;
bogdanm 0:9b334a45a8ff 376 GPIOF->AFR[1] = 0xCCCCC000;
bogdanm 0:9b334a45a8ff 377 /* Configure PFx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 378 GPIOF->MODER = 0xAA800AAA;
bogdanm 0:9b334a45a8ff 379 /* Configure PFx pins speed to 50 MHz */
bogdanm 0:9b334a45a8ff 380 GPIOF->OSPEEDR = 0xAA800AAA;
bogdanm 0:9b334a45a8ff 381 /* Configure PFx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 382 GPIOF->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 383 /* No pull-up, pull-down for PFx pins */
bogdanm 0:9b334a45a8ff 384 GPIOF->PUPDR = 0x55400555;
bogdanm 0:9b334a45a8ff 385
bogdanm 0:9b334a45a8ff 386 /* Connect PGx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 387 GPIOG->AFR[0] = 0x00CC00CC;
bogdanm 0:9b334a45a8ff 388 GPIOG->AFR[1] = 0xC000000C;
bogdanm 0:9b334a45a8ff 389 /* Configure PGx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 390 GPIOG->MODER = 0x80020A0A;
bogdanm 0:9b334a45a8ff 391 /* Configure PGx pins speed to 50 MHz */
bogdanm 0:9b334a45a8ff 392 GPIOG->OSPEEDR = 0x80020A0A;
bogdanm 0:9b334a45a8ff 393 /* Configure PGx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 394 GPIOG->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 395 /* No pull-up, pull-down for PGx pins */
bogdanm 0:9b334a45a8ff 396 GPIOG->PUPDR = 0x40010505;
bogdanm 0:9b334a45a8ff 397
bogdanm 0:9b334a45a8ff 398 /* Connect PHx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 399 GPIOH->AFR[0] = 0x00C0CC00;
bogdanm 0:9b334a45a8ff 400 GPIOH->AFR[1] = 0xCCCCCCCC;
bogdanm 0:9b334a45a8ff 401 /* Configure PHx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 402 GPIOH->MODER = 0xAAAA08A0;
bogdanm 0:9b334a45a8ff 403 /* Configure PHx pins speed to 50 MHz */
bogdanm 0:9b334a45a8ff 404 GPIOH->OSPEEDR = 0xAAAA08A0;
bogdanm 0:9b334a45a8ff 405 /* Configure PHx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 406 GPIOH->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 407 /* No pull-up, pull-down for PHx pins */
bogdanm 0:9b334a45a8ff 408 GPIOH->PUPDR = 0x55550450;
bogdanm 0:9b334a45a8ff 409
bogdanm 0:9b334a45a8ff 410 /* Connect PIx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 411 GPIOI->AFR[0] = 0xCCCCCCCC;
bogdanm 0:9b334a45a8ff 412 GPIOI->AFR[1] = 0x00000CC0;
bogdanm 0:9b334a45a8ff 413 /* Configure PIx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 414 GPIOI->MODER = 0x0028AAAA;
bogdanm 0:9b334a45a8ff 415 /* Configure PIx pins speed to 50 MHz */
bogdanm 0:9b334a45a8ff 416 GPIOI->OSPEEDR = 0x0028AAAA;
bogdanm 0:9b334a45a8ff 417 /* Configure PIx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 418 GPIOI->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 419 /* No pull-up, pull-down for PIx pins */
bogdanm 0:9b334a45a8ff 420 GPIOI->PUPDR = 0x00145555;
bogdanm 0:9b334a45a8ff 421
bogdanm 0:9b334a45a8ff 422 /*-- FMC Configuration ------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 423 /* Enable the FMC interface clock */
bogdanm 0:9b334a45a8ff 424 RCC->AHB3ENR |= 0x00000001;
bogdanm 0:9b334a45a8ff 425
bogdanm 0:9b334a45a8ff 426 /* Delay after an RCC peripheral clock enabling */
bogdanm 0:9b334a45a8ff 427 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
bogdanm 0:9b334a45a8ff 428
bogdanm 0:9b334a45a8ff 429 /* Configure and enable SDRAM bank1 */
bogdanm 0:9b334a45a8ff 430 FMC_Bank5_6->SDCR[0] = 0x000019E5;
bogdanm 0:9b334a45a8ff 431 FMC_Bank5_6->SDTR[0] = 0x01116361;
bogdanm 0:9b334a45a8ff 432
bogdanm 0:9b334a45a8ff 433 /* SDRAM initialization sequence */
bogdanm 0:9b334a45a8ff 434 /* Clock enable command */
bogdanm 0:9b334a45a8ff 435 FMC_Bank5_6->SDCMR = 0x00000011;
bogdanm 0:9b334a45a8ff 436 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
bogdanm 0:9b334a45a8ff 437 while((tmpreg != 0) && (timeout-- > 0))
bogdanm 0:9b334a45a8ff 438 {
bogdanm 0:9b334a45a8ff 439 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
bogdanm 0:9b334a45a8ff 440 }
bogdanm 0:9b334a45a8ff 441
bogdanm 0:9b334a45a8ff 442 /* Delay */
bogdanm 0:9b334a45a8ff 443 for (index = 0; index<1000; index++);
bogdanm 0:9b334a45a8ff 444
bogdanm 0:9b334a45a8ff 445 /* PALL command */
bogdanm 0:9b334a45a8ff 446 FMC_Bank5_6->SDCMR = 0x00000012;
bogdanm 0:9b334a45a8ff 447 timeout = 0xFFFF;
bogdanm 0:9b334a45a8ff 448 while((tmpreg != 0) && (timeout-- > 0))
bogdanm 0:9b334a45a8ff 449 {
bogdanm 0:9b334a45a8ff 450 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
bogdanm 0:9b334a45a8ff 451 }
bogdanm 0:9b334a45a8ff 452
bogdanm 0:9b334a45a8ff 453 /* Auto refresh command */
bogdanm 0:9b334a45a8ff 454 FMC_Bank5_6->SDCMR = 0x000000F3;
bogdanm 0:9b334a45a8ff 455 timeout = 0xFFFF;
bogdanm 0:9b334a45a8ff 456 while((tmpreg != 0) && (timeout-- > 0))
bogdanm 0:9b334a45a8ff 457 {
bogdanm 0:9b334a45a8ff 458 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
bogdanm 0:9b334a45a8ff 459 }
bogdanm 0:9b334a45a8ff 460
bogdanm 0:9b334a45a8ff 461 /* MRD register program */
bogdanm 0:9b334a45a8ff 462 FMC_Bank5_6->SDCMR = 0x00046014;
bogdanm 0:9b334a45a8ff 463 timeout = 0xFFFF;
bogdanm 0:9b334a45a8ff 464 while((tmpreg != 0) && (timeout-- > 0))
bogdanm 0:9b334a45a8ff 465 {
bogdanm 0:9b334a45a8ff 466 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
bogdanm 0:9b334a45a8ff 467 }
bogdanm 0:9b334a45a8ff 468
bogdanm 0:9b334a45a8ff 469 /* Set refresh count */
bogdanm 0:9b334a45a8ff 470 tmpreg = FMC_Bank5_6->SDRTR;
bogdanm 0:9b334a45a8ff 471 FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
bogdanm 0:9b334a45a8ff 472
bogdanm 0:9b334a45a8ff 473 /* Disable write protection */
bogdanm 0:9b334a45a8ff 474 tmpreg = FMC_Bank5_6->SDCR[0];
bogdanm 0:9b334a45a8ff 475 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
bogdanm 0:9b334a45a8ff 476 #endif /* DATA_IN_ExtSDRAM */
bogdanm 0:9b334a45a8ff 477
bogdanm 0:9b334a45a8ff 478 #if defined(DATA_IN_ExtSRAM)
bogdanm 0:9b334a45a8ff 479 /*-- GPIOs Configuration -----------------------------------------------------*/
bogdanm 0:9b334a45a8ff 480 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
bogdanm 0:9b334a45a8ff 481 RCC->AHB1ENR |= 0x00000078;
bogdanm 0:9b334a45a8ff 482
bogdanm 0:9b334a45a8ff 483 /* Delay after an RCC peripheral clock enabling */
bogdanm 0:9b334a45a8ff 484 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
bogdanm 0:9b334a45a8ff 485
bogdanm 0:9b334a45a8ff 486 /* Connect PDx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 487 GPIOD->AFR[0] = 0x00CCC0CC;
bogdanm 0:9b334a45a8ff 488 GPIOD->AFR[1] = 0xCCCCCCCC;
bogdanm 0:9b334a45a8ff 489 /* Configure PDx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 490 GPIOD->MODER = 0xAAAA0A8A;
bogdanm 0:9b334a45a8ff 491 /* Configure PDx pins speed to 100 MHz */
bogdanm 0:9b334a45a8ff 492 GPIOD->OSPEEDR = 0xFFFF0FCF;
bogdanm 0:9b334a45a8ff 493 /* Configure PDx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 494 GPIOD->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 495 /* No pull-up, pull-down for PDx pins */
bogdanm 0:9b334a45a8ff 496 GPIOD->PUPDR = 0x55550545;
bogdanm 0:9b334a45a8ff 497
bogdanm 0:9b334a45a8ff 498 /* Connect PEx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 499 GPIOE->AFR[0] = 0xC00CC0CC;
bogdanm 0:9b334a45a8ff 500 GPIOE->AFR[1] = 0xCCCCCCCC;
bogdanm 0:9b334a45a8ff 501 /* Configure PEx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 502 GPIOE->MODER = 0xAAAA828A;
bogdanm 0:9b334a45a8ff 503 /* Configure PEx pins speed to 100 MHz */
bogdanm 0:9b334a45a8ff 504 GPIOE->OSPEEDR = 0xFFFFC3CF;
bogdanm 0:9b334a45a8ff 505 /* Configure PEx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 506 GPIOE->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 507 /* No pull-up, pull-down for PEx pins */
bogdanm 0:9b334a45a8ff 508 GPIOE->PUPDR = 0x55554145;
bogdanm 0:9b334a45a8ff 509
bogdanm 0:9b334a45a8ff 510 /* Connect PFx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 511 GPIOF->AFR[0] = 0x00CCCCCC;
bogdanm 0:9b334a45a8ff 512 GPIOF->AFR[1] = 0xCCCC0000;
bogdanm 0:9b334a45a8ff 513 /* Configure PFx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 514 GPIOF->MODER = 0xAA000AAA;
bogdanm 0:9b334a45a8ff 515 /* Configure PFx pins speed to 100 MHz */
bogdanm 0:9b334a45a8ff 516 GPIOF->OSPEEDR = 0xFF000FFF;
bogdanm 0:9b334a45a8ff 517 /* Configure PFx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 518 GPIOF->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 519 /* No pull-up, pull-down for PFx pins */
bogdanm 0:9b334a45a8ff 520 GPIOF->PUPDR = 0x55000555;
bogdanm 0:9b334a45a8ff 521
bogdanm 0:9b334a45a8ff 522 /* Connect PGx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 523 GPIOG->AFR[0] = 0x00CCCCCC;
bogdanm 0:9b334a45a8ff 524 GPIOG->AFR[1] = 0x000000C0;
bogdanm 0:9b334a45a8ff 525 /* Configure PGx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 526 GPIOG->MODER = 0x00200AAA;
bogdanm 0:9b334a45a8ff 527 /* Configure PGx pins speed to 100 MHz */
bogdanm 0:9b334a45a8ff 528 GPIOG->OSPEEDR = 0x00300FFF;
bogdanm 0:9b334a45a8ff 529 /* Configure PGx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 530 GPIOG->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 531 /* No pull-up, pull-down for PGx pins */
bogdanm 0:9b334a45a8ff 532 GPIOG->PUPDR = 0x00100555;
bogdanm 0:9b334a45a8ff 533
bogdanm 0:9b334a45a8ff 534 /*-- FMC/FSMC Configuration --------------------------------------------------*/
bogdanm 0:9b334a45a8ff 535 /* Enable the FMC/FSMC interface clock */
bogdanm 0:9b334a45a8ff 536 RCC->AHB3ENR |= 0x00000001;
bogdanm 0:9b334a45a8ff 537
bogdanm 0:9b334a45a8ff 538 /* Delay after an RCC peripheral clock enabling */
bogdanm 0:9b334a45a8ff 539 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
bogdanm 0:9b334a45a8ff 540
bogdanm 0:9b334a45a8ff 541 /* Configure and enable Bank1_SRAM2 */
bogdanm 0:9b334a45a8ff 542 FMC_Bank1->BTCR[4] = 0x00001091;
bogdanm 0:9b334a45a8ff 543 FMC_Bank1->BTCR[5] = 0x00110212;
bogdanm 0:9b334a45a8ff 544 FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
bogdanm 0:9b334a45a8ff 545
bogdanm 0:9b334a45a8ff 546 #endif /* DATA_IN_ExtSRAM */
bogdanm 0:9b334a45a8ff 547
bogdanm 0:9b334a45a8ff 548 (void)(tmp);
bogdanm 0:9b334a45a8ff 549 }
bogdanm 0:9b334a45a8ff 550 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
bogdanm 0:9b334a45a8ff 551
bogdanm 0:9b334a45a8ff 552 /**
bogdanm 0:9b334a45a8ff 553 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
bogdanm 0:9b334a45a8ff 554 * AHB/APBx prescalers and Flash settings
bogdanm 0:9b334a45a8ff 555 * @note This function should be called only once the RCC clock configuration
bogdanm 0:9b334a45a8ff 556 * is reset to the default reset state (done in SystemInit() function).
bogdanm 0:9b334a45a8ff 557 * @param None
bogdanm 0:9b334a45a8ff 558 * @retval None
bogdanm 0:9b334a45a8ff 559 */
bogdanm 0:9b334a45a8ff 560 void SetSysClock(void)
bogdanm 0:9b334a45a8ff 561 {
bogdanm 0:9b334a45a8ff 562 /* 1- Try to start with HSE and external clock */
bogdanm 0:9b334a45a8ff 563 #if USE_PLL_HSE_EXTC != 0
bogdanm 0:9b334a45a8ff 564 if (SetSysClock_PLL_HSE(1) == 0)
bogdanm 0:9b334a45a8ff 565 #endif
bogdanm 0:9b334a45a8ff 566 {
bogdanm 0:9b334a45a8ff 567 /* 2- If fail try to start with HSE and external xtal */
bogdanm 0:9b334a45a8ff 568 #if USE_PLL_HSE_XTAL != 0
bogdanm 0:9b334a45a8ff 569 if (SetSysClock_PLL_HSE(0) == 0)
bogdanm 0:9b334a45a8ff 570 #endif
bogdanm 0:9b334a45a8ff 571 {
bogdanm 0:9b334a45a8ff 572 /* 3- If fail start with HSI clock */
bogdanm 0:9b334a45a8ff 573 if (SetSysClock_PLL_HSI() == 0)
bogdanm 0:9b334a45a8ff 574 {
bogdanm 0:9b334a45a8ff 575 while(1)
bogdanm 0:9b334a45a8ff 576 {
bogdanm 0:9b334a45a8ff 577 // [TODO] Put something here to tell the user that a problem occured...
bogdanm 0:9b334a45a8ff 578 }
bogdanm 0:9b334a45a8ff 579 }
bogdanm 0:9b334a45a8ff 580 }
bogdanm 0:9b334a45a8ff 581 }
bogdanm 0:9b334a45a8ff 582
bogdanm 0:9b334a45a8ff 583 // Output clock on MCO2 pin(PC9) for debugging purpose
bogdanm 0:9b334a45a8ff 584 // Can be visualized on uSD card CN3 connector pin 8
bogdanm 0:9b334a45a8ff 585 //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 216 MHz / 4 = 54 MHz
bogdanm 0:9b334a45a8ff 586 }
bogdanm 0:9b334a45a8ff 587
bogdanm 0:9b334a45a8ff 588 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
bogdanm 0:9b334a45a8ff 589 /******************************************************************************/
bogdanm 0:9b334a45a8ff 590 /* PLL (clocked by HSE) used as System clock source */
bogdanm 0:9b334a45a8ff 591 /******************************************************************************/
bogdanm 0:9b334a45a8ff 592 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
bogdanm 0:9b334a45a8ff 593 {
bogdanm 0:9b334a45a8ff 594 RCC_ClkInitTypeDef RCC_ClkInitStruct;
bogdanm 0:9b334a45a8ff 595 RCC_OscInitTypeDef RCC_OscInitStruct;
bogdanm 0:9b334a45a8ff 596
bogdanm 0:9b334a45a8ff 597 // Enable power clock
bogdanm 0:9b334a45a8ff 598 __PWR_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 599
bogdanm 0:9b334a45a8ff 600 // Enable HSE oscillator and activate PLL with HSE as source
bogdanm 0:9b334a45a8ff 601 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
bogdanm 0:9b334a45a8ff 602 if (bypass == 0)
bogdanm 0:9b334a45a8ff 603 {
bogdanm 0:9b334a45a8ff 604 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External xtal on OSC_IN/OSC_OUT */
bogdanm 0:9b334a45a8ff 605 }
bogdanm 0:9b334a45a8ff 606 else
bogdanm 0:9b334a45a8ff 607 {
bogdanm 0:9b334a45a8ff 608 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External clock on OSC_IN */
bogdanm 0:9b334a45a8ff 609 }
bogdanm 0:9b334a45a8ff 610 // Warning: this configuration is for a 25 MHz xtal clock only
bogdanm 0:9b334a45a8ff 611 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
bogdanm 0:9b334a45a8ff 612 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
bogdanm 0:9b334a45a8ff 613 RCC_OscInitStruct.PLL.PLLM = 25; // VCO input clock = 1 MHz (25 MHz / 25)
bogdanm 0:9b334a45a8ff 614 RCC_OscInitStruct.PLL.PLLN = 432; // VCO output clock = 432 MHz (1 MHz * 432)
bogdanm 0:9b334a45a8ff 615 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
bogdanm 0:9b334a45a8ff 616 RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
bogdanm 0:9b334a45a8ff 617
bogdanm 0:9b334a45a8ff 618 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
bogdanm 0:9b334a45a8ff 619 {
bogdanm 0:9b334a45a8ff 620 return 0; // FAIL
bogdanm 0:9b334a45a8ff 621 }
bogdanm 0:9b334a45a8ff 622
bogdanm 0:9b334a45a8ff 623 // Activate the OverDrive to reach the 216 MHz Frequency
bogdanm 0:9b334a45a8ff 624 if (HAL_PWREx_EnableOverDrive() != HAL_OK)
bogdanm 0:9b334a45a8ff 625 {
bogdanm 0:9b334a45a8ff 626 return 0; // FAIL
bogdanm 0:9b334a45a8ff 627 }
bogdanm 0:9b334a45a8ff 628
bogdanm 0:9b334a45a8ff 629 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
bogdanm 0:9b334a45a8ff 630 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
bogdanm 0:9b334a45a8ff 631 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
bogdanm 0:9b334a45a8ff 632 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 216 MHz
bogdanm 0:9b334a45a8ff 633 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 54 MHz
bogdanm 0:9b334a45a8ff 634 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 108 MHz
bogdanm 0:9b334a45a8ff 635
bogdanm 0:9b334a45a8ff 636 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
bogdanm 0:9b334a45a8ff 637 {
bogdanm 0:9b334a45a8ff 638 return 0; // FAIL
bogdanm 0:9b334a45a8ff 639 }
bogdanm 0:9b334a45a8ff 640
bogdanm 0:9b334a45a8ff 641 return 1; // OK
bogdanm 0:9b334a45a8ff 642 }
bogdanm 0:9b334a45a8ff 643 #endif
bogdanm 0:9b334a45a8ff 644
bogdanm 0:9b334a45a8ff 645 /******************************************************************************/
bogdanm 0:9b334a45a8ff 646 /* PLL (clocked by HSI) used as System clock source */
bogdanm 0:9b334a45a8ff 647 /******************************************************************************/
bogdanm 0:9b334a45a8ff 648 uint8_t SetSysClock_PLL_HSI(void)
bogdanm 0:9b334a45a8ff 649 {
bogdanm 0:9b334a45a8ff 650 RCC_ClkInitTypeDef RCC_ClkInitStruct;
bogdanm 0:9b334a45a8ff 651 RCC_OscInitTypeDef RCC_OscInitStruct;
bogdanm 0:9b334a45a8ff 652
bogdanm 0:9b334a45a8ff 653 // Enable CPU L1-Cache
bogdanm 0:9b334a45a8ff 654 SCB_EnableICache();
bogdanm 0:9b334a45a8ff 655 SCB_EnableDCache();
bogdanm 0:9b334a45a8ff 656
bogdanm 0:9b334a45a8ff 657 // Enable power clock
bogdanm 0:9b334a45a8ff 658 __PWR_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 659
bogdanm 0:9b334a45a8ff 660 // Enable HSI oscillator and activate PLL with HSI as source
bogdanm 0:9b334a45a8ff 661 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
bogdanm 0:9b334a45a8ff 662 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
bogdanm 0:9b334a45a8ff 663 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
bogdanm 0:9b334a45a8ff 664 RCC_OscInitStruct.HSICalibrationValue = 16;
bogdanm 0:9b334a45a8ff 665 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
bogdanm 0:9b334a45a8ff 666 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
bogdanm 0:9b334a45a8ff 667 RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
bogdanm 0:9b334a45a8ff 668 RCC_OscInitStruct.PLL.PLLN = 432; // VCO output clock = 432 MHz (1 MHz * 432)
bogdanm 0:9b334a45a8ff 669 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
bogdanm 0:9b334a45a8ff 670 RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
bogdanm 0:9b334a45a8ff 671
bogdanm 0:9b334a45a8ff 672 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
bogdanm 0:9b334a45a8ff 673 {
bogdanm 0:9b334a45a8ff 674 return 0; // FAIL
bogdanm 0:9b334a45a8ff 675 }
bogdanm 0:9b334a45a8ff 676
bogdanm 0:9b334a45a8ff 677 // Activate the OverDrive to reach the 216 MHz Frequency
bogdanm 0:9b334a45a8ff 678 if (HAL_PWREx_EnableOverDrive() != HAL_OK)
bogdanm 0:9b334a45a8ff 679 {
bogdanm 0:9b334a45a8ff 680 return 0; // FAIL
bogdanm 0:9b334a45a8ff 681 }
bogdanm 0:9b334a45a8ff 682
bogdanm 0:9b334a45a8ff 683 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
bogdanm 0:9b334a45a8ff 684 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
bogdanm 0:9b334a45a8ff 685 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
bogdanm 0:9b334a45a8ff 686 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 216 MHz
bogdanm 0:9b334a45a8ff 687 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 54 MHz
bogdanm 0:9b334a45a8ff 688 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 108 MHz
bogdanm 0:9b334a45a8ff 689
bogdanm 0:9b334a45a8ff 690 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
bogdanm 0:9b334a45a8ff 691 {
bogdanm 0:9b334a45a8ff 692 return 0; // FAIL
bogdanm 0:9b334a45a8ff 693 }
bogdanm 0:9b334a45a8ff 694
bogdanm 0:9b334a45a8ff 695 return 1; // OK
bogdanm 0:9b334a45a8ff 696 }
bogdanm 0:9b334a45a8ff 697
bogdanm 0:9b334a45a8ff 698 /**
bogdanm 0:9b334a45a8ff 699 * @}
bogdanm 0:9b334a45a8ff 700 */
bogdanm 0:9b334a45a8ff 701
bogdanm 0:9b334a45a8ff 702 /**
bogdanm 0:9b334a45a8ff 703 * @}
bogdanm 0:9b334a45a8ff 704 */
bogdanm 0:9b334a45a8ff 705
bogdanm 0:9b334a45a8ff 706 /**
bogdanm 0:9b334a45a8ff 707 * @}
bogdanm 0:9b334a45a8ff 708 */
bogdanm 0:9b334a45a8ff 709 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/